1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 /* The ASM_DOT macro allows easy string pasting to handle the differences
48 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
49 support the %. option. */
52 # define ASM_DOTW ".w"
53 # define ASM_DOTL ".l"
61 /* Structure describing stack frame layout. */
64 /* Stack pointer to frame pointer offset. */
67 /* Offset of FPU registers. */
68 HOST_WIDE_INT foffset
;
70 /* Frame size in bytes (rounded up). */
73 /* Data and address register. */
75 unsigned int reg_mask
;
76 unsigned int reg_rev_mask
;
80 unsigned int fpu_mask
;
81 unsigned int fpu_rev_mask
;
83 /* Offsets relative to ARG_POINTER. */
84 HOST_WIDE_INT frame_pointer_offset
;
85 HOST_WIDE_INT stack_pointer_offset
;
87 /* Function which the above information refers to. */
91 /* Current frame information calculated by m68k_compute_frame_layout(). */
92 static struct m68k_frame current_frame
;
94 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
95 if SGS_SWITCH_TABLE. */
96 int switch_table_difference_label_flag
;
98 static rtx
find_addr_reg (rtx
);
99 static const char *singlemove_string (rtx
*);
100 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
101 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
102 #ifdef M68K_TARGET_COFF
103 static void m68k_coff_asm_named_section (const char *, unsigned int);
104 #endif /* M68K_TARGET_COFF */
106 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
107 static void m68k_hp320_file_start (void);
109 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
110 HOST_WIDE_INT
, tree
);
111 static rtx
m68k_struct_value_rtx (tree
, int);
112 static bool m68k_interrupt_function_p (tree func
);
113 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
114 tree args
, int flags
,
116 static void m68k_compute_frame_layout (void);
117 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
118 static int const_int_cost (rtx
);
119 static bool m68k_rtx_costs (rtx
, int, int, int *);
122 /* Alignment to use for loops and jumps */
123 /* Specify power of two alignment used for loops. */
124 const char *m68k_align_loops_string
;
125 /* Specify power of two alignment used for non-loop jumps. */
126 const char *m68k_align_jumps_string
;
127 /* Specify power of two alignment used for functions. */
128 const char *m68k_align_funcs_string
;
129 /* Specify the identification number of the library being built */
130 const char *m68k_library_id_string
;
132 /* Specify power of two alignment used for loops. */
133 int m68k_align_loops
;
134 /* Specify power of two alignment used for non-loop jumps. */
135 int m68k_align_jumps
;
136 /* Specify power of two alignment used for functions. */
137 int m68k_align_funcs
;
139 /* Nonzero if the last compare/test insn had FP operands. The
140 sCC expanders peek at this to determine what to do for the
141 68060, which has no fsCC instructions. */
142 int m68k_last_compare_had_fp_operands
;
144 /* Initialize the GCC target structure. */
146 #if INT_OP_GROUP == INT_OP_DOT_WORD
147 #undef TARGET_ASM_ALIGNED_HI_OP
148 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
151 #if INT_OP_GROUP == INT_OP_NO_DOT
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tbyte\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
160 #if INT_OP_GROUP == INT_OP_DC
161 #undef TARGET_ASM_BYTE_OP
162 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
169 #undef TARGET_ASM_UNALIGNED_HI_OP
170 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
171 #undef TARGET_ASM_UNALIGNED_SI_OP
172 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
174 #undef TARGET_ASM_FUNCTION_PROLOGUE
175 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
176 #undef TARGET_ASM_FUNCTION_EPILOGUE
177 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
179 #undef TARGET_ASM_INTERNAL_LABEL
180 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
183 #undef TARGET_ASM_OUTPUT_MI_THUNK
184 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
185 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
186 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
188 #undef TARGET_ASM_FILE_START_APP_OFF
189 #define TARGET_ASM_FILE_START_APP_OFF true
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS m68k_rtx_costs
194 #undef TARGET_ATTRIBUTE_TABLE
195 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
197 #undef TARGET_PROMOTE_PROTOTYPES
198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
200 #undef TARGET_STRUCT_VALUE_RTX
201 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
203 static const struct attribute_spec m68k_attribute_table
[] =
205 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
206 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
207 { NULL
, 0, 0, false, false, false, NULL
}
210 struct gcc_target targetm
= TARGET_INITIALIZER
;
212 /* Sometimes certain combinations of command options do not make
213 sense on a particular target machine. You can define a macro
214 `OVERRIDE_OPTIONS' to take account of this. This macro, if
215 defined, is executed once just after all the command options have
218 Don't use this macro to turn on various extra optimizations for
219 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
222 override_options (void)
229 /* Validate -malign-loops= value, or provide default */
230 m68k_align_loops
= def_align
;
231 if (m68k_align_loops_string
)
233 i
= atoi (m68k_align_loops_string
);
234 if (i
< 1 || i
> MAX_CODE_ALIGN
)
235 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
237 m68k_align_loops
= i
;
240 /* Library identification */
241 if (m68k_library_id_string
)
245 if (! TARGET_ID_SHARED_LIBRARY
)
246 error ("-mshared-library-id= specified without -mid-shared-library");
247 id
= atoi (m68k_library_id_string
);
248 if (id
< 0 || id
> MAX_LIBRARY_ID
)
249 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
251 /* From now on, m68k_library_id_string will contain the library offset. */
252 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
255 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
257 m68k_library_id_string
= "_current_shared_library_a5_offset_";
259 /* Sanity check to ensure that msep-data and mid-sahred-library are not
260 * both specified together. Doing so simply doesn't make sense.
262 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
263 error ("cannot specify both -msep-data and -mid-shared-library");
265 /* If we're generating code for a separate A5 relative data segment,
266 * we've got to enable -fPIC as well. This might be relaxable to
267 * -fpic but it hasn't been tested properly.
269 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
272 /* Validate -malign-jumps= value, or provide default */
273 m68k_align_jumps
= def_align
;
274 if (m68k_align_jumps_string
)
276 i
= atoi (m68k_align_jumps_string
);
277 if (i
< 1 || i
> MAX_CODE_ALIGN
)
278 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
280 m68k_align_jumps
= i
;
283 /* Validate -malign-functions= value, or provide default */
284 m68k_align_funcs
= def_align
;
285 if (m68k_align_funcs_string
)
287 i
= atoi (m68k_align_funcs_string
);
288 if (i
< 1 || i
> MAX_CODE_ALIGN
)
289 error ("-malign-functions=%d is not between 1 and %d",
292 m68k_align_funcs
= i
;
295 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
297 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
298 error("-fPIC is not currently supported on the 68000 or 68010\n");
300 /* ??? A historic way of turning on pic, or is this intended to
301 be an embedded thing that doesn't have the same name binding
302 significance that it does on hosted ELF systems? */
303 if (TARGET_PCREL
&& flag_pic
== 0)
306 /* Turn off function cse if we are doing PIC. We always want function call
307 to be done as `bsr foo@PLTPC', so it will force the assembler to create
308 the PLT entry for `foo'. Doing function cse will cause the address of
309 `foo' to be loaded into a register, which is exactly what we want to
310 avoid when we are doing PIC on svr4 m68k. */
312 flag_no_function_cse
= 1;
314 SUBTARGET_OVERRIDE_OPTIONS
;
317 /* Return nonzero if FUNC is an interrupt function as specified by the
318 "interrupt_handler" attribute. */
320 m68k_interrupt_function_p(tree func
)
324 if (TREE_CODE (func
) != FUNCTION_DECL
)
327 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
328 return (a
!= NULL_TREE
);
331 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
332 struct attribute_spec.handler. */
334 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
335 tree args ATTRIBUTE_UNUSED
,
336 int flags ATTRIBUTE_UNUSED
,
339 if (TREE_CODE (*node
) != FUNCTION_DECL
)
341 warning ("`%s' attribute only applies to functions",
342 IDENTIFIER_POINTER (name
));
343 *no_add_attrs
= true;
350 m68k_compute_frame_layout (void)
353 unsigned int mask
, rmask
;
354 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
356 /* Only compute the frame once per function.
357 Don't cache information until reload has been completed. */
358 if (current_frame
.funcdef_no
== current_function_funcdef_no
362 current_frame
.size
= (get_frame_size () + 3) & -4;
364 mask
= rmask
= saved
= 0;
365 for (regno
= 0; regno
< 16; regno
++)
366 if (m68k_save_reg (regno
, interrupt_handler
))
369 rmask
|= 1 << (15 - regno
);
372 current_frame
.offset
= saved
* 4;
373 current_frame
.reg_no
= saved
;
374 current_frame
.reg_mask
= mask
;
375 current_frame
.reg_rev_mask
= rmask
;
377 current_frame
.foffset
= 0;
378 mask
= rmask
= saved
= 0;
379 if (TARGET_68881
/* || TARGET_CFV4E */)
381 for (regno
= 16; regno
< 24; regno
++)
382 if (m68k_save_reg (regno
, interrupt_handler
))
384 mask
|= 1 << (regno
- 16);
385 rmask
|= 1 << (23 - regno
);
388 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
389 current_frame
.offset
+= current_frame
.foffset
;
391 current_frame
.fpu_no
= saved
;
392 current_frame
.fpu_mask
= mask
;
393 current_frame
.fpu_rev_mask
= rmask
;
395 /* Remember what function this frame refers to. */
396 current_frame
.funcdef_no
= current_function_funcdef_no
;
400 m68k_initial_elimination_offset (int from
, int to
)
402 /* FIXME: The correct offset to compute here would appear to be
403 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
404 but for some obscure reason, this must be 0 to get correct code. */
405 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
408 m68k_compute_frame_layout ();
410 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
411 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
412 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
413 return current_frame
.offset
+ current_frame
.size
;
418 /* Refer to the array `regs_ever_live' to determine which registers
419 to save; `regs_ever_live[I]' is nonzero if register number I
420 is ever used in the function. This function is responsible for
421 knowing which registers should not be saved even if used.
422 Return true if we need to save REGNO. */
425 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
427 if (flag_pic
&& current_function_uses_pic_offset_table
428 && regno
== PIC_OFFSET_TABLE_REGNUM
)
431 if (current_function_calls_eh_return
)
436 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
437 if (test
== INVALID_REGNUM
)
444 /* Fixed regs we never touch. */
445 if (fixed_regs
[regno
])
448 /* The frame pointer (if it is such) is handled specially. */
449 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
452 /* Interrupt handlers must also save call_used_regs
453 if they are live or when calling nested functions. */
454 if (interrupt_handler
)
456 if (regs_ever_live
[regno
])
459 if (!current_function_is_leaf
&& call_used_regs
[regno
])
463 /* Never need to save registers that aren't touched. */
464 if (!regs_ever_live
[regno
])
467 /* Otherwise save everything that isn't call-clobbered. */
468 return !call_used_regs
[regno
];
471 /* This function generates the assembly code for function entry.
472 STREAM is a stdio stream to output the code to.
473 SIZE is an int: how many units of temporary storage to allocate. */
476 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
478 HOST_WIDE_INT fsize_with_regs
;
479 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
481 m68k_compute_frame_layout();
483 /* If the stack limit is a symbol, we can check it here,
484 before actually allocating the space. */
485 if (current_function_limit_stack
486 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
487 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
488 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
490 /* On ColdFire add register save into initial stack frame setup, if possible. */
491 fsize_with_regs
= current_frame
.size
;
492 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
493 fsize_with_regs
+= current_frame
.reg_no
* 4;
495 if (frame_pointer_needed
)
497 if (current_frame
.size
== 0 && TARGET_68040
)
498 /* on the 68040, pea + move is faster than link.w 0 */
499 fprintf (stream
, MOTOROLA
?
500 "\tpea (%s)\n\tmove.l %s,%s\n" :
501 "\tpea %s@\n\tmovel %s,%s\n",
502 M68K_REGNAME(FRAME_POINTER_REGNUM
),
503 M68K_REGNAME(STACK_POINTER_REGNUM
),
504 M68K_REGNAME(FRAME_POINTER_REGNUM
));
505 else if (fsize_with_regs
< 0x8000)
506 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
507 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
508 else if (TARGET_68020
)
509 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
510 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
512 /* Adding negative number is faster on the 68040. */
513 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
514 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
515 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
517 if (dwarf2out_do_frame ())
520 l
= (char *) dwarf2out_cfi_label ();
522 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
523 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
524 cfa_offset
+= current_frame
.size
;
527 else if (fsize_with_regs
) /* !frame_pointer_needed */
529 if (fsize_with_regs
< 0x8000)
531 if (fsize_with_regs
<= 8)
533 if (!TARGET_COLDFIRE
)
534 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
537 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
540 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
541 /* On the CPU32 it is faster to use two subqw instructions to
542 subtract a small integer (8 < N <= 16) to a register. */
544 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
545 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
546 fsize_with_regs
- 8);
547 else if (TARGET_68040
)
548 /* Adding negative number is faster on the 68040. */
549 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
552 asm_fprintf (stream
, MOTOROLA
?
553 "\tlea (%wd,%Rsp),%Rsp\n" :
554 "\tlea %Rsp@(%wd),%Rsp\n",
557 else /* fsize_with_regs >= 0x8000 */
558 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
560 if (dwarf2out_do_frame ())
562 cfa_offset
+= current_frame
.size
+ 4;
563 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
565 } /* !frame_pointer_needed */
567 if (current_frame
.fpu_mask
)
569 asm_fprintf (stream
, MOTOROLA
?
570 "\tfmovm %I0x%x,-(%Rsp)\n" :
571 "\tfmovem %I0x%x,%Rsp@-\n",
572 current_frame
.fpu_mask
);
574 if (dwarf2out_do_frame ())
576 char *l
= (char *) dwarf2out_cfi_label ();
579 cfa_offset
+= current_frame
.fpu_no
* 12;
580 if (! frame_pointer_needed
)
581 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
582 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
583 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
584 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
588 /* If the stack limit is not a symbol, check it here.
589 This has the disadvantage that it may be too late... */
590 if (current_function_limit_stack
)
592 if (REG_P (stack_limit_rtx
))
593 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
594 M68K_REGNAME(REGNO (stack_limit_rtx
)));
595 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
596 warning ("stack limit expression is not supported");
599 if (current_frame
.reg_no
<= 2)
601 /* Store each separately in the same order moveml uses.
602 Using two movel instructions instead of a single moveml
603 is about 15% faster for the 68020 and 68030 at no expense
608 for (i
= 0; i
< 16; i
++)
609 if (current_frame
.reg_rev_mask
& (1 << i
))
611 asm_fprintf (stream
, MOTOROLA
?
612 "\t%Omove.l %s,-(%Rsp)\n" :
613 "\tmovel %s,%Rsp@-\n",
614 M68K_REGNAME(15 - i
));
615 if (dwarf2out_do_frame ())
617 char *l
= (char *) dwarf2out_cfi_label ();
620 if (! frame_pointer_needed
)
621 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
622 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
626 else if (current_frame
.reg_rev_mask
)
629 /* The ColdFire does not support the predecrement form of the
630 MOVEM instruction, so we must adjust the stack pointer and
631 then use the plain address register indirect mode.
632 The required register save space was combined earlier with
633 the fsize_with_regs amount. */
635 asm_fprintf (stream
, MOTOROLA
?
636 "\tmovm.l %I0x%x,(%Rsp)\n" :
637 "\tmoveml %I0x%x,%Rsp@\n",
638 current_frame
.reg_mask
);
640 asm_fprintf (stream
, MOTOROLA
?
641 "\tmovm.l %I0x%x,-(%Rsp)\n" :
642 "\tmoveml %I0x%x,%Rsp@-\n",
643 current_frame
.reg_rev_mask
);
644 if (dwarf2out_do_frame ())
646 char *l
= (char *) dwarf2out_cfi_label ();
649 cfa_offset
+= current_frame
.reg_no
* 4;
650 if (! frame_pointer_needed
)
651 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
652 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
653 if (current_frame
.reg_mask
& (1 << regno
))
654 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
657 if (!TARGET_SEP_DATA
&& flag_pic
&&
658 (current_function_uses_pic_offset_table
||
659 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
661 if (TARGET_ID_SHARED_LIBRARY
)
663 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
664 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
665 m68k_library_id_string
,
666 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
671 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
672 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
675 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
676 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
677 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
678 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
679 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
685 /* Return true if this function's epilogue can be output as RTL. */
688 use_return_insn (void)
690 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
693 /* We can output the epilogue as RTL only if no registers need to be
695 m68k_compute_frame_layout();
696 return current_frame
.reg_no
? false : true;
699 /* This function generates the assembly code for function exit,
700 on machines that need it.
702 The function epilogue should not depend on the current stack pointer!
703 It should use the frame pointer only, if there is a frame pointer.
704 This is mandatory because of alloca; we also take advantage of it to
705 omit stack adjustments before returning. */
708 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
710 HOST_WIDE_INT fsize
, fsize_with_regs
;
712 bool restore_from_sp
= false;
713 rtx insn
= get_last_insn ();
715 m68k_compute_frame_layout();
717 /* If the last insn was a BARRIER, we don't have to write any code. */
718 if (GET_CODE (insn
) == NOTE
)
719 insn
= prev_nonnote_insn (insn
);
720 if (insn
&& GET_CODE (insn
) == BARRIER
)
722 /* Output just a no-op so that debuggers don't get confused
723 about which function the pc is in at this address. */
724 fprintf (stream
, "\tnop\n");
728 #ifdef FUNCTION_EXTRA_EPILOGUE
729 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
732 fsize
= current_frame
.size
;
734 /* FIXME : leaf_function_p below is too strong.
735 What we really need to know there is if there could be pending
736 stack adjustment needed at that point. */
737 restore_from_sp
= ! frame_pointer_needed
738 || (! current_function_calls_alloca
&& leaf_function_p ());
740 /* fsize_with_regs is the size we need to adjust the sp when
741 popping the frame. */
742 fsize_with_regs
= fsize
;
744 /* Because the ColdFire doesn't support moveml with
745 complex address modes, we must adjust the stack manually
746 after restoring registers. When the frame pointer isn't used,
747 we can merge movem adjustment into frame unlinking
748 made immediately after it. */
749 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
750 fsize_with_regs
+= current_frame
.reg_no
* 4;
752 if (current_frame
.offset
+ fsize
>= 0x8000
754 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
756 /* Because the ColdFire doesn't support moveml with
757 complex address modes we make an extra correction here. */
759 fsize
+= current_frame
.offset
;
761 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
762 fsize
= 0, big
= true;
764 if (current_frame
.reg_no
<= 2)
766 /* Restore each separately in the same order moveml does.
767 Using two movel instructions instead of a single moveml
768 is about 15% faster for the 68020 and 68030 at no expense
772 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
774 for (i
= 0; i
< 16; i
++)
775 if (current_frame
.reg_mask
& (1 << i
))
780 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
782 M68K_REGNAME(FRAME_POINTER_REGNUM
),
785 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
786 M68K_REGNAME(FRAME_POINTER_REGNUM
),
790 else if (restore_from_sp
)
791 asm_fprintf (stream
, MOTOROLA
?
792 "\t%Omove.l (%Rsp)+,%s\n" :
793 "\tmovel %Rsp@+,%s\n",
798 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
800 M68K_REGNAME(FRAME_POINTER_REGNUM
),
803 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
804 M68K_REGNAME(FRAME_POINTER_REGNUM
),
811 else if (current_frame
.reg_mask
)
813 /* The ColdFire requires special handling due to its limited moveml insn. */
818 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
819 M68K_REGNAME(FRAME_POINTER_REGNUM
));
820 asm_fprintf (stream
, MOTOROLA
?
821 "\tmovm.l (%Ra1),%I0x%x\n" :
822 "\tmoveml %Ra1@,%I0x%x\n",
823 current_frame
.reg_mask
);
825 else if (restore_from_sp
)
826 asm_fprintf (stream
, MOTOROLA
?
827 "\tmovm.l (%Rsp),%I0x%x\n" :
828 "\tmoveml %Rsp@,%I0x%x\n",
829 current_frame
.reg_mask
);
833 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
834 current_frame
.offset
+ fsize
,
835 M68K_REGNAME(FRAME_POINTER_REGNUM
),
836 current_frame
.reg_mask
);
838 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.offset
+ fsize
,
841 current_frame
.reg_mask
);
844 else /* !TARGET_COLDFIRE */
849 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
850 current_frame
.offset
+ fsize
,
851 M68K_REGNAME(FRAME_POINTER_REGNUM
),
852 current_frame
.reg_mask
);
854 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
855 M68K_REGNAME(FRAME_POINTER_REGNUM
),
856 current_frame
.offset
+ fsize
,
857 current_frame
.reg_mask
);
859 else if (restore_from_sp
)
861 asm_fprintf (stream
, MOTOROLA
?
862 "\tmovm.l (%Rsp)+,%I0x%x\n" :
863 "\tmoveml %Rsp@+,%I0x%x\n",
864 current_frame
.reg_mask
);
869 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
870 current_frame
.offset
+ fsize
,
871 M68K_REGNAME(FRAME_POINTER_REGNUM
),
872 current_frame
.reg_mask
);
874 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
875 M68K_REGNAME(FRAME_POINTER_REGNUM
),
876 current_frame
.offset
+ fsize
,
877 current_frame
.reg_mask
);
881 if (current_frame
.fpu_rev_mask
)
886 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
887 current_frame
.foffset
+ fsize
,
888 M68K_REGNAME(FRAME_POINTER_REGNUM
),
889 current_frame
.fpu_rev_mask
);
891 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
892 M68K_REGNAME(FRAME_POINTER_REGNUM
),
893 current_frame
.foffset
+ fsize
,
894 current_frame
.fpu_rev_mask
);
896 else if (restore_from_sp
)
899 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
900 current_frame
.fpu_rev_mask
);
902 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
903 current_frame
.fpu_rev_mask
);
908 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
909 current_frame
.foffset
+ fsize
,
910 M68K_REGNAME(FRAME_POINTER_REGNUM
),
911 current_frame
.fpu_rev_mask
);
913 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
914 M68K_REGNAME(FRAME_POINTER_REGNUM
),
915 current_frame
.foffset
+ fsize
,
916 current_frame
.fpu_rev_mask
);
919 if (frame_pointer_needed
)
920 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
921 else if (fsize_with_regs
)
923 if (fsize_with_regs
<= 8)
925 if (!TARGET_COLDFIRE
)
926 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
929 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
932 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
934 /* On the CPU32 it is faster to use two addqw instructions to
935 add a small integer (8 < N <= 16) to a register. */
936 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
937 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
938 fsize_with_regs
- 8);
940 else if (fsize_with_regs
< 0x8000)
943 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
946 asm_fprintf (stream
, MOTOROLA
?
947 "\tlea (%wd,%Rsp),%Rsp\n" :
948 "\tlea %Rsp@(%wd),%Rsp\n",
952 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
954 if (current_function_calls_eh_return
)
955 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
956 if (m68k_interrupt_function_p (current_function_decl
))
957 fprintf (stream
, "\trte\n");
958 else if (current_function_pops_args
)
959 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
961 fprintf (stream
, "\trts\n");
964 /* Similar to general_operand, but exclude stack_pointer_rtx. */
967 not_sp_operand (rtx op
, enum machine_mode mode
)
969 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
972 /* Return true if X is a valid comparison operator for the dbcc
975 Note it rejects floating point comparison operators.
976 (In the future we could use Fdbcc).
978 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
981 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
983 switch (GET_CODE (x
))
985 case EQ
: case NE
: case GTU
: case LTU
:
989 /* Reject some when CC_NO_OVERFLOW is set. This may be over
991 case GT
: case LT
: case GE
: case LE
:
992 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
998 /* Return nonzero if flags are currently in the 68881 flag register. */
1000 flags_in_68881 (void)
1002 /* We could add support for these in the future */
1003 return cc_status
.flags
& CC_IN_68881
;
1006 /* Output a BSR instruction suitable for PIC code. */
1008 m68k_output_pic_call(rtx dest
)
1012 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1014 /* We output a BSR instruction if we're using -fpic or we're building for
1015 * a target that supports long branches. If we're building -fPIC on the
1016 * 68000, 68010 or ColdFire we generate one of two sequences:
1017 * a shorter one that uses a GOT entry or a longer one that doesn't.
1018 * We'll use the -Os command-line flag to decide which to generate.
1019 * Both sequences take the same time to execute on the ColdFire.
1021 else if (TARGET_PCREL
)
1023 else if ((flag_pic
== 1) || TARGET_68020
)
1026 #elif defined(USE_GAS)
1027 out
= "bsr.l %0@PLTPC";
1029 out
= "bsr %0@PLTPC";
1031 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1032 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1034 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1036 output_asm_insn(out
, &dest
);
1039 /* Output a dbCC; jCC sequence. Note we do not handle the
1040 floating point version of this sequence (Fdbcc). We also
1041 do not handle alternative conditions when CC_NO_OVERFLOW is
1042 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1043 kick those out before we get here. */
1046 output_dbcc_and_branch (rtx
*operands
)
1048 switch (GET_CODE (operands
[3]))
1051 output_asm_insn (MOTOROLA
?
1052 "dbeq %0,%l1\n\tjbeq %l2" :
1053 "dbeq %0,%l1\n\tjeq %l2",
1058 output_asm_insn (MOTOROLA
?
1059 "dbne %0,%l1\n\tjbne %l2" :
1060 "dbne %0,%l1\n\tjne %l2",
1065 output_asm_insn (MOTOROLA
?
1066 "dbgt %0,%l1\n\tjbgt %l2" :
1067 "dbgt %0,%l1\n\tjgt %l2",
1072 output_asm_insn (MOTOROLA
?
1073 "dbhi %0,%l1\n\tjbhi %l2" :
1074 "dbhi %0,%l1\n\tjhi %l2",
1079 output_asm_insn (MOTOROLA
?
1080 "dblt %0,%l1\n\tjblt %l2" :
1081 "dblt %0,%l1\n\tjlt %l2",
1086 output_asm_insn (MOTOROLA
?
1087 "dbcs %0,%l1\n\tjbcs %l2" :
1088 "dbcs %0,%l1\n\tjcs %l2",
1093 output_asm_insn (MOTOROLA
?
1094 "dbge %0,%l1\n\tjbge %l2" :
1095 "dbge %0,%l1\n\tjge %l2",
1100 output_asm_insn (MOTOROLA
?
1101 "dbcc %0,%l1\n\tjbcc %l2" :
1102 "dbcc %0,%l1\n\tjcc %l2",
1107 output_asm_insn (MOTOROLA
?
1108 "dble %0,%l1\n\tjble %l2" :
1109 "dble %0,%l1\n\tjle %l2",
1114 output_asm_insn (MOTOROLA
?
1115 "dbls %0,%l1\n\tjbls %l2" :
1116 "dbls %0,%l1\n\tjls %l2",
1124 /* If the decrement is to be done in SImode, then we have
1125 to compensate for the fact that dbcc decrements in HImode. */
1126 switch (GET_MODE (operands
[0]))
1129 output_asm_insn (MOTOROLA
?
1130 "clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1" :
1131 "clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1",
1144 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1147 enum rtx_code op_code
= GET_CODE (op
);
1149 /* This does not produce a useful cc. */
1152 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1153 below. Swap the operands and change the op if these requirements
1154 are not fulfilled. */
1155 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1159 operand1
= operand2
;
1161 op_code
= swap_condition (op_code
);
1163 loperands
[0] = operand1
;
1164 if (GET_CODE (operand1
) == REG
)
1165 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1167 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1168 if (operand2
!= const0_rtx
)
1170 loperands
[2] = operand2
;
1171 if (GET_CODE (operand2
) == REG
)
1172 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1174 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1176 loperands
[4] = gen_label_rtx();
1177 if (operand2
!= const0_rtx
)
1180 #ifdef SGS_CMP_ORDER
1181 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1183 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1186 #ifdef SGS_CMP_ORDER
1187 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1189 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1194 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1195 output_asm_insn ("tst%.l %0", loperands
);
1198 #ifdef SGS_CMP_ORDER
1199 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1201 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1205 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1207 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1208 output_asm_insn ("tst%.l %1", loperands
);
1211 #ifdef SGS_CMP_ORDER
1212 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1214 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1219 loperands
[5] = dest
;
1224 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1225 CODE_LABEL_NUMBER (loperands
[4]));
1226 output_asm_insn ("seq %5", loperands
);
1230 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1231 CODE_LABEL_NUMBER (loperands
[4]));
1232 output_asm_insn ("sne %5", loperands
);
1236 loperands
[6] = gen_label_rtx();
1237 output_asm_insn (MOTOROLA
?
1238 "shi %5\n\tjbra %l6" :
1239 "shi %5\n\tjra %l6",
1241 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1242 CODE_LABEL_NUMBER (loperands
[4]));
1243 output_asm_insn ("sgt %5", loperands
);
1244 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1245 CODE_LABEL_NUMBER (loperands
[6]));
1249 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1250 CODE_LABEL_NUMBER (loperands
[4]));
1251 output_asm_insn ("shi %5", loperands
);
1255 loperands
[6] = gen_label_rtx();
1256 output_asm_insn (MOTOROLA
?
1257 "scs %5\n\tjbra %l6" :
1258 "scs %5\n\tjra %l6",
1260 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1261 CODE_LABEL_NUMBER (loperands
[4]));
1262 output_asm_insn ("slt %5", loperands
);
1263 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1264 CODE_LABEL_NUMBER (loperands
[6]));
1268 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1269 CODE_LABEL_NUMBER (loperands
[4]));
1270 output_asm_insn ("scs %5", loperands
);
1274 loperands
[6] = gen_label_rtx();
1275 output_asm_insn (MOTOROLA
?
1276 "scc %5\n\tjbra %l6" :
1277 "scc %5\n\tjra %l6",
1279 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1280 CODE_LABEL_NUMBER (loperands
[4]));
1281 output_asm_insn ("sge %5", loperands
);
1282 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1283 CODE_LABEL_NUMBER (loperands
[6]));
1287 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1288 CODE_LABEL_NUMBER (loperands
[4]));
1289 output_asm_insn ("scc %5", loperands
);
1293 loperands
[6] = gen_label_rtx();
1294 output_asm_insn (MOTOROLA
?
1295 "sls %5\n\tjbra %l6" :
1296 "sls %5\n\tjra %l6",
1298 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1299 CODE_LABEL_NUMBER (loperands
[4]));
1300 output_asm_insn ("sle %5", loperands
);
1301 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1302 CODE_LABEL_NUMBER (loperands
[6]));
1306 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1307 CODE_LABEL_NUMBER (loperands
[4]));
1308 output_asm_insn ("sls %5", loperands
);
1318 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1320 operands
[0] = countop
;
1321 operands
[1] = dataop
;
1323 if (GET_CODE (countop
) == CONST_INT
)
1325 register int count
= INTVAL (countop
);
1326 /* If COUNT is bigger than size of storage unit in use,
1327 advance to the containing unit of same size. */
1328 if (count
> signpos
)
1330 int offset
= (count
& ~signpos
) / 8;
1331 count
= count
& signpos
;
1332 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1334 if (count
== signpos
)
1335 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1337 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1339 /* These three statements used to use next_insns_test_no...
1340 but it appears that this should do the same job. */
1342 && next_insn_tests_no_inequality (insn
))
1345 && next_insn_tests_no_inequality (insn
))
1348 && next_insn_tests_no_inequality (insn
))
1351 cc_status
.flags
= CC_NOT_NEGATIVE
;
1353 return "btst %0,%1";
1356 /* Returns true if OP is either a symbol reference or a sum of a symbol
1357 reference and a constant. */
1360 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1362 switch (GET_CODE (op
))
1370 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1371 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1372 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1374 #if 0 /* Deleted, with corresponding change in m68k.h,
1375 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1377 return GET_MODE (op
) == mode
;
1385 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1388 extend_operator(rtx x
, enum machine_mode mode
)
1390 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1392 switch (GET_CODE(x
))
1403 /* Legitimize PIC addresses. If the address is already
1404 position-independent, we return ORIG. Newly generated
1405 position-independent addresses go to REG. If we need more
1406 than one register, we lose.
1408 An address is legitimized by making an indirect reference
1409 through the Global Offset Table with the name of the symbol
1412 The assembler and linker are responsible for placing the
1413 address of the symbol in the GOT. The function prologue
1414 is responsible for initializing a5 to the starting address
1417 The assembler is also responsible for translating a symbol name
1418 into a constant displacement from the start of the GOT.
1420 A quick example may make things a little clearer:
1422 When not generating PIC code to store the value 12345 into _foo
1423 we would generate the following code:
1427 When generating PIC two transformations are made. First, the compiler
1428 loads the address of foo into a register. So the first transformation makes:
1433 The code in movsi will intercept the lea instruction and call this
1434 routine which will transform the instructions into:
1436 movel a5@(_foo:w), a0
1440 That (in a nutshell) is how *all* symbol and label references are
1444 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1449 /* First handle a simple SYMBOL_REF or LABEL_REF */
1450 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1455 pic_ref
= gen_rtx_MEM (Pmode
,
1456 gen_rtx_PLUS (Pmode
,
1457 pic_offset_table_rtx
, orig
));
1458 current_function_uses_pic_offset_table
= 1;
1459 RTX_UNCHANGING_P (pic_ref
) = 1;
1460 emit_move_insn (reg
, pic_ref
);
1463 else if (GET_CODE (orig
) == CONST
)
1467 /* Make sure this has not already been legitimized. */
1468 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1469 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1475 /* legitimize both operands of the PLUS */
1476 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1478 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1479 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1480 base
== reg
? 0 : reg
);
1484 if (GET_CODE (orig
) == CONST_INT
)
1485 return plus_constant (base
, INTVAL (orig
));
1486 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1487 /* Likewise, should we set special REG_NOTEs here? */
1493 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1495 static CONST_METHOD
const_method (rtx
);
1497 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1500 const_method (rtx constant
)
1505 i
= INTVAL (constant
);
1509 /* The ColdFire doesn't have byte or word operations. */
1510 /* FIXME: This may not be useful for the m68060 either. */
1511 if (!TARGET_COLDFIRE
)
1513 /* if -256 < N < 256 but N is not in range for a moveq
1514 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1515 if (USE_MOVQ (i
^ 0xff))
1517 /* Likewise, try with not.w */
1518 if (USE_MOVQ (i
^ 0xffff))
1520 /* This is the only value where neg.w is useful */
1523 /* Try also with swap */
1525 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1528 /* Otherwise, use move.l */
1533 const_int_cost (rtx constant
)
1535 switch (const_method (constant
))
1538 /* Constants between -128 and 127 are cheap due to moveq */
1544 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1554 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1559 /* Constant zero is super cheap due to clr instruction. */
1560 if (x
== const0_rtx
)
1563 *total
= const_int_cost (x
);
1573 /* Make 0.0 cheaper than other floating constants to
1574 encourage creating tstsf and tstdf insns. */
1575 if (outer_code
== COMPARE
1576 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1582 /* These are vaguely right for a 68020. */
1583 /* The costs for long multiply have been adjusted to work properly
1584 in synth_mult on the 68020, relative to an average of the time
1585 for add and the time for shift, taking away a little more because
1586 sometimes move insns are needed. */
1587 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1588 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1589 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1590 TARGET_CFV3 ? 2 : 5)
1591 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1594 /* An lea costs about three times as much as a simple add. */
1595 if (GET_MODE (x
) == SImode
1596 && GET_CODE (XEXP (x
, 1)) == REG
1597 && GET_CODE (XEXP (x
, 0)) == MULT
1598 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1599 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1600 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1601 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1602 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1604 /* lea an@(dx:l:i),am */
1605 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1615 *total
= COSTS_N_INSNS(1);
1618 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1620 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1622 if (INTVAL (XEXP (x
, 1)) < 16)
1623 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1625 /* We're using clrw + swap for these cases. */
1626 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1629 *total
= COSTS_N_INSNS (10); /* worst case */
1632 /* A shift by a big integer takes an extra instruction. */
1633 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1634 && (INTVAL (XEXP (x
, 1)) == 16))
1636 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1639 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1640 && !(INTVAL (XEXP (x
, 1)) > 0
1641 && INTVAL (XEXP (x
, 1)) <= 8))
1643 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1649 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1650 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1651 && GET_MODE (x
) == SImode
)
1652 *total
= COSTS_N_INSNS (MULW_COST
);
1653 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1654 *total
= COSTS_N_INSNS (MULW_COST
);
1656 *total
= COSTS_N_INSNS (MULL_COST
);
1663 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1664 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1665 else if (TARGET_CF_HWDIV
)
1666 *total
= COSTS_N_INSNS (18);
1668 *total
= COSTS_N_INSNS (43); /* div.l */
1677 output_move_const_into_data_reg (rtx
*operands
)
1681 i
= INTVAL (operands
[1]);
1682 switch (const_method (operands
[1]))
1685 return "moveq %1,%0";
1688 operands
[1] = GEN_INT (i
^ 0xff);
1689 return "moveq %1,%0\n\tnot%.b %0";
1692 operands
[1] = GEN_INT (i
^ 0xffff);
1693 return "moveq %1,%0\n\tnot%.w %0";
1696 return "moveq %#-128,%0\n\tneg%.w %0";
1701 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1702 return "moveq %1,%0\n\tswap %0";
1705 return "move%.l %1,%0";
1712 output_move_simode_const (rtx
*operands
)
1714 if (operands
[1] == const0_rtx
1715 && (DATA_REG_P (operands
[0])
1716 || GET_CODE (operands
[0]) == MEM
)
1717 /* clr insns on 68000 read before writing.
1718 This isn't so on the 68010, but we have no TARGET_68010. */
1719 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1720 || !(GET_CODE (operands
[0]) == MEM
1721 && MEM_VOLATILE_P (operands
[0]))))
1723 else if (operands
[1] == const0_rtx
1724 && ADDRESS_REG_P (operands
[0]))
1725 return "sub%.l %0,%0";
1726 else if (DATA_REG_P (operands
[0]))
1727 return output_move_const_into_data_reg (operands
);
1728 else if (ADDRESS_REG_P (operands
[0])
1729 && INTVAL (operands
[1]) < 0x8000
1730 && INTVAL (operands
[1]) >= -0x8000)
1731 return "move%.w %1,%0";
1732 else if (GET_CODE (operands
[0]) == MEM
1733 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1734 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1735 && INTVAL (operands
[1]) < 0x8000
1736 && INTVAL (operands
[1]) >= -0x8000)
1738 return "move%.l %1,%0";
1742 output_move_simode (rtx
*operands
)
1744 if (GET_CODE (operands
[1]) == CONST_INT
)
1745 return output_move_simode_const (operands
);
1746 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1747 || GET_CODE (operands
[1]) == CONST
)
1748 && push_operand (operands
[0], SImode
))
1750 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1751 || GET_CODE (operands
[1]) == CONST
)
1752 && ADDRESS_REG_P (operands
[0]))
1753 return "lea %a1,%0";
1754 return "move%.l %1,%0";
1758 output_move_himode (rtx
*operands
)
1760 if (GET_CODE (operands
[1]) == CONST_INT
)
1762 if (operands
[1] == const0_rtx
1763 && (DATA_REG_P (operands
[0])
1764 || GET_CODE (operands
[0]) == MEM
)
1765 /* clr insns on 68000 read before writing.
1766 This isn't so on the 68010, but we have no TARGET_68010. */
1767 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1768 || !(GET_CODE (operands
[0]) == MEM
1769 && MEM_VOLATILE_P (operands
[0]))))
1771 else if (operands
[1] == const0_rtx
1772 && ADDRESS_REG_P (operands
[0]))
1773 return "sub%.l %0,%0";
1774 else if (DATA_REG_P (operands
[0])
1775 && INTVAL (operands
[1]) < 128
1776 && INTVAL (operands
[1]) >= -128)
1778 return "moveq %1,%0";
1780 else if (INTVAL (operands
[1]) < 0x8000
1781 && INTVAL (operands
[1]) >= -0x8000)
1782 return "move%.w %1,%0";
1784 else if (CONSTANT_P (operands
[1]))
1785 return "move%.l %1,%0";
1786 /* Recognize the insn before a tablejump, one that refers
1787 to a table of offsets. Such an insn will need to refer
1788 to a label on the insn. So output one. Use the label-number
1789 of the table of offsets to generate this label. This code,
1790 and similar code below, assumes that there will be at most one
1791 reference to each table. */
1792 if (GET_CODE (operands
[1]) == MEM
1793 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1794 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1795 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1797 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1798 #if MOTOROLA && !defined (SGS_SWITCH_TABLES)
1800 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1801 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1803 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1804 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1805 #endif /* not SGS */
1806 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1807 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1808 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1809 #ifdef SGS_SWITCH_TABLES
1810 /* Set flag saying we need to define the symbol
1811 LD%n (with value L%n-LI%n) at the end of the switch table. */
1812 switch_table_difference_label_flag
= 1;
1813 #endif /* SGS_SWITCH_TABLES */
1814 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1816 return "move%.w %1,%0";
1820 output_move_qimode (rtx
*operands
)
1824 /* This is probably useless, since it loses for pushing a struct
1825 of several bytes a byte at a time. */
1826 /* 68k family always modifies the stack pointer by at least 2, even for
1827 byte pushes. The 5200 (ColdFire) does not do this. */
1828 if (GET_CODE (operands
[0]) == MEM
1829 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1830 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1831 && ! ADDRESS_REG_P (operands
[1])
1832 && ! TARGET_COLDFIRE
)
1834 xoperands
[1] = operands
[1];
1836 = gen_rtx_MEM (QImode
,
1837 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1838 /* Just pushing a byte puts it in the high byte of the halfword. */
1839 /* We must put it in the low-order, high-numbered byte. */
1840 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1842 xoperands
[3] = stack_pointer_rtx
;
1843 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1846 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1850 /* clr and st insns on 68000 read before writing.
1851 This isn't so on the 68010, but we have no TARGET_68010. */
1852 if (!ADDRESS_REG_P (operands
[0])
1853 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1854 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1856 if (operands
[1] == const0_rtx
)
1858 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1859 && GET_CODE (operands
[1]) == CONST_INT
1860 && (INTVAL (operands
[1]) & 255) == 255)
1866 if (GET_CODE (operands
[1]) == CONST_INT
1867 && DATA_REG_P (operands
[0])
1868 && INTVAL (operands
[1]) < 128
1869 && INTVAL (operands
[1]) >= -128)
1871 return "moveq %1,%0";
1873 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1874 return "sub%.l %0,%0";
1875 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1876 return "move%.l %1,%0";
1877 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1878 from address registers. */
1879 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1880 return "move%.w %1,%0";
1881 return "move%.b %1,%0";
1885 output_move_stricthi (rtx
*operands
)
1887 if (operands
[1] == const0_rtx
1888 /* clr insns on 68000 read before writing.
1889 This isn't so on the 68010, but we have no TARGET_68010. */
1890 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1891 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1893 return "move%.w %1,%0";
1897 output_move_strictqi (rtx
*operands
)
1899 if (operands
[1] == const0_rtx
1900 /* clr insns on 68000 read before writing.
1901 This isn't so on the 68010, but we have no TARGET_68010. */
1902 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1903 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1905 return "move%.b %1,%0";
1908 /* Return the best assembler insn template
1909 for moving operands[1] into operands[0] as a fullword. */
1912 singlemove_string (rtx
*operands
)
1914 if (GET_CODE (operands
[1]) == CONST_INT
)
1915 return output_move_simode_const (operands
);
1916 return "move%.l %1,%0";
1920 /* Output assembler code to perform a doubleword move insn
1921 with operands OPERANDS. */
1924 output_move_double (rtx
*operands
)
1928 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1933 rtx addreg0
= 0, addreg1
= 0;
1934 int dest_overlapped_low
= 0;
1935 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1940 /* First classify both operands. */
1942 if (REG_P (operands
[0]))
1944 else if (offsettable_memref_p (operands
[0]))
1946 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1948 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1950 else if (GET_CODE (operands
[0]) == MEM
)
1955 if (REG_P (operands
[1]))
1957 else if (CONSTANT_P (operands
[1]))
1959 else if (offsettable_memref_p (operands
[1]))
1961 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1963 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1965 else if (GET_CODE (operands
[1]) == MEM
)
1970 /* Check for the cases that the operand constraints are not
1971 supposed to allow to happen. Abort if we get one,
1972 because generating code for these cases is painful. */
1974 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1977 /* If one operand is decrementing and one is incrementing
1978 decrement the former register explicitly
1979 and change that operand into ordinary indexing. */
1981 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1983 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1985 output_asm_insn ("sub%.l %#12,%0", operands
);
1987 output_asm_insn ("subq%.l %#8,%0", operands
);
1988 if (GET_MODE (operands
[1]) == XFmode
)
1989 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1990 else if (GET_MODE (operands
[0]) == DFmode
)
1991 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1993 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1996 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1998 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2000 output_asm_insn ("sub%.l %#12,%1", operands
);
2002 output_asm_insn ("subq%.l %#8,%1", operands
);
2003 if (GET_MODE (operands
[1]) == XFmode
)
2004 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2005 else if (GET_MODE (operands
[1]) == DFmode
)
2006 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2008 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2012 /* If an operand is an unoffsettable memory ref, find a register
2013 we can increment temporarily to make it refer to the second word. */
2015 if (optype0
== MEMOP
)
2016 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2018 if (optype1
== MEMOP
)
2019 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2021 /* Ok, we can do one word at a time.
2022 Normally we do the low-numbered word first,
2023 but if either operand is autodecrementing then we
2024 do the high-numbered word first.
2026 In either case, set up in LATEHALF the operands to use
2027 for the high-numbered word and in some cases alter the
2028 operands in OPERANDS to be suitable for the low-numbered word. */
2032 if (optype0
== REGOP
)
2034 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2035 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2037 else if (optype0
== OFFSOP
)
2039 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2040 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2044 middlehalf
[0] = operands
[0];
2045 latehalf
[0] = operands
[0];
2048 if (optype1
== REGOP
)
2050 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2051 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2053 else if (optype1
== OFFSOP
)
2055 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2056 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2058 else if (optype1
== CNSTOP
)
2060 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2065 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2066 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2067 operands
[1] = GEN_INT (l
[0]);
2068 middlehalf
[1] = GEN_INT (l
[1]);
2069 latehalf
[1] = GEN_INT (l
[2]);
2071 else if (CONSTANT_P (operands
[1]))
2073 /* actually, no non-CONST_DOUBLE constant should ever
2076 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2077 latehalf
[1] = constm1_rtx
;
2079 latehalf
[1] = const0_rtx
;
2084 middlehalf
[1] = operands
[1];
2085 latehalf
[1] = operands
[1];
2089 /* size is not 12: */
2091 if (optype0
== REGOP
)
2092 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2093 else if (optype0
== OFFSOP
)
2094 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2096 latehalf
[0] = operands
[0];
2098 if (optype1
== REGOP
)
2099 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2100 else if (optype1
== OFFSOP
)
2101 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2102 else if (optype1
== CNSTOP
)
2103 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2105 latehalf
[1] = operands
[1];
2108 /* If insn is effectively movd N(sp),-(sp) then we will do the
2109 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2110 for the low word as well, to compensate for the first decrement of sp. */
2111 if (optype0
== PUSHOP
2112 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2113 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2114 operands
[1] = middlehalf
[1] = latehalf
[1];
2116 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2117 if the upper part of reg N does not appear in the MEM, arrange to
2118 emit the move late-half first. Otherwise, compute the MEM address
2119 into the upper part of N and use that as a pointer to the memory
2121 if (optype0
== REGOP
2122 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2124 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2126 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2127 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2129 /* If both halves of dest are used in the src memory address,
2130 compute the address into latehalf of dest.
2131 Note that this can't happen if the dest is two data regs. */
2133 xops
[0] = latehalf
[0];
2134 xops
[1] = XEXP (operands
[1], 0);
2135 output_asm_insn ("lea %a1,%0", xops
);
2136 if (GET_MODE (operands
[1]) == XFmode
)
2138 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2139 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2140 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2144 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2145 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2149 && reg_overlap_mentioned_p (middlehalf
[0],
2150 XEXP (operands
[1], 0)))
2152 /* Check for two regs used by both source and dest.
2153 Note that this can't happen if the dest is all data regs.
2154 It can happen if the dest is d6, d7, a0.
2155 But in that case, latehalf is an addr reg, so
2156 the code at compadr does ok. */
2158 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2159 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2162 /* JRV says this can't happen: */
2163 if (addreg0
|| addreg1
)
2166 /* Only the middle reg conflicts; simply put it last. */
2167 output_asm_insn (singlemove_string (operands
), operands
);
2168 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2169 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2172 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2173 /* If the low half of dest is mentioned in the source memory
2174 address, the arrange to emit the move late half first. */
2175 dest_overlapped_low
= 1;
2178 /* If one or both operands autodecrementing,
2179 do the two words, high-numbered first. */
2181 /* Likewise, the first move would clobber the source of the second one,
2182 do them in the other order. This happens only for registers;
2183 such overlap can't happen in memory unless the user explicitly
2184 sets it up, and that is an undefined circumstance. */
2186 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2187 || (optype0
== REGOP
&& optype1
== REGOP
2188 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2189 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2190 || dest_overlapped_low
)
2192 /* Make any unoffsettable addresses point at high-numbered word. */
2196 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2198 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2203 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2205 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2209 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2211 /* Undo the adds we just did. */
2213 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2215 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2219 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2221 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2223 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2226 /* Do low-numbered word. */
2227 return singlemove_string (operands
);
2230 /* Normal case: do the two words, low-numbered first. */
2232 output_asm_insn (singlemove_string (operands
), operands
);
2234 /* Do the middle one of the three words for long double */
2238 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2240 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2242 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2245 /* Make any unoffsettable addresses point at high-numbered word. */
2247 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2249 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2252 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2254 /* Undo the adds we just did. */
2258 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2260 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2265 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2267 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2273 /* Return a REG that occurs in ADDR with coefficient 1.
2274 ADDR can be effectively incremented by incrementing REG. */
2277 find_addr_reg (rtx addr
)
2279 while (GET_CODE (addr
) == PLUS
)
2281 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2282 addr
= XEXP (addr
, 0);
2283 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2284 addr
= XEXP (addr
, 1);
2285 else if (CONSTANT_P (XEXP (addr
, 0)))
2286 addr
= XEXP (addr
, 1);
2287 else if (CONSTANT_P (XEXP (addr
, 1)))
2288 addr
= XEXP (addr
, 0);
2292 if (GET_CODE (addr
) == REG
)
2297 /* Output assembler code to perform a 32-bit 3-operand add. */
2300 output_addsi3 (rtx
*operands
)
2302 if (! operands_match_p (operands
[0], operands
[1]))
2304 if (!ADDRESS_REG_P (operands
[1]))
2306 rtx tmp
= operands
[1];
2308 operands
[1] = operands
[2];
2312 /* These insns can result from reloads to access
2313 stack slots over 64k from the frame pointer. */
2314 if (GET_CODE (operands
[2]) == CONST_INT
2315 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2316 return "move%.l %2,%0\n\tadd%.l %1,%0";
2318 if (GET_CODE (operands
[2]) == REG
)
2319 return "lea 0(%1,%2.l),%0";
2321 return "lea %c2(%1),%0";
2325 if (GET_CODE (operands
[2]) == REG
)
2326 return "lea (%1,%2.l),%0";
2328 return "lea (%c2,%1),%0";
2330 else /* !MOTOROLA (MIT syntax) */
2332 if (GET_CODE (operands
[2]) == REG
)
2333 return "lea %1@(0,%2:l),%0";
2335 return "lea %1@(%c2),%0";
2339 if (GET_CODE (operands
[2]) == CONST_INT
)
2341 if (INTVAL (operands
[2]) > 0
2342 && INTVAL (operands
[2]) <= 8)
2343 return "addq%.l %2,%0";
2344 if (INTVAL (operands
[2]) < 0
2345 && INTVAL (operands
[2]) >= -8)
2347 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2348 return "subq%.l %2,%0";
2350 /* On the CPU32 it is faster to use two addql instructions to
2351 add a small integer (8 < N <= 16) to a register.
2352 Likewise for subql. */
2353 if (TARGET_CPU32
&& REG_P (operands
[0]))
2355 if (INTVAL (operands
[2]) > 8
2356 && INTVAL (operands
[2]) <= 16)
2358 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2359 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2361 if (INTVAL (operands
[2]) < -8
2362 && INTVAL (operands
[2]) >= -16)
2364 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2365 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2368 if (ADDRESS_REG_P (operands
[0])
2369 && INTVAL (operands
[2]) >= -0x8000
2370 && INTVAL (operands
[2]) < 0x8000)
2373 return "add%.w %2,%0";
2375 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2378 return "add%.l %2,%0";
2381 /* Store in cc_status the expressions that the condition codes will
2382 describe after execution of an instruction whose pattern is EXP.
2383 Do not alter them if the instruction would not alter the cc's. */
2385 /* On the 68000, all the insns to store in an address register fail to
2386 set the cc's. However, in some cases these instructions can make it
2387 possibly invalid to use the saved cc's. In those cases we clear out
2388 some or all of the saved cc's so they won't be used. */
2391 notice_update_cc (rtx exp
, rtx insn
)
2393 if (GET_CODE (exp
) == SET
)
2395 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2399 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2401 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2402 cc_status
.value1
= 0;
2403 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2404 cc_status
.value2
= 0;
2406 else if (!FP_REG_P (SET_DEST (exp
))
2407 && SET_DEST (exp
) != cc0_rtx
2408 && (FP_REG_P (SET_SRC (exp
))
2409 || GET_CODE (SET_SRC (exp
)) == FIX
2410 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2411 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2415 /* A pair of move insns doesn't produce a useful overall cc. */
2416 else if (!FP_REG_P (SET_DEST (exp
))
2417 && !FP_REG_P (SET_SRC (exp
))
2418 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2419 && (GET_CODE (SET_SRC (exp
)) == REG
2420 || GET_CODE (SET_SRC (exp
)) == MEM
2421 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2425 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2429 else if (XEXP (exp
, 0) != pc_rtx
)
2431 cc_status
.flags
= 0;
2432 cc_status
.value1
= XEXP (exp
, 0);
2433 cc_status
.value2
= XEXP (exp
, 1);
2436 else if (GET_CODE (exp
) == PARALLEL
2437 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2439 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2441 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2443 cc_status
.flags
= 0;
2444 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2445 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2450 if (cc_status
.value2
!= 0
2451 && ADDRESS_REG_P (cc_status
.value2
)
2452 && GET_MODE (cc_status
.value2
) == QImode
)
2454 if (cc_status
.value2
!= 0)
2455 switch (GET_CODE (cc_status
.value2
))
2457 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2458 case ROTATE
: case ROTATERT
:
2459 /* These instructions always clear the overflow bit, and set
2460 the carry to the bit shifted out. */
2461 /* ??? We don't currently have a way to signal carry not valid,
2462 nor do we check for it in the branch insns. */
2466 case PLUS
: case MINUS
: case MULT
:
2467 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2468 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2469 cc_status
.flags
|= CC_NO_OVERFLOW
;
2472 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2473 ends with a move insn moving r2 in r2's mode.
2474 Thus, the cc's are set for r2.
2475 This can set N bit spuriously. */
2476 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2481 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2483 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2484 cc_status
.value2
= 0;
2485 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2486 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2487 cc_status
.flags
= CC_IN_68881
;
2491 output_move_const_double (rtx
*operands
)
2493 int code
= standard_68881_constant_p (operands
[1]);
2497 static char buf
[40];
2499 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2502 return "fmove%.d %1,%0";
2506 output_move_const_single (rtx
*operands
)
2508 int code
= standard_68881_constant_p (operands
[1]);
2512 static char buf
[40];
2514 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2517 return "fmove%.s %f1,%0";
2520 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2521 from the "fmovecr" instruction.
2522 The value, anded with 0xff, gives the code to use in fmovecr
2523 to get the desired constant. */
2525 /* This code has been fixed for cross-compilation. */
2527 static int inited_68881_table
= 0;
2529 static const char *const strings_68881
[7] = {
2539 static const int codes_68881
[7] = {
2549 REAL_VALUE_TYPE values_68881
[7];
2551 /* Set up values_68881 array by converting the decimal values
2552 strings_68881 to binary. */
2555 init_68881_table (void)
2559 enum machine_mode mode
;
2562 for (i
= 0; i
< 7; i
++)
2566 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2567 values_68881
[i
] = r
;
2569 inited_68881_table
= 1;
2573 standard_68881_constant_p (rtx x
)
2578 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2579 used at all on those chips. */
2580 if (TARGET_68040
|| TARGET_68060
)
2583 if (! inited_68881_table
)
2584 init_68881_table ();
2586 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2588 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2590 for (i
= 0; i
< 6; i
++)
2592 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2593 return (codes_68881
[i
]);
2596 if (GET_MODE (x
) == SFmode
)
2599 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2600 return (codes_68881
[6]);
2602 /* larger powers of ten in the constants ram are not used
2603 because they are not equal to a `double' C constant. */
2607 /* If X is a floating-point constant, return the logarithm of X base 2,
2608 or 0 if X is not a power of 2. */
2611 floating_exact_log2 (rtx x
)
2613 REAL_VALUE_TYPE r
, r1
;
2616 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2618 if (REAL_VALUES_LESS (r
, dconst1
))
2621 exp
= real_exponent (&r
);
2622 real_2expN (&r1
, exp
);
2623 if (REAL_VALUES_EQUAL (r1
, r
))
2629 /* A C compound statement to output to stdio stream STREAM the
2630 assembler syntax for an instruction operand X. X is an RTL
2633 CODE is a value that can be used to specify one of several ways
2634 of printing the operand. It is used when identical operands
2635 must be printed differently depending on the context. CODE
2636 comes from the `%' specification that was used to request
2637 printing of the operand. If the specification was just `%DIGIT'
2638 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2639 is the ASCII code for LTR.
2641 If X is a register, this macro should print the register's name.
2642 The names can be found in an array `reg_names' whose type is
2643 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2645 When the machine description has a specification `%PUNCT' (a `%'
2646 followed by a punctuation character), this macro is called with
2647 a null pointer for X and the punctuation character for CODE.
2649 The m68k specific codes are:
2651 '.' for dot needed in Motorola-style opcode names.
2652 '-' for an operand pushing on the stack:
2653 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2654 '+' for an operand pushing on the stack:
2655 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2656 '@' for a reference to the top word on the stack:
2657 sp@, (sp) or (%sp) depending on the style of syntax.
2658 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2659 but & in SGS syntax).
2660 '!' for the cc register (used in an `and to cc' insn).
2661 '$' for the letter `s' in an op code, but only on the 68040.
2662 '&' for the letter `d' in an op code, but only on the 68040.
2663 '/' for register prefix needed by longlong.h.
2665 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2666 'd' to force memory addressing to be absolute, not relative.
2667 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2668 'o' for operands to go directly to output_operand_address (bypassing
2669 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2670 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2671 or print pair of registers as rx:ry.
2676 print_operand (FILE *file
, rtx op
, int letter
)
2681 fprintf (file
, ".");
2683 else if (letter
== '#')
2684 asm_fprintf (file
, "%I");
2685 else if (letter
== '-')
2686 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2687 else if (letter
== '+')
2688 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2689 else if (letter
== '@')
2690 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2691 else if (letter
== '!')
2692 asm_fprintf (file
, "%Rfpcr");
2693 else if (letter
== '$')
2695 if (TARGET_68040_ONLY
)
2696 fprintf (file
, "s");
2698 else if (letter
== '&')
2700 if (TARGET_68040_ONLY
)
2701 fprintf (file
, "d");
2703 else if (letter
== '/')
2704 asm_fprintf (file
, "%R");
2705 else if (letter
== 'o')
2707 /* This is only for direct addresses with TARGET_PCREL */
2708 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2711 output_addr_const (file
, XEXP (op
, 0));
2713 else if (GET_CODE (op
) == REG
)
2716 /* Print out the second register name of a register pair.
2717 I.e., R (6) => 7. */
2718 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2720 fputs (M68K_REGNAME(REGNO (op
)), file
);
2722 else if (GET_CODE (op
) == MEM
)
2724 output_address (XEXP (op
, 0));
2725 if (letter
== 'd' && ! TARGET_68020
2726 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2727 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2728 && INTVAL (XEXP (op
, 0)) < 0x8000
2729 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2730 fprintf (file
, MOTOROLA
? ".l" : ":l");
2732 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2735 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2736 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2738 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2741 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2742 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2744 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2747 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2748 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2752 /* Use `print_operand_address' instead of `output_addr_const'
2753 to ensure that we print relevant PIC stuff. */
2754 asm_fprintf (file
, "%I");
2756 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2757 print_operand_address (file
, op
);
2759 output_addr_const (file
, op
);
2764 /* A C compound statement to output to stdio stream STREAM the
2765 assembler syntax for an instruction operand that is a memory
2766 reference whose address is ADDR. ADDR is an RTL expression.
2768 Note that this contains a kludge that knows that the only reason
2769 we have an address (plus (label_ref...) (reg...)) when not generating
2770 PIC code is in the insn before a tablejump, and we know that m68k.md
2771 generates a label LInnn: on such an insn.
2773 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2774 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2776 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2777 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2778 we want. This difference can be accommodated by using an assembler
2779 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2780 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2781 macro. See m68k/sgs.h for an example; for versions without the bug.
2782 Some assemblers refuse all the above solutions. The workaround is to
2783 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2786 They also do not like things like "pea 1.w", so we simple leave off
2787 the .w on small constants.
2789 This routine is responsible for distinguishing between -fpic and -fPIC
2790 style relocations in an address. When generating -fpic code the
2791 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2792 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2794 #ifndef ASM_OUTPUT_CASE_FETCH
2797 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2798 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2800 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2801 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2803 # else /* !MOTOROLA */
2804 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2805 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2806 # endif /* !MOTOROLA */
2807 #endif /* ASM_OUTPUT_CASE_FETCH */
2810 print_operand_address (FILE *file
, rtx addr
)
2812 register rtx reg1
, reg2
, breg
, ireg
;
2815 switch (GET_CODE (addr
))
2818 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2821 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2822 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2825 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2826 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2829 reg1
= reg2
= ireg
= breg
= offset
= 0;
2830 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2832 offset
= XEXP (addr
, 0);
2833 addr
= XEXP (addr
, 1);
2835 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2837 offset
= XEXP (addr
, 1);
2838 addr
= XEXP (addr
, 0);
2840 if (GET_CODE (addr
) != PLUS
)
2844 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2846 reg1
= XEXP (addr
, 0);
2847 addr
= XEXP (addr
, 1);
2849 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2851 reg1
= XEXP (addr
, 1);
2852 addr
= XEXP (addr
, 0);
2854 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2856 reg1
= XEXP (addr
, 0);
2857 addr
= XEXP (addr
, 1);
2859 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2861 reg1
= XEXP (addr
, 1);
2862 addr
= XEXP (addr
, 0);
2864 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2866 reg1
= XEXP (addr
, 0);
2867 addr
= XEXP (addr
, 1);
2869 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2871 reg1
= XEXP (addr
, 1);
2872 addr
= XEXP (addr
, 0);
2874 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2875 || GET_CODE (addr
) == SIGN_EXTEND
)
2887 #if 0 /* for OLD_INDEXING */
2888 else if (GET_CODE (addr
) == PLUS
)
2890 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2892 reg2
= XEXP (addr
, 0);
2893 addr
= XEXP (addr
, 1);
2895 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2897 reg2
= XEXP (addr
, 1);
2898 addr
= XEXP (addr
, 0);
2910 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2911 || GET_CODE (reg1
) == MULT
))
2912 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2917 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2922 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2923 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2926 if (GET_CODE (ireg
) == MULT
)
2928 scale
= INTVAL (XEXP (ireg
, 1));
2929 ireg
= XEXP (ireg
, 0);
2931 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2933 ASM_OUTPUT_CASE_FETCH (file
,
2934 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2935 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2936 fprintf (file
, "w");
2940 ASM_OUTPUT_CASE_FETCH (file
,
2941 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2942 M68K_REGNAME(REGNO (ireg
)));
2943 fprintf (file
, "l");
2946 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2950 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2951 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2953 ASM_OUTPUT_CASE_FETCH (file
,
2954 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2955 M68K_REGNAME(REGNO (breg
)));
2956 fprintf (file
, "l)");
2959 if (ireg
!= 0 || breg
!= 0)
2966 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2974 output_addr_const (file
, addr
);
2975 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2977 fprintf (file
, "@GOT");
2979 fprintf (file
, ".w");
2982 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2986 else /* !MOTOROLA */
2988 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2991 output_addr_const (file
, addr
);
2992 if (breg
== pic_offset_table_rtx
)
2996 fprintf (file
, ":w"); break;
2998 fprintf (file
, ":l"); break;
3006 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3008 scale
= INTVAL (XEXP (ireg
, 1));
3009 ireg
= XEXP (ireg
, 0);
3011 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3012 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3013 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
3015 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3016 M68K_REGNAME(REGNO (ireg
)));
3018 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3022 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3023 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3025 ASM_OUTPUT_CASE_FETCH (file
,
3026 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3027 M68K_REGNAME(REGNO (reg1
)));
3028 fprintf (file
, "l)");
3031 /* FALL-THROUGH (is this really what we want?) */
3033 if (GET_CODE (addr
) == CONST_INT
3034 && INTVAL (addr
) < 0x8000
3035 && INTVAL (addr
) >= -0x8000)
3039 /* Many SGS assemblers croak on size specifiers for constants. */
3040 fprintf (file
, "%d", (int) INTVAL (addr
));
3042 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3044 else /* !MOTOROLA */
3045 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3047 else if (GET_CODE (addr
) == CONST_INT
)
3049 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3051 else if (TARGET_PCREL
)
3054 output_addr_const (file
, addr
);
3056 asm_fprintf (file
, ":w,%Rpc)");
3058 asm_fprintf (file
, ":l,%Rpc)");
3062 /* Special case for SYMBOL_REF if the symbol name ends in
3063 `.<letter>', this can be mistaken as a size suffix. Put
3064 the name in parentheses. */
3065 if (GET_CODE (addr
) == SYMBOL_REF
3066 && strlen (XSTR (addr
, 0)) > 2
3067 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3070 output_addr_const (file
, addr
);
3074 output_addr_const (file
, addr
);
3080 /* Check for cases where a clr insns can be omitted from code using
3081 strict_low_part sets. For example, the second clrl here is not needed:
3082 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3084 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3085 insn we are checking for redundancy. TARGET is the register set by the
3089 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3094 p
= prev_nonnote_insn (first_insn
);
3098 /* If it isn't an insn, then give up. */
3099 if (GET_CODE (p
) != INSN
)
3102 if (reg_set_p (target
, p
))
3104 rtx set
= single_set (p
);
3107 /* If it isn't an easy to recognize insn, then give up. */
3111 dest
= SET_DEST (set
);
3113 /* If this sets the entire target register to zero, then our
3114 first_insn is redundant. */
3115 if (rtx_equal_p (dest
, target
)
3116 && SET_SRC (set
) == const0_rtx
)
3118 else if (GET_CODE (dest
) == STRICT_LOW_PART
3119 && GET_CODE (XEXP (dest
, 0)) == REG
3120 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3121 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3122 <= GET_MODE_SIZE (mode
)))
3123 /* This is a strict low part set which modifies less than
3124 we are using, so it is safe. */
3130 p
= prev_nonnote_insn (p
);
3136 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3137 range carefully since this predicate is used in DImode contexts. Also, we
3138 need some extra crud to make it work when hosted on 64-bit machines. */
3141 const_uint32_operand (rtx op
, enum machine_mode mode
)
3143 /* It doesn't make sense to ask this question with a mode that is
3144 not larger than 32 bits. */
3145 if (GET_MODE_BITSIZE (mode
) <= 32)
3148 #if HOST_BITS_PER_WIDE_INT > 32
3149 /* All allowed constants will fit a CONST_INT. */
3150 return (GET_CODE (op
) == CONST_INT
3151 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3153 return (GET_CODE (op
) == CONST_INT
3154 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3158 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3159 to check the range carefully since this predicate is used in DImode
3163 const_sint32_operand (rtx op
, enum machine_mode mode
)
3165 /* It doesn't make sense to ask this question with a mode that is
3166 not larger than 32 bits. */
3167 if (GET_MODE_BITSIZE (mode
) <= 32)
3170 /* All allowed constants will fit a CONST_INT. */
3171 return (GET_CODE (op
) == CONST_INT
3172 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3175 /* Operand predicates for implementing asymmetric pc-relative addressing
3176 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3177 when used as a source operand, but not as a destination operand.
3179 We model this by restricting the meaning of the basic predicates
3180 (general_operand, memory_operand, etc) to forbid the use of this
3181 addressing mode, and then define the following predicates that permit
3182 this addressing mode. These predicates can then be used for the
3183 source operands of the appropriate instructions.
3185 n.b. While it is theoretically possible to change all machine patterns
3186 to use this addressing more where permitted by the architecture,
3187 it has only been implemented for "common" cases: SImode, HImode, and
3188 QImode operands, and only for the principle operations that would
3189 require this addressing mode: data movement and simple integer operations.
3191 In parallel with these new predicates, two new constraint letters
3192 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3193 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3194 In the pcrel case 's' is only valid in combination with 'a' registers.
3195 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3196 of how these constraints are used.
3198 The use of these predicates is strictly optional, though patterns that
3199 don't will cause an extra reload register to be allocated where one
3202 lea (abc:w,%pc),%a0 ; need to reload address
3203 moveq &1,%d1 ; since write to pc-relative space
3204 movel %d1,%a0@ ; is not allowed
3206 lea (abc:w,%pc),%a1 ; no need to reload address here
3207 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3209 For more info, consult tiemann@cygnus.com.
3212 All of the ugliness with predicates and constraints is due to the
3213 simple fact that the m68k does not allow a pc-relative addressing
3214 mode as a destination. gcc does not distinguish between source and
3215 destination addresses. Hence, if we claim that pc-relative address
3216 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3217 end up with invalid code. To get around this problem, we left
3218 pc-relative modes as invalid addresses, and then added special
3219 predicates and constraints to accept them.
3221 A cleaner way to handle this is to modify gcc to distinguish
3222 between source and destination addresses. We can then say that
3223 pc-relative is a valid source address but not a valid destination
3224 address, and hopefully avoid a lot of the predicate and constraint
3225 hackery. Unfortunately, this would be a pretty big change. It would
3226 be a useful change for a number of ports, but there aren't any current
3227 plans to undertake this.
3229 ***************************************************************************/
3232 /* Special case of a general operand that's used as a source operand.
3233 Use this to permit reads from PC-relative memory when -mpcrel
3237 general_src_operand (rtx op
, enum machine_mode mode
)
3240 && GET_CODE (op
) == MEM
3241 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3242 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3243 || GET_CODE (XEXP (op
, 0)) == CONST
))
3245 return general_operand (op
, mode
);
3248 /* Special case of a nonimmediate operand that's used as a source.
3249 Use this to permit reads from PC-relative memory when -mpcrel
3253 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3255 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3256 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3257 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3258 || GET_CODE (XEXP (op
, 0)) == CONST
))
3260 return nonimmediate_operand (op
, mode
);
3263 /* Special case of a memory operand that's used as a source.
3264 Use this to permit reads from PC-relative memory when -mpcrel
3268 memory_src_operand (rtx op
, enum machine_mode mode
)
3270 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3271 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3272 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3273 || GET_CODE (XEXP (op
, 0)) == CONST
))
3275 return memory_operand (op
, mode
);
3278 /* Predicate that accepts only a pc-relative address. This is needed
3279 because pc-relative addresses don't satisfy the predicate
3280 "general_src_operand". */
3283 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3285 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3286 || GET_CODE (op
) == CONST
);
3290 output_andsi3 (rtx
*operands
)
3293 if (GET_CODE (operands
[2]) == CONST_INT
3294 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3295 && (DATA_REG_P (operands
[0])
3296 || offsettable_memref_p (operands
[0]))
3297 && !TARGET_COLDFIRE
)
3299 if (GET_CODE (operands
[0]) != REG
)
3300 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3301 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3302 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3304 if (operands
[2] == const0_rtx
)
3306 return "and%.w %2,%0";
3308 if (GET_CODE (operands
[2]) == CONST_INT
3309 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3310 && (DATA_REG_P (operands
[0])
3311 || offsettable_memref_p (operands
[0])))
3313 if (DATA_REG_P (operands
[0]))
3315 operands
[1] = GEN_INT (logval
);
3319 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3320 operands
[1] = GEN_INT (logval
% 8);
3322 /* This does not set condition codes in a standard way. */
3324 return "bclr %1,%0";
3326 return "and%.l %2,%0";
3330 output_iorsi3 (rtx
*operands
)
3332 register int logval
;
3333 if (GET_CODE (operands
[2]) == CONST_INT
3334 && INTVAL (operands
[2]) >> 16 == 0
3335 && (DATA_REG_P (operands
[0])
3336 || offsettable_memref_p (operands
[0]))
3337 && !TARGET_COLDFIRE
)
3339 if (GET_CODE (operands
[0]) != REG
)
3340 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3341 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3343 if (INTVAL (operands
[2]) == 0xffff)
3344 return "mov%.w %2,%0";
3345 return "or%.w %2,%0";
3347 if (GET_CODE (operands
[2]) == CONST_INT
3348 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3349 && (DATA_REG_P (operands
[0])
3350 || offsettable_memref_p (operands
[0])))
3352 if (DATA_REG_P (operands
[0]))
3353 operands
[1] = GEN_INT (logval
);
3356 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3357 operands
[1] = GEN_INT (logval
% 8);
3360 return "bset %1,%0";
3362 return "or%.l %2,%0";
3366 output_xorsi3 (rtx
*operands
)
3368 register int logval
;
3369 if (GET_CODE (operands
[2]) == CONST_INT
3370 && INTVAL (operands
[2]) >> 16 == 0
3371 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3372 && !TARGET_COLDFIRE
)
3374 if (! DATA_REG_P (operands
[0]))
3375 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3376 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3378 if (INTVAL (operands
[2]) == 0xffff)
3380 return "eor%.w %2,%0";
3382 if (GET_CODE (operands
[2]) == CONST_INT
3383 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3384 && (DATA_REG_P (operands
[0])
3385 || offsettable_memref_p (operands
[0])))
3387 if (DATA_REG_P (operands
[0]))
3388 operands
[1] = GEN_INT (logval
);
3391 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3392 operands
[1] = GEN_INT (logval
% 8);
3395 return "bchg %1,%0";
3397 return "eor%.l %2,%0";
3400 #ifdef M68K_TARGET_COFF
3402 /* Output assembly to switch to section NAME with attribute FLAGS. */
3405 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3409 if (flags
& SECTION_WRITE
)
3414 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3417 #endif /* M68K_TARGET_COFF */
3421 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3422 unsigned long labelno
)
3424 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3425 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3427 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3431 m68k_hp320_file_start (void)
3433 /* version 1: 68010.
3434 2: 68020 without FPU.
3435 3: 68020 with FPU. */
3436 fprintf (asm_out_file
, "\tversion %d\n",
3437 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3442 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3443 HOST_WIDE_INT delta
,
3444 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3450 if (delta
> 0 && delta
<= 8)
3451 asm_fprintf (file
, MOTOROLA
?
3452 "\taddq.l %I%d,4(%Rsp)\n" :
3453 "\taddql %I%d,%Rsp@(4)\n",
3455 else if (delta
< 0 && delta
>= -8)
3456 asm_fprintf (file
, MOTOROLA
?
3457 "\tsubq.l %I%d,4(%Rsp)\n" :
3458 "\tsubql %I%d,%Rsp@(4)\n",
3461 asm_fprintf (file
, MOTOROLA
?
3462 "\tadd.l %I%wd,4(%Rsp)\n" :
3463 "\taddl %I%wd,%Rsp@(4)\n",
3466 xops
[0] = DECL_RTL (function
);
3468 /* Logic taken from call patterns in m68k.md. */
3473 else if ((flag_pic
== 1) || TARGET_68020
)
3478 #elif defined(USE_GAS)
3479 fmt
= "bra.l %0@PLTPC";
3481 fmt
= "bra %0@PLTPC";
3483 else /* !MOTOROLA */
3490 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3491 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3493 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3497 #if MOTOROLA && !defined (USE_GAS)
3504 output_asm_insn (fmt
, xops
);
3507 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3510 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3511 int incoming ATTRIBUTE_UNUSED
)
3513 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);