1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 /* Needed for use_return_insn. */
44 #ifdef SUPPORT_SUN_FPA
46 /* Index into this array by (register number >> 3) to find the
47 smallest class which contains that register. */
48 enum reg_class regno_reg_class
[]
49 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
50 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
52 #endif /* defined SUPPORT_SUN_FPA */
54 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
55 if SGS_SWITCH_TABLE. */
56 int switch_table_difference_label_flag
;
58 static rtx
find_addr_reg ();
59 rtx
legitimize_pic_address ();
62 /* Alignment to use for loops and jumps */
63 /* Specify power of two alignment used for loops. */
64 char *m68k_align_loops_string
;
65 /* Specify power of two alignment used for non-loop jumps. */
66 char *m68k_align_jumps_string
;
67 /* Specify power of two alignment used for functions. */
68 char *m68k_align_funcs_string
;
70 /* Specify power of two alignment used for loops. */
72 /* Specify power of two alignment used for non-loop jumps. */
74 /* Specify power of two alignment used for functions. */
77 /* Nonzero if the last compare/test insn had FP operands. The
78 sCC expanders peek at this to determine what to do for the
79 68060, which has no fsCC instructions. */
80 int m68k_last_compare_had_fp_operands
;
82 /* Sometimes certain combinations of command options do not make
83 sense on a particular target machine. You can define a macro
84 `OVERRIDE_OPTIONS' to take account of this. This macro, if
85 defined, is executed once just after all the command options have
88 Don't use this macro to turn on various extra optimizations for
89 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
98 /* Validate -malign-loops= value, or provide default */
99 if (m68k_align_loops_string
)
101 m68k_align_loops
= atoi (m68k_align_loops_string
);
102 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
103 fatal ("-malign-loops=%d is not between 1 and %d",
104 m68k_align_loops
, MAX_CODE_ALIGN
);
107 m68k_align_loops
= def_align
;
109 /* Validate -malign-jumps= value, or provide default */
110 if (m68k_align_jumps_string
)
112 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
113 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
114 fatal ("-malign-jumps=%d is not between 1 and %d",
115 m68k_align_jumps
, MAX_CODE_ALIGN
);
118 m68k_align_jumps
= def_align
;
120 /* Validate -malign-functions= value, or provide default */
121 if (m68k_align_funcs_string
)
123 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
124 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
125 fatal ("-malign-functions=%d is not between 1 and %d",
126 m68k_align_funcs
, MAX_CODE_ALIGN
);
129 m68k_align_funcs
= def_align
;
132 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
133 function at any time during the compilation process. In the future
134 we should try and eliminate the USE if we can easily determine that
135 all PIC references were deleted from the current function. That would
136 save an address register */
141 if (flag_pic
&& current_function_uses_pic_offset_table
)
143 rtx insn
= gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
);
144 emit_insn_after (insn
, get_insns ());
150 /* This function generates the assembly code for function entry.
151 STREAM is a stdio stream to output the code to.
152 SIZE is an int: how many units of temporary storage to allocate.
153 Refer to the array `regs_ever_live' to determine which registers
154 to save; `regs_ever_live[I]' is nonzero if register number I
155 is ever used in the function. This function is responsible for
156 knowing which registers should not be saved even if used. */
159 /* Note that the order of the bit mask for fmovem is the opposite
160 of the order for movem! */
164 output_function_prologue (stream
, size
)
169 register int mask
= 0;
170 int num_saved_regs
= 0;
171 extern char call_used_regs
[];
172 int fsize
= (size
+ 3) & -4;
173 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
176 if (frame_pointer_needed
)
178 if (fsize
== 0 && TARGET_68040
)
180 /* on the 68040, pea + move is faster than link.w 0 */
182 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
183 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
184 reg_names
[FRAME_POINTER_REGNUM
]);
186 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
187 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
188 reg_names
[FRAME_POINTER_REGNUM
]);
191 else if (fsize
< 0x8000)
194 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
195 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
197 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
198 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
201 else if (TARGET_68020
)
204 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
205 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
207 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
208 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
213 /* Adding negative number is faster on the 68040. */
215 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
216 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
218 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
219 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
222 if (dwarf2out_do_frame ())
225 l
= (char *) dwarf2out_cfi_label ();
226 cfa_store_offset
+= 4;
227 cfa_offset
= cfa_store_offset
;
228 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
229 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
230 cfa_store_offset
+= fsize
;
235 if (fsize
+ 4 < 0x8000)
242 /* asm_fprintf() cannot handle %. */
244 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
246 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
251 /* asm_fprintf() cannot handle %. */
253 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
255 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
259 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
261 /* On the CPU32 it is faster to use two subqw instructions to
262 subtract a small integer (8 < N <= 16) to a register. */
263 /* asm_fprintf() cannot handle %. */
265 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
268 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
273 #endif /* NO_ADDSUB_Q */
276 /* Adding negative number is faster on the 68040. */
277 /* asm_fprintf() cannot handle %. */
279 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
281 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
287 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
289 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
295 /* asm_fprintf() cannot handle %. */
297 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
299 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
302 if (dwarf2out_do_frame ())
304 cfa_store_offset
+= fsize
;
305 cfa_offset
= cfa_store_offset
;
306 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
309 #ifdef SUPPORT_SUN_FPA
310 for (regno
= 24; regno
< 56; regno
++)
311 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
314 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
317 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
320 if (dwarf2out_do_frame ())
322 char *l
= dwarf2out_cfi_label ();
324 cfa_store_offset
+= 8;
325 if (! frame_pointer_needed
)
327 cfa_offset
= cfa_store_offset
;
328 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
330 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
336 for (regno
= 16; regno
< 24; regno
++)
337 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
339 mask
|= 1 << (regno
- 16);
342 if ((mask
& 0xff) != 0)
345 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
347 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
349 if (dwarf2out_do_frame ())
351 char *l
= (char *) dwarf2out_cfi_label ();
354 cfa_store_offset
+= num_saved_regs
* 12;
355 if (! frame_pointer_needed
)
357 cfa_offset
= cfa_store_offset
;
358 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
360 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
361 if (mask
& (1 << (regno
- 16)))
362 dwarf2out_reg_save (l
, regno
,
363 -cfa_store_offset
+ n_regs
++ * 12);
369 for (regno
= 0; regno
< 16; regno
++)
370 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
372 mask
|= 1 << (15 - regno
);
375 if (frame_pointer_needed
)
377 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
384 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
386 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
389 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
393 if (num_saved_regs
<= 2)
395 /* Store each separately in the same order moveml uses.
396 Using two movel instructions instead of a single moveml
397 is about 15% faster for the 68020 and 68030 at no expense
402 /* Undo the work from above. */
403 for (i
= 0; i
< 16; i
++)
408 "\t%Omove.l %s,-(%Rsp)\n",
410 "\tmovel %s,%Rsp@-\n",
413 if (dwarf2out_do_frame ())
415 char *l
= (char *) dwarf2out_cfi_label ();
417 cfa_store_offset
+= 4;
418 if (! frame_pointer_needed
)
420 cfa_offset
= cfa_store_offset
;
421 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
423 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
431 /* The coldfire does not support the predecrement form of the
432 movml instruction, so we must adjust the stack pointer and
433 then use the plain address register indirect mode. We also
434 have to invert the register save mask to use the new mode.
436 FIXME: if num_saved_regs was calculated earlier, we could
437 combine the stack pointer adjustment with any adjustment
438 done when the initial stack frame is created. This would
439 save an instruction */
444 for (i
= 0; i
< 16; i
++)
446 newmask
|= (1 << (15-i
));
449 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
450 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
452 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
453 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
459 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
461 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
464 if (dwarf2out_do_frame ())
466 char *l
= (char *) dwarf2out_cfi_label ();
469 cfa_store_offset
+= num_saved_regs
* 4;
470 if (! frame_pointer_needed
)
472 cfa_offset
= cfa_store_offset
;
473 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
475 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
476 if (mask
& (1 << (15 - regno
)))
477 dwarf2out_reg_save (l
, regno
,
478 -cfa_store_offset
+ n_regs
++ * 4);
481 if (flag_pic
&& current_function_uses_pic_offset_table
)
484 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
485 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
487 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
488 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
489 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
490 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
491 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
496 /* Return true if this function's epilogue can be output as RTL. */
503 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
506 /* Copied from output_function_epilogue (). We should probably create a
507 separate layout routine to perform the common work. */
509 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
510 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
516 /* This function generates the assembly code for function exit,
517 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
519 The function epilogue should not depend on the current stack pointer!
520 It should use the frame pointer only, if there is a frame pointer.
521 This is mandatory because of alloca; we also take advantage of it to
522 omit stack adjustments before returning. */
525 output_function_epilogue (stream
, size
)
530 register int mask
, fmask
;
532 int offset
, foffset
, fpoffset
;
533 extern char call_used_regs
[];
534 int fsize
= (size
+ 3) & -4;
536 rtx insn
= get_last_insn ();
537 int restore_from_sp
= 0;
539 /* If the last insn was a BARRIER, we don't have to write any code. */
540 if (GET_CODE (insn
) == NOTE
)
541 insn
= prev_nonnote_insn (insn
);
542 if (insn
&& GET_CODE (insn
) == BARRIER
)
544 /* Output just a no-op so that debuggers don't get confused
545 about which function the pc is in at this address. */
546 asm_fprintf (stream
, "\tnop\n");
550 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
551 if (profile_block_flag
== 2)
553 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
557 #ifdef FUNCTION_EXTRA_EPILOGUE
558 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
560 nregs
= 0; fmask
= 0; fpoffset
= 0;
561 #ifdef SUPPORT_SUN_FPA
562 for (regno
= 24 ; regno
< 56 ; regno
++)
563 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
565 fpoffset
= nregs
* 8;
570 for (regno
= 16; regno
< 24; regno
++)
571 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
574 fmask
|= 1 << (23 - regno
);
577 foffset
= fpoffset
+ nregs
* 12;
579 if (frame_pointer_needed
)
580 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
581 for (regno
= 0; regno
< 16; regno
++)
582 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
587 offset
= foffset
+ nregs
* 4;
588 /* FIXME : leaf_function_p below is too strong.
589 What we really need to know there is if there could be pending
590 stack adjustment needed at that point. */
591 restore_from_sp
= ! frame_pointer_needed
592 || (! current_function_calls_alloca
&& leaf_function_p ());
593 if (offset
+ fsize
>= 0x8000
595 && (mask
|| fmask
|| fpoffset
))
598 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
600 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
604 if (TARGET_5200
|| nregs
<= 2)
606 /* Restore each separately in the same order moveml does.
607 Using two movel instructions instead of a single moveml
608 is about 15% faster for the 68020 and 68030 at no expense
613 /* Undo the work from above. */
614 for (i
= 0; i
< 16; i
++)
620 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
622 reg_names
[FRAME_POINTER_REGNUM
],
625 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
626 reg_names
[FRAME_POINTER_REGNUM
],
627 offset
+ fsize
, reg_names
[i
]);
630 else if (restore_from_sp
)
633 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
636 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
643 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
645 reg_names
[FRAME_POINTER_REGNUM
],
648 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
649 reg_names
[FRAME_POINTER_REGNUM
],
650 offset
+ fsize
, reg_names
[i
]);
661 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
663 reg_names
[FRAME_POINTER_REGNUM
],
666 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
667 reg_names
[FRAME_POINTER_REGNUM
],
668 offset
+ fsize
, mask
);
671 else if (restore_from_sp
)
674 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
676 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
682 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
684 reg_names
[FRAME_POINTER_REGNUM
],
687 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
688 reg_names
[FRAME_POINTER_REGNUM
],
689 offset
+ fsize
, mask
);
698 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
700 reg_names
[FRAME_POINTER_REGNUM
],
703 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
704 reg_names
[FRAME_POINTER_REGNUM
],
705 foffset
+ fsize
, fmask
);
708 else if (restore_from_sp
)
711 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
713 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
719 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
721 reg_names
[FRAME_POINTER_REGNUM
],
724 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
725 reg_names
[FRAME_POINTER_REGNUM
],
726 foffset
+ fsize
, fmask
);
731 for (regno
= 55; regno
>= 24; regno
--)
732 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
737 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
739 reg_names
[FRAME_POINTER_REGNUM
],
742 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
743 reg_names
[FRAME_POINTER_REGNUM
],
744 fpoffset
+ fsize
, reg_names
[regno
]);
747 else if (restore_from_sp
)
750 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
753 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
760 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
762 reg_names
[FRAME_POINTER_REGNUM
],
765 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
766 reg_names
[FRAME_POINTER_REGNUM
],
767 fpoffset
+ fsize
, reg_names
[regno
]);
772 if (frame_pointer_needed
)
773 fprintf (stream
, "\tunlk %s\n",
774 reg_names
[FRAME_POINTER_REGNUM
]);
783 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
785 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
791 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
793 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
797 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
799 /* On the CPU32 it is faster to use two addqw instructions to
800 add a small integer (8 < N <= 16) to a register. */
801 /* asm_fprintf() cannot handle %. */
803 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
806 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
811 #endif /* NO_ADDSUB_Q */
812 if (fsize
+ 4 < 0x8000)
816 /* asm_fprintf() cannot handle %. */
818 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
820 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
826 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
828 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
834 /* asm_fprintf() cannot handle %. */
836 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
838 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
842 if (current_function_pops_args
)
843 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
845 fprintf (stream
, "\trts\n");
848 /* Similar to general_operand, but exclude stack_pointer_rtx. */
851 not_sp_operand (op
, mode
)
853 enum machine_mode mode
;
855 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
858 /* Return TRUE if X is a valid comparison operator for the dbcc
861 Note it rejects floating point comparison operators.
862 (In the future we could use Fdbcc).
864 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
867 valid_dbcc_comparison_p (x
, mode
)
869 enum machine_mode mode
;
871 switch (GET_CODE (x
))
873 case EQ
: case NE
: case GTU
: case LTU
:
877 /* Reject some when CC_NO_OVERFLOW is set. This may be over
879 case GT
: case LT
: case GE
: case LE
:
880 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
886 /* Return non-zero if flags are currently in the 68881 flag register. */
890 /* We could add support for these in the future */
891 return cc_status
.flags
& CC_IN_68881
;
894 /* Output a dbCC; jCC sequence. Note we do not handle the
895 floating point version of this sequence (Fdbcc). We also
896 do not handle alternative conditions when CC_NO_OVERFLOW is
897 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
898 kick those out before we get here. */
901 output_dbcc_and_branch (operands
)
904 switch (GET_CODE (operands
[3]))
908 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
910 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
916 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
918 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
924 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
926 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
932 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
934 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
940 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
942 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
948 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
950 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
956 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
958 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
964 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
966 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
972 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
974 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
980 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
982 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
990 /* If the decrement is to be done in SImode, then we have
991 to compensate for the fact that dbcc decrements in HImode. */
992 switch (GET_MODE (operands
[0]))
996 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
998 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1011 output_scc_di(op
, operand1
, operand2
, dest
)
1018 enum rtx_code op_code
= GET_CODE (op
);
1020 /* This does not produce a usefull cc. */
1023 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1024 below. Swap the operands and change the op if these requirements
1025 are not fulfilled. */
1026 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1030 operand1
= operand2
;
1032 op_code
= swap_condition (op_code
);
1034 loperands
[0] = operand1
;
1035 if (GET_CODE (operand1
) == REG
)
1036 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1038 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1039 if (operand2
!= const0_rtx
)
1041 loperands
[2] = operand2
;
1042 if (GET_CODE (operand2
) == REG
)
1043 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1045 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1047 loperands
[4] = gen_label_rtx();
1048 if (operand2
!= const0_rtx
)
1050 #ifdef SGS_CMP_ORDER
1051 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1053 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1056 #ifdef SGS_CMP_ORDER
1057 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1059 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1062 else if (TARGET_68020
|| TARGET_5200
)
1064 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
1066 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
1070 #ifdef SGS_CMP_ORDER
1071 output_asm_insn ("cmp%.w %0,%#0\n\tjbne %l4\n\tcmp%.w %1,%#0", loperands
);
1073 output_asm_insn ("cmp%.w %#0,%0\n\tjbne %l4\n\tcmp%.w %#0,%1", loperands
);
1076 #ifdef SGS_CMP_ORDER
1077 output_asm_insn ("cmp%.w %0,%#0\n\tjne %l4\n\tcmp%.w %1,%#0", loperands
);
1079 output_asm_insn ("cmp%.w %#0,%0\n\tjne %l4\n\tcmp%.w %#0,%1", loperands
);
1082 loperands
[5] = dest
;
1087 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1088 CODE_LABEL_NUMBER (loperands
[4]));
1089 output_asm_insn ("seq %5", loperands
);
1093 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1094 CODE_LABEL_NUMBER (loperands
[4]));
1095 output_asm_insn ("sne %5", loperands
);
1099 loperands
[6] = gen_label_rtx();
1101 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1103 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1105 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1106 CODE_LABEL_NUMBER (loperands
[4]));
1107 output_asm_insn ("sgt %5", loperands
);
1108 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1109 CODE_LABEL_NUMBER (loperands
[6]));
1113 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1114 CODE_LABEL_NUMBER (loperands
[4]));
1115 output_asm_insn ("shi %5", loperands
);
1119 loperands
[6] = gen_label_rtx();
1121 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1123 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1125 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1126 CODE_LABEL_NUMBER (loperands
[4]));
1127 output_asm_insn ("slt %5", loperands
);
1128 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1129 CODE_LABEL_NUMBER (loperands
[6]));
1133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1134 CODE_LABEL_NUMBER (loperands
[4]));
1135 output_asm_insn ("scs %5", loperands
);
1139 loperands
[6] = gen_label_rtx();
1141 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1143 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1145 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1146 CODE_LABEL_NUMBER (loperands
[4]));
1147 output_asm_insn ("sge %5", loperands
);
1148 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1149 CODE_LABEL_NUMBER (loperands
[6]));
1153 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1154 CODE_LABEL_NUMBER (loperands
[4]));
1155 output_asm_insn ("scc %5", loperands
);
1159 loperands
[6] = gen_label_rtx();
1161 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1163 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1165 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1166 CODE_LABEL_NUMBER (loperands
[4]));
1167 output_asm_insn ("sle %5", loperands
);
1168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1169 CODE_LABEL_NUMBER (loperands
[6]));
1173 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1174 CODE_LABEL_NUMBER (loperands
[4]));
1175 output_asm_insn ("sls %5", loperands
);
1185 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1187 rtx countop
, dataop
;
1191 operands
[0] = countop
;
1192 operands
[1] = dataop
;
1194 if (GET_CODE (countop
) == CONST_INT
)
1196 register int count
= INTVAL (countop
);
1197 /* If COUNT is bigger than size of storage unit in use,
1198 advance to the containing unit of same size. */
1199 if (count
> signpos
)
1201 int offset
= (count
& ~signpos
) / 8;
1202 count
= count
& signpos
;
1203 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1205 if (count
== signpos
)
1206 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1208 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1210 /* These three statements used to use next_insns_test_no...
1211 but it appears that this should do the same job. */
1213 && next_insn_tests_no_inequality (insn
))
1216 && next_insn_tests_no_inequality (insn
))
1219 && next_insn_tests_no_inequality (insn
))
1222 cc_status
.flags
= CC_NOT_NEGATIVE
;
1224 return "btst %0,%1";
1227 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1228 reference and a constant. */
1231 symbolic_operand (op
, mode
)
1233 enum machine_mode mode
;
1235 switch (GET_CODE (op
))
1243 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1244 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1245 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1247 #if 0 /* Deleted, with corresponding change in m68k.h,
1248 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1250 return GET_MODE (op
) == mode
;
1258 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1261 extend_operator(x
, mode
)
1263 enum machine_mode mode
;
1265 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1267 switch (GET_CODE(x
))
1278 /* Legitimize PIC addresses. If the address is already
1279 position-independent, we return ORIG. Newly generated
1280 position-independent addresses go to REG. If we need more
1281 than one register, we lose.
1283 An address is legitimized by making an indirect reference
1284 through the Global Offset Table with the name of the symbol
1287 The assembler and linker are responsible for placing the
1288 address of the symbol in the GOT. The function prologue
1289 is responsible for initializing a5 to the starting address
1292 The assembler is also responsible for translating a symbol name
1293 into a constant displacement from the start of the GOT.
1295 A quick example may make things a little clearer:
1297 When not generating PIC code to store the value 12345 into _foo
1298 we would generate the following code:
1302 When generating PIC two transformations are made. First, the compiler
1303 loads the address of foo into a register. So the first transformation makes:
1308 The code in movsi will intercept the lea instruction and call this
1309 routine which will transform the instructions into:
1311 movel a5@(_foo:w), a0
1315 That (in a nutshell) is how *all* symbol and label references are
1319 legitimize_pic_address (orig
, mode
, reg
)
1321 enum machine_mode mode
;
1325 /* First handle a simple SYMBOL_REF or LABEL_REF */
1326 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1331 pic_ref
= gen_rtx_MEM (Pmode
,
1332 gen_rtx_PLUS (Pmode
,
1333 pic_offset_table_rtx
, orig
));
1334 current_function_uses_pic_offset_table
= 1;
1335 if (reload_in_progress
)
1336 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1337 RTX_UNCHANGING_P (pic_ref
) = 1;
1338 emit_move_insn (reg
, pic_ref
);
1341 else if (GET_CODE (orig
) == CONST
)
1345 /* Make sure this is CONST has not already been legitimized */
1346 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1347 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1353 /* legitimize both operands of the PLUS */
1354 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1356 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1357 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1358 base
== reg
? 0 : reg
);
1362 if (GET_CODE (orig
) == CONST_INT
)
1363 return plus_constant_for_output (base
, INTVAL (orig
));
1364 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1365 /* Likewise, should we set special REG_NOTEs here? */
1371 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1373 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1376 const_method (constant
)
1382 i
= INTVAL (constant
);
1386 /* The Coldfire doesn't have byte or word operations. */
1387 /* FIXME: This may not be useful for the m68060 either */
1390 /* if -256 < N < 256 but N is not in range for a moveq
1391 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1392 if (USE_MOVQ (i
^ 0xff))
1394 /* Likewise, try with not.w */
1395 if (USE_MOVQ (i
^ 0xffff))
1397 /* This is the only value where neg.w is useful */
1400 /* Try also with swap */
1402 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1405 /* Otherwise, use move.l */
1410 const_int_cost (constant
)
1413 switch (const_method (constant
))
1416 /* Constants between -128 and 127 are cheap due to moveq */
1422 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1432 output_move_const_into_data_reg (operands
)
1437 i
= INTVAL (operands
[1]);
1438 switch (const_method (operands
[1]))
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %1,%0";
1444 return "moveq %1,%0";
1447 operands
[1] = GEN_INT (i
^ 0xff);
1448 #if defined (MOTOROLA) && !defined (CRDS)
1449 return "moveq%.l %1,%0\n\tnot%.b %0";
1451 return "moveq %1,%0\n\tnot%.b %0";
1454 operands
[1] = GEN_INT (i
^ 0xffff);
1455 #if defined (MOTOROLA) && !defined (CRDS)
1456 return "moveq%.l %1,%0\n\tnot%.w %0";
1458 return "moveq %1,%0\n\tnot%.w %0";
1461 #if defined (MOTOROLA) && !defined (CRDS)
1462 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1464 return "moveq %#-128,%0\n\tneg%.w %0";
1470 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1471 #if defined (MOTOROLA) && !defined (CRDS)
1472 return "moveq%.l %1,%0\n\tswap %0";
1474 return "moveq %1,%0\n\tswap %0";
1478 return "move%.l %1,%0";
1485 output_move_simode_const (operands
)
1488 if (operands
[1] == const0_rtx
1489 && (DATA_REG_P (operands
[0])
1490 || GET_CODE (operands
[0]) == MEM
)
1491 /* clr insns on 68000 read before writing.
1492 This isn't so on the 68010, but we have no TARGET_68010. */
1493 && ((TARGET_68020
|| TARGET_5200
)
1494 || !(GET_CODE (operands
[0]) == MEM
1495 && MEM_VOLATILE_P (operands
[0]))))
1497 else if (DATA_REG_P (operands
[0]))
1498 return output_move_const_into_data_reg (operands
);
1499 else if (ADDRESS_REG_P (operands
[0])
1500 && INTVAL (operands
[1]) < 0x8000
1501 && INTVAL (operands
[1]) >= -0x8000)
1502 return "move%.w %1,%0";
1503 else if (GET_CODE (operands
[0]) == MEM
1504 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1505 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1506 && INTVAL (operands
[1]) < 0x8000
1507 && INTVAL (operands
[1]) >= -0x8000)
1509 return "move%.l %1,%0";
1513 output_move_simode (operands
)
1516 if (GET_CODE (operands
[1]) == CONST_INT
)
1517 return output_move_simode_const (operands
);
1518 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1519 || GET_CODE (operands
[1]) == CONST
)
1520 && push_operand (operands
[0], SImode
))
1522 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1523 || GET_CODE (operands
[1]) == CONST
)
1524 && ADDRESS_REG_P (operands
[0]))
1525 return "lea %a1,%0";
1526 return "move%.l %1,%0";
1530 output_move_himode (operands
)
1533 if (GET_CODE (operands
[1]) == CONST_INT
)
1535 if (operands
[1] == const0_rtx
1536 && (DATA_REG_P (operands
[0])
1537 || GET_CODE (operands
[0]) == MEM
)
1538 /* clr insns on 68000 read before writing.
1539 This isn't so on the 68010, but we have no TARGET_68010. */
1540 && ((TARGET_68020
|| TARGET_5200
)
1541 || !(GET_CODE (operands
[0]) == MEM
1542 && MEM_VOLATILE_P (operands
[0]))))
1544 else if (DATA_REG_P (operands
[0])
1545 && INTVAL (operands
[1]) < 128
1546 && INTVAL (operands
[1]) >= -128)
1548 #if defined(MOTOROLA) && !defined(CRDS)
1549 return "moveq%.l %1,%0";
1551 return "moveq %1,%0";
1554 else if (INTVAL (operands
[1]) < 0x8000
1555 && INTVAL (operands
[1]) >= -0x8000)
1556 return "move%.w %1,%0";
1558 else if (CONSTANT_P (operands
[1]))
1559 return "move%.l %1,%0";
1561 /* Recognize the insn before a tablejump, one that refers
1562 to a table of offsets. Such an insn will need to refer
1563 to a label on the insn. So output one. Use the label-number
1564 of the table of offsets to generate this label. This code,
1565 and similar code below, assumes that there will be at most one
1566 reference to each table. */
1567 if (GET_CODE (operands
[1]) == MEM
1568 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1569 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1570 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1572 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1573 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1575 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1576 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1578 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1579 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1580 #endif /* not SGS */
1581 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1582 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1583 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1584 #ifdef SGS_SWITCH_TABLES
1585 /* Set flag saying we need to define the symbol
1586 LD%n (with value L%n-LI%n) at the end of the switch table. */
1587 switch_table_difference_label_flag
= 1;
1588 #endif /* SGS_SWITCH_TABLES */
1589 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1591 #endif /* SGS_NO_LI */
1592 return "move%.w %1,%0";
1596 output_move_qimode (operands
)
1601 /* This is probably useless, since it loses for pushing a struct
1602 of several bytes a byte at a time. */
1603 /* 68k family always modifies the stack pointer by at least 2, even for
1604 byte pushes. The 5200 (coldfire) does not do this. */
1605 if (GET_CODE (operands
[0]) == MEM
1606 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1607 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1608 && ! ADDRESS_REG_P (operands
[1])
1611 xoperands
[1] = operands
[1];
1613 = gen_rtx_MEM (QImode
,
1614 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1615 /* Just pushing a byte puts it in the high byte of the halfword. */
1616 /* We must put it in the low-order, high-numbered byte. */
1617 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1619 xoperands
[3] = stack_pointer_rtx
;
1621 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1623 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1627 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1631 /* clr and st insns on 68000 read before writing.
1632 This isn't so on the 68010, but we have no TARGET_68010. */
1633 if (!ADDRESS_REG_P (operands
[0])
1634 && ((TARGET_68020
|| TARGET_5200
)
1635 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1637 if (operands
[1] == const0_rtx
)
1639 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1640 && GET_CODE (operands
[1]) == CONST_INT
1641 && (INTVAL (operands
[1]) & 255) == 255)
1647 if (GET_CODE (operands
[1]) == CONST_INT
1648 && DATA_REG_P (operands
[0])
1649 && INTVAL (operands
[1]) < 128
1650 && INTVAL (operands
[1]) >= -128)
1652 #if defined(MOTOROLA) && !defined(CRDS)
1653 return "moveq%.l %1,%0";
1655 return "moveq %1,%0";
1658 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1659 return "move%.l %1,%0";
1660 /* 68k family doesn't support byte moves to from address registers. The
1661 5200 (coldfire) does not have this restriction. */
1662 if ((ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1664 return "move%.w %1,%0";
1665 return "move%.b %1,%0";
1669 output_move_stricthi (operands
)
1672 if (operands
[1] == const0_rtx
1673 /* clr insns on 68000 read before writing.
1674 This isn't so on the 68010, but we have no TARGET_68010. */
1675 && ((TARGET_68020
|| TARGET_5200
)
1676 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1678 return "move%.w %1,%0";
1682 output_move_strictqi (operands
)
1685 if (operands
[1] == const0_rtx
1686 /* clr insns on 68000 read before writing.
1687 This isn't so on the 68010, but we have no TARGET_68010. */
1688 && ((TARGET_68020
|| TARGET_5200
)
1689 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1691 return "move%.b %1,%0";
1694 /* Return the best assembler insn template
1695 for moving operands[1] into operands[0] as a fullword. */
1698 singlemove_string (operands
)
1701 #ifdef SUPPORT_SUN_FPA
1702 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1703 return "fpmoves %1,%0";
1705 if (GET_CODE (operands
[1]) == CONST_INT
)
1706 return output_move_simode_const (operands
);
1707 return "move%.l %1,%0";
1711 /* Output assembler code to perform a doubleword move insn
1712 with operands OPERANDS. */
1715 output_move_double (operands
)
1720 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1725 rtx addreg0
= 0, addreg1
= 0;
1726 int dest_overlapped_low
= 0;
1727 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1732 /* First classify both operands. */
1734 if (REG_P (operands
[0]))
1736 else if (offsettable_memref_p (operands
[0]))
1738 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1740 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1742 else if (GET_CODE (operands
[0]) == MEM
)
1747 if (REG_P (operands
[1]))
1749 else if (CONSTANT_P (operands
[1]))
1751 else if (offsettable_memref_p (operands
[1]))
1753 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1755 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1757 else if (GET_CODE (operands
[1]) == MEM
)
1762 /* Check for the cases that the operand constraints are not
1763 supposed to allow to happen. Abort if we get one,
1764 because generating code for these cases is painful. */
1766 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1769 /* If one operand is decrementing and one is incrementing
1770 decrement the former register explicitly
1771 and change that operand into ordinary indexing. */
1773 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1775 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1777 output_asm_insn ("sub%.l %#12,%0", operands
);
1779 output_asm_insn ("subq%.l %#8,%0", operands
);
1780 if (GET_MODE (operands
[1]) == XFmode
)
1781 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1782 else if (GET_MODE (operands
[0]) == DFmode
)
1783 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1785 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1788 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1790 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1792 output_asm_insn ("sub%.l %#12,%1", operands
);
1794 output_asm_insn ("subq%.l %#8,%1", operands
);
1795 if (GET_MODE (operands
[1]) == XFmode
)
1796 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1797 else if (GET_MODE (operands
[1]) == DFmode
)
1798 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1800 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1804 /* If an operand is an unoffsettable memory ref, find a register
1805 we can increment temporarily to make it refer to the second word. */
1807 if (optype0
== MEMOP
)
1808 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1810 if (optype1
== MEMOP
)
1811 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1813 /* Ok, we can do one word at a time.
1814 Normally we do the low-numbered word first,
1815 but if either operand is autodecrementing then we
1816 do the high-numbered word first.
1818 In either case, set up in LATEHALF the operands to use
1819 for the high-numbered word and in some cases alter the
1820 operands in OPERANDS to be suitable for the low-numbered word. */
1824 if (optype0
== REGOP
)
1826 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1827 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1829 else if (optype0
== OFFSOP
)
1831 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1832 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1836 middlehalf
[0] = operands
[0];
1837 latehalf
[0] = operands
[0];
1840 if (optype1
== REGOP
)
1842 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1843 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1845 else if (optype1
== OFFSOP
)
1847 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1848 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1850 else if (optype1
== CNSTOP
)
1852 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1857 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1858 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1859 operands
[1] = GEN_INT (l
[0]);
1860 middlehalf
[1] = GEN_INT (l
[1]);
1861 latehalf
[1] = GEN_INT (l
[2]);
1863 else if (CONSTANT_P (operands
[1]))
1865 /* actually, no non-CONST_DOUBLE constant should ever
1868 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1869 latehalf
[1] = constm1_rtx
;
1871 latehalf
[1] = const0_rtx
;
1876 middlehalf
[1] = operands
[1];
1877 latehalf
[1] = operands
[1];
1881 /* size is not 12: */
1883 if (optype0
== REGOP
)
1884 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1885 else if (optype0
== OFFSOP
)
1886 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1888 latehalf
[0] = operands
[0];
1890 if (optype1
== REGOP
)
1891 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1892 else if (optype1
== OFFSOP
)
1893 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1894 else if (optype1
== CNSTOP
)
1895 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1897 latehalf
[1] = operands
[1];
1900 /* If insn is effectively movd N(sp),-(sp) then we will do the
1901 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1902 for the low word as well, to compensate for the first decrement of sp. */
1903 if (optype0
== PUSHOP
1904 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1905 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1906 operands
[1] = middlehalf
[1] = latehalf
[1];
1908 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1909 if the upper part of reg N does not appear in the MEM, arrange to
1910 emit the move late-half first. Otherwise, compute the MEM address
1911 into the upper part of N and use that as a pointer to the memory
1913 if (optype0
== REGOP
1914 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1916 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1918 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1919 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1921 /* If both halves of dest are used in the src memory address,
1922 compute the address into latehalf of dest.
1923 Note that this can't happen if the dest is two data regs. */
1925 xops
[0] = latehalf
[0];
1926 xops
[1] = XEXP (operands
[1], 0);
1927 output_asm_insn ("lea %a1,%0", xops
);
1928 if( GET_MODE (operands
[1]) == XFmode
)
1930 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1931 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1932 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1936 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1937 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1941 && reg_overlap_mentioned_p (middlehalf
[0],
1942 XEXP (operands
[1], 0)))
1944 /* Check for two regs used by both source and dest.
1945 Note that this can't happen if the dest is all data regs.
1946 It can happen if the dest is d6, d7, a0.
1947 But in that case, latehalf is an addr reg, so
1948 the code at compadr does ok. */
1950 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1951 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1954 /* JRV says this can't happen: */
1955 if (addreg0
|| addreg1
)
1958 /* Only the middle reg conflicts; simply put it last. */
1959 output_asm_insn (singlemove_string (operands
), operands
);
1960 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1961 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1964 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1965 /* If the low half of dest is mentioned in the source memory
1966 address, the arrange to emit the move late half first. */
1967 dest_overlapped_low
= 1;
1970 /* If one or both operands autodecrementing,
1971 do the two words, high-numbered first. */
1973 /* Likewise, the first move would clobber the source of the second one,
1974 do them in the other order. This happens only for registers;
1975 such overlap can't happen in memory unless the user explicitly
1976 sets it up, and that is an undefined circumstance. */
1978 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1979 || (optype0
== REGOP
&& optype1
== REGOP
1980 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1981 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1982 || dest_overlapped_low
)
1984 /* Make any unoffsettable addresses point at high-numbered word. */
1988 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1990 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1995 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1997 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2001 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2003 /* Undo the adds we just did. */
2005 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2007 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2011 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2013 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2015 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2018 /* Do low-numbered word. */
2019 return singlemove_string (operands
);
2022 /* Normal case: do the two words, low-numbered first. */
2024 output_asm_insn (singlemove_string (operands
), operands
);
2026 /* Do the middle one of the three words for long double */
2030 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2032 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2034 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2037 /* Make any unoffsettable addresses point at high-numbered word. */
2039 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2041 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2044 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2046 /* Undo the adds we just did. */
2050 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2052 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2057 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2059 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2065 /* Return a REG that occurs in ADDR with coefficient 1.
2066 ADDR can be effectively incremented by incrementing REG. */
2069 find_addr_reg (addr
)
2072 while (GET_CODE (addr
) == PLUS
)
2074 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2075 addr
= XEXP (addr
, 0);
2076 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2077 addr
= XEXP (addr
, 1);
2078 else if (CONSTANT_P (XEXP (addr
, 0)))
2079 addr
= XEXP (addr
, 1);
2080 else if (CONSTANT_P (XEXP (addr
, 1)))
2081 addr
= XEXP (addr
, 0);
2085 if (GET_CODE (addr
) == REG
)
2090 /* Output assembler code to perform a 32 bit 3 operand add. */
2093 output_addsi3 (operands
)
2096 if (! operands_match_p (operands
[0], operands
[1]))
2098 if (!ADDRESS_REG_P (operands
[1]))
2100 rtx tmp
= operands
[1];
2102 operands
[1] = operands
[2];
2106 /* These insns can result from reloads to access
2107 stack slots over 64k from the frame pointer. */
2108 if (GET_CODE (operands
[2]) == CONST_INT
2109 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2110 return "move%.l %2,%0\n\tadd%.l %1,%0";
2112 if (GET_CODE (operands
[2]) == REG
)
2113 return "lea 0(%1,%2.l),%0";
2115 return "lea %c2(%1),%0";
2118 if (GET_CODE (operands
[2]) == REG
)
2119 return "lea (%1,%2.l),%0";
2121 return "lea (%c2,%1),%0";
2122 #else /* not MOTOROLA (MIT syntax) */
2123 if (GET_CODE (operands
[2]) == REG
)
2124 return "lea %1@(0,%2:l),%0";
2126 return "lea %1@(%c2),%0";
2127 #endif /* not MOTOROLA */
2128 #endif /* not SGS */
2130 if (GET_CODE (operands
[2]) == CONST_INT
)
2133 if (INTVAL (operands
[2]) > 0
2134 && INTVAL (operands
[2]) <= 8)
2135 return "addq%.l %2,%0";
2136 if (INTVAL (operands
[2]) < 0
2137 && INTVAL (operands
[2]) >= -8)
2139 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2140 return "subq%.l %2,%0";
2142 /* On the CPU32 it is faster to use two addql instructions to
2143 add a small integer (8 < N <= 16) to a register.
2144 Likewise for subql. */
2145 if (TARGET_CPU32
&& REG_P (operands
[0]))
2147 if (INTVAL (operands
[2]) > 8
2148 && INTVAL (operands
[2]) <= 16)
2150 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2151 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2153 if (INTVAL (operands
[2]) < -8
2154 && INTVAL (operands
[2]) >= -16)
2156 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2157 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2161 if (ADDRESS_REG_P (operands
[0])
2162 && INTVAL (operands
[2]) >= -0x8000
2163 && INTVAL (operands
[2]) < 0x8000)
2166 return "add%.w %2,%0";
2169 return "lea (%c2,%0),%0";
2171 return "lea %0@(%c2),%0";
2175 return "add%.l %2,%0";
2178 /* Store in cc_status the expressions that the condition codes will
2179 describe after execution of an instruction whose pattern is EXP.
2180 Do not alter them if the instruction would not alter the cc's. */
2182 /* On the 68000, all the insns to store in an address register fail to
2183 set the cc's. However, in some cases these instructions can make it
2184 possibly invalid to use the saved cc's. In those cases we clear out
2185 some or all of the saved cc's so they won't be used. */
2188 notice_update_cc (exp
, insn
)
2192 /* If the cc is being set from the fpa and the expression is not an
2193 explicit floating point test instruction (which has code to deal with
2194 this), reinit the CC. */
2195 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2196 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2197 && !(GET_CODE (exp
) == PARALLEL
2198 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2199 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2203 else if (GET_CODE (exp
) == SET
)
2205 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2209 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2211 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2212 cc_status
.value1
= 0;
2213 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2214 cc_status
.value2
= 0;
2216 else if (!FP_REG_P (SET_DEST (exp
))
2217 && SET_DEST (exp
) != cc0_rtx
2218 && (FP_REG_P (SET_SRC (exp
))
2219 || GET_CODE (SET_SRC (exp
)) == FIX
2220 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2221 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2225 /* A pair of move insns doesn't produce a useful overall cc. */
2226 else if (!FP_REG_P (SET_DEST (exp
))
2227 && !FP_REG_P (SET_SRC (exp
))
2228 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2229 && (GET_CODE (SET_SRC (exp
)) == REG
2230 || GET_CODE (SET_SRC (exp
)) == MEM
2231 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2235 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2239 else if (XEXP (exp
, 0) != pc_rtx
)
2241 cc_status
.flags
= 0;
2242 cc_status
.value1
= XEXP (exp
, 0);
2243 cc_status
.value2
= XEXP (exp
, 1);
2246 else if (GET_CODE (exp
) == PARALLEL
2247 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2249 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2251 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2253 cc_status
.flags
= 0;
2254 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2255 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2260 if (cc_status
.value2
!= 0
2261 && ADDRESS_REG_P (cc_status
.value2
)
2262 && GET_MODE (cc_status
.value2
) == QImode
)
2264 if (cc_status
.value2
!= 0
2265 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2266 switch (GET_CODE (cc_status
.value2
))
2268 case PLUS
: case MINUS
: case MULT
:
2269 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2270 #if 0 /* These instructions always clear the overflow bit */
2271 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2272 case ROTATE
: case ROTATERT
:
2274 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2275 cc_status
.flags
|= CC_NO_OVERFLOW
;
2278 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2279 ends with a move insn moving r2 in r2's mode.
2280 Thus, the cc's are set for r2.
2281 This can set N bit spuriously. */
2282 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2287 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2289 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2290 cc_status
.value2
= 0;
2291 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2292 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2293 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2294 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2295 cc_status
.flags
= CC_IN_68881
;
2299 output_move_const_double (operands
)
2302 #ifdef SUPPORT_SUN_FPA
2303 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2305 int code
= standard_sun_fpa_constant_p (operands
[1]);
2309 static char buf
[40];
2311 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2314 return "fpmove%.d %1,%0";
2319 int code
= standard_68881_constant_p (operands
[1]);
2323 static char buf
[40];
2325 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2328 return "fmove%.d %1,%0";
2333 output_move_const_single (operands
)
2336 #ifdef SUPPORT_SUN_FPA
2339 int code
= standard_sun_fpa_constant_p (operands
[1]);
2343 static char buf
[40];
2345 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2348 return "fpmove%.s %1,%0";
2351 #endif /* defined SUPPORT_SUN_FPA */
2353 int code
= standard_68881_constant_p (operands
[1]);
2357 static char buf
[40];
2359 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2362 return "fmove%.s %f1,%0";
2366 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2367 from the "fmovecr" instruction.
2368 The value, anded with 0xff, gives the code to use in fmovecr
2369 to get the desired constant. */
2371 /* This code has been fixed for cross-compilation. */
2373 static int inited_68881_table
= 0;
2375 char *strings_68881
[7] = {
2385 int codes_68881
[7] = {
2395 REAL_VALUE_TYPE values_68881
[7];
2397 /* Set up values_68881 array by converting the decimal values
2398 strings_68881 to binary. */
2405 enum machine_mode mode
;
2408 for (i
= 0; i
< 7; i
++)
2412 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2413 values_68881
[i
] = r
;
2415 inited_68881_table
= 1;
2419 standard_68881_constant_p (x
)
2425 #ifdef NO_ASM_FMOVECR
2429 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2430 used at all on those chips. */
2431 if (TARGET_68040
|| TARGET_68060
)
2434 #ifndef REAL_ARITHMETIC
2435 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2436 if (! flag_pretend_float
)
2441 if (! inited_68881_table
)
2442 init_68881_table ();
2444 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2446 for (i
= 0; i
< 6; i
++)
2448 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2449 return (codes_68881
[i
]);
2452 if (GET_MODE (x
) == SFmode
)
2455 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2456 return (codes_68881
[6]);
2458 /* larger powers of ten in the constants ram are not used
2459 because they are not equal to a `double' C constant. */
2463 /* If X is a floating-point constant, return the logarithm of X base 2,
2464 or 0 if X is not a power of 2. */
2467 floating_exact_log2 (x
)
2470 REAL_VALUE_TYPE r
, r1
;
2473 #ifndef REAL_ARITHMETIC
2474 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2475 if (! flag_pretend_float
)
2480 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2482 if (REAL_VALUES_LESS (r
, dconst0
))
2487 while (REAL_VALUES_LESS (r1
, r
))
2489 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2490 if (REAL_VALUES_EQUAL (r1
, r
))
2497 #ifdef SUPPORT_SUN_FPA
2498 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2499 from the Sun FPA's constant RAM.
2500 The value returned, anded with 0x1ff, gives the code to use in fpmove
2501 to get the desired constant. */
2503 static int inited_FPA_table
= 0;
2505 char *strings_FPA
[38] = {
2506 /* small rationals */
2519 /* Decimal equivalents of double precision values */
2520 "2.718281828459045091", /* D_E */
2521 "6.283185307179586477", /* 2 pi */
2522 "3.141592653589793116", /* D_PI */
2523 "1.570796326794896619", /* pi/2 */
2524 "1.414213562373095145", /* D_SQRT2 */
2525 "0.7071067811865475244", /* 1/sqrt(2) */
2526 "-1.570796326794896619", /* -pi/2 */
2527 "1.442695040888963387", /* D_LOG2ofE */
2528 "3.321928024887362182", /* D_LOG2of10 */
2529 "0.6931471805599452862", /* D_LOGEof2 */
2530 "2.302585092994045901", /* D_LOGEof10 */
2531 "0.3010299956639811980", /* D_LOG10of2 */
2532 "0.4342944819032518167", /* D_LOG10ofE */
2533 /* Decimal equivalents of single precision values */
2534 "2.718281745910644531", /* S_E */
2535 "6.283185307179586477", /* 2 pi */
2536 "3.141592741012573242", /* S_PI */
2537 "1.570796326794896619", /* pi/2 */
2538 "1.414213538169860840", /* S_SQRT2 */
2539 "0.7071067811865475244", /* 1/sqrt(2) */
2540 "-1.570796326794896619", /* -pi/2 */
2541 "1.442695021629333496", /* S_LOG2ofE */
2542 "3.321928024291992188", /* S_LOG2of10 */
2543 "0.6931471824645996094", /* S_LOGEof2 */
2544 "2.302585124969482442", /* S_LOGEof10 */
2545 "0.3010300099849700928", /* S_LOG10of2 */
2546 "0.4342944920063018799", /* S_LOG10ofE */
2550 int codes_FPA
[38] = {
2551 /* small rationals */
2564 /* double precision */
2578 /* single precision */
2594 REAL_VALUE_TYPE values_FPA
[38];
2596 /* This code has been fixed for cross-compilation. */
2601 enum machine_mode mode
;
2606 for (i
= 0; i
< 38; i
++)
2610 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2613 inited_FPA_table
= 1;
2618 standard_sun_fpa_constant_p (x
)
2624 #ifndef REAL_ARITHMETIC
2625 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2626 if (! flag_pretend_float
)
2631 if (! inited_FPA_table
)
2634 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2636 for (i
=0; i
<12; i
++)
2638 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2639 return (codes_FPA
[i
]);
2642 if (GET_MODE (x
) == SFmode
)
2644 for (i
=25; i
<38; i
++)
2646 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2647 return (codes_FPA
[i
]);
2652 for (i
=12; i
<25; i
++)
2654 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2655 return (codes_FPA
[i
]);
2660 #endif /* define SUPPORT_SUN_FPA */
2662 /* A C compound statement to output to stdio stream STREAM the
2663 assembler syntax for an instruction operand X. X is an RTL
2666 CODE is a value that can be used to specify one of several ways
2667 of printing the operand. It is used when identical operands
2668 must be printed differently depending on the context. CODE
2669 comes from the `%' specification that was used to request
2670 printing of the operand. If the specification was just `%DIGIT'
2671 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2672 is the ASCII code for LTR.
2674 If X is a register, this macro should print the register's name.
2675 The names can be found in an array `reg_names' whose type is
2676 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2678 When the machine description has a specification `%PUNCT' (a `%'
2679 followed by a punctuation character), this macro is called with
2680 a null pointer for X and the punctuation character for CODE.
2682 The m68k specific codes are:
2684 '.' for dot needed in Motorola-style opcode names.
2685 '-' for an operand pushing on the stack:
2686 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2687 '+' for an operand pushing on the stack:
2688 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2689 '@' for a reference to the top word on the stack:
2690 sp@, (sp) or (%sp) depending on the style of syntax.
2691 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2692 but & in SGS syntax, $ in CRDS/UNOS syntax).
2693 '!' for the cc register (used in an `and to cc' insn).
2694 '$' for the letter `s' in an op code, but only on the 68040.
2695 '&' for the letter `d' in an op code, but only on the 68040.
2696 '/' for register prefix needed by longlong.h.
2698 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2699 'd' to force memory addressing to be absolute, not relative.
2700 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2701 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2702 than directly). Second part of 'y' below.
2703 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2704 or print pair of registers as rx:ry.
2705 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2706 CONST_DOUBLE's as SunFPA constant RAM registers if
2707 possible, so it should not be used except for the SunFPA.
2712 print_operand (file
, op
, letter
)
2713 FILE *file
; /* file to write to */
2714 rtx op
; /* operand to print */
2715 int letter
; /* %<letter> or 0 */
2717 #ifdef SUPPORT_SUN_FPA
2723 #if defined (MOTOROLA) && !defined (CRDS)
2724 asm_fprintf (file
, ".");
2727 else if (letter
== '#')
2729 asm_fprintf (file
, "%0I");
2731 else if (letter
== '-')
2734 asm_fprintf (file
, "-(%Rsp)");
2736 asm_fprintf (file
, "%Rsp@-");
2739 else if (letter
== '+')
2742 asm_fprintf (file
, "(%Rsp)+");
2744 asm_fprintf (file
, "%Rsp@+");
2747 else if (letter
== '@')
2750 asm_fprintf (file
, "(%Rsp)");
2752 asm_fprintf (file
, "%Rsp@");
2755 else if (letter
== '!')
2757 asm_fprintf (file
, "%Rfpcr");
2759 else if (letter
== '$')
2761 if (TARGET_68040_ONLY
)
2763 fprintf (file
, "s");
2766 else if (letter
== '&')
2768 if (TARGET_68040_ONLY
)
2770 fprintf (file
, "d");
2773 else if (letter
== '/')
2775 asm_fprintf (file
, "%R");
2777 else if (GET_CODE (op
) == REG
)
2779 #ifdef SUPPORT_SUN_FPA
2781 && (letter
== 'y' || letter
== 'x')
2782 && GET_MODE (op
) == DFmode
)
2784 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2785 reg_names
[REGNO (op
)+1]);
2791 /* Print out the second register name of a register pair.
2792 I.e., R (6) => 7. */
2793 fputs (reg_names
[REGNO (op
) + 1], file
);
2795 fputs (reg_names
[REGNO (op
)], file
);
2798 else if (GET_CODE (op
) == MEM
)
2800 output_address (XEXP (op
, 0));
2801 if (letter
== 'd' && ! TARGET_68020
2802 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2803 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2804 && INTVAL (XEXP (op
, 0)) < 0x8000
2805 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2808 fprintf (file
, ".l");
2810 fprintf (file
, ":l");
2814 #ifdef SUPPORT_SUN_FPA
2815 else if ((letter
== 'y' || letter
== 'w')
2816 && GET_CODE (op
) == CONST_DOUBLE
2817 && (i
= standard_sun_fpa_constant_p (op
)))
2819 fprintf (file
, "%%%d", i
& 0x1ff);
2822 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2825 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2826 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2828 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2831 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2832 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2834 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2837 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2838 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2842 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2847 /* A C compound statement to output to stdio stream STREAM the
2848 assembler syntax for an instruction operand that is a memory
2849 reference whose address is ADDR. ADDR is an RTL expression.
2851 Note that this contains a kludge that knows that the only reason
2852 we have an address (plus (label_ref...) (reg...)) when not generating
2853 PIC code is in the insn before a tablejump, and we know that m68k.md
2854 generates a label LInnn: on such an insn.
2856 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2857 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2859 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2860 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2861 we want. This difference can be accommodated by using an assembler
2862 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2863 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2864 macro. See m68k/sgs.h for an example; for versions without the bug.
2865 Some assemblers refuse all the above solutions. The workaround is to
2866 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2869 They also do not like things like "pea 1.w", so we simple leave off
2870 the .w on small constants.
2872 This routine is responsible for distinguishing between -fpic and -fPIC
2873 style relocations in an address. When generating -fpic code the
2874 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2875 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2877 #ifndef ASM_OUTPUT_CASE_FETCH
2880 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2881 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2883 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2884 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2887 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2888 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2890 #endif /* ASM_OUTPUT_CASE_FETCH */
2893 print_operand_address (file
, addr
)
2897 register rtx reg1
, reg2
, breg
, ireg
;
2900 switch (GET_CODE (addr
))
2904 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2906 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2911 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2913 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2918 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2920 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2924 reg1
= reg2
= ireg
= breg
= offset
= 0;
2925 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2927 offset
= XEXP (addr
, 0);
2928 addr
= XEXP (addr
, 1);
2930 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2932 offset
= XEXP (addr
, 1);
2933 addr
= XEXP (addr
, 0);
2935 if (GET_CODE (addr
) != PLUS
)
2939 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2941 reg1
= XEXP (addr
, 0);
2942 addr
= XEXP (addr
, 1);
2944 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2946 reg1
= XEXP (addr
, 1);
2947 addr
= XEXP (addr
, 0);
2949 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2951 reg1
= XEXP (addr
, 0);
2952 addr
= XEXP (addr
, 1);
2954 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2956 reg1
= XEXP (addr
, 1);
2957 addr
= XEXP (addr
, 0);
2959 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2961 reg1
= XEXP (addr
, 0);
2962 addr
= XEXP (addr
, 1);
2964 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2966 reg1
= XEXP (addr
, 1);
2967 addr
= XEXP (addr
, 0);
2969 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2970 || GET_CODE (addr
) == SIGN_EXTEND
)
2982 #if 0 /* for OLD_INDEXING */
2983 else if (GET_CODE (addr
) == PLUS
)
2985 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2987 reg2
= XEXP (addr
, 0);
2988 addr
= XEXP (addr
, 1);
2990 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2992 reg2
= XEXP (addr
, 1);
2993 addr
= XEXP (addr
, 0);
3005 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3006 || GET_CODE (reg1
) == MULT
))
3007 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3012 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3017 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3018 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3021 if (GET_CODE (ireg
) == MULT
)
3023 scale
= INTVAL (XEXP (ireg
, 1));
3024 ireg
= XEXP (ireg
, 0);
3026 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3028 ASM_OUTPUT_CASE_FETCH (file
,
3029 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3030 reg_names
[REGNO (XEXP (ireg
, 0))]);
3031 fprintf (file
, "w");
3035 ASM_OUTPUT_CASE_FETCH (file
,
3036 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3037 reg_names
[REGNO (ireg
)]);
3038 fprintf (file
, "l");
3043 fprintf (file
, "*%d", scale
);
3045 fprintf (file
, ":%d", scale
);
3051 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3052 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3054 ASM_OUTPUT_CASE_FETCH (file
,
3055 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3056 reg_names
[REGNO (breg
)]);
3057 fprintf (file
, "l)");
3060 if (ireg
!= 0 || breg
!= 0)
3067 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3074 output_addr_const (file
, addr
);
3075 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3077 fprintf (file
, "@GOT");
3079 fprintf (file
, ".w");
3082 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3088 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3091 output_addr_const (file
, addr
);
3092 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3093 fprintf (file
, ":w");
3094 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3095 fprintf (file
, ":l");
3097 if (addr
!= 0 && ireg
!= 0)
3102 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3104 scale
= INTVAL (XEXP (ireg
, 1));
3105 ireg
= XEXP (ireg
, 0);
3107 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3110 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3112 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3118 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3120 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3126 fprintf (file
, "*%d", scale
);
3128 fprintf (file
, ":%d", scale
);
3134 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3135 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3137 ASM_OUTPUT_CASE_FETCH (file
,
3138 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3139 reg_names
[REGNO (reg1
)]);
3140 fprintf (file
, "l)");
3143 /* FALL-THROUGH (is this really what we want? */
3145 if (GET_CODE (addr
) == CONST_INT
3146 && INTVAL (addr
) < 0x8000
3147 && INTVAL (addr
) >= -0x8000)
3151 /* Many SGS assemblers croak on size specifiers for constants. */
3152 fprintf (file
, "%d", INTVAL (addr
));
3154 fprintf (file
, "%d.w", INTVAL (addr
));
3157 fprintf (file
, "%d:w", INTVAL (addr
));
3162 output_addr_const (file
, addr
);
3168 /* Check for cases where a clr insns can be omitted from code using
3169 strict_low_part sets. For example, the second clrl here is not needed:
3170 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3172 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3173 insn we are checking for redundancy. TARGET is the register set by the
3177 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3178 enum machine_mode mode
;
3184 p
= prev_nonnote_insn (first_insn
);
3188 /* If it isn't an insn, then give up. */
3189 if (GET_CODE (p
) != INSN
)
3192 if (reg_set_p (target
, p
))
3194 rtx set
= single_set (p
);
3197 /* If it isn't an easy to recognize insn, then give up. */
3201 dest
= SET_DEST (set
);
3203 /* If this sets the entire target register to zero, then our
3204 first_insn is redundant. */
3205 if (rtx_equal_p (dest
, target
)
3206 && SET_SRC (set
) == const0_rtx
)
3208 else if (GET_CODE (dest
) == STRICT_LOW_PART
3209 && GET_CODE (XEXP (dest
, 0)) == REG
3210 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3211 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3212 <= GET_MODE_SIZE (mode
)))
3213 /* This is a strict low part set which modifies less than
3214 we are using, so it is safe. */
3220 p
= prev_nonnote_insn (p
);
3227 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3228 range carefully since this predicate is used in DImode contexts. Also, we
3229 need some extra crud to make it work when hosted on 64-bit machines. */
3232 const_uint32_operand (op
, mode
)
3234 enum machine_mode mode
;
3236 if (GET_CODE (op
) == CONSTANT_P_RTX
)
3238 #if HOST_BITS_PER_WIDE_INT > 32
3239 /* All allowed constants will fit a CONST_INT. */
3240 return (GET_CODE (op
) == CONST_INT
3241 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3243 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3244 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3248 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3249 to check the range carefully since this predicate is used in DImode
3253 const_sint32_operand (op
, mode
)
3255 enum machine_mode mode
;
3257 if (GET_CODE (op
) == CONSTANT_P_RTX
)
3259 /* All allowed constants will fit a CONST_INT. */
3260 return (GET_CODE (op
) == CONST_INT
3261 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3265 output_andsi3 (operands
)
3269 if (GET_CODE (operands
[2]) == CONST_INT
3270 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3271 && (DATA_REG_P (operands
[0])
3272 || offsettable_memref_p (operands
[0]))
3275 if (GET_CODE (operands
[0]) != REG
)
3276 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3277 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3278 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3280 if (operands
[2] == const0_rtx
)
3282 return "and%.w %2,%0";
3284 if (GET_CODE (operands
[2]) == CONST_INT
3285 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3286 && (DATA_REG_P (operands
[0])
3287 || offsettable_memref_p (operands
[0])))
3289 if (DATA_REG_P (operands
[0]))
3291 operands
[1] = GEN_INT (logval
);
3295 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3296 operands
[1] = GEN_INT (logval
% 8);
3298 /* This does not set condition codes in a standard way. */
3300 return "bclr %1,%0";
3302 return "and%.l %2,%0";
3306 output_iorsi3 (operands
)
3309 register int logval
;
3310 if (GET_CODE (operands
[2]) == CONST_INT
3311 && INTVAL (operands
[2]) >> 16 == 0
3312 && (DATA_REG_P (operands
[0])
3313 || offsettable_memref_p (operands
[0]))
3316 if (GET_CODE (operands
[0]) != REG
)
3317 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3318 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3320 if (INTVAL (operands
[2]) == 0xffff)
3321 return "mov%.w %2,%0";
3322 return "or%.w %2,%0";
3324 if (GET_CODE (operands
[2]) == CONST_INT
3325 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3326 && (DATA_REG_P (operands
[0])
3327 || offsettable_memref_p (operands
[0])))
3329 if (DATA_REG_P (operands
[0]))
3331 operands
[1] = GEN_INT (logval
);
3335 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3336 operands
[1] = GEN_INT (logval
% 8);
3339 return "bset %1,%0";
3341 return "or%.l %2,%0";
3345 output_xorsi3 (operands
)
3348 register int logval
;
3349 if (GET_CODE (operands
[2]) == CONST_INT
3350 && INTVAL (operands
[2]) >> 16 == 0
3351 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3354 if (! DATA_REG_P (operands
[0]))
3355 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3356 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3358 if (INTVAL (operands
[2]) == 0xffff)
3360 return "eor%.w %2,%0";
3362 if (GET_CODE (operands
[2]) == CONST_INT
3363 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3364 && (DATA_REG_P (operands
[0])
3365 || offsettable_memref_p (operands
[0])))
3367 if (DATA_REG_P (operands
[0]))
3369 operands
[1] = GEN_INT (logval
);
3373 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3374 operands
[1] = GEN_INT (logval
% 8);
3377 return "bchg %1,%0";
3379 return "eor%.l %2,%0";