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m68k.c (use_return_insn): Return false if the pic register is in use.
[gcc.git] / gcc / config / m68k / m68k.c
1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
3
4 This file is part of GNU CC.
5
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "tree.h"
24 #include "rtl.h"
25 #include "function.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "real.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
32 #include "output.h"
33 #include "insn-attr.h"
34 #include "recog.h"
35 #include "toplev.h"
36
37 /* Needed for use_return_insn. */
38 #include "flags.h"
39
40 #ifdef SUPPORT_SUN_FPA
41
42 /* Index into this array by (register number >> 3) to find the
43 smallest class which contains that register. */
44 enum reg_class regno_reg_class[]
45 = { DATA_REGS, ADDR_REGS, FP_REGS,
46 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
47
48 #endif /* defined SUPPORT_SUN_FPA */
49
50 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
51 if SGS_SWITCH_TABLE. */
52 int switch_table_difference_label_flag;
53
54 static rtx find_addr_reg ();
55 rtx legitimize_pic_address ();
56 void print_operand_address ();
57 \f
58
59 /* Alignment to use for loops and jumps */
60 /* Specify power of two alignment used for loops. */
61 const char *m68k_align_loops_string;
62 /* Specify power of two alignment used for non-loop jumps. */
63 const char *m68k_align_jumps_string;
64 /* Specify power of two alignment used for functions. */
65 const char *m68k_align_funcs_string;
66
67 /* Specify power of two alignment used for loops. */
68 int m68k_align_loops;
69 /* Specify power of two alignment used for non-loop jumps. */
70 int m68k_align_jumps;
71 /* Specify power of two alignment used for functions. */
72 int m68k_align_funcs;
73
74 /* Nonzero if the last compare/test insn had FP operands. The
75 sCC expanders peek at this to determine what to do for the
76 68060, which has no fsCC instructions. */
77 int m68k_last_compare_had_fp_operands;
78
79 /* Sometimes certain combinations of command options do not make
80 sense on a particular target machine. You can define a macro
81 `OVERRIDE_OPTIONS' to take account of this. This macro, if
82 defined, is executed once just after all the command options have
83 been parsed.
84
85 Don't use this macro to turn on various extra optimizations for
86 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
87
88 void
89 override_options ()
90 {
91 int def_align;
92
93 def_align = 1;
94
95 /* Validate -malign-loops= value, or provide default */
96 if (m68k_align_loops_string)
97 {
98 m68k_align_loops = atoi (m68k_align_loops_string);
99 if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
100 fatal ("-malign-loops=%d is not between 1 and %d",
101 m68k_align_loops, MAX_CODE_ALIGN);
102 }
103 else
104 m68k_align_loops = def_align;
105
106 /* Validate -malign-jumps= value, or provide default */
107 if (m68k_align_jumps_string)
108 {
109 m68k_align_jumps = atoi (m68k_align_jumps_string);
110 if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
111 fatal ("-malign-jumps=%d is not between 1 and %d",
112 m68k_align_jumps, MAX_CODE_ALIGN);
113 }
114 else
115 m68k_align_jumps = def_align;
116
117 /* Validate -malign-functions= value, or provide default */
118 if (m68k_align_funcs_string)
119 {
120 m68k_align_funcs = atoi (m68k_align_funcs_string);
121 if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
122 fatal ("-malign-functions=%d is not between 1 and %d",
123 m68k_align_funcs, MAX_CODE_ALIGN);
124 }
125 else
126 m68k_align_funcs = def_align;
127 }
128 \f
129 /* This function generates the assembly code for function entry.
130 STREAM is a stdio stream to output the code to.
131 SIZE is an int: how many units of temporary storage to allocate.
132 Refer to the array `regs_ever_live' to determine which registers
133 to save; `regs_ever_live[I]' is nonzero if register number I
134 is ever used in the function. This function is responsible for
135 knowing which registers should not be saved even if used. */
136
137
138 /* Note that the order of the bit mask for fmovem is the opposite
139 of the order for movem! */
140
141
142 void
143 output_function_prologue (stream, size)
144 FILE *stream;
145 int size;
146 {
147 register int regno;
148 register int mask = 0;
149 int num_saved_regs = 0;
150 extern char call_used_regs[];
151 int fsize = (size + 3) & -4;
152 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
153
154
155 if (frame_pointer_needed)
156 {
157 if (fsize == 0 && TARGET_68040)
158 {
159 /* on the 68040, pea + move is faster than link.w 0 */
160 #ifdef MOTOROLA
161 asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
162 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
163 reg_names[FRAME_POINTER_REGNUM]);
164 #else
165 asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
166 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
167 reg_names[FRAME_POINTER_REGNUM]);
168 #endif
169 }
170 else if (fsize < 0x8000)
171 {
172 #ifdef MOTOROLA
173 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
174 reg_names[FRAME_POINTER_REGNUM], -fsize);
175 #else
176 asm_fprintf (stream, "\tlink %s,%0I%d\n",
177 reg_names[FRAME_POINTER_REGNUM], -fsize);
178 #endif
179 }
180 else if (TARGET_68020)
181 {
182 #ifdef MOTOROLA
183 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
184 reg_names[FRAME_POINTER_REGNUM], -fsize);
185 #else
186 asm_fprintf (stream, "\tlink %s,%0I%d\n",
187 reg_names[FRAME_POINTER_REGNUM], -fsize);
188 #endif
189 }
190 else
191 {
192 /* Adding negative number is faster on the 68040. */
193 #ifdef MOTOROLA
194 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
195 reg_names[FRAME_POINTER_REGNUM], -fsize);
196 #else
197 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
198 reg_names[FRAME_POINTER_REGNUM], -fsize);
199 #endif
200 }
201 if (dwarf2out_do_frame ())
202 {
203 char *l;
204 l = (char *) dwarf2out_cfi_label ();
205 cfa_store_offset += 4;
206 cfa_offset = cfa_store_offset;
207 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
208 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
209 cfa_store_offset += fsize;
210 }
211 }
212 else if (fsize)
213 {
214 if (fsize + 4 < 0x8000)
215 {
216 #ifndef NO_ADDSUB_Q
217 if (fsize + 4 <= 8)
218 {
219 if (!TARGET_5200)
220 {
221 /* asm_fprintf() cannot handle %. */
222 #ifdef MOTOROLA
223 asm_fprintf (stream, "\tsubq.w %0I%d,%Rsp\n", fsize + 4);
224 #else
225 asm_fprintf (stream, "\tsubqw %0I%d,%Rsp\n", fsize + 4);
226 #endif
227 }
228 else
229 {
230 /* asm_fprintf() cannot handle %. */
231 #ifdef MOTOROLA
232 asm_fprintf (stream, "\tsubq.l %0I%d,%Rsp\n", fsize + 4);
233 #else
234 asm_fprintf (stream, "\tsubql %0I%d,%Rsp\n", fsize + 4);
235 #endif
236 }
237 }
238 else if (fsize + 4 <= 16 && TARGET_CPU32)
239 {
240 /* On the CPU32 it is faster to use two subqw instructions to
241 subtract a small integer (8 < N <= 16) to a register. */
242 /* asm_fprintf() cannot handle %. */
243 #ifdef MOTOROLA
244 asm_fprintf (stream, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
245 fsize + 4 - 8);
246 #else
247 asm_fprintf (stream, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
248 fsize + 4 - 8);
249 #endif
250 }
251 else
252 #endif /* not NO_ADDSUB_Q */
253 if (TARGET_68040)
254 {
255 /* Adding negative number is faster on the 68040. */
256 /* asm_fprintf() cannot handle %. */
257 #ifdef MOTOROLA
258 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
259 #else
260 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
261 #endif
262 }
263 else
264 {
265 #ifdef MOTOROLA
266 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
267 #else
268 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
269 #endif
270 }
271 }
272 else
273 {
274 /* asm_fprintf() cannot handle %. */
275 #ifdef MOTOROLA
276 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
277 #else
278 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
279 #endif
280 }
281 if (dwarf2out_do_frame ())
282 {
283 cfa_store_offset += fsize;
284 cfa_offset = cfa_store_offset;
285 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
286 }
287 }
288 #ifdef SUPPORT_SUN_FPA
289 for (regno = 24; regno < 56; regno++)
290 if (regs_ever_live[regno] && ! call_used_regs[regno])
291 {
292 #ifdef MOTOROLA
293 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
294 reg_names[regno]);
295 #else
296 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
297 reg_names[regno]);
298 #endif
299 if (dwarf2out_do_frame ())
300 {
301 char *l = dwarf2out_cfi_label ();
302
303 cfa_store_offset += 8;
304 if (! frame_pointer_needed)
305 {
306 cfa_offset = cfa_store_offset;
307 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
308 }
309 dwarf2out_reg_save (l, regno, -cfa_store_offset);
310 }
311 }
312 #endif
313 if (TARGET_68881)
314 {
315 for (regno = 16; regno < 24; regno++)
316 if (regs_ever_live[regno] && ! call_used_regs[regno])
317 {
318 mask |= 1 << (regno - 16);
319 num_saved_regs++;
320 }
321 if ((mask & 0xff) != 0)
322 {
323 #ifdef MOTOROLA
324 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
325 #else
326 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
327 #endif
328 if (dwarf2out_do_frame ())
329 {
330 char *l = (char *) dwarf2out_cfi_label ();
331 int n_regs;
332
333 cfa_store_offset += num_saved_regs * 12;
334 if (! frame_pointer_needed)
335 {
336 cfa_offset = cfa_store_offset;
337 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
338 }
339 for (regno = 16, n_regs = 0; regno < 24; regno++)
340 if (mask & (1 << (regno - 16)))
341 dwarf2out_reg_save (l, regno,
342 -cfa_store_offset + n_regs++ * 12);
343 }
344 }
345 mask = 0;
346 num_saved_regs = 0;
347 }
348 for (regno = 0; regno < 16; regno++)
349 if (regs_ever_live[regno] && ! call_used_regs[regno])
350 {
351 mask |= 1 << (15 - regno);
352 num_saved_regs++;
353 }
354 if (frame_pointer_needed)
355 {
356 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
357 num_saved_regs--;
358 }
359 if (flag_pic && current_function_uses_pic_offset_table)
360 {
361 mask |= 1 << (15 - PIC_OFFSET_TABLE_REGNUM);
362 num_saved_regs++;
363 }
364
365 #if NEED_PROBE
366 #ifdef MOTOROLA
367 #ifdef CRDS
368 asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
369 #else
370 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
371 #endif
372 #else
373 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
374 #endif
375 #endif
376
377 if (num_saved_regs <= 2)
378 {
379 /* Store each separately in the same order moveml uses.
380 Using two movel instructions instead of a single moveml
381 is about 15% faster for the 68020 and 68030 at no expense
382 in code size */
383
384 int i;
385
386 /* Undo the work from above. */
387 for (i = 0; i< 16; i++)
388 if (mask & (1 << i))
389 {
390 asm_fprintf (stream,
391 #ifdef MOTOROLA
392 "\t%Omove.l %s,-(%Rsp)\n",
393 #else
394 "\tmovel %s,%Rsp@-\n",
395 #endif
396 reg_names[15 - i]);
397 if (dwarf2out_do_frame ())
398 {
399 char *l = (char *) dwarf2out_cfi_label ();
400
401 cfa_store_offset += 4;
402 if (! frame_pointer_needed)
403 {
404 cfa_offset = cfa_store_offset;
405 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
406 }
407 dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
408 }
409 }
410 }
411 else if (mask)
412 {
413 if (TARGET_5200)
414 {
415 /* The coldfire does not support the predecrement form of the
416 movml instruction, so we must adjust the stack pointer and
417 then use the plain address register indirect mode. We also
418 have to invert the register save mask to use the new mode.
419
420 FIXME: if num_saved_regs was calculated earlier, we could
421 combine the stack pointer adjustment with any adjustment
422 done when the initial stack frame is created. This would
423 save an instruction */
424
425 int newmask = 0;
426 int i;
427
428 for (i = 0; i < 16; i++)
429 if (mask & (1 << i))
430 newmask |= (1 << (15-i));
431
432 #ifdef MOTOROLA
433 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
434 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
435 #else
436 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
437 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
438 #endif
439 }
440 else
441 {
442 #ifdef MOTOROLA
443 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
444 #else
445 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
446 #endif
447 }
448 if (dwarf2out_do_frame ())
449 {
450 char *l = (char *) dwarf2out_cfi_label ();
451 int n_regs;
452
453 cfa_store_offset += num_saved_regs * 4;
454 if (! frame_pointer_needed)
455 {
456 cfa_offset = cfa_store_offset;
457 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
458 }
459 for (regno = 0, n_regs = 0; regno < 16; regno++)
460 if (mask & (1 << (15 - regno)))
461 dwarf2out_reg_save (l, regno,
462 -cfa_store_offset + n_regs++ * 4);
463 }
464 }
465 if (flag_pic && current_function_uses_pic_offset_table)
466 {
467 #ifdef MOTOROLA
468 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
469 reg_names[PIC_OFFSET_TABLE_REGNUM]);
470 #else
471 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
472 reg_names[PIC_OFFSET_TABLE_REGNUM]);
473 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
474 reg_names[PIC_OFFSET_TABLE_REGNUM],
475 reg_names[PIC_OFFSET_TABLE_REGNUM]);
476 #endif
477 }
478 }
479 \f
480 /* Return true if this function's epilogue can be output as RTL. */
481
482 int
483 use_return_insn ()
484 {
485 int regno;
486
487 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
488 return 0;
489
490 /* Copied from output_function_epilogue (). We should probably create a
491 separate layout routine to perform the common work. */
492
493 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
494 if (regs_ever_live[regno] && ! call_used_regs[regno])
495 return 0;
496
497 if (flag_pic && current_function_uses_pic_offset_table)
498 return 0;
499
500 return 1;
501 }
502
503 /* This function generates the assembly code for function exit,
504 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
505
506 The function epilogue should not depend on the current stack pointer!
507 It should use the frame pointer only, if there is a frame pointer.
508 This is mandatory because of alloca; we also take advantage of it to
509 omit stack adjustments before returning. */
510
511 void
512 output_function_epilogue (stream, size)
513 FILE *stream;
514 int size;
515 {
516 register int regno;
517 register int mask, fmask;
518 register int nregs;
519 int offset, foffset, fpoffset;
520 extern char call_used_regs[];
521 int fsize = (size + 3) & -4;
522 int big = 0;
523 rtx insn = get_last_insn ();
524 int restore_from_sp = 0;
525
526 /* If the last insn was a BARRIER, we don't have to write any code. */
527 if (GET_CODE (insn) == NOTE)
528 insn = prev_nonnote_insn (insn);
529 if (insn && GET_CODE (insn) == BARRIER)
530 {
531 /* Output just a no-op so that debuggers don't get confused
532 about which function the pc is in at this address. */
533 asm_fprintf (stream, "\tnop\n");
534 return;
535 }
536
537 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
538 if (profile_block_flag == 2)
539 {
540 FUNCTION_BLOCK_PROFILER_EXIT (stream);
541 }
542 #endif
543
544 #ifdef FUNCTION_EXTRA_EPILOGUE
545 FUNCTION_EXTRA_EPILOGUE (stream, size);
546 #endif
547 nregs = 0; fmask = 0; fpoffset = 0;
548 #ifdef SUPPORT_SUN_FPA
549 for (regno = 24 ; regno < 56 ; regno++)
550 if (regs_ever_live[regno] && ! call_used_regs[regno])
551 nregs++;
552 fpoffset = nregs * 8;
553 #endif
554 nregs = 0;
555 if (TARGET_68881)
556 {
557 for (regno = 16; regno < 24; regno++)
558 if (regs_ever_live[regno] && ! call_used_regs[regno])
559 {
560 nregs++;
561 fmask |= 1 << (23 - regno);
562 }
563 }
564 foffset = fpoffset + nregs * 12;
565 nregs = 0; mask = 0;
566 if (frame_pointer_needed)
567 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
568 for (regno = 0; regno < 16; regno++)
569 if (regs_ever_live[regno] && ! call_used_regs[regno])
570 {
571 nregs++;
572 mask |= 1 << regno;
573 }
574 if (flag_pic && current_function_uses_pic_offset_table)
575 {
576 nregs++;
577 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
578 }
579 offset = foffset + nregs * 4;
580 /* FIXME : leaf_function_p below is too strong.
581 What we really need to know there is if there could be pending
582 stack adjustment needed at that point. */
583 restore_from_sp = ! frame_pointer_needed
584 || (! current_function_calls_alloca && leaf_function_p ());
585 if (offset + fsize >= 0x8000
586 && ! restore_from_sp
587 && (mask || fmask || fpoffset))
588 {
589 #ifdef MOTOROLA
590 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
591 #else
592 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
593 #endif
594 fsize = 0, big = 1;
595 }
596 if (TARGET_5200 || nregs <= 2)
597 {
598 /* Restore each separately in the same order moveml does.
599 Using two movel instructions instead of a single moveml
600 is about 15% faster for the 68020 and 68030 at no expense
601 in code size. */
602
603 int i;
604
605 /* Undo the work from above. */
606 for (i = 0; i< 16; i++)
607 if (mask & (1 << i))
608 {
609 if (big)
610 {
611 #ifdef MOTOROLA
612 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
613 offset + fsize,
614 reg_names[FRAME_POINTER_REGNUM],
615 reg_names[i]);
616 #else
617 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
618 reg_names[FRAME_POINTER_REGNUM],
619 offset + fsize, reg_names[i]);
620 #endif
621 }
622 else if (restore_from_sp)
623 {
624 #ifdef MOTOROLA
625 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
626 reg_names[i]);
627 #else
628 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
629 reg_names[i]);
630 #endif
631 }
632 else
633 {
634 #ifdef MOTOROLA
635 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
636 offset + fsize,
637 reg_names[FRAME_POINTER_REGNUM],
638 reg_names[i]);
639 #else
640 asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
641 reg_names[FRAME_POINTER_REGNUM],
642 offset + fsize, reg_names[i]);
643 #endif
644 }
645 offset = offset - 4;
646 }
647 }
648 else if (mask)
649 {
650 if (big)
651 {
652 #ifdef MOTOROLA
653 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
654 offset + fsize,
655 reg_names[FRAME_POINTER_REGNUM],
656 mask);
657 #else
658 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
659 reg_names[FRAME_POINTER_REGNUM],
660 offset + fsize, mask);
661 #endif
662 }
663 else if (restore_from_sp)
664 {
665 #ifdef MOTOROLA
666 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
667 #else
668 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
669 #endif
670 }
671 else
672 {
673 #ifdef MOTOROLA
674 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
675 offset + fsize,
676 reg_names[FRAME_POINTER_REGNUM],
677 mask);
678 #else
679 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
680 reg_names[FRAME_POINTER_REGNUM],
681 offset + fsize, mask);
682 #endif
683 }
684 }
685 if (fmask)
686 {
687 if (big)
688 {
689 #ifdef MOTOROLA
690 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
691 foffset + fsize,
692 reg_names[FRAME_POINTER_REGNUM],
693 fmask);
694 #else
695 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
696 reg_names[FRAME_POINTER_REGNUM],
697 foffset + fsize, fmask);
698 #endif
699 }
700 else if (restore_from_sp)
701 {
702 #ifdef MOTOROLA
703 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
704 #else
705 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
706 #endif
707 }
708 else
709 {
710 #ifdef MOTOROLA
711 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
712 foffset + fsize,
713 reg_names[FRAME_POINTER_REGNUM],
714 fmask);
715 #else
716 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
717 reg_names[FRAME_POINTER_REGNUM],
718 foffset + fsize, fmask);
719 #endif
720 }
721 }
722 if (fpoffset != 0)
723 for (regno = 55; regno >= 24; regno--)
724 if (regs_ever_live[regno] && ! call_used_regs[regno])
725 {
726 if (big)
727 {
728 #ifdef MOTOROLA
729 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
730 fpoffset + fsize,
731 reg_names[FRAME_POINTER_REGNUM],
732 reg_names[regno]);
733 #else
734 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
735 reg_names[FRAME_POINTER_REGNUM],
736 fpoffset + fsize, reg_names[regno]);
737 #endif
738 }
739 else if (restore_from_sp)
740 {
741 #ifdef MOTOROLA
742 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
743 reg_names[regno]);
744 #else
745 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
746 reg_names[regno]);
747 #endif
748 }
749 else
750 {
751 #ifdef MOTOROLA
752 asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
753 fpoffset + fsize,
754 reg_names[FRAME_POINTER_REGNUM],
755 reg_names[regno]);
756 #else
757 asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
758 reg_names[FRAME_POINTER_REGNUM],
759 fpoffset + fsize, reg_names[regno]);
760 #endif
761 }
762 fpoffset -= 8;
763 }
764 if (frame_pointer_needed)
765 fprintf (stream, "\tunlk %s\n",
766 reg_names[FRAME_POINTER_REGNUM]);
767 else if (fsize)
768 {
769 #ifndef NO_ADDSUB_Q
770 if (fsize + 4 <= 8)
771 {
772 if (!TARGET_5200)
773 {
774 #ifdef MOTOROLA
775 asm_fprintf (stream, "\taddq.w %0I%d,%Rsp\n", fsize + 4);
776 #else
777 asm_fprintf (stream, "\taddqw %0I%d,%Rsp\n", fsize + 4);
778 #endif
779 }
780 else
781 {
782 #ifdef MOTOROLA
783 asm_fprintf (stream, "\taddq.l %0I%d,%Rsp\n", fsize + 4);
784 #else
785 asm_fprintf (stream, "\taddql %0I%d,%Rsp\n", fsize + 4);
786 #endif
787 }
788 }
789 else if (fsize + 4 <= 16 && TARGET_CPU32)
790 {
791 /* On the CPU32 it is faster to use two addqw instructions to
792 add a small integer (8 < N <= 16) to a register. */
793 /* asm_fprintf() cannot handle %. */
794 #ifdef MOTOROLA
795 asm_fprintf (stream, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
796 fsize + 4 - 8);
797 #else
798 asm_fprintf (stream, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
799 fsize + 4 - 8);
800 #endif
801 }
802 else
803 #endif /* not NO_ADDSUB_Q */
804 if (fsize + 4 < 0x8000)
805 {
806 if (TARGET_68040)
807 {
808 /* asm_fprintf() cannot handle %. */
809 #ifdef MOTOROLA
810 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
811 #else
812 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
813 #endif
814 }
815 else
816 {
817 #ifdef MOTOROLA
818 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
819 #else
820 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
821 #endif
822 }
823 }
824 else
825 {
826 /* asm_fprintf() cannot handle %. */
827 #ifdef MOTOROLA
828 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
829 #else
830 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
831 #endif
832 }
833 }
834 if (current_function_pops_args)
835 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
836 else
837 fprintf (stream, "\trts\n");
838 }
839 \f
840 /* Similar to general_operand, but exclude stack_pointer_rtx. */
841
842 int
843 not_sp_operand (op, mode)
844 register rtx op;
845 enum machine_mode mode;
846 {
847 return op != stack_pointer_rtx && general_operand (op, mode);
848 }
849
850 /* Return TRUE if X is a valid comparison operator for the dbcc
851 instruction.
852
853 Note it rejects floating point comparison operators.
854 (In the future we could use Fdbcc).
855
856 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
857
858 int
859 valid_dbcc_comparison_p (x, mode)
860 rtx x;
861 enum machine_mode mode ATTRIBUTE_UNUSED;
862 {
863 switch (GET_CODE (x))
864 {
865 case EQ: case NE: case GTU: case LTU:
866 case GEU: case LEU:
867 return 1;
868
869 /* Reject some when CC_NO_OVERFLOW is set. This may be over
870 conservative */
871 case GT: case LT: case GE: case LE:
872 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
873 default:
874 return 0;
875 }
876 }
877
878 /* Return non-zero if flags are currently in the 68881 flag register. */
879 int
880 flags_in_68881 ()
881 {
882 /* We could add support for these in the future */
883 return cc_status.flags & CC_IN_68881;
884 }
885
886 /* Output a dbCC; jCC sequence. Note we do not handle the
887 floating point version of this sequence (Fdbcc). We also
888 do not handle alternative conditions when CC_NO_OVERFLOW is
889 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
890 kick those out before we get here. */
891
892 void
893 output_dbcc_and_branch (operands)
894 rtx *operands;
895 {
896 switch (GET_CODE (operands[3]))
897 {
898 case EQ:
899 #ifdef MOTOROLA
900 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
901 #else
902 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
903 #endif
904 break;
905
906 case NE:
907 #ifdef MOTOROLA
908 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
909 #else
910 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
911 #endif
912 break;
913
914 case GT:
915 #ifdef MOTOROLA
916 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
917 #else
918 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
919 #endif
920 break;
921
922 case GTU:
923 #ifdef MOTOROLA
924 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
925 #else
926 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
927 #endif
928 break;
929
930 case LT:
931 #ifdef MOTOROLA
932 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
933 #else
934 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
935 #endif
936 break;
937
938 case LTU:
939 #ifdef MOTOROLA
940 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
941 #else
942 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
943 #endif
944 break;
945
946 case GE:
947 #ifdef MOTOROLA
948 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
949 #else
950 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
951 #endif
952 break;
953
954 case GEU:
955 #ifdef MOTOROLA
956 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
957 #else
958 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
959 #endif
960 break;
961
962 case LE:
963 #ifdef MOTOROLA
964 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
965 #else
966 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
967 #endif
968 break;
969
970 case LEU:
971 #ifdef MOTOROLA
972 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
973 #else
974 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
975 #endif
976 break;
977
978 default:
979 abort ();
980 }
981
982 /* If the decrement is to be done in SImode, then we have
983 to compensate for the fact that dbcc decrements in HImode. */
984 switch (GET_MODE (operands[0]))
985 {
986 case SImode:
987 #ifdef MOTOROLA
988 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
989 #else
990 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
991 #endif
992 break;
993
994 case HImode:
995 break;
996
997 default:
998 abort ();
999 }
1000 }
1001
1002 char *
1003 output_scc_di(op, operand1, operand2, dest)
1004 rtx op;
1005 rtx operand1;
1006 rtx operand2;
1007 rtx dest;
1008 {
1009 rtx loperands[7];
1010 enum rtx_code op_code = GET_CODE (op);
1011
1012 /* This does not produce a usefull cc. */
1013 CC_STATUS_INIT;
1014
1015 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1016 below. Swap the operands and change the op if these requirements
1017 are not fulfilled. */
1018 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1019 {
1020 rtx tmp = operand1;
1021
1022 operand1 = operand2;
1023 operand2 = tmp;
1024 op_code = swap_condition (op_code);
1025 }
1026 loperands[0] = operand1;
1027 if (GET_CODE (operand1) == REG)
1028 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1029 else
1030 loperands[1] = adj_offsettable_operand (operand1, 4);
1031 if (operand2 != const0_rtx)
1032 {
1033 loperands[2] = operand2;
1034 if (GET_CODE (operand2) == REG)
1035 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1036 else
1037 loperands[3] = adj_offsettable_operand (operand2, 4);
1038 }
1039 loperands[4] = gen_label_rtx();
1040 if (operand2 != const0_rtx)
1041 {
1042 #ifdef MOTOROLA
1043 #ifdef SGS_CMP_ORDER
1044 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
1045 #else
1046 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
1047 #endif
1048 #else
1049 #ifdef SGS_CMP_ORDER
1050 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
1051 #else
1052 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1053 #endif
1054 #endif
1055 }
1056 else
1057 {
1058 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0]))
1059 output_asm_insn ("tst%.l %0", loperands);
1060 else
1061 {
1062 #ifdef SGS_CMP_ORDER
1063 output_asm_insn ("cmp%.w %0,%#0", loperands);
1064 #else
1065 output_asm_insn ("cmp%.w %#0,%0", loperands);
1066 #endif
1067 }
1068
1069 #ifdef MOTOROLA
1070 output_asm_insn ("jbne %l4", loperands);
1071 #else
1072 output_asm_insn ("jne %l4", loperands);
1073 #endif
1074
1075 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1]))
1076 output_asm_insn ("tst%.l %1", loperands);
1077 else
1078 {
1079 #ifdef SGS_CMP_ORDER
1080 output_asm_insn ("cmp%.w %1,%#0", loperands);
1081 #else
1082 output_asm_insn ("cmp%.w %#0,%1", loperands);
1083 #endif
1084 }
1085 }
1086
1087 loperands[5] = dest;
1088
1089 switch (op_code)
1090 {
1091 case EQ:
1092 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1093 CODE_LABEL_NUMBER (loperands[4]));
1094 output_asm_insn ("seq %5", loperands);
1095 break;
1096
1097 case NE:
1098 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1099 CODE_LABEL_NUMBER (loperands[4]));
1100 output_asm_insn ("sne %5", loperands);
1101 break;
1102
1103 case GT:
1104 loperands[6] = gen_label_rtx();
1105 #ifdef MOTOROLA
1106 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1107 #else
1108 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1109 #endif
1110 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1111 CODE_LABEL_NUMBER (loperands[4]));
1112 output_asm_insn ("sgt %5", loperands);
1113 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1114 CODE_LABEL_NUMBER (loperands[6]));
1115 break;
1116
1117 case GTU:
1118 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1119 CODE_LABEL_NUMBER (loperands[4]));
1120 output_asm_insn ("shi %5", loperands);
1121 break;
1122
1123 case LT:
1124 loperands[6] = gen_label_rtx();
1125 #ifdef MOTOROLA
1126 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1127 #else
1128 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1129 #endif
1130 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1131 CODE_LABEL_NUMBER (loperands[4]));
1132 output_asm_insn ("slt %5", loperands);
1133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1134 CODE_LABEL_NUMBER (loperands[6]));
1135 break;
1136
1137 case LTU:
1138 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1139 CODE_LABEL_NUMBER (loperands[4]));
1140 output_asm_insn ("scs %5", loperands);
1141 break;
1142
1143 case GE:
1144 loperands[6] = gen_label_rtx();
1145 #ifdef MOTOROLA
1146 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1147 #else
1148 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1149 #endif
1150 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1151 CODE_LABEL_NUMBER (loperands[4]));
1152 output_asm_insn ("sge %5", loperands);
1153 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1154 CODE_LABEL_NUMBER (loperands[6]));
1155 break;
1156
1157 case GEU:
1158 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1159 CODE_LABEL_NUMBER (loperands[4]));
1160 output_asm_insn ("scc %5", loperands);
1161 break;
1162
1163 case LE:
1164 loperands[6] = gen_label_rtx();
1165 #ifdef MOTOROLA
1166 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1167 #else
1168 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1169 #endif
1170 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1171 CODE_LABEL_NUMBER (loperands[4]));
1172 output_asm_insn ("sle %5", loperands);
1173 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1174 CODE_LABEL_NUMBER (loperands[6]));
1175 break;
1176
1177 case LEU:
1178 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1179 CODE_LABEL_NUMBER (loperands[4]));
1180 output_asm_insn ("sls %5", loperands);
1181 break;
1182
1183 default:
1184 abort ();
1185 }
1186 return "";
1187 }
1188
1189 char *
1190 output_btst (operands, countop, dataop, insn, signpos)
1191 rtx *operands;
1192 rtx countop, dataop;
1193 rtx insn;
1194 int signpos;
1195 {
1196 operands[0] = countop;
1197 operands[1] = dataop;
1198
1199 if (GET_CODE (countop) == CONST_INT)
1200 {
1201 register int count = INTVAL (countop);
1202 /* If COUNT is bigger than size of storage unit in use,
1203 advance to the containing unit of same size. */
1204 if (count > signpos)
1205 {
1206 int offset = (count & ~signpos) / 8;
1207 count = count & signpos;
1208 operands[1] = dataop = adj_offsettable_operand (dataop, offset);
1209 }
1210 if (count == signpos)
1211 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1212 else
1213 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1214
1215 /* These three statements used to use next_insns_test_no...
1216 but it appears that this should do the same job. */
1217 if (count == 31
1218 && next_insn_tests_no_inequality (insn))
1219 return "tst%.l %1";
1220 if (count == 15
1221 && next_insn_tests_no_inequality (insn))
1222 return "tst%.w %1";
1223 if (count == 7
1224 && next_insn_tests_no_inequality (insn))
1225 return "tst%.b %1";
1226
1227 cc_status.flags = CC_NOT_NEGATIVE;
1228 }
1229 return "btst %0,%1";
1230 }
1231 \f
1232 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1233 reference and a constant. */
1234
1235 int
1236 symbolic_operand (op, mode)
1237 register rtx op;
1238 enum machine_mode mode ATTRIBUTE_UNUSED;
1239 {
1240 switch (GET_CODE (op))
1241 {
1242 case SYMBOL_REF:
1243 case LABEL_REF:
1244 return 1;
1245
1246 case CONST:
1247 op = XEXP (op, 0);
1248 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1249 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1250 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1251
1252 #if 0 /* Deleted, with corresponding change in m68k.h,
1253 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1254 case CONST_DOUBLE:
1255 return GET_MODE (op) == mode;
1256 #endif
1257
1258 default:
1259 return 0;
1260 }
1261 }
1262 \f
1263 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1264
1265 int
1266 extend_operator(x, mode)
1267 rtx x;
1268 enum machine_mode mode;
1269 {
1270 if (mode != VOIDmode && GET_MODE(x) != mode)
1271 return 0;
1272 switch (GET_CODE(x))
1273 {
1274 case SIGN_EXTEND :
1275 case ZERO_EXTEND :
1276 return 1;
1277 default :
1278 return 0;
1279 }
1280 }
1281
1282 \f
1283 /* Legitimize PIC addresses. If the address is already
1284 position-independent, we return ORIG. Newly generated
1285 position-independent addresses go to REG. If we need more
1286 than one register, we lose.
1287
1288 An address is legitimized by making an indirect reference
1289 through the Global Offset Table with the name of the symbol
1290 used as an offset.
1291
1292 The assembler and linker are responsible for placing the
1293 address of the symbol in the GOT. The function prologue
1294 is responsible for initializing a5 to the starting address
1295 of the GOT.
1296
1297 The assembler is also responsible for translating a symbol name
1298 into a constant displacement from the start of the GOT.
1299
1300 A quick example may make things a little clearer:
1301
1302 When not generating PIC code to store the value 12345 into _foo
1303 we would generate the following code:
1304
1305 movel #12345, _foo
1306
1307 When generating PIC two transformations are made. First, the compiler
1308 loads the address of foo into a register. So the first transformation makes:
1309
1310 lea _foo, a0
1311 movel #12345, a0@
1312
1313 The code in movsi will intercept the lea instruction and call this
1314 routine which will transform the instructions into:
1315
1316 movel a5@(_foo:w), a0
1317 movel #12345, a0@
1318
1319
1320 That (in a nutshell) is how *all* symbol and label references are
1321 handled. */
1322
1323 rtx
1324 legitimize_pic_address (orig, mode, reg)
1325 rtx orig, reg;
1326 enum machine_mode mode ATTRIBUTE_UNUSED;
1327 {
1328 rtx pic_ref = orig;
1329
1330 /* First handle a simple SYMBOL_REF or LABEL_REF */
1331 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1332 {
1333 if (reg == 0)
1334 abort ();
1335
1336 pic_ref = gen_rtx_MEM (Pmode,
1337 gen_rtx_PLUS (Pmode,
1338 pic_offset_table_rtx, orig));
1339 current_function_uses_pic_offset_table = 1;
1340 RTX_UNCHANGING_P (pic_ref) = 1;
1341 emit_move_insn (reg, pic_ref);
1342 return reg;
1343 }
1344 else if (GET_CODE (orig) == CONST)
1345 {
1346 rtx base;
1347
1348 /* Make sure this is CONST has not already been legitimized */
1349 if (GET_CODE (XEXP (orig, 0)) == PLUS
1350 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1351 return orig;
1352
1353 if (reg == 0)
1354 abort ();
1355
1356 /* legitimize both operands of the PLUS */
1357 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1358 {
1359 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1360 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1361 base == reg ? 0 : reg);
1362 }
1363 else abort ();
1364
1365 if (GET_CODE (orig) == CONST_INT)
1366 return plus_constant_for_output (base, INTVAL (orig));
1367 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1368 /* Likewise, should we set special REG_NOTEs here? */
1369 }
1370 return pic_ref;
1371 }
1372
1373 \f
1374 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1375
1376 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1377
1378 CONST_METHOD
1379 const_method (constant)
1380 rtx constant;
1381 {
1382 int i;
1383 unsigned u;
1384
1385 i = INTVAL (constant);
1386 if (USE_MOVQ (i))
1387 return MOVQ;
1388
1389 /* The Coldfire doesn't have byte or word operations. */
1390 /* FIXME: This may not be useful for the m68060 either */
1391 if (!TARGET_5200)
1392 {
1393 /* if -256 < N < 256 but N is not in range for a moveq
1394 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1395 if (USE_MOVQ (i ^ 0xff))
1396 return NOTB;
1397 /* Likewise, try with not.w */
1398 if (USE_MOVQ (i ^ 0xffff))
1399 return NOTW;
1400 /* This is the only value where neg.w is useful */
1401 if (i == -65408)
1402 return NEGW;
1403 /* Try also with swap */
1404 u = i;
1405 if (USE_MOVQ ((u >> 16) | (u << 16)))
1406 return SWAP;
1407 }
1408 /* Otherwise, use move.l */
1409 return MOVL;
1410 }
1411
1412 int
1413 const_int_cost (constant)
1414 rtx constant;
1415 {
1416 switch (const_method (constant))
1417 {
1418 case MOVQ :
1419 /* Constants between -128 and 127 are cheap due to moveq */
1420 return 0;
1421 case NOTB :
1422 case NOTW :
1423 case NEGW :
1424 case SWAP :
1425 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1426 return 1;
1427 case MOVL :
1428 return 2;
1429 default :
1430 abort ();
1431 }
1432 }
1433
1434 char *
1435 output_move_const_into_data_reg (operands)
1436 rtx *operands;
1437 {
1438 int i;
1439
1440 i = INTVAL (operands[1]);
1441 switch (const_method (operands[1]))
1442 {
1443 case MOVQ :
1444 #if defined (MOTOROLA) && !defined (CRDS)
1445 return "moveq%.l %1,%0";
1446 #else
1447 return "moveq %1,%0";
1448 #endif
1449 case NOTB :
1450 operands[1] = GEN_INT (i ^ 0xff);
1451 #if defined (MOTOROLA) && !defined (CRDS)
1452 return "moveq%.l %1,%0\n\tnot%.b %0";
1453 #else
1454 return "moveq %1,%0\n\tnot%.b %0";
1455 #endif
1456 case NOTW :
1457 operands[1] = GEN_INT (i ^ 0xffff);
1458 #if defined (MOTOROLA) && !defined (CRDS)
1459 return "moveq%.l %1,%0\n\tnot%.w %0";
1460 #else
1461 return "moveq %1,%0\n\tnot%.w %0";
1462 #endif
1463 case NEGW :
1464 #if defined (MOTOROLA) && !defined (CRDS)
1465 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1466 #else
1467 return "moveq %#-128,%0\n\tneg%.w %0";
1468 #endif
1469 case SWAP :
1470 {
1471 unsigned u = i;
1472
1473 operands[1] = GEN_INT ((u << 16) | (u >> 16));
1474 #if defined (MOTOROLA) && !defined (CRDS)
1475 return "moveq%.l %1,%0\n\tswap %0";
1476 #else
1477 return "moveq %1,%0\n\tswap %0";
1478 #endif
1479 }
1480 case MOVL :
1481 return "move%.l %1,%0";
1482 default :
1483 abort ();
1484 }
1485 }
1486
1487 char *
1488 output_move_simode_const (operands)
1489 rtx *operands;
1490 {
1491 if (operands[1] == const0_rtx
1492 && (DATA_REG_P (operands[0])
1493 || GET_CODE (operands[0]) == MEM)
1494 /* clr insns on 68000 read before writing.
1495 This isn't so on the 68010, but we have no TARGET_68010. */
1496 && ((TARGET_68020 || TARGET_5200)
1497 || !(GET_CODE (operands[0]) == MEM
1498 && MEM_VOLATILE_P (operands[0]))))
1499 return "clr%.l %0";
1500 else if (operands[1] == const0_rtx
1501 && ADDRESS_REG_P (operands[0]))
1502 return "sub%.l %0,%0";
1503 else if (DATA_REG_P (operands[0]))
1504 return output_move_const_into_data_reg (operands);
1505 else if (ADDRESS_REG_P (operands[0])
1506 && INTVAL (operands[1]) < 0x8000
1507 && INTVAL (operands[1]) >= -0x8000)
1508 return "move%.w %1,%0";
1509 else if (GET_CODE (operands[0]) == MEM
1510 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1511 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1512 && INTVAL (operands[1]) < 0x8000
1513 && INTVAL (operands[1]) >= -0x8000)
1514 return "pea %a1";
1515 return "move%.l %1,%0";
1516 }
1517
1518 char *
1519 output_move_simode (operands)
1520 rtx *operands;
1521 {
1522 if (GET_CODE (operands[1]) == CONST_INT)
1523 return output_move_simode_const (operands);
1524 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1525 || GET_CODE (operands[1]) == CONST)
1526 && push_operand (operands[0], SImode))
1527 return "pea %a1";
1528 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1529 || GET_CODE (operands[1]) == CONST)
1530 && ADDRESS_REG_P (operands[0]))
1531 return "lea %a1,%0";
1532 return "move%.l %1,%0";
1533 }
1534
1535 char *
1536 output_move_himode (operands)
1537 rtx *operands;
1538 {
1539 if (GET_CODE (operands[1]) == CONST_INT)
1540 {
1541 if (operands[1] == const0_rtx
1542 && (DATA_REG_P (operands[0])
1543 || GET_CODE (operands[0]) == MEM)
1544 /* clr insns on 68000 read before writing.
1545 This isn't so on the 68010, but we have no TARGET_68010. */
1546 && ((TARGET_68020 || TARGET_5200)
1547 || !(GET_CODE (operands[0]) == MEM
1548 && MEM_VOLATILE_P (operands[0]))))
1549 return "clr%.w %0";
1550 else if (operands[1] == const0_rtx
1551 && ADDRESS_REG_P (operands[0]))
1552 return "sub%.l %0,%0";
1553 else if (DATA_REG_P (operands[0])
1554 && INTVAL (operands[1]) < 128
1555 && INTVAL (operands[1]) >= -128)
1556 {
1557 #if defined(MOTOROLA) && !defined(CRDS)
1558 return "moveq%.l %1,%0";
1559 #else
1560 return "moveq %1,%0";
1561 #endif
1562 }
1563 else if (INTVAL (operands[1]) < 0x8000
1564 && INTVAL (operands[1]) >= -0x8000)
1565 return "move%.w %1,%0";
1566 }
1567 else if (CONSTANT_P (operands[1]))
1568 return "move%.l %1,%0";
1569 #ifndef SGS_NO_LI
1570 /* Recognize the insn before a tablejump, one that refers
1571 to a table of offsets. Such an insn will need to refer
1572 to a label on the insn. So output one. Use the label-number
1573 of the table of offsets to generate this label. This code,
1574 and similar code below, assumes that there will be at most one
1575 reference to each table. */
1576 if (GET_CODE (operands[1]) == MEM
1577 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1578 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1579 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1580 {
1581 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1582 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1583 #ifdef SGS
1584 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1585 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1586 #else /* not SGS */
1587 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1588 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1589 #endif /* not SGS */
1590 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1591 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
1592 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1593 #ifdef SGS_SWITCH_TABLES
1594 /* Set flag saying we need to define the symbol
1595 LD%n (with value L%n-LI%n) at the end of the switch table. */
1596 switch_table_difference_label_flag = 1;
1597 #endif /* SGS_SWITCH_TABLES */
1598 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1599 }
1600 #endif /* SGS_NO_LI */
1601 return "move%.w %1,%0";
1602 }
1603
1604 char *
1605 output_move_qimode (operands)
1606 rtx *operands;
1607 {
1608 rtx xoperands[4];
1609
1610 /* This is probably useless, since it loses for pushing a struct
1611 of several bytes a byte at a time. */
1612 /* 68k family always modifies the stack pointer by at least 2, even for
1613 byte pushes. The 5200 (coldfire) does not do this. */
1614 if (GET_CODE (operands[0]) == MEM
1615 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1616 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1617 && ! ADDRESS_REG_P (operands[1])
1618 && ! TARGET_5200)
1619 {
1620 xoperands[1] = operands[1];
1621 xoperands[2]
1622 = gen_rtx_MEM (QImode,
1623 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
1624 /* Just pushing a byte puts it in the high byte of the halfword. */
1625 /* We must put it in the low-order, high-numbered byte. */
1626 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1627 {
1628 xoperands[3] = stack_pointer_rtx;
1629 #ifndef NO_ADDSUB_Q
1630 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1631 #else
1632 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1633 #endif
1634 }
1635 else
1636 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
1637 return "";
1638 }
1639
1640 /* clr and st insns on 68000 read before writing.
1641 This isn't so on the 68010, but we have no TARGET_68010. */
1642 if (!ADDRESS_REG_P (operands[0])
1643 && ((TARGET_68020 || TARGET_5200)
1644 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1645 {
1646 if (operands[1] == const0_rtx)
1647 return "clr%.b %0";
1648 if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1649 && GET_CODE (operands[1]) == CONST_INT
1650 && (INTVAL (operands[1]) & 255) == 255)
1651 {
1652 CC_STATUS_INIT;
1653 return "st %0";
1654 }
1655 }
1656 if (GET_CODE (operands[1]) == CONST_INT
1657 && DATA_REG_P (operands[0])
1658 && INTVAL (operands[1]) < 128
1659 && INTVAL (operands[1]) >= -128)
1660 {
1661 #if defined(MOTOROLA) && !defined(CRDS)
1662 return "moveq%.l %1,%0";
1663 #else
1664 return "moveq %1,%0";
1665 #endif
1666 }
1667 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
1668 return "sub%.l %0,%0";
1669 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1670 return "move%.l %1,%0";
1671 /* 68k family (including the 5200 coldfire) does not support byte moves to
1672 from address registers. */
1673 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1674 return "move%.w %1,%0";
1675 return "move%.b %1,%0";
1676 }
1677
1678 char *
1679 output_move_stricthi (operands)
1680 rtx *operands;
1681 {
1682 if (operands[1] == const0_rtx
1683 /* clr insns on 68000 read before writing.
1684 This isn't so on the 68010, but we have no TARGET_68010. */
1685 && ((TARGET_68020 || TARGET_5200)
1686 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1687 return "clr%.w %0";
1688 return "move%.w %1,%0";
1689 }
1690
1691 char *
1692 output_move_strictqi (operands)
1693 rtx *operands;
1694 {
1695 if (operands[1] == const0_rtx
1696 /* clr insns on 68000 read before writing.
1697 This isn't so on the 68010, but we have no TARGET_68010. */
1698 && ((TARGET_68020 || TARGET_5200)
1699 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1700 return "clr%.b %0";
1701 return "move%.b %1,%0";
1702 }
1703
1704 /* Return the best assembler insn template
1705 for moving operands[1] into operands[0] as a fullword. */
1706
1707 static char *
1708 singlemove_string (operands)
1709 rtx *operands;
1710 {
1711 #ifdef SUPPORT_SUN_FPA
1712 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1713 return "fpmoves %1,%0";
1714 #endif
1715 if (GET_CODE (operands[1]) == CONST_INT)
1716 return output_move_simode_const (operands);
1717 return "move%.l %1,%0";
1718 }
1719
1720
1721 /* Output assembler code to perform a doubleword move insn
1722 with operands OPERANDS. */
1723
1724 char *
1725 output_move_double (operands)
1726 rtx *operands;
1727 {
1728 enum
1729 {
1730 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1731 } optype0, optype1;
1732 rtx latehalf[2];
1733 rtx middlehalf[2];
1734 rtx xops[2];
1735 rtx addreg0 = 0, addreg1 = 0;
1736 int dest_overlapped_low = 0;
1737 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1738
1739 middlehalf[0] = 0;
1740 middlehalf[1] = 0;
1741
1742 /* First classify both operands. */
1743
1744 if (REG_P (operands[0]))
1745 optype0 = REGOP;
1746 else if (offsettable_memref_p (operands[0]))
1747 optype0 = OFFSOP;
1748 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1749 optype0 = POPOP;
1750 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1751 optype0 = PUSHOP;
1752 else if (GET_CODE (operands[0]) == MEM)
1753 optype0 = MEMOP;
1754 else
1755 optype0 = RNDOP;
1756
1757 if (REG_P (operands[1]))
1758 optype1 = REGOP;
1759 else if (CONSTANT_P (operands[1]))
1760 optype1 = CNSTOP;
1761 else if (offsettable_memref_p (operands[1]))
1762 optype1 = OFFSOP;
1763 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1764 optype1 = POPOP;
1765 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1766 optype1 = PUSHOP;
1767 else if (GET_CODE (operands[1]) == MEM)
1768 optype1 = MEMOP;
1769 else
1770 optype1 = RNDOP;
1771
1772 /* Check for the cases that the operand constraints are not
1773 supposed to allow to happen. Abort if we get one,
1774 because generating code for these cases is painful. */
1775
1776 if (optype0 == RNDOP || optype1 == RNDOP)
1777 abort ();
1778
1779 /* If one operand is decrementing and one is incrementing
1780 decrement the former register explicitly
1781 and change that operand into ordinary indexing. */
1782
1783 if (optype0 == PUSHOP && optype1 == POPOP)
1784 {
1785 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1786 if (size == 12)
1787 output_asm_insn ("sub%.l %#12,%0", operands);
1788 else
1789 output_asm_insn ("subq%.l %#8,%0", operands);
1790 if (GET_MODE (operands[1]) == XFmode)
1791 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1792 else if (GET_MODE (operands[0]) == DFmode)
1793 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1794 else
1795 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1796 optype0 = OFFSOP;
1797 }
1798 if (optype0 == POPOP && optype1 == PUSHOP)
1799 {
1800 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1801 if (size == 12)
1802 output_asm_insn ("sub%.l %#12,%1", operands);
1803 else
1804 output_asm_insn ("subq%.l %#8,%1", operands);
1805 if (GET_MODE (operands[1]) == XFmode)
1806 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1807 else if (GET_MODE (operands[1]) == DFmode)
1808 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1809 else
1810 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1811 optype1 = OFFSOP;
1812 }
1813
1814 /* If an operand is an unoffsettable memory ref, find a register
1815 we can increment temporarily to make it refer to the second word. */
1816
1817 if (optype0 == MEMOP)
1818 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1819
1820 if (optype1 == MEMOP)
1821 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1822
1823 /* Ok, we can do one word at a time.
1824 Normally we do the low-numbered word first,
1825 but if either operand is autodecrementing then we
1826 do the high-numbered word first.
1827
1828 In either case, set up in LATEHALF the operands to use
1829 for the high-numbered word and in some cases alter the
1830 operands in OPERANDS to be suitable for the low-numbered word. */
1831
1832 if (size == 12)
1833 {
1834 if (optype0 == REGOP)
1835 {
1836 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1837 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1838 }
1839 else if (optype0 == OFFSOP)
1840 {
1841 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1842 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1843 }
1844 else
1845 {
1846 middlehalf[0] = operands[0];
1847 latehalf[0] = operands[0];
1848 }
1849
1850 if (optype1 == REGOP)
1851 {
1852 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1853 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1854 }
1855 else if (optype1 == OFFSOP)
1856 {
1857 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1858 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1859 }
1860 else if (optype1 == CNSTOP)
1861 {
1862 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1863 {
1864 REAL_VALUE_TYPE r;
1865 long l[3];
1866
1867 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1868 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1869 operands[1] = GEN_INT (l[0]);
1870 middlehalf[1] = GEN_INT (l[1]);
1871 latehalf[1] = GEN_INT (l[2]);
1872 }
1873 else if (CONSTANT_P (operands[1]))
1874 {
1875 /* actually, no non-CONST_DOUBLE constant should ever
1876 appear here. */
1877 abort ();
1878 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
1879 latehalf[1] = constm1_rtx;
1880 else
1881 latehalf[1] = const0_rtx;
1882 }
1883 }
1884 else
1885 {
1886 middlehalf[1] = operands[1];
1887 latehalf[1] = operands[1];
1888 }
1889 }
1890 else
1891 /* size is not 12: */
1892 {
1893 if (optype0 == REGOP)
1894 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1895 else if (optype0 == OFFSOP)
1896 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1897 else
1898 latehalf[0] = operands[0];
1899
1900 if (optype1 == REGOP)
1901 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1902 else if (optype1 == OFFSOP)
1903 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1904 else if (optype1 == CNSTOP)
1905 split_double (operands[1], &operands[1], &latehalf[1]);
1906 else
1907 latehalf[1] = operands[1];
1908 }
1909
1910 /* If insn is effectively movd N(sp),-(sp) then we will do the
1911 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1912 for the low word as well, to compensate for the first decrement of sp. */
1913 if (optype0 == PUSHOP
1914 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1915 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1916 operands[1] = middlehalf[1] = latehalf[1];
1917
1918 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1919 if the upper part of reg N does not appear in the MEM, arrange to
1920 emit the move late-half first. Otherwise, compute the MEM address
1921 into the upper part of N and use that as a pointer to the memory
1922 operand. */
1923 if (optype0 == REGOP
1924 && (optype1 == OFFSOP || optype1 == MEMOP))
1925 {
1926 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
1927
1928 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1929 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1930 {
1931 /* If both halves of dest are used in the src memory address,
1932 compute the address into latehalf of dest.
1933 Note that this can't happen if the dest is two data regs. */
1934 compadr:
1935 xops[0] = latehalf[0];
1936 xops[1] = XEXP (operands[1], 0);
1937 output_asm_insn ("lea %a1,%0", xops);
1938 if( GET_MODE (operands[1]) == XFmode )
1939 {
1940 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1941 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1942 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1943 }
1944 else
1945 {
1946 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1947 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1948 }
1949 }
1950 else if (size == 12
1951 && reg_overlap_mentioned_p (middlehalf[0],
1952 XEXP (operands[1], 0)))
1953 {
1954 /* Check for two regs used by both source and dest.
1955 Note that this can't happen if the dest is all data regs.
1956 It can happen if the dest is d6, d7, a0.
1957 But in that case, latehalf is an addr reg, so
1958 the code at compadr does ok. */
1959
1960 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1961 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1962 goto compadr;
1963
1964 /* JRV says this can't happen: */
1965 if (addreg0 || addreg1)
1966 abort ();
1967
1968 /* Only the middle reg conflicts; simply put it last. */
1969 output_asm_insn (singlemove_string (operands), operands);
1970 output_asm_insn (singlemove_string (latehalf), latehalf);
1971 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1972 return "";
1973 }
1974 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
1975 /* If the low half of dest is mentioned in the source memory
1976 address, the arrange to emit the move late half first. */
1977 dest_overlapped_low = 1;
1978 }
1979
1980 /* If one or both operands autodecrementing,
1981 do the two words, high-numbered first. */
1982
1983 /* Likewise, the first move would clobber the source of the second one,
1984 do them in the other order. This happens only for registers;
1985 such overlap can't happen in memory unless the user explicitly
1986 sets it up, and that is an undefined circumstance. */
1987
1988 if (optype0 == PUSHOP || optype1 == PUSHOP
1989 || (optype0 == REGOP && optype1 == REGOP
1990 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1991 || REGNO (operands[0]) == REGNO (latehalf[1])))
1992 || dest_overlapped_low)
1993 {
1994 /* Make any unoffsettable addresses point at high-numbered word. */
1995 if (addreg0)
1996 {
1997 if (size == 12)
1998 output_asm_insn ("addq%.l %#8,%0", &addreg0);
1999 else
2000 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2001 }
2002 if (addreg1)
2003 {
2004 if (size == 12)
2005 output_asm_insn ("addq%.l %#8,%0", &addreg1);
2006 else
2007 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2008 }
2009
2010 /* Do that word. */
2011 output_asm_insn (singlemove_string (latehalf), latehalf);
2012
2013 /* Undo the adds we just did. */
2014 if (addreg0)
2015 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2016 if (addreg1)
2017 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2018
2019 if (size == 12)
2020 {
2021 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2022 if (addreg0)
2023 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2024 if (addreg1)
2025 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2026 }
2027
2028 /* Do low-numbered word. */
2029 return singlemove_string (operands);
2030 }
2031
2032 /* Normal case: do the two words, low-numbered first. */
2033
2034 output_asm_insn (singlemove_string (operands), operands);
2035
2036 /* Do the middle one of the three words for long double */
2037 if (size == 12)
2038 {
2039 if (addreg0)
2040 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2041 if (addreg1)
2042 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2043
2044 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2045 }
2046
2047 /* Make any unoffsettable addresses point at high-numbered word. */
2048 if (addreg0)
2049 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2050 if (addreg1)
2051 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2052
2053 /* Do that word. */
2054 output_asm_insn (singlemove_string (latehalf), latehalf);
2055
2056 /* Undo the adds we just did. */
2057 if (addreg0)
2058 {
2059 if (size == 12)
2060 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2061 else
2062 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2063 }
2064 if (addreg1)
2065 {
2066 if (size == 12)
2067 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2068 else
2069 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2070 }
2071
2072 return "";
2073 }
2074
2075 /* Return a REG that occurs in ADDR with coefficient 1.
2076 ADDR can be effectively incremented by incrementing REG. */
2077
2078 static rtx
2079 find_addr_reg (addr)
2080 rtx addr;
2081 {
2082 while (GET_CODE (addr) == PLUS)
2083 {
2084 if (GET_CODE (XEXP (addr, 0)) == REG)
2085 addr = XEXP (addr, 0);
2086 else if (GET_CODE (XEXP (addr, 1)) == REG)
2087 addr = XEXP (addr, 1);
2088 else if (CONSTANT_P (XEXP (addr, 0)))
2089 addr = XEXP (addr, 1);
2090 else if (CONSTANT_P (XEXP (addr, 1)))
2091 addr = XEXP (addr, 0);
2092 else
2093 abort ();
2094 }
2095 if (GET_CODE (addr) == REG)
2096 return addr;
2097 abort ();
2098 }
2099
2100 /* Output assembler code to perform a 32 bit 3 operand add. */
2101
2102 char *
2103 output_addsi3 (operands)
2104 rtx *operands;
2105 {
2106 if (! operands_match_p (operands[0], operands[1]))
2107 {
2108 if (!ADDRESS_REG_P (operands[1]))
2109 {
2110 rtx tmp = operands[1];
2111
2112 operands[1] = operands[2];
2113 operands[2] = tmp;
2114 }
2115
2116 /* These insns can result from reloads to access
2117 stack slots over 64k from the frame pointer. */
2118 if (GET_CODE (operands[2]) == CONST_INT
2119 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2120 return "move%.l %2,%0\n\tadd%.l %1,%0";
2121 #ifdef SGS
2122 if (GET_CODE (operands[2]) == REG)
2123 return "lea 0(%1,%2.l),%0";
2124 else
2125 return "lea %c2(%1),%0";
2126 #else /* not SGS */
2127 #ifdef MOTOROLA
2128 if (GET_CODE (operands[2]) == REG)
2129 return "lea (%1,%2.l),%0";
2130 else
2131 return "lea (%c2,%1),%0";
2132 #else /* not MOTOROLA (MIT syntax) */
2133 if (GET_CODE (operands[2]) == REG)
2134 return "lea %1@(0,%2:l),%0";
2135 else
2136 return "lea %1@(%c2),%0";
2137 #endif /* not MOTOROLA */
2138 #endif /* not SGS */
2139 }
2140 if (GET_CODE (operands[2]) == CONST_INT)
2141 {
2142 #ifndef NO_ADDSUB_Q
2143 if (INTVAL (operands[2]) > 0
2144 && INTVAL (operands[2]) <= 8)
2145 return "addq%.l %2,%0";
2146 if (INTVAL (operands[2]) < 0
2147 && INTVAL (operands[2]) >= -8)
2148 {
2149 operands[2] = GEN_INT (- INTVAL (operands[2]));
2150 return "subq%.l %2,%0";
2151 }
2152 /* On the CPU32 it is faster to use two addql instructions to
2153 add a small integer (8 < N <= 16) to a register.
2154 Likewise for subql. */
2155 if (TARGET_CPU32 && REG_P (operands[0]))
2156 {
2157 if (INTVAL (operands[2]) > 8
2158 && INTVAL (operands[2]) <= 16)
2159 {
2160 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2161 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2162 }
2163 if (INTVAL (operands[2]) < -8
2164 && INTVAL (operands[2]) >= -16)
2165 {
2166 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2167 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2168 }
2169 }
2170 #endif
2171 if (ADDRESS_REG_P (operands[0])
2172 && INTVAL (operands[2]) >= -0x8000
2173 && INTVAL (operands[2]) < 0x8000)
2174 {
2175 if (TARGET_68040)
2176 return "add%.w %2,%0";
2177 else
2178 #ifdef MOTOROLA
2179 return "lea (%c2,%0),%0";
2180 #else
2181 return "lea %0@(%c2),%0";
2182 #endif
2183 }
2184 }
2185 return "add%.l %2,%0";
2186 }
2187 \f
2188 /* Store in cc_status the expressions that the condition codes will
2189 describe after execution of an instruction whose pattern is EXP.
2190 Do not alter them if the instruction would not alter the cc's. */
2191
2192 /* On the 68000, all the insns to store in an address register fail to
2193 set the cc's. However, in some cases these instructions can make it
2194 possibly invalid to use the saved cc's. In those cases we clear out
2195 some or all of the saved cc's so they won't be used. */
2196
2197 void
2198 notice_update_cc (exp, insn)
2199 rtx exp;
2200 rtx insn;
2201 {
2202 /* If the cc is being set from the fpa and the expression is not an
2203 explicit floating point test instruction (which has code to deal with
2204 this), reinit the CC. */
2205 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
2206 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
2207 && !(GET_CODE (exp) == PARALLEL
2208 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
2209 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
2210 {
2211 CC_STATUS_INIT;
2212 }
2213 else if (GET_CODE (exp) == SET)
2214 {
2215 if (GET_CODE (SET_SRC (exp)) == CALL)
2216 {
2217 CC_STATUS_INIT;
2218 }
2219 else if (ADDRESS_REG_P (SET_DEST (exp)))
2220 {
2221 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
2222 cc_status.value1 = 0;
2223 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
2224 cc_status.value2 = 0;
2225 }
2226 else if (!FP_REG_P (SET_DEST (exp))
2227 && SET_DEST (exp) != cc0_rtx
2228 && (FP_REG_P (SET_SRC (exp))
2229 || GET_CODE (SET_SRC (exp)) == FIX
2230 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2231 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2232 {
2233 CC_STATUS_INIT;
2234 }
2235 /* A pair of move insns doesn't produce a useful overall cc. */
2236 else if (!FP_REG_P (SET_DEST (exp))
2237 && !FP_REG_P (SET_SRC (exp))
2238 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2239 && (GET_CODE (SET_SRC (exp)) == REG
2240 || GET_CODE (SET_SRC (exp)) == MEM
2241 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2242 {
2243 CC_STATUS_INIT;
2244 }
2245 else if (GET_CODE (SET_SRC (exp)) == CALL)
2246 {
2247 CC_STATUS_INIT;
2248 }
2249 else if (XEXP (exp, 0) != pc_rtx)
2250 {
2251 cc_status.flags = 0;
2252 cc_status.value1 = XEXP (exp, 0);
2253 cc_status.value2 = XEXP (exp, 1);
2254 }
2255 }
2256 else if (GET_CODE (exp) == PARALLEL
2257 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2258 {
2259 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2260 CC_STATUS_INIT;
2261 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2262 {
2263 cc_status.flags = 0;
2264 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2265 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2266 }
2267 }
2268 else
2269 CC_STATUS_INIT;
2270 if (cc_status.value2 != 0
2271 && ADDRESS_REG_P (cc_status.value2)
2272 && GET_MODE (cc_status.value2) == QImode)
2273 CC_STATUS_INIT;
2274 if (cc_status.value2 != 0
2275 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
2276 switch (GET_CODE (cc_status.value2))
2277 {
2278 case PLUS: case MINUS: case MULT:
2279 case DIV: case UDIV: case MOD: case UMOD: case NEG:
2280 #if 0 /* These instructions always clear the overflow bit */
2281 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
2282 case ROTATE: case ROTATERT:
2283 #endif
2284 if (GET_MODE (cc_status.value2) != VOIDmode)
2285 cc_status.flags |= CC_NO_OVERFLOW;
2286 break;
2287 case ZERO_EXTEND:
2288 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2289 ends with a move insn moving r2 in r2's mode.
2290 Thus, the cc's are set for r2.
2291 This can set N bit spuriously. */
2292 cc_status.flags |= CC_NOT_NEGATIVE;
2293
2294 default:
2295 break;
2296 }
2297 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2298 && cc_status.value2
2299 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2300 cc_status.value2 = 0;
2301 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2302 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
2303 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
2304 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
2305 cc_status.flags = CC_IN_68881;
2306 }
2307 \f
2308 char *
2309 output_move_const_double (operands)
2310 rtx *operands;
2311 {
2312 #ifdef SUPPORT_SUN_FPA
2313 if (TARGET_FPA && FPA_REG_P (operands[0]))
2314 {
2315 int code = standard_sun_fpa_constant_p (operands[1]);
2316
2317 if (code != 0)
2318 {
2319 static char buf[40];
2320
2321 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
2322 return buf;
2323 }
2324 return "fpmove%.d %1,%0";
2325 }
2326 else
2327 #endif
2328 {
2329 int code = standard_68881_constant_p (operands[1]);
2330
2331 if (code != 0)
2332 {
2333 static char buf[40];
2334
2335 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2336 return buf;
2337 }
2338 return "fmove%.d %1,%0";
2339 }
2340 }
2341
2342 char *
2343 output_move_const_single (operands)
2344 rtx *operands;
2345 {
2346 #ifdef SUPPORT_SUN_FPA
2347 if (TARGET_FPA)
2348 {
2349 int code = standard_sun_fpa_constant_p (operands[1]);
2350
2351 if (code != 0)
2352 {
2353 static char buf[40];
2354
2355 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
2356 return buf;
2357 }
2358 return "fpmove%.s %1,%0";
2359 }
2360 else
2361 #endif /* defined SUPPORT_SUN_FPA */
2362 {
2363 int code = standard_68881_constant_p (operands[1]);
2364
2365 if (code != 0)
2366 {
2367 static char buf[40];
2368
2369 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2370 return buf;
2371 }
2372 return "fmove%.s %f1,%0";
2373 }
2374 }
2375
2376 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2377 from the "fmovecr" instruction.
2378 The value, anded with 0xff, gives the code to use in fmovecr
2379 to get the desired constant. */
2380
2381 /* This code has been fixed for cross-compilation. */
2382
2383 static int inited_68881_table = 0;
2384
2385 char *strings_68881[7] = {
2386 "0.0",
2387 "1.0",
2388 "10.0",
2389 "100.0",
2390 "10000.0",
2391 "1e8",
2392 "1e16"
2393 };
2394
2395 int codes_68881[7] = {
2396 0x0f,
2397 0x32,
2398 0x33,
2399 0x34,
2400 0x35,
2401 0x36,
2402 0x37
2403 };
2404
2405 REAL_VALUE_TYPE values_68881[7];
2406
2407 /* Set up values_68881 array by converting the decimal values
2408 strings_68881 to binary. */
2409
2410 void
2411 init_68881_table ()
2412 {
2413 int i;
2414 REAL_VALUE_TYPE r;
2415 enum machine_mode mode;
2416
2417 mode = SFmode;
2418 for (i = 0; i < 7; i++)
2419 {
2420 if (i == 6)
2421 mode = DFmode;
2422 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2423 values_68881[i] = r;
2424 }
2425 inited_68881_table = 1;
2426 }
2427
2428 int
2429 standard_68881_constant_p (x)
2430 rtx x;
2431 {
2432 REAL_VALUE_TYPE r;
2433 int i;
2434
2435 #ifdef NO_ASM_FMOVECR
2436 return 0;
2437 #endif
2438
2439 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2440 used at all on those chips. */
2441 if (TARGET_68040 || TARGET_68060)
2442 return 0;
2443
2444 #ifndef REAL_ARITHMETIC
2445 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2446 if (! flag_pretend_float)
2447 return 0;
2448 #endif
2449 #endif
2450
2451 if (! inited_68881_table)
2452 init_68881_table ();
2453
2454 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2455
2456 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2457 is rejected. */
2458 for (i = 0; i < 6; i++)
2459 {
2460 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
2461 return (codes_68881[i]);
2462 }
2463
2464 if (GET_MODE (x) == SFmode)
2465 return 0;
2466
2467 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2468 return (codes_68881[6]);
2469
2470 /* larger powers of ten in the constants ram are not used
2471 because they are not equal to a `double' C constant. */
2472 return 0;
2473 }
2474
2475 /* If X is a floating-point constant, return the logarithm of X base 2,
2476 or 0 if X is not a power of 2. */
2477
2478 int
2479 floating_exact_log2 (x)
2480 rtx x;
2481 {
2482 REAL_VALUE_TYPE r, r1;
2483 int i;
2484
2485 #ifndef REAL_ARITHMETIC
2486 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2487 if (! flag_pretend_float)
2488 return 0;
2489 #endif
2490 #endif
2491
2492 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2493
2494 if (REAL_VALUES_LESS (r, dconst0))
2495 return 0;
2496
2497 r1 = dconst1;
2498 i = 0;
2499 while (REAL_VALUES_LESS (r1, r))
2500 {
2501 r1 = REAL_VALUE_LDEXP (dconst1, i);
2502 if (REAL_VALUES_EQUAL (r1, r))
2503 return i;
2504 i = i + 1;
2505 }
2506 return 0;
2507 }
2508 \f
2509 #ifdef SUPPORT_SUN_FPA
2510 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2511 from the Sun FPA's constant RAM.
2512 The value returned, anded with 0x1ff, gives the code to use in fpmove
2513 to get the desired constant. */
2514
2515 static int inited_FPA_table = 0;
2516
2517 char *strings_FPA[38] = {
2518 /* small rationals */
2519 "0.0",
2520 "1.0",
2521 "0.5",
2522 "-1.0",
2523 "2.0",
2524 "3.0",
2525 "4.0",
2526 "8.0",
2527 "0.25",
2528 "0.125",
2529 "10.0",
2530 "-0.5",
2531 /* Decimal equivalents of double precision values */
2532 "2.718281828459045091", /* D_E */
2533 "6.283185307179586477", /* 2 pi */
2534 "3.141592653589793116", /* D_PI */
2535 "1.570796326794896619", /* pi/2 */
2536 "1.414213562373095145", /* D_SQRT2 */
2537 "0.7071067811865475244", /* 1/sqrt(2) */
2538 "-1.570796326794896619", /* -pi/2 */
2539 "1.442695040888963387", /* D_LOG2ofE */
2540 "3.321928024887362182", /* D_LOG2of10 */
2541 "0.6931471805599452862", /* D_LOGEof2 */
2542 "2.302585092994045901", /* D_LOGEof10 */
2543 "0.3010299956639811980", /* D_LOG10of2 */
2544 "0.4342944819032518167", /* D_LOG10ofE */
2545 /* Decimal equivalents of single precision values */
2546 "2.718281745910644531", /* S_E */
2547 "6.283185307179586477", /* 2 pi */
2548 "3.141592741012573242", /* S_PI */
2549 "1.570796326794896619", /* pi/2 */
2550 "1.414213538169860840", /* S_SQRT2 */
2551 "0.7071067811865475244", /* 1/sqrt(2) */
2552 "-1.570796326794896619", /* -pi/2 */
2553 "1.442695021629333496", /* S_LOG2ofE */
2554 "3.321928024291992188", /* S_LOG2of10 */
2555 "0.6931471824645996094", /* S_LOGEof2 */
2556 "2.302585124969482442", /* S_LOGEof10 */
2557 "0.3010300099849700928", /* S_LOG10of2 */
2558 "0.4342944920063018799", /* S_LOG10ofE */
2559 };
2560
2561
2562 int codes_FPA[38] = {
2563 /* small rationals */
2564 0x200,
2565 0xe,
2566 0xf,
2567 0x10,
2568 0x11,
2569 0xb1,
2570 0x12,
2571 0x13,
2572 0x15,
2573 0x16,
2574 0x17,
2575 0x2e,
2576 /* double precision */
2577 0x8,
2578 0x9,
2579 0xa,
2580 0xb,
2581 0xc,
2582 0xd,
2583 0x27,
2584 0x28,
2585 0x29,
2586 0x2a,
2587 0x2b,
2588 0x2c,
2589 0x2d,
2590 /* single precision */
2591 0x8,
2592 0x9,
2593 0xa,
2594 0xb,
2595 0xc,
2596 0xd,
2597 0x27,
2598 0x28,
2599 0x29,
2600 0x2a,
2601 0x2b,
2602 0x2c,
2603 0x2d
2604 };
2605
2606 REAL_VALUE_TYPE values_FPA[38];
2607
2608 /* This code has been fixed for cross-compilation. */
2609
2610 void
2611 init_FPA_table ()
2612 {
2613 enum machine_mode mode;
2614 int i;
2615 REAL_VALUE_TYPE r;
2616
2617 mode = DFmode;
2618 for (i = 0; i < 38; i++)
2619 {
2620 if (i == 25)
2621 mode = SFmode;
2622 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2623 values_FPA[i] = r;
2624 }
2625 inited_FPA_table = 1;
2626 }
2627
2628
2629 int
2630 standard_sun_fpa_constant_p (x)
2631 rtx x;
2632 {
2633 REAL_VALUE_TYPE r;
2634 int i;
2635
2636 #ifndef REAL_ARITHMETIC
2637 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2638 if (! flag_pretend_float)
2639 return 0;
2640 #endif
2641 #endif
2642
2643 if (! inited_FPA_table)
2644 init_FPA_table ();
2645
2646 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2647
2648 for (i=0; i<12; i++)
2649 {
2650 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2651 return (codes_FPA[i]);
2652 }
2653
2654 if (GET_MODE (x) == SFmode)
2655 {
2656 for (i=25; i<38; i++)
2657 {
2658 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2659 return (codes_FPA[i]);
2660 }
2661 }
2662 else
2663 {
2664 for (i=12; i<25; i++)
2665 {
2666 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2667 return (codes_FPA[i]);
2668 }
2669 }
2670 return 0x0;
2671 }
2672 #endif /* define SUPPORT_SUN_FPA */
2673 \f
2674 /* A C compound statement to output to stdio stream STREAM the
2675 assembler syntax for an instruction operand X. X is an RTL
2676 expression.
2677
2678 CODE is a value that can be used to specify one of several ways
2679 of printing the operand. It is used when identical operands
2680 must be printed differently depending on the context. CODE
2681 comes from the `%' specification that was used to request
2682 printing of the operand. If the specification was just `%DIGIT'
2683 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2684 is the ASCII code for LTR.
2685
2686 If X is a register, this macro should print the register's name.
2687 The names can be found in an array `reg_names' whose type is
2688 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2689
2690 When the machine description has a specification `%PUNCT' (a `%'
2691 followed by a punctuation character), this macro is called with
2692 a null pointer for X and the punctuation character for CODE.
2693
2694 The m68k specific codes are:
2695
2696 '.' for dot needed in Motorola-style opcode names.
2697 '-' for an operand pushing on the stack:
2698 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2699 '+' for an operand pushing on the stack:
2700 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2701 '@' for a reference to the top word on the stack:
2702 sp@, (sp) or (%sp) depending on the style of syntax.
2703 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2704 but & in SGS syntax, $ in CRDS/UNOS syntax).
2705 '!' for the cc register (used in an `and to cc' insn).
2706 '$' for the letter `s' in an op code, but only on the 68040.
2707 '&' for the letter `d' in an op code, but only on the 68040.
2708 '/' for register prefix needed by longlong.h.
2709
2710 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2711 'd' to force memory addressing to be absolute, not relative.
2712 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2713 'o' for operands to go directly to output_operand_address (bypassing
2714 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2715 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2716 than directly). Second part of 'y' below.
2717 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2718 or print pair of registers as rx:ry.
2719 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2720 CONST_DOUBLE's as SunFPA constant RAM registers if
2721 possible, so it should not be used except for the SunFPA.
2722
2723 */
2724
2725 void
2726 print_operand (file, op, letter)
2727 FILE *file; /* file to write to */
2728 rtx op; /* operand to print */
2729 int letter; /* %<letter> or 0 */
2730 {
2731 #ifdef SUPPORT_SUN_FPA
2732 int i;
2733 #endif
2734
2735 if (letter == '.')
2736 {
2737 #if defined (MOTOROLA) && !defined (CRDS)
2738 asm_fprintf (file, ".");
2739 #endif
2740 }
2741 else if (letter == '#')
2742 {
2743 asm_fprintf (file, "%0I");
2744 }
2745 else if (letter == '-')
2746 {
2747 #ifdef MOTOROLA
2748 asm_fprintf (file, "-(%Rsp)");
2749 #else
2750 asm_fprintf (file, "%Rsp@-");
2751 #endif
2752 }
2753 else if (letter == '+')
2754 {
2755 #ifdef MOTOROLA
2756 asm_fprintf (file, "(%Rsp)+");
2757 #else
2758 asm_fprintf (file, "%Rsp@+");
2759 #endif
2760 }
2761 else if (letter == '@')
2762 {
2763 #ifdef MOTOROLA
2764 asm_fprintf (file, "(%Rsp)");
2765 #else
2766 asm_fprintf (file, "%Rsp@");
2767 #endif
2768 }
2769 else if (letter == '!')
2770 {
2771 asm_fprintf (file, "%Rfpcr");
2772 }
2773 else if (letter == '$')
2774 {
2775 if (TARGET_68040_ONLY)
2776 {
2777 fprintf (file, "s");
2778 }
2779 }
2780 else if (letter == '&')
2781 {
2782 if (TARGET_68040_ONLY)
2783 {
2784 fprintf (file, "d");
2785 }
2786 }
2787 else if (letter == '/')
2788 {
2789 asm_fprintf (file, "%R");
2790 }
2791 else if (letter == 'o')
2792 {
2793 /* This is only for direct addresses with TARGET_PCREL */
2794 if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
2795 || !TARGET_PCREL)
2796 abort ();
2797 output_addr_const (file, XEXP (op, 0));
2798 }
2799 else if (GET_CODE (op) == REG)
2800 {
2801 #ifdef SUPPORT_SUN_FPA
2802 if (REGNO (op) < 16
2803 && (letter == 'y' || letter == 'x')
2804 && GET_MODE (op) == DFmode)
2805 {
2806 fprintf (file, "%s:%s", reg_names[REGNO (op)],
2807 reg_names[REGNO (op)+1]);
2808 }
2809 else
2810 #endif
2811 {
2812 if (letter == 'R')
2813 /* Print out the second register name of a register pair.
2814 I.e., R (6) => 7. */
2815 fputs (reg_names[REGNO (op) + 1], file);
2816 else
2817 fputs (reg_names[REGNO (op)], file);
2818 }
2819 }
2820 else if (GET_CODE (op) == MEM)
2821 {
2822 output_address (XEXP (op, 0));
2823 if (letter == 'd' && ! TARGET_68020
2824 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2825 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2826 && INTVAL (XEXP (op, 0)) < 0x8000
2827 && INTVAL (XEXP (op, 0)) >= -0x8000))
2828 {
2829 #ifdef MOTOROLA
2830 fprintf (file, ".l");
2831 #else
2832 fprintf (file, ":l");
2833 #endif
2834 }
2835 }
2836 #ifdef SUPPORT_SUN_FPA
2837 else if ((letter == 'y' || letter == 'w')
2838 && GET_CODE (op) == CONST_DOUBLE
2839 && (i = standard_sun_fpa_constant_p (op)))
2840 {
2841 fprintf (file, "%%%d", i & 0x1ff);
2842 }
2843 #endif
2844 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2845 {
2846 REAL_VALUE_TYPE r;
2847 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2848 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2849 }
2850 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2851 {
2852 REAL_VALUE_TYPE r;
2853 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2854 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
2855 }
2856 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
2857 {
2858 REAL_VALUE_TYPE r;
2859 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2860 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
2861 }
2862 else
2863 {
2864 /* Use `print_operand_address' instead of `output_addr_const'
2865 to ensure that we print relevant PIC stuff. */
2866 asm_fprintf (file, "%0I");
2867 if (TARGET_PCREL
2868 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
2869 print_operand_address (file, op);
2870 else
2871 output_addr_const (file, op);
2872 }
2873 }
2874
2875 \f
2876 /* A C compound statement to output to stdio stream STREAM the
2877 assembler syntax for an instruction operand that is a memory
2878 reference whose address is ADDR. ADDR is an RTL expression.
2879
2880 Note that this contains a kludge that knows that the only reason
2881 we have an address (plus (label_ref...) (reg...)) when not generating
2882 PIC code is in the insn before a tablejump, and we know that m68k.md
2883 generates a label LInnn: on such an insn.
2884
2885 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2886 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2887
2888 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2889 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2890 we want. This difference can be accommodated by using an assembler
2891 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2892 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2893 macro. See m68k/sgs.h for an example; for versions without the bug.
2894 Some assemblers refuse all the above solutions. The workaround is to
2895 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2896 right behaviour.
2897
2898 They also do not like things like "pea 1.w", so we simple leave off
2899 the .w on small constants.
2900
2901 This routine is responsible for distinguishing between -fpic and -fPIC
2902 style relocations in an address. When generating -fpic code the
2903 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2904 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2905
2906 #ifndef ASM_OUTPUT_CASE_FETCH
2907 #ifdef MOTOROLA
2908 #ifdef SGS
2909 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2910 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2911 #else
2912 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2913 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2914 #endif
2915 #else
2916 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2917 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2918 #endif
2919 #endif /* ASM_OUTPUT_CASE_FETCH */
2920
2921 void
2922 print_operand_address (file, addr)
2923 FILE *file;
2924 rtx addr;
2925 {
2926 register rtx reg1, reg2, breg, ireg;
2927 rtx offset;
2928
2929 switch (GET_CODE (addr))
2930 {
2931 case REG:
2932 #ifdef MOTOROLA
2933 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2934 #else
2935 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2936 #endif
2937 break;
2938 case PRE_DEC:
2939 #ifdef MOTOROLA
2940 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2941 #else
2942 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2943 #endif
2944 break;
2945 case POST_INC:
2946 #ifdef MOTOROLA
2947 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2948 #else
2949 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2950 #endif
2951 break;
2952 case PLUS:
2953 reg1 = reg2 = ireg = breg = offset = 0;
2954 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2955 {
2956 offset = XEXP (addr, 0);
2957 addr = XEXP (addr, 1);
2958 }
2959 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2960 {
2961 offset = XEXP (addr, 1);
2962 addr = XEXP (addr, 0);
2963 }
2964 if (GET_CODE (addr) != PLUS)
2965 {
2966 ;
2967 }
2968 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2969 {
2970 reg1 = XEXP (addr, 0);
2971 addr = XEXP (addr, 1);
2972 }
2973 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2974 {
2975 reg1 = XEXP (addr, 1);
2976 addr = XEXP (addr, 0);
2977 }
2978 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2979 {
2980 reg1 = XEXP (addr, 0);
2981 addr = XEXP (addr, 1);
2982 }
2983 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2984 {
2985 reg1 = XEXP (addr, 1);
2986 addr = XEXP (addr, 0);
2987 }
2988 else if (GET_CODE (XEXP (addr, 0)) == REG)
2989 {
2990 reg1 = XEXP (addr, 0);
2991 addr = XEXP (addr, 1);
2992 }
2993 else if (GET_CODE (XEXP (addr, 1)) == REG)
2994 {
2995 reg1 = XEXP (addr, 1);
2996 addr = XEXP (addr, 0);
2997 }
2998 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2999 || GET_CODE (addr) == SIGN_EXTEND)
3000 {
3001 if (reg1 == 0)
3002 {
3003 reg1 = addr;
3004 }
3005 else
3006 {
3007 reg2 = addr;
3008 }
3009 addr = 0;
3010 }
3011 #if 0 /* for OLD_INDEXING */
3012 else if (GET_CODE (addr) == PLUS)
3013 {
3014 if (GET_CODE (XEXP (addr, 0)) == REG)
3015 {
3016 reg2 = XEXP (addr, 0);
3017 addr = XEXP (addr, 1);
3018 }
3019 else if (GET_CODE (XEXP (addr, 1)) == REG)
3020 {
3021 reg2 = XEXP (addr, 1);
3022 addr = XEXP (addr, 0);
3023 }
3024 }
3025 #endif
3026 if (offset != 0)
3027 {
3028 if (addr != 0)
3029 {
3030 abort ();
3031 }
3032 addr = offset;
3033 }
3034 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
3035 || GET_CODE (reg1) == MULT))
3036 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3037 {
3038 breg = reg2;
3039 ireg = reg1;
3040 }
3041 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3042 {
3043 breg = reg1;
3044 ireg = reg2;
3045 }
3046 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
3047 && ! (flag_pic && ireg == pic_offset_table_rtx))
3048 {
3049 int scale = 1;
3050 if (GET_CODE (ireg) == MULT)
3051 {
3052 scale = INTVAL (XEXP (ireg, 1));
3053 ireg = XEXP (ireg, 0);
3054 }
3055 if (GET_CODE (ireg) == SIGN_EXTEND)
3056 {
3057 ASM_OUTPUT_CASE_FETCH (file,
3058 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3059 reg_names[REGNO (XEXP (ireg, 0))]);
3060 fprintf (file, "w");
3061 }
3062 else
3063 {
3064 ASM_OUTPUT_CASE_FETCH (file,
3065 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3066 reg_names[REGNO (ireg)]);
3067 fprintf (file, "l");
3068 }
3069 if (scale != 1)
3070 {
3071 #ifdef MOTOROLA
3072 fprintf (file, "*%d", scale);
3073 #else
3074 fprintf (file, ":%d", scale);
3075 #endif
3076 }
3077 putc (')', file);
3078 break;
3079 }
3080 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
3081 && ! (flag_pic && breg == pic_offset_table_rtx))
3082 {
3083 ASM_OUTPUT_CASE_FETCH (file,
3084 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3085 reg_names[REGNO (breg)]);
3086 fprintf (file, "l)");
3087 break;
3088 }
3089 if (ireg != 0 || breg != 0)
3090 {
3091 int scale = 1;
3092 if (breg == 0)
3093 {
3094 abort ();
3095 }
3096 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
3097 {
3098 abort ();
3099 }
3100 #ifdef MOTOROLA
3101 if (addr != 0)
3102 {
3103 output_addr_const (file, addr);
3104 if (flag_pic && (breg == pic_offset_table_rtx))
3105 {
3106 fprintf (file, "@GOT");
3107 if (flag_pic == 1)
3108 fprintf (file, ".w");
3109 }
3110 }
3111 fprintf (file, "(%s", reg_names[REGNO (breg)]);
3112 if (ireg != 0)
3113 {
3114 putc (',', file);
3115 }
3116 #else
3117 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
3118 if (addr != 0)
3119 {
3120 output_addr_const (file, addr);
3121 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
3122 fprintf (file, ":w");
3123 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
3124 fprintf (file, ":l");
3125 }
3126 if (addr != 0 && ireg != 0)
3127 {
3128 putc (',', file);
3129 }
3130 #endif
3131 if (ireg != 0 && GET_CODE (ireg) == MULT)
3132 {
3133 scale = INTVAL (XEXP (ireg, 1));
3134 ireg = XEXP (ireg, 0);
3135 }
3136 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
3137 {
3138 #ifdef MOTOROLA
3139 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
3140 #else
3141 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
3142 #endif
3143 }
3144 else if (ireg != 0)
3145 {
3146 #ifdef MOTOROLA
3147 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3148 #else
3149 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3150 #endif
3151 }
3152 if (scale != 1)
3153 {
3154 #ifdef MOTOROLA
3155 fprintf (file, "*%d", scale);
3156 #else
3157 fprintf (file, ":%d", scale);
3158 #endif
3159 }
3160 putc (')', file);
3161 break;
3162 }
3163 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
3164 && ! (flag_pic && reg1 == pic_offset_table_rtx))
3165 {
3166 ASM_OUTPUT_CASE_FETCH (file,
3167 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3168 reg_names[REGNO (reg1)]);
3169 fprintf (file, "l)");
3170 break;
3171 }
3172 /* FALL-THROUGH (is this really what we want?) */
3173 default:
3174 if (GET_CODE (addr) == CONST_INT
3175 && INTVAL (addr) < 0x8000
3176 && INTVAL (addr) >= -0x8000)
3177 {
3178 #ifdef MOTOROLA
3179 #ifdef SGS
3180 /* Many SGS assemblers croak on size specifiers for constants. */
3181 fprintf (file, "%d", INTVAL (addr));
3182 #else
3183 fprintf (file, "%d.w", INTVAL (addr));
3184 #endif
3185 #else
3186 fprintf (file, "%d:w", INTVAL (addr));
3187 #endif
3188 }
3189 else if (GET_CODE (addr) == CONST_INT)
3190 {
3191 fprintf (file,
3192 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
3193 "%d",
3194 #else
3195 "%ld",
3196 #endif
3197 INTVAL (addr));
3198 }
3199 else if (TARGET_PCREL)
3200 {
3201 fputc ('(', file);
3202 output_addr_const (file, addr);
3203 if (flag_pic == 1)
3204 asm_fprintf (file, ":w,%Rpc)");
3205 else
3206 asm_fprintf (file, ":l,%Rpc)");
3207 }
3208 else
3209 {
3210 /* Special case for SYMBOL_REF if the symbol name ends in
3211 `.<letter>', this can be mistaken as a size suffix. Put
3212 the name in parentheses. */
3213 if (GET_CODE (addr) == SYMBOL_REF
3214 && strlen (XSTR (addr, 0)) > 2
3215 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3216 {
3217 putc ('(', file);
3218 output_addr_const (file, addr);
3219 putc (')', file);
3220 }
3221 else
3222 output_addr_const (file, addr);
3223 }
3224 break;
3225 }
3226 }
3227 \f
3228 /* Check for cases where a clr insns can be omitted from code using
3229 strict_low_part sets. For example, the second clrl here is not needed:
3230 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3231
3232 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3233 insn we are checking for redundancy. TARGET is the register set by the
3234 clear insn. */
3235
3236 int
3237 strict_low_part_peephole_ok (mode, first_insn, target)
3238 enum machine_mode mode;
3239 rtx first_insn;
3240 rtx target;
3241 {
3242 rtx p;
3243
3244 p = prev_nonnote_insn (first_insn);
3245
3246 while (p)
3247 {
3248 /* If it isn't an insn, then give up. */
3249 if (GET_CODE (p) != INSN)
3250 return 0;
3251
3252 if (reg_set_p (target, p))
3253 {
3254 rtx set = single_set (p);
3255 rtx dest;
3256
3257 /* If it isn't an easy to recognize insn, then give up. */
3258 if (! set)
3259 return 0;
3260
3261 dest = SET_DEST (set);
3262
3263 /* If this sets the entire target register to zero, then our
3264 first_insn is redundant. */
3265 if (rtx_equal_p (dest, target)
3266 && SET_SRC (set) == const0_rtx)
3267 return 1;
3268 else if (GET_CODE (dest) == STRICT_LOW_PART
3269 && GET_CODE (XEXP (dest, 0)) == REG
3270 && REGNO (XEXP (dest, 0)) == REGNO (target)
3271 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3272 <= GET_MODE_SIZE (mode)))
3273 /* This is a strict low part set which modifies less than
3274 we are using, so it is safe. */
3275 ;
3276 else
3277 return 0;
3278 }
3279
3280 p = prev_nonnote_insn (p);
3281
3282 }
3283
3284 return 0;
3285 }
3286
3287 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3288 range carefully since this predicate is used in DImode contexts. Also, we
3289 need some extra crud to make it work when hosted on 64-bit machines. */
3290
3291 int
3292 const_uint32_operand (op, mode)
3293 rtx op;
3294 enum machine_mode mode ATTRIBUTE_UNUSED;
3295 {
3296 #if HOST_BITS_PER_WIDE_INT > 32
3297 /* All allowed constants will fit a CONST_INT. */
3298 return (GET_CODE (op) == CONST_INT
3299 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3300 #else
3301 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
3302 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3303 #endif
3304 }
3305
3306 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3307 to check the range carefully since this predicate is used in DImode
3308 contexts. */
3309
3310 int
3311 const_sint32_operand (op, mode)
3312 rtx op;
3313 enum machine_mode mode ATTRIBUTE_UNUSED;
3314 {
3315 /* All allowed constants will fit a CONST_INT. */
3316 return (GET_CODE (op) == CONST_INT
3317 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3318 }
3319
3320 /* Operand predicates for implementing asymmetric pc-relative addressing
3321 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3322 when used as a source operand, but not as a destintation operand.
3323
3324 We model this by restricting the meaning of the basic predicates
3325 (general_operand, memory_operand, etc) to forbid the use of this
3326 addressing mode, and then define the following predicates that permit
3327 this addressing mode. These predicates can then be used for the
3328 source operands of the appropriate instructions.
3329
3330 n.b. While it is theoretically possible to change all machine patterns
3331 to use this addressing more where permitted by the architecture,
3332 it has only been implemented for "common" cases: SImode, HImode, and
3333 QImode operands, and only for the principle operations that would
3334 require this addressing mode: data movement and simple integer operations.
3335
3336 In parallel with these new predicates, two new constraint letters
3337 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3338 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3339 In the pcrel case 's' is only valid in combination with 'a' registers.
3340 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3341 of how these constraints are used.
3342
3343 The use of these predicates is strictly optional, though patterns that
3344 don't will cause an extra reload register to be allocated where one
3345 was not necessary:
3346
3347 lea (abc:w,%pc),%a0 ; need to reload address
3348 moveq &1,%d1 ; since write to pc-relative space
3349 movel %d1,%a0@ ; is not allowed
3350 ...
3351 lea (abc:w,%pc),%a1 ; no need to reload address here
3352 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3353
3354 For more info, consult tiemann@cygnus.com.
3355
3356
3357 All of the ugliness with predicates and constraints is due to the
3358 simple fact that the m68k does not allow a pc-relative addressing
3359 mode as a destination. gcc does not distinguish between source and
3360 destination addresses. Hence, if we claim that pc-relative address
3361 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3362 end up with invalid code. To get around this problem, we left
3363 pc-relative modes as invalid addresses, and then added special
3364 predicates and constraints to accept them.
3365
3366 A cleaner way to handle this is to modify gcc to distinguish
3367 between source and destination addresses. We can then say that
3368 pc-relative is a valid source address but not a valid destination
3369 address, and hopefully avoid a lot of the predicate and constraint
3370 hackery. Unfortunately, this would be a pretty big change. It would
3371 be a useful change for a number of ports, but there aren't any current
3372 plans to undertake this.
3373
3374 ***************************************************************************/
3375
3376
3377 /* Special case of a general operand that's used as a source operand.
3378 Use this to permit reads from PC-relative memory when -mpcrel
3379 is specified. */
3380
3381 int
3382 general_src_operand (op, mode)
3383 rtx op;
3384 enum machine_mode mode;
3385 {
3386 if (TARGET_PCREL
3387 && GET_CODE (op) == MEM
3388 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3389 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3390 || GET_CODE (XEXP (op, 0)) == CONST))
3391 return 1;
3392 return general_operand (op, mode);
3393 }
3394
3395 /* Special case of a nonimmediate operand that's used as a source.
3396 Use this to permit reads from PC-relative memory when -mpcrel
3397 is specified. */
3398
3399 int
3400 nonimmediate_src_operand (op, mode)
3401 rtx op;
3402 enum machine_mode mode;
3403 {
3404 if (TARGET_PCREL && GET_CODE (op) == MEM
3405 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3406 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3407 || GET_CODE (XEXP (op, 0)) == CONST))
3408 return 1;
3409 return nonimmediate_operand (op, mode);
3410 }
3411
3412 /* Special case of a memory operand that's used as a source.
3413 Use this to permit reads from PC-relative memory when -mpcrel
3414 is specified. */
3415
3416 int
3417 memory_src_operand (op, mode)
3418 rtx op;
3419 enum machine_mode mode;
3420 {
3421 if (TARGET_PCREL && GET_CODE (op) == MEM
3422 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3423 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3424 || GET_CODE (XEXP (op, 0)) == CONST))
3425 return 1;
3426 return memory_operand (op, mode);
3427 }
3428
3429 /* Predicate that accepts only a pc-relative address. This is needed
3430 because pc-relative addresses don't satisfy the predicate
3431 "general_src_operand". */
3432
3433 int
3434 pcrel_address (op, mode)
3435 rtx op;
3436 enum machine_mode mode;
3437 {
3438 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF
3439 || GET_CODE (op) == CONST);
3440 }
3441
3442 char *
3443 output_andsi3 (operands)
3444 rtx *operands;
3445 {
3446 int logval;
3447 if (GET_CODE (operands[2]) == CONST_INT
3448 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3449 && (DATA_REG_P (operands[0])
3450 || offsettable_memref_p (operands[0]))
3451 && !TARGET_5200)
3452 {
3453 if (GET_CODE (operands[0]) != REG)
3454 operands[0] = adj_offsettable_operand (operands[0], 2);
3455 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
3456 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3457 CC_STATUS_INIT;
3458 if (operands[2] == const0_rtx)
3459 return "clr%.w %0";
3460 return "and%.w %2,%0";
3461 }
3462 if (GET_CODE (operands[2]) == CONST_INT
3463 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3464 && (DATA_REG_P (operands[0])
3465 || offsettable_memref_p (operands[0])))
3466 {
3467 if (DATA_REG_P (operands[0]))
3468 {
3469 operands[1] = GEN_INT (logval);
3470 }
3471 else
3472 {
3473 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3474 operands[1] = GEN_INT (logval % 8);
3475 }
3476 /* This does not set condition codes in a standard way. */
3477 CC_STATUS_INIT;
3478 return "bclr %1,%0";
3479 }
3480 return "and%.l %2,%0";
3481 }
3482
3483 char *
3484 output_iorsi3 (operands)
3485 rtx *operands;
3486 {
3487 register int logval;
3488 if (GET_CODE (operands[2]) == CONST_INT
3489 && INTVAL (operands[2]) >> 16 == 0
3490 && (DATA_REG_P (operands[0])
3491 || offsettable_memref_p (operands[0]))
3492 && !TARGET_5200)
3493 {
3494 if (GET_CODE (operands[0]) != REG)
3495 operands[0] = adj_offsettable_operand (operands[0], 2);
3496 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3497 CC_STATUS_INIT;
3498 if (INTVAL (operands[2]) == 0xffff)
3499 return "mov%.w %2,%0";
3500 return "or%.w %2,%0";
3501 }
3502 if (GET_CODE (operands[2]) == CONST_INT
3503 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3504 && (DATA_REG_P (operands[0])
3505 || offsettable_memref_p (operands[0])))
3506 {
3507 if (DATA_REG_P (operands[0]))
3508 {
3509 operands[1] = GEN_INT (logval);
3510 }
3511 else
3512 {
3513 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3514 operands[1] = GEN_INT (logval % 8);
3515 }
3516 CC_STATUS_INIT;
3517 return "bset %1,%0";
3518 }
3519 return "or%.l %2,%0";
3520 }
3521
3522 char *
3523 output_xorsi3 (operands)
3524 rtx *operands;
3525 {
3526 register int logval;
3527 if (GET_CODE (operands[2]) == CONST_INT
3528 && INTVAL (operands[2]) >> 16 == 0
3529 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
3530 && !TARGET_5200)
3531 {
3532 if (! DATA_REG_P (operands[0]))
3533 operands[0] = adj_offsettable_operand (operands[0], 2);
3534 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3535 CC_STATUS_INIT;
3536 if (INTVAL (operands[2]) == 0xffff)
3537 return "not%.w %0";
3538 return "eor%.w %2,%0";
3539 }
3540 if (GET_CODE (operands[2]) == CONST_INT
3541 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3542 && (DATA_REG_P (operands[0])
3543 || offsettable_memref_p (operands[0])))
3544 {
3545 if (DATA_REG_P (operands[0]))
3546 {
3547 operands[1] = GEN_INT (logval);
3548 }
3549 else
3550 {
3551 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3552 operands[1] = GEN_INT (logval % 8);
3553 }
3554 CC_STATUS_INIT;
3555 return "bchg %1,%0";
3556 }
3557 return "eor%.l %2,%0";
3558 }