1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* These bits are controlled by all CPU selection options. Many options
205 also control MASK_68881, but some (notably -m68020) leave it alone. */
207 #define MASK_ALL_CPU_BITS \
208 (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
209 | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_BITFIELD)
211 /* Implement TARGET_HANDLE_OPTION. */
214 m68k_handle_option (size_t code
, const char *arg
, int value
)
219 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
220 target_flags
|= MASK_5200
;
224 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
225 target_flags
|= MASK_5200
| MASK_CF_HWDIV
;
229 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
230 target_flags
|= MASK_528x
| MASK_CF_HWDIV
;
234 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
235 target_flags
|= MASK_CFV3
| MASK_CF_HWDIV
;
239 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
240 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
;
245 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
250 target_flags
&= ~MASK_ALL_CPU_BITS
;
251 target_flags
|= MASK_68020
| MASK_BITFIELD
;
255 target_flags
&= ~MASK_ALL_CPU_BITS
;
256 target_flags
|= MASK_BITFIELD
| MASK_68881
| MASK_68020
| MASK_68040
;
260 target_flags
&= ~MASK_ALL_CPU_BITS
;
261 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68020
262 | MASK_68040
| MASK_68060
);
266 target_flags
&= ~MASK_ALL_CPU_BITS
;
267 target_flags
|= MASK_68020
| MASK_68030
| MASK_BITFIELD
;
271 target_flags
&= ~MASK_ALL_CPU_BITS
;
272 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
273 | MASK_68040_ONLY
| MASK_68040
);
277 target_flags
&= ~MASK_ALL_CPU_BITS
;
278 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
279 | MASK_68040_ONLY
| MASK_68060
);
283 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
288 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
289 target_flags
|= MASK_68020
;
292 case OPT_mshared_library_id_
:
293 if (value
> MAX_LIBRARY_ID
)
294 error ("-mshared-library-id=%s is not between 0 and %d",
295 arg
, MAX_LIBRARY_ID
);
297 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
305 /* Sometimes certain combinations of command options do not make
306 sense on a particular target machine. You can define a macro
307 `OVERRIDE_OPTIONS' to take account of this. This macro, if
308 defined, is executed once just after all the command options have
311 Don't use this macro to turn on various extra optimizations for
312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
315 override_options (void)
317 /* Sanity check to ensure that msep-data and mid-sahred-library are not
318 * both specified together. Doing so simply doesn't make sense.
320 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
321 error ("cannot specify both -msep-data and -mid-shared-library");
323 /* If we're generating code for a separate A5 relative data segment,
324 * we've got to enable -fPIC as well. This might be relaxable to
325 * -fpic but it hasn't been tested properly.
327 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
330 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
332 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
333 error ("-fPIC is not currently supported on the 68000 or 68010");
335 /* ??? A historic way of turning on pic, or is this intended to
336 be an embedded thing that doesn't have the same name binding
337 significance that it does on hosted ELF systems? */
338 if (TARGET_PCREL
&& flag_pic
== 0)
341 /* Turn off function cse if we are doing PIC. We always want function call
342 to be done as `bsr foo@PLTPC', so it will force the assembler to create
343 the PLT entry for `foo'. Doing function cse will cause the address of
344 `foo' to be loaded into a register, which is exactly what we want to
345 avoid when we are doing PIC on svr4 m68k. */
347 flag_no_function_cse
= 1;
349 SUBTARGET_OVERRIDE_OPTIONS
;
352 /* Return nonzero if FUNC is an interrupt function as specified by the
353 "interrupt_handler" attribute. */
355 m68k_interrupt_function_p(tree func
)
359 if (TREE_CODE (func
) != FUNCTION_DECL
)
362 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
363 return (a
!= NULL_TREE
);
366 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
367 struct attribute_spec.handler. */
369 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
370 tree args ATTRIBUTE_UNUSED
,
371 int flags ATTRIBUTE_UNUSED
,
374 if (TREE_CODE (*node
) != FUNCTION_DECL
)
376 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
377 IDENTIFIER_POINTER (name
));
378 *no_add_attrs
= true;
385 m68k_compute_frame_layout (void)
388 unsigned int mask
, rmask
;
389 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
391 /* Only compute the frame once per function.
392 Don't cache information until reload has been completed. */
393 if (current_frame
.funcdef_no
== current_function_funcdef_no
397 current_frame
.size
= (get_frame_size () + 3) & -4;
399 mask
= rmask
= saved
= 0;
400 for (regno
= 0; regno
< 16; regno
++)
401 if (m68k_save_reg (regno
, interrupt_handler
))
404 rmask
|= 1 << (15 - regno
);
407 current_frame
.offset
= saved
* 4;
408 current_frame
.reg_no
= saved
;
409 current_frame
.reg_mask
= mask
;
410 current_frame
.reg_rev_mask
= rmask
;
412 current_frame
.foffset
= 0;
413 mask
= rmask
= saved
= 0;
414 if (TARGET_68881
/* || TARGET_CFV4E */)
416 for (regno
= 16; regno
< 24; regno
++)
417 if (m68k_save_reg (regno
, interrupt_handler
))
419 mask
|= 1 << (regno
- 16);
420 rmask
|= 1 << (23 - regno
);
423 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
424 current_frame
.offset
+= current_frame
.foffset
;
426 current_frame
.fpu_no
= saved
;
427 current_frame
.fpu_mask
= mask
;
428 current_frame
.fpu_rev_mask
= rmask
;
430 /* Remember what function this frame refers to. */
431 current_frame
.funcdef_no
= current_function_funcdef_no
;
435 m68k_initial_elimination_offset (int from
, int to
)
438 /* The arg pointer points 8 bytes before the start of the arguments,
439 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
440 frame pointer in most frames. */
441 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
442 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
443 return argptr_offset
;
445 m68k_compute_frame_layout ();
447 gcc_assert (to
== STACK_POINTER_REGNUM
);
450 case ARG_POINTER_REGNUM
:
451 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
452 case FRAME_POINTER_REGNUM
:
453 return current_frame
.offset
+ current_frame
.size
;
459 /* Refer to the array `regs_ever_live' to determine which registers
460 to save; `regs_ever_live[I]' is nonzero if register number I
461 is ever used in the function. This function is responsible for
462 knowing which registers should not be saved even if used.
463 Return true if we need to save REGNO. */
466 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
468 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
470 if (current_function_uses_pic_offset_table
)
472 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
476 if (current_function_calls_eh_return
)
481 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
482 if (test
== INVALID_REGNUM
)
489 /* Fixed regs we never touch. */
490 if (fixed_regs
[regno
])
493 /* The frame pointer (if it is such) is handled specially. */
494 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
497 /* Interrupt handlers must also save call_used_regs
498 if they are live or when calling nested functions. */
499 if (interrupt_handler
)
501 if (regs_ever_live
[regno
])
504 if (!current_function_is_leaf
&& call_used_regs
[regno
])
508 /* Never need to save registers that aren't touched. */
509 if (!regs_ever_live
[regno
])
512 /* Otherwise save everything that isn't call-clobbered. */
513 return !call_used_regs
[regno
];
516 /* This function generates the assembly code for function entry.
517 STREAM is a stdio stream to output the code to.
518 SIZE is an int: how many units of temporary storage to allocate. */
521 m68k_output_function_prologue (FILE *stream
,
522 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
524 HOST_WIDE_INT fsize_with_regs
;
525 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
527 m68k_compute_frame_layout();
529 /* If the stack limit is a symbol, we can check it here,
530 before actually allocating the space. */
531 if (current_function_limit_stack
532 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
533 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
534 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
536 /* On ColdFire add register save into initial stack frame setup, if possible. */
537 fsize_with_regs
= current_frame
.size
;
538 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
539 fsize_with_regs
+= current_frame
.reg_no
* 4;
541 if (frame_pointer_needed
)
543 if (current_frame
.size
== 0 && TARGET_68040
)
544 /* on the 68040, pea + move is faster than link.w 0 */
545 fprintf (stream
, (MOTOROLA
546 ? "\tpea (%s)\n\tmove.l %s,%s\n"
547 : "\tpea %s@\n\tmovel %s,%s\n"),
548 M68K_REGNAME (FRAME_POINTER_REGNUM
),
549 M68K_REGNAME (STACK_POINTER_REGNUM
),
550 M68K_REGNAME (FRAME_POINTER_REGNUM
));
551 else if (fsize_with_regs
< 0x8000)
552 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
553 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
554 else if (TARGET_68020
)
555 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
556 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
558 /* Adding negative number is faster on the 68040. */
560 "\tlink" ASM_DOTW
" %s,%I0\n"
561 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
562 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
564 else if (fsize_with_regs
) /* !frame_pointer_needed */
566 if (fsize_with_regs
< 0x8000)
568 if (fsize_with_regs
<= 8)
570 if (!TARGET_COLDFIRE
)
571 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
574 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
577 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
578 /* On the CPU32 it is faster to use two subqw instructions to
579 subtract a small integer (8 < N <= 16) to a register. */
581 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
582 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
583 fsize_with_regs
- 8);
584 else if (TARGET_68040
)
585 /* Adding negative number is faster on the 68040. */
586 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
589 asm_fprintf (stream
, (MOTOROLA
590 ? "\tlea (%wd,%Rsp),%Rsp\n"
591 : "\tlea %Rsp@(%wd),%Rsp\n"),
594 else /* fsize_with_regs >= 0x8000 */
595 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
597 } /* !frame_pointer_needed */
599 if (dwarf2out_do_frame ())
601 if (frame_pointer_needed
)
604 l
= (char *) dwarf2out_cfi_label ();
606 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
607 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
608 cfa_offset
+= current_frame
.size
;
612 cfa_offset
+= current_frame
.size
;
613 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
617 if (current_frame
.fpu_mask
)
619 asm_fprintf (stream
, (MOTOROLA
620 ? "\tfmovm %I0x%x,-(%Rsp)\n"
621 : "\tfmovem %I0x%x,%Rsp@-\n"),
622 current_frame
.fpu_mask
);
624 if (dwarf2out_do_frame ())
626 char *l
= (char *) dwarf2out_cfi_label ();
629 cfa_offset
+= current_frame
.fpu_no
* 12;
630 if (! frame_pointer_needed
)
631 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
632 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
633 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
634 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
638 /* If the stack limit is not a symbol, check it here.
639 This has the disadvantage that it may be too late... */
640 if (current_function_limit_stack
)
642 if (REG_P (stack_limit_rtx
))
643 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
644 M68K_REGNAME (REGNO (stack_limit_rtx
)));
645 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
646 warning (0, "stack limit expression is not supported");
649 if (current_frame
.reg_no
<= 2)
651 /* Store each separately in the same order moveml uses.
652 Using two movel instructions instead of a single moveml
653 is about 15% faster for the 68020 and 68030 at no expense
658 for (i
= 0; i
< 16; i
++)
659 if (current_frame
.reg_rev_mask
& (1 << i
))
661 asm_fprintf (stream
, (MOTOROLA
662 ? "\t%Omove.l %s,-(%Rsp)\n"
663 : "\tmovel %s,%Rsp@-\n"),
664 M68K_REGNAME (15 - i
));
665 if (dwarf2out_do_frame ())
667 char *l
= (char *) dwarf2out_cfi_label ();
670 if (! frame_pointer_needed
)
671 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
672 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
676 else if (current_frame
.reg_rev_mask
)
679 /* The ColdFire does not support the predecrement form of the
680 MOVEM instruction, so we must adjust the stack pointer and
681 then use the plain address register indirect mode.
682 The required register save space was combined earlier with
683 the fsize_with_regs amount. */
685 asm_fprintf (stream
, (MOTOROLA
686 ? "\tmovm.l %I0x%x,(%Rsp)\n"
687 : "\tmoveml %I0x%x,%Rsp@\n"),
688 current_frame
.reg_mask
);
690 asm_fprintf (stream
, (MOTOROLA
691 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
692 : "\tmoveml %I0x%x,%Rsp@-\n"),
693 current_frame
.reg_rev_mask
);
694 if (dwarf2out_do_frame ())
696 char *l
= (char *) dwarf2out_cfi_label ();
699 cfa_offset
+= current_frame
.reg_no
* 4;
700 if (! frame_pointer_needed
)
701 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
702 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
703 if (current_frame
.reg_mask
& (1 << regno
))
704 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
707 if (!TARGET_SEP_DATA
&& flag_pic
708 && (current_function_uses_pic_offset_table
709 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
711 if (TARGET_ID_SHARED_LIBRARY
)
713 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
714 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
715 m68k_library_id_string
,
716 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
722 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
723 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
726 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
727 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
728 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
729 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
730 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
736 /* Return true if this function's epilogue can be output as RTL. */
739 use_return_insn (void)
741 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
744 /* We can output the epilogue as RTL only if no registers need to be
746 m68k_compute_frame_layout ();
747 return current_frame
.reg_no
? false : true;
750 /* This function generates the assembly code for function exit,
751 on machines that need it.
753 The function epilogue should not depend on the current stack pointer!
754 It should use the frame pointer only, if there is a frame pointer.
755 This is mandatory because of alloca; we also take advantage of it to
756 omit stack adjustments before returning. */
759 m68k_output_function_epilogue (FILE *stream
,
760 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
762 HOST_WIDE_INT fsize
, fsize_with_regs
;
764 bool restore_from_sp
= false;
765 rtx insn
= get_last_insn ();
767 m68k_compute_frame_layout ();
769 /* If the last insn was a BARRIER, we don't have to write any code. */
770 if (GET_CODE (insn
) == NOTE
)
771 insn
= prev_nonnote_insn (insn
);
772 if (insn
&& GET_CODE (insn
) == BARRIER
)
774 /* Output just a no-op so that debuggers don't get confused
775 about which function the pc is in at this address. */
776 fprintf (stream
, "\tnop\n");
780 #ifdef FUNCTION_EXTRA_EPILOGUE
781 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
784 fsize
= current_frame
.size
;
786 /* FIXME: leaf_function_p below is too strong.
787 What we really need to know there is if there could be pending
788 stack adjustment needed at that point. */
790 = (! frame_pointer_needed
791 || (! current_function_calls_alloca
&& leaf_function_p ()));
793 /* fsize_with_regs is the size we need to adjust the sp when
794 popping the frame. */
795 fsize_with_regs
= fsize
;
797 /* Because the ColdFire doesn't support moveml with
798 complex address modes, we must adjust the stack manually
799 after restoring registers. When the frame pointer isn't used,
800 we can merge movem adjustment into frame unlinking
801 made immediately after it. */
802 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
803 fsize_with_regs
+= current_frame
.reg_no
* 4;
805 if (current_frame
.offset
+ fsize
>= 0x8000
807 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
809 /* Because the ColdFire doesn't support moveml with
810 complex address modes we make an extra correction here. */
812 fsize
+= current_frame
.offset
;
814 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
815 fsize
= 0, big
= true;
817 if (current_frame
.reg_no
<= 2)
819 /* Restore each separately in the same order moveml does.
820 Using two movel instructions instead of a single moveml
821 is about 15% faster for the 68020 and 68030 at no expense
825 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
827 for (i
= 0; i
< 16; i
++)
828 if (current_frame
.reg_mask
& (1 << i
))
833 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
835 M68K_REGNAME (FRAME_POINTER_REGNUM
),
838 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
839 M68K_REGNAME (FRAME_POINTER_REGNUM
),
843 else if (restore_from_sp
)
844 asm_fprintf (stream
, (MOTOROLA
845 ? "\t%Omove.l (%Rsp)+,%s\n"
846 : "\tmovel %Rsp@+,%s\n"),
851 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
853 M68K_REGNAME (FRAME_POINTER_REGNUM
),
856 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
857 M68K_REGNAME (FRAME_POINTER_REGNUM
),
864 else if (current_frame
.reg_mask
)
866 /* The ColdFire requires special handling due to its limited moveml
872 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
873 M68K_REGNAME (FRAME_POINTER_REGNUM
));
874 asm_fprintf (stream
, (MOTOROLA
875 ? "\tmovm.l (%Ra1),%I0x%x\n"
876 : "\tmoveml %Ra1@,%I0x%x\n"),
877 current_frame
.reg_mask
);
879 else if (restore_from_sp
)
880 asm_fprintf (stream
, (MOTOROLA
881 ? "\tmovm.l (%Rsp),%I0x%x\n"
882 : "\tmoveml %Rsp@,%I0x%x\n"),
883 current_frame
.reg_mask
);
887 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
888 current_frame
.offset
+ fsize
,
889 M68K_REGNAME (FRAME_POINTER_REGNUM
),
890 current_frame
.reg_mask
);
892 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
893 M68K_REGNAME (FRAME_POINTER_REGNUM
),
894 current_frame
.offset
+ fsize
,
895 current_frame
.reg_mask
);
898 else /* !TARGET_COLDFIRE */
903 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
904 current_frame
.offset
+ fsize
,
905 M68K_REGNAME (FRAME_POINTER_REGNUM
),
906 current_frame
.reg_mask
);
908 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
909 M68K_REGNAME (FRAME_POINTER_REGNUM
),
910 current_frame
.offset
+ fsize
,
911 current_frame
.reg_mask
);
913 else if (restore_from_sp
)
915 asm_fprintf (stream
, (MOTOROLA
916 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
917 : "\tmoveml %Rsp@+,%I0x%x\n"),
918 current_frame
.reg_mask
);
923 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
924 current_frame
.offset
+ fsize
,
925 M68K_REGNAME (FRAME_POINTER_REGNUM
),
926 current_frame
.reg_mask
);
928 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
929 M68K_REGNAME (FRAME_POINTER_REGNUM
),
930 current_frame
.offset
+ fsize
,
931 current_frame
.reg_mask
);
935 if (current_frame
.fpu_rev_mask
)
940 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
941 current_frame
.foffset
+ fsize
,
942 M68K_REGNAME (FRAME_POINTER_REGNUM
),
943 current_frame
.fpu_rev_mask
);
945 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
946 M68K_REGNAME (FRAME_POINTER_REGNUM
),
947 current_frame
.foffset
+ fsize
,
948 current_frame
.fpu_rev_mask
);
950 else if (restore_from_sp
)
953 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
954 current_frame
.fpu_rev_mask
);
956 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
957 current_frame
.fpu_rev_mask
);
962 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
963 current_frame
.foffset
+ fsize
,
964 M68K_REGNAME (FRAME_POINTER_REGNUM
),
965 current_frame
.fpu_rev_mask
);
967 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
968 M68K_REGNAME (FRAME_POINTER_REGNUM
),
969 current_frame
.foffset
+ fsize
,
970 current_frame
.fpu_rev_mask
);
973 if (frame_pointer_needed
)
974 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
975 else if (fsize_with_regs
)
977 if (fsize_with_regs
<= 8)
979 if (!TARGET_COLDFIRE
)
980 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
983 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
986 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
988 /* On the CPU32 it is faster to use two addqw instructions to
989 add a small integer (8 < N <= 16) to a register. */
991 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
992 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
993 fsize_with_regs
- 8);
995 else if (fsize_with_regs
< 0x8000)
998 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1001 asm_fprintf (stream
, (MOTOROLA
1002 ? "\tlea (%wd,%Rsp),%Rsp\n"
1003 : "\tlea %Rsp@(%wd),%Rsp\n"),
1007 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1009 if (current_function_calls_eh_return
)
1010 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1011 if (m68k_interrupt_function_p (current_function_decl
))
1012 fprintf (stream
, "\trte\n");
1013 else if (current_function_pops_args
)
1014 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1016 fprintf (stream
, "\trts\n");
1019 /* Return true if X is a valid comparison operator for the dbcc
1022 Note it rejects floating point comparison operators.
1023 (In the future we could use Fdbcc).
1025 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1028 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1030 switch (GET_CODE (x
))
1032 case EQ
: case NE
: case GTU
: case LTU
:
1036 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1038 case GT
: case LT
: case GE
: case LE
:
1039 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1045 /* Return nonzero if flags are currently in the 68881 flag register. */
1047 flags_in_68881 (void)
1049 /* We could add support for these in the future */
1050 return cc_status
.flags
& CC_IN_68881
;
1053 /* Output a BSR instruction suitable for PIC code. */
1055 m68k_output_pic_call (rtx dest
)
1059 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1061 /* We output a BSR instruction if we're building for a target that
1062 supports long branches. Otherwise we generate one of two sequences:
1063 a shorter one that uses a GOT entry or a longer one that doesn't.
1064 We'll use the -Os command-line flag to decide which to generate.
1065 Both sequences take the same time to execute on the ColdFire. */
1066 else if (TARGET_PCREL
)
1068 else if (TARGET_68020
)
1069 #if defined(USE_GAS)
1070 out
= "bsr.l %0@PLTPC";
1072 out
= "bsr %0@PLTPC";
1074 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1075 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1077 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1079 output_asm_insn (out
, &dest
);
1082 /* Output a dbCC; jCC sequence. Note we do not handle the
1083 floating point version of this sequence (Fdbcc). We also
1084 do not handle alternative conditions when CC_NO_OVERFLOW is
1085 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1086 kick those out before we get here. */
1089 output_dbcc_and_branch (rtx
*operands
)
1091 switch (GET_CODE (operands
[3]))
1094 output_asm_insn (MOTOROLA
1095 ? "dbeq %0,%l1\n\tjbeq %l2"
1096 : "dbeq %0,%l1\n\tjeq %l2",
1101 output_asm_insn (MOTOROLA
1102 ? "dbne %0,%l1\n\tjbne %l2"
1103 : "dbne %0,%l1\n\tjne %l2",
1108 output_asm_insn (MOTOROLA
1109 ? "dbgt %0,%l1\n\tjbgt %l2"
1110 : "dbgt %0,%l1\n\tjgt %l2",
1115 output_asm_insn (MOTOROLA
1116 ? "dbhi %0,%l1\n\tjbhi %l2"
1117 : "dbhi %0,%l1\n\tjhi %l2",
1122 output_asm_insn (MOTOROLA
1123 ? "dblt %0,%l1\n\tjblt %l2"
1124 : "dblt %0,%l1\n\tjlt %l2",
1129 output_asm_insn (MOTOROLA
1130 ? "dbcs %0,%l1\n\tjbcs %l2"
1131 : "dbcs %0,%l1\n\tjcs %l2",
1136 output_asm_insn (MOTOROLA
1137 ? "dbge %0,%l1\n\tjbge %l2"
1138 : "dbge %0,%l1\n\tjge %l2",
1143 output_asm_insn (MOTOROLA
1144 ? "dbcc %0,%l1\n\tjbcc %l2"
1145 : "dbcc %0,%l1\n\tjcc %l2",
1150 output_asm_insn (MOTOROLA
1151 ? "dble %0,%l1\n\tjble %l2"
1152 : "dble %0,%l1\n\tjle %l2",
1157 output_asm_insn (MOTOROLA
1158 ? "dbls %0,%l1\n\tjbls %l2"
1159 : "dbls %0,%l1\n\tjls %l2",
1167 /* If the decrement is to be done in SImode, then we have
1168 to compensate for the fact that dbcc decrements in HImode. */
1169 switch (GET_MODE (operands
[0]))
1172 output_asm_insn (MOTOROLA
1173 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1174 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1187 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1190 enum rtx_code op_code
= GET_CODE (op
);
1192 /* This does not produce a useful cc. */
1195 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1196 below. Swap the operands and change the op if these requirements
1197 are not fulfilled. */
1198 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1202 operand1
= operand2
;
1204 op_code
= swap_condition (op_code
);
1206 loperands
[0] = operand1
;
1207 if (GET_CODE (operand1
) == REG
)
1208 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1210 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1211 if (operand2
!= const0_rtx
)
1213 loperands
[2] = operand2
;
1214 if (GET_CODE (operand2
) == REG
)
1215 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1217 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1219 loperands
[4] = gen_label_rtx ();
1220 if (operand2
!= const0_rtx
)
1222 output_asm_insn (MOTOROLA
1223 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1224 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1229 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1230 output_asm_insn ("tst%.l %0", loperands
);
1232 output_asm_insn ("cmp%.w #0,%0", loperands
);
1234 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1236 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1237 output_asm_insn ("tst%.l %1", loperands
);
1239 output_asm_insn ("cmp%.w #0,%1", loperands
);
1242 loperands
[5] = dest
;
1247 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1248 CODE_LABEL_NUMBER (loperands
[4]));
1249 output_asm_insn ("seq %5", loperands
);
1253 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1254 CODE_LABEL_NUMBER (loperands
[4]));
1255 output_asm_insn ("sne %5", loperands
);
1259 loperands
[6] = gen_label_rtx ();
1260 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1262 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1263 CODE_LABEL_NUMBER (loperands
[4]));
1264 output_asm_insn ("sgt %5", loperands
);
1265 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1266 CODE_LABEL_NUMBER (loperands
[6]));
1270 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1271 CODE_LABEL_NUMBER (loperands
[4]));
1272 output_asm_insn ("shi %5", loperands
);
1276 loperands
[6] = gen_label_rtx ();
1277 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1279 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1280 CODE_LABEL_NUMBER (loperands
[4]));
1281 output_asm_insn ("slt %5", loperands
);
1282 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1283 CODE_LABEL_NUMBER (loperands
[6]));
1287 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1288 CODE_LABEL_NUMBER (loperands
[4]));
1289 output_asm_insn ("scs %5", loperands
);
1293 loperands
[6] = gen_label_rtx ();
1294 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1296 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1297 CODE_LABEL_NUMBER (loperands
[4]));
1298 output_asm_insn ("sge %5", loperands
);
1299 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1300 CODE_LABEL_NUMBER (loperands
[6]));
1304 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1305 CODE_LABEL_NUMBER (loperands
[4]));
1306 output_asm_insn ("scc %5", loperands
);
1310 loperands
[6] = gen_label_rtx ();
1311 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1313 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1314 CODE_LABEL_NUMBER (loperands
[4]));
1315 output_asm_insn ("sle %5", loperands
);
1316 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1317 CODE_LABEL_NUMBER (loperands
[6]));
1321 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1322 CODE_LABEL_NUMBER (loperands
[4]));
1323 output_asm_insn ("sls %5", loperands
);
1333 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1335 operands
[0] = countop
;
1336 operands
[1] = dataop
;
1338 if (GET_CODE (countop
) == CONST_INT
)
1340 register int count
= INTVAL (countop
);
1341 /* If COUNT is bigger than size of storage unit in use,
1342 advance to the containing unit of same size. */
1343 if (count
> signpos
)
1345 int offset
= (count
& ~signpos
) / 8;
1346 count
= count
& signpos
;
1347 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1349 if (count
== signpos
)
1350 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1352 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1354 /* These three statements used to use next_insns_test_no...
1355 but it appears that this should do the same job. */
1357 && next_insn_tests_no_inequality (insn
))
1360 && next_insn_tests_no_inequality (insn
))
1363 && next_insn_tests_no_inequality (insn
))
1366 cc_status
.flags
= CC_NOT_NEGATIVE
;
1368 return "btst %0,%1";
1371 /* Legitimize PIC addresses. If the address is already
1372 position-independent, we return ORIG. Newly generated
1373 position-independent addresses go to REG. If we need more
1374 than one register, we lose.
1376 An address is legitimized by making an indirect reference
1377 through the Global Offset Table with the name of the symbol
1380 The assembler and linker are responsible for placing the
1381 address of the symbol in the GOT. The function prologue
1382 is responsible for initializing a5 to the starting address
1385 The assembler is also responsible for translating a symbol name
1386 into a constant displacement from the start of the GOT.
1388 A quick example may make things a little clearer:
1390 When not generating PIC code to store the value 12345 into _foo
1391 we would generate the following code:
1395 When generating PIC two transformations are made. First, the compiler
1396 loads the address of foo into a register. So the first transformation makes:
1401 The code in movsi will intercept the lea instruction and call this
1402 routine which will transform the instructions into:
1404 movel a5@(_foo:w), a0
1408 That (in a nutshell) is how *all* symbol and label references are
1412 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1417 /* First handle a simple SYMBOL_REF or LABEL_REF */
1418 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1422 pic_ref
= gen_rtx_MEM (Pmode
,
1423 gen_rtx_PLUS (Pmode
,
1424 pic_offset_table_rtx
, orig
));
1425 current_function_uses_pic_offset_table
= 1;
1426 MEM_READONLY_P (pic_ref
) = 1;
1427 emit_move_insn (reg
, pic_ref
);
1430 else if (GET_CODE (orig
) == CONST
)
1434 /* Make sure this has not already been legitimized. */
1435 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1436 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1441 /* legitimize both operands of the PLUS */
1442 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1444 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1445 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1446 base
== reg
? 0 : reg
);
1448 if (GET_CODE (orig
) == CONST_INT
)
1449 return plus_constant (base
, INTVAL (orig
));
1450 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1451 /* Likewise, should we set special REG_NOTEs here? */
1457 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1459 static CONST_METHOD
const_method (rtx
);
1461 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1464 const_method (rtx constant
)
1469 i
= INTVAL (constant
);
1473 /* The ColdFire doesn't have byte or word operations. */
1474 /* FIXME: This may not be useful for the m68060 either. */
1475 if (!TARGET_COLDFIRE
)
1477 /* if -256 < N < 256 but N is not in range for a moveq
1478 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1479 if (USE_MOVQ (i
^ 0xff))
1481 /* Likewise, try with not.w */
1482 if (USE_MOVQ (i
^ 0xffff))
1484 /* This is the only value where neg.w is useful */
1489 /* Try also with swap. */
1491 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1496 /* Try using MVZ/MVS with an immediate value to load constants. */
1497 if (i
>= 0 && i
<= 65535)
1499 if (i
>= -32768 && i
<= 32767)
1503 /* Otherwise, use move.l */
1508 const_int_cost (rtx constant
)
1510 switch (const_method (constant
))
1513 /* Constants between -128 and 127 are cheap due to moveq. */
1521 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1531 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1536 /* Constant zero is super cheap due to clr instruction. */
1537 if (x
== const0_rtx
)
1540 *total
= const_int_cost (x
);
1550 /* Make 0.0 cheaper than other floating constants to
1551 encourage creating tstsf and tstdf insns. */
1552 if (outer_code
== COMPARE
1553 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1559 /* These are vaguely right for a 68020. */
1560 /* The costs for long multiply have been adjusted to work properly
1561 in synth_mult on the 68020, relative to an average of the time
1562 for add and the time for shift, taking away a little more because
1563 sometimes move insns are needed. */
1564 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1566 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 \
1567 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 \
1568 : TARGET_COLDFIRE ? 10 : 13)
1569 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 \
1570 : (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
1571 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1574 /* An lea costs about three times as much as a simple add. */
1575 if (GET_MODE (x
) == SImode
1576 && GET_CODE (XEXP (x
, 1)) == REG
1577 && GET_CODE (XEXP (x
, 0)) == MULT
1578 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1579 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1580 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1581 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1582 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1584 /* lea an@(dx:l:i),am */
1585 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1595 *total
= COSTS_N_INSNS(1);
1598 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1600 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1602 if (INTVAL (XEXP (x
, 1)) < 16)
1603 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1605 /* We're using clrw + swap for these cases. */
1606 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1609 *total
= COSTS_N_INSNS (10); /* Worst case. */
1612 /* A shift by a big integer takes an extra instruction. */
1613 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1614 && (INTVAL (XEXP (x
, 1)) == 16))
1616 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1619 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1620 && !(INTVAL (XEXP (x
, 1)) > 0
1621 && INTVAL (XEXP (x
, 1)) <= 8))
1623 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1629 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1630 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1631 && GET_MODE (x
) == SImode
)
1632 *total
= COSTS_N_INSNS (MULW_COST
);
1633 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1634 *total
= COSTS_N_INSNS (MULW_COST
);
1636 *total
= COSTS_N_INSNS (MULL_COST
);
1643 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1644 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1645 else if (TARGET_CF_HWDIV
)
1646 *total
= COSTS_N_INSNS (18);
1648 *total
= COSTS_N_INSNS (43); /* div.l */
1657 output_move_const_into_data_reg (rtx
*operands
)
1661 i
= INTVAL (operands
[1]);
1662 switch (const_method (operands
[1]))
1665 return "mvzw %1,%0";
1667 return "mvsw %1,%0";
1669 return "moveq %1,%0";
1672 operands
[1] = GEN_INT (i
^ 0xff);
1673 return "moveq %1,%0\n\tnot%.b %0";
1676 operands
[1] = GEN_INT (i
^ 0xffff);
1677 return "moveq %1,%0\n\tnot%.w %0";
1680 return "moveq #-128,%0\n\tneg%.w %0";
1685 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1686 return "moveq %1,%0\n\tswap %0";
1689 return "move%.l %1,%0";
1695 /* Return 1 if 'constant' can be represented by
1696 mov3q on a ColdFire V4 core. */
1698 valid_mov3q_const (rtx constant
)
1702 if (TARGET_CFV4
&& GET_CODE (constant
) == CONST_INT
)
1704 i
= INTVAL (constant
);
1705 if (i
== -1 || (i
>= 1 && i
<= 7))
1713 output_move_simode_const (rtx
*operands
)
1715 if (operands
[1] == const0_rtx
1716 && (DATA_REG_P (operands
[0])
1717 || GET_CODE (operands
[0]) == MEM
)
1718 /* clr insns on 68000 read before writing.
1719 This isn't so on the 68010, but we have no TARGET_68010. */
1720 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1721 || !(GET_CODE (operands
[0]) == MEM
1722 && MEM_VOLATILE_P (operands
[0]))))
1724 else if ((GET_MODE (operands
[0]) == SImode
)
1725 && valid_mov3q_const (operands
[1]))
1726 return "mov3q%.l %1,%0";
1727 else if (operands
[1] == const0_rtx
1728 && ADDRESS_REG_P (operands
[0]))
1729 return "sub%.l %0,%0";
1730 else if (DATA_REG_P (operands
[0]))
1731 return output_move_const_into_data_reg (operands
);
1732 else if (ADDRESS_REG_P (operands
[0])
1733 && INTVAL (operands
[1]) < 0x8000
1734 && INTVAL (operands
[1]) >= -0x8000)
1736 if (valid_mov3q_const (operands
[1]))
1737 return "mov3q%.l %1,%0";
1738 return "move%.w %1,%0";
1740 else if (GET_CODE (operands
[0]) == MEM
1741 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1742 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1743 && INTVAL (operands
[1]) < 0x8000
1744 && INTVAL (operands
[1]) >= -0x8000)
1746 if (valid_mov3q_const (operands
[1]))
1747 return "mov3q%.l %1,%-";
1750 return "move%.l %1,%0";
1754 output_move_simode (rtx
*operands
)
1756 if (GET_CODE (operands
[1]) == CONST_INT
)
1757 return output_move_simode_const (operands
);
1758 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1759 || GET_CODE (operands
[1]) == CONST
)
1760 && push_operand (operands
[0], SImode
))
1762 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1763 || GET_CODE (operands
[1]) == CONST
)
1764 && ADDRESS_REG_P (operands
[0]))
1765 return "lea %a1,%0";
1766 return "move%.l %1,%0";
1770 output_move_himode (rtx
*operands
)
1772 if (GET_CODE (operands
[1]) == CONST_INT
)
1774 if (operands
[1] == const0_rtx
1775 && (DATA_REG_P (operands
[0])
1776 || GET_CODE (operands
[0]) == MEM
)
1777 /* clr insns on 68000 read before writing.
1778 This isn't so on the 68010, but we have no TARGET_68010. */
1779 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1780 || !(GET_CODE (operands
[0]) == MEM
1781 && MEM_VOLATILE_P (operands
[0]))))
1783 else if (operands
[1] == const0_rtx
1784 && ADDRESS_REG_P (operands
[0]))
1785 return "sub%.l %0,%0";
1786 else if (DATA_REG_P (operands
[0])
1787 && INTVAL (operands
[1]) < 128
1788 && INTVAL (operands
[1]) >= -128)
1789 return "moveq %1,%0";
1790 else if (INTVAL (operands
[1]) < 0x8000
1791 && INTVAL (operands
[1]) >= -0x8000)
1792 return "move%.w %1,%0";
1794 else if (CONSTANT_P (operands
[1]))
1795 return "move%.l %1,%0";
1796 /* Recognize the insn before a tablejump, one that refers
1797 to a table of offsets. Such an insn will need to refer
1798 to a label on the insn. So output one. Use the label-number
1799 of the table of offsets to generate this label. This code,
1800 and similar code below, assumes that there will be at most one
1801 reference to each table. */
1802 if (GET_CODE (operands
[1]) == MEM
1803 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1804 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1805 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1807 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1809 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1810 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1812 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1813 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1815 return "move%.w %1,%0";
1819 output_move_qimode (rtx
*operands
)
1821 /* 68k family always modifies the stack pointer by at least 2, even for
1822 byte pushes. The 5200 (ColdFire) does not do this. */
1824 /* This case is generated by pushqi1 pattern now. */
1825 gcc_assert (!(GET_CODE (operands
[0]) == MEM
1826 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1827 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1828 && ! ADDRESS_REG_P (operands
[1])
1829 && ! TARGET_COLDFIRE
));
1831 /* clr and st insns on 68000 read before writing.
1832 This isn't so on the 68010, but we have no TARGET_68010. */
1833 if (!ADDRESS_REG_P (operands
[0])
1834 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1835 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1837 if (operands
[1] == const0_rtx
)
1839 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1840 && GET_CODE (operands
[1]) == CONST_INT
1841 && (INTVAL (operands
[1]) & 255) == 255)
1847 if (GET_CODE (operands
[1]) == CONST_INT
1848 && DATA_REG_P (operands
[0])
1849 && INTVAL (operands
[1]) < 128
1850 && INTVAL (operands
[1]) >= -128)
1851 return "moveq %1,%0";
1852 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1853 return "sub%.l %0,%0";
1854 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1855 return "move%.l %1,%0";
1856 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1857 from address registers. */
1858 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1859 return "move%.w %1,%0";
1860 return "move%.b %1,%0";
1864 output_move_stricthi (rtx
*operands
)
1866 if (operands
[1] == const0_rtx
1867 /* clr insns on 68000 read before writing.
1868 This isn't so on the 68010, but we have no TARGET_68010. */
1869 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1870 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1872 return "move%.w %1,%0";
1876 output_move_strictqi (rtx
*operands
)
1878 if (operands
[1] == const0_rtx
1879 /* clr insns on 68000 read before writing.
1880 This isn't so on the 68010, but we have no TARGET_68010. */
1881 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1882 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1884 return "move%.b %1,%0";
1887 /* Return the best assembler insn template
1888 for moving operands[1] into operands[0] as a fullword. */
1891 singlemove_string (rtx
*operands
)
1893 if (GET_CODE (operands
[1]) == CONST_INT
)
1894 return output_move_simode_const (operands
);
1895 return "move%.l %1,%0";
1899 /* Output assembler code to perform a doubleword move insn
1900 with operands OPERANDS. */
1903 output_move_double (rtx
*operands
)
1907 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1912 rtx addreg0
= 0, addreg1
= 0;
1913 int dest_overlapped_low
= 0;
1914 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1919 /* First classify both operands. */
1921 if (REG_P (operands
[0]))
1923 else if (offsettable_memref_p (operands
[0]))
1925 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1927 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1929 else if (GET_CODE (operands
[0]) == MEM
)
1934 if (REG_P (operands
[1]))
1936 else if (CONSTANT_P (operands
[1]))
1938 else if (offsettable_memref_p (operands
[1]))
1940 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1942 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1944 else if (GET_CODE (operands
[1]) == MEM
)
1949 /* Check for the cases that the operand constraints are not supposed
1950 to allow to happen. Generating code for these cases is
1952 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
1954 /* If one operand is decrementing and one is incrementing
1955 decrement the former register explicitly
1956 and change that operand into ordinary indexing. */
1958 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1960 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1962 output_asm_insn ("sub%.l #12,%0", operands
);
1964 output_asm_insn ("subq%.l #8,%0", operands
);
1965 if (GET_MODE (operands
[1]) == XFmode
)
1966 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1967 else if (GET_MODE (operands
[0]) == DFmode
)
1968 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1970 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1973 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1975 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1977 output_asm_insn ("sub%.l #12,%1", operands
);
1979 output_asm_insn ("subq%.l #8,%1", operands
);
1980 if (GET_MODE (operands
[1]) == XFmode
)
1981 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1982 else if (GET_MODE (operands
[1]) == DFmode
)
1983 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1985 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1989 /* If an operand is an unoffsettable memory ref, find a register
1990 we can increment temporarily to make it refer to the second word. */
1992 if (optype0
== MEMOP
)
1993 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1995 if (optype1
== MEMOP
)
1996 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1998 /* Ok, we can do one word at a time.
1999 Normally we do the low-numbered word first,
2000 but if either operand is autodecrementing then we
2001 do the high-numbered word first.
2003 In either case, set up in LATEHALF the operands to use
2004 for the high-numbered word and in some cases alter the
2005 operands in OPERANDS to be suitable for the low-numbered word. */
2009 if (optype0
== REGOP
)
2011 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2012 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2014 else if (optype0
== OFFSOP
)
2016 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2017 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2021 middlehalf
[0] = operands
[0];
2022 latehalf
[0] = operands
[0];
2025 if (optype1
== REGOP
)
2027 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2028 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2030 else if (optype1
== OFFSOP
)
2032 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2033 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2035 else if (optype1
== CNSTOP
)
2037 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2042 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2043 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2044 operands
[1] = GEN_INT (l
[0]);
2045 middlehalf
[1] = GEN_INT (l
[1]);
2046 latehalf
[1] = GEN_INT (l
[2]);
2050 /* No non-CONST_DOUBLE constant should ever appear
2052 gcc_assert (!CONSTANT_P (operands
[1]));
2057 middlehalf
[1] = operands
[1];
2058 latehalf
[1] = operands
[1];
2062 /* size is not 12: */
2064 if (optype0
== REGOP
)
2065 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2066 else if (optype0
== OFFSOP
)
2067 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2069 latehalf
[0] = operands
[0];
2071 if (optype1
== REGOP
)
2072 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2073 else if (optype1
== OFFSOP
)
2074 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2075 else if (optype1
== CNSTOP
)
2076 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2078 latehalf
[1] = operands
[1];
2081 /* If insn is effectively movd N(sp),-(sp) then we will do the
2082 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2083 for the low word as well, to compensate for the first decrement of sp. */
2084 if (optype0
== PUSHOP
2085 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2086 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2087 operands
[1] = middlehalf
[1] = latehalf
[1];
2089 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2090 if the upper part of reg N does not appear in the MEM, arrange to
2091 emit the move late-half first. Otherwise, compute the MEM address
2092 into the upper part of N and use that as a pointer to the memory
2094 if (optype0
== REGOP
2095 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2097 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2099 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2100 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2102 /* If both halves of dest are used in the src memory address,
2103 compute the address into latehalf of dest.
2104 Note that this can't happen if the dest is two data regs. */
2106 xops
[0] = latehalf
[0];
2107 xops
[1] = XEXP (operands
[1], 0);
2108 output_asm_insn ("lea %a1,%0", xops
);
2109 if (GET_MODE (operands
[1]) == XFmode
)
2111 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2112 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2113 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2117 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2118 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2122 && reg_overlap_mentioned_p (middlehalf
[0],
2123 XEXP (operands
[1], 0)))
2125 /* Check for two regs used by both source and dest.
2126 Note that this can't happen if the dest is all data regs.
2127 It can happen if the dest is d6, d7, a0.
2128 But in that case, latehalf is an addr reg, so
2129 the code at compadr does ok. */
2131 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2132 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2135 /* JRV says this can't happen: */
2136 gcc_assert (!addreg0
&& !addreg1
);
2138 /* Only the middle reg conflicts; simply put it last. */
2139 output_asm_insn (singlemove_string (operands
), operands
);
2140 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2141 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2144 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2145 /* If the low half of dest is mentioned in the source memory
2146 address, the arrange to emit the move late half first. */
2147 dest_overlapped_low
= 1;
2150 /* If one or both operands autodecrementing,
2151 do the two words, high-numbered first. */
2153 /* Likewise, the first move would clobber the source of the second one,
2154 do them in the other order. This happens only for registers;
2155 such overlap can't happen in memory unless the user explicitly
2156 sets it up, and that is an undefined circumstance. */
2158 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2159 || (optype0
== REGOP
&& optype1
== REGOP
2160 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2161 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2162 || dest_overlapped_low
)
2164 /* Make any unoffsettable addresses point at high-numbered word. */
2168 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2170 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2175 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2177 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2181 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2183 /* Undo the adds we just did. */
2185 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2187 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2191 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2193 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2195 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2198 /* Do low-numbered word. */
2199 return singlemove_string (operands
);
2202 /* Normal case: do the two words, low-numbered first. */
2204 output_asm_insn (singlemove_string (operands
), operands
);
2206 /* Do the middle one of the three words for long double */
2210 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2212 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2214 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2217 /* Make any unoffsettable addresses point at high-numbered word. */
2219 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2221 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2224 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2226 /* Undo the adds we just did. */
2230 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2232 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2237 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2239 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2245 /* Return a REG that occurs in ADDR with coefficient 1.
2246 ADDR can be effectively incremented by incrementing REG. */
2249 find_addr_reg (rtx addr
)
2251 while (GET_CODE (addr
) == PLUS
)
2253 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2254 addr
= XEXP (addr
, 0);
2255 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2256 addr
= XEXP (addr
, 1);
2257 else if (CONSTANT_P (XEXP (addr
, 0)))
2258 addr
= XEXP (addr
, 1);
2259 else if (CONSTANT_P (XEXP (addr
, 1)))
2260 addr
= XEXP (addr
, 0);
2264 gcc_assert (GET_CODE (addr
) == REG
);
2268 /* Output assembler code to perform a 32-bit 3-operand add. */
2271 output_addsi3 (rtx
*operands
)
2273 if (! operands_match_p (operands
[0], operands
[1]))
2275 if (!ADDRESS_REG_P (operands
[1]))
2277 rtx tmp
= operands
[1];
2279 operands
[1] = operands
[2];
2283 /* These insns can result from reloads to access
2284 stack slots over 64k from the frame pointer. */
2285 if (GET_CODE (operands
[2]) == CONST_INT
2286 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2287 return "move%.l %2,%0\n\tadd%.l %1,%0";
2288 if (GET_CODE (operands
[2]) == REG
)
2289 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2290 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2292 if (GET_CODE (operands
[2]) == CONST_INT
)
2294 if (INTVAL (operands
[2]) > 0
2295 && INTVAL (operands
[2]) <= 8)
2296 return "addq%.l %2,%0";
2297 if (INTVAL (operands
[2]) < 0
2298 && INTVAL (operands
[2]) >= -8)
2300 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2301 return "subq%.l %2,%0";
2303 /* On the CPU32 it is faster to use two addql instructions to
2304 add a small integer (8 < N <= 16) to a register.
2305 Likewise for subql. */
2306 if (TARGET_CPU32
&& REG_P (operands
[0]))
2308 if (INTVAL (operands
[2]) > 8
2309 && INTVAL (operands
[2]) <= 16)
2311 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2312 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2314 if (INTVAL (operands
[2]) < -8
2315 && INTVAL (operands
[2]) >= -16)
2317 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2318 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2321 if (ADDRESS_REG_P (operands
[0])
2322 && INTVAL (operands
[2]) >= -0x8000
2323 && INTVAL (operands
[2]) < 0x8000)
2326 return "add%.w %2,%0";
2328 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2331 return "add%.l %2,%0";
2334 /* Store in cc_status the expressions that the condition codes will
2335 describe after execution of an instruction whose pattern is EXP.
2336 Do not alter them if the instruction would not alter the cc's. */
2338 /* On the 68000, all the insns to store in an address register fail to
2339 set the cc's. However, in some cases these instructions can make it
2340 possibly invalid to use the saved cc's. In those cases we clear out
2341 some or all of the saved cc's so they won't be used. */
2344 notice_update_cc (rtx exp
, rtx insn
)
2346 if (GET_CODE (exp
) == SET
)
2348 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2350 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2352 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2353 cc_status
.value1
= 0;
2354 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2355 cc_status
.value2
= 0;
2357 else if (!FP_REG_P (SET_DEST (exp
))
2358 && SET_DEST (exp
) != cc0_rtx
2359 && (FP_REG_P (SET_SRC (exp
))
2360 || GET_CODE (SET_SRC (exp
)) == FIX
2361 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2362 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2364 /* A pair of move insns doesn't produce a useful overall cc. */
2365 else if (!FP_REG_P (SET_DEST (exp
))
2366 && !FP_REG_P (SET_SRC (exp
))
2367 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2368 && (GET_CODE (SET_SRC (exp
)) == REG
2369 || GET_CODE (SET_SRC (exp
)) == MEM
2370 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2372 else if (SET_DEST (exp
) != pc_rtx
)
2374 cc_status
.flags
= 0;
2375 cc_status
.value1
= SET_DEST (exp
);
2376 cc_status
.value2
= SET_SRC (exp
);
2379 else if (GET_CODE (exp
) == PARALLEL
2380 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2382 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2383 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2385 if (ADDRESS_REG_P (dest
))
2387 else if (dest
!= pc_rtx
)
2389 cc_status
.flags
= 0;
2390 cc_status
.value1
= dest
;
2391 cc_status
.value2
= src
;
2396 if (cc_status
.value2
!= 0
2397 && ADDRESS_REG_P (cc_status
.value2
)
2398 && GET_MODE (cc_status
.value2
) == QImode
)
2400 if (cc_status
.value2
!= 0)
2401 switch (GET_CODE (cc_status
.value2
))
2403 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2404 case ROTATE
: case ROTATERT
:
2405 /* These instructions always clear the overflow bit, and set
2406 the carry to the bit shifted out. */
2407 /* ??? We don't currently have a way to signal carry not valid,
2408 nor do we check for it in the branch insns. */
2412 case PLUS
: case MINUS
: case MULT
:
2413 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2414 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2415 cc_status
.flags
|= CC_NO_OVERFLOW
;
2418 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2419 ends with a move insn moving r2 in r2's mode.
2420 Thus, the cc's are set for r2.
2421 This can set N bit spuriously. */
2422 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2427 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2429 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2430 cc_status
.value2
= 0;
2431 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2432 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2433 cc_status
.flags
= CC_IN_68881
;
2437 output_move_const_double (rtx
*operands
)
2439 int code
= standard_68881_constant_p (operands
[1]);
2443 static char buf
[40];
2445 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2448 return "fmove%.d %1,%0";
2452 output_move_const_single (rtx
*operands
)
2454 int code
= standard_68881_constant_p (operands
[1]);
2458 static char buf
[40];
2460 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2463 return "fmove%.s %f1,%0";
2466 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2467 from the "fmovecr" instruction.
2468 The value, anded with 0xff, gives the code to use in fmovecr
2469 to get the desired constant. */
2471 /* This code has been fixed for cross-compilation. */
2473 static int inited_68881_table
= 0;
2475 static const char *const strings_68881
[7] = {
2485 static const int codes_68881
[7] = {
2495 REAL_VALUE_TYPE values_68881
[7];
2497 /* Set up values_68881 array by converting the decimal values
2498 strings_68881 to binary. */
2501 init_68881_table (void)
2505 enum machine_mode mode
;
2508 for (i
= 0; i
< 7; i
++)
2512 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2513 values_68881
[i
] = r
;
2515 inited_68881_table
= 1;
2519 standard_68881_constant_p (rtx x
)
2524 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2525 used at all on those chips. */
2526 if (TARGET_68040
|| TARGET_68060
)
2529 if (! inited_68881_table
)
2530 init_68881_table ();
2532 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2534 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2536 for (i
= 0; i
< 6; i
++)
2538 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2539 return (codes_68881
[i
]);
2542 if (GET_MODE (x
) == SFmode
)
2545 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2546 return (codes_68881
[6]);
2548 /* larger powers of ten in the constants ram are not used
2549 because they are not equal to a `double' C constant. */
2553 /* If X is a floating-point constant, return the logarithm of X base 2,
2554 or 0 if X is not a power of 2. */
2557 floating_exact_log2 (rtx x
)
2559 REAL_VALUE_TYPE r
, r1
;
2562 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2564 if (REAL_VALUES_LESS (r
, dconst1
))
2567 exp
= real_exponent (&r
);
2568 real_2expN (&r1
, exp
);
2569 if (REAL_VALUES_EQUAL (r1
, r
))
2575 /* A C compound statement to output to stdio stream STREAM the
2576 assembler syntax for an instruction operand X. X is an RTL
2579 CODE is a value that can be used to specify one of several ways
2580 of printing the operand. It is used when identical operands
2581 must be printed differently depending on the context. CODE
2582 comes from the `%' specification that was used to request
2583 printing of the operand. If the specification was just `%DIGIT'
2584 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2585 is the ASCII code for LTR.
2587 If X is a register, this macro should print the register's name.
2588 The names can be found in an array `reg_names' whose type is
2589 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2591 When the machine description has a specification `%PUNCT' (a `%'
2592 followed by a punctuation character), this macro is called with
2593 a null pointer for X and the punctuation character for CODE.
2595 The m68k specific codes are:
2597 '.' for dot needed in Motorola-style opcode names.
2598 '-' for an operand pushing on the stack:
2599 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2600 '+' for an operand pushing on the stack:
2601 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2602 '@' for a reference to the top word on the stack:
2603 sp@, (sp) or (%sp) depending on the style of syntax.
2604 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2605 but & in SGS syntax).
2606 '!' for the cc register (used in an `and to cc' insn).
2607 '$' for the letter `s' in an op code, but only on the 68040.
2608 '&' for the letter `d' in an op code, but only on the 68040.
2609 '/' for register prefix needed by longlong.h.
2611 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2612 'd' to force memory addressing to be absolute, not relative.
2613 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2614 'o' for operands to go directly to output_operand_address (bypassing
2615 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2616 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2617 or print pair of registers as rx:ry.
2622 print_operand (FILE *file
, rtx op
, int letter
)
2627 fprintf (file
, ".");
2629 else if (letter
== '#')
2630 asm_fprintf (file
, "%I");
2631 else if (letter
== '-')
2632 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2633 else if (letter
== '+')
2634 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2635 else if (letter
== '@')
2636 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2637 else if (letter
== '!')
2638 asm_fprintf (file
, "%Rfpcr");
2639 else if (letter
== '$')
2641 if (TARGET_68040_ONLY
)
2642 fprintf (file
, "s");
2644 else if (letter
== '&')
2646 if (TARGET_68040_ONLY
)
2647 fprintf (file
, "d");
2649 else if (letter
== '/')
2650 asm_fprintf (file
, "%R");
2651 else if (letter
== 'o')
2653 /* This is only for direct addresses with TARGET_PCREL */
2654 gcc_assert (GET_CODE (op
) == MEM
2655 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
2657 output_addr_const (file
, XEXP (op
, 0));
2659 else if (GET_CODE (op
) == REG
)
2662 /* Print out the second register name of a register pair.
2663 I.e., R (6) => 7. */
2664 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2666 fputs (M68K_REGNAME(REGNO (op
)), file
);
2668 else if (GET_CODE (op
) == MEM
)
2670 output_address (XEXP (op
, 0));
2671 if (letter
== 'd' && ! TARGET_68020
2672 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2673 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2674 && INTVAL (XEXP (op
, 0)) < 0x8000
2675 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2676 fprintf (file
, MOTOROLA
? ".l" : ":l");
2678 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2681 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2682 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2684 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2687 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2688 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2690 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2693 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2694 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2698 /* Use `print_operand_address' instead of `output_addr_const'
2699 to ensure that we print relevant PIC stuff. */
2700 asm_fprintf (file
, "%I");
2702 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2703 print_operand_address (file
, op
);
2705 output_addr_const (file
, op
);
2710 /* A C compound statement to output to stdio stream STREAM the
2711 assembler syntax for an instruction operand that is a memory
2712 reference whose address is ADDR. ADDR is an RTL expression.
2714 Note that this contains a kludge that knows that the only reason
2715 we have an address (plus (label_ref...) (reg...)) when not generating
2716 PIC code is in the insn before a tablejump, and we know that m68k.md
2717 generates a label LInnn: on such an insn.
2719 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2720 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2722 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2723 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2724 we want. This difference can be accommodated by using an assembler
2725 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2726 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2727 macro. See m68k/sgs.h for an example; for versions without the bug.
2728 Some assemblers refuse all the above solutions. The workaround is to
2729 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2732 They also do not like things like "pea 1.w", so we simple leave off
2733 the .w on small constants.
2735 This routine is responsible for distinguishing between -fpic and -fPIC
2736 style relocations in an address. When generating -fpic code the
2737 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
2738 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
2741 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
2742 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2743 #else /* !MOTOROLA */
2744 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
2745 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2746 #endif /* !MOTOROLA */
2749 print_operand_address (FILE *file
, rtx addr
)
2751 register rtx reg1
, reg2
, breg
, ireg
;
2754 switch (GET_CODE (addr
))
2757 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
2760 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2761 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
2764 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2765 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
2768 reg1
= reg2
= ireg
= breg
= offset
= 0;
2769 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2771 offset
= XEXP (addr
, 0);
2772 addr
= XEXP (addr
, 1);
2774 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2776 offset
= XEXP (addr
, 1);
2777 addr
= XEXP (addr
, 0);
2779 if (GET_CODE (addr
) != PLUS
)
2783 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2785 reg1
= XEXP (addr
, 0);
2786 addr
= XEXP (addr
, 1);
2788 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2790 reg1
= XEXP (addr
, 1);
2791 addr
= XEXP (addr
, 0);
2793 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2795 reg1
= XEXP (addr
, 0);
2796 addr
= XEXP (addr
, 1);
2798 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2800 reg1
= XEXP (addr
, 1);
2801 addr
= XEXP (addr
, 0);
2803 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2805 reg1
= XEXP (addr
, 0);
2806 addr
= XEXP (addr
, 1);
2808 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2810 reg1
= XEXP (addr
, 1);
2811 addr
= XEXP (addr
, 0);
2813 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2814 || GET_CODE (addr
) == SIGN_EXTEND
)
2822 #if 0 /* for OLD_INDEXING */
2823 else if (GET_CODE (addr
) == PLUS
)
2825 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2827 reg2
= XEXP (addr
, 0);
2828 addr
= XEXP (addr
, 1);
2830 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2832 reg2
= XEXP (addr
, 1);
2833 addr
= XEXP (addr
, 0);
2842 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2843 || GET_CODE (reg1
) == MULT
))
2844 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2849 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2854 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2855 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2858 if (GET_CODE (ireg
) == MULT
)
2860 scale
= INTVAL (XEXP (ireg
, 1));
2861 ireg
= XEXP (ireg
, 0);
2863 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2865 ASM_OUTPUT_CASE_FETCH (file
,
2866 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2867 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
2868 fprintf (file
, "w");
2872 ASM_OUTPUT_CASE_FETCH (file
,
2873 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2874 M68K_REGNAME (REGNO (ireg
)));
2875 fprintf (file
, "l");
2878 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2882 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2883 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2885 ASM_OUTPUT_CASE_FETCH (file
,
2886 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2887 M68K_REGNAME (REGNO (breg
)));
2888 fprintf (file
, "l)");
2891 if (ireg
!= 0 || breg
!= 0)
2896 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
2902 output_addr_const (file
, addr
);
2903 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2905 fprintf (file
, "@GOT");
2907 fprintf (file
, ".w");
2910 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
2914 else /* !MOTOROLA */
2916 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
2919 output_addr_const (file
, addr
);
2920 if (breg
== pic_offset_table_rtx
)
2924 fprintf (file
, ":w");
2927 fprintf (file
, ":l");
2936 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2938 scale
= INTVAL (XEXP (ireg
, 1));
2939 ireg
= XEXP (ireg
, 0);
2941 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2942 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2943 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
2945 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2946 M68K_REGNAME (REGNO (ireg
)));
2948 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2952 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2953 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2955 ASM_OUTPUT_CASE_FETCH (file
,
2956 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2957 M68K_REGNAME (REGNO (reg1
)));
2958 fprintf (file
, "l)");
2961 /* FALL-THROUGH (is this really what we want?) */
2963 if (GET_CODE (addr
) == CONST_INT
2964 && INTVAL (addr
) < 0x8000
2965 && INTVAL (addr
) >= -0x8000)
2967 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2969 else if (GET_CODE (addr
) == CONST_INT
)
2971 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2973 else if (TARGET_PCREL
)
2976 output_addr_const (file
, addr
);
2978 asm_fprintf (file
, ":w,%Rpc)");
2980 asm_fprintf (file
, ":l,%Rpc)");
2984 /* Special case for SYMBOL_REF if the symbol name ends in
2985 `.<letter>', this can be mistaken as a size suffix. Put
2986 the name in parentheses. */
2987 if (GET_CODE (addr
) == SYMBOL_REF
2988 && strlen (XSTR (addr
, 0)) > 2
2989 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
2992 output_addr_const (file
, addr
);
2996 output_addr_const (file
, addr
);
3002 /* Check for cases where a clr insns can be omitted from code using
3003 strict_low_part sets. For example, the second clrl here is not needed:
3004 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3006 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3007 insn we are checking for redundancy. TARGET is the register set by the
3011 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3016 p
= prev_nonnote_insn (first_insn
);
3020 /* If it isn't an insn, then give up. */
3021 if (GET_CODE (p
) != INSN
)
3024 if (reg_set_p (target
, p
))
3026 rtx set
= single_set (p
);
3029 /* If it isn't an easy to recognize insn, then give up. */
3033 dest
= SET_DEST (set
);
3035 /* If this sets the entire target register to zero, then our
3036 first_insn is redundant. */
3037 if (rtx_equal_p (dest
, target
)
3038 && SET_SRC (set
) == const0_rtx
)
3040 else if (GET_CODE (dest
) == STRICT_LOW_PART
3041 && GET_CODE (XEXP (dest
, 0)) == REG
3042 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3043 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3044 <= GET_MODE_SIZE (mode
)))
3045 /* This is a strict low part set which modifies less than
3046 we are using, so it is safe. */
3052 p
= prev_nonnote_insn (p
);
3058 /* Operand predicates for implementing asymmetric pc-relative addressing
3059 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3060 when used as a source operand, but not as a destination operand.
3062 We model this by restricting the meaning of the basic predicates
3063 (general_operand, memory_operand, etc) to forbid the use of this
3064 addressing mode, and then define the following predicates that permit
3065 this addressing mode. These predicates can then be used for the
3066 source operands of the appropriate instructions.
3068 n.b. While it is theoretically possible to change all machine patterns
3069 to use this addressing more where permitted by the architecture,
3070 it has only been implemented for "common" cases: SImode, HImode, and
3071 QImode operands, and only for the principle operations that would
3072 require this addressing mode: data movement and simple integer operations.
3074 In parallel with these new predicates, two new constraint letters
3075 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3076 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3077 In the pcrel case 's' is only valid in combination with 'a' registers.
3078 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3079 of how these constraints are used.
3081 The use of these predicates is strictly optional, though patterns that
3082 don't will cause an extra reload register to be allocated where one
3085 lea (abc:w,%pc),%a0 ; need to reload address
3086 moveq &1,%d1 ; since write to pc-relative space
3087 movel %d1,%a0@ ; is not allowed
3089 lea (abc:w,%pc),%a1 ; no need to reload address here
3090 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3092 For more info, consult tiemann@cygnus.com.
3095 All of the ugliness with predicates and constraints is due to the
3096 simple fact that the m68k does not allow a pc-relative addressing
3097 mode as a destination. gcc does not distinguish between source and
3098 destination addresses. Hence, if we claim that pc-relative address
3099 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3100 end up with invalid code. To get around this problem, we left
3101 pc-relative modes as invalid addresses, and then added special
3102 predicates and constraints to accept them.
3104 A cleaner way to handle this is to modify gcc to distinguish
3105 between source and destination addresses. We can then say that
3106 pc-relative is a valid source address but not a valid destination
3107 address, and hopefully avoid a lot of the predicate and constraint
3108 hackery. Unfortunately, this would be a pretty big change. It would
3109 be a useful change for a number of ports, but there aren't any current
3110 plans to undertake this.
3112 ***************************************************************************/
3116 output_andsi3 (rtx
*operands
)
3119 if (GET_CODE (operands
[2]) == CONST_INT
3120 && (INTVAL (operands
[2]) | 0xffff) == -1
3121 && (DATA_REG_P (operands
[0])
3122 || offsettable_memref_p (operands
[0]))
3123 && !TARGET_COLDFIRE
)
3125 if (GET_CODE (operands
[0]) != REG
)
3126 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3127 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3128 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3130 if (operands
[2] == const0_rtx
)
3132 return "and%.w %2,%0";
3134 if (GET_CODE (operands
[2]) == CONST_INT
3135 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3136 && (DATA_REG_P (operands
[0])
3137 || offsettable_memref_p (operands
[0])))
3139 if (DATA_REG_P (operands
[0]))
3140 operands
[1] = GEN_INT (logval
);
3143 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3144 operands
[1] = GEN_INT (logval
% 8);
3146 /* This does not set condition codes in a standard way. */
3148 return "bclr %1,%0";
3150 return "and%.l %2,%0";
3154 output_iorsi3 (rtx
*operands
)
3156 register int logval
;
3157 if (GET_CODE (operands
[2]) == CONST_INT
3158 && INTVAL (operands
[2]) >> 16 == 0
3159 && (DATA_REG_P (operands
[0])
3160 || offsettable_memref_p (operands
[0]))
3161 && !TARGET_COLDFIRE
)
3163 if (GET_CODE (operands
[0]) != REG
)
3164 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3165 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3167 if (INTVAL (operands
[2]) == 0xffff)
3168 return "mov%.w %2,%0";
3169 return "or%.w %2,%0";
3171 if (GET_CODE (operands
[2]) == CONST_INT
3172 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3173 && (DATA_REG_P (operands
[0])
3174 || offsettable_memref_p (operands
[0])))
3176 if (DATA_REG_P (operands
[0]))
3177 operands
[1] = GEN_INT (logval
);
3180 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3181 operands
[1] = GEN_INT (logval
% 8);
3184 return "bset %1,%0";
3186 return "or%.l %2,%0";
3190 output_xorsi3 (rtx
*operands
)
3192 register int logval
;
3193 if (GET_CODE (operands
[2]) == CONST_INT
3194 && INTVAL (operands
[2]) >> 16 == 0
3195 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3196 && !TARGET_COLDFIRE
)
3198 if (! DATA_REG_P (operands
[0]))
3199 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3200 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3202 if (INTVAL (operands
[2]) == 0xffff)
3204 return "eor%.w %2,%0";
3206 if (GET_CODE (operands
[2]) == CONST_INT
3207 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3208 && (DATA_REG_P (operands
[0])
3209 || offsettable_memref_p (operands
[0])))
3211 if (DATA_REG_P (operands
[0]))
3212 operands
[1] = GEN_INT (logval
);
3215 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3216 operands
[1] = GEN_INT (logval
% 8);
3219 return "bchg %1,%0";
3221 return "eor%.l %2,%0";
3224 #ifdef M68K_TARGET_COFF
3226 /* Output assembly to switch to section NAME with attribute FLAGS. */
3229 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3230 tree decl ATTRIBUTE_UNUSED
)
3234 if (flags
& SECTION_WRITE
)
3239 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3242 #endif /* M68K_TARGET_COFF */
3245 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3246 HOST_WIDE_INT delta
,
3247 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3253 if (delta
> 0 && delta
<= 8)
3254 asm_fprintf (file
, (MOTOROLA
3255 ? "\taddq.l %I%d,4(%Rsp)\n"
3256 : "\taddql %I%d,%Rsp@(4)\n"),
3258 else if (delta
< 0 && delta
>= -8)
3259 asm_fprintf (file
, (MOTOROLA
3260 ? "\tsubq.l %I%d,4(%Rsp)\n"
3261 : "\tsubql %I%d,%Rsp@(4)\n"),
3263 else if (TARGET_COLDFIRE
)
3265 /* ColdFire can't add/sub a constant to memory unless it is in
3266 the range of addq/subq. So load the value into %d0 and
3267 then add it to 4(%sp). */
3268 if (delta
>= -128 && delta
<= 127)
3269 asm_fprintf (file
, (MOTOROLA
3270 ? "\tmoveq.l %I%wd,%Rd0\n"
3271 : "\tmoveql %I%wd,%Rd0\n"),
3274 asm_fprintf (file
, (MOTOROLA
3275 ? "\tmove.l %I%wd,%Rd0\n"
3276 : "\tmovel %I%wd,%Rd0\n"),
3278 asm_fprintf (file
, (MOTOROLA
3279 ? "\tadd.l %Rd0,4(%Rsp)\n"
3280 : "\taddl %Rd0,%Rsp@(4)\n"));
3283 asm_fprintf (file
, (MOTOROLA
3284 ? "\tadd.l %I%wd,4(%Rsp)\n"
3285 : "\taddl %I%wd,%Rsp@(4)\n"),
3288 xops
[0] = DECL_RTL (function
);
3290 /* Logic taken from call patterns in m68k.md. */
3295 else if (flag_pic
== 1 || TARGET_68020
)
3299 #if defined (USE_GAS)
3300 fmt
= "bra.l %0@PLTPC";
3302 fmt
= "bra %0@PLTPC";
3305 else /* !MOTOROLA */
3314 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3315 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3317 fmt
= "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)";
3321 #if MOTOROLA && !defined (USE_GAS)
3328 output_asm_insn (fmt
, xops
);
3331 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3334 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3335 int incoming ATTRIBUTE_UNUSED
)
3337 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3340 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3342 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3343 unsigned int new_reg
)
3346 /* Interrupt functions can only use registers that have already been
3347 saved by the prologue, even if they would normally be
3350 if (m68k_interrupt_function_p (current_function_decl
)
3351 && !regs_ever_live
[new_reg
])
3357 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3358 On the 68000, the cpu registers can hold any mode except bytes in address
3359 registers, but the 68881 registers can hold only SFmode or DFmode. */
3361 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3365 /* Data Registers, can hold aggregate if fits in. */
3366 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3369 else if (regno
< 16)
3371 /* Address Registers, can't hold bytes, can hold aggregate if
3373 if (GET_MODE_SIZE (mode
) == 1)
3375 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3378 else if (regno
< 24)
3380 /* FPU registers, hold float or complex float of long double or
3382 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3383 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3384 && GET_MODE_UNIT_SIZE (mode
) <= 12)