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m68k.c: Include <stdlib.h> for atoi.
[gcc.git] / gcc / config / m68k / m68k.c
1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
3
4 This file is part of GNU CC.
5
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21
22 /* Some output-actions in m68k.md need these. */
23 #include "config.h"
24 #include <stdio.h>
25 #include "tree.h"
26 #include "rtl.h"
27 #include "regs.h"
28 #include "hard-reg-set.h"
29 #include "real.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "recog.h"
36
37 /* Needed for use_return_insn. */
38 #include "flags.h"
39
40 #if HAVE_STDLIB_H
41 #include <stdlib.h>
42 #endif
43
44 #ifdef SUPPORT_SUN_FPA
45
46 /* Index into this array by (register number >> 3) to find the
47 smallest class which contains that register. */
48 enum reg_class regno_reg_class[]
49 = { DATA_REGS, ADDR_REGS, FP_REGS,
50 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
51
52 #endif /* defined SUPPORT_SUN_FPA */
53
54 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
55 if SGS_SWITCH_TABLE. */
56 int switch_table_difference_label_flag;
57
58 static rtx find_addr_reg ();
59 rtx legitimize_pic_address ();
60 \f
61
62 /* Alignment to use for loops and jumps */
63 /* Specify power of two alignment used for loops. */
64 char *m68k_align_loops_string;
65 /* Specify power of two alignment used for non-loop jumps. */
66 char *m68k_align_jumps_string;
67 /* Specify power of two alignment used for functions. */
68 char *m68k_align_funcs_string;
69
70 /* Specify power of two alignment used for loops. */
71 int m68k_align_loops;
72 /* Specify power of two alignment used for non-loop jumps. */
73 int m68k_align_jumps;
74 /* Specify power of two alignment used for functions. */
75 int m68k_align_funcs;
76
77 /* Nonzero if the last compare/test insn had FP operands. The
78 sCC expanders peek at this to determine what to do for the
79 68060, which has no fsCC instructions. */
80 int m68k_last_compare_had_fp_operands;
81
82 /* Sometimes certain combinations of command options do not make
83 sense on a particular target machine. You can define a macro
84 `OVERRIDE_OPTIONS' to take account of this. This macro, if
85 defined, is executed once just after all the command options have
86 been parsed.
87
88 Don't use this macro to turn on various extra optimizations for
89 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
90
91 void
92 override_options ()
93 {
94 int def_align;
95
96 def_align = 1;
97
98 /* Validate -malign-loops= value, or provide default */
99 if (m68k_align_loops_string)
100 {
101 m68k_align_loops = atoi (m68k_align_loops_string);
102 if (m68k_align_loops < 1 || m68k_align_loops > MAX_CODE_ALIGN)
103 fatal ("-malign-loops=%d is not between 1 and %d",
104 m68k_align_loops, MAX_CODE_ALIGN);
105 }
106 else
107 m68k_align_loops = def_align;
108
109 /* Validate -malign-jumps= value, or provide default */
110 if (m68k_align_jumps_string)
111 {
112 m68k_align_jumps = atoi (m68k_align_jumps_string);
113 if (m68k_align_jumps < 1 || m68k_align_jumps > MAX_CODE_ALIGN)
114 fatal ("-malign-jumps=%d is not between 1 and %d",
115 m68k_align_jumps, MAX_CODE_ALIGN);
116 }
117 else
118 m68k_align_jumps = def_align;
119
120 /* Validate -malign-functions= value, or provide default */
121 if (m68k_align_funcs_string)
122 {
123 m68k_align_funcs = atoi (m68k_align_funcs_string);
124 if (m68k_align_funcs < 1 || m68k_align_funcs > MAX_CODE_ALIGN)
125 fatal ("-malign-functions=%d is not between 1 and %d",
126 m68k_align_funcs, MAX_CODE_ALIGN);
127 }
128 else
129 m68k_align_funcs = def_align;
130 }
131 \f
132 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
133 function at any time during the compilation process. In the future
134 we should try and eliminate the USE if we can easily determine that
135 all PIC references were deleted from the current function. That would
136 save an address register */
137
138 void
139 finalize_pic ()
140 {
141 if (flag_pic && current_function_uses_pic_offset_table)
142 {
143 rtx insn = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
144 emit_insn_after (insn, get_insns ());
145 emit_insn (insn);
146 }
147 }
148
149 \f
150 /* This function generates the assembly code for function entry.
151 STREAM is a stdio stream to output the code to.
152 SIZE is an int: how many units of temporary storage to allocate.
153 Refer to the array `regs_ever_live' to determine which registers
154 to save; `regs_ever_live[I]' is nonzero if register number I
155 is ever used in the function. This function is responsible for
156 knowing which registers should not be saved even if used. */
157
158
159 /* Note that the order of the bit mask for fmovem is the opposite
160 of the order for movem! */
161
162
163 void
164 output_function_prologue (stream, size)
165 FILE *stream;
166 int size;
167 {
168 register int regno;
169 register int mask = 0;
170 int num_saved_regs = 0;
171 extern char call_used_regs[];
172 int fsize = (size + 3) & -4;
173 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
174
175
176 if (frame_pointer_needed)
177 {
178 if (fsize == 0 && TARGET_68040)
179 {
180 /* on the 68040, pea + move is faster than link.w 0 */
181 #ifdef MOTOROLA
182 asm_fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
183 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
184 reg_names[FRAME_POINTER_REGNUM]);
185 #else
186 asm_fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
187 reg_names[FRAME_POINTER_REGNUM], reg_names[STACK_POINTER_REGNUM],
188 reg_names[FRAME_POINTER_REGNUM]);
189 #endif
190 }
191 else if (fsize < 0x8000)
192 {
193 #ifdef MOTOROLA
194 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
195 reg_names[FRAME_POINTER_REGNUM], -fsize);
196 #else
197 asm_fprintf (stream, "\tlink %s,%0I%d\n",
198 reg_names[FRAME_POINTER_REGNUM], -fsize);
199 #endif
200 }
201 else if (TARGET_68020)
202 {
203 #ifdef MOTOROLA
204 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
205 reg_names[FRAME_POINTER_REGNUM], -fsize);
206 #else
207 asm_fprintf (stream, "\tlink %s,%0I%d\n",
208 reg_names[FRAME_POINTER_REGNUM], -fsize);
209 #endif
210 }
211 else
212 {
213 /* Adding negative number is faster on the 68040. */
214 #ifdef MOTOROLA
215 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
216 reg_names[FRAME_POINTER_REGNUM], -fsize);
217 #else
218 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
219 reg_names[FRAME_POINTER_REGNUM], -fsize);
220 #endif
221 }
222 if (dwarf2out_do_frame ())
223 {
224 char *l;
225 l = (char *) dwarf2out_cfi_label ();
226 cfa_store_offset += 4;
227 cfa_offset = cfa_store_offset;
228 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
229 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
230 cfa_store_offset += fsize;
231 }
232 }
233 else if (fsize)
234 {
235 if (fsize + 4 < 0x8000)
236 {
237 #ifdef NO_ADDSUB_Q
238 if (fsize + 4 <= 8)
239 {
240 if (!TARGET_5200)
241 {
242 /* asm_fprintf() cannot handle %. */
243 #ifdef MOTOROLA
244 asm_fprintf (stream, "\tsubq.w %OI%d,%Rsp\n", fsize + 4);
245 #else
246 asm_fprintf (stream, "\tsubqw %OI%d,%Rsp\n", fsize + 4);
247 #endif
248 }
249 else
250 {
251 /* asm_fprintf() cannot handle %. */
252 #ifdef MOTOROLA
253 asm_fprintf (stream, "\tsubq.l %OI%d,%Rsp\n", fsize + 4);
254 #else
255 asm_fprintf (stream, "\tsubql %OI%d,%Rsp\n", fsize + 4);
256 #endif
257 }
258 }
259 else if (fsize + 4 <= 16 && TARGET_CPU32)
260 {
261 /* On the CPU32 it is faster to use two subqw instructions to
262 subtract a small integer (8 < N <= 16) to a register. */
263 /* asm_fprintf() cannot handle %. */
264 #ifdef MOTOROLA
265 asm_fprintf (stream, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
266 fsize + 4);
267 #else
268 asm_fprintf (stream, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
269 fsize + 4);
270 #endif
271 }
272 else
273 #endif /* NO_ADDSUB_Q */
274 if (TARGET_68040)
275 {
276 /* Adding negative number is faster on the 68040. */
277 /* asm_fprintf() cannot handle %. */
278 #ifdef MOTOROLA
279 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
280 #else
281 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
282 #endif
283 }
284 else
285 {
286 #ifdef MOTOROLA
287 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
288 #else
289 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
290 #endif
291 }
292 }
293 else
294 {
295 /* asm_fprintf() cannot handle %. */
296 #ifdef MOTOROLA
297 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
298 #else
299 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
300 #endif
301 }
302 if (dwarf2out_do_frame ())
303 {
304 cfa_store_offset += fsize;
305 cfa_offset = cfa_store_offset;
306 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
307 }
308 }
309 #ifdef SUPPORT_SUN_FPA
310 for (regno = 24; regno < 56; regno++)
311 if (regs_ever_live[regno] && ! call_used_regs[regno])
312 {
313 #ifdef MOTOROLA
314 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
315 reg_names[regno]);
316 #else
317 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
318 reg_names[regno]);
319 #endif
320 if (dwarf2out_do_frame ())
321 {
322 char *l = dwarf2out_cfi_label ();
323
324 cfa_store_offset += 8;
325 if (! frame_pointer_needed)
326 {
327 cfa_offset = cfa_store_offset;
328 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
329 }
330 dwarf2out_reg_save (l, regno, -cfa_store_offset);
331 }
332 }
333 #endif
334 if (TARGET_68881)
335 {
336 for (regno = 16; regno < 24; regno++)
337 if (regs_ever_live[regno] && ! call_used_regs[regno])
338 {
339 mask |= 1 << (regno - 16);
340 num_saved_regs++;
341 }
342 if ((mask & 0xff) != 0)
343 {
344 #ifdef MOTOROLA
345 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
346 #else
347 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
348 #endif
349 if (dwarf2out_do_frame ())
350 {
351 char *l = (char *) dwarf2out_cfi_label ();
352 int n_regs;
353
354 cfa_store_offset += num_saved_regs * 12;
355 if (! frame_pointer_needed)
356 {
357 cfa_offset = cfa_store_offset;
358 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
359 }
360 for (regno = 16, n_regs = 0; regno < 24; regno++)
361 if (mask & (1 << (regno - 16)))
362 dwarf2out_reg_save (l, regno,
363 -cfa_store_offset + n_regs++ * 12);
364 }
365 }
366 mask = 0;
367 num_saved_regs = 0;
368 }
369 for (regno = 0; regno < 16; regno++)
370 if (regs_ever_live[regno] && ! call_used_regs[regno])
371 {
372 mask |= 1 << (15 - regno);
373 num_saved_regs++;
374 }
375 if (frame_pointer_needed)
376 {
377 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
378 num_saved_regs--;
379 }
380
381 #if NEED_PROBE
382 #ifdef MOTOROLA
383 #ifdef CRDS
384 asm_fprintf (stream, "\ttstl %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
385 #else
386 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
387 #endif
388 #else
389 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
390 #endif
391 #endif
392
393 if (num_saved_regs <= 2)
394 {
395 /* Store each separately in the same order moveml uses.
396 Using two movel instructions instead of a single moveml
397 is about 15% faster for the 68020 and 68030 at no expense
398 in code size */
399
400 int i;
401
402 /* Undo the work from above. */
403 for (i = 0; i< 16; i++)
404 if (mask & (1 << i))
405 {
406 asm_fprintf (stream,
407 #ifdef MOTOROLA
408 "\t%Omove.l %s,-(%Rsp)\n",
409 #else
410 "\tmovel %s,%Rsp@-\n",
411 #endif
412 reg_names[15 - i]);
413 if (dwarf2out_do_frame ())
414 {
415 char *l = (char *) dwarf2out_cfi_label ();
416
417 cfa_store_offset += 4;
418 if (! frame_pointer_needed)
419 {
420 cfa_offset = cfa_store_offset;
421 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
422 }
423 dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
424 }
425 }
426 }
427 else if (mask)
428 {
429 if (TARGET_5200)
430 {
431 /* The coldfire does not support the predecrement form of the
432 movml instruction, so we must adjust the stack pointer and
433 then use the plain address register indirect mode. We also
434 have to invert the register save mask to use the new mode.
435
436 FIXME: if num_saved_regs was calculated earlier, we could
437 combine the stack pointer adjustment with any adjustment
438 done when the initial stack frame is created. This would
439 save an instruction */
440
441 int newmask = 0;
442 int i;
443
444 for (i = 0; i < 16; i++)
445 if (mask & (1 << i))
446 newmask |= (1 << (15-i));
447
448 #ifdef MOTOROLA
449 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
450 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
451 #else
452 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
453 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
454 #endif
455 }
456 else
457 {
458 #ifdef MOTOROLA
459 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
460 #else
461 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
462 #endif
463 }
464 if (dwarf2out_do_frame ())
465 {
466 char *l = (char *) dwarf2out_cfi_label ();
467 int n_regs;
468
469 cfa_store_offset += num_saved_regs * 4;
470 if (! frame_pointer_needed)
471 {
472 cfa_offset = cfa_store_offset;
473 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
474 }
475 for (regno = 0, n_regs = 0; regno < 16; regno++)
476 if (mask & (1 << (15 - regno)))
477 dwarf2out_reg_save (l, regno,
478 -cfa_store_offset + n_regs++ * 4);
479 }
480 }
481 if (flag_pic && current_function_uses_pic_offset_table)
482 {
483 #ifdef MOTOROLA
484 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
485 reg_names[PIC_OFFSET_TABLE_REGNUM]);
486 #else
487 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
488 reg_names[PIC_OFFSET_TABLE_REGNUM]);
489 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
490 reg_names[PIC_OFFSET_TABLE_REGNUM],
491 reg_names[PIC_OFFSET_TABLE_REGNUM]);
492 #endif
493 }
494 }
495 \f
496 /* Return true if this function's epilogue can be output as RTL. */
497
498 int
499 use_return_insn ()
500 {
501 int regno;
502
503 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
504 return 0;
505
506 /* Copied from output_function_epilogue (). We should probably create a
507 separate layout routine to perform the common work. */
508
509 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
510 if (regs_ever_live[regno] && ! call_used_regs[regno])
511 return 0;
512
513 return 1;
514 }
515
516 /* This function generates the assembly code for function exit,
517 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
518
519 The function epilogue should not depend on the current stack pointer!
520 It should use the frame pointer only, if there is a frame pointer.
521 This is mandatory because of alloca; we also take advantage of it to
522 omit stack adjustments before returning. */
523
524 void
525 output_function_epilogue (stream, size)
526 FILE *stream;
527 int size;
528 {
529 register int regno;
530 register int mask, fmask;
531 register int nregs;
532 int offset, foffset, fpoffset;
533 extern char call_used_regs[];
534 int fsize = (size + 3) & -4;
535 int big = 0;
536 rtx insn = get_last_insn ();
537 int restore_from_sp = 0;
538
539 /* If the last insn was a BARRIER, we don't have to write any code. */
540 if (GET_CODE (insn) == NOTE)
541 insn = prev_nonnote_insn (insn);
542 if (insn && GET_CODE (insn) == BARRIER)
543 {
544 /* Output just a no-op so that debuggers don't get confused
545 about which function the pc is in at this address. */
546 asm_fprintf (stream, "\tnop\n");
547 return;
548 }
549
550 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
551 if (profile_block_flag == 2)
552 {
553 FUNCTION_BLOCK_PROFILER_EXIT (stream);
554 }
555 #endif
556
557 #ifdef FUNCTION_EXTRA_EPILOGUE
558 FUNCTION_EXTRA_EPILOGUE (stream, size);
559 #endif
560 nregs = 0; fmask = 0; fpoffset = 0;
561 #ifdef SUPPORT_SUN_FPA
562 for (regno = 24 ; regno < 56 ; regno++)
563 if (regs_ever_live[regno] && ! call_used_regs[regno])
564 nregs++;
565 fpoffset = nregs * 8;
566 #endif
567 nregs = 0;
568 if (TARGET_68881)
569 {
570 for (regno = 16; regno < 24; regno++)
571 if (regs_ever_live[regno] && ! call_used_regs[regno])
572 {
573 nregs++;
574 fmask |= 1 << (23 - regno);
575 }
576 }
577 foffset = fpoffset + nregs * 12;
578 nregs = 0; mask = 0;
579 if (frame_pointer_needed)
580 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
581 for (regno = 0; regno < 16; regno++)
582 if (regs_ever_live[regno] && ! call_used_regs[regno])
583 {
584 nregs++;
585 mask |= 1 << regno;
586 }
587 offset = foffset + nregs * 4;
588 /* FIXME : leaf_function_p below is too strong.
589 What we really need to know there is if there could be pending
590 stack adjustment needed at that point. */
591 restore_from_sp = ! frame_pointer_needed
592 || (! current_function_calls_alloca && leaf_function_p ());
593 if (offset + fsize >= 0x8000
594 && ! restore_from_sp
595 && (mask || fmask || fpoffset))
596 {
597 #ifdef MOTOROLA
598 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
599 #else
600 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
601 #endif
602 fsize = 0, big = 1;
603 }
604 if (TARGET_5200 || nregs <= 2)
605 {
606 /* Restore each separately in the same order moveml does.
607 Using two movel instructions instead of a single moveml
608 is about 15% faster for the 68020 and 68030 at no expense
609 in code size. */
610
611 int i;
612
613 /* Undo the work from above. */
614 for (i = 0; i< 16; i++)
615 if (mask & (1 << i))
616 {
617 if (big)
618 {
619 #ifdef MOTOROLA
620 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
621 offset + fsize,
622 reg_names[FRAME_POINTER_REGNUM],
623 reg_names[i]);
624 #else
625 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
626 reg_names[FRAME_POINTER_REGNUM],
627 offset + fsize, reg_names[i]);
628 #endif
629 }
630 else if (restore_from_sp)
631 {
632 #ifdef MOTOROLA
633 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
634 reg_names[i]);
635 #else
636 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
637 reg_names[i]);
638 #endif
639 }
640 else
641 {
642 #ifdef MOTOROLA
643 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
644 offset + fsize,
645 reg_names[FRAME_POINTER_REGNUM],
646 reg_names[i]);
647 #else
648 asm_fprintf (stream, "\tmovel %s@(-%d),%s\n",
649 reg_names[FRAME_POINTER_REGNUM],
650 offset + fsize, reg_names[i]);
651 #endif
652 }
653 offset = offset - 4;
654 }
655 }
656 else if (mask)
657 {
658 if (big)
659 {
660 #ifdef MOTOROLA
661 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
662 offset + fsize,
663 reg_names[FRAME_POINTER_REGNUM],
664 mask);
665 #else
666 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
667 reg_names[FRAME_POINTER_REGNUM],
668 offset + fsize, mask);
669 #endif
670 }
671 else if (restore_from_sp)
672 {
673 #ifdef MOTOROLA
674 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
675 #else
676 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
677 #endif
678 }
679 else
680 {
681 #ifdef MOTOROLA
682 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
683 offset + fsize,
684 reg_names[FRAME_POINTER_REGNUM],
685 mask);
686 #else
687 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
688 reg_names[FRAME_POINTER_REGNUM],
689 offset + fsize, mask);
690 #endif
691 }
692 }
693 if (fmask)
694 {
695 if (big)
696 {
697 #ifdef MOTOROLA
698 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
699 foffset + fsize,
700 reg_names[FRAME_POINTER_REGNUM],
701 fmask);
702 #else
703 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
704 reg_names[FRAME_POINTER_REGNUM],
705 foffset + fsize, fmask);
706 #endif
707 }
708 else if (restore_from_sp)
709 {
710 #ifdef MOTOROLA
711 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
712 #else
713 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
714 #endif
715 }
716 else
717 {
718 #ifdef MOTOROLA
719 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
720 foffset + fsize,
721 reg_names[FRAME_POINTER_REGNUM],
722 fmask);
723 #else
724 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
725 reg_names[FRAME_POINTER_REGNUM],
726 foffset + fsize, fmask);
727 #endif
728 }
729 }
730 if (fpoffset != 0)
731 for (regno = 55; regno >= 24; regno--)
732 if (regs_ever_live[regno] && ! call_used_regs[regno])
733 {
734 if (big)
735 {
736 #ifdef MOTOROLA
737 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
738 fpoffset + fsize,
739 reg_names[FRAME_POINTER_REGNUM],
740 reg_names[regno]);
741 #else
742 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
743 reg_names[FRAME_POINTER_REGNUM],
744 fpoffset + fsize, reg_names[regno]);
745 #endif
746 }
747 else if (restore_from_sp)
748 {
749 #ifdef MOTOROLA
750 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
751 reg_names[regno]);
752 #else
753 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
754 reg_names[regno]);
755 #endif
756 }
757 else
758 {
759 #ifdef MOTOROLA
760 asm_fprintf (stream, "\tfpmovd -%d(%s), %s\n",
761 fpoffset + fsize,
762 reg_names[FRAME_POINTER_REGNUM],
763 reg_names[regno]);
764 #else
765 asm_fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
766 reg_names[FRAME_POINTER_REGNUM],
767 fpoffset + fsize, reg_names[regno]);
768 #endif
769 }
770 fpoffset -= 8;
771 }
772 if (frame_pointer_needed)
773 fprintf (stream, "\tunlk %s\n",
774 reg_names[FRAME_POINTER_REGNUM]);
775 else if (fsize)
776 {
777 #ifdef NO_ADDSUB_Q
778 if (fsize + 4 <= 8)
779 {
780 if (!TARGET_5200)
781 {
782 #ifdef MOTOROLA
783 asm_fprintf (stream, "\taddq.w %OI%d,%Rsp\n", fsize + 4);
784 #else
785 asm_fprintf (stream, "\taddqw %OI%d,%Rsp\n", fsize + 4);
786 #endif
787 }
788 else
789 {
790 #ifdef MOTOROLA
791 asm_fprintf (stream, "\taddq.l %OI%d,%Rsp\n", fsize + 4);
792 #else
793 asm_fprintf (stream, "\taddql %OI%d,%Rsp\n", fsize + 4);
794 #endif
795 }
796 }
797 else if (fsize + 4 <= 16 && TARGET_CPU32)
798 {
799 /* On the CPU32 it is faster to use two addqw instructions to
800 add a small integer (8 < N <= 16) to a register. */
801 /* asm_fprintf() cannot handle %. */
802 #ifdef MOTOROLA
803 asm_fprintf (stream, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
804 fsize + 4);
805 #else
806 asm_fprintf (stream, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
807 fsize + 4);
808 #endif
809 }
810 else
811 #endif /* NO_ADDSUB_Q */
812 if (fsize + 4 < 0x8000)
813 {
814 if (TARGET_68040)
815 {
816 /* asm_fprintf() cannot handle %. */
817 #ifdef MOTOROLA
818 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
819 #else
820 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
821 #endif
822 }
823 else
824 {
825 #ifdef MOTOROLA
826 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
827 #else
828 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
829 #endif
830 }
831 }
832 else
833 {
834 /* asm_fprintf() cannot handle %. */
835 #ifdef MOTOROLA
836 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
837 #else
838 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
839 #endif
840 }
841 }
842 if (current_function_pops_args)
843 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
844 else
845 fprintf (stream, "\trts\n");
846 }
847 \f
848 /* Similar to general_operand, but exclude stack_pointer_rtx. */
849
850 int
851 not_sp_operand (op, mode)
852 register rtx op;
853 enum machine_mode mode;
854 {
855 return op != stack_pointer_rtx && general_operand (op, mode);
856 }
857
858 /* Return TRUE if X is a valid comparison operator for the dbcc
859 instruction.
860
861 Note it rejects floating point comparison operators.
862 (In the future we could use Fdbcc).
863
864 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
865
866 int
867 valid_dbcc_comparison_p (x, mode)
868 rtx x;
869 enum machine_mode mode;
870 {
871 switch (GET_CODE (x))
872 {
873 case EQ: case NE: case GTU: case LTU:
874 case GEU: case LEU:
875 return 1;
876
877 /* Reject some when CC_NO_OVERFLOW is set. This may be over
878 conservative */
879 case GT: case LT: case GE: case LE:
880 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
881 default:
882 return 0;
883 }
884 }
885
886 /* Return non-zero if flags are currently in the 68881 flag register. */
887 int
888 flags_in_68881 ()
889 {
890 /* We could add support for these in the future */
891 return cc_status.flags & CC_IN_68881;
892 }
893
894 /* Output a dbCC; jCC sequence. Note we do not handle the
895 floating point version of this sequence (Fdbcc). We also
896 do not handle alternative conditions when CC_NO_OVERFLOW is
897 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
898 kick those out before we get here. */
899
900 void
901 output_dbcc_and_branch (operands)
902 rtx *operands;
903 {
904 switch (GET_CODE (operands[3]))
905 {
906 case EQ:
907 #ifdef MOTOROLA
908 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
909 #else
910 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
911 #endif
912 break;
913
914 case NE:
915 #ifdef MOTOROLA
916 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
917 #else
918 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
919 #endif
920 break;
921
922 case GT:
923 #ifdef MOTOROLA
924 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
925 #else
926 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
927 #endif
928 break;
929
930 case GTU:
931 #ifdef MOTOROLA
932 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
933 #else
934 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
935 #endif
936 break;
937
938 case LT:
939 #ifdef MOTOROLA
940 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
941 #else
942 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
943 #endif
944 break;
945
946 case LTU:
947 #ifdef MOTOROLA
948 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
949 #else
950 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
951 #endif
952 break;
953
954 case GE:
955 #ifdef MOTOROLA
956 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
957 #else
958 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
959 #endif
960 break;
961
962 case GEU:
963 #ifdef MOTOROLA
964 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
965 #else
966 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
967 #endif
968 break;
969
970 case LE:
971 #ifdef MOTOROLA
972 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
973 #else
974 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
975 #endif
976 break;
977
978 case LEU:
979 #ifdef MOTOROLA
980 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
981 #else
982 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
983 #endif
984 break;
985
986 default:
987 abort ();
988 }
989
990 /* If the decrement is to be done in SImode, then we have
991 to compensate for the fact that dbcc decrements in HImode. */
992 switch (GET_MODE (operands[0]))
993 {
994 case SImode:
995 #ifdef MOTOROLA
996 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
997 #else
998 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
999 #endif
1000 break;
1001
1002 case HImode:
1003 break;
1004
1005 default:
1006 abort ();
1007 }
1008 }
1009
1010 char *
1011 output_scc_di(op, operand1, operand2, dest)
1012 rtx op;
1013 rtx operand1;
1014 rtx operand2;
1015 rtx dest;
1016 {
1017 rtx loperands[7];
1018 enum rtx_code op_code = GET_CODE (op);
1019
1020 /* This does not produce a usefull cc. */
1021 CC_STATUS_INIT;
1022
1023 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1024 below. Swap the operands and change the op if these requirements
1025 are not fulfilled. */
1026 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1027 {
1028 rtx tmp = operand1;
1029
1030 operand1 = operand2;
1031 operand2 = tmp;
1032 op_code = swap_condition (op_code);
1033 }
1034 loperands[0] = operand1;
1035 if (GET_CODE (operand1) == REG)
1036 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1037 else
1038 loperands[1] = adj_offsettable_operand (operand1, 4);
1039 if (operand2 != const0_rtx)
1040 {
1041 loperands[2] = operand2;
1042 if (GET_CODE (operand2) == REG)
1043 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1044 else
1045 loperands[3] = adj_offsettable_operand (operand2, 4);
1046 }
1047 loperands[4] = gen_label_rtx();
1048 if (operand2 != const0_rtx)
1049 #ifdef MOTOROLA
1050 #ifdef SGS_CMP_ORDER
1051 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
1052 #else
1053 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
1054 #endif
1055 #else
1056 #ifdef SGS_CMP_ORDER
1057 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
1058 #else
1059 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1060 #endif
1061 #endif
1062 else
1063 #ifdef MOTOROLA
1064 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands);
1065 #else
1066 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands);
1067 #endif
1068 loperands[5] = dest;
1069
1070 switch (op_code)
1071 {
1072 case EQ:
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1074 CODE_LABEL_NUMBER (loperands[4]));
1075 output_asm_insn ("seq %5", loperands);
1076 break;
1077
1078 case NE:
1079 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1080 CODE_LABEL_NUMBER (loperands[4]));
1081 output_asm_insn ("sne %5", loperands);
1082 break;
1083
1084 case GT:
1085 loperands[6] = gen_label_rtx();
1086 #ifdef MOTOROLA
1087 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1088 #else
1089 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1090 #endif
1091 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1092 CODE_LABEL_NUMBER (loperands[4]));
1093 output_asm_insn ("sgt %5", loperands);
1094 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1095 CODE_LABEL_NUMBER (loperands[6]));
1096 break;
1097
1098 case GTU:
1099 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1100 CODE_LABEL_NUMBER (loperands[4]));
1101 output_asm_insn ("shi %5", loperands);
1102 break;
1103
1104 case LT:
1105 loperands[6] = gen_label_rtx();
1106 #ifdef MOTOROLA
1107 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1108 #else
1109 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1110 #endif
1111 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1112 CODE_LABEL_NUMBER (loperands[4]));
1113 output_asm_insn ("slt %5", loperands);
1114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1115 CODE_LABEL_NUMBER (loperands[6]));
1116 break;
1117
1118 case LTU:
1119 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1120 CODE_LABEL_NUMBER (loperands[4]));
1121 output_asm_insn ("scs %5", loperands);
1122 break;
1123
1124 case GE:
1125 loperands[6] = gen_label_rtx();
1126 #ifdef MOTOROLA
1127 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1128 #else
1129 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1130 #endif
1131 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1132 CODE_LABEL_NUMBER (loperands[4]));
1133 output_asm_insn ("sge %5", loperands);
1134 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1135 CODE_LABEL_NUMBER (loperands[6]));
1136 break;
1137
1138 case GEU:
1139 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1140 CODE_LABEL_NUMBER (loperands[4]));
1141 output_asm_insn ("scc %5", loperands);
1142 break;
1143
1144 case LE:
1145 loperands[6] = gen_label_rtx();
1146 #ifdef MOTOROLA
1147 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1148 #else
1149 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1150 #endif
1151 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1152 CODE_LABEL_NUMBER (loperands[4]));
1153 output_asm_insn ("sle %5", loperands);
1154 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1155 CODE_LABEL_NUMBER (loperands[6]));
1156 break;
1157
1158 case LEU:
1159 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1160 CODE_LABEL_NUMBER (loperands[4]));
1161 output_asm_insn ("sls %5", loperands);
1162 break;
1163
1164 default:
1165 abort ();
1166 }
1167 return "";
1168 }
1169
1170 char *
1171 output_btst (operands, countop, dataop, insn, signpos)
1172 rtx *operands;
1173 rtx countop, dataop;
1174 rtx insn;
1175 int signpos;
1176 {
1177 operands[0] = countop;
1178 operands[1] = dataop;
1179
1180 if (GET_CODE (countop) == CONST_INT)
1181 {
1182 register int count = INTVAL (countop);
1183 /* If COUNT is bigger than size of storage unit in use,
1184 advance to the containing unit of same size. */
1185 if (count > signpos)
1186 {
1187 int offset = (count & ~signpos) / 8;
1188 count = count & signpos;
1189 operands[1] = dataop = adj_offsettable_operand (dataop, offset);
1190 }
1191 if (count == signpos)
1192 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1193 else
1194 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1195
1196 /* These three statements used to use next_insns_test_no...
1197 but it appears that this should do the same job. */
1198 if (count == 31
1199 && next_insn_tests_no_inequality (insn))
1200 return "tst%.l %1";
1201 if (count == 15
1202 && next_insn_tests_no_inequality (insn))
1203 return "tst%.w %1";
1204 if (count == 7
1205 && next_insn_tests_no_inequality (insn))
1206 return "tst%.b %1";
1207
1208 cc_status.flags = CC_NOT_NEGATIVE;
1209 }
1210 return "btst %0,%1";
1211 }
1212 \f
1213 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1214 reference and a constant. */
1215
1216 int
1217 symbolic_operand (op, mode)
1218 register rtx op;
1219 enum machine_mode mode;
1220 {
1221 switch (GET_CODE (op))
1222 {
1223 case SYMBOL_REF:
1224 case LABEL_REF:
1225 return 1;
1226
1227 case CONST:
1228 op = XEXP (op, 0);
1229 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1230 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1231 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1232
1233 #if 0 /* Deleted, with corresponding change in m68k.h,
1234 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1235 case CONST_DOUBLE:
1236 return GET_MODE (op) == mode;
1237 #endif
1238
1239 default:
1240 return 0;
1241 }
1242 }
1243 \f
1244 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1245
1246 int
1247 extend_operator(x, mode)
1248 rtx x;
1249 enum machine_mode mode;
1250 {
1251 if (mode != VOIDmode && GET_MODE(x) != mode)
1252 return 0;
1253 switch (GET_CODE(x))
1254 {
1255 case SIGN_EXTEND :
1256 case ZERO_EXTEND :
1257 return 1;
1258 default :
1259 return 0;
1260 }
1261 }
1262
1263 \f
1264 /* Legitimize PIC addresses. If the address is already
1265 position-independent, we return ORIG. Newly generated
1266 position-independent addresses go to REG. If we need more
1267 than one register, we lose.
1268
1269 An address is legitimized by making an indirect reference
1270 through the Global Offset Table with the name of the symbol
1271 used as an offset.
1272
1273 The assembler and linker are responsible for placing the
1274 address of the symbol in the GOT. The function prologue
1275 is responsible for initializing a5 to the starting address
1276 of the GOT.
1277
1278 The assembler is also responsible for translating a symbol name
1279 into a constant displacement from the start of the GOT.
1280
1281 A quick example may make things a little clearer:
1282
1283 When not generating PIC code to store the value 12345 into _foo
1284 we would generate the following code:
1285
1286 movel #12345, _foo
1287
1288 When generating PIC two transformations are made. First, the compiler
1289 loads the address of foo into a register. So the first transformation makes:
1290
1291 lea _foo, a0
1292 movel #12345, a0@
1293
1294 The code in movsi will intercept the lea instruction and call this
1295 routine which will transform the instructions into:
1296
1297 movel a5@(_foo:w), a0
1298 movel #12345, a0@
1299
1300
1301 That (in a nutshell) is how *all* symbol and label references are
1302 handled. */
1303
1304 rtx
1305 legitimize_pic_address (orig, mode, reg)
1306 rtx orig, reg;
1307 enum machine_mode mode;
1308 {
1309 rtx pic_ref = orig;
1310
1311 /* First handle a simple SYMBOL_REF or LABEL_REF */
1312 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1313 {
1314 if (reg == 0)
1315 abort ();
1316
1317 pic_ref = gen_rtx_MEM (Pmode,
1318 gen_rtx_PLUS (Pmode,
1319 pic_offset_table_rtx, orig));
1320 current_function_uses_pic_offset_table = 1;
1321 if (reload_in_progress)
1322 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
1323 RTX_UNCHANGING_P (pic_ref) = 1;
1324 emit_move_insn (reg, pic_ref);
1325 return reg;
1326 }
1327 else if (GET_CODE (orig) == CONST)
1328 {
1329 rtx base;
1330
1331 /* Make sure this is CONST has not already been legitimized */
1332 if (GET_CODE (XEXP (orig, 0)) == PLUS
1333 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1334 return orig;
1335
1336 if (reg == 0)
1337 abort ();
1338
1339 /* legitimize both operands of the PLUS */
1340 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1341 {
1342 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1343 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1344 base == reg ? 0 : reg);
1345 }
1346 else abort ();
1347
1348 if (GET_CODE (orig) == CONST_INT)
1349 return plus_constant_for_output (base, INTVAL (orig));
1350 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1351 /* Likewise, should we set special REG_NOTEs here? */
1352 }
1353 return pic_ref;
1354 }
1355
1356 \f
1357 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1358
1359 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1360
1361 CONST_METHOD
1362 const_method (constant)
1363 rtx constant;
1364 {
1365 int i;
1366 unsigned u;
1367
1368 i = INTVAL (constant);
1369 if (USE_MOVQ (i))
1370 return MOVQ;
1371
1372 /* The Coldfire doesn't have byte or word operations. */
1373 /* FIXME: This may not be useful for the m68060 either */
1374 if (!TARGET_5200)
1375 {
1376 /* if -256 < N < 256 but N is not in range for a moveq
1377 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1378 if (USE_MOVQ (i ^ 0xff))
1379 return NOTB;
1380 /* Likewise, try with not.w */
1381 if (USE_MOVQ (i ^ 0xffff))
1382 return NOTW;
1383 /* This is the only value where neg.w is useful */
1384 if (i == -65408)
1385 return NEGW;
1386 /* Try also with swap */
1387 u = i;
1388 if (USE_MOVQ ((u >> 16) | (u << 16)))
1389 return SWAP;
1390 }
1391 /* Otherwise, use move.l */
1392 return MOVL;
1393 }
1394
1395 int
1396 const_int_cost (constant)
1397 rtx constant;
1398 {
1399 switch (const_method (constant))
1400 {
1401 case MOVQ :
1402 /* Constants between -128 and 127 are cheap due to moveq */
1403 return 0;
1404 case NOTB :
1405 case NOTW :
1406 case NEGW :
1407 case SWAP :
1408 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1409 return 1;
1410 case MOVL :
1411 return 2;
1412 default :
1413 abort ();
1414 }
1415 }
1416
1417 char *
1418 output_move_const_into_data_reg (operands)
1419 rtx *operands;
1420 {
1421 int i;
1422
1423 i = INTVAL (operands[1]);
1424 switch (const_method (operands[1]))
1425 {
1426 case MOVQ :
1427 #if defined (MOTOROLA) && !defined (CRDS)
1428 return "moveq%.l %1,%0";
1429 #else
1430 return "moveq %1,%0";
1431 #endif
1432 case NOTB :
1433 operands[1] = GEN_INT (i ^ 0xff);
1434 #if defined (MOTOROLA) && !defined (CRDS)
1435 return "moveq%.l %1,%0\n\tnot%.b %0";
1436 #else
1437 return "moveq %1,%0\n\tnot%.b %0";
1438 #endif
1439 case NOTW :
1440 operands[1] = GEN_INT (i ^ 0xffff);
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %1,%0\n\tnot%.w %0";
1443 #else
1444 return "moveq %1,%0\n\tnot%.w %0";
1445 #endif
1446 case NEGW :
1447 #if defined (MOTOROLA) && !defined (CRDS)
1448 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1449 #else
1450 return "moveq %#-128,%0\n\tneg%.w %0";
1451 #endif
1452 case SWAP :
1453 {
1454 unsigned u = i;
1455
1456 operands[1] = GEN_INT ((u << 16) | (u >> 16));
1457 #if defined (MOTOROLA) && !defined (CRDS)
1458 return "moveq%.l %1,%0\n\tswap %0";
1459 #else
1460 return "moveq %1,%0\n\tswap %0";
1461 #endif
1462 }
1463 case MOVL :
1464 return "move%.l %1,%0";
1465 default :
1466 abort ();
1467 }
1468 }
1469
1470 char *
1471 output_move_simode_const (operands)
1472 rtx *operands;
1473 {
1474 if (operands[1] == const0_rtx
1475 && (DATA_REG_P (operands[0])
1476 || GET_CODE (operands[0]) == MEM)
1477 /* clr insns on 68000 read before writing.
1478 This isn't so on the 68010, but we have no TARGET_68010. */
1479 && ((TARGET_68020 || TARGET_5200)
1480 || !(GET_CODE (operands[0]) == MEM
1481 && MEM_VOLATILE_P (operands[0]))))
1482 return "clr%.l %0";
1483 else if (DATA_REG_P (operands[0]))
1484 return output_move_const_into_data_reg (operands);
1485 else if (ADDRESS_REG_P (operands[0])
1486 && INTVAL (operands[1]) < 0x8000
1487 && INTVAL (operands[1]) >= -0x8000)
1488 return "move%.w %1,%0";
1489 else if (GET_CODE (operands[0]) == MEM
1490 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1491 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1492 && INTVAL (operands[1]) < 0x8000
1493 && INTVAL (operands[1]) >= -0x8000)
1494 return "pea %a1";
1495 return "move%.l %1,%0";
1496 }
1497
1498 char *
1499 output_move_simode (operands)
1500 rtx *operands;
1501 {
1502 if (GET_CODE (operands[1]) == CONST_INT)
1503 return output_move_simode_const (operands);
1504 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1505 || GET_CODE (operands[1]) == CONST)
1506 && push_operand (operands[0], SImode))
1507 return "pea %a1";
1508 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1509 || GET_CODE (operands[1]) == CONST)
1510 && ADDRESS_REG_P (operands[0]))
1511 return "lea %a1,%0";
1512 return "move%.l %1,%0";
1513 }
1514
1515 char *
1516 output_move_himode (operands)
1517 rtx *operands;
1518 {
1519 if (GET_CODE (operands[1]) == CONST_INT)
1520 {
1521 if (operands[1] == const0_rtx
1522 && (DATA_REG_P (operands[0])
1523 || GET_CODE (operands[0]) == MEM)
1524 /* clr insns on 68000 read before writing.
1525 This isn't so on the 68010, but we have no TARGET_68010. */
1526 && ((TARGET_68020 || TARGET_5200)
1527 || !(GET_CODE (operands[0]) == MEM
1528 && MEM_VOLATILE_P (operands[0]))))
1529 return "clr%.w %0";
1530 else if (DATA_REG_P (operands[0])
1531 && INTVAL (operands[1]) < 128
1532 && INTVAL (operands[1]) >= -128)
1533 {
1534 #if defined(MOTOROLA) && !defined(CRDS)
1535 return "moveq%.l %1,%0";
1536 #else
1537 return "moveq %1,%0";
1538 #endif
1539 }
1540 else if (INTVAL (operands[1]) < 0x8000
1541 && INTVAL (operands[1]) >= -0x8000)
1542 return "move%.w %1,%0";
1543 }
1544 else if (CONSTANT_P (operands[1]))
1545 return "move%.l %1,%0";
1546 #ifndef SGS_NO_LI
1547 /* Recognize the insn before a tablejump, one that refers
1548 to a table of offsets. Such an insn will need to refer
1549 to a label on the insn. So output one. Use the label-number
1550 of the table of offsets to generate this label. This code,
1551 and similar code below, assumes that there will be at most one
1552 reference to each table. */
1553 if (GET_CODE (operands[1]) == MEM
1554 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1555 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1556 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1557 {
1558 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1559 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1560 #ifdef SGS
1561 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1562 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1563 #else /* not SGS */
1564 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1565 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1566 #endif /* not SGS */
1567 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1568 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
1569 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1570 #ifdef SGS_SWITCH_TABLES
1571 /* Set flag saying we need to define the symbol
1572 LD%n (with value L%n-LI%n) at the end of the switch table. */
1573 switch_table_difference_label_flag = 1;
1574 #endif /* SGS_SWITCH_TABLES */
1575 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1576 }
1577 #endif /* SGS_NO_LI */
1578 return "move%.w %1,%0";
1579 }
1580
1581 char *
1582 output_move_qimode (operands)
1583 rtx *operands;
1584 {
1585 rtx xoperands[4];
1586
1587 /* This is probably useless, since it loses for pushing a struct
1588 of several bytes a byte at a time. */
1589 /* 68k family always modifies the stack pointer by at least 2, even for
1590 byte pushes. The 5200 (coldfire) does not do this. */
1591 if (GET_CODE (operands[0]) == MEM
1592 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1593 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1594 && ! ADDRESS_REG_P (operands[1])
1595 && ! TARGET_5200)
1596 {
1597 xoperands[1] = operands[1];
1598 xoperands[2]
1599 = gen_rtx_MEM (QImode,
1600 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
1601 /* Just pushing a byte puts it in the high byte of the halfword. */
1602 /* We must put it in the low-order, high-numbered byte. */
1603 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1604 {
1605 xoperands[3] = stack_pointer_rtx;
1606 #ifndef NO_ADDSUB_Q
1607 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1608 #else
1609 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1610 #endif
1611 }
1612 else
1613 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
1614 return "";
1615 }
1616
1617 /* clr and st insns on 68000 read before writing.
1618 This isn't so on the 68010, but we have no TARGET_68010. */
1619 if (!ADDRESS_REG_P (operands[0])
1620 && ((TARGET_68020 || TARGET_5200)
1621 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1622 {
1623 if (operands[1] == const0_rtx)
1624 return "clr%.b %0";
1625 if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1626 && GET_CODE (operands[1]) == CONST_INT
1627 && (INTVAL (operands[1]) & 255) == 255)
1628 {
1629 CC_STATUS_INIT;
1630 return "st %0";
1631 }
1632 }
1633 if (GET_CODE (operands[1]) == CONST_INT
1634 && DATA_REG_P (operands[0])
1635 && INTVAL (operands[1]) < 128
1636 && INTVAL (operands[1]) >= -128)
1637 {
1638 #if defined(MOTOROLA) && !defined(CRDS)
1639 return "moveq%.l %1,%0";
1640 #else
1641 return "moveq %1,%0";
1642 #endif
1643 }
1644 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1645 return "move%.l %1,%0";
1646 /* 68k family doesn't support byte moves to from address registers. The
1647 5200 (coldfire) does not have this restriction. */
1648 if ((ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1649 && ! TARGET_5200)
1650 return "move%.w %1,%0";
1651 return "move%.b %1,%0";
1652 }
1653
1654 char *
1655 output_move_stricthi (operands)
1656 rtx *operands;
1657 {
1658 if (operands[1] == const0_rtx
1659 /* clr insns on 68000 read before writing.
1660 This isn't so on the 68010, but we have no TARGET_68010. */
1661 && ((TARGET_68020 || TARGET_5200)
1662 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1663 return "clr%.w %0";
1664 return "move%.w %1,%0";
1665 }
1666
1667 char *
1668 output_move_strictqi (operands)
1669 rtx *operands;
1670 {
1671 if (operands[1] == const0_rtx
1672 /* clr insns on 68000 read before writing.
1673 This isn't so on the 68010, but we have no TARGET_68010. */
1674 && ((TARGET_68020 || TARGET_5200)
1675 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1676 return "clr%.b %0";
1677 return "move%.b %1,%0";
1678 }
1679
1680 /* Return the best assembler insn template
1681 for moving operands[1] into operands[0] as a fullword. */
1682
1683 static char *
1684 singlemove_string (operands)
1685 rtx *operands;
1686 {
1687 #ifdef SUPPORT_SUN_FPA
1688 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1689 return "fpmoves %1,%0";
1690 #endif
1691 if (GET_CODE (operands[1]) == CONST_INT)
1692 return output_move_simode_const (operands);
1693 return "move%.l %1,%0";
1694 }
1695
1696
1697 /* Output assembler code to perform a doubleword move insn
1698 with operands OPERANDS. */
1699
1700 char *
1701 output_move_double (operands)
1702 rtx *operands;
1703 {
1704 enum
1705 {
1706 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1707 } optype0, optype1;
1708 rtx latehalf[2];
1709 rtx middlehalf[2];
1710 rtx xops[2];
1711 rtx addreg0 = 0, addreg1 = 0;
1712 int dest_overlapped_low = 0;
1713 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1714
1715 middlehalf[0] = 0;
1716 middlehalf[1] = 0;
1717
1718 /* First classify both operands. */
1719
1720 if (REG_P (operands[0]))
1721 optype0 = REGOP;
1722 else if (offsettable_memref_p (operands[0]))
1723 optype0 = OFFSOP;
1724 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1725 optype0 = POPOP;
1726 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1727 optype0 = PUSHOP;
1728 else if (GET_CODE (operands[0]) == MEM)
1729 optype0 = MEMOP;
1730 else
1731 optype0 = RNDOP;
1732
1733 if (REG_P (operands[1]))
1734 optype1 = REGOP;
1735 else if (CONSTANT_P (operands[1]))
1736 optype1 = CNSTOP;
1737 else if (offsettable_memref_p (operands[1]))
1738 optype1 = OFFSOP;
1739 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1740 optype1 = POPOP;
1741 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1742 optype1 = PUSHOP;
1743 else if (GET_CODE (operands[1]) == MEM)
1744 optype1 = MEMOP;
1745 else
1746 optype1 = RNDOP;
1747
1748 /* Check for the cases that the operand constraints are not
1749 supposed to allow to happen. Abort if we get one,
1750 because generating code for these cases is painful. */
1751
1752 if (optype0 == RNDOP || optype1 == RNDOP)
1753 abort ();
1754
1755 /* If one operand is decrementing and one is incrementing
1756 decrement the former register explicitly
1757 and change that operand into ordinary indexing. */
1758
1759 if (optype0 == PUSHOP && optype1 == POPOP)
1760 {
1761 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1762 if (size == 12)
1763 output_asm_insn ("sub%.l %#12,%0", operands);
1764 else
1765 output_asm_insn ("subq%.l %#8,%0", operands);
1766 if (GET_MODE (operands[1]) == XFmode)
1767 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1768 else if (GET_MODE (operands[0]) == DFmode)
1769 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1770 else
1771 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1772 optype0 = OFFSOP;
1773 }
1774 if (optype0 == POPOP && optype1 == PUSHOP)
1775 {
1776 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1777 if (size == 12)
1778 output_asm_insn ("sub%.l %#12,%1", operands);
1779 else
1780 output_asm_insn ("subq%.l %#8,%1", operands);
1781 if (GET_MODE (operands[1]) == XFmode)
1782 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1783 else if (GET_MODE (operands[1]) == DFmode)
1784 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1785 else
1786 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1787 optype1 = OFFSOP;
1788 }
1789
1790 /* If an operand is an unoffsettable memory ref, find a register
1791 we can increment temporarily to make it refer to the second word. */
1792
1793 if (optype0 == MEMOP)
1794 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1795
1796 if (optype1 == MEMOP)
1797 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1798
1799 /* Ok, we can do one word at a time.
1800 Normally we do the low-numbered word first,
1801 but if either operand is autodecrementing then we
1802 do the high-numbered word first.
1803
1804 In either case, set up in LATEHALF the operands to use
1805 for the high-numbered word and in some cases alter the
1806 operands in OPERANDS to be suitable for the low-numbered word. */
1807
1808 if (size == 12)
1809 {
1810 if (optype0 == REGOP)
1811 {
1812 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1813 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1814 }
1815 else if (optype0 == OFFSOP)
1816 {
1817 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1818 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1819 }
1820 else
1821 {
1822 middlehalf[0] = operands[0];
1823 latehalf[0] = operands[0];
1824 }
1825
1826 if (optype1 == REGOP)
1827 {
1828 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1829 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1830 }
1831 else if (optype1 == OFFSOP)
1832 {
1833 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1834 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1835 }
1836 else if (optype1 == CNSTOP)
1837 {
1838 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1839 {
1840 REAL_VALUE_TYPE r;
1841 long l[3];
1842
1843 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1844 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1845 operands[1] = GEN_INT (l[0]);
1846 middlehalf[1] = GEN_INT (l[1]);
1847 latehalf[1] = GEN_INT (l[2]);
1848 }
1849 else if (CONSTANT_P (operands[1]))
1850 {
1851 /* actually, no non-CONST_DOUBLE constant should ever
1852 appear here. */
1853 abort ();
1854 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
1855 latehalf[1] = constm1_rtx;
1856 else
1857 latehalf[1] = const0_rtx;
1858 }
1859 }
1860 else
1861 {
1862 middlehalf[1] = operands[1];
1863 latehalf[1] = operands[1];
1864 }
1865 }
1866 else
1867 /* size is not 12: */
1868 {
1869 if (optype0 == REGOP)
1870 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1871 else if (optype0 == OFFSOP)
1872 latehalf[0] = adj_offsettable_operand (operands[0], size - 4);
1873 else
1874 latehalf[0] = operands[0];
1875
1876 if (optype1 == REGOP)
1877 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1878 else if (optype1 == OFFSOP)
1879 latehalf[1] = adj_offsettable_operand (operands[1], size - 4);
1880 else if (optype1 == CNSTOP)
1881 split_double (operands[1], &operands[1], &latehalf[1]);
1882 else
1883 latehalf[1] = operands[1];
1884 }
1885
1886 /* If insn is effectively movd N(sp),-(sp) then we will do the
1887 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1888 for the low word as well, to compensate for the first decrement of sp. */
1889 if (optype0 == PUSHOP
1890 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1891 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1892 operands[1] = middlehalf[1] = latehalf[1];
1893
1894 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1895 if the upper part of reg N does not appear in the MEM, arrange to
1896 emit the move late-half first. Otherwise, compute the MEM address
1897 into the upper part of N and use that as a pointer to the memory
1898 operand. */
1899 if (optype0 == REGOP
1900 && (optype1 == OFFSOP || optype1 == MEMOP))
1901 {
1902 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
1903
1904 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1905 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1906 {
1907 /* If both halves of dest are used in the src memory address,
1908 compute the address into latehalf of dest.
1909 Note that this can't happen if the dest is two data regs. */
1910 compadr:
1911 xops[0] = latehalf[0];
1912 xops[1] = XEXP (operands[1], 0);
1913 output_asm_insn ("lea %a1,%0", xops);
1914 if( GET_MODE (operands[1]) == XFmode )
1915 {
1916 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1917 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1918 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1919 }
1920 else
1921 {
1922 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1923 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1924 }
1925 }
1926 else if (size == 12
1927 && reg_overlap_mentioned_p (middlehalf[0],
1928 XEXP (operands[1], 0)))
1929 {
1930 /* Check for two regs used by both source and dest.
1931 Note that this can't happen if the dest is all data regs.
1932 It can happen if the dest is d6, d7, a0.
1933 But in that case, latehalf is an addr reg, so
1934 the code at compadr does ok. */
1935
1936 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
1937 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1938 goto compadr;
1939
1940 /* JRV says this can't happen: */
1941 if (addreg0 || addreg1)
1942 abort ();
1943
1944 /* Only the middle reg conflicts; simply put it last. */
1945 output_asm_insn (singlemove_string (operands), operands);
1946 output_asm_insn (singlemove_string (latehalf), latehalf);
1947 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1948 return "";
1949 }
1950 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
1951 /* If the low half of dest is mentioned in the source memory
1952 address, the arrange to emit the move late half first. */
1953 dest_overlapped_low = 1;
1954 }
1955
1956 /* If one or both operands autodecrementing,
1957 do the two words, high-numbered first. */
1958
1959 /* Likewise, the first move would clobber the source of the second one,
1960 do them in the other order. This happens only for registers;
1961 such overlap can't happen in memory unless the user explicitly
1962 sets it up, and that is an undefined circumstance. */
1963
1964 if (optype0 == PUSHOP || optype1 == PUSHOP
1965 || (optype0 == REGOP && optype1 == REGOP
1966 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1967 || REGNO (operands[0]) == REGNO (latehalf[1])))
1968 || dest_overlapped_low)
1969 {
1970 /* Make any unoffsettable addresses point at high-numbered word. */
1971 if (addreg0)
1972 {
1973 if (size == 12)
1974 output_asm_insn ("addq%.l %#8,%0", &addreg0);
1975 else
1976 output_asm_insn ("addq%.l %#4,%0", &addreg0);
1977 }
1978 if (addreg1)
1979 {
1980 if (size == 12)
1981 output_asm_insn ("addq%.l %#8,%0", &addreg1);
1982 else
1983 output_asm_insn ("addq%.l %#4,%0", &addreg1);
1984 }
1985
1986 /* Do that word. */
1987 output_asm_insn (singlemove_string (latehalf), latehalf);
1988
1989 /* Undo the adds we just did. */
1990 if (addreg0)
1991 output_asm_insn ("subq%.l %#4,%0", &addreg0);
1992 if (addreg1)
1993 output_asm_insn ("subq%.l %#4,%0", &addreg1);
1994
1995 if (size == 12)
1996 {
1997 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1998 if (addreg0)
1999 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2000 if (addreg1)
2001 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2002 }
2003
2004 /* Do low-numbered word. */
2005 return singlemove_string (operands);
2006 }
2007
2008 /* Normal case: do the two words, low-numbered first. */
2009
2010 output_asm_insn (singlemove_string (operands), operands);
2011
2012 /* Do the middle one of the three words for long double */
2013 if (size == 12)
2014 {
2015 if (addreg0)
2016 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2017 if (addreg1)
2018 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2019
2020 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2021 }
2022
2023 /* Make any unoffsettable addresses point at high-numbered word. */
2024 if (addreg0)
2025 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2026 if (addreg1)
2027 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2028
2029 /* Do that word. */
2030 output_asm_insn (singlemove_string (latehalf), latehalf);
2031
2032 /* Undo the adds we just did. */
2033 if (addreg0)
2034 {
2035 if (size == 12)
2036 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2037 else
2038 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2039 }
2040 if (addreg1)
2041 {
2042 if (size == 12)
2043 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2044 else
2045 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2046 }
2047
2048 return "";
2049 }
2050
2051 /* Return a REG that occurs in ADDR with coefficient 1.
2052 ADDR can be effectively incremented by incrementing REG. */
2053
2054 static rtx
2055 find_addr_reg (addr)
2056 rtx addr;
2057 {
2058 while (GET_CODE (addr) == PLUS)
2059 {
2060 if (GET_CODE (XEXP (addr, 0)) == REG)
2061 addr = XEXP (addr, 0);
2062 else if (GET_CODE (XEXP (addr, 1)) == REG)
2063 addr = XEXP (addr, 1);
2064 else if (CONSTANT_P (XEXP (addr, 0)))
2065 addr = XEXP (addr, 1);
2066 else if (CONSTANT_P (XEXP (addr, 1)))
2067 addr = XEXP (addr, 0);
2068 else
2069 abort ();
2070 }
2071 if (GET_CODE (addr) == REG)
2072 return addr;
2073 abort ();
2074 }
2075
2076 /* Output assembler code to perform a 32 bit 3 operand add. */
2077
2078 char *
2079 output_addsi3 (operands)
2080 rtx *operands;
2081 {
2082 if (! operands_match_p (operands[0], operands[1]))
2083 {
2084 if (!ADDRESS_REG_P (operands[1]))
2085 {
2086 rtx tmp = operands[1];
2087
2088 operands[1] = operands[2];
2089 operands[2] = tmp;
2090 }
2091
2092 /* These insns can result from reloads to access
2093 stack slots over 64k from the frame pointer. */
2094 if (GET_CODE (operands[2]) == CONST_INT
2095 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2096 return "move%.l %2,%0\n\tadd%.l %1,%0";
2097 #ifdef SGS
2098 if (GET_CODE (operands[2]) == REG)
2099 return "lea 0(%1,%2.l),%0";
2100 else
2101 return "lea %c2(%1),%0";
2102 #else /* not SGS */
2103 #ifdef MOTOROLA
2104 if (GET_CODE (operands[2]) == REG)
2105 return "lea (%1,%2.l),%0";
2106 else
2107 return "lea (%c2,%1),%0";
2108 #else /* not MOTOROLA (MIT syntax) */
2109 if (GET_CODE (operands[2]) == REG)
2110 return "lea %1@(0,%2:l),%0";
2111 else
2112 return "lea %1@(%c2),%0";
2113 #endif /* not MOTOROLA */
2114 #endif /* not SGS */
2115 }
2116 if (GET_CODE (operands[2]) == CONST_INT)
2117 {
2118 #ifndef NO_ADDSUB_Q
2119 if (INTVAL (operands[2]) > 0
2120 && INTVAL (operands[2]) <= 8)
2121 return "addq%.l %2,%0";
2122 if (INTVAL (operands[2]) < 0
2123 && INTVAL (operands[2]) >= -8)
2124 {
2125 operands[2] = GEN_INT (-INTVAL (operands[2]));
2126 return "subq%.l %2,%0";
2127 }
2128 /* On the CPU32 it is faster to use two addql instructions to
2129 add a small integer (8 < N <= 16) to a register.
2130 Likewise for subql. */
2131 if (TARGET_CPU32 && REG_P (operands[0]))
2132 {
2133 if (INTVAL (operands[2]) > 8
2134 && INTVAL (operands[2]) <= 16)
2135 {
2136 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2137 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2138 }
2139 if (INTVAL (operands[2]) < -8
2140 && INTVAL (operands[2]) >= -16)
2141 {
2142 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2143 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2144 }
2145 }
2146 #endif
2147 if (ADDRESS_REG_P (operands[0])
2148 && INTVAL (operands[2]) >= -0x8000
2149 && INTVAL (operands[2]) < 0x8000)
2150 {
2151 if (TARGET_68040)
2152 return "add%.w %2,%0";
2153 else
2154 #ifdef MOTOROLA
2155 return "lea (%c2,%0),%0";
2156 #else
2157 return "lea %0@(%c2),%0";
2158 #endif
2159 }
2160 }
2161 return "add%.l %2,%0";
2162 }
2163 \f
2164 /* Store in cc_status the expressions that the condition codes will
2165 describe after execution of an instruction whose pattern is EXP.
2166 Do not alter them if the instruction would not alter the cc's. */
2167
2168 /* On the 68000, all the insns to store in an address register fail to
2169 set the cc's. However, in some cases these instructions can make it
2170 possibly invalid to use the saved cc's. In those cases we clear out
2171 some or all of the saved cc's so they won't be used. */
2172
2173 void
2174 notice_update_cc (exp, insn)
2175 rtx exp;
2176 rtx insn;
2177 {
2178 /* If the cc is being set from the fpa and the expression is not an
2179 explicit floating point test instruction (which has code to deal with
2180 this), reinit the CC. */
2181 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
2182 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
2183 && !(GET_CODE (exp) == PARALLEL
2184 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
2185 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
2186 {
2187 CC_STATUS_INIT;
2188 }
2189 else if (GET_CODE (exp) == SET)
2190 {
2191 if (GET_CODE (SET_SRC (exp)) == CALL)
2192 {
2193 CC_STATUS_INIT;
2194 }
2195 else if (ADDRESS_REG_P (SET_DEST (exp)))
2196 {
2197 if (cc_status.value1
2198 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
2199 cc_status.value1 = 0;
2200 if (cc_status.value2
2201 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
2202 cc_status.value2 = 0;
2203 }
2204 else if (!FP_REG_P (SET_DEST (exp))
2205 && SET_DEST (exp) != cc0_rtx
2206 && (FP_REG_P (SET_SRC (exp))
2207 || GET_CODE (SET_SRC (exp)) == FIX
2208 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2209 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2210 {
2211 CC_STATUS_INIT;
2212 }
2213 /* A pair of move insns doesn't produce a useful overall cc. */
2214 else if (!FP_REG_P (SET_DEST (exp))
2215 && !FP_REG_P (SET_SRC (exp))
2216 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2217 && (GET_CODE (SET_SRC (exp)) == REG
2218 || GET_CODE (SET_SRC (exp)) == MEM
2219 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2220 {
2221 CC_STATUS_INIT;
2222 }
2223 else if (GET_CODE (SET_SRC (exp)) == CALL)
2224 {
2225 CC_STATUS_INIT;
2226 }
2227 else if (XEXP (exp, 0) != pc_rtx)
2228 {
2229 cc_status.flags = 0;
2230 cc_status.value1 = XEXP (exp, 0);
2231 cc_status.value2 = XEXP (exp, 1);
2232 }
2233 }
2234 else if (GET_CODE (exp) == PARALLEL
2235 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2236 {
2237 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2238 CC_STATUS_INIT;
2239 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2240 {
2241 cc_status.flags = 0;
2242 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2243 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2244 }
2245 }
2246 else
2247 CC_STATUS_INIT;
2248 if (cc_status.value2 != 0
2249 && ADDRESS_REG_P (cc_status.value2)
2250 && GET_MODE (cc_status.value2) == QImode)
2251 CC_STATUS_INIT;
2252 if (cc_status.value2 != 0
2253 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
2254 switch (GET_CODE (cc_status.value2))
2255 {
2256 case PLUS: case MINUS: case MULT:
2257 case DIV: case UDIV: case MOD: case UMOD: case NEG:
2258 #if 0 /* These instructions always clear the overflow bit */
2259 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
2260 case ROTATE: case ROTATERT:
2261 #endif
2262 if (GET_MODE (cc_status.value2) != VOIDmode)
2263 cc_status.flags |= CC_NO_OVERFLOW;
2264 break;
2265 case ZERO_EXTEND:
2266 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2267 ends with a move insn moving r2 in r2's mode.
2268 Thus, the cc's are set for r2.
2269 This can set N bit spuriously. */
2270 cc_status.flags |= CC_NOT_NEGATIVE;
2271
2272 default:
2273 break;
2274 }
2275 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2276 && cc_status.value2
2277 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2278 cc_status.value2 = 0;
2279 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2280 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
2281 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
2282 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
2283 cc_status.flags = CC_IN_68881;
2284 }
2285 \f
2286 char *
2287 output_move_const_double (operands)
2288 rtx *operands;
2289 {
2290 #ifdef SUPPORT_SUN_FPA
2291 if (TARGET_FPA && FPA_REG_P (operands[0]))
2292 {
2293 int code = standard_sun_fpa_constant_p (operands[1]);
2294
2295 if (code != 0)
2296 {
2297 static char buf[40];
2298
2299 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
2300 return buf;
2301 }
2302 return "fpmove%.d %1,%0";
2303 }
2304 else
2305 #endif
2306 {
2307 int code = standard_68881_constant_p (operands[1]);
2308
2309 if (code != 0)
2310 {
2311 static char buf[40];
2312
2313 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2314 return buf;
2315 }
2316 return "fmove%.d %1,%0";
2317 }
2318 }
2319
2320 char *
2321 output_move_const_single (operands)
2322 rtx *operands;
2323 {
2324 #ifdef SUPPORT_SUN_FPA
2325 if (TARGET_FPA)
2326 {
2327 int code = standard_sun_fpa_constant_p (operands[1]);
2328
2329 if (code != 0)
2330 {
2331 static char buf[40];
2332
2333 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
2334 return buf;
2335 }
2336 return "fpmove%.s %1,%0";
2337 }
2338 else
2339 #endif /* defined SUPPORT_SUN_FPA */
2340 {
2341 int code = standard_68881_constant_p (operands[1]);
2342
2343 if (code != 0)
2344 {
2345 static char buf[40];
2346
2347 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2348 return buf;
2349 }
2350 return "fmove%.s %f1,%0";
2351 }
2352 }
2353
2354 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2355 from the "fmovecr" instruction.
2356 The value, anded with 0xff, gives the code to use in fmovecr
2357 to get the desired constant. */
2358
2359 /* This code has been fixed for cross-compilation. */
2360
2361 static int inited_68881_table = 0;
2362
2363 char *strings_68881[7] = {
2364 "0.0",
2365 "1.0",
2366 "10.0",
2367 "100.0",
2368 "10000.0",
2369 "1e8",
2370 "1e16"
2371 };
2372
2373 int codes_68881[7] = {
2374 0x0f,
2375 0x32,
2376 0x33,
2377 0x34,
2378 0x35,
2379 0x36,
2380 0x37
2381 };
2382
2383 REAL_VALUE_TYPE values_68881[7];
2384
2385 /* Set up values_68881 array by converting the decimal values
2386 strings_68881 to binary. */
2387
2388 void
2389 init_68881_table ()
2390 {
2391 int i;
2392 REAL_VALUE_TYPE r;
2393 enum machine_mode mode;
2394
2395 mode = SFmode;
2396 for (i = 0; i < 7; i++)
2397 {
2398 if (i == 6)
2399 mode = DFmode;
2400 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2401 values_68881[i] = r;
2402 }
2403 inited_68881_table = 1;
2404 }
2405
2406 int
2407 standard_68881_constant_p (x)
2408 rtx x;
2409 {
2410 REAL_VALUE_TYPE r;
2411 int i;
2412
2413 #ifdef NO_ASM_FMOVECR
2414 return 0;
2415 #endif
2416
2417 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2418 if (TARGET_68040)
2419 return 0;
2420
2421 #ifndef REAL_ARITHMETIC
2422 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2423 if (! flag_pretend_float)
2424 return 0;
2425 #endif
2426 #endif
2427
2428 if (! inited_68881_table)
2429 init_68881_table ();
2430
2431 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2432
2433 for (i = 0; i < 6; i++)
2434 {
2435 if (REAL_VALUES_EQUAL (r, values_68881[i]))
2436 return (codes_68881[i]);
2437 }
2438
2439 if (GET_MODE (x) == SFmode)
2440 return 0;
2441
2442 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2443 return (codes_68881[6]);
2444
2445 /* larger powers of ten in the constants ram are not used
2446 because they are not equal to a `double' C constant. */
2447 return 0;
2448 }
2449
2450 /* If X is a floating-point constant, return the logarithm of X base 2,
2451 or 0 if X is not a power of 2. */
2452
2453 int
2454 floating_exact_log2 (x)
2455 rtx x;
2456 {
2457 REAL_VALUE_TYPE r, r1;
2458 int i;
2459
2460 #ifndef REAL_ARITHMETIC
2461 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2462 if (! flag_pretend_float)
2463 return 0;
2464 #endif
2465 #endif
2466
2467 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2468
2469 if (REAL_VALUES_LESS (r, dconst0))
2470 return 0;
2471
2472 r1 = dconst1;
2473 i = 0;
2474 while (REAL_VALUES_LESS (r1, r))
2475 {
2476 r1 = REAL_VALUE_LDEXP (dconst1, i);
2477 if (REAL_VALUES_EQUAL (r1, r))
2478 return i;
2479 i = i + 1;
2480 }
2481 return 0;
2482 }
2483 \f
2484 #ifdef SUPPORT_SUN_FPA
2485 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2486 from the Sun FPA's constant RAM.
2487 The value returned, anded with 0x1ff, gives the code to use in fpmove
2488 to get the desired constant. */
2489
2490 static int inited_FPA_table = 0;
2491
2492 char *strings_FPA[38] = {
2493 /* small rationals */
2494 "0.0",
2495 "1.0",
2496 "0.5",
2497 "-1.0",
2498 "2.0",
2499 "3.0",
2500 "4.0",
2501 "8.0",
2502 "0.25",
2503 "0.125",
2504 "10.0",
2505 "-0.5",
2506 /* Decimal equivalents of double precision values */
2507 "2.718281828459045091", /* D_E */
2508 "6.283185307179586477", /* 2 pi */
2509 "3.141592653589793116", /* D_PI */
2510 "1.570796326794896619", /* pi/2 */
2511 "1.414213562373095145", /* D_SQRT2 */
2512 "0.7071067811865475244", /* 1/sqrt(2) */
2513 "-1.570796326794896619", /* -pi/2 */
2514 "1.442695040888963387", /* D_LOG2ofE */
2515 "3.321928024887362182", /* D_LOG2of10 */
2516 "0.6931471805599452862", /* D_LOGEof2 */
2517 "2.302585092994045901", /* D_LOGEof10 */
2518 "0.3010299956639811980", /* D_LOG10of2 */
2519 "0.4342944819032518167", /* D_LOG10ofE */
2520 /* Decimal equivalents of single precision values */
2521 "2.718281745910644531", /* S_E */
2522 "6.283185307179586477", /* 2 pi */
2523 "3.141592741012573242", /* S_PI */
2524 "1.570796326794896619", /* pi/2 */
2525 "1.414213538169860840", /* S_SQRT2 */
2526 "0.7071067811865475244", /* 1/sqrt(2) */
2527 "-1.570796326794896619", /* -pi/2 */
2528 "1.442695021629333496", /* S_LOG2ofE */
2529 "3.321928024291992188", /* S_LOG2of10 */
2530 "0.6931471824645996094", /* S_LOGEof2 */
2531 "2.302585124969482442", /* S_LOGEof10 */
2532 "0.3010300099849700928", /* S_LOG10of2 */
2533 "0.4342944920063018799", /* S_LOG10ofE */
2534 };
2535
2536
2537 int codes_FPA[38] = {
2538 /* small rationals */
2539 0x200,
2540 0xe,
2541 0xf,
2542 0x10,
2543 0x11,
2544 0xb1,
2545 0x12,
2546 0x13,
2547 0x15,
2548 0x16,
2549 0x17,
2550 0x2e,
2551 /* double precision */
2552 0x8,
2553 0x9,
2554 0xa,
2555 0xb,
2556 0xc,
2557 0xd,
2558 0x27,
2559 0x28,
2560 0x29,
2561 0x2a,
2562 0x2b,
2563 0x2c,
2564 0x2d,
2565 /* single precision */
2566 0x8,
2567 0x9,
2568 0xa,
2569 0xb,
2570 0xc,
2571 0xd,
2572 0x27,
2573 0x28,
2574 0x29,
2575 0x2a,
2576 0x2b,
2577 0x2c,
2578 0x2d
2579 };
2580
2581 REAL_VALUE_TYPE values_FPA[38];
2582
2583 /* This code has been fixed for cross-compilation. */
2584
2585 void
2586 init_FPA_table ()
2587 {
2588 enum machine_mode mode;
2589 int i;
2590 REAL_VALUE_TYPE r;
2591
2592 mode = DFmode;
2593 for (i = 0; i < 38; i++)
2594 {
2595 if (i == 25)
2596 mode = SFmode;
2597 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2598 values_FPA[i] = r;
2599 }
2600 inited_FPA_table = 1;
2601 }
2602
2603
2604 int
2605 standard_sun_fpa_constant_p (x)
2606 rtx x;
2607 {
2608 REAL_VALUE_TYPE r;
2609 int i;
2610
2611 #ifndef REAL_ARITHMETIC
2612 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2613 if (! flag_pretend_float)
2614 return 0;
2615 #endif
2616 #endif
2617
2618 if (! inited_FPA_table)
2619 init_FPA_table ();
2620
2621 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2622
2623 for (i=0; i<12; i++)
2624 {
2625 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2626 return (codes_FPA[i]);
2627 }
2628
2629 if (GET_MODE (x) == SFmode)
2630 {
2631 for (i=25; i<38; i++)
2632 {
2633 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2634 return (codes_FPA[i]);
2635 }
2636 }
2637 else
2638 {
2639 for (i=12; i<25; i++)
2640 {
2641 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2642 return (codes_FPA[i]);
2643 }
2644 }
2645 return 0x0;
2646 }
2647 #endif /* define SUPPORT_SUN_FPA */
2648 \f
2649 /* A C compound statement to output to stdio stream STREAM the
2650 assembler syntax for an instruction operand X. X is an RTL
2651 expression.
2652
2653 CODE is a value that can be used to specify one of several ways
2654 of printing the operand. It is used when identical operands
2655 must be printed differently depending on the context. CODE
2656 comes from the `%' specification that was used to request
2657 printing of the operand. If the specification was just `%DIGIT'
2658 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2659 is the ASCII code for LTR.
2660
2661 If X is a register, this macro should print the register's name.
2662 The names can be found in an array `reg_names' whose type is
2663 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2664
2665 When the machine description has a specification `%PUNCT' (a `%'
2666 followed by a punctuation character), this macro is called with
2667 a null pointer for X and the punctuation character for CODE.
2668
2669 The m68k specific codes are:
2670
2671 '.' for dot needed in Motorola-style opcode names.
2672 '-' for an operand pushing on the stack:
2673 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2674 '+' for an operand pushing on the stack:
2675 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2676 '@' for a reference to the top word on the stack:
2677 sp@, (sp) or (%sp) depending on the style of syntax.
2678 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2679 but & in SGS syntax, $ in CRDS/UNOS syntax).
2680 '!' for the cc register (used in an `and to cc' insn).
2681 '$' for the letter `s' in an op code, but only on the 68040.
2682 '&' for the letter `d' in an op code, but only on the 68040.
2683 '/' for register prefix needed by longlong.h.
2684
2685 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2686 'd' to force memory addressing to be absolute, not relative.
2687 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2688 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2689 than directly). Second part of 'y' below.
2690 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2691 or print pair of registers as rx:ry.
2692 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2693 CONST_DOUBLE's as SunFPA constant RAM registers if
2694 possible, so it should not be used except for the SunFPA.
2695
2696 */
2697
2698 void
2699 print_operand (file, op, letter)
2700 FILE *file; /* file to write to */
2701 rtx op; /* operand to print */
2702 int letter; /* %<letter> or 0 */
2703 {
2704 #ifdef SUPPORT_SUN_FPA
2705 int i;
2706 #endif
2707
2708 if (letter == '.')
2709 {
2710 #if defined (MOTOROLA) && !defined (CRDS)
2711 asm_fprintf (file, ".");
2712 #endif
2713 }
2714 else if (letter == '#')
2715 {
2716 asm_fprintf (file, "%0I");
2717 }
2718 else if (letter == '-')
2719 {
2720 #ifdef MOTOROLA
2721 asm_fprintf (file, "-(%Rsp)");
2722 #else
2723 asm_fprintf (file, "%Rsp@-");
2724 #endif
2725 }
2726 else if (letter == '+')
2727 {
2728 #ifdef MOTOROLA
2729 asm_fprintf (file, "(%Rsp)+");
2730 #else
2731 asm_fprintf (file, "%Rsp@+");
2732 #endif
2733 }
2734 else if (letter == '@')
2735 {
2736 #ifdef MOTOROLA
2737 asm_fprintf (file, "(%Rsp)");
2738 #else
2739 asm_fprintf (file, "%Rsp@");
2740 #endif
2741 }
2742 else if (letter == '!')
2743 {
2744 asm_fprintf (file, "%Rfpcr");
2745 }
2746 else if (letter == '$')
2747 {
2748 if (TARGET_68040_ONLY)
2749 {
2750 fprintf (file, "s");
2751 }
2752 }
2753 else if (letter == '&')
2754 {
2755 if (TARGET_68040_ONLY)
2756 {
2757 fprintf (file, "d");
2758 }
2759 }
2760 else if (letter == '/')
2761 {
2762 asm_fprintf (file, "%R");
2763 }
2764 else if (GET_CODE (op) == REG)
2765 {
2766 #ifdef SUPPORT_SUN_FPA
2767 if (REGNO (op) < 16
2768 && (letter == 'y' || letter == 'x')
2769 && GET_MODE (op) == DFmode)
2770 {
2771 fprintf (file, "%s:%s", reg_names[REGNO (op)],
2772 reg_names[REGNO (op)+1]);
2773 }
2774 else
2775 #endif
2776 {
2777 if (letter == 'R')
2778 /* Print out the second register name of a register pair.
2779 I.e., R (6) => 7. */
2780 fputs (reg_names[REGNO (op) + 1], file);
2781 else
2782 fputs (reg_names[REGNO (op)], file);
2783 }
2784 }
2785 else if (GET_CODE (op) == MEM)
2786 {
2787 output_address (XEXP (op, 0));
2788 if (letter == 'd' && ! TARGET_68020
2789 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2790 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2791 && INTVAL (XEXP (op, 0)) < 0x8000
2792 && INTVAL (XEXP (op, 0)) >= -0x8000))
2793 {
2794 #ifdef MOTOROLA
2795 fprintf (file, ".l");
2796 #else
2797 fprintf (file, ":l");
2798 #endif
2799 }
2800 }
2801 #ifdef SUPPORT_SUN_FPA
2802 else if ((letter == 'y' || letter == 'w')
2803 && GET_CODE (op) == CONST_DOUBLE
2804 && (i = standard_sun_fpa_constant_p (op)))
2805 {
2806 fprintf (file, "%%%d", i & 0x1ff);
2807 }
2808 #endif
2809 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2810 {
2811 REAL_VALUE_TYPE r;
2812 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2813 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2814 }
2815 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2816 {
2817 REAL_VALUE_TYPE r;
2818 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2819 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
2820 }
2821 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
2822 {
2823 REAL_VALUE_TYPE r;
2824 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2825 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
2826 }
2827 else
2828 {
2829 asm_fprintf (file, "%0I"); output_addr_const (file, op);
2830 }
2831 }
2832
2833 \f
2834 /* A C compound statement to output to stdio stream STREAM the
2835 assembler syntax for an instruction operand that is a memory
2836 reference whose address is ADDR. ADDR is an RTL expression.
2837
2838 Note that this contains a kludge that knows that the only reason
2839 we have an address (plus (label_ref...) (reg...)) when not generating
2840 PIC code is in the insn before a tablejump, and we know that m68k.md
2841 generates a label LInnn: on such an insn.
2842
2843 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2844 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2845
2846 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2847 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2848 we want. This difference can be accommodated by using an assembler
2849 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2850 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2851 macro. See m68k/sgs.h for an example; for versions without the bug.
2852 Some assemblers refuse all the above solutions. The workaround is to
2853 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2854 right behaviour.
2855
2856 They also do not like things like "pea 1.w", so we simple leave off
2857 the .w on small constants.
2858
2859 This routine is responsible for distinguishing between -fpic and -fPIC
2860 style relocations in an address. When generating -fpic code the
2861 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2862 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2863
2864 #ifndef ASM_OUTPUT_CASE_FETCH
2865 #ifdef MOTOROLA
2866 #ifdef SGS
2867 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2868 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2869 #else
2870 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2871 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2872 #endif
2873 #else
2874 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2875 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2876 #endif
2877 #endif /* ASM_OUTPUT_CASE_FETCH */
2878
2879 void
2880 print_operand_address (file, addr)
2881 FILE *file;
2882 rtx addr;
2883 {
2884 register rtx reg1, reg2, breg, ireg;
2885 rtx offset;
2886
2887 switch (GET_CODE (addr))
2888 {
2889 case REG:
2890 #ifdef MOTOROLA
2891 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2892 #else
2893 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2894 #endif
2895 break;
2896 case PRE_DEC:
2897 #ifdef MOTOROLA
2898 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2899 #else
2900 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2901 #endif
2902 break;
2903 case POST_INC:
2904 #ifdef MOTOROLA
2905 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2906 #else
2907 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2908 #endif
2909 break;
2910 case PLUS:
2911 reg1 = reg2 = ireg = breg = offset = 0;
2912 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2913 {
2914 offset = XEXP (addr, 0);
2915 addr = XEXP (addr, 1);
2916 }
2917 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2918 {
2919 offset = XEXP (addr, 1);
2920 addr = XEXP (addr, 0);
2921 }
2922 if (GET_CODE (addr) != PLUS)
2923 {
2924 ;
2925 }
2926 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2927 {
2928 reg1 = XEXP (addr, 0);
2929 addr = XEXP (addr, 1);
2930 }
2931 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2932 {
2933 reg1 = XEXP (addr, 1);
2934 addr = XEXP (addr, 0);
2935 }
2936 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2937 {
2938 reg1 = XEXP (addr, 0);
2939 addr = XEXP (addr, 1);
2940 }
2941 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2942 {
2943 reg1 = XEXP (addr, 1);
2944 addr = XEXP (addr, 0);
2945 }
2946 else if (GET_CODE (XEXP (addr, 0)) == REG)
2947 {
2948 reg1 = XEXP (addr, 0);
2949 addr = XEXP (addr, 1);
2950 }
2951 else if (GET_CODE (XEXP (addr, 1)) == REG)
2952 {
2953 reg1 = XEXP (addr, 1);
2954 addr = XEXP (addr, 0);
2955 }
2956 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2957 || GET_CODE (addr) == SIGN_EXTEND)
2958 {
2959 if (reg1 == 0)
2960 {
2961 reg1 = addr;
2962 }
2963 else
2964 {
2965 reg2 = addr;
2966 }
2967 addr = 0;
2968 }
2969 #if 0 /* for OLD_INDEXING */
2970 else if (GET_CODE (addr) == PLUS)
2971 {
2972 if (GET_CODE (XEXP (addr, 0)) == REG)
2973 {
2974 reg2 = XEXP (addr, 0);
2975 addr = XEXP (addr, 1);
2976 }
2977 else if (GET_CODE (XEXP (addr, 1)) == REG)
2978 {
2979 reg2 = XEXP (addr, 1);
2980 addr = XEXP (addr, 0);
2981 }
2982 }
2983 #endif
2984 if (offset != 0)
2985 {
2986 if (addr != 0)
2987 {
2988 abort ();
2989 }
2990 addr = offset;
2991 }
2992 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
2993 || GET_CODE (reg1) == MULT))
2994 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2995 {
2996 breg = reg2;
2997 ireg = reg1;
2998 }
2999 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3000 {
3001 breg = reg1;
3002 ireg = reg2;
3003 }
3004 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
3005 && ! (flag_pic && ireg == pic_offset_table_rtx))
3006 {
3007 int scale = 1;
3008 if (GET_CODE (ireg) == MULT)
3009 {
3010 scale = INTVAL (XEXP (ireg, 1));
3011 ireg = XEXP (ireg, 0);
3012 }
3013 if (GET_CODE (ireg) == SIGN_EXTEND)
3014 {
3015 ASM_OUTPUT_CASE_FETCH (file,
3016 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3017 reg_names[REGNO (XEXP (ireg, 0))]);
3018 fprintf (file, "w");
3019 }
3020 else
3021 {
3022 ASM_OUTPUT_CASE_FETCH (file,
3023 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3024 reg_names[REGNO (ireg)]);
3025 fprintf (file, "l");
3026 }
3027 if (scale != 1)
3028 {
3029 #ifdef MOTOROLA
3030 fprintf (file, "*%d", scale);
3031 #else
3032 fprintf (file, ":%d", scale);
3033 #endif
3034 }
3035 putc (')', file);
3036 break;
3037 }
3038 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
3039 && ! (flag_pic && breg == pic_offset_table_rtx))
3040 {
3041 ASM_OUTPUT_CASE_FETCH (file,
3042 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3043 reg_names[REGNO (breg)]);
3044 fprintf (file, "l)");
3045 break;
3046 }
3047 if (ireg != 0 || breg != 0)
3048 {
3049 int scale = 1;
3050 if (breg == 0)
3051 {
3052 abort ();
3053 }
3054 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
3055 {
3056 abort ();
3057 }
3058 #ifdef MOTOROLA
3059 if (addr != 0)
3060 {
3061 output_addr_const (file, addr);
3062 if (flag_pic && (breg == pic_offset_table_rtx))
3063 {
3064 fprintf (file, "@GOT");
3065 if (flag_pic == 1)
3066 fprintf (file, ".w");
3067 }
3068 }
3069 fprintf (file, "(%s", reg_names[REGNO (breg)]);
3070 if (ireg != 0)
3071 {
3072 putc (',', file);
3073 }
3074 #else
3075 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
3076 if (addr != 0)
3077 {
3078 output_addr_const (file, addr);
3079 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
3080 fprintf (file, ":w");
3081 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
3082 fprintf (file, ":l");
3083 }
3084 if (addr != 0 && ireg != 0)
3085 {
3086 putc (',', file);
3087 }
3088 #endif
3089 if (ireg != 0 && GET_CODE (ireg) == MULT)
3090 {
3091 scale = INTVAL (XEXP (ireg, 1));
3092 ireg = XEXP (ireg, 0);
3093 }
3094 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
3095 {
3096 #ifdef MOTOROLA
3097 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
3098 #else
3099 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
3100 #endif
3101 }
3102 else if (ireg != 0)
3103 {
3104 #ifdef MOTOROLA
3105 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3106 #else
3107 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3108 #endif
3109 }
3110 if (scale != 1)
3111 {
3112 #ifdef MOTOROLA
3113 fprintf (file, "*%d", scale);
3114 #else
3115 fprintf (file, ":%d", scale);
3116 #endif
3117 }
3118 putc (')', file);
3119 break;
3120 }
3121 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
3122 && ! (flag_pic && reg1 == pic_offset_table_rtx))
3123 {
3124 ASM_OUTPUT_CASE_FETCH (file,
3125 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3126 reg_names[REGNO (reg1)]);
3127 fprintf (file, "l)");
3128 break;
3129 }
3130 /* FALL-THROUGH (is this really what we want? */
3131 default:
3132 if (GET_CODE (addr) == CONST_INT
3133 && INTVAL (addr) < 0x8000
3134 && INTVAL (addr) >= -0x8000)
3135 {
3136 #ifdef MOTOROLA
3137 #ifdef SGS
3138 /* Many SGS assemblers croak on size specifiers for constants. */
3139 fprintf (file, "%d", INTVAL (addr));
3140 #else
3141 fprintf (file, "%d.w", INTVAL (addr));
3142 #endif
3143 #else
3144 fprintf (file, "%d:w", INTVAL (addr));
3145 #endif
3146 }
3147 else
3148 {
3149 output_addr_const (file, addr);
3150 }
3151 break;
3152 }
3153 }
3154 \f
3155 /* Check for cases where a clr insns can be omitted from code using
3156 strict_low_part sets. For example, the second clrl here is not needed:
3157 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3158
3159 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3160 insn we are checking for redundancy. TARGET is the register set by the
3161 clear insn. */
3162
3163 int
3164 strict_low_part_peephole_ok (mode, first_insn, target)
3165 enum machine_mode mode;
3166 rtx first_insn;
3167 rtx target;
3168 {
3169 rtx p;
3170
3171 p = prev_nonnote_insn (first_insn);
3172
3173 while (p)
3174 {
3175 /* If it isn't an insn, then give up. */
3176 if (GET_CODE (p) != INSN)
3177 return 0;
3178
3179 if (reg_set_p (target, p))
3180 {
3181 rtx set = single_set (p);
3182 rtx dest;
3183
3184 /* If it isn't an easy to recognize insn, then give up. */
3185 if (! set)
3186 return 0;
3187
3188 dest = SET_DEST (set);
3189
3190 /* If this sets the entire target register to zero, then our
3191 first_insn is redundant. */
3192 if (rtx_equal_p (dest, target)
3193 && SET_SRC (set) == const0_rtx)
3194 return 1;
3195 else if (GET_CODE (dest) == STRICT_LOW_PART
3196 && GET_CODE (XEXP (dest, 0)) == REG
3197 && REGNO (XEXP (dest, 0)) == REGNO (target)
3198 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3199 <= GET_MODE_SIZE (mode)))
3200 /* This is a strict low part set which modifies less than
3201 we are using, so it is safe. */
3202 ;
3203 else
3204 return 0;
3205 }
3206
3207 p = prev_nonnote_insn (p);
3208
3209 }
3210
3211 return 0;
3212 }
3213
3214 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3215 range carefully since this predicate is used in DImode contexts. Also, we
3216 need some extra crud to make it work when hosted on 64-bit machines. */
3217
3218 int
3219 const_uint32_operand (op, mode)
3220 rtx op;
3221 enum machine_mode mode;
3222 {
3223 #if HOST_BITS_PER_WIDE_INT > 32
3224 /* All allowed constants will fit a CONST_INT. */
3225 return (GET_CODE (op) == CONST_INT
3226 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3227 #else
3228 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
3229 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3230 #endif
3231 }
3232
3233 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3234 to check the range carefully since this predicate is used in DImode
3235 contexts. */
3236
3237 int
3238 const_sint32_operand (op, mode)
3239 rtx op;
3240 enum machine_mode mode;
3241 {
3242 /* All allowed constants will fit a CONST_INT. */
3243 return (GET_CODE (op) == CONST_INT
3244 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3245 }
3246
3247 char *
3248 output_andsi3 (operands)
3249 rtx *operands;
3250 {
3251 int logval;
3252 if (GET_CODE (operands[2]) == CONST_INT
3253 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3254 && (DATA_REG_P (operands[0])
3255 || offsettable_memref_p (operands[0]))
3256 && !TARGET_5200)
3257 {
3258 if (GET_CODE (operands[0]) != REG)
3259 operands[0] = adj_offsettable_operand (operands[0], 2);
3260 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
3261 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3262 CC_STATUS_INIT;
3263 if (operands[2] == const0_rtx)
3264 return "clr%.w %0";
3265 return "and%.w %2,%0";
3266 }
3267 if (GET_CODE (operands[2]) == CONST_INT
3268 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3269 && (DATA_REG_P (operands[0])
3270 || offsettable_memref_p (operands[0])))
3271 {
3272 if (DATA_REG_P (operands[0]))
3273 {
3274 operands[1] = GEN_INT (logval);
3275 }
3276 else
3277 {
3278 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3279 operands[1] = GEN_INT (logval % 8);
3280 }
3281 /* This does not set condition codes in a standard way. */
3282 CC_STATUS_INIT;
3283 return "bclr %1,%0";
3284 }
3285 return "and%.l %2,%0";
3286 }
3287
3288 char *
3289 output_iorsi3 (operands)
3290 rtx *operands;
3291 {
3292 register int logval;
3293 if (GET_CODE (operands[2]) == CONST_INT
3294 && INTVAL (operands[2]) >> 16 == 0
3295 && (DATA_REG_P (operands[0])
3296 || offsettable_memref_p (operands[0]))
3297 && !TARGET_5200)
3298 {
3299 if (GET_CODE (operands[0]) != REG)
3300 operands[0] = adj_offsettable_operand (operands[0], 2);
3301 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3302 CC_STATUS_INIT;
3303 if (INTVAL (operands[2]) == 0xffff)
3304 return "mov%.w %2,%0";
3305 return "or%.w %2,%0";
3306 }
3307 if (GET_CODE (operands[2]) == CONST_INT
3308 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3309 && (DATA_REG_P (operands[0])
3310 || offsettable_memref_p (operands[0])))
3311 {
3312 if (DATA_REG_P (operands[0]))
3313 {
3314 operands[1] = GEN_INT (logval);
3315 }
3316 else
3317 {
3318 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3319 operands[1] = GEN_INT (logval % 8);
3320 }
3321 CC_STATUS_INIT;
3322 return "bset %1,%0";
3323 }
3324 return "or%.l %2,%0";
3325 }
3326
3327 char *
3328 output_xorsi3 (operands)
3329 rtx *operands;
3330 {
3331 register int logval;
3332 if (GET_CODE (operands[2]) == CONST_INT
3333 && INTVAL (operands[2]) >> 16 == 0
3334 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
3335 && !TARGET_5200)
3336 {
3337 if (! DATA_REG_P (operands[0]))
3338 operands[0] = adj_offsettable_operand (operands[0], 2);
3339 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3340 CC_STATUS_INIT;
3341 if (INTVAL (operands[2]) == 0xffff)
3342 return "not%.w %0";
3343 return "eor%.w %2,%0";
3344 }
3345 if (GET_CODE (operands[2]) == CONST_INT
3346 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3347 && (DATA_REG_P (operands[0])
3348 || offsettable_memref_p (operands[0])))
3349 {
3350 if (DATA_REG_P (operands[0]))
3351 {
3352 operands[1] = GEN_INT (logval);
3353 }
3354 else
3355 {
3356 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3357 operands[1] = GEN_INT (logval % 8);
3358 }
3359 CC_STATUS_INIT;
3360 return "bchg %1,%0";
3361 }
3362 return "eor%.l %2,%0";
3363 }