1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 /* Needed for use_return_insn. */
44 #ifdef SUPPORT_SUN_FPA
46 /* Index into this array by (register number >> 3) to find the
47 smallest class which contains that register. */
48 enum reg_class regno_reg_class
[]
49 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
50 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
52 #endif /* defined SUPPORT_SUN_FPA */
54 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
55 if SGS_SWITCH_TABLE. */
56 int switch_table_difference_label_flag
;
58 static rtx
find_addr_reg ();
59 rtx
legitimize_pic_address ();
62 /* Alignment to use for loops and jumps */
63 /* Specify power of two alignment used for loops. */
64 char *m68k_align_loops_string
;
65 /* Specify power of two alignment used for non-loop jumps. */
66 char *m68k_align_jumps_string
;
67 /* Specify power of two alignment used for functions. */
68 char *m68k_align_funcs_string
;
70 /* Specify power of two alignment used for loops. */
72 /* Specify power of two alignment used for non-loop jumps. */
74 /* Specify power of two alignment used for functions. */
77 /* Nonzero if the last compare/test insn had FP operands. The
78 sCC expanders peek at this to determine what to do for the
79 68060, which has no fsCC instructions. */
80 int m68k_last_compare_had_fp_operands
;
82 /* Sometimes certain combinations of command options do not make
83 sense on a particular target machine. You can define a macro
84 `OVERRIDE_OPTIONS' to take account of this. This macro, if
85 defined, is executed once just after all the command options have
88 Don't use this macro to turn on various extra optimizations for
89 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
98 /* Validate -malign-loops= value, or provide default */
99 if (m68k_align_loops_string
)
101 m68k_align_loops
= atoi (m68k_align_loops_string
);
102 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
103 fatal ("-malign-loops=%d is not between 1 and %d",
104 m68k_align_loops
, MAX_CODE_ALIGN
);
107 m68k_align_loops
= def_align
;
109 /* Validate -malign-jumps= value, or provide default */
110 if (m68k_align_jumps_string
)
112 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
113 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
114 fatal ("-malign-jumps=%d is not between 1 and %d",
115 m68k_align_jumps
, MAX_CODE_ALIGN
);
118 m68k_align_jumps
= def_align
;
120 /* Validate -malign-functions= value, or provide default */
121 if (m68k_align_funcs_string
)
123 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
124 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
125 fatal ("-malign-functions=%d is not between 1 and %d",
126 m68k_align_funcs
, MAX_CODE_ALIGN
);
129 m68k_align_funcs
= def_align
;
132 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
133 function at any time during the compilation process. In the future
134 we should try and eliminate the USE if we can easily determine that
135 all PIC references were deleted from the current function. That would
136 save an address register */
141 if (flag_pic
&& current_function_uses_pic_offset_table
)
143 rtx insn
= gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
);
144 emit_insn_after (insn
, get_insns ());
150 /* This function generates the assembly code for function entry.
151 STREAM is a stdio stream to output the code to.
152 SIZE is an int: how many units of temporary storage to allocate.
153 Refer to the array `regs_ever_live' to determine which registers
154 to save; `regs_ever_live[I]' is nonzero if register number I
155 is ever used in the function. This function is responsible for
156 knowing which registers should not be saved even if used. */
159 /* Note that the order of the bit mask for fmovem is the opposite
160 of the order for movem! */
164 output_function_prologue (stream
, size
)
169 register int mask
= 0;
170 int num_saved_regs
= 0;
171 extern char call_used_regs
[];
172 int fsize
= (size
+ 3) & -4;
173 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
176 if (frame_pointer_needed
)
178 if (fsize
== 0 && TARGET_68040
)
180 /* on the 68040, pea + move is faster than link.w 0 */
182 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
183 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
184 reg_names
[FRAME_POINTER_REGNUM
]);
186 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
187 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
188 reg_names
[FRAME_POINTER_REGNUM
]);
191 else if (fsize
< 0x8000)
194 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
195 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
197 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
198 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
201 else if (TARGET_68020
)
204 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
205 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
207 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
208 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
213 /* Adding negative number is faster on the 68040. */
215 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
216 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
218 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
219 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
222 if (dwarf2out_do_frame ())
225 l
= (char *) dwarf2out_cfi_label ();
226 cfa_store_offset
+= 4;
227 cfa_offset
= cfa_store_offset
;
228 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
229 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
230 cfa_store_offset
+= fsize
;
235 if (fsize
+ 4 < 0x8000)
242 /* asm_fprintf() cannot handle %. */
244 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
246 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
251 /* asm_fprintf() cannot handle %. */
253 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
255 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
259 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
261 /* On the CPU32 it is faster to use two subqw instructions to
262 subtract a small integer (8 < N <= 16) to a register. */
263 /* asm_fprintf() cannot handle %. */
265 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
268 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
273 #endif /* NO_ADDSUB_Q */
276 /* Adding negative number is faster on the 68040. */
277 /* asm_fprintf() cannot handle %. */
279 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
281 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
287 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
289 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
295 /* asm_fprintf() cannot handle %. */
297 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
299 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
302 if (dwarf2out_do_frame ())
304 cfa_store_offset
+= fsize
;
305 cfa_offset
= cfa_store_offset
;
306 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
309 #ifdef SUPPORT_SUN_FPA
310 for (regno
= 24; regno
< 56; regno
++)
311 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
314 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
317 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
320 if (dwarf2out_do_frame ())
322 char *l
= dwarf2out_cfi_label ();
324 cfa_store_offset
+= 8;
325 if (! frame_pointer_needed
)
327 cfa_offset
= cfa_store_offset
;
328 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
330 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
336 for (regno
= 16; regno
< 24; regno
++)
337 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
339 mask
|= 1 << (regno
- 16);
342 if ((mask
& 0xff) != 0)
345 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
347 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
349 if (dwarf2out_do_frame ())
351 char *l
= (char *) dwarf2out_cfi_label ();
354 cfa_store_offset
+= num_saved_regs
* 12;
355 if (! frame_pointer_needed
)
357 cfa_offset
= cfa_store_offset
;
358 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
360 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
361 if (mask
& (1 << (regno
- 16)))
362 dwarf2out_reg_save (l
, regno
,
363 -cfa_store_offset
+ n_regs
++ * 12);
369 for (regno
= 0; regno
< 16; regno
++)
370 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
372 mask
|= 1 << (15 - regno
);
375 if (frame_pointer_needed
)
377 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
384 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
386 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
389 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
393 if (num_saved_regs
<= 2)
395 /* Store each separately in the same order moveml uses.
396 Using two movel instructions instead of a single moveml
397 is about 15% faster for the 68020 and 68030 at no expense
402 /* Undo the work from above. */
403 for (i
= 0; i
< 16; i
++)
408 "\t%Omove.l %s,-(%Rsp)\n",
410 "\tmovel %s,%Rsp@-\n",
413 if (dwarf2out_do_frame ())
415 char *l
= (char *) dwarf2out_cfi_label ();
417 cfa_store_offset
+= 4;
418 if (! frame_pointer_needed
)
420 cfa_offset
= cfa_store_offset
;
421 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
423 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
431 /* The coldfire does not support the predecrement form of the
432 movml instruction, so we must adjust the stack pointer and
433 then use the plain address register indirect mode. We also
434 have to invert the register save mask to use the new mode.
436 FIXME: if num_saved_regs was calculated earlier, we could
437 combine the stack pointer adjustment with any adjustment
438 done when the initial stack frame is created. This would
439 save an instruction */
444 for (i
= 0; i
< 16; i
++)
446 newmask
|= (1 << (15-i
));
449 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
450 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
452 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
453 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
459 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
461 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
464 if (dwarf2out_do_frame ())
466 char *l
= (char *) dwarf2out_cfi_label ();
469 cfa_store_offset
+= num_saved_regs
* 4;
470 if (! frame_pointer_needed
)
472 cfa_offset
= cfa_store_offset
;
473 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
475 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
476 if (mask
& (1 << (15 - regno
)))
477 dwarf2out_reg_save (l
, regno
,
478 -cfa_store_offset
+ n_regs
++ * 4);
481 if (flag_pic
&& current_function_uses_pic_offset_table
)
484 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
485 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
487 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
488 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
489 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
490 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
491 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
496 /* Return true if this function's epilogue can be output as RTL. */
503 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
506 /* Copied from output_function_epilogue (). We should probably create a
507 separate layout routine to perform the common work. */
509 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
510 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
516 /* This function generates the assembly code for function exit,
517 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
519 The function epilogue should not depend on the current stack pointer!
520 It should use the frame pointer only, if there is a frame pointer.
521 This is mandatory because of alloca; we also take advantage of it to
522 omit stack adjustments before returning. */
525 output_function_epilogue (stream
, size
)
530 register int mask
, fmask
;
532 int offset
, foffset
, fpoffset
;
533 extern char call_used_regs
[];
534 int fsize
= (size
+ 3) & -4;
536 rtx insn
= get_last_insn ();
537 int restore_from_sp
= 0;
539 /* If the last insn was a BARRIER, we don't have to write any code. */
540 if (GET_CODE (insn
) == NOTE
)
541 insn
= prev_nonnote_insn (insn
);
542 if (insn
&& GET_CODE (insn
) == BARRIER
)
544 /* Output just a no-op so that debuggers don't get confused
545 about which function the pc is in at this address. */
546 asm_fprintf (stream
, "\tnop\n");
550 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
551 if (profile_block_flag
== 2)
553 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
557 #ifdef FUNCTION_EXTRA_EPILOGUE
558 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
560 nregs
= 0; fmask
= 0; fpoffset
= 0;
561 #ifdef SUPPORT_SUN_FPA
562 for (regno
= 24 ; regno
< 56 ; regno
++)
563 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
565 fpoffset
= nregs
* 8;
570 for (regno
= 16; regno
< 24; regno
++)
571 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
574 fmask
|= 1 << (23 - regno
);
577 foffset
= fpoffset
+ nregs
* 12;
579 if (frame_pointer_needed
)
580 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
581 for (regno
= 0; regno
< 16; regno
++)
582 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
587 offset
= foffset
+ nregs
* 4;
588 /* FIXME : leaf_function_p below is too strong.
589 What we really need to know there is if there could be pending
590 stack adjustment needed at that point. */
591 restore_from_sp
= ! frame_pointer_needed
592 || (! current_function_calls_alloca
&& leaf_function_p ());
593 if (offset
+ fsize
>= 0x8000
595 && (mask
|| fmask
|| fpoffset
))
598 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
600 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
604 if (TARGET_5200
|| nregs
<= 2)
606 /* Restore each separately in the same order moveml does.
607 Using two movel instructions instead of a single moveml
608 is about 15% faster for the 68020 and 68030 at no expense
613 /* Undo the work from above. */
614 for (i
= 0; i
< 16; i
++)
620 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
622 reg_names
[FRAME_POINTER_REGNUM
],
625 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
626 reg_names
[FRAME_POINTER_REGNUM
],
627 offset
+ fsize
, reg_names
[i
]);
630 else if (restore_from_sp
)
633 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
636 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
643 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
645 reg_names
[FRAME_POINTER_REGNUM
],
648 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
649 reg_names
[FRAME_POINTER_REGNUM
],
650 offset
+ fsize
, reg_names
[i
]);
661 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
663 reg_names
[FRAME_POINTER_REGNUM
],
666 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
667 reg_names
[FRAME_POINTER_REGNUM
],
668 offset
+ fsize
, mask
);
671 else if (restore_from_sp
)
674 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
676 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
682 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
684 reg_names
[FRAME_POINTER_REGNUM
],
687 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
688 reg_names
[FRAME_POINTER_REGNUM
],
689 offset
+ fsize
, mask
);
698 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
700 reg_names
[FRAME_POINTER_REGNUM
],
703 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
704 reg_names
[FRAME_POINTER_REGNUM
],
705 foffset
+ fsize
, fmask
);
708 else if (restore_from_sp
)
711 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
713 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
719 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
721 reg_names
[FRAME_POINTER_REGNUM
],
724 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
725 reg_names
[FRAME_POINTER_REGNUM
],
726 foffset
+ fsize
, fmask
);
731 for (regno
= 55; regno
>= 24; regno
--)
732 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
737 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
739 reg_names
[FRAME_POINTER_REGNUM
],
742 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
743 reg_names
[FRAME_POINTER_REGNUM
],
744 fpoffset
+ fsize
, reg_names
[regno
]);
747 else if (restore_from_sp
)
750 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
753 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
760 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
762 reg_names
[FRAME_POINTER_REGNUM
],
765 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
766 reg_names
[FRAME_POINTER_REGNUM
],
767 fpoffset
+ fsize
, reg_names
[regno
]);
772 if (frame_pointer_needed
)
773 fprintf (stream
, "\tunlk %s\n",
774 reg_names
[FRAME_POINTER_REGNUM
]);
783 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
785 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
791 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
793 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
797 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
799 /* On the CPU32 it is faster to use two addqw instructions to
800 add a small integer (8 < N <= 16) to a register. */
801 /* asm_fprintf() cannot handle %. */
803 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
806 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
811 #endif /* NO_ADDSUB_Q */
812 if (fsize
+ 4 < 0x8000)
816 /* asm_fprintf() cannot handle %. */
818 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
820 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
826 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
828 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
834 /* asm_fprintf() cannot handle %. */
836 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
838 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
842 if (current_function_pops_args
)
843 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
845 fprintf (stream
, "\trts\n");
848 /* Similar to general_operand, but exclude stack_pointer_rtx. */
851 not_sp_operand (op
, mode
)
853 enum machine_mode mode
;
855 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
858 /* Return TRUE if X is a valid comparison operator for the dbcc
861 Note it rejects floating point comparison operators.
862 (In the future we could use Fdbcc).
864 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
867 valid_dbcc_comparison_p (x
, mode
)
869 enum machine_mode mode
;
871 switch (GET_CODE (x
))
873 case EQ
: case NE
: case GTU
: case LTU
:
877 /* Reject some when CC_NO_OVERFLOW is set. This may be over
879 case GT
: case LT
: case GE
: case LE
:
880 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
886 /* Return non-zero if flags are currently in the 68881 flag register. */
890 /* We could add support for these in the future */
891 return cc_status
.flags
& CC_IN_68881
;
894 /* Output a dbCC; jCC sequence. Note we do not handle the
895 floating point version of this sequence (Fdbcc). We also
896 do not handle alternative conditions when CC_NO_OVERFLOW is
897 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
898 kick those out before we get here. */
901 output_dbcc_and_branch (operands
)
904 switch (GET_CODE (operands
[3]))
908 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
910 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
916 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
918 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
924 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
926 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
932 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
934 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
940 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
942 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
948 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
950 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
956 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
958 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
964 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
966 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
972 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
974 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
980 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
982 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
990 /* If the decrement is to be done in SImode, then we have
991 to compensate for the fact that dbcc decrements in HImode. */
992 switch (GET_MODE (operands
[0]))
996 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
998 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1011 output_scc_di(op
, operand1
, operand2
, dest
)
1018 enum rtx_code op_code
= GET_CODE (op
);
1020 /* This does not produce a usefull cc. */
1023 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1024 below. Swap the operands and change the op if these requirements
1025 are not fulfilled. */
1026 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1030 operand1
= operand2
;
1032 op_code
= swap_condition (op_code
);
1034 loperands
[0] = operand1
;
1035 if (GET_CODE (operand1
) == REG
)
1036 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1038 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1039 if (operand2
!= const0_rtx
)
1041 loperands
[2] = operand2
;
1042 if (GET_CODE (operand2
) == REG
)
1043 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1045 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1047 loperands
[4] = gen_label_rtx();
1048 if (operand2
!= const0_rtx
)
1050 #ifdef SGS_CMP_ORDER
1051 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1053 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1056 #ifdef SGS_CMP_ORDER
1057 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1059 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1064 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
1066 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
1068 loperands
[5] = dest
;
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1074 CODE_LABEL_NUMBER (loperands
[4]));
1075 output_asm_insn ("seq %5", loperands
);
1079 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1080 CODE_LABEL_NUMBER (loperands
[4]));
1081 output_asm_insn ("sne %5", loperands
);
1085 loperands
[6] = gen_label_rtx();
1087 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1089 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1091 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1092 CODE_LABEL_NUMBER (loperands
[4]));
1093 output_asm_insn ("sgt %5", loperands
);
1094 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1095 CODE_LABEL_NUMBER (loperands
[6]));
1099 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1100 CODE_LABEL_NUMBER (loperands
[4]));
1101 output_asm_insn ("shi %5", loperands
);
1105 loperands
[6] = gen_label_rtx();
1107 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1109 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1111 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1112 CODE_LABEL_NUMBER (loperands
[4]));
1113 output_asm_insn ("slt %5", loperands
);
1114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1115 CODE_LABEL_NUMBER (loperands
[6]));
1119 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1120 CODE_LABEL_NUMBER (loperands
[4]));
1121 output_asm_insn ("scs %5", loperands
);
1125 loperands
[6] = gen_label_rtx();
1127 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1129 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1131 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1132 CODE_LABEL_NUMBER (loperands
[4]));
1133 output_asm_insn ("sge %5", loperands
);
1134 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1135 CODE_LABEL_NUMBER (loperands
[6]));
1139 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1140 CODE_LABEL_NUMBER (loperands
[4]));
1141 output_asm_insn ("scc %5", loperands
);
1145 loperands
[6] = gen_label_rtx();
1147 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1149 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1151 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1152 CODE_LABEL_NUMBER (loperands
[4]));
1153 output_asm_insn ("sle %5", loperands
);
1154 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1155 CODE_LABEL_NUMBER (loperands
[6]));
1159 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1160 CODE_LABEL_NUMBER (loperands
[4]));
1161 output_asm_insn ("sls %5", loperands
);
1171 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1173 rtx countop
, dataop
;
1177 operands
[0] = countop
;
1178 operands
[1] = dataop
;
1180 if (GET_CODE (countop
) == CONST_INT
)
1182 register int count
= INTVAL (countop
);
1183 /* If COUNT is bigger than size of storage unit in use,
1184 advance to the containing unit of same size. */
1185 if (count
> signpos
)
1187 int offset
= (count
& ~signpos
) / 8;
1188 count
= count
& signpos
;
1189 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1191 if (count
== signpos
)
1192 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1194 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1196 /* These three statements used to use next_insns_test_no...
1197 but it appears that this should do the same job. */
1199 && next_insn_tests_no_inequality (insn
))
1202 && next_insn_tests_no_inequality (insn
))
1205 && next_insn_tests_no_inequality (insn
))
1208 cc_status
.flags
= CC_NOT_NEGATIVE
;
1210 return "btst %0,%1";
1213 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1214 reference and a constant. */
1217 symbolic_operand (op
, mode
)
1219 enum machine_mode mode
;
1221 switch (GET_CODE (op
))
1229 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1230 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1231 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1233 #if 0 /* Deleted, with corresponding change in m68k.h,
1234 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1236 return GET_MODE (op
) == mode
;
1244 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1247 extend_operator(x
, mode
)
1249 enum machine_mode mode
;
1251 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1253 switch (GET_CODE(x
))
1264 /* Legitimize PIC addresses. If the address is already
1265 position-independent, we return ORIG. Newly generated
1266 position-independent addresses go to REG. If we need more
1267 than one register, we lose.
1269 An address is legitimized by making an indirect reference
1270 through the Global Offset Table with the name of the symbol
1273 The assembler and linker are responsible for placing the
1274 address of the symbol in the GOT. The function prologue
1275 is responsible for initializing a5 to the starting address
1278 The assembler is also responsible for translating a symbol name
1279 into a constant displacement from the start of the GOT.
1281 A quick example may make things a little clearer:
1283 When not generating PIC code to store the value 12345 into _foo
1284 we would generate the following code:
1288 When generating PIC two transformations are made. First, the compiler
1289 loads the address of foo into a register. So the first transformation makes:
1294 The code in movsi will intercept the lea instruction and call this
1295 routine which will transform the instructions into:
1297 movel a5@(_foo:w), a0
1301 That (in a nutshell) is how *all* symbol and label references are
1305 legitimize_pic_address (orig
, mode
, reg
)
1307 enum machine_mode mode
;
1311 /* First handle a simple SYMBOL_REF or LABEL_REF */
1312 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1317 pic_ref
= gen_rtx_MEM (Pmode
,
1318 gen_rtx_PLUS (Pmode
,
1319 pic_offset_table_rtx
, orig
));
1320 current_function_uses_pic_offset_table
= 1;
1321 if (reload_in_progress
)
1322 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1323 RTX_UNCHANGING_P (pic_ref
) = 1;
1324 emit_move_insn (reg
, pic_ref
);
1327 else if (GET_CODE (orig
) == CONST
)
1331 /* Make sure this is CONST has not already been legitimized */
1332 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1333 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1339 /* legitimize both operands of the PLUS */
1340 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1342 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1343 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1344 base
== reg
? 0 : reg
);
1348 if (GET_CODE (orig
) == CONST_INT
)
1349 return plus_constant_for_output (base
, INTVAL (orig
));
1350 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1351 /* Likewise, should we set special REG_NOTEs here? */
1357 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1359 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1362 const_method (constant
)
1368 i
= INTVAL (constant
);
1372 /* The Coldfire doesn't have byte or word operations. */
1373 /* FIXME: This may not be useful for the m68060 either */
1376 /* if -256 < N < 256 but N is not in range for a moveq
1377 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1378 if (USE_MOVQ (i
^ 0xff))
1380 /* Likewise, try with not.w */
1381 if (USE_MOVQ (i
^ 0xffff))
1383 /* This is the only value where neg.w is useful */
1386 /* Try also with swap */
1388 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1391 /* Otherwise, use move.l */
1396 const_int_cost (constant
)
1399 switch (const_method (constant
))
1402 /* Constants between -128 and 127 are cheap due to moveq */
1408 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1418 output_move_const_into_data_reg (operands
)
1423 i
= INTVAL (operands
[1]);
1424 switch (const_method (operands
[1]))
1427 #if defined (MOTOROLA) && !defined (CRDS)
1428 return "moveq%.l %1,%0";
1430 return "moveq %1,%0";
1433 operands
[1] = GEN_INT (i
^ 0xff);
1434 #if defined (MOTOROLA) && !defined (CRDS)
1435 return "moveq%.l %1,%0\n\tnot%.b %0";
1437 return "moveq %1,%0\n\tnot%.b %0";
1440 operands
[1] = GEN_INT (i
^ 0xffff);
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %1,%0\n\tnot%.w %0";
1444 return "moveq %1,%0\n\tnot%.w %0";
1447 #if defined (MOTOROLA) && !defined (CRDS)
1448 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1450 return "moveq %#-128,%0\n\tneg%.w %0";
1456 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1457 #if defined (MOTOROLA) && !defined (CRDS)
1458 return "moveq%.l %1,%0\n\tswap %0";
1460 return "moveq %1,%0\n\tswap %0";
1464 return "move%.l %1,%0";
1471 output_move_simode_const (operands
)
1474 if (operands
[1] == const0_rtx
1475 && (DATA_REG_P (operands
[0])
1476 || GET_CODE (operands
[0]) == MEM
)
1477 /* clr insns on 68000 read before writing.
1478 This isn't so on the 68010, but we have no TARGET_68010. */
1479 && ((TARGET_68020
|| TARGET_5200
)
1480 || !(GET_CODE (operands
[0]) == MEM
1481 && MEM_VOLATILE_P (operands
[0]))))
1483 else if (DATA_REG_P (operands
[0]))
1484 return output_move_const_into_data_reg (operands
);
1485 else if (ADDRESS_REG_P (operands
[0])
1486 && INTVAL (operands
[1]) < 0x8000
1487 && INTVAL (operands
[1]) >= -0x8000)
1488 return "move%.w %1,%0";
1489 else if (GET_CODE (operands
[0]) == MEM
1490 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1491 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1492 && INTVAL (operands
[1]) < 0x8000
1493 && INTVAL (operands
[1]) >= -0x8000)
1495 return "move%.l %1,%0";
1499 output_move_simode (operands
)
1502 if (GET_CODE (operands
[1]) == CONST_INT
)
1503 return output_move_simode_const (operands
);
1504 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1505 || GET_CODE (operands
[1]) == CONST
)
1506 && push_operand (operands
[0], SImode
))
1508 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1509 || GET_CODE (operands
[1]) == CONST
)
1510 && ADDRESS_REG_P (operands
[0]))
1511 return "lea %a1,%0";
1512 return "move%.l %1,%0";
1516 output_move_himode (operands
)
1519 if (GET_CODE (operands
[1]) == CONST_INT
)
1521 if (operands
[1] == const0_rtx
1522 && (DATA_REG_P (operands
[0])
1523 || GET_CODE (operands
[0]) == MEM
)
1524 /* clr insns on 68000 read before writing.
1525 This isn't so on the 68010, but we have no TARGET_68010. */
1526 && ((TARGET_68020
|| TARGET_5200
)
1527 || !(GET_CODE (operands
[0]) == MEM
1528 && MEM_VOLATILE_P (operands
[0]))))
1530 else if (DATA_REG_P (operands
[0])
1531 && INTVAL (operands
[1]) < 128
1532 && INTVAL (operands
[1]) >= -128)
1534 #if defined(MOTOROLA) && !defined(CRDS)
1535 return "moveq%.l %1,%0";
1537 return "moveq %1,%0";
1540 else if (INTVAL (operands
[1]) < 0x8000
1541 && INTVAL (operands
[1]) >= -0x8000)
1542 return "move%.w %1,%0";
1544 else if (CONSTANT_P (operands
[1]))
1545 return "move%.l %1,%0";
1547 /* Recognize the insn before a tablejump, one that refers
1548 to a table of offsets. Such an insn will need to refer
1549 to a label on the insn. So output one. Use the label-number
1550 of the table of offsets to generate this label. This code,
1551 and similar code below, assumes that there will be at most one
1552 reference to each table. */
1553 if (GET_CODE (operands
[1]) == MEM
1554 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1555 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1556 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1558 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1559 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1561 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1562 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1564 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1565 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1566 #endif /* not SGS */
1567 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1568 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1569 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1570 #ifdef SGS_SWITCH_TABLES
1571 /* Set flag saying we need to define the symbol
1572 LD%n (with value L%n-LI%n) at the end of the switch table. */
1573 switch_table_difference_label_flag
= 1;
1574 #endif /* SGS_SWITCH_TABLES */
1575 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1577 #endif /* SGS_NO_LI */
1578 return "move%.w %1,%0";
1582 output_move_qimode (operands
)
1587 /* This is probably useless, since it loses for pushing a struct
1588 of several bytes a byte at a time. */
1589 /* 68k family always modifies the stack pointer by at least 2, even for
1590 byte pushes. The 5200 (coldfire) does not do this. */
1591 if (GET_CODE (operands
[0]) == MEM
1592 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1593 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1594 && ! ADDRESS_REG_P (operands
[1])
1597 xoperands
[1] = operands
[1];
1599 = gen_rtx_MEM (QImode
,
1600 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1601 /* Just pushing a byte puts it in the high byte of the halfword. */
1602 /* We must put it in the low-order, high-numbered byte. */
1603 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1605 xoperands
[3] = stack_pointer_rtx
;
1607 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1609 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1613 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1617 /* clr and st insns on 68000 read before writing.
1618 This isn't so on the 68010, but we have no TARGET_68010. */
1619 if (!ADDRESS_REG_P (operands
[0])
1620 && ((TARGET_68020
|| TARGET_5200
)
1621 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1623 if (operands
[1] == const0_rtx
)
1625 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1626 && GET_CODE (operands
[1]) == CONST_INT
1627 && (INTVAL (operands
[1]) & 255) == 255)
1633 if (GET_CODE (operands
[1]) == CONST_INT
1634 && DATA_REG_P (operands
[0])
1635 && INTVAL (operands
[1]) < 128
1636 && INTVAL (operands
[1]) >= -128)
1638 #if defined(MOTOROLA) && !defined(CRDS)
1639 return "moveq%.l %1,%0";
1641 return "moveq %1,%0";
1644 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1645 return "move%.l %1,%0";
1646 /* 68k family doesn't support byte moves to from address registers. The
1647 5200 (coldfire) does not have this restriction. */
1648 if ((ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1650 return "move%.w %1,%0";
1651 return "move%.b %1,%0";
1655 output_move_stricthi (operands
)
1658 if (operands
[1] == const0_rtx
1659 /* clr insns on 68000 read before writing.
1660 This isn't so on the 68010, but we have no TARGET_68010. */
1661 && ((TARGET_68020
|| TARGET_5200
)
1662 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1664 return "move%.w %1,%0";
1668 output_move_strictqi (operands
)
1671 if (operands
[1] == const0_rtx
1672 /* clr insns on 68000 read before writing.
1673 This isn't so on the 68010, but we have no TARGET_68010. */
1674 && ((TARGET_68020
|| TARGET_5200
)
1675 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1677 return "move%.b %1,%0";
1680 /* Return the best assembler insn template
1681 for moving operands[1] into operands[0] as a fullword. */
1684 singlemove_string (operands
)
1687 #ifdef SUPPORT_SUN_FPA
1688 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1689 return "fpmoves %1,%0";
1691 if (GET_CODE (operands
[1]) == CONST_INT
)
1692 return output_move_simode_const (operands
);
1693 return "move%.l %1,%0";
1697 /* Output assembler code to perform a doubleword move insn
1698 with operands OPERANDS. */
1701 output_move_double (operands
)
1706 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1711 rtx addreg0
= 0, addreg1
= 0;
1712 int dest_overlapped_low
= 0;
1713 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1718 /* First classify both operands. */
1720 if (REG_P (operands
[0]))
1722 else if (offsettable_memref_p (operands
[0]))
1724 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1726 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1728 else if (GET_CODE (operands
[0]) == MEM
)
1733 if (REG_P (operands
[1]))
1735 else if (CONSTANT_P (operands
[1]))
1737 else if (offsettable_memref_p (operands
[1]))
1739 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1741 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1743 else if (GET_CODE (operands
[1]) == MEM
)
1748 /* Check for the cases that the operand constraints are not
1749 supposed to allow to happen. Abort if we get one,
1750 because generating code for these cases is painful. */
1752 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1755 /* If one operand is decrementing and one is incrementing
1756 decrement the former register explicitly
1757 and change that operand into ordinary indexing. */
1759 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1761 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1763 output_asm_insn ("sub%.l %#12,%0", operands
);
1765 output_asm_insn ("subq%.l %#8,%0", operands
);
1766 if (GET_MODE (operands
[1]) == XFmode
)
1767 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1768 else if (GET_MODE (operands
[0]) == DFmode
)
1769 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1771 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1774 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1776 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1778 output_asm_insn ("sub%.l %#12,%1", operands
);
1780 output_asm_insn ("subq%.l %#8,%1", operands
);
1781 if (GET_MODE (operands
[1]) == XFmode
)
1782 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1783 else if (GET_MODE (operands
[1]) == DFmode
)
1784 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1786 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1790 /* If an operand is an unoffsettable memory ref, find a register
1791 we can increment temporarily to make it refer to the second word. */
1793 if (optype0
== MEMOP
)
1794 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1796 if (optype1
== MEMOP
)
1797 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1799 /* Ok, we can do one word at a time.
1800 Normally we do the low-numbered word first,
1801 but if either operand is autodecrementing then we
1802 do the high-numbered word first.
1804 In either case, set up in LATEHALF the operands to use
1805 for the high-numbered word and in some cases alter the
1806 operands in OPERANDS to be suitable for the low-numbered word. */
1810 if (optype0
== REGOP
)
1812 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1813 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1815 else if (optype0
== OFFSOP
)
1817 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1818 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1822 middlehalf
[0] = operands
[0];
1823 latehalf
[0] = operands
[0];
1826 if (optype1
== REGOP
)
1828 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1829 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1831 else if (optype1
== OFFSOP
)
1833 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1834 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1836 else if (optype1
== CNSTOP
)
1838 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1843 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1844 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1845 operands
[1] = GEN_INT (l
[0]);
1846 middlehalf
[1] = GEN_INT (l
[1]);
1847 latehalf
[1] = GEN_INT (l
[2]);
1849 else if (CONSTANT_P (operands
[1]))
1851 /* actually, no non-CONST_DOUBLE constant should ever
1854 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1855 latehalf
[1] = constm1_rtx
;
1857 latehalf
[1] = const0_rtx
;
1862 middlehalf
[1] = operands
[1];
1863 latehalf
[1] = operands
[1];
1867 /* size is not 12: */
1869 if (optype0
== REGOP
)
1870 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1871 else if (optype0
== OFFSOP
)
1872 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1874 latehalf
[0] = operands
[0];
1876 if (optype1
== REGOP
)
1877 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1878 else if (optype1
== OFFSOP
)
1879 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1880 else if (optype1
== CNSTOP
)
1881 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1883 latehalf
[1] = operands
[1];
1886 /* If insn is effectively movd N(sp),-(sp) then we will do the
1887 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1888 for the low word as well, to compensate for the first decrement of sp. */
1889 if (optype0
== PUSHOP
1890 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1891 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1892 operands
[1] = middlehalf
[1] = latehalf
[1];
1894 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1895 if the upper part of reg N does not appear in the MEM, arrange to
1896 emit the move late-half first. Otherwise, compute the MEM address
1897 into the upper part of N and use that as a pointer to the memory
1899 if (optype0
== REGOP
1900 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1902 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1904 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1905 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1907 /* If both halves of dest are used in the src memory address,
1908 compute the address into latehalf of dest.
1909 Note that this can't happen if the dest is two data regs. */
1911 xops
[0] = latehalf
[0];
1912 xops
[1] = XEXP (operands
[1], 0);
1913 output_asm_insn ("lea %a1,%0", xops
);
1914 if( GET_MODE (operands
[1]) == XFmode
)
1916 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1917 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1918 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1922 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1923 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1927 && reg_overlap_mentioned_p (middlehalf
[0],
1928 XEXP (operands
[1], 0)))
1930 /* Check for two regs used by both source and dest.
1931 Note that this can't happen if the dest is all data regs.
1932 It can happen if the dest is d6, d7, a0.
1933 But in that case, latehalf is an addr reg, so
1934 the code at compadr does ok. */
1936 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1937 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1940 /* JRV says this can't happen: */
1941 if (addreg0
|| addreg1
)
1944 /* Only the middle reg conflicts; simply put it last. */
1945 output_asm_insn (singlemove_string (operands
), operands
);
1946 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1947 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1950 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1951 /* If the low half of dest is mentioned in the source memory
1952 address, the arrange to emit the move late half first. */
1953 dest_overlapped_low
= 1;
1956 /* If one or both operands autodecrementing,
1957 do the two words, high-numbered first. */
1959 /* Likewise, the first move would clobber the source of the second one,
1960 do them in the other order. This happens only for registers;
1961 such overlap can't happen in memory unless the user explicitly
1962 sets it up, and that is an undefined circumstance. */
1964 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1965 || (optype0
== REGOP
&& optype1
== REGOP
1966 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1967 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1968 || dest_overlapped_low
)
1970 /* Make any unoffsettable addresses point at high-numbered word. */
1974 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1976 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1981 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1983 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1987 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1989 /* Undo the adds we just did. */
1991 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1993 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1997 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1999 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2001 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2004 /* Do low-numbered word. */
2005 return singlemove_string (operands
);
2008 /* Normal case: do the two words, low-numbered first. */
2010 output_asm_insn (singlemove_string (operands
), operands
);
2012 /* Do the middle one of the three words for long double */
2016 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2018 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2020 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2023 /* Make any unoffsettable addresses point at high-numbered word. */
2025 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2027 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2030 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2032 /* Undo the adds we just did. */
2036 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2038 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2043 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2045 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2051 /* Return a REG that occurs in ADDR with coefficient 1.
2052 ADDR can be effectively incremented by incrementing REG. */
2055 find_addr_reg (addr
)
2058 while (GET_CODE (addr
) == PLUS
)
2060 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2061 addr
= XEXP (addr
, 0);
2062 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2063 addr
= XEXP (addr
, 1);
2064 else if (CONSTANT_P (XEXP (addr
, 0)))
2065 addr
= XEXP (addr
, 1);
2066 else if (CONSTANT_P (XEXP (addr
, 1)))
2067 addr
= XEXP (addr
, 0);
2071 if (GET_CODE (addr
) == REG
)
2076 /* Output assembler code to perform a 32 bit 3 operand add. */
2079 output_addsi3 (operands
)
2082 if (! operands_match_p (operands
[0], operands
[1]))
2084 if (!ADDRESS_REG_P (operands
[1]))
2086 rtx tmp
= operands
[1];
2088 operands
[1] = operands
[2];
2092 /* These insns can result from reloads to access
2093 stack slots over 64k from the frame pointer. */
2094 if (GET_CODE (operands
[2]) == CONST_INT
2095 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2096 return "move%.l %2,%0\n\tadd%.l %1,%0";
2098 if (GET_CODE (operands
[2]) == REG
)
2099 return "lea 0(%1,%2.l),%0";
2101 return "lea %c2(%1),%0";
2104 if (GET_CODE (operands
[2]) == REG
)
2105 return "lea (%1,%2.l),%0";
2107 return "lea (%c2,%1),%0";
2108 #else /* not MOTOROLA (MIT syntax) */
2109 if (GET_CODE (operands
[2]) == REG
)
2110 return "lea %1@(0,%2:l),%0";
2112 return "lea %1@(%c2),%0";
2113 #endif /* not MOTOROLA */
2114 #endif /* not SGS */
2116 if (GET_CODE (operands
[2]) == CONST_INT
)
2119 if (INTVAL (operands
[2]) > 0
2120 && INTVAL (operands
[2]) <= 8)
2121 return "addq%.l %2,%0";
2122 if (INTVAL (operands
[2]) < 0
2123 && INTVAL (operands
[2]) >= -8)
2125 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2126 return "subq%.l %2,%0";
2128 /* On the CPU32 it is faster to use two addql instructions to
2129 add a small integer (8 < N <= 16) to a register.
2130 Likewise for subql. */
2131 if (TARGET_CPU32
&& REG_P (operands
[0]))
2133 if (INTVAL (operands
[2]) > 8
2134 && INTVAL (operands
[2]) <= 16)
2136 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2137 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2139 if (INTVAL (operands
[2]) < -8
2140 && INTVAL (operands
[2]) >= -16)
2142 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2143 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2147 if (ADDRESS_REG_P (operands
[0])
2148 && INTVAL (operands
[2]) >= -0x8000
2149 && INTVAL (operands
[2]) < 0x8000)
2152 return "add%.w %2,%0";
2155 return "lea (%c2,%0),%0";
2157 return "lea %0@(%c2),%0";
2161 return "add%.l %2,%0";
2164 /* Store in cc_status the expressions that the condition codes will
2165 describe after execution of an instruction whose pattern is EXP.
2166 Do not alter them if the instruction would not alter the cc's. */
2168 /* On the 68000, all the insns to store in an address register fail to
2169 set the cc's. However, in some cases these instructions can make it
2170 possibly invalid to use the saved cc's. In those cases we clear out
2171 some or all of the saved cc's so they won't be used. */
2174 notice_update_cc (exp
, insn
)
2178 /* If the cc is being set from the fpa and the expression is not an
2179 explicit floating point test instruction (which has code to deal with
2180 this), reinit the CC. */
2181 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2182 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2183 && !(GET_CODE (exp
) == PARALLEL
2184 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2185 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2189 else if (GET_CODE (exp
) == SET
)
2191 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2195 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2197 if (cc_status
.value1
2198 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
2199 cc_status
.value1
= 0;
2200 if (cc_status
.value2
2201 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
2202 cc_status
.value2
= 0;
2204 else if (!FP_REG_P (SET_DEST (exp
))
2205 && SET_DEST (exp
) != cc0_rtx
2206 && (FP_REG_P (SET_SRC (exp
))
2207 || GET_CODE (SET_SRC (exp
)) == FIX
2208 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2209 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2213 /* A pair of move insns doesn't produce a useful overall cc. */
2214 else if (!FP_REG_P (SET_DEST (exp
))
2215 && !FP_REG_P (SET_SRC (exp
))
2216 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2217 && (GET_CODE (SET_SRC (exp
)) == REG
2218 || GET_CODE (SET_SRC (exp
)) == MEM
2219 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2223 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2227 else if (XEXP (exp
, 0) != pc_rtx
)
2229 cc_status
.flags
= 0;
2230 cc_status
.value1
= XEXP (exp
, 0);
2231 cc_status
.value2
= XEXP (exp
, 1);
2234 else if (GET_CODE (exp
) == PARALLEL
2235 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2237 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2239 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2241 cc_status
.flags
= 0;
2242 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2243 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2248 if (cc_status
.value2
!= 0
2249 && ADDRESS_REG_P (cc_status
.value2
)
2250 && GET_MODE (cc_status
.value2
) == QImode
)
2252 if (cc_status
.value2
!= 0
2253 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2254 switch (GET_CODE (cc_status
.value2
))
2256 case PLUS
: case MINUS
: case MULT
:
2257 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2258 #if 0 /* These instructions always clear the overflow bit */
2259 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2260 case ROTATE
: case ROTATERT
:
2262 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2263 cc_status
.flags
|= CC_NO_OVERFLOW
;
2266 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2267 ends with a move insn moving r2 in r2's mode.
2268 Thus, the cc's are set for r2.
2269 This can set N bit spuriously. */
2270 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2275 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2277 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2278 cc_status
.value2
= 0;
2279 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2280 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2281 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2282 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2283 cc_status
.flags
= CC_IN_68881
;
2287 output_move_const_double (operands
)
2290 #ifdef SUPPORT_SUN_FPA
2291 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2293 int code
= standard_sun_fpa_constant_p (operands
[1]);
2297 static char buf
[40];
2299 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2302 return "fpmove%.d %1,%0";
2307 int code
= standard_68881_constant_p (operands
[1]);
2311 static char buf
[40];
2313 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2316 return "fmove%.d %1,%0";
2321 output_move_const_single (operands
)
2324 #ifdef SUPPORT_SUN_FPA
2327 int code
= standard_sun_fpa_constant_p (operands
[1]);
2331 static char buf
[40];
2333 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2336 return "fpmove%.s %1,%0";
2339 #endif /* defined SUPPORT_SUN_FPA */
2341 int code
= standard_68881_constant_p (operands
[1]);
2345 static char buf
[40];
2347 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2350 return "fmove%.s %f1,%0";
2354 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2355 from the "fmovecr" instruction.
2356 The value, anded with 0xff, gives the code to use in fmovecr
2357 to get the desired constant. */
2359 /* This code has been fixed for cross-compilation. */
2361 static int inited_68881_table
= 0;
2363 char *strings_68881
[7] = {
2373 int codes_68881
[7] = {
2383 REAL_VALUE_TYPE values_68881
[7];
2385 /* Set up values_68881 array by converting the decimal values
2386 strings_68881 to binary. */
2393 enum machine_mode mode
;
2396 for (i
= 0; i
< 7; i
++)
2400 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2401 values_68881
[i
] = r
;
2403 inited_68881_table
= 1;
2407 standard_68881_constant_p (x
)
2413 #ifdef NO_ASM_FMOVECR
2417 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2421 #ifndef REAL_ARITHMETIC
2422 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2423 if (! flag_pretend_float
)
2428 if (! inited_68881_table
)
2429 init_68881_table ();
2431 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2433 for (i
= 0; i
< 6; i
++)
2435 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2436 return (codes_68881
[i
]);
2439 if (GET_MODE (x
) == SFmode
)
2442 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2443 return (codes_68881
[6]);
2445 /* larger powers of ten in the constants ram are not used
2446 because they are not equal to a `double' C constant. */
2450 /* If X is a floating-point constant, return the logarithm of X base 2,
2451 or 0 if X is not a power of 2. */
2454 floating_exact_log2 (x
)
2457 REAL_VALUE_TYPE r
, r1
;
2460 #ifndef REAL_ARITHMETIC
2461 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2462 if (! flag_pretend_float
)
2467 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2469 if (REAL_VALUES_LESS (r
, dconst0
))
2474 while (REAL_VALUES_LESS (r1
, r
))
2476 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2477 if (REAL_VALUES_EQUAL (r1
, r
))
2484 #ifdef SUPPORT_SUN_FPA
2485 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2486 from the Sun FPA's constant RAM.
2487 The value returned, anded with 0x1ff, gives the code to use in fpmove
2488 to get the desired constant. */
2490 static int inited_FPA_table
= 0;
2492 char *strings_FPA
[38] = {
2493 /* small rationals */
2506 /* Decimal equivalents of double precision values */
2507 "2.718281828459045091", /* D_E */
2508 "6.283185307179586477", /* 2 pi */
2509 "3.141592653589793116", /* D_PI */
2510 "1.570796326794896619", /* pi/2 */
2511 "1.414213562373095145", /* D_SQRT2 */
2512 "0.7071067811865475244", /* 1/sqrt(2) */
2513 "-1.570796326794896619", /* -pi/2 */
2514 "1.442695040888963387", /* D_LOG2ofE */
2515 "3.321928024887362182", /* D_LOG2of10 */
2516 "0.6931471805599452862", /* D_LOGEof2 */
2517 "2.302585092994045901", /* D_LOGEof10 */
2518 "0.3010299956639811980", /* D_LOG10of2 */
2519 "0.4342944819032518167", /* D_LOG10ofE */
2520 /* Decimal equivalents of single precision values */
2521 "2.718281745910644531", /* S_E */
2522 "6.283185307179586477", /* 2 pi */
2523 "3.141592741012573242", /* S_PI */
2524 "1.570796326794896619", /* pi/2 */
2525 "1.414213538169860840", /* S_SQRT2 */
2526 "0.7071067811865475244", /* 1/sqrt(2) */
2527 "-1.570796326794896619", /* -pi/2 */
2528 "1.442695021629333496", /* S_LOG2ofE */
2529 "3.321928024291992188", /* S_LOG2of10 */
2530 "0.6931471824645996094", /* S_LOGEof2 */
2531 "2.302585124969482442", /* S_LOGEof10 */
2532 "0.3010300099849700928", /* S_LOG10of2 */
2533 "0.4342944920063018799", /* S_LOG10ofE */
2537 int codes_FPA
[38] = {
2538 /* small rationals */
2551 /* double precision */
2565 /* single precision */
2581 REAL_VALUE_TYPE values_FPA
[38];
2583 /* This code has been fixed for cross-compilation. */
2588 enum machine_mode mode
;
2593 for (i
= 0; i
< 38; i
++)
2597 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2600 inited_FPA_table
= 1;
2605 standard_sun_fpa_constant_p (x
)
2611 #ifndef REAL_ARITHMETIC
2612 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2613 if (! flag_pretend_float
)
2618 if (! inited_FPA_table
)
2621 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2623 for (i
=0; i
<12; i
++)
2625 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2626 return (codes_FPA
[i
]);
2629 if (GET_MODE (x
) == SFmode
)
2631 for (i
=25; i
<38; i
++)
2633 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2634 return (codes_FPA
[i
]);
2639 for (i
=12; i
<25; i
++)
2641 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2642 return (codes_FPA
[i
]);
2647 #endif /* define SUPPORT_SUN_FPA */
2649 /* A C compound statement to output to stdio stream STREAM the
2650 assembler syntax for an instruction operand X. X is an RTL
2653 CODE is a value that can be used to specify one of several ways
2654 of printing the operand. It is used when identical operands
2655 must be printed differently depending on the context. CODE
2656 comes from the `%' specification that was used to request
2657 printing of the operand. If the specification was just `%DIGIT'
2658 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2659 is the ASCII code for LTR.
2661 If X is a register, this macro should print the register's name.
2662 The names can be found in an array `reg_names' whose type is
2663 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2665 When the machine description has a specification `%PUNCT' (a `%'
2666 followed by a punctuation character), this macro is called with
2667 a null pointer for X and the punctuation character for CODE.
2669 The m68k specific codes are:
2671 '.' for dot needed in Motorola-style opcode names.
2672 '-' for an operand pushing on the stack:
2673 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2674 '+' for an operand pushing on the stack:
2675 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2676 '@' for a reference to the top word on the stack:
2677 sp@, (sp) or (%sp) depending on the style of syntax.
2678 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2679 but & in SGS syntax, $ in CRDS/UNOS syntax).
2680 '!' for the cc register (used in an `and to cc' insn).
2681 '$' for the letter `s' in an op code, but only on the 68040.
2682 '&' for the letter `d' in an op code, but only on the 68040.
2683 '/' for register prefix needed by longlong.h.
2685 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2686 'd' to force memory addressing to be absolute, not relative.
2687 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2688 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2689 than directly). Second part of 'y' below.
2690 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2691 or print pair of registers as rx:ry.
2692 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2693 CONST_DOUBLE's as SunFPA constant RAM registers if
2694 possible, so it should not be used except for the SunFPA.
2699 print_operand (file
, op
, letter
)
2700 FILE *file
; /* file to write to */
2701 rtx op
; /* operand to print */
2702 int letter
; /* %<letter> or 0 */
2704 #ifdef SUPPORT_SUN_FPA
2710 #if defined (MOTOROLA) && !defined (CRDS)
2711 asm_fprintf (file
, ".");
2714 else if (letter
== '#')
2716 asm_fprintf (file
, "%0I");
2718 else if (letter
== '-')
2721 asm_fprintf (file
, "-(%Rsp)");
2723 asm_fprintf (file
, "%Rsp@-");
2726 else if (letter
== '+')
2729 asm_fprintf (file
, "(%Rsp)+");
2731 asm_fprintf (file
, "%Rsp@+");
2734 else if (letter
== '@')
2737 asm_fprintf (file
, "(%Rsp)");
2739 asm_fprintf (file
, "%Rsp@");
2742 else if (letter
== '!')
2744 asm_fprintf (file
, "%Rfpcr");
2746 else if (letter
== '$')
2748 if (TARGET_68040_ONLY
)
2750 fprintf (file
, "s");
2753 else if (letter
== '&')
2755 if (TARGET_68040_ONLY
)
2757 fprintf (file
, "d");
2760 else if (letter
== '/')
2762 asm_fprintf (file
, "%R");
2764 else if (GET_CODE (op
) == REG
)
2766 #ifdef SUPPORT_SUN_FPA
2768 && (letter
== 'y' || letter
== 'x')
2769 && GET_MODE (op
) == DFmode
)
2771 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2772 reg_names
[REGNO (op
)+1]);
2778 /* Print out the second register name of a register pair.
2779 I.e., R (6) => 7. */
2780 fputs (reg_names
[REGNO (op
) + 1], file
);
2782 fputs (reg_names
[REGNO (op
)], file
);
2785 else if (GET_CODE (op
) == MEM
)
2787 output_address (XEXP (op
, 0));
2788 if (letter
== 'd' && ! TARGET_68020
2789 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2790 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2791 && INTVAL (XEXP (op
, 0)) < 0x8000
2792 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2795 fprintf (file
, ".l");
2797 fprintf (file
, ":l");
2801 #ifdef SUPPORT_SUN_FPA
2802 else if ((letter
== 'y' || letter
== 'w')
2803 && GET_CODE (op
) == CONST_DOUBLE
2804 && (i
= standard_sun_fpa_constant_p (op
)))
2806 fprintf (file
, "%%%d", i
& 0x1ff);
2809 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2812 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2813 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2815 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2818 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2819 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2821 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2824 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2825 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2829 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2834 /* A C compound statement to output to stdio stream STREAM the
2835 assembler syntax for an instruction operand that is a memory
2836 reference whose address is ADDR. ADDR is an RTL expression.
2838 Note that this contains a kludge that knows that the only reason
2839 we have an address (plus (label_ref...) (reg...)) when not generating
2840 PIC code is in the insn before a tablejump, and we know that m68k.md
2841 generates a label LInnn: on such an insn.
2843 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2844 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2846 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2847 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2848 we want. This difference can be accommodated by using an assembler
2849 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2850 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2851 macro. See m68k/sgs.h for an example; for versions without the bug.
2852 Some assemblers refuse all the above solutions. The workaround is to
2853 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2856 They also do not like things like "pea 1.w", so we simple leave off
2857 the .w on small constants.
2859 This routine is responsible for distinguishing between -fpic and -fPIC
2860 style relocations in an address. When generating -fpic code the
2861 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2862 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2864 #ifndef ASM_OUTPUT_CASE_FETCH
2867 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2868 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2870 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2871 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2874 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2875 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2877 #endif /* ASM_OUTPUT_CASE_FETCH */
2880 print_operand_address (file
, addr
)
2884 register rtx reg1
, reg2
, breg
, ireg
;
2887 switch (GET_CODE (addr
))
2891 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2893 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2898 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2900 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2905 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2907 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2911 reg1
= reg2
= ireg
= breg
= offset
= 0;
2912 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2914 offset
= XEXP (addr
, 0);
2915 addr
= XEXP (addr
, 1);
2917 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2919 offset
= XEXP (addr
, 1);
2920 addr
= XEXP (addr
, 0);
2922 if (GET_CODE (addr
) != PLUS
)
2926 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2928 reg1
= XEXP (addr
, 0);
2929 addr
= XEXP (addr
, 1);
2931 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2933 reg1
= XEXP (addr
, 1);
2934 addr
= XEXP (addr
, 0);
2936 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2938 reg1
= XEXP (addr
, 0);
2939 addr
= XEXP (addr
, 1);
2941 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2943 reg1
= XEXP (addr
, 1);
2944 addr
= XEXP (addr
, 0);
2946 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2948 reg1
= XEXP (addr
, 0);
2949 addr
= XEXP (addr
, 1);
2951 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2953 reg1
= XEXP (addr
, 1);
2954 addr
= XEXP (addr
, 0);
2956 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2957 || GET_CODE (addr
) == SIGN_EXTEND
)
2969 #if 0 /* for OLD_INDEXING */
2970 else if (GET_CODE (addr
) == PLUS
)
2972 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2974 reg2
= XEXP (addr
, 0);
2975 addr
= XEXP (addr
, 1);
2977 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2979 reg2
= XEXP (addr
, 1);
2980 addr
= XEXP (addr
, 0);
2992 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2993 || GET_CODE (reg1
) == MULT
))
2994 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2999 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3004 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3005 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3008 if (GET_CODE (ireg
) == MULT
)
3010 scale
= INTVAL (XEXP (ireg
, 1));
3011 ireg
= XEXP (ireg
, 0);
3013 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3015 ASM_OUTPUT_CASE_FETCH (file
,
3016 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3017 reg_names
[REGNO (XEXP (ireg
, 0))]);
3018 fprintf (file
, "w");
3022 ASM_OUTPUT_CASE_FETCH (file
,
3023 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3024 reg_names
[REGNO (ireg
)]);
3025 fprintf (file
, "l");
3030 fprintf (file
, "*%d", scale
);
3032 fprintf (file
, ":%d", scale
);
3038 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3039 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3041 ASM_OUTPUT_CASE_FETCH (file
,
3042 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3043 reg_names
[REGNO (breg
)]);
3044 fprintf (file
, "l)");
3047 if (ireg
!= 0 || breg
!= 0)
3054 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3061 output_addr_const (file
, addr
);
3062 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3064 fprintf (file
, "@GOT");
3066 fprintf (file
, ".w");
3069 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3075 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3078 output_addr_const (file
, addr
);
3079 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3080 fprintf (file
, ":w");
3081 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3082 fprintf (file
, ":l");
3084 if (addr
!= 0 && ireg
!= 0)
3089 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3091 scale
= INTVAL (XEXP (ireg
, 1));
3092 ireg
= XEXP (ireg
, 0);
3094 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3097 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3099 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3105 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3107 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3113 fprintf (file
, "*%d", scale
);
3115 fprintf (file
, ":%d", scale
);
3121 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3122 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3124 ASM_OUTPUT_CASE_FETCH (file
,
3125 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3126 reg_names
[REGNO (reg1
)]);
3127 fprintf (file
, "l)");
3130 /* FALL-THROUGH (is this really what we want? */
3132 if (GET_CODE (addr
) == CONST_INT
3133 && INTVAL (addr
) < 0x8000
3134 && INTVAL (addr
) >= -0x8000)
3138 /* Many SGS assemblers croak on size specifiers for constants. */
3139 fprintf (file
, "%d", INTVAL (addr
));
3141 fprintf (file
, "%d.w", INTVAL (addr
));
3144 fprintf (file
, "%d:w", INTVAL (addr
));
3149 output_addr_const (file
, addr
);
3155 /* Check for cases where a clr insns can be omitted from code using
3156 strict_low_part sets. For example, the second clrl here is not needed:
3157 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3159 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3160 insn we are checking for redundancy. TARGET is the register set by the
3164 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3165 enum machine_mode mode
;
3171 p
= prev_nonnote_insn (first_insn
);
3175 /* If it isn't an insn, then give up. */
3176 if (GET_CODE (p
) != INSN
)
3179 if (reg_set_p (target
, p
))
3181 rtx set
= single_set (p
);
3184 /* If it isn't an easy to recognize insn, then give up. */
3188 dest
= SET_DEST (set
);
3190 /* If this sets the entire target register to zero, then our
3191 first_insn is redundant. */
3192 if (rtx_equal_p (dest
, target
)
3193 && SET_SRC (set
) == const0_rtx
)
3195 else if (GET_CODE (dest
) == STRICT_LOW_PART
3196 && GET_CODE (XEXP (dest
, 0)) == REG
3197 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3198 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3199 <= GET_MODE_SIZE (mode
)))
3200 /* This is a strict low part set which modifies less than
3201 we are using, so it is safe. */
3207 p
= prev_nonnote_insn (p
);
3214 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3215 range carefully since this predicate is used in DImode contexts. Also, we
3216 need some extra crud to make it work when hosted on 64-bit machines. */
3219 const_uint32_operand (op
, mode
)
3221 enum machine_mode mode
;
3223 #if HOST_BITS_PER_WIDE_INT > 32
3224 /* All allowed constants will fit a CONST_INT. */
3225 return (GET_CODE (op
) == CONST_INT
3226 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3228 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3229 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3233 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3234 to check the range carefully since this predicate is used in DImode
3238 const_sint32_operand (op
, mode
)
3240 enum machine_mode mode
;
3242 /* All allowed constants will fit a CONST_INT. */
3243 return (GET_CODE (op
) == CONST_INT
3244 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3248 output_andsi3 (operands
)
3252 if (GET_CODE (operands
[2]) == CONST_INT
3253 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3254 && (DATA_REG_P (operands
[0])
3255 || offsettable_memref_p (operands
[0]))
3258 if (GET_CODE (operands
[0]) != REG
)
3259 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3260 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3261 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3263 if (operands
[2] == const0_rtx
)
3265 return "and%.w %2,%0";
3267 if (GET_CODE (operands
[2]) == CONST_INT
3268 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3269 && (DATA_REG_P (operands
[0])
3270 || offsettable_memref_p (operands
[0])))
3272 if (DATA_REG_P (operands
[0]))
3274 operands
[1] = GEN_INT (logval
);
3278 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3279 operands
[1] = GEN_INT (logval
% 8);
3281 /* This does not set condition codes in a standard way. */
3283 return "bclr %1,%0";
3285 return "and%.l %2,%0";
3289 output_iorsi3 (operands
)
3292 register int logval
;
3293 if (GET_CODE (operands
[2]) == CONST_INT
3294 && INTVAL (operands
[2]) >> 16 == 0
3295 && (DATA_REG_P (operands
[0])
3296 || offsettable_memref_p (operands
[0]))
3299 if (GET_CODE (operands
[0]) != REG
)
3300 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3301 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3303 if (INTVAL (operands
[2]) == 0xffff)
3304 return "mov%.w %2,%0";
3305 return "or%.w %2,%0";
3307 if (GET_CODE (operands
[2]) == CONST_INT
3308 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3309 && (DATA_REG_P (operands
[0])
3310 || offsettable_memref_p (operands
[0])))
3312 if (DATA_REG_P (operands
[0]))
3314 operands
[1] = GEN_INT (logval
);
3318 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3319 operands
[1] = GEN_INT (logval
% 8);
3322 return "bset %1,%0";
3324 return "or%.l %2,%0";
3328 output_xorsi3 (operands
)
3331 register int logval
;
3332 if (GET_CODE (operands
[2]) == CONST_INT
3333 && INTVAL (operands
[2]) >> 16 == 0
3334 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3337 if (! DATA_REG_P (operands
[0]))
3338 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3339 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3341 if (INTVAL (operands
[2]) == 0xffff)
3343 return "eor%.w %2,%0";
3345 if (GET_CODE (operands
[2]) == CONST_INT
3346 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3347 && (DATA_REG_P (operands
[0])
3348 || offsettable_memref_p (operands
[0])))
3350 if (DATA_REG_P (operands
[0]))
3352 operands
[1] = GEN_INT (logval
);
3356 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3357 operands
[1] = GEN_INT (logval
% 8);
3360 return "bchg %1,%0";
3362 return "eor%.l %2,%0";