1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 /* The ASM_DOT macro allows easy string pasting to handle the differences
48 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
49 support the %. option. */
52 # define ASM_DOTW ".w"
53 # define ASM_DOTL ".l"
61 /* Structure describing stack frame layout. */
64 /* Stack pointer to frame pointer offset. */
67 /* Offset of FPU registers. */
68 HOST_WIDE_INT foffset
;
70 /* Frame size in bytes (rounded up). */
73 /* Data and address register. */
75 unsigned int reg_mask
;
76 unsigned int reg_rev_mask
;
80 unsigned int fpu_mask
;
81 unsigned int fpu_rev_mask
;
83 /* Offsets relative to ARG_POINTER. */
84 HOST_WIDE_INT frame_pointer_offset
;
85 HOST_WIDE_INT stack_pointer_offset
;
87 /* Function which the above information refers to. */
91 /* Current frame information calculated by m68k_compute_frame_layout(). */
92 static struct m68k_frame current_frame
;
94 static rtx
find_addr_reg (rtx
);
95 static const char *singlemove_string (rtx
*);
96 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
97 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
98 #ifdef M68K_TARGET_COFF
99 static void m68k_coff_asm_named_section (const char *, unsigned int);
100 #endif /* M68K_TARGET_COFF */
101 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
102 HOST_WIDE_INT
, tree
);
103 static rtx
m68k_struct_value_rtx (tree
, int);
104 static bool m68k_interrupt_function_p (tree func
);
105 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
106 tree args
, int flags
,
108 static void m68k_compute_frame_layout (void);
109 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
110 static int const_int_cost (rtx
);
111 static bool m68k_rtx_costs (rtx
, int, int, int *);
114 /* Alignment to use for loops and jumps */
115 /* Specify power of two alignment used for loops. */
116 const char *m68k_align_loops_string
;
117 /* Specify power of two alignment used for non-loop jumps. */
118 const char *m68k_align_jumps_string
;
119 /* Specify power of two alignment used for functions. */
120 const char *m68k_align_funcs_string
;
121 /* Specify the identification number of the library being built */
122 const char *m68k_library_id_string
;
124 /* Specify power of two alignment used for loops. */
125 int m68k_align_loops
;
126 /* Specify power of two alignment used for non-loop jumps. */
127 int m68k_align_jumps
;
128 /* Specify power of two alignment used for functions. */
129 int m68k_align_funcs
;
131 /* Nonzero if the last compare/test insn had FP operands. The
132 sCC expanders peek at this to determine what to do for the
133 68060, which has no fsCC instructions. */
134 int m68k_last_compare_had_fp_operands
;
136 /* Initialize the GCC target structure. */
138 #if INT_OP_GROUP == INT_OP_DOT_WORD
139 #undef TARGET_ASM_ALIGNED_HI_OP
140 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
143 #if INT_OP_GROUP == INT_OP_NO_DOT
144 #undef TARGET_ASM_BYTE_OP
145 #define TARGET_ASM_BYTE_OP "\tbyte\t"
146 #undef TARGET_ASM_ALIGNED_HI_OP
147 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
148 #undef TARGET_ASM_ALIGNED_SI_OP
149 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
152 #if INT_OP_GROUP == INT_OP_DC
153 #undef TARGET_ASM_BYTE_OP
154 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
155 #undef TARGET_ASM_ALIGNED_HI_OP
156 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
157 #undef TARGET_ASM_ALIGNED_SI_OP
158 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
161 #undef TARGET_ASM_UNALIGNED_HI_OP
162 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
163 #undef TARGET_ASM_UNALIGNED_SI_OP
164 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
166 #undef TARGET_ASM_FUNCTION_PROLOGUE
167 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
168 #undef TARGET_ASM_FUNCTION_EPILOGUE
169 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
171 #undef TARGET_ASM_OUTPUT_MI_THUNK
172 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
173 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
174 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
176 #undef TARGET_ASM_FILE_START_APP_OFF
177 #define TARGET_ASM_FILE_START_APP_OFF true
179 #undef TARGET_RTX_COSTS
180 #define TARGET_RTX_COSTS m68k_rtx_costs
182 #undef TARGET_ATTRIBUTE_TABLE
183 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
185 #undef TARGET_PROMOTE_PROTOTYPES
186 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
188 #undef TARGET_STRUCT_VALUE_RTX
189 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
191 static const struct attribute_spec m68k_attribute_table
[] =
193 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
194 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
195 { NULL
, 0, 0, false, false, false, NULL
}
198 struct gcc_target targetm
= TARGET_INITIALIZER
;
200 /* Sometimes certain combinations of command options do not make
201 sense on a particular target machine. You can define a macro
202 `OVERRIDE_OPTIONS' to take account of this. This macro, if
203 defined, is executed once just after all the command options have
206 Don't use this macro to turn on various extra optimizations for
207 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
210 override_options (void)
217 /* Validate -malign-loops= value, or provide default */
218 m68k_align_loops
= def_align
;
219 if (m68k_align_loops_string
)
221 i
= atoi (m68k_align_loops_string
);
222 if (i
< 1 || i
> MAX_CODE_ALIGN
)
223 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
225 m68k_align_loops
= i
;
228 /* Library identification */
229 if (m68k_library_id_string
)
233 if (! TARGET_ID_SHARED_LIBRARY
)
234 error ("-mshared-library-id= specified without -mid-shared-library");
235 id
= atoi (m68k_library_id_string
);
236 if (id
< 0 || id
> MAX_LIBRARY_ID
)
237 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
239 /* From now on, m68k_library_id_string will contain the library offset. */
240 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
243 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
245 m68k_library_id_string
= "_current_shared_library_a5_offset_";
247 /* Sanity check to ensure that msep-data and mid-sahred-library are not
248 * both specified together. Doing so simply doesn't make sense.
250 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
251 error ("cannot specify both -msep-data and -mid-shared-library");
253 /* If we're generating code for a separate A5 relative data segment,
254 * we've got to enable -fPIC as well. This might be relaxable to
255 * -fpic but it hasn't been tested properly.
257 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
260 /* Validate -malign-jumps= value, or provide default */
261 m68k_align_jumps
= def_align
;
262 if (m68k_align_jumps_string
)
264 i
= atoi (m68k_align_jumps_string
);
265 if (i
< 1 || i
> MAX_CODE_ALIGN
)
266 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
268 m68k_align_jumps
= i
;
271 /* Validate -malign-functions= value, or provide default */
272 m68k_align_funcs
= def_align
;
273 if (m68k_align_funcs_string
)
275 i
= atoi (m68k_align_funcs_string
);
276 if (i
< 1 || i
> MAX_CODE_ALIGN
)
277 error ("-malign-functions=%d is not between 1 and %d",
280 m68k_align_funcs
= i
;
283 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
285 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
286 error("-fPIC is not currently supported on the 68000 or 68010\n");
288 /* ??? A historic way of turning on pic, or is this intended to
289 be an embedded thing that doesn't have the same name binding
290 significance that it does on hosted ELF systems? */
291 if (TARGET_PCREL
&& flag_pic
== 0)
294 /* Turn off function cse if we are doing PIC. We always want function call
295 to be done as `bsr foo@PLTPC', so it will force the assembler to create
296 the PLT entry for `foo'. Doing function cse will cause the address of
297 `foo' to be loaded into a register, which is exactly what we want to
298 avoid when we are doing PIC on svr4 m68k. */
300 flag_no_function_cse
= 1;
302 SUBTARGET_OVERRIDE_OPTIONS
;
305 /* Return nonzero if FUNC is an interrupt function as specified by the
306 "interrupt_handler" attribute. */
308 m68k_interrupt_function_p(tree func
)
312 if (TREE_CODE (func
) != FUNCTION_DECL
)
315 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
316 return (a
!= NULL_TREE
);
319 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
320 struct attribute_spec.handler. */
322 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
323 tree args ATTRIBUTE_UNUSED
,
324 int flags ATTRIBUTE_UNUSED
,
327 if (TREE_CODE (*node
) != FUNCTION_DECL
)
329 warning ("`%s' attribute only applies to functions",
330 IDENTIFIER_POINTER (name
));
331 *no_add_attrs
= true;
338 m68k_compute_frame_layout (void)
341 unsigned int mask
, rmask
;
342 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
344 /* Only compute the frame once per function.
345 Don't cache information until reload has been completed. */
346 if (current_frame
.funcdef_no
== current_function_funcdef_no
350 current_frame
.size
= (get_frame_size () + 3) & -4;
352 mask
= rmask
= saved
= 0;
353 for (regno
= 0; regno
< 16; regno
++)
354 if (m68k_save_reg (regno
, interrupt_handler
))
357 rmask
|= 1 << (15 - regno
);
360 current_frame
.offset
= saved
* 4;
361 current_frame
.reg_no
= saved
;
362 current_frame
.reg_mask
= mask
;
363 current_frame
.reg_rev_mask
= rmask
;
365 current_frame
.foffset
= 0;
366 mask
= rmask
= saved
= 0;
367 if (TARGET_68881
/* || TARGET_CFV4E */)
369 for (regno
= 16; regno
< 24; regno
++)
370 if (m68k_save_reg (regno
, interrupt_handler
))
372 mask
|= 1 << (regno
- 16);
373 rmask
|= 1 << (23 - regno
);
376 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
377 current_frame
.offset
+= current_frame
.foffset
;
379 current_frame
.fpu_no
= saved
;
380 current_frame
.fpu_mask
= mask
;
381 current_frame
.fpu_rev_mask
= rmask
;
383 /* Remember what function this frame refers to. */
384 current_frame
.funcdef_no
= current_function_funcdef_no
;
388 m68k_initial_elimination_offset (int from
, int to
)
390 /* FIXME: The correct offset to compute here would appear to be
391 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
392 but for some obscure reason, this must be 0 to get correct code. */
393 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
396 m68k_compute_frame_layout ();
398 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
399 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
400 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
401 return current_frame
.offset
+ current_frame
.size
;
406 /* Refer to the array `regs_ever_live' to determine which registers
407 to save; `regs_ever_live[I]' is nonzero if register number I
408 is ever used in the function. This function is responsible for
409 knowing which registers should not be saved even if used.
410 Return true if we need to save REGNO. */
413 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
415 if (flag_pic
&& current_function_uses_pic_offset_table
416 && regno
== PIC_OFFSET_TABLE_REGNUM
)
419 if (current_function_calls_eh_return
)
424 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
425 if (test
== INVALID_REGNUM
)
432 /* Fixed regs we never touch. */
433 if (fixed_regs
[regno
])
436 /* The frame pointer (if it is such) is handled specially. */
437 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
440 /* Interrupt handlers must also save call_used_regs
441 if they are live or when calling nested functions. */
442 if (interrupt_handler
)
444 if (regs_ever_live
[regno
])
447 if (!current_function_is_leaf
&& call_used_regs
[regno
])
451 /* Never need to save registers that aren't touched. */
452 if (!regs_ever_live
[regno
])
455 /* Otherwise save everything that isn't call-clobbered. */
456 return !call_used_regs
[regno
];
459 /* This function generates the assembly code for function entry.
460 STREAM is a stdio stream to output the code to.
461 SIZE is an int: how many units of temporary storage to allocate. */
464 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
466 HOST_WIDE_INT fsize_with_regs
;
467 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
469 m68k_compute_frame_layout();
471 /* If the stack limit is a symbol, we can check it here,
472 before actually allocating the space. */
473 if (current_function_limit_stack
474 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
475 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
476 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
478 /* On ColdFire add register save into initial stack frame setup, if possible. */
479 fsize_with_regs
= current_frame
.size
;
480 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
481 fsize_with_regs
+= current_frame
.reg_no
* 4;
483 if (frame_pointer_needed
)
485 if (current_frame
.size
== 0 && TARGET_68040
)
486 /* on the 68040, pea + move is faster than link.w 0 */
487 fprintf (stream
, MOTOROLA
?
488 "\tpea (%s)\n\tmove.l %s,%s\n" :
489 "\tpea %s@\n\tmovel %s,%s\n",
490 M68K_REGNAME(FRAME_POINTER_REGNUM
),
491 M68K_REGNAME(STACK_POINTER_REGNUM
),
492 M68K_REGNAME(FRAME_POINTER_REGNUM
));
493 else if (fsize_with_regs
< 0x8000)
494 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
495 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
496 else if (TARGET_68020
)
497 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
498 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
500 /* Adding negative number is faster on the 68040. */
501 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
502 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
503 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
505 if (dwarf2out_do_frame ())
508 l
= (char *) dwarf2out_cfi_label ();
510 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
511 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
512 cfa_offset
+= current_frame
.size
;
515 else if (fsize_with_regs
) /* !frame_pointer_needed */
517 if (fsize_with_regs
< 0x8000)
519 if (fsize_with_regs
<= 8)
521 if (!TARGET_COLDFIRE
)
522 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
525 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
528 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
529 /* On the CPU32 it is faster to use two subqw instructions to
530 subtract a small integer (8 < N <= 16) to a register. */
532 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
533 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
534 fsize_with_regs
- 8);
535 else if (TARGET_68040
)
536 /* Adding negative number is faster on the 68040. */
537 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
540 asm_fprintf (stream
, MOTOROLA
?
541 "\tlea (%wd,%Rsp),%Rsp\n" :
542 "\tlea %Rsp@(%wd),%Rsp\n",
545 else /* fsize_with_regs >= 0x8000 */
546 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
548 if (dwarf2out_do_frame ())
550 cfa_offset
+= current_frame
.size
+ 4;
551 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
553 } /* !frame_pointer_needed */
555 if (current_frame
.fpu_mask
)
557 asm_fprintf (stream
, MOTOROLA
?
558 "\tfmovm %I0x%x,-(%Rsp)\n" :
559 "\tfmovem %I0x%x,%Rsp@-\n",
560 current_frame
.fpu_mask
);
562 if (dwarf2out_do_frame ())
564 char *l
= (char *) dwarf2out_cfi_label ();
567 cfa_offset
+= current_frame
.fpu_no
* 12;
568 if (! frame_pointer_needed
)
569 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
570 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
571 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
572 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
576 /* If the stack limit is not a symbol, check it here.
577 This has the disadvantage that it may be too late... */
578 if (current_function_limit_stack
)
580 if (REG_P (stack_limit_rtx
))
581 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
582 M68K_REGNAME(REGNO (stack_limit_rtx
)));
583 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
584 warning ("stack limit expression is not supported");
587 if (current_frame
.reg_no
<= 2)
589 /* Store each separately in the same order moveml uses.
590 Using two movel instructions instead of a single moveml
591 is about 15% faster for the 68020 and 68030 at no expense
596 for (i
= 0; i
< 16; i
++)
597 if (current_frame
.reg_rev_mask
& (1 << i
))
599 asm_fprintf (stream
, MOTOROLA
?
600 "\t%Omove.l %s,-(%Rsp)\n" :
601 "\tmovel %s,%Rsp@-\n",
602 M68K_REGNAME(15 - i
));
603 if (dwarf2out_do_frame ())
605 char *l
= (char *) dwarf2out_cfi_label ();
608 if (! frame_pointer_needed
)
609 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
610 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
614 else if (current_frame
.reg_rev_mask
)
617 /* The ColdFire does not support the predecrement form of the
618 MOVEM instruction, so we must adjust the stack pointer and
619 then use the plain address register indirect mode.
620 The required register save space was combined earlier with
621 the fsize_with_regs amount. */
623 asm_fprintf (stream
, MOTOROLA
?
624 "\tmovm.l %I0x%x,(%Rsp)\n" :
625 "\tmoveml %I0x%x,%Rsp@\n",
626 current_frame
.reg_mask
);
628 asm_fprintf (stream
, MOTOROLA
?
629 "\tmovm.l %I0x%x,-(%Rsp)\n" :
630 "\tmoveml %I0x%x,%Rsp@-\n",
631 current_frame
.reg_rev_mask
);
632 if (dwarf2out_do_frame ())
634 char *l
= (char *) dwarf2out_cfi_label ();
637 cfa_offset
+= current_frame
.reg_no
* 4;
638 if (! frame_pointer_needed
)
639 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
640 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
641 if (current_frame
.reg_mask
& (1 << regno
))
642 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
645 if (!TARGET_SEP_DATA
&& flag_pic
&&
646 (current_function_uses_pic_offset_table
||
647 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
649 if (TARGET_ID_SHARED_LIBRARY
)
651 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
652 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
653 m68k_library_id_string
,
654 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
659 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
660 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
663 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
664 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
665 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
666 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
667 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
673 /* Return true if this function's epilogue can be output as RTL. */
676 use_return_insn (void)
678 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
681 /* We can output the epilogue as RTL only if no registers need to be
683 m68k_compute_frame_layout();
684 return current_frame
.reg_no
? false : true;
687 /* This function generates the assembly code for function exit,
688 on machines that need it.
690 The function epilogue should not depend on the current stack pointer!
691 It should use the frame pointer only, if there is a frame pointer.
692 This is mandatory because of alloca; we also take advantage of it to
693 omit stack adjustments before returning. */
696 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
698 HOST_WIDE_INT fsize
, fsize_with_regs
;
700 bool restore_from_sp
= false;
701 rtx insn
= get_last_insn ();
703 m68k_compute_frame_layout();
705 /* If the last insn was a BARRIER, we don't have to write any code. */
706 if (GET_CODE (insn
) == NOTE
)
707 insn
= prev_nonnote_insn (insn
);
708 if (insn
&& GET_CODE (insn
) == BARRIER
)
710 /* Output just a no-op so that debuggers don't get confused
711 about which function the pc is in at this address. */
712 fprintf (stream
, "\tnop\n");
716 #ifdef FUNCTION_EXTRA_EPILOGUE
717 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
720 fsize
= current_frame
.size
;
722 /* FIXME : leaf_function_p below is too strong.
723 What we really need to know there is if there could be pending
724 stack adjustment needed at that point. */
725 restore_from_sp
= ! frame_pointer_needed
726 || (! current_function_calls_alloca
&& leaf_function_p ());
728 /* fsize_with_regs is the size we need to adjust the sp when
729 popping the frame. */
730 fsize_with_regs
= fsize
;
732 /* Because the ColdFire doesn't support moveml with
733 complex address modes, we must adjust the stack manually
734 after restoring registers. When the frame pointer isn't used,
735 we can merge movem adjustment into frame unlinking
736 made immediately after it. */
737 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
738 fsize_with_regs
+= current_frame
.reg_no
* 4;
740 if (current_frame
.offset
+ fsize
>= 0x8000
742 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
744 /* Because the ColdFire doesn't support moveml with
745 complex address modes we make an extra correction here. */
747 fsize
+= current_frame
.offset
;
749 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
750 fsize
= 0, big
= true;
752 if (current_frame
.reg_no
<= 2)
754 /* Restore each separately in the same order moveml does.
755 Using two movel instructions instead of a single moveml
756 is about 15% faster for the 68020 and 68030 at no expense
760 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
762 for (i
= 0; i
< 16; i
++)
763 if (current_frame
.reg_mask
& (1 << i
))
768 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
770 M68K_REGNAME(FRAME_POINTER_REGNUM
),
773 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
774 M68K_REGNAME(FRAME_POINTER_REGNUM
),
778 else if (restore_from_sp
)
779 asm_fprintf (stream
, MOTOROLA
?
780 "\t%Omove.l (%Rsp)+,%s\n" :
781 "\tmovel %Rsp@+,%s\n",
786 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
788 M68K_REGNAME(FRAME_POINTER_REGNUM
),
791 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
792 M68K_REGNAME(FRAME_POINTER_REGNUM
),
799 else if (current_frame
.reg_mask
)
801 /* The ColdFire requires special handling due to its limited moveml insn. */
806 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
807 M68K_REGNAME(FRAME_POINTER_REGNUM
));
808 asm_fprintf (stream
, MOTOROLA
?
809 "\tmovm.l (%Ra1),%I0x%x\n" :
810 "\tmoveml %Ra1@,%I0x%x\n",
811 current_frame
.reg_mask
);
813 else if (restore_from_sp
)
814 asm_fprintf (stream
, MOTOROLA
?
815 "\tmovm.l (%Rsp),%I0x%x\n" :
816 "\tmoveml %Rsp@,%I0x%x\n",
817 current_frame
.reg_mask
);
821 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
822 current_frame
.offset
+ fsize
,
823 M68K_REGNAME(FRAME_POINTER_REGNUM
),
824 current_frame
.reg_mask
);
826 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
827 M68K_REGNAME(FRAME_POINTER_REGNUM
),
828 current_frame
.offset
+ fsize
,
829 current_frame
.reg_mask
);
832 else /* !TARGET_COLDFIRE */
837 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
838 current_frame
.offset
+ fsize
,
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.reg_mask
);
842 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
843 M68K_REGNAME(FRAME_POINTER_REGNUM
),
844 current_frame
.offset
+ fsize
,
845 current_frame
.reg_mask
);
847 else if (restore_from_sp
)
849 asm_fprintf (stream
, MOTOROLA
?
850 "\tmovm.l (%Rsp)+,%I0x%x\n" :
851 "\tmoveml %Rsp@+,%I0x%x\n",
852 current_frame
.reg_mask
);
857 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
858 current_frame
.offset
+ fsize
,
859 M68K_REGNAME(FRAME_POINTER_REGNUM
),
860 current_frame
.reg_mask
);
862 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
863 M68K_REGNAME(FRAME_POINTER_REGNUM
),
864 current_frame
.offset
+ fsize
,
865 current_frame
.reg_mask
);
869 if (current_frame
.fpu_rev_mask
)
874 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
875 current_frame
.foffset
+ fsize
,
876 M68K_REGNAME(FRAME_POINTER_REGNUM
),
877 current_frame
.fpu_rev_mask
);
879 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
880 M68K_REGNAME(FRAME_POINTER_REGNUM
),
881 current_frame
.foffset
+ fsize
,
882 current_frame
.fpu_rev_mask
);
884 else if (restore_from_sp
)
887 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
888 current_frame
.fpu_rev_mask
);
890 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
891 current_frame
.fpu_rev_mask
);
896 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
897 current_frame
.foffset
+ fsize
,
898 M68K_REGNAME(FRAME_POINTER_REGNUM
),
899 current_frame
.fpu_rev_mask
);
901 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
902 M68K_REGNAME(FRAME_POINTER_REGNUM
),
903 current_frame
.foffset
+ fsize
,
904 current_frame
.fpu_rev_mask
);
907 if (frame_pointer_needed
)
908 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
909 else if (fsize_with_regs
)
911 if (fsize_with_regs
<= 8)
913 if (!TARGET_COLDFIRE
)
914 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
917 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
920 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
922 /* On the CPU32 it is faster to use two addqw instructions to
923 add a small integer (8 < N <= 16) to a register. */
924 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
925 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
926 fsize_with_regs
- 8);
928 else if (fsize_with_regs
< 0x8000)
931 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
934 asm_fprintf (stream
, MOTOROLA
?
935 "\tlea (%wd,%Rsp),%Rsp\n" :
936 "\tlea %Rsp@(%wd),%Rsp\n",
940 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
942 if (current_function_calls_eh_return
)
943 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
944 if (m68k_interrupt_function_p (current_function_decl
))
945 fprintf (stream
, "\trte\n");
946 else if (current_function_pops_args
)
947 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
949 fprintf (stream
, "\trts\n");
952 /* Similar to general_operand, but exclude stack_pointer_rtx. */
955 not_sp_operand (rtx op
, enum machine_mode mode
)
957 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
960 /* Return true if X is a valid comparison operator for the dbcc
963 Note it rejects floating point comparison operators.
964 (In the future we could use Fdbcc).
966 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
969 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
971 switch (GET_CODE (x
))
973 case EQ
: case NE
: case GTU
: case LTU
:
977 /* Reject some when CC_NO_OVERFLOW is set. This may be over
979 case GT
: case LT
: case GE
: case LE
:
980 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
986 /* Return nonzero if flags are currently in the 68881 flag register. */
988 flags_in_68881 (void)
990 /* We could add support for these in the future */
991 return cc_status
.flags
& CC_IN_68881
;
994 /* Output a BSR instruction suitable for PIC code. */
996 m68k_output_pic_call(rtx dest
)
1000 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1002 /* We output a BSR instruction if we're using -fpic or we're building for
1003 * a target that supports long branches. If we're building -fPIC on the
1004 * 68000, 68010 or ColdFire we generate one of two sequences:
1005 * a shorter one that uses a GOT entry or a longer one that doesn't.
1006 * We'll use the -Os command-line flag to decide which to generate.
1007 * Both sequences take the same time to execute on the ColdFire.
1009 else if (TARGET_PCREL
)
1011 else if ((flag_pic
== 1) || TARGET_68020
)
1012 #if defined(USE_GAS)
1013 out
= "bsr.l %0@PLTPC";
1015 out
= "bsr %0@PLTPC";
1017 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1018 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1020 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1022 output_asm_insn(out
, &dest
);
1025 /* Output a dbCC; jCC sequence. Note we do not handle the
1026 floating point version of this sequence (Fdbcc). We also
1027 do not handle alternative conditions when CC_NO_OVERFLOW is
1028 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1029 kick those out before we get here. */
1032 output_dbcc_and_branch (rtx
*operands
)
1034 switch (GET_CODE (operands
[3]))
1037 output_asm_insn (MOTOROLA
?
1038 "dbeq %0,%l1\n\tjbeq %l2" :
1039 "dbeq %0,%l1\n\tjeq %l2",
1044 output_asm_insn (MOTOROLA
?
1045 "dbne %0,%l1\n\tjbne %l2" :
1046 "dbne %0,%l1\n\tjne %l2",
1051 output_asm_insn (MOTOROLA
?
1052 "dbgt %0,%l1\n\tjbgt %l2" :
1053 "dbgt %0,%l1\n\tjgt %l2",
1058 output_asm_insn (MOTOROLA
?
1059 "dbhi %0,%l1\n\tjbhi %l2" :
1060 "dbhi %0,%l1\n\tjhi %l2",
1065 output_asm_insn (MOTOROLA
?
1066 "dblt %0,%l1\n\tjblt %l2" :
1067 "dblt %0,%l1\n\tjlt %l2",
1072 output_asm_insn (MOTOROLA
?
1073 "dbcs %0,%l1\n\tjbcs %l2" :
1074 "dbcs %0,%l1\n\tjcs %l2",
1079 output_asm_insn (MOTOROLA
?
1080 "dbge %0,%l1\n\tjbge %l2" :
1081 "dbge %0,%l1\n\tjge %l2",
1086 output_asm_insn (MOTOROLA
?
1087 "dbcc %0,%l1\n\tjbcc %l2" :
1088 "dbcc %0,%l1\n\tjcc %l2",
1093 output_asm_insn (MOTOROLA
?
1094 "dble %0,%l1\n\tjble %l2" :
1095 "dble %0,%l1\n\tjle %l2",
1100 output_asm_insn (MOTOROLA
?
1101 "dbls %0,%l1\n\tjbls %l2" :
1102 "dbls %0,%l1\n\tjls %l2",
1110 /* If the decrement is to be done in SImode, then we have
1111 to compensate for the fact that dbcc decrements in HImode. */
1112 switch (GET_MODE (operands
[0]))
1115 output_asm_insn (MOTOROLA
?
1116 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1117 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1130 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1133 enum rtx_code op_code
= GET_CODE (op
);
1135 /* This does not produce a useful cc. */
1138 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1139 below. Swap the operands and change the op if these requirements
1140 are not fulfilled. */
1141 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1145 operand1
= operand2
;
1147 op_code
= swap_condition (op_code
);
1149 loperands
[0] = operand1
;
1150 if (GET_CODE (operand1
) == REG
)
1151 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1153 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1154 if (operand2
!= const0_rtx
)
1156 loperands
[2] = operand2
;
1157 if (GET_CODE (operand2
) == REG
)
1158 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1160 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1162 loperands
[4] = gen_label_rtx();
1163 if (operand2
!= const0_rtx
)
1165 output_asm_insn (MOTOROLA
?
1166 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1167 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1172 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1173 output_asm_insn ("tst%.l %0", loperands
);
1176 output_asm_insn ("cmp%.w #0,%0", loperands
);
1179 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1181 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1182 output_asm_insn ("tst%.l %1", loperands
);
1184 output_asm_insn ("cmp%.w #0,%1", loperands
);
1187 loperands
[5] = dest
;
1192 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1193 CODE_LABEL_NUMBER (loperands
[4]));
1194 output_asm_insn ("seq %5", loperands
);
1198 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1199 CODE_LABEL_NUMBER (loperands
[4]));
1200 output_asm_insn ("sne %5", loperands
);
1204 loperands
[6] = gen_label_rtx();
1205 output_asm_insn (MOTOROLA
?
1206 "shi %5\n\tjbra %l6" :
1207 "shi %5\n\tjra %l6",
1209 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1210 CODE_LABEL_NUMBER (loperands
[4]));
1211 output_asm_insn ("sgt %5", loperands
);
1212 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1213 CODE_LABEL_NUMBER (loperands
[6]));
1217 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1218 CODE_LABEL_NUMBER (loperands
[4]));
1219 output_asm_insn ("shi %5", loperands
);
1223 loperands
[6] = gen_label_rtx();
1224 output_asm_insn (MOTOROLA
?
1225 "scs %5\n\tjbra %l6" :
1226 "scs %5\n\tjra %l6",
1228 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1229 CODE_LABEL_NUMBER (loperands
[4]));
1230 output_asm_insn ("slt %5", loperands
);
1231 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1232 CODE_LABEL_NUMBER (loperands
[6]));
1236 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1237 CODE_LABEL_NUMBER (loperands
[4]));
1238 output_asm_insn ("scs %5", loperands
);
1242 loperands
[6] = gen_label_rtx();
1243 output_asm_insn (MOTOROLA
?
1244 "scc %5\n\tjbra %l6" :
1245 "scc %5\n\tjra %l6",
1247 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1248 CODE_LABEL_NUMBER (loperands
[4]));
1249 output_asm_insn ("sge %5", loperands
);
1250 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1251 CODE_LABEL_NUMBER (loperands
[6]));
1255 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1256 CODE_LABEL_NUMBER (loperands
[4]));
1257 output_asm_insn ("scc %5", loperands
);
1261 loperands
[6] = gen_label_rtx();
1262 output_asm_insn (MOTOROLA
?
1263 "sls %5\n\tjbra %l6" :
1264 "sls %5\n\tjra %l6",
1266 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1267 CODE_LABEL_NUMBER (loperands
[4]));
1268 output_asm_insn ("sle %5", loperands
);
1269 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1270 CODE_LABEL_NUMBER (loperands
[6]));
1274 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1275 CODE_LABEL_NUMBER (loperands
[4]));
1276 output_asm_insn ("sls %5", loperands
);
1286 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1288 operands
[0] = countop
;
1289 operands
[1] = dataop
;
1291 if (GET_CODE (countop
) == CONST_INT
)
1293 register int count
= INTVAL (countop
);
1294 /* If COUNT is bigger than size of storage unit in use,
1295 advance to the containing unit of same size. */
1296 if (count
> signpos
)
1298 int offset
= (count
& ~signpos
) / 8;
1299 count
= count
& signpos
;
1300 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1302 if (count
== signpos
)
1303 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1305 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1307 /* These three statements used to use next_insns_test_no...
1308 but it appears that this should do the same job. */
1310 && next_insn_tests_no_inequality (insn
))
1313 && next_insn_tests_no_inequality (insn
))
1316 && next_insn_tests_no_inequality (insn
))
1319 cc_status
.flags
= CC_NOT_NEGATIVE
;
1321 return "btst %0,%1";
1324 /* Returns true if OP is either a symbol reference or a sum of a symbol
1325 reference and a constant. */
1328 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1330 switch (GET_CODE (op
))
1338 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1339 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1340 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1342 #if 0 /* Deleted, with corresponding change in m68k.h,
1343 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1345 return GET_MODE (op
) == mode
;
1353 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1356 extend_operator(rtx x
, enum machine_mode mode
)
1358 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1360 switch (GET_CODE(x
))
1371 /* Legitimize PIC addresses. If the address is already
1372 position-independent, we return ORIG. Newly generated
1373 position-independent addresses go to REG. If we need more
1374 than one register, we lose.
1376 An address is legitimized by making an indirect reference
1377 through the Global Offset Table with the name of the symbol
1380 The assembler and linker are responsible for placing the
1381 address of the symbol in the GOT. The function prologue
1382 is responsible for initializing a5 to the starting address
1385 The assembler is also responsible for translating a symbol name
1386 into a constant displacement from the start of the GOT.
1388 A quick example may make things a little clearer:
1390 When not generating PIC code to store the value 12345 into _foo
1391 we would generate the following code:
1395 When generating PIC two transformations are made. First, the compiler
1396 loads the address of foo into a register. So the first transformation makes:
1401 The code in movsi will intercept the lea instruction and call this
1402 routine which will transform the instructions into:
1404 movel a5@(_foo:w), a0
1408 That (in a nutshell) is how *all* symbol and label references are
1412 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1417 /* First handle a simple SYMBOL_REF or LABEL_REF */
1418 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1423 pic_ref
= gen_rtx_MEM (Pmode
,
1424 gen_rtx_PLUS (Pmode
,
1425 pic_offset_table_rtx
, orig
));
1426 current_function_uses_pic_offset_table
= 1;
1427 RTX_UNCHANGING_P (pic_ref
) = 1;
1428 emit_move_insn (reg
, pic_ref
);
1431 else if (GET_CODE (orig
) == CONST
)
1435 /* Make sure this has not already been legitimized. */
1436 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1437 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1443 /* legitimize both operands of the PLUS */
1444 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1446 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1447 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1448 base
== reg
? 0 : reg
);
1452 if (GET_CODE (orig
) == CONST_INT
)
1453 return plus_constant (base
, INTVAL (orig
));
1454 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1455 /* Likewise, should we set special REG_NOTEs here? */
1461 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1463 static CONST_METHOD
const_method (rtx
);
1465 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1468 const_method (rtx constant
)
1473 i
= INTVAL (constant
);
1477 /* The ColdFire doesn't have byte or word operations. */
1478 /* FIXME: This may not be useful for the m68060 either. */
1479 if (!TARGET_COLDFIRE
)
1481 /* if -256 < N < 256 but N is not in range for a moveq
1482 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1483 if (USE_MOVQ (i
^ 0xff))
1485 /* Likewise, try with not.w */
1486 if (USE_MOVQ (i
^ 0xffff))
1488 /* This is the only value where neg.w is useful */
1491 /* Try also with swap */
1493 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1496 /* Otherwise, use move.l */
1501 const_int_cost (rtx constant
)
1503 switch (const_method (constant
))
1506 /* Constants between -128 and 127 are cheap due to moveq */
1512 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1522 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1527 /* Constant zero is super cheap due to clr instruction. */
1528 if (x
== const0_rtx
)
1531 *total
= const_int_cost (x
);
1541 /* Make 0.0 cheaper than other floating constants to
1542 encourage creating tstsf and tstdf insns. */
1543 if (outer_code
== COMPARE
1544 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1550 /* These are vaguely right for a 68020. */
1551 /* The costs for long multiply have been adjusted to work properly
1552 in synth_mult on the 68020, relative to an average of the time
1553 for add and the time for shift, taking away a little more because
1554 sometimes move insns are needed. */
1555 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1556 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1557 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1558 TARGET_CFV3 ? 2 : 5)
1559 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1562 /* An lea costs about three times as much as a simple add. */
1563 if (GET_MODE (x
) == SImode
1564 && GET_CODE (XEXP (x
, 1)) == REG
1565 && GET_CODE (XEXP (x
, 0)) == MULT
1566 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1567 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1568 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1569 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1570 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1572 /* lea an@(dx:l:i),am */
1573 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1583 *total
= COSTS_N_INSNS(1);
1586 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1588 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1590 if (INTVAL (XEXP (x
, 1)) < 16)
1591 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1593 /* We're using clrw + swap for these cases. */
1594 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1597 *total
= COSTS_N_INSNS (10); /* worst case */
1600 /* A shift by a big integer takes an extra instruction. */
1601 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1602 && (INTVAL (XEXP (x
, 1)) == 16))
1604 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1607 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1608 && !(INTVAL (XEXP (x
, 1)) > 0
1609 && INTVAL (XEXP (x
, 1)) <= 8))
1611 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1617 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1618 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1619 && GET_MODE (x
) == SImode
)
1620 *total
= COSTS_N_INSNS (MULW_COST
);
1621 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1622 *total
= COSTS_N_INSNS (MULW_COST
);
1624 *total
= COSTS_N_INSNS (MULL_COST
);
1631 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1632 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1633 else if (TARGET_CF_HWDIV
)
1634 *total
= COSTS_N_INSNS (18);
1636 *total
= COSTS_N_INSNS (43); /* div.l */
1645 output_move_const_into_data_reg (rtx
*operands
)
1649 i
= INTVAL (operands
[1]);
1650 switch (const_method (operands
[1]))
1653 return "moveq %1,%0";
1656 operands
[1] = GEN_INT (i
^ 0xff);
1657 return "moveq %1,%0\n\tnot%.b %0";
1660 operands
[1] = GEN_INT (i
^ 0xffff);
1661 return "moveq %1,%0\n\tnot%.w %0";
1664 return "moveq #-128,%0\n\tneg%.w %0";
1669 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1670 return "moveq %1,%0\n\tswap %0";
1673 return "move%.l %1,%0";
1680 output_move_simode_const (rtx
*operands
)
1682 if (operands
[1] == const0_rtx
1683 && (DATA_REG_P (operands
[0])
1684 || GET_CODE (operands
[0]) == MEM
)
1685 /* clr insns on 68000 read before writing.
1686 This isn't so on the 68010, but we have no TARGET_68010. */
1687 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1688 || !(GET_CODE (operands
[0]) == MEM
1689 && MEM_VOLATILE_P (operands
[0]))))
1691 else if (operands
[1] == const0_rtx
1692 && ADDRESS_REG_P (operands
[0]))
1693 return "sub%.l %0,%0";
1694 else if (DATA_REG_P (operands
[0]))
1695 return output_move_const_into_data_reg (operands
);
1696 else if (ADDRESS_REG_P (operands
[0])
1697 && INTVAL (operands
[1]) < 0x8000
1698 && INTVAL (operands
[1]) >= -0x8000)
1699 return "move%.w %1,%0";
1700 else if (GET_CODE (operands
[0]) == MEM
1701 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1702 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1703 && INTVAL (operands
[1]) < 0x8000
1704 && INTVAL (operands
[1]) >= -0x8000)
1706 return "move%.l %1,%0";
1710 output_move_simode (rtx
*operands
)
1712 if (GET_CODE (operands
[1]) == CONST_INT
)
1713 return output_move_simode_const (operands
);
1714 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1715 || GET_CODE (operands
[1]) == CONST
)
1716 && push_operand (operands
[0], SImode
))
1718 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1719 || GET_CODE (operands
[1]) == CONST
)
1720 && ADDRESS_REG_P (operands
[0]))
1721 return "lea %a1,%0";
1722 return "move%.l %1,%0";
1726 output_move_himode (rtx
*operands
)
1728 if (GET_CODE (operands
[1]) == CONST_INT
)
1730 if (operands
[1] == const0_rtx
1731 && (DATA_REG_P (operands
[0])
1732 || GET_CODE (operands
[0]) == MEM
)
1733 /* clr insns on 68000 read before writing.
1734 This isn't so on the 68010, but we have no TARGET_68010. */
1735 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1736 || !(GET_CODE (operands
[0]) == MEM
1737 && MEM_VOLATILE_P (operands
[0]))))
1739 else if (operands
[1] == const0_rtx
1740 && ADDRESS_REG_P (operands
[0]))
1741 return "sub%.l %0,%0";
1742 else if (DATA_REG_P (operands
[0])
1743 && INTVAL (operands
[1]) < 128
1744 && INTVAL (operands
[1]) >= -128)
1746 return "moveq %1,%0";
1748 else if (INTVAL (operands
[1]) < 0x8000
1749 && INTVAL (operands
[1]) >= -0x8000)
1750 return "move%.w %1,%0";
1752 else if (CONSTANT_P (operands
[1]))
1753 return "move%.l %1,%0";
1754 /* Recognize the insn before a tablejump, one that refers
1755 to a table of offsets. Such an insn will need to refer
1756 to a label on the insn. So output one. Use the label-number
1757 of the table of offsets to generate this label. This code,
1758 and similar code below, assumes that there will be at most one
1759 reference to each table. */
1760 if (GET_CODE (operands
[1]) == MEM
1761 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1762 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1763 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1765 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1767 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1768 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1770 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1771 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1773 return "move%.w %1,%0";
1777 output_move_qimode (rtx
*operands
)
1781 /* This is probably useless, since it loses for pushing a struct
1782 of several bytes a byte at a time. */
1783 /* 68k family always modifies the stack pointer by at least 2, even for
1784 byte pushes. The 5200 (ColdFire) does not do this. */
1785 if (GET_CODE (operands
[0]) == MEM
1786 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1787 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1788 && ! ADDRESS_REG_P (operands
[1])
1789 && ! TARGET_COLDFIRE
)
1791 xoperands
[1] = operands
[1];
1793 = gen_rtx_MEM (QImode
,
1794 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1795 /* Just pushing a byte puts it in the high byte of the halfword. */
1796 /* We must put it in the low-order, high-numbered byte. */
1797 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1799 xoperands
[3] = stack_pointer_rtx
;
1800 output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands
);
1803 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1807 /* clr and st insns on 68000 read before writing.
1808 This isn't so on the 68010, but we have no TARGET_68010. */
1809 if (!ADDRESS_REG_P (operands
[0])
1810 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1811 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1813 if (operands
[1] == const0_rtx
)
1815 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1816 && GET_CODE (operands
[1]) == CONST_INT
1817 && (INTVAL (operands
[1]) & 255) == 255)
1823 if (GET_CODE (operands
[1]) == CONST_INT
1824 && DATA_REG_P (operands
[0])
1825 && INTVAL (operands
[1]) < 128
1826 && INTVAL (operands
[1]) >= -128)
1828 return "moveq %1,%0";
1830 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1831 return "sub%.l %0,%0";
1832 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1833 return "move%.l %1,%0";
1834 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1835 from address registers. */
1836 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1837 return "move%.w %1,%0";
1838 return "move%.b %1,%0";
1842 output_move_stricthi (rtx
*operands
)
1844 if (operands
[1] == const0_rtx
1845 /* clr insns on 68000 read before writing.
1846 This isn't so on the 68010, but we have no TARGET_68010. */
1847 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1848 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1850 return "move%.w %1,%0";
1854 output_move_strictqi (rtx
*operands
)
1856 if (operands
[1] == const0_rtx
1857 /* clr insns on 68000 read before writing.
1858 This isn't so on the 68010, but we have no TARGET_68010. */
1859 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1860 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1862 return "move%.b %1,%0";
1865 /* Return the best assembler insn template
1866 for moving operands[1] into operands[0] as a fullword. */
1869 singlemove_string (rtx
*operands
)
1871 if (GET_CODE (operands
[1]) == CONST_INT
)
1872 return output_move_simode_const (operands
);
1873 return "move%.l %1,%0";
1877 /* Output assembler code to perform a doubleword move insn
1878 with operands OPERANDS. */
1881 output_move_double (rtx
*operands
)
1885 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1890 rtx addreg0
= 0, addreg1
= 0;
1891 int dest_overlapped_low
= 0;
1892 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1897 /* First classify both operands. */
1899 if (REG_P (operands
[0]))
1901 else if (offsettable_memref_p (operands
[0]))
1903 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1905 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1907 else if (GET_CODE (operands
[0]) == MEM
)
1912 if (REG_P (operands
[1]))
1914 else if (CONSTANT_P (operands
[1]))
1916 else if (offsettable_memref_p (operands
[1]))
1918 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1920 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1922 else if (GET_CODE (operands
[1]) == MEM
)
1927 /* Check for the cases that the operand constraints are not
1928 supposed to allow to happen. Abort if we get one,
1929 because generating code for these cases is painful. */
1931 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1934 /* If one operand is decrementing and one is incrementing
1935 decrement the former register explicitly
1936 and change that operand into ordinary indexing. */
1938 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1940 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1942 output_asm_insn ("sub%.l #12,%0", operands
);
1944 output_asm_insn ("subq%.l #8,%0", operands
);
1945 if (GET_MODE (operands
[1]) == XFmode
)
1946 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1947 else if (GET_MODE (operands
[0]) == DFmode
)
1948 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1950 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1953 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1955 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1957 output_asm_insn ("sub%.l #12,%1", operands
);
1959 output_asm_insn ("subq%.l #8,%1", operands
);
1960 if (GET_MODE (operands
[1]) == XFmode
)
1961 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1962 else if (GET_MODE (operands
[1]) == DFmode
)
1963 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1965 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1969 /* If an operand is an unoffsettable memory ref, find a register
1970 we can increment temporarily to make it refer to the second word. */
1972 if (optype0
== MEMOP
)
1973 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1975 if (optype1
== MEMOP
)
1976 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1978 /* Ok, we can do one word at a time.
1979 Normally we do the low-numbered word first,
1980 but if either operand is autodecrementing then we
1981 do the high-numbered word first.
1983 In either case, set up in LATEHALF the operands to use
1984 for the high-numbered word and in some cases alter the
1985 operands in OPERANDS to be suitable for the low-numbered word. */
1989 if (optype0
== REGOP
)
1991 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1992 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1994 else if (optype0
== OFFSOP
)
1996 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
1997 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2001 middlehalf
[0] = operands
[0];
2002 latehalf
[0] = operands
[0];
2005 if (optype1
== REGOP
)
2007 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2008 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2010 else if (optype1
== OFFSOP
)
2012 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2013 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2015 else if (optype1
== CNSTOP
)
2017 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2022 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2023 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2024 operands
[1] = GEN_INT (l
[0]);
2025 middlehalf
[1] = GEN_INT (l
[1]);
2026 latehalf
[1] = GEN_INT (l
[2]);
2028 else if (CONSTANT_P (operands
[1]))
2030 /* actually, no non-CONST_DOUBLE constant should ever
2033 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2034 latehalf
[1] = constm1_rtx
;
2036 latehalf
[1] = const0_rtx
;
2041 middlehalf
[1] = operands
[1];
2042 latehalf
[1] = operands
[1];
2046 /* size is not 12: */
2048 if (optype0
== REGOP
)
2049 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2050 else if (optype0
== OFFSOP
)
2051 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2053 latehalf
[0] = operands
[0];
2055 if (optype1
== REGOP
)
2056 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2057 else if (optype1
== OFFSOP
)
2058 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2059 else if (optype1
== CNSTOP
)
2060 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2062 latehalf
[1] = operands
[1];
2065 /* If insn is effectively movd N(sp),-(sp) then we will do the
2066 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2067 for the low word as well, to compensate for the first decrement of sp. */
2068 if (optype0
== PUSHOP
2069 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2070 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2071 operands
[1] = middlehalf
[1] = latehalf
[1];
2073 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2074 if the upper part of reg N does not appear in the MEM, arrange to
2075 emit the move late-half first. Otherwise, compute the MEM address
2076 into the upper part of N and use that as a pointer to the memory
2078 if (optype0
== REGOP
2079 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2081 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2083 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2084 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2086 /* If both halves of dest are used in the src memory address,
2087 compute the address into latehalf of dest.
2088 Note that this can't happen if the dest is two data regs. */
2090 xops
[0] = latehalf
[0];
2091 xops
[1] = XEXP (operands
[1], 0);
2092 output_asm_insn ("lea %a1,%0", xops
);
2093 if (GET_MODE (operands
[1]) == XFmode
)
2095 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2096 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2097 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2101 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2102 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2106 && reg_overlap_mentioned_p (middlehalf
[0],
2107 XEXP (operands
[1], 0)))
2109 /* Check for two regs used by both source and dest.
2110 Note that this can't happen if the dest is all data regs.
2111 It can happen if the dest is d6, d7, a0.
2112 But in that case, latehalf is an addr reg, so
2113 the code at compadr does ok. */
2115 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2116 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2119 /* JRV says this can't happen: */
2120 if (addreg0
|| addreg1
)
2123 /* Only the middle reg conflicts; simply put it last. */
2124 output_asm_insn (singlemove_string (operands
), operands
);
2125 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2126 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2129 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2130 /* If the low half of dest is mentioned in the source memory
2131 address, the arrange to emit the move late half first. */
2132 dest_overlapped_low
= 1;
2135 /* If one or both operands autodecrementing,
2136 do the two words, high-numbered first. */
2138 /* Likewise, the first move would clobber the source of the second one,
2139 do them in the other order. This happens only for registers;
2140 such overlap can't happen in memory unless the user explicitly
2141 sets it up, and that is an undefined circumstance. */
2143 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2144 || (optype0
== REGOP
&& optype1
== REGOP
2145 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2146 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2147 || dest_overlapped_low
)
2149 /* Make any unoffsettable addresses point at high-numbered word. */
2153 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2155 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2160 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2162 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2166 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2168 /* Undo the adds we just did. */
2170 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2172 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2176 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2178 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2180 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2183 /* Do low-numbered word. */
2184 return singlemove_string (operands
);
2187 /* Normal case: do the two words, low-numbered first. */
2189 output_asm_insn (singlemove_string (operands
), operands
);
2191 /* Do the middle one of the three words for long double */
2195 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2197 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2199 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2202 /* Make any unoffsettable addresses point at high-numbered word. */
2204 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2206 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2209 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2211 /* Undo the adds we just did. */
2215 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2217 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2222 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2224 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2230 /* Return a REG that occurs in ADDR with coefficient 1.
2231 ADDR can be effectively incremented by incrementing REG. */
2234 find_addr_reg (rtx addr
)
2236 while (GET_CODE (addr
) == PLUS
)
2238 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2239 addr
= XEXP (addr
, 0);
2240 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2241 addr
= XEXP (addr
, 1);
2242 else if (CONSTANT_P (XEXP (addr
, 0)))
2243 addr
= XEXP (addr
, 1);
2244 else if (CONSTANT_P (XEXP (addr
, 1)))
2245 addr
= XEXP (addr
, 0);
2249 if (GET_CODE (addr
) == REG
)
2254 /* Output assembler code to perform a 32-bit 3-operand add. */
2257 output_addsi3 (rtx
*operands
)
2259 if (! operands_match_p (operands
[0], operands
[1]))
2261 if (!ADDRESS_REG_P (operands
[1]))
2263 rtx tmp
= operands
[1];
2265 operands
[1] = operands
[2];
2269 /* These insns can result from reloads to access
2270 stack slots over 64k from the frame pointer. */
2271 if (GET_CODE (operands
[2]) == CONST_INT
2272 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2273 return "move%.l %2,%0\n\tadd%.l %1,%0";
2274 if (GET_CODE (operands
[2]) == REG
)
2275 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2276 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2278 if (GET_CODE (operands
[2]) == CONST_INT
)
2280 if (INTVAL (operands
[2]) > 0
2281 && INTVAL (operands
[2]) <= 8)
2282 return "addq%.l %2,%0";
2283 if (INTVAL (operands
[2]) < 0
2284 && INTVAL (operands
[2]) >= -8)
2286 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2287 return "subq%.l %2,%0";
2289 /* On the CPU32 it is faster to use two addql instructions to
2290 add a small integer (8 < N <= 16) to a register.
2291 Likewise for subql. */
2292 if (TARGET_CPU32
&& REG_P (operands
[0]))
2294 if (INTVAL (operands
[2]) > 8
2295 && INTVAL (operands
[2]) <= 16)
2297 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2298 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2300 if (INTVAL (operands
[2]) < -8
2301 && INTVAL (operands
[2]) >= -16)
2303 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2304 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2307 if (ADDRESS_REG_P (operands
[0])
2308 && INTVAL (operands
[2]) >= -0x8000
2309 && INTVAL (operands
[2]) < 0x8000)
2312 return "add%.w %2,%0";
2314 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2317 return "add%.l %2,%0";
2320 /* Store in cc_status the expressions that the condition codes will
2321 describe after execution of an instruction whose pattern is EXP.
2322 Do not alter them if the instruction would not alter the cc's. */
2324 /* On the 68000, all the insns to store in an address register fail to
2325 set the cc's. However, in some cases these instructions can make it
2326 possibly invalid to use the saved cc's. In those cases we clear out
2327 some or all of the saved cc's so they won't be used. */
2330 notice_update_cc (rtx exp
, rtx insn
)
2332 if (GET_CODE (exp
) == SET
)
2334 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2338 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2340 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2341 cc_status
.value1
= 0;
2342 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2343 cc_status
.value2
= 0;
2345 else if (!FP_REG_P (SET_DEST (exp
))
2346 && SET_DEST (exp
) != cc0_rtx
2347 && (FP_REG_P (SET_SRC (exp
))
2348 || GET_CODE (SET_SRC (exp
)) == FIX
2349 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2350 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2354 /* A pair of move insns doesn't produce a useful overall cc. */
2355 else if (!FP_REG_P (SET_DEST (exp
))
2356 && !FP_REG_P (SET_SRC (exp
))
2357 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2358 && (GET_CODE (SET_SRC (exp
)) == REG
2359 || GET_CODE (SET_SRC (exp
)) == MEM
2360 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2364 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2368 else if (XEXP (exp
, 0) != pc_rtx
)
2370 cc_status
.flags
= 0;
2371 cc_status
.value1
= XEXP (exp
, 0);
2372 cc_status
.value2
= XEXP (exp
, 1);
2375 else if (GET_CODE (exp
) == PARALLEL
2376 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2378 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2380 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2382 cc_status
.flags
= 0;
2383 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2384 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2389 if (cc_status
.value2
!= 0
2390 && ADDRESS_REG_P (cc_status
.value2
)
2391 && GET_MODE (cc_status
.value2
) == QImode
)
2393 if (cc_status
.value2
!= 0)
2394 switch (GET_CODE (cc_status
.value2
))
2396 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2397 case ROTATE
: case ROTATERT
:
2398 /* These instructions always clear the overflow bit, and set
2399 the carry to the bit shifted out. */
2400 /* ??? We don't currently have a way to signal carry not valid,
2401 nor do we check for it in the branch insns. */
2405 case PLUS
: case MINUS
: case MULT
:
2406 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2407 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2408 cc_status
.flags
|= CC_NO_OVERFLOW
;
2411 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2412 ends with a move insn moving r2 in r2's mode.
2413 Thus, the cc's are set for r2.
2414 This can set N bit spuriously. */
2415 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2420 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2422 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2423 cc_status
.value2
= 0;
2424 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2425 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2426 cc_status
.flags
= CC_IN_68881
;
2430 output_move_const_double (rtx
*operands
)
2432 int code
= standard_68881_constant_p (operands
[1]);
2436 static char buf
[40];
2438 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2441 return "fmove%.d %1,%0";
2445 output_move_const_single (rtx
*operands
)
2447 int code
= standard_68881_constant_p (operands
[1]);
2451 static char buf
[40];
2453 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2456 return "fmove%.s %f1,%0";
2459 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2460 from the "fmovecr" instruction.
2461 The value, anded with 0xff, gives the code to use in fmovecr
2462 to get the desired constant. */
2464 /* This code has been fixed for cross-compilation. */
2466 static int inited_68881_table
= 0;
2468 static const char *const strings_68881
[7] = {
2478 static const int codes_68881
[7] = {
2488 REAL_VALUE_TYPE values_68881
[7];
2490 /* Set up values_68881 array by converting the decimal values
2491 strings_68881 to binary. */
2494 init_68881_table (void)
2498 enum machine_mode mode
;
2501 for (i
= 0; i
< 7; i
++)
2505 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2506 values_68881
[i
] = r
;
2508 inited_68881_table
= 1;
2512 standard_68881_constant_p (rtx x
)
2517 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2518 used at all on those chips. */
2519 if (TARGET_68040
|| TARGET_68060
)
2522 if (! inited_68881_table
)
2523 init_68881_table ();
2525 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2527 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2529 for (i
= 0; i
< 6; i
++)
2531 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2532 return (codes_68881
[i
]);
2535 if (GET_MODE (x
) == SFmode
)
2538 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2539 return (codes_68881
[6]);
2541 /* larger powers of ten in the constants ram are not used
2542 because they are not equal to a `double' C constant. */
2546 /* If X is a floating-point constant, return the logarithm of X base 2,
2547 or 0 if X is not a power of 2. */
2550 floating_exact_log2 (rtx x
)
2552 REAL_VALUE_TYPE r
, r1
;
2555 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2557 if (REAL_VALUES_LESS (r
, dconst1
))
2560 exp
= real_exponent (&r
);
2561 real_2expN (&r1
, exp
);
2562 if (REAL_VALUES_EQUAL (r1
, r
))
2568 /* A C compound statement to output to stdio stream STREAM the
2569 assembler syntax for an instruction operand X. X is an RTL
2572 CODE is a value that can be used to specify one of several ways
2573 of printing the operand. It is used when identical operands
2574 must be printed differently depending on the context. CODE
2575 comes from the `%' specification that was used to request
2576 printing of the operand. If the specification was just `%DIGIT'
2577 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2578 is the ASCII code for LTR.
2580 If X is a register, this macro should print the register's name.
2581 The names can be found in an array `reg_names' whose type is
2582 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2584 When the machine description has a specification `%PUNCT' (a `%'
2585 followed by a punctuation character), this macro is called with
2586 a null pointer for X and the punctuation character for CODE.
2588 The m68k specific codes are:
2590 '.' for dot needed in Motorola-style opcode names.
2591 '-' for an operand pushing on the stack:
2592 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2593 '+' for an operand pushing on the stack:
2594 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2595 '@' for a reference to the top word on the stack:
2596 sp@, (sp) or (%sp) depending on the style of syntax.
2597 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2598 but & in SGS syntax).
2599 '!' for the cc register (used in an `and to cc' insn).
2600 '$' for the letter `s' in an op code, but only on the 68040.
2601 '&' for the letter `d' in an op code, but only on the 68040.
2602 '/' for register prefix needed by longlong.h.
2604 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2605 'd' to force memory addressing to be absolute, not relative.
2606 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2607 'o' for operands to go directly to output_operand_address (bypassing
2608 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2609 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2610 or print pair of registers as rx:ry.
2615 print_operand (FILE *file
, rtx op
, int letter
)
2620 fprintf (file
, ".");
2622 else if (letter
== '#')
2623 asm_fprintf (file
, "%I");
2624 else if (letter
== '-')
2625 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2626 else if (letter
== '+')
2627 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2628 else if (letter
== '@')
2629 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2630 else if (letter
== '!')
2631 asm_fprintf (file
, "%Rfpcr");
2632 else if (letter
== '$')
2634 if (TARGET_68040_ONLY
)
2635 fprintf (file
, "s");
2637 else if (letter
== '&')
2639 if (TARGET_68040_ONLY
)
2640 fprintf (file
, "d");
2642 else if (letter
== '/')
2643 asm_fprintf (file
, "%R");
2644 else if (letter
== 'o')
2646 /* This is only for direct addresses with TARGET_PCREL */
2647 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2650 output_addr_const (file
, XEXP (op
, 0));
2652 else if (GET_CODE (op
) == REG
)
2655 /* Print out the second register name of a register pair.
2656 I.e., R (6) => 7. */
2657 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2659 fputs (M68K_REGNAME(REGNO (op
)), file
);
2661 else if (GET_CODE (op
) == MEM
)
2663 output_address (XEXP (op
, 0));
2664 if (letter
== 'd' && ! TARGET_68020
2665 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2666 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2667 && INTVAL (XEXP (op
, 0)) < 0x8000
2668 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2669 fprintf (file
, MOTOROLA
? ".l" : ":l");
2671 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2674 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2675 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2677 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2680 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2681 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2683 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2686 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2687 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2691 /* Use `print_operand_address' instead of `output_addr_const'
2692 to ensure that we print relevant PIC stuff. */
2693 asm_fprintf (file
, "%I");
2695 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2696 print_operand_address (file
, op
);
2698 output_addr_const (file
, op
);
2703 /* A C compound statement to output to stdio stream STREAM the
2704 assembler syntax for an instruction operand that is a memory
2705 reference whose address is ADDR. ADDR is an RTL expression.
2707 Note that this contains a kludge that knows that the only reason
2708 we have an address (plus (label_ref...) (reg...)) when not generating
2709 PIC code is in the insn before a tablejump, and we know that m68k.md
2710 generates a label LInnn: on such an insn.
2712 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2713 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2715 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2716 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2717 we want. This difference can be accommodated by using an assembler
2718 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2719 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2720 macro. See m68k/sgs.h for an example; for versions without the bug.
2721 Some assemblers refuse all the above solutions. The workaround is to
2722 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2725 They also do not like things like "pea 1.w", so we simple leave off
2726 the .w on small constants.
2728 This routine is responsible for distinguishing between -fpic and -fPIC
2729 style relocations in an address. When generating -fpic code the
2730 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2731 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2734 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2735 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2736 #else /* !MOTOROLA */
2737 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2738 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2739 #endif /* !MOTOROLA */
2742 print_operand_address (FILE *file
, rtx addr
)
2744 register rtx reg1
, reg2
, breg
, ireg
;
2747 switch (GET_CODE (addr
))
2750 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2753 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2754 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2757 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2758 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2761 reg1
= reg2
= ireg
= breg
= offset
= 0;
2762 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2764 offset
= XEXP (addr
, 0);
2765 addr
= XEXP (addr
, 1);
2767 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2769 offset
= XEXP (addr
, 1);
2770 addr
= XEXP (addr
, 0);
2772 if (GET_CODE (addr
) != PLUS
)
2776 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2778 reg1
= XEXP (addr
, 0);
2779 addr
= XEXP (addr
, 1);
2781 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2783 reg1
= XEXP (addr
, 1);
2784 addr
= XEXP (addr
, 0);
2786 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2788 reg1
= XEXP (addr
, 0);
2789 addr
= XEXP (addr
, 1);
2791 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2793 reg1
= XEXP (addr
, 1);
2794 addr
= XEXP (addr
, 0);
2796 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2798 reg1
= XEXP (addr
, 0);
2799 addr
= XEXP (addr
, 1);
2801 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2803 reg1
= XEXP (addr
, 1);
2804 addr
= XEXP (addr
, 0);
2806 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2807 || GET_CODE (addr
) == SIGN_EXTEND
)
2819 #if 0 /* for OLD_INDEXING */
2820 else if (GET_CODE (addr
) == PLUS
)
2822 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2824 reg2
= XEXP (addr
, 0);
2825 addr
= XEXP (addr
, 1);
2827 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2829 reg2
= XEXP (addr
, 1);
2830 addr
= XEXP (addr
, 0);
2842 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2843 || GET_CODE (reg1
) == MULT
))
2844 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2849 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2854 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2855 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2858 if (GET_CODE (ireg
) == MULT
)
2860 scale
= INTVAL (XEXP (ireg
, 1));
2861 ireg
= XEXP (ireg
, 0);
2863 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2865 ASM_OUTPUT_CASE_FETCH (file
,
2866 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2867 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2868 fprintf (file
, "w");
2872 ASM_OUTPUT_CASE_FETCH (file
,
2873 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2874 M68K_REGNAME(REGNO (ireg
)));
2875 fprintf (file
, "l");
2878 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2882 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2883 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2885 ASM_OUTPUT_CASE_FETCH (file
,
2886 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2887 M68K_REGNAME(REGNO (breg
)));
2888 fprintf (file
, "l)");
2891 if (ireg
!= 0 || breg
!= 0)
2898 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2906 output_addr_const (file
, addr
);
2907 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2909 fprintf (file
, "@GOT");
2911 fprintf (file
, ".w");
2914 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2918 else /* !MOTOROLA */
2920 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2923 output_addr_const (file
, addr
);
2924 if (breg
== pic_offset_table_rtx
)
2928 fprintf (file
, ":w"); break;
2930 fprintf (file
, ":l"); break;
2938 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2940 scale
= INTVAL (XEXP (ireg
, 1));
2941 ireg
= XEXP (ireg
, 0);
2943 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2944 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2945 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2947 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2948 M68K_REGNAME(REGNO (ireg
)));
2950 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2954 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2955 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2957 ASM_OUTPUT_CASE_FETCH (file
,
2958 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2959 M68K_REGNAME(REGNO (reg1
)));
2960 fprintf (file
, "l)");
2963 /* FALL-THROUGH (is this really what we want?) */
2965 if (GET_CODE (addr
) == CONST_INT
2966 && INTVAL (addr
) < 0x8000
2967 && INTVAL (addr
) >= -0x8000)
2969 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2971 else if (GET_CODE (addr
) == CONST_INT
)
2973 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2975 else if (TARGET_PCREL
)
2978 output_addr_const (file
, addr
);
2980 asm_fprintf (file
, ":w,%Rpc)");
2982 asm_fprintf (file
, ":l,%Rpc)");
2986 /* Special case for SYMBOL_REF if the symbol name ends in
2987 `.<letter>', this can be mistaken as a size suffix. Put
2988 the name in parentheses. */
2989 if (GET_CODE (addr
) == SYMBOL_REF
2990 && strlen (XSTR (addr
, 0)) > 2
2991 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
2994 output_addr_const (file
, addr
);
2998 output_addr_const (file
, addr
);
3004 /* Check for cases where a clr insns can be omitted from code using
3005 strict_low_part sets. For example, the second clrl here is not needed:
3006 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3008 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3009 insn we are checking for redundancy. TARGET is the register set by the
3013 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3018 p
= prev_nonnote_insn (first_insn
);
3022 /* If it isn't an insn, then give up. */
3023 if (GET_CODE (p
) != INSN
)
3026 if (reg_set_p (target
, p
))
3028 rtx set
= single_set (p
);
3031 /* If it isn't an easy to recognize insn, then give up. */
3035 dest
= SET_DEST (set
);
3037 /* If this sets the entire target register to zero, then our
3038 first_insn is redundant. */
3039 if (rtx_equal_p (dest
, target
)
3040 && SET_SRC (set
) == const0_rtx
)
3042 else if (GET_CODE (dest
) == STRICT_LOW_PART
3043 && GET_CODE (XEXP (dest
, 0)) == REG
3044 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3045 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3046 <= GET_MODE_SIZE (mode
)))
3047 /* This is a strict low part set which modifies less than
3048 we are using, so it is safe. */
3054 p
= prev_nonnote_insn (p
);
3060 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3061 range carefully since this predicate is used in DImode contexts. Also, we
3062 need some extra crud to make it work when hosted on 64-bit machines. */
3065 const_uint32_operand (rtx op
, enum machine_mode mode
)
3067 /* It doesn't make sense to ask this question with a mode that is
3068 not larger than 32 bits. */
3069 if (GET_MODE_BITSIZE (mode
) <= 32)
3072 #if HOST_BITS_PER_WIDE_INT > 32
3073 /* All allowed constants will fit a CONST_INT. */
3074 return (GET_CODE (op
) == CONST_INT
3075 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3077 return (GET_CODE (op
) == CONST_INT
3078 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3082 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3083 to check the range carefully since this predicate is used in DImode
3087 const_sint32_operand (rtx op
, enum machine_mode mode
)
3089 /* It doesn't make sense to ask this question with a mode that is
3090 not larger than 32 bits. */
3091 if (GET_MODE_BITSIZE (mode
) <= 32)
3094 /* All allowed constants will fit a CONST_INT. */
3095 return (GET_CODE (op
) == CONST_INT
3096 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3099 /* Operand predicates for implementing asymmetric pc-relative addressing
3100 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3101 when used as a source operand, but not as a destination operand.
3103 We model this by restricting the meaning of the basic predicates
3104 (general_operand, memory_operand, etc) to forbid the use of this
3105 addressing mode, and then define the following predicates that permit
3106 this addressing mode. These predicates can then be used for the
3107 source operands of the appropriate instructions.
3109 n.b. While it is theoretically possible to change all machine patterns
3110 to use this addressing more where permitted by the architecture,
3111 it has only been implemented for "common" cases: SImode, HImode, and
3112 QImode operands, and only for the principle operations that would
3113 require this addressing mode: data movement and simple integer operations.
3115 In parallel with these new predicates, two new constraint letters
3116 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3117 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3118 In the pcrel case 's' is only valid in combination with 'a' registers.
3119 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3120 of how these constraints are used.
3122 The use of these predicates is strictly optional, though patterns that
3123 don't will cause an extra reload register to be allocated where one
3126 lea (abc:w,%pc),%a0 ; need to reload address
3127 moveq &1,%d1 ; since write to pc-relative space
3128 movel %d1,%a0@ ; is not allowed
3130 lea (abc:w,%pc),%a1 ; no need to reload address here
3131 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3133 For more info, consult tiemann@cygnus.com.
3136 All of the ugliness with predicates and constraints is due to the
3137 simple fact that the m68k does not allow a pc-relative addressing
3138 mode as a destination. gcc does not distinguish between source and
3139 destination addresses. Hence, if we claim that pc-relative address
3140 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3141 end up with invalid code. To get around this problem, we left
3142 pc-relative modes as invalid addresses, and then added special
3143 predicates and constraints to accept them.
3145 A cleaner way to handle this is to modify gcc to distinguish
3146 between source and destination addresses. We can then say that
3147 pc-relative is a valid source address but not a valid destination
3148 address, and hopefully avoid a lot of the predicate and constraint
3149 hackery. Unfortunately, this would be a pretty big change. It would
3150 be a useful change for a number of ports, but there aren't any current
3151 plans to undertake this.
3153 ***************************************************************************/
3156 /* Special case of a general operand that's used as a source operand.
3157 Use this to permit reads from PC-relative memory when -mpcrel
3161 general_src_operand (rtx op
, enum machine_mode mode
)
3164 && GET_CODE (op
) == MEM
3165 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3166 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3167 || GET_CODE (XEXP (op
, 0)) == CONST
))
3169 return general_operand (op
, mode
);
3172 /* Special case of a nonimmediate operand that's used as a source.
3173 Use this to permit reads from PC-relative memory when -mpcrel
3177 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3179 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3180 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3181 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3182 || GET_CODE (XEXP (op
, 0)) == CONST
))
3184 return nonimmediate_operand (op
, mode
);
3187 /* Special case of a memory operand that's used as a source.
3188 Use this to permit reads from PC-relative memory when -mpcrel
3192 memory_src_operand (rtx op
, enum machine_mode mode
)
3194 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3195 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3196 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3197 || GET_CODE (XEXP (op
, 0)) == CONST
))
3199 return memory_operand (op
, mode
);
3202 /* Predicate that accepts only a pc-relative address. This is needed
3203 because pc-relative addresses don't satisfy the predicate
3204 "general_src_operand". */
3207 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3209 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3210 || GET_CODE (op
) == CONST
);
3214 output_andsi3 (rtx
*operands
)
3217 if (GET_CODE (operands
[2]) == CONST_INT
3218 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3219 && (DATA_REG_P (operands
[0])
3220 || offsettable_memref_p (operands
[0]))
3221 && !TARGET_COLDFIRE
)
3223 if (GET_CODE (operands
[0]) != REG
)
3224 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3225 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3226 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3228 if (operands
[2] == const0_rtx
)
3230 return "and%.w %2,%0";
3232 if (GET_CODE (operands
[2]) == CONST_INT
3233 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3234 && (DATA_REG_P (operands
[0])
3235 || offsettable_memref_p (operands
[0])))
3237 if (DATA_REG_P (operands
[0]))
3239 operands
[1] = GEN_INT (logval
);
3243 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3244 operands
[1] = GEN_INT (logval
% 8);
3246 /* This does not set condition codes in a standard way. */
3248 return "bclr %1,%0";
3250 return "and%.l %2,%0";
3254 output_iorsi3 (rtx
*operands
)
3256 register int logval
;
3257 if (GET_CODE (operands
[2]) == CONST_INT
3258 && INTVAL (operands
[2]) >> 16 == 0
3259 && (DATA_REG_P (operands
[0])
3260 || offsettable_memref_p (operands
[0]))
3261 && !TARGET_COLDFIRE
)
3263 if (GET_CODE (operands
[0]) != REG
)
3264 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3265 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3267 if (INTVAL (operands
[2]) == 0xffff)
3268 return "mov%.w %2,%0";
3269 return "or%.w %2,%0";
3271 if (GET_CODE (operands
[2]) == CONST_INT
3272 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3273 && (DATA_REG_P (operands
[0])
3274 || offsettable_memref_p (operands
[0])))
3276 if (DATA_REG_P (operands
[0]))
3277 operands
[1] = GEN_INT (logval
);
3280 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3281 operands
[1] = GEN_INT (logval
% 8);
3284 return "bset %1,%0";
3286 return "or%.l %2,%0";
3290 output_xorsi3 (rtx
*operands
)
3292 register int logval
;
3293 if (GET_CODE (operands
[2]) == CONST_INT
3294 && INTVAL (operands
[2]) >> 16 == 0
3295 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3296 && !TARGET_COLDFIRE
)
3298 if (! DATA_REG_P (operands
[0]))
3299 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3300 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3302 if (INTVAL (operands
[2]) == 0xffff)
3304 return "eor%.w %2,%0";
3306 if (GET_CODE (operands
[2]) == CONST_INT
3307 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3308 && (DATA_REG_P (operands
[0])
3309 || offsettable_memref_p (operands
[0])))
3311 if (DATA_REG_P (operands
[0]))
3312 operands
[1] = GEN_INT (logval
);
3315 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3316 operands
[1] = GEN_INT (logval
% 8);
3319 return "bchg %1,%0";
3321 return "eor%.l %2,%0";
3324 #ifdef M68K_TARGET_COFF
3326 /* Output assembly to switch to section NAME with attribute FLAGS. */
3329 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3333 if (flags
& SECTION_WRITE
)
3338 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3341 #endif /* M68K_TARGET_COFF */
3344 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3345 HOST_WIDE_INT delta
,
3346 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3352 if (delta
> 0 && delta
<= 8)
3353 asm_fprintf (file
, MOTOROLA
?
3354 "\taddq.l %I%d,4(%Rsp)\n" :
3355 "\taddql %I%d,%Rsp@(4)\n",
3357 else if (delta
< 0 && delta
>= -8)
3358 asm_fprintf (file
, MOTOROLA
?
3359 "\tsubq.l %I%d,4(%Rsp)\n" :
3360 "\tsubql %I%d,%Rsp@(4)\n",
3363 asm_fprintf (file
, MOTOROLA
?
3364 "\tadd.l %I%wd,4(%Rsp)\n" :
3365 "\taddl %I%wd,%Rsp@(4)\n",
3368 xops
[0] = DECL_RTL (function
);
3370 /* Logic taken from call patterns in m68k.md. */
3375 else if ((flag_pic
== 1) || TARGET_68020
)
3378 #if defined(USE_GAS)
3379 fmt
= "bra.l %0@PLTPC";
3381 fmt
= "bra %0@PLTPC";
3383 else /* !MOTOROLA */
3390 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3391 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3393 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3397 #if MOTOROLA && !defined (USE_GAS)
3404 output_asm_insn (fmt
, xops
);
3407 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3410 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3411 int incoming ATTRIBUTE_UNUSED
)
3413 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);