1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static rtx
find_addr_reg (rtx
);
107 static const char *singlemove_string (rtx
*);
108 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
109 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
110 #ifdef M68K_TARGET_COFF
111 static void m68k_coff_asm_named_section (const char *, unsigned int);
112 #endif /* M68K_TARGET_COFF */
113 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
114 HOST_WIDE_INT
, tree
);
115 static rtx
m68k_struct_value_rtx (tree
, int);
116 static bool m68k_interrupt_function_p (tree func
);
117 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
118 tree args
, int flags
,
120 static void m68k_compute_frame_layout (void);
121 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
122 static int const_int_cost (rtx
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Alignment to use for loops and jumps */
127 /* Specify power of two alignment used for loops. */
128 const char *m68k_align_loops_string
;
129 /* Specify power of two alignment used for non-loop jumps. */
130 const char *m68k_align_jumps_string
;
131 /* Specify power of two alignment used for functions. */
132 const char *m68k_align_funcs_string
;
133 /* Specify the identification number of the library being built */
134 const char *m68k_library_id_string
;
136 /* Specify power of two alignment used for loops. */
137 int m68k_align_loops
;
138 /* Specify power of two alignment used for non-loop jumps. */
139 int m68k_align_jumps
;
140 /* Specify power of two alignment used for functions. */
141 int m68k_align_funcs
;
143 /* Nonzero if the last compare/test insn had FP operands. The
144 sCC expanders peek at this to determine what to do for the
145 68060, which has no fsCC instructions. */
146 int m68k_last_compare_had_fp_operands
;
148 /* Initialize the GCC target structure. */
150 #if INT_OP_GROUP == INT_OP_DOT_WORD
151 #undef TARGET_ASM_ALIGNED_HI_OP
152 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
155 #if INT_OP_GROUP == INT_OP_NO_DOT
156 #undef TARGET_ASM_BYTE_OP
157 #define TARGET_ASM_BYTE_OP "\tbyte\t"
158 #undef TARGET_ASM_ALIGNED_HI_OP
159 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
160 #undef TARGET_ASM_ALIGNED_SI_OP
161 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
164 #if INT_OP_GROUP == INT_OP_DC
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
173 #undef TARGET_ASM_UNALIGNED_HI_OP
174 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
175 #undef TARGET_ASM_UNALIGNED_SI_OP
176 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
183 #undef TARGET_ASM_OUTPUT_MI_THUNK
184 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
185 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
186 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
188 #undef TARGET_ASM_FILE_START_APP_OFF
189 #define TARGET_ASM_FILE_START_APP_OFF true
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS m68k_rtx_costs
194 #undef TARGET_ATTRIBUTE_TABLE
195 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
197 #undef TARGET_PROMOTE_PROTOTYPES
198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
200 #undef TARGET_STRUCT_VALUE_RTX
201 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
203 static const struct attribute_spec m68k_attribute_table
[] =
205 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
206 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
207 { NULL
, 0, 0, false, false, false, NULL
}
210 struct gcc_target targetm
= TARGET_INITIALIZER
;
212 /* Sometimes certain combinations of command options do not make
213 sense on a particular target machine. You can define a macro
214 `OVERRIDE_OPTIONS' to take account of this. This macro, if
215 defined, is executed once just after all the command options have
218 Don't use this macro to turn on various extra optimizations for
219 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
222 override_options (void)
229 /* Validate -malign-loops= value, or provide default */
230 m68k_align_loops
= def_align
;
231 if (m68k_align_loops_string
)
233 i
= atoi (m68k_align_loops_string
);
234 if (i
< 1 || i
> MAX_CODE_ALIGN
)
235 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
237 m68k_align_loops
= i
;
240 /* Library identification */
241 if (m68k_library_id_string
)
245 if (! TARGET_ID_SHARED_LIBRARY
)
246 error ("-mshared-library-id= specified without -mid-shared-library");
247 id
= atoi (m68k_library_id_string
);
248 if (id
< 0 || id
> MAX_LIBRARY_ID
)
249 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
251 /* From now on, m68k_library_id_string will contain the library offset. */
252 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
255 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
257 m68k_library_id_string
= "_current_shared_library_a5_offset_";
259 /* Sanity check to ensure that msep-data and mid-sahred-library are not
260 * both specified together. Doing so simply doesn't make sense.
262 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
263 error ("cannot specify both -msep-data and -mid-shared-library");
265 /* If we're generating code for a separate A5 relative data segment,
266 * we've got to enable -fPIC as well. This might be relaxable to
267 * -fpic but it hasn't been tested properly.
269 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
272 /* Validate -malign-jumps= value, or provide default */
273 m68k_align_jumps
= def_align
;
274 if (m68k_align_jumps_string
)
276 i
= atoi (m68k_align_jumps_string
);
277 if (i
< 1 || i
> MAX_CODE_ALIGN
)
278 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
280 m68k_align_jumps
= i
;
283 /* Validate -malign-functions= value, or provide default */
284 m68k_align_funcs
= def_align
;
285 if (m68k_align_funcs_string
)
287 i
= atoi (m68k_align_funcs_string
);
288 if (i
< 1 || i
> MAX_CODE_ALIGN
)
289 error ("-malign-functions=%d is not between 1 and %d",
292 m68k_align_funcs
= i
;
295 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
297 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
298 error("-fPIC is not currently supported on the 68000 or 68010\n");
300 /* ??? A historic way of turning on pic, or is this intended to
301 be an embedded thing that doesn't have the same name binding
302 significance that it does on hosted ELF systems? */
303 if (TARGET_PCREL
&& flag_pic
== 0)
306 /* Turn off function cse if we are doing PIC. We always want function call
307 to be done as `bsr foo@PLTPC', so it will force the assembler to create
308 the PLT entry for `foo'. Doing function cse will cause the address of
309 `foo' to be loaded into a register, which is exactly what we want to
310 avoid when we are doing PIC on svr4 m68k. */
312 flag_no_function_cse
= 1;
314 SUBTARGET_OVERRIDE_OPTIONS
;
317 /* Return nonzero if FUNC is an interrupt function as specified by the
318 "interrupt_handler" attribute. */
320 m68k_interrupt_function_p(tree func
)
324 if (TREE_CODE (func
) != FUNCTION_DECL
)
327 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
328 return (a
!= NULL_TREE
);
331 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
332 struct attribute_spec.handler. */
334 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
335 tree args ATTRIBUTE_UNUSED
,
336 int flags ATTRIBUTE_UNUSED
,
339 if (TREE_CODE (*node
) != FUNCTION_DECL
)
341 warning ("`%s' attribute only applies to functions",
342 IDENTIFIER_POINTER (name
));
343 *no_add_attrs
= true;
350 m68k_compute_frame_layout (void)
353 unsigned int mask
, rmask
;
354 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
356 /* Only compute the frame once per function.
357 Don't cache information until reload has been completed. */
358 if (current_frame
.funcdef_no
== current_function_funcdef_no
362 current_frame
.size
= (get_frame_size () + 3) & -4;
364 mask
= rmask
= saved
= 0;
365 for (regno
= 0; regno
< 16; regno
++)
366 if (m68k_save_reg (regno
, interrupt_handler
))
369 rmask
|= 1 << (15 - regno
);
372 current_frame
.offset
= saved
* 4;
373 current_frame
.reg_no
= saved
;
374 current_frame
.reg_mask
= mask
;
375 current_frame
.reg_rev_mask
= rmask
;
377 current_frame
.foffset
= 0;
378 mask
= rmask
= saved
= 0;
379 if (TARGET_68881
/* || TARGET_CFV4E */)
381 for (regno
= 16; regno
< 24; regno
++)
382 if (m68k_save_reg (regno
, interrupt_handler
))
384 mask
|= 1 << (regno
- 16);
385 rmask
|= 1 << (23 - regno
);
388 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
389 current_frame
.offset
+= current_frame
.foffset
;
391 current_frame
.fpu_no
= saved
;
392 current_frame
.fpu_mask
= mask
;
393 current_frame
.fpu_rev_mask
= rmask
;
395 /* Remember what function this frame refers to. */
396 current_frame
.funcdef_no
= current_function_funcdef_no
;
400 m68k_initial_elimination_offset (int from
, int to
)
402 /* FIXME: The correct offset to compute here would appear to be
403 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
404 but for some obscure reason, this must be 0 to get correct code. */
405 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
408 m68k_compute_frame_layout ();
410 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
411 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
412 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
413 return current_frame
.offset
+ current_frame
.size
;
418 /* Refer to the array `regs_ever_live' to determine which registers
419 to save; `regs_ever_live[I]' is nonzero if register number I
420 is ever used in the function. This function is responsible for
421 knowing which registers should not be saved even if used.
422 Return true if we need to save REGNO. */
425 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
427 if (flag_pic
&& current_function_uses_pic_offset_table
428 && regno
== PIC_OFFSET_TABLE_REGNUM
)
431 if (current_function_calls_eh_return
)
436 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
437 if (test
== INVALID_REGNUM
)
444 /* Fixed regs we never touch. */
445 if (fixed_regs
[regno
])
448 /* The frame pointer (if it is such) is handled specially. */
449 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
452 /* Interrupt handlers must also save call_used_regs
453 if they are live or when calling nested functions. */
454 if (interrupt_handler
)
456 if (regs_ever_live
[regno
])
459 if (!current_function_is_leaf
&& call_used_regs
[regno
])
463 /* Never need to save registers that aren't touched. */
464 if (!regs_ever_live
[regno
])
467 /* Otherwise save everything that isn't call-clobbered. */
468 return !call_used_regs
[regno
];
471 /* This function generates the assembly code for function entry.
472 STREAM is a stdio stream to output the code to.
473 SIZE is an int: how many units of temporary storage to allocate. */
476 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
478 HOST_WIDE_INT fsize_with_regs
;
479 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
481 m68k_compute_frame_layout();
483 /* If the stack limit is a symbol, we can check it here,
484 before actually allocating the space. */
485 if (current_function_limit_stack
486 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
487 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
488 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
490 /* On ColdFire add register save into initial stack frame setup, if possible. */
491 fsize_with_regs
= current_frame
.size
;
492 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
493 fsize_with_regs
+= current_frame
.reg_no
* 4;
495 if (frame_pointer_needed
)
497 if (current_frame
.size
== 0 && TARGET_68040
)
498 /* on the 68040, pea + move is faster than link.w 0 */
499 fprintf (stream
, MOTOROLA
?
500 "\tpea (%s)\n\tmove.l %s,%s\n" :
501 "\tpea %s@\n\tmovel %s,%s\n",
502 M68K_REGNAME(FRAME_POINTER_REGNUM
),
503 M68K_REGNAME(STACK_POINTER_REGNUM
),
504 M68K_REGNAME(FRAME_POINTER_REGNUM
));
505 else if (fsize_with_regs
< 0x8000)
506 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
507 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
508 else if (TARGET_68020
)
509 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
510 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
512 /* Adding negative number is faster on the 68040. */
513 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
514 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
515 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
517 if (dwarf2out_do_frame ())
520 l
= (char *) dwarf2out_cfi_label ();
522 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
523 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
524 cfa_offset
+= current_frame
.size
;
527 else if (fsize_with_regs
) /* !frame_pointer_needed */
529 if (fsize_with_regs
< 0x8000)
531 if (fsize_with_regs
<= 8)
533 if (!TARGET_COLDFIRE
)
534 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
537 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
540 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
541 /* On the CPU32 it is faster to use two subqw instructions to
542 subtract a small integer (8 < N <= 16) to a register. */
544 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
545 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
546 fsize_with_regs
- 8);
547 else if (TARGET_68040
)
548 /* Adding negative number is faster on the 68040. */
549 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
552 asm_fprintf (stream
, MOTOROLA
?
553 "\tlea (%wd,%Rsp),%Rsp\n" :
554 "\tlea %Rsp@(%wd),%Rsp\n",
557 else /* fsize_with_regs >= 0x8000 */
558 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
560 if (dwarf2out_do_frame ())
562 cfa_offset
+= current_frame
.size
+ 4;
563 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
565 } /* !frame_pointer_needed */
567 if (current_frame
.fpu_mask
)
569 asm_fprintf (stream
, MOTOROLA
?
570 "\tfmovm %I0x%x,-(%Rsp)\n" :
571 "\tfmovem %I0x%x,%Rsp@-\n",
572 current_frame
.fpu_mask
);
574 if (dwarf2out_do_frame ())
576 char *l
= (char *) dwarf2out_cfi_label ();
579 cfa_offset
+= current_frame
.fpu_no
* 12;
580 if (! frame_pointer_needed
)
581 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
582 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
583 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
584 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
588 /* If the stack limit is not a symbol, check it here.
589 This has the disadvantage that it may be too late... */
590 if (current_function_limit_stack
)
592 if (REG_P (stack_limit_rtx
))
593 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
594 M68K_REGNAME(REGNO (stack_limit_rtx
)));
595 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
596 warning ("stack limit expression is not supported");
599 if (current_frame
.reg_no
<= 2)
601 /* Store each separately in the same order moveml uses.
602 Using two movel instructions instead of a single moveml
603 is about 15% faster for the 68020 and 68030 at no expense
608 for (i
= 0; i
< 16; i
++)
609 if (current_frame
.reg_rev_mask
& (1 << i
))
611 asm_fprintf (stream
, MOTOROLA
?
612 "\t%Omove.l %s,-(%Rsp)\n" :
613 "\tmovel %s,%Rsp@-\n",
614 M68K_REGNAME(15 - i
));
615 if (dwarf2out_do_frame ())
617 char *l
= (char *) dwarf2out_cfi_label ();
620 if (! frame_pointer_needed
)
621 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
622 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
626 else if (current_frame
.reg_rev_mask
)
629 /* The ColdFire does not support the predecrement form of the
630 MOVEM instruction, so we must adjust the stack pointer and
631 then use the plain address register indirect mode.
632 The required register save space was combined earlier with
633 the fsize_with_regs amount. */
635 asm_fprintf (stream
, MOTOROLA
?
636 "\tmovm.l %I0x%x,(%Rsp)\n" :
637 "\tmoveml %I0x%x,%Rsp@\n",
638 current_frame
.reg_mask
);
640 asm_fprintf (stream
, MOTOROLA
?
641 "\tmovm.l %I0x%x,-(%Rsp)\n" :
642 "\tmoveml %I0x%x,%Rsp@-\n",
643 current_frame
.reg_rev_mask
);
644 if (dwarf2out_do_frame ())
646 char *l
= (char *) dwarf2out_cfi_label ();
649 cfa_offset
+= current_frame
.reg_no
* 4;
650 if (! frame_pointer_needed
)
651 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
652 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
653 if (current_frame
.reg_mask
& (1 << regno
))
654 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
657 if (!TARGET_SEP_DATA
&& flag_pic
&&
658 (current_function_uses_pic_offset_table
||
659 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
661 if (TARGET_ID_SHARED_LIBRARY
)
663 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
664 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
665 m68k_library_id_string
,
666 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
671 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
672 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
675 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
676 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
677 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
678 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
679 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
685 /* Return true if this function's epilogue can be output as RTL. */
688 use_return_insn (void)
690 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
693 /* We can output the epilogue as RTL only if no registers need to be
695 m68k_compute_frame_layout();
696 return current_frame
.reg_no
? false : true;
699 /* This function generates the assembly code for function exit,
700 on machines that need it.
702 The function epilogue should not depend on the current stack pointer!
703 It should use the frame pointer only, if there is a frame pointer.
704 This is mandatory because of alloca; we also take advantage of it to
705 omit stack adjustments before returning. */
708 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
710 HOST_WIDE_INT fsize
, fsize_with_regs
;
712 bool restore_from_sp
= false;
713 rtx insn
= get_last_insn ();
715 m68k_compute_frame_layout();
717 /* If the last insn was a BARRIER, we don't have to write any code. */
718 if (GET_CODE (insn
) == NOTE
)
719 insn
= prev_nonnote_insn (insn
);
720 if (insn
&& GET_CODE (insn
) == BARRIER
)
722 /* Output just a no-op so that debuggers don't get confused
723 about which function the pc is in at this address. */
724 fprintf (stream
, "\tnop\n");
728 #ifdef FUNCTION_EXTRA_EPILOGUE
729 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
732 fsize
= current_frame
.size
;
734 /* FIXME : leaf_function_p below is too strong.
735 What we really need to know there is if there could be pending
736 stack adjustment needed at that point. */
737 restore_from_sp
= ! frame_pointer_needed
738 || (! current_function_calls_alloca
&& leaf_function_p ());
740 /* fsize_with_regs is the size we need to adjust the sp when
741 popping the frame. */
742 fsize_with_regs
= fsize
;
744 /* Because the ColdFire doesn't support moveml with
745 complex address modes, we must adjust the stack manually
746 after restoring registers. When the frame pointer isn't used,
747 we can merge movem adjustment into frame unlinking
748 made immediately after it. */
749 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
750 fsize_with_regs
+= current_frame
.reg_no
* 4;
752 if (current_frame
.offset
+ fsize
>= 0x8000
754 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
756 /* Because the ColdFire doesn't support moveml with
757 complex address modes we make an extra correction here. */
759 fsize
+= current_frame
.offset
;
761 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
762 fsize
= 0, big
= true;
764 if (current_frame
.reg_no
<= 2)
766 /* Restore each separately in the same order moveml does.
767 Using two movel instructions instead of a single moveml
768 is about 15% faster for the 68020 and 68030 at no expense
772 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
774 for (i
= 0; i
< 16; i
++)
775 if (current_frame
.reg_mask
& (1 << i
))
780 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
782 M68K_REGNAME(FRAME_POINTER_REGNUM
),
785 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
786 M68K_REGNAME(FRAME_POINTER_REGNUM
),
790 else if (restore_from_sp
)
791 asm_fprintf (stream
, MOTOROLA
?
792 "\t%Omove.l (%Rsp)+,%s\n" :
793 "\tmovel %Rsp@+,%s\n",
798 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
800 M68K_REGNAME(FRAME_POINTER_REGNUM
),
803 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
804 M68K_REGNAME(FRAME_POINTER_REGNUM
),
811 else if (current_frame
.reg_mask
)
813 /* The ColdFire requires special handling due to its limited moveml insn. */
818 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
819 M68K_REGNAME(FRAME_POINTER_REGNUM
));
820 asm_fprintf (stream
, MOTOROLA
?
821 "\tmovm.l (%Ra1),%I0x%x\n" :
822 "\tmoveml %Ra1@,%I0x%x\n",
823 current_frame
.reg_mask
);
825 else if (restore_from_sp
)
826 asm_fprintf (stream
, MOTOROLA
?
827 "\tmovm.l (%Rsp),%I0x%x\n" :
828 "\tmoveml %Rsp@,%I0x%x\n",
829 current_frame
.reg_mask
);
833 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
834 current_frame
.offset
+ fsize
,
835 M68K_REGNAME(FRAME_POINTER_REGNUM
),
836 current_frame
.reg_mask
);
838 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.offset
+ fsize
,
841 current_frame
.reg_mask
);
844 else /* !TARGET_COLDFIRE */
849 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
850 current_frame
.offset
+ fsize
,
851 M68K_REGNAME(FRAME_POINTER_REGNUM
),
852 current_frame
.reg_mask
);
854 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
855 M68K_REGNAME(FRAME_POINTER_REGNUM
),
856 current_frame
.offset
+ fsize
,
857 current_frame
.reg_mask
);
859 else if (restore_from_sp
)
861 asm_fprintf (stream
, MOTOROLA
?
862 "\tmovm.l (%Rsp)+,%I0x%x\n" :
863 "\tmoveml %Rsp@+,%I0x%x\n",
864 current_frame
.reg_mask
);
869 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
870 current_frame
.offset
+ fsize
,
871 M68K_REGNAME(FRAME_POINTER_REGNUM
),
872 current_frame
.reg_mask
);
874 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
875 M68K_REGNAME(FRAME_POINTER_REGNUM
),
876 current_frame
.offset
+ fsize
,
877 current_frame
.reg_mask
);
881 if (current_frame
.fpu_rev_mask
)
886 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
887 current_frame
.foffset
+ fsize
,
888 M68K_REGNAME(FRAME_POINTER_REGNUM
),
889 current_frame
.fpu_rev_mask
);
891 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
892 M68K_REGNAME(FRAME_POINTER_REGNUM
),
893 current_frame
.foffset
+ fsize
,
894 current_frame
.fpu_rev_mask
);
896 else if (restore_from_sp
)
899 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
900 current_frame
.fpu_rev_mask
);
902 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
903 current_frame
.fpu_rev_mask
);
908 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
909 current_frame
.foffset
+ fsize
,
910 M68K_REGNAME(FRAME_POINTER_REGNUM
),
911 current_frame
.fpu_rev_mask
);
913 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
914 M68K_REGNAME(FRAME_POINTER_REGNUM
),
915 current_frame
.foffset
+ fsize
,
916 current_frame
.fpu_rev_mask
);
919 if (frame_pointer_needed
)
920 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
921 else if (fsize_with_regs
)
923 if (fsize_with_regs
<= 8)
925 if (!TARGET_COLDFIRE
)
926 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
929 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
932 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
934 /* On the CPU32 it is faster to use two addqw instructions to
935 add a small integer (8 < N <= 16) to a register. */
936 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
937 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
938 fsize_with_regs
- 8);
940 else if (fsize_with_regs
< 0x8000)
943 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
946 asm_fprintf (stream
, MOTOROLA
?
947 "\tlea (%wd,%Rsp),%Rsp\n" :
948 "\tlea %Rsp@(%wd),%Rsp\n",
952 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
954 if (current_function_calls_eh_return
)
955 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
956 if (m68k_interrupt_function_p (current_function_decl
))
957 fprintf (stream
, "\trte\n");
958 else if (current_function_pops_args
)
959 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
961 fprintf (stream
, "\trts\n");
964 /* Similar to general_operand, but exclude stack_pointer_rtx. */
967 not_sp_operand (rtx op
, enum machine_mode mode
)
969 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
972 /* Return true if X is a valid comparison operator for the dbcc
975 Note it rejects floating point comparison operators.
976 (In the future we could use Fdbcc).
978 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
981 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
983 switch (GET_CODE (x
))
985 case EQ
: case NE
: case GTU
: case LTU
:
989 /* Reject some when CC_NO_OVERFLOW is set. This may be over
991 case GT
: case LT
: case GE
: case LE
:
992 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
998 /* Return nonzero if flags are currently in the 68881 flag register. */
1000 flags_in_68881 (void)
1002 /* We could add support for these in the future */
1003 return cc_status
.flags
& CC_IN_68881
;
1006 /* Output a BSR instruction suitable for PIC code. */
1008 m68k_output_pic_call(rtx dest
)
1012 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1014 /* We output a BSR instruction if we're using -fpic or we're building for
1015 * a target that supports long branches. If we're building -fPIC on the
1016 * 68000, 68010 or ColdFire we generate one of two sequences:
1017 * a shorter one that uses a GOT entry or a longer one that doesn't.
1018 * We'll use the -Os command-line flag to decide which to generate.
1019 * Both sequences take the same time to execute on the ColdFire.
1021 else if (TARGET_PCREL
)
1023 else if ((flag_pic
== 1) || TARGET_68020
)
1024 #if defined(USE_GAS)
1025 out
= "bsr.l %0@PLTPC";
1027 out
= "bsr %0@PLTPC";
1029 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1030 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1032 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1034 output_asm_insn(out
, &dest
);
1037 /* Output a dbCC; jCC sequence. Note we do not handle the
1038 floating point version of this sequence (Fdbcc). We also
1039 do not handle alternative conditions when CC_NO_OVERFLOW is
1040 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1041 kick those out before we get here. */
1044 output_dbcc_and_branch (rtx
*operands
)
1046 switch (GET_CODE (operands
[3]))
1049 output_asm_insn (MOTOROLA
?
1050 "dbeq %0,%l1\n\tjbeq %l2" :
1051 "dbeq %0,%l1\n\tjeq %l2",
1056 output_asm_insn (MOTOROLA
?
1057 "dbne %0,%l1\n\tjbne %l2" :
1058 "dbne %0,%l1\n\tjne %l2",
1063 output_asm_insn (MOTOROLA
?
1064 "dbgt %0,%l1\n\tjbgt %l2" :
1065 "dbgt %0,%l1\n\tjgt %l2",
1070 output_asm_insn (MOTOROLA
?
1071 "dbhi %0,%l1\n\tjbhi %l2" :
1072 "dbhi %0,%l1\n\tjhi %l2",
1077 output_asm_insn (MOTOROLA
?
1078 "dblt %0,%l1\n\tjblt %l2" :
1079 "dblt %0,%l1\n\tjlt %l2",
1084 output_asm_insn (MOTOROLA
?
1085 "dbcs %0,%l1\n\tjbcs %l2" :
1086 "dbcs %0,%l1\n\tjcs %l2",
1091 output_asm_insn (MOTOROLA
?
1092 "dbge %0,%l1\n\tjbge %l2" :
1093 "dbge %0,%l1\n\tjge %l2",
1098 output_asm_insn (MOTOROLA
?
1099 "dbcc %0,%l1\n\tjbcc %l2" :
1100 "dbcc %0,%l1\n\tjcc %l2",
1105 output_asm_insn (MOTOROLA
?
1106 "dble %0,%l1\n\tjble %l2" :
1107 "dble %0,%l1\n\tjle %l2",
1112 output_asm_insn (MOTOROLA
?
1113 "dbls %0,%l1\n\tjbls %l2" :
1114 "dbls %0,%l1\n\tjls %l2",
1122 /* If the decrement is to be done in SImode, then we have
1123 to compensate for the fact that dbcc decrements in HImode. */
1124 switch (GET_MODE (operands
[0]))
1127 output_asm_insn (MOTOROLA
?
1128 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1129 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1142 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1145 enum rtx_code op_code
= GET_CODE (op
);
1147 /* This does not produce a useful cc. */
1150 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1151 below. Swap the operands and change the op if these requirements
1152 are not fulfilled. */
1153 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1157 operand1
= operand2
;
1159 op_code
= swap_condition (op_code
);
1161 loperands
[0] = operand1
;
1162 if (GET_CODE (operand1
) == REG
)
1163 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1165 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1166 if (operand2
!= const0_rtx
)
1168 loperands
[2] = operand2
;
1169 if (GET_CODE (operand2
) == REG
)
1170 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1172 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1174 loperands
[4] = gen_label_rtx();
1175 if (operand2
!= const0_rtx
)
1177 output_asm_insn (MOTOROLA
?
1178 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1179 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1184 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1185 output_asm_insn ("tst%.l %0", loperands
);
1188 output_asm_insn ("cmp%.w #0,%0", loperands
);
1191 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1193 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1194 output_asm_insn ("tst%.l %1", loperands
);
1196 output_asm_insn ("cmp%.w #0,%1", loperands
);
1199 loperands
[5] = dest
;
1204 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1205 CODE_LABEL_NUMBER (loperands
[4]));
1206 output_asm_insn ("seq %5", loperands
);
1210 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1211 CODE_LABEL_NUMBER (loperands
[4]));
1212 output_asm_insn ("sne %5", loperands
);
1216 loperands
[6] = gen_label_rtx();
1217 output_asm_insn (MOTOROLA
?
1218 "shi %5\n\tjbra %l6" :
1219 "shi %5\n\tjra %l6",
1221 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1222 CODE_LABEL_NUMBER (loperands
[4]));
1223 output_asm_insn ("sgt %5", loperands
);
1224 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1225 CODE_LABEL_NUMBER (loperands
[6]));
1229 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1230 CODE_LABEL_NUMBER (loperands
[4]));
1231 output_asm_insn ("shi %5", loperands
);
1235 loperands
[6] = gen_label_rtx();
1236 output_asm_insn (MOTOROLA
?
1237 "scs %5\n\tjbra %l6" :
1238 "scs %5\n\tjra %l6",
1240 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1241 CODE_LABEL_NUMBER (loperands
[4]));
1242 output_asm_insn ("slt %5", loperands
);
1243 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1244 CODE_LABEL_NUMBER (loperands
[6]));
1248 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1249 CODE_LABEL_NUMBER (loperands
[4]));
1250 output_asm_insn ("scs %5", loperands
);
1254 loperands
[6] = gen_label_rtx();
1255 output_asm_insn (MOTOROLA
?
1256 "scc %5\n\tjbra %l6" :
1257 "scc %5\n\tjra %l6",
1259 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1260 CODE_LABEL_NUMBER (loperands
[4]));
1261 output_asm_insn ("sge %5", loperands
);
1262 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1263 CODE_LABEL_NUMBER (loperands
[6]));
1267 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1268 CODE_LABEL_NUMBER (loperands
[4]));
1269 output_asm_insn ("scc %5", loperands
);
1273 loperands
[6] = gen_label_rtx();
1274 output_asm_insn (MOTOROLA
?
1275 "sls %5\n\tjbra %l6" :
1276 "sls %5\n\tjra %l6",
1278 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1279 CODE_LABEL_NUMBER (loperands
[4]));
1280 output_asm_insn ("sle %5", loperands
);
1281 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1282 CODE_LABEL_NUMBER (loperands
[6]));
1286 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1287 CODE_LABEL_NUMBER (loperands
[4]));
1288 output_asm_insn ("sls %5", loperands
);
1298 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1300 operands
[0] = countop
;
1301 operands
[1] = dataop
;
1303 if (GET_CODE (countop
) == CONST_INT
)
1305 register int count
= INTVAL (countop
);
1306 /* If COUNT is bigger than size of storage unit in use,
1307 advance to the containing unit of same size. */
1308 if (count
> signpos
)
1310 int offset
= (count
& ~signpos
) / 8;
1311 count
= count
& signpos
;
1312 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1314 if (count
== signpos
)
1315 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1317 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1319 /* These three statements used to use next_insns_test_no...
1320 but it appears that this should do the same job. */
1322 && next_insn_tests_no_inequality (insn
))
1325 && next_insn_tests_no_inequality (insn
))
1328 && next_insn_tests_no_inequality (insn
))
1331 cc_status
.flags
= CC_NOT_NEGATIVE
;
1333 return "btst %0,%1";
1336 /* Returns true if OP is either a symbol reference or a sum of a symbol
1337 reference and a constant. */
1340 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1342 switch (GET_CODE (op
))
1350 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1351 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1352 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1354 #if 0 /* Deleted, with corresponding change in m68k.h,
1355 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1357 return GET_MODE (op
) == mode
;
1365 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1368 extend_operator(rtx x
, enum machine_mode mode
)
1370 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1372 switch (GET_CODE(x
))
1383 /* Legitimize PIC addresses. If the address is already
1384 position-independent, we return ORIG. Newly generated
1385 position-independent addresses go to REG. If we need more
1386 than one register, we lose.
1388 An address is legitimized by making an indirect reference
1389 through the Global Offset Table with the name of the symbol
1392 The assembler and linker are responsible for placing the
1393 address of the symbol in the GOT. The function prologue
1394 is responsible for initializing a5 to the starting address
1397 The assembler is also responsible for translating a symbol name
1398 into a constant displacement from the start of the GOT.
1400 A quick example may make things a little clearer:
1402 When not generating PIC code to store the value 12345 into _foo
1403 we would generate the following code:
1407 When generating PIC two transformations are made. First, the compiler
1408 loads the address of foo into a register. So the first transformation makes:
1413 The code in movsi will intercept the lea instruction and call this
1414 routine which will transform the instructions into:
1416 movel a5@(_foo:w), a0
1420 That (in a nutshell) is how *all* symbol and label references are
1424 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1429 /* First handle a simple SYMBOL_REF or LABEL_REF */
1430 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1435 pic_ref
= gen_rtx_MEM (Pmode
,
1436 gen_rtx_PLUS (Pmode
,
1437 pic_offset_table_rtx
, orig
));
1438 current_function_uses_pic_offset_table
= 1;
1439 RTX_UNCHANGING_P (pic_ref
) = 1;
1440 emit_move_insn (reg
, pic_ref
);
1443 else if (GET_CODE (orig
) == CONST
)
1447 /* Make sure this has not already been legitimized. */
1448 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1449 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1455 /* legitimize both operands of the PLUS */
1456 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1458 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1459 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1460 base
== reg
? 0 : reg
);
1464 if (GET_CODE (orig
) == CONST_INT
)
1465 return plus_constant (base
, INTVAL (orig
));
1466 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1467 /* Likewise, should we set special REG_NOTEs here? */
1473 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1475 static CONST_METHOD
const_method (rtx
);
1477 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1480 const_method (rtx constant
)
1485 i
= INTVAL (constant
);
1489 /* The ColdFire doesn't have byte or word operations. */
1490 /* FIXME: This may not be useful for the m68060 either. */
1491 if (!TARGET_COLDFIRE
)
1493 /* if -256 < N < 256 but N is not in range for a moveq
1494 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1495 if (USE_MOVQ (i
^ 0xff))
1497 /* Likewise, try with not.w */
1498 if (USE_MOVQ (i
^ 0xffff))
1500 /* This is the only value where neg.w is useful */
1503 /* Try also with swap */
1505 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1511 /* Try using MVZ/MVS with an immedaite value to load constants. */
1512 if (i
>= 0 && i
<= 65535)
1514 if (i
>= -32768 && i
<= 32767)
1518 /* Otherwise, use move.l */
1523 const_int_cost (rtx constant
)
1525 switch (const_method (constant
))
1528 /* Constants between -128 and 127 are cheap due to moveq */
1536 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1546 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1551 /* Constant zero is super cheap due to clr instruction. */
1552 if (x
== const0_rtx
)
1555 *total
= const_int_cost (x
);
1565 /* Make 0.0 cheaper than other floating constants to
1566 encourage creating tstsf and tstdf insns. */
1567 if (outer_code
== COMPARE
1568 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1574 /* These are vaguely right for a 68020. */
1575 /* The costs for long multiply have been adjusted to work properly
1576 in synth_mult on the 68020, relative to an average of the time
1577 for add and the time for shift, taking away a little more because
1578 sometimes move insns are needed. */
1579 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1580 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1581 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1582 TARGET_CFV3 ? 2 : 5)
1583 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1586 /* An lea costs about three times as much as a simple add. */
1587 if (GET_MODE (x
) == SImode
1588 && GET_CODE (XEXP (x
, 1)) == REG
1589 && GET_CODE (XEXP (x
, 0)) == MULT
1590 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1591 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1592 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1593 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1594 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1596 /* lea an@(dx:l:i),am */
1597 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1607 *total
= COSTS_N_INSNS(1);
1610 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1612 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1614 if (INTVAL (XEXP (x
, 1)) < 16)
1615 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1617 /* We're using clrw + swap for these cases. */
1618 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1621 *total
= COSTS_N_INSNS (10); /* worst case */
1624 /* A shift by a big integer takes an extra instruction. */
1625 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1626 && (INTVAL (XEXP (x
, 1)) == 16))
1628 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1631 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1632 && !(INTVAL (XEXP (x
, 1)) > 0
1633 && INTVAL (XEXP (x
, 1)) <= 8))
1635 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1641 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1642 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1643 && GET_MODE (x
) == SImode
)
1644 *total
= COSTS_N_INSNS (MULW_COST
);
1645 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1646 *total
= COSTS_N_INSNS (MULW_COST
);
1648 *total
= COSTS_N_INSNS (MULL_COST
);
1655 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1656 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1657 else if (TARGET_CF_HWDIV
)
1658 *total
= COSTS_N_INSNS (18);
1660 *total
= COSTS_N_INSNS (43); /* div.l */
1669 output_move_const_into_data_reg (rtx
*operands
)
1673 i
= INTVAL (operands
[1]);
1674 switch (const_method (operands
[1]))
1677 return "mvsw %1,%0";
1679 return "mvzw %1,%0";
1681 return "moveq %1,%0";
1684 operands
[1] = GEN_INT (i
^ 0xff);
1685 return "moveq %1,%0\n\tnot%.b %0";
1688 operands
[1] = GEN_INT (i
^ 0xffff);
1689 return "moveq %1,%0\n\tnot%.w %0";
1692 return "moveq #-128,%0\n\tneg%.w %0";
1697 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1698 return "moveq %1,%0\n\tswap %0";
1701 return "move%.l %1,%0";
1708 output_move_simode_const (rtx
*operands
)
1710 if (operands
[1] == const0_rtx
1711 && (DATA_REG_P (operands
[0])
1712 || GET_CODE (operands
[0]) == MEM
)
1713 /* clr insns on 68000 read before writing.
1714 This isn't so on the 68010, but we have no TARGET_68010. */
1715 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1716 || !(GET_CODE (operands
[0]) == MEM
1717 && MEM_VOLATILE_P (operands
[0]))))
1719 else if (operands
[1] == const0_rtx
1720 && ADDRESS_REG_P (operands
[0]))
1721 return "sub%.l %0,%0";
1722 else if (DATA_REG_P (operands
[0]))
1723 return output_move_const_into_data_reg (operands
);
1724 else if (ADDRESS_REG_P (operands
[0])
1725 && INTVAL (operands
[1]) < 0x8000
1726 && INTVAL (operands
[1]) >= -0x8000)
1727 return "move%.w %1,%0";
1728 else if (GET_CODE (operands
[0]) == MEM
1729 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1730 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1731 && INTVAL (operands
[1]) < 0x8000
1732 && INTVAL (operands
[1]) >= -0x8000)
1734 return "move%.l %1,%0";
1738 output_move_simode (rtx
*operands
)
1740 if (GET_CODE (operands
[1]) == CONST_INT
)
1741 return output_move_simode_const (operands
);
1742 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1743 || GET_CODE (operands
[1]) == CONST
)
1744 && push_operand (operands
[0], SImode
))
1746 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1747 || GET_CODE (operands
[1]) == CONST
)
1748 && ADDRESS_REG_P (operands
[0]))
1749 return "lea %a1,%0";
1750 return "move%.l %1,%0";
1754 output_move_himode (rtx
*operands
)
1756 if (GET_CODE (operands
[1]) == CONST_INT
)
1758 if (operands
[1] == const0_rtx
1759 && (DATA_REG_P (operands
[0])
1760 || GET_CODE (operands
[0]) == MEM
)
1761 /* clr insns on 68000 read before writing.
1762 This isn't so on the 68010, but we have no TARGET_68010. */
1763 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1764 || !(GET_CODE (operands
[0]) == MEM
1765 && MEM_VOLATILE_P (operands
[0]))))
1767 else if (operands
[1] == const0_rtx
1768 && ADDRESS_REG_P (operands
[0]))
1769 return "sub%.l %0,%0";
1770 else if (DATA_REG_P (operands
[0])
1771 && INTVAL (operands
[1]) < 128
1772 && INTVAL (operands
[1]) >= -128)
1774 return "moveq %1,%0";
1776 else if (INTVAL (operands
[1]) < 0x8000
1777 && INTVAL (operands
[1]) >= -0x8000)
1778 return "move%.w %1,%0";
1780 else if (CONSTANT_P (operands
[1]))
1781 return "move%.l %1,%0";
1782 /* Recognize the insn before a tablejump, one that refers
1783 to a table of offsets. Such an insn will need to refer
1784 to a label on the insn. So output one. Use the label-number
1785 of the table of offsets to generate this label. This code,
1786 and similar code below, assumes that there will be at most one
1787 reference to each table. */
1788 if (GET_CODE (operands
[1]) == MEM
1789 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1790 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1791 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1793 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1795 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1796 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1798 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1799 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1801 return "move%.w %1,%0";
1805 output_move_qimode (rtx
*operands
)
1809 /* This is probably useless, since it loses for pushing a struct
1810 of several bytes a byte at a time. */
1811 /* 68k family always modifies the stack pointer by at least 2, even for
1812 byte pushes. The 5200 (ColdFire) does not do this. */
1813 if (GET_CODE (operands
[0]) == MEM
1814 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1815 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1816 && ! ADDRESS_REG_P (operands
[1])
1817 && ! TARGET_COLDFIRE
)
1819 xoperands
[1] = operands
[1];
1821 = gen_rtx_MEM (QImode
,
1822 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1823 /* Just pushing a byte puts it in the high byte of the halfword. */
1824 /* We must put it in the low-order, high-numbered byte. */
1825 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1827 xoperands
[3] = stack_pointer_rtx
;
1828 output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands
);
1831 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1835 /* clr and st insns on 68000 read before writing.
1836 This isn't so on the 68010, but we have no TARGET_68010. */
1837 if (!ADDRESS_REG_P (operands
[0])
1838 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1839 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1841 if (operands
[1] == const0_rtx
)
1843 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1844 && GET_CODE (operands
[1]) == CONST_INT
1845 && (INTVAL (operands
[1]) & 255) == 255)
1851 if (GET_CODE (operands
[1]) == CONST_INT
1852 && DATA_REG_P (operands
[0])
1853 && INTVAL (operands
[1]) < 128
1854 && INTVAL (operands
[1]) >= -128)
1856 return "moveq %1,%0";
1858 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1859 return "sub%.l %0,%0";
1860 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1861 return "move%.l %1,%0";
1862 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1863 from address registers. */
1864 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1865 return "move%.w %1,%0";
1866 return "move%.b %1,%0";
1870 output_move_stricthi (rtx
*operands
)
1872 if (operands
[1] == const0_rtx
1873 /* clr insns on 68000 read before writing.
1874 This isn't so on the 68010, but we have no TARGET_68010. */
1875 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1876 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1878 return "move%.w %1,%0";
1882 output_move_strictqi (rtx
*operands
)
1884 if (operands
[1] == const0_rtx
1885 /* clr insns on 68000 read before writing.
1886 This isn't so on the 68010, but we have no TARGET_68010. */
1887 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1888 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1890 return "move%.b %1,%0";
1893 /* Return the best assembler insn template
1894 for moving operands[1] into operands[0] as a fullword. */
1897 singlemove_string (rtx
*operands
)
1899 if (GET_CODE (operands
[1]) == CONST_INT
)
1900 return output_move_simode_const (operands
);
1901 return "move%.l %1,%0";
1905 /* Output assembler code to perform a doubleword move insn
1906 with operands OPERANDS. */
1909 output_move_double (rtx
*operands
)
1913 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1918 rtx addreg0
= 0, addreg1
= 0;
1919 int dest_overlapped_low
= 0;
1920 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1925 /* First classify both operands. */
1927 if (REG_P (operands
[0]))
1929 else if (offsettable_memref_p (operands
[0]))
1931 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1933 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1935 else if (GET_CODE (operands
[0]) == MEM
)
1940 if (REG_P (operands
[1]))
1942 else if (CONSTANT_P (operands
[1]))
1944 else if (offsettable_memref_p (operands
[1]))
1946 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1948 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1950 else if (GET_CODE (operands
[1]) == MEM
)
1955 /* Check for the cases that the operand constraints are not
1956 supposed to allow to happen. Abort if we get one,
1957 because generating code for these cases is painful. */
1959 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1962 /* If one operand is decrementing and one is incrementing
1963 decrement the former register explicitly
1964 and change that operand into ordinary indexing. */
1966 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1968 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1970 output_asm_insn ("sub%.l #12,%0", operands
);
1972 output_asm_insn ("subq%.l #8,%0", operands
);
1973 if (GET_MODE (operands
[1]) == XFmode
)
1974 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1975 else if (GET_MODE (operands
[0]) == DFmode
)
1976 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1978 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1981 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1983 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1985 output_asm_insn ("sub%.l #12,%1", operands
);
1987 output_asm_insn ("subq%.l #8,%1", operands
);
1988 if (GET_MODE (operands
[1]) == XFmode
)
1989 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1990 else if (GET_MODE (operands
[1]) == DFmode
)
1991 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1993 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1997 /* If an operand is an unoffsettable memory ref, find a register
1998 we can increment temporarily to make it refer to the second word. */
2000 if (optype0
== MEMOP
)
2001 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2003 if (optype1
== MEMOP
)
2004 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2006 /* Ok, we can do one word at a time.
2007 Normally we do the low-numbered word first,
2008 but if either operand is autodecrementing then we
2009 do the high-numbered word first.
2011 In either case, set up in LATEHALF the operands to use
2012 for the high-numbered word and in some cases alter the
2013 operands in OPERANDS to be suitable for the low-numbered word. */
2017 if (optype0
== REGOP
)
2019 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2020 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2022 else if (optype0
== OFFSOP
)
2024 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2025 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2029 middlehalf
[0] = operands
[0];
2030 latehalf
[0] = operands
[0];
2033 if (optype1
== REGOP
)
2035 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2036 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2038 else if (optype1
== OFFSOP
)
2040 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2041 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2043 else if (optype1
== CNSTOP
)
2045 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2050 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2051 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2052 operands
[1] = GEN_INT (l
[0]);
2053 middlehalf
[1] = GEN_INT (l
[1]);
2054 latehalf
[1] = GEN_INT (l
[2]);
2056 else if (CONSTANT_P (operands
[1]))
2058 /* actually, no non-CONST_DOUBLE constant should ever
2061 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2062 latehalf
[1] = constm1_rtx
;
2064 latehalf
[1] = const0_rtx
;
2069 middlehalf
[1] = operands
[1];
2070 latehalf
[1] = operands
[1];
2074 /* size is not 12: */
2076 if (optype0
== REGOP
)
2077 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2078 else if (optype0
== OFFSOP
)
2079 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2081 latehalf
[0] = operands
[0];
2083 if (optype1
== REGOP
)
2084 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2085 else if (optype1
== OFFSOP
)
2086 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2087 else if (optype1
== CNSTOP
)
2088 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2090 latehalf
[1] = operands
[1];
2093 /* If insn is effectively movd N(sp),-(sp) then we will do the
2094 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2095 for the low word as well, to compensate for the first decrement of sp. */
2096 if (optype0
== PUSHOP
2097 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2098 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2099 operands
[1] = middlehalf
[1] = latehalf
[1];
2101 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2102 if the upper part of reg N does not appear in the MEM, arrange to
2103 emit the move late-half first. Otherwise, compute the MEM address
2104 into the upper part of N and use that as a pointer to the memory
2106 if (optype0
== REGOP
2107 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2109 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2111 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2112 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2114 /* If both halves of dest are used in the src memory address,
2115 compute the address into latehalf of dest.
2116 Note that this can't happen if the dest is two data regs. */
2118 xops
[0] = latehalf
[0];
2119 xops
[1] = XEXP (operands
[1], 0);
2120 output_asm_insn ("lea %a1,%0", xops
);
2121 if (GET_MODE (operands
[1]) == XFmode
)
2123 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2124 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2125 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2129 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2130 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2134 && reg_overlap_mentioned_p (middlehalf
[0],
2135 XEXP (operands
[1], 0)))
2137 /* Check for two regs used by both source and dest.
2138 Note that this can't happen if the dest is all data regs.
2139 It can happen if the dest is d6, d7, a0.
2140 But in that case, latehalf is an addr reg, so
2141 the code at compadr does ok. */
2143 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2144 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2147 /* JRV says this can't happen: */
2148 if (addreg0
|| addreg1
)
2151 /* Only the middle reg conflicts; simply put it last. */
2152 output_asm_insn (singlemove_string (operands
), operands
);
2153 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2154 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2157 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2158 /* If the low half of dest is mentioned in the source memory
2159 address, the arrange to emit the move late half first. */
2160 dest_overlapped_low
= 1;
2163 /* If one or both operands autodecrementing,
2164 do the two words, high-numbered first. */
2166 /* Likewise, the first move would clobber the source of the second one,
2167 do them in the other order. This happens only for registers;
2168 such overlap can't happen in memory unless the user explicitly
2169 sets it up, and that is an undefined circumstance. */
2171 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2172 || (optype0
== REGOP
&& optype1
== REGOP
2173 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2174 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2175 || dest_overlapped_low
)
2177 /* Make any unoffsettable addresses point at high-numbered word. */
2181 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2183 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2188 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2190 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2194 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2196 /* Undo the adds we just did. */
2198 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2200 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2204 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2206 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2208 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2211 /* Do low-numbered word. */
2212 return singlemove_string (operands
);
2215 /* Normal case: do the two words, low-numbered first. */
2217 output_asm_insn (singlemove_string (operands
), operands
);
2219 /* Do the middle one of the three words for long double */
2223 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2225 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2227 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2230 /* Make any unoffsettable addresses point at high-numbered word. */
2232 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2234 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2237 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2239 /* Undo the adds we just did. */
2243 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2245 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2250 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2252 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2258 /* Return a REG that occurs in ADDR with coefficient 1.
2259 ADDR can be effectively incremented by incrementing REG. */
2262 find_addr_reg (rtx addr
)
2264 while (GET_CODE (addr
) == PLUS
)
2266 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2267 addr
= XEXP (addr
, 0);
2268 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2269 addr
= XEXP (addr
, 1);
2270 else if (CONSTANT_P (XEXP (addr
, 0)))
2271 addr
= XEXP (addr
, 1);
2272 else if (CONSTANT_P (XEXP (addr
, 1)))
2273 addr
= XEXP (addr
, 0);
2277 if (GET_CODE (addr
) == REG
)
2282 /* Output assembler code to perform a 32-bit 3-operand add. */
2285 output_addsi3 (rtx
*operands
)
2287 if (! operands_match_p (operands
[0], operands
[1]))
2289 if (!ADDRESS_REG_P (operands
[1]))
2291 rtx tmp
= operands
[1];
2293 operands
[1] = operands
[2];
2297 /* These insns can result from reloads to access
2298 stack slots over 64k from the frame pointer. */
2299 if (GET_CODE (operands
[2]) == CONST_INT
2300 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2301 return "move%.l %2,%0\n\tadd%.l %1,%0";
2302 if (GET_CODE (operands
[2]) == REG
)
2303 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2304 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2306 if (GET_CODE (operands
[2]) == CONST_INT
)
2308 if (INTVAL (operands
[2]) > 0
2309 && INTVAL (operands
[2]) <= 8)
2310 return "addq%.l %2,%0";
2311 if (INTVAL (operands
[2]) < 0
2312 && INTVAL (operands
[2]) >= -8)
2314 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2315 return "subq%.l %2,%0";
2317 /* On the CPU32 it is faster to use two addql instructions to
2318 add a small integer (8 < N <= 16) to a register.
2319 Likewise for subql. */
2320 if (TARGET_CPU32
&& REG_P (operands
[0]))
2322 if (INTVAL (operands
[2]) > 8
2323 && INTVAL (operands
[2]) <= 16)
2325 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2326 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2328 if (INTVAL (operands
[2]) < -8
2329 && INTVAL (operands
[2]) >= -16)
2331 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2332 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2335 if (ADDRESS_REG_P (operands
[0])
2336 && INTVAL (operands
[2]) >= -0x8000
2337 && INTVAL (operands
[2]) < 0x8000)
2340 return "add%.w %2,%0";
2342 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2345 return "add%.l %2,%0";
2348 /* Store in cc_status the expressions that the condition codes will
2349 describe after execution of an instruction whose pattern is EXP.
2350 Do not alter them if the instruction would not alter the cc's. */
2352 /* On the 68000, all the insns to store in an address register fail to
2353 set the cc's. However, in some cases these instructions can make it
2354 possibly invalid to use the saved cc's. In those cases we clear out
2355 some or all of the saved cc's so they won't be used. */
2358 notice_update_cc (rtx exp
, rtx insn
)
2360 if (GET_CODE (exp
) == SET
)
2362 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2366 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2368 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2369 cc_status
.value1
= 0;
2370 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2371 cc_status
.value2
= 0;
2373 else if (!FP_REG_P (SET_DEST (exp
))
2374 && SET_DEST (exp
) != cc0_rtx
2375 && (FP_REG_P (SET_SRC (exp
))
2376 || GET_CODE (SET_SRC (exp
)) == FIX
2377 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2378 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2382 /* A pair of move insns doesn't produce a useful overall cc. */
2383 else if (!FP_REG_P (SET_DEST (exp
))
2384 && !FP_REG_P (SET_SRC (exp
))
2385 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2386 && (GET_CODE (SET_SRC (exp
)) == REG
2387 || GET_CODE (SET_SRC (exp
)) == MEM
2388 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2392 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2396 else if (XEXP (exp
, 0) != pc_rtx
)
2398 cc_status
.flags
= 0;
2399 cc_status
.value1
= XEXP (exp
, 0);
2400 cc_status
.value2
= XEXP (exp
, 1);
2403 else if (GET_CODE (exp
) == PARALLEL
2404 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2406 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2408 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2410 cc_status
.flags
= 0;
2411 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2412 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2417 if (cc_status
.value2
!= 0
2418 && ADDRESS_REG_P (cc_status
.value2
)
2419 && GET_MODE (cc_status
.value2
) == QImode
)
2421 if (cc_status
.value2
!= 0)
2422 switch (GET_CODE (cc_status
.value2
))
2424 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2425 case ROTATE
: case ROTATERT
:
2426 /* These instructions always clear the overflow bit, and set
2427 the carry to the bit shifted out. */
2428 /* ??? We don't currently have a way to signal carry not valid,
2429 nor do we check for it in the branch insns. */
2433 case PLUS
: case MINUS
: case MULT
:
2434 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2435 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2436 cc_status
.flags
|= CC_NO_OVERFLOW
;
2439 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2440 ends with a move insn moving r2 in r2's mode.
2441 Thus, the cc's are set for r2.
2442 This can set N bit spuriously. */
2443 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2448 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2450 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2451 cc_status
.value2
= 0;
2452 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2453 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2454 cc_status
.flags
= CC_IN_68881
;
2458 output_move_const_double (rtx
*operands
)
2460 int code
= standard_68881_constant_p (operands
[1]);
2464 static char buf
[40];
2466 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2469 return "fmove%.d %1,%0";
2473 output_move_const_single (rtx
*operands
)
2475 int code
= standard_68881_constant_p (operands
[1]);
2479 static char buf
[40];
2481 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2484 return "fmove%.s %f1,%0";
2487 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2488 from the "fmovecr" instruction.
2489 The value, anded with 0xff, gives the code to use in fmovecr
2490 to get the desired constant. */
2492 /* This code has been fixed for cross-compilation. */
2494 static int inited_68881_table
= 0;
2496 static const char *const strings_68881
[7] = {
2506 static const int codes_68881
[7] = {
2516 REAL_VALUE_TYPE values_68881
[7];
2518 /* Set up values_68881 array by converting the decimal values
2519 strings_68881 to binary. */
2522 init_68881_table (void)
2526 enum machine_mode mode
;
2529 for (i
= 0; i
< 7; i
++)
2533 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2534 values_68881
[i
] = r
;
2536 inited_68881_table
= 1;
2540 standard_68881_constant_p (rtx x
)
2545 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2546 used at all on those chips. */
2547 if (TARGET_68040
|| TARGET_68060
)
2550 if (! inited_68881_table
)
2551 init_68881_table ();
2553 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2555 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2557 for (i
= 0; i
< 6; i
++)
2559 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2560 return (codes_68881
[i
]);
2563 if (GET_MODE (x
) == SFmode
)
2566 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2567 return (codes_68881
[6]);
2569 /* larger powers of ten in the constants ram are not used
2570 because they are not equal to a `double' C constant. */
2574 /* If X is a floating-point constant, return the logarithm of X base 2,
2575 or 0 if X is not a power of 2. */
2578 floating_exact_log2 (rtx x
)
2580 REAL_VALUE_TYPE r
, r1
;
2583 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2585 if (REAL_VALUES_LESS (r
, dconst1
))
2588 exp
= real_exponent (&r
);
2589 real_2expN (&r1
, exp
);
2590 if (REAL_VALUES_EQUAL (r1
, r
))
2596 /* A C compound statement to output to stdio stream STREAM the
2597 assembler syntax for an instruction operand X. X is an RTL
2600 CODE is a value that can be used to specify one of several ways
2601 of printing the operand. It is used when identical operands
2602 must be printed differently depending on the context. CODE
2603 comes from the `%' specification that was used to request
2604 printing of the operand. If the specification was just `%DIGIT'
2605 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2606 is the ASCII code for LTR.
2608 If X is a register, this macro should print the register's name.
2609 The names can be found in an array `reg_names' whose type is
2610 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2612 When the machine description has a specification `%PUNCT' (a `%'
2613 followed by a punctuation character), this macro is called with
2614 a null pointer for X and the punctuation character for CODE.
2616 The m68k specific codes are:
2618 '.' for dot needed in Motorola-style opcode names.
2619 '-' for an operand pushing on the stack:
2620 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2621 '+' for an operand pushing on the stack:
2622 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2623 '@' for a reference to the top word on the stack:
2624 sp@, (sp) or (%sp) depending on the style of syntax.
2625 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2626 but & in SGS syntax).
2627 '!' for the cc register (used in an `and to cc' insn).
2628 '$' for the letter `s' in an op code, but only on the 68040.
2629 '&' for the letter `d' in an op code, but only on the 68040.
2630 '/' for register prefix needed by longlong.h.
2632 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2633 'd' to force memory addressing to be absolute, not relative.
2634 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2635 'o' for operands to go directly to output_operand_address (bypassing
2636 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2637 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2638 or print pair of registers as rx:ry.
2643 print_operand (FILE *file
, rtx op
, int letter
)
2648 fprintf (file
, ".");
2650 else if (letter
== '#')
2651 asm_fprintf (file
, "%I");
2652 else if (letter
== '-')
2653 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2654 else if (letter
== '+')
2655 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2656 else if (letter
== '@')
2657 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2658 else if (letter
== '!')
2659 asm_fprintf (file
, "%Rfpcr");
2660 else if (letter
== '$')
2662 if (TARGET_68040_ONLY
)
2663 fprintf (file
, "s");
2665 else if (letter
== '&')
2667 if (TARGET_68040_ONLY
)
2668 fprintf (file
, "d");
2670 else if (letter
== '/')
2671 asm_fprintf (file
, "%R");
2672 else if (letter
== 'o')
2674 /* This is only for direct addresses with TARGET_PCREL */
2675 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2678 output_addr_const (file
, XEXP (op
, 0));
2680 else if (GET_CODE (op
) == REG
)
2683 /* Print out the second register name of a register pair.
2684 I.e., R (6) => 7. */
2685 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2687 fputs (M68K_REGNAME(REGNO (op
)), file
);
2689 else if (GET_CODE (op
) == MEM
)
2691 output_address (XEXP (op
, 0));
2692 if (letter
== 'd' && ! TARGET_68020
2693 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2694 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2695 && INTVAL (XEXP (op
, 0)) < 0x8000
2696 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2697 fprintf (file
, MOTOROLA
? ".l" : ":l");
2699 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2702 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2703 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2705 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2708 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2709 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2711 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2714 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2715 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2719 /* Use `print_operand_address' instead of `output_addr_const'
2720 to ensure that we print relevant PIC stuff. */
2721 asm_fprintf (file
, "%I");
2723 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2724 print_operand_address (file
, op
);
2726 output_addr_const (file
, op
);
2731 /* A C compound statement to output to stdio stream STREAM the
2732 assembler syntax for an instruction operand that is a memory
2733 reference whose address is ADDR. ADDR is an RTL expression.
2735 Note that this contains a kludge that knows that the only reason
2736 we have an address (plus (label_ref...) (reg...)) when not generating
2737 PIC code is in the insn before a tablejump, and we know that m68k.md
2738 generates a label LInnn: on such an insn.
2740 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2741 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2743 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2744 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2745 we want. This difference can be accommodated by using an assembler
2746 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2747 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2748 macro. See m68k/sgs.h for an example; for versions without the bug.
2749 Some assemblers refuse all the above solutions. The workaround is to
2750 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2753 They also do not like things like "pea 1.w", so we simple leave off
2754 the .w on small constants.
2756 This routine is responsible for distinguishing between -fpic and -fPIC
2757 style relocations in an address. When generating -fpic code the
2758 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2759 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2762 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2763 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2764 #else /* !MOTOROLA */
2765 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2766 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2767 #endif /* !MOTOROLA */
2770 print_operand_address (FILE *file
, rtx addr
)
2772 register rtx reg1
, reg2
, breg
, ireg
;
2775 switch (GET_CODE (addr
))
2778 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2781 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2782 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2785 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2786 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2789 reg1
= reg2
= ireg
= breg
= offset
= 0;
2790 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2792 offset
= XEXP (addr
, 0);
2793 addr
= XEXP (addr
, 1);
2795 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2797 offset
= XEXP (addr
, 1);
2798 addr
= XEXP (addr
, 0);
2800 if (GET_CODE (addr
) != PLUS
)
2804 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2806 reg1
= XEXP (addr
, 0);
2807 addr
= XEXP (addr
, 1);
2809 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2811 reg1
= XEXP (addr
, 1);
2812 addr
= XEXP (addr
, 0);
2814 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2816 reg1
= XEXP (addr
, 0);
2817 addr
= XEXP (addr
, 1);
2819 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2821 reg1
= XEXP (addr
, 1);
2822 addr
= XEXP (addr
, 0);
2824 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2826 reg1
= XEXP (addr
, 0);
2827 addr
= XEXP (addr
, 1);
2829 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2831 reg1
= XEXP (addr
, 1);
2832 addr
= XEXP (addr
, 0);
2834 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2835 || GET_CODE (addr
) == SIGN_EXTEND
)
2847 #if 0 /* for OLD_INDEXING */
2848 else if (GET_CODE (addr
) == PLUS
)
2850 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2852 reg2
= XEXP (addr
, 0);
2853 addr
= XEXP (addr
, 1);
2855 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2857 reg2
= XEXP (addr
, 1);
2858 addr
= XEXP (addr
, 0);
2870 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2871 || GET_CODE (reg1
) == MULT
))
2872 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2877 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2882 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2883 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2886 if (GET_CODE (ireg
) == MULT
)
2888 scale
= INTVAL (XEXP (ireg
, 1));
2889 ireg
= XEXP (ireg
, 0);
2891 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2893 ASM_OUTPUT_CASE_FETCH (file
,
2894 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2895 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2896 fprintf (file
, "w");
2900 ASM_OUTPUT_CASE_FETCH (file
,
2901 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2902 M68K_REGNAME(REGNO (ireg
)));
2903 fprintf (file
, "l");
2906 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2910 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2911 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2913 ASM_OUTPUT_CASE_FETCH (file
,
2914 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2915 M68K_REGNAME(REGNO (breg
)));
2916 fprintf (file
, "l)");
2919 if (ireg
!= 0 || breg
!= 0)
2926 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2934 output_addr_const (file
, addr
);
2935 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2937 fprintf (file
, "@GOT");
2939 fprintf (file
, ".w");
2942 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2946 else /* !MOTOROLA */
2948 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2951 output_addr_const (file
, addr
);
2952 if (breg
== pic_offset_table_rtx
)
2956 fprintf (file
, ":w"); break;
2958 fprintf (file
, ":l"); break;
2966 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2968 scale
= INTVAL (XEXP (ireg
, 1));
2969 ireg
= XEXP (ireg
, 0);
2971 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2972 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2973 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2975 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2976 M68K_REGNAME(REGNO (ireg
)));
2978 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2982 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2983 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2985 ASM_OUTPUT_CASE_FETCH (file
,
2986 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2987 M68K_REGNAME(REGNO (reg1
)));
2988 fprintf (file
, "l)");
2991 /* FALL-THROUGH (is this really what we want?) */
2993 if (GET_CODE (addr
) == CONST_INT
2994 && INTVAL (addr
) < 0x8000
2995 && INTVAL (addr
) >= -0x8000)
2997 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2999 else if (GET_CODE (addr
) == CONST_INT
)
3001 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3003 else if (TARGET_PCREL
)
3006 output_addr_const (file
, addr
);
3008 asm_fprintf (file
, ":w,%Rpc)");
3010 asm_fprintf (file
, ":l,%Rpc)");
3014 /* Special case for SYMBOL_REF if the symbol name ends in
3015 `.<letter>', this can be mistaken as a size suffix. Put
3016 the name in parentheses. */
3017 if (GET_CODE (addr
) == SYMBOL_REF
3018 && strlen (XSTR (addr
, 0)) > 2
3019 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3022 output_addr_const (file
, addr
);
3026 output_addr_const (file
, addr
);
3032 /* Check for cases where a clr insns can be omitted from code using
3033 strict_low_part sets. For example, the second clrl here is not needed:
3034 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3036 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3037 insn we are checking for redundancy. TARGET is the register set by the
3041 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3046 p
= prev_nonnote_insn (first_insn
);
3050 /* If it isn't an insn, then give up. */
3051 if (GET_CODE (p
) != INSN
)
3054 if (reg_set_p (target
, p
))
3056 rtx set
= single_set (p
);
3059 /* If it isn't an easy to recognize insn, then give up. */
3063 dest
= SET_DEST (set
);
3065 /* If this sets the entire target register to zero, then our
3066 first_insn is redundant. */
3067 if (rtx_equal_p (dest
, target
)
3068 && SET_SRC (set
) == const0_rtx
)
3070 else if (GET_CODE (dest
) == STRICT_LOW_PART
3071 && GET_CODE (XEXP (dest
, 0)) == REG
3072 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3073 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3074 <= GET_MODE_SIZE (mode
)))
3075 /* This is a strict low part set which modifies less than
3076 we are using, so it is safe. */
3082 p
= prev_nonnote_insn (p
);
3088 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3089 range carefully since this predicate is used in DImode contexts. Also, we
3090 need some extra crud to make it work when hosted on 64-bit machines. */
3093 const_uint32_operand (rtx op
, enum machine_mode mode
)
3095 /* It doesn't make sense to ask this question with a mode that is
3096 not larger than 32 bits. */
3097 if (GET_MODE_BITSIZE (mode
) <= 32)
3100 #if HOST_BITS_PER_WIDE_INT > 32
3101 /* All allowed constants will fit a CONST_INT. */
3102 return (GET_CODE (op
) == CONST_INT
3103 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3105 return (GET_CODE (op
) == CONST_INT
3106 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3110 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3111 to check the range carefully since this predicate is used in DImode
3115 const_sint32_operand (rtx op
, enum machine_mode mode
)
3117 /* It doesn't make sense to ask this question with a mode that is
3118 not larger than 32 bits. */
3119 if (GET_MODE_BITSIZE (mode
) <= 32)
3122 /* All allowed constants will fit a CONST_INT. */
3123 return (GET_CODE (op
) == CONST_INT
3124 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3127 /* Operand predicates for implementing asymmetric pc-relative addressing
3128 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3129 when used as a source operand, but not as a destination operand.
3131 We model this by restricting the meaning of the basic predicates
3132 (general_operand, memory_operand, etc) to forbid the use of this
3133 addressing mode, and then define the following predicates that permit
3134 this addressing mode. These predicates can then be used for the
3135 source operands of the appropriate instructions.
3137 n.b. While it is theoretically possible to change all machine patterns
3138 to use this addressing more where permitted by the architecture,
3139 it has only been implemented for "common" cases: SImode, HImode, and
3140 QImode operands, and only for the principle operations that would
3141 require this addressing mode: data movement and simple integer operations.
3143 In parallel with these new predicates, two new constraint letters
3144 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3145 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3146 In the pcrel case 's' is only valid in combination with 'a' registers.
3147 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3148 of how these constraints are used.
3150 The use of these predicates is strictly optional, though patterns that
3151 don't will cause an extra reload register to be allocated where one
3154 lea (abc:w,%pc),%a0 ; need to reload address
3155 moveq &1,%d1 ; since write to pc-relative space
3156 movel %d1,%a0@ ; is not allowed
3158 lea (abc:w,%pc),%a1 ; no need to reload address here
3159 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3161 For more info, consult tiemann@cygnus.com.
3164 All of the ugliness with predicates and constraints is due to the
3165 simple fact that the m68k does not allow a pc-relative addressing
3166 mode as a destination. gcc does not distinguish between source and
3167 destination addresses. Hence, if we claim that pc-relative address
3168 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3169 end up with invalid code. To get around this problem, we left
3170 pc-relative modes as invalid addresses, and then added special
3171 predicates and constraints to accept them.
3173 A cleaner way to handle this is to modify gcc to distinguish
3174 between source and destination addresses. We can then say that
3175 pc-relative is a valid source address but not a valid destination
3176 address, and hopefully avoid a lot of the predicate and constraint
3177 hackery. Unfortunately, this would be a pretty big change. It would
3178 be a useful change for a number of ports, but there aren't any current
3179 plans to undertake this.
3181 ***************************************************************************/
3184 /* Special case of a general operand that's used as a source operand.
3185 Use this to permit reads from PC-relative memory when -mpcrel
3189 general_src_operand (rtx op
, enum machine_mode mode
)
3192 && GET_CODE (op
) == MEM
3193 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3194 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3195 || GET_CODE (XEXP (op
, 0)) == CONST
))
3197 return general_operand (op
, mode
);
3200 /* Special case of a nonimmediate operand that's used as a source.
3201 Use this to permit reads from PC-relative memory when -mpcrel
3205 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3207 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3208 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3209 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3210 || GET_CODE (XEXP (op
, 0)) == CONST
))
3212 return nonimmediate_operand (op
, mode
);
3215 /* Special case of a memory operand that's used as a source.
3216 Use this to permit reads from PC-relative memory when -mpcrel
3220 memory_src_operand (rtx op
, enum machine_mode mode
)
3222 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3223 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3224 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3225 || GET_CODE (XEXP (op
, 0)) == CONST
))
3227 return memory_operand (op
, mode
);
3230 /* Predicate that accepts only a pc-relative address. This is needed
3231 because pc-relative addresses don't satisfy the predicate
3232 "general_src_operand". */
3235 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3237 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3238 || GET_CODE (op
) == CONST
);
3242 output_andsi3 (rtx
*operands
)
3245 if (GET_CODE (operands
[2]) == CONST_INT
3246 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3247 && (DATA_REG_P (operands
[0])
3248 || offsettable_memref_p (operands
[0]))
3249 && !TARGET_COLDFIRE
)
3251 if (GET_CODE (operands
[0]) != REG
)
3252 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3253 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3254 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3256 if (operands
[2] == const0_rtx
)
3258 return "and%.w %2,%0";
3260 if (GET_CODE (operands
[2]) == CONST_INT
3261 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3262 && (DATA_REG_P (operands
[0])
3263 || offsettable_memref_p (operands
[0])))
3265 if (DATA_REG_P (operands
[0]))
3267 operands
[1] = GEN_INT (logval
);
3271 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3272 operands
[1] = GEN_INT (logval
% 8);
3274 /* This does not set condition codes in a standard way. */
3276 return "bclr %1,%0";
3278 return "and%.l %2,%0";
3282 output_iorsi3 (rtx
*operands
)
3284 register int logval
;
3285 if (GET_CODE (operands
[2]) == CONST_INT
3286 && INTVAL (operands
[2]) >> 16 == 0
3287 && (DATA_REG_P (operands
[0])
3288 || offsettable_memref_p (operands
[0]))
3289 && !TARGET_COLDFIRE
)
3291 if (GET_CODE (operands
[0]) != REG
)
3292 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3293 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3295 if (INTVAL (operands
[2]) == 0xffff)
3296 return "mov%.w %2,%0";
3297 return "or%.w %2,%0";
3299 if (GET_CODE (operands
[2]) == CONST_INT
3300 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3301 && (DATA_REG_P (operands
[0])
3302 || offsettable_memref_p (operands
[0])))
3304 if (DATA_REG_P (operands
[0]))
3305 operands
[1] = GEN_INT (logval
);
3308 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3309 operands
[1] = GEN_INT (logval
% 8);
3312 return "bset %1,%0";
3314 return "or%.l %2,%0";
3318 output_xorsi3 (rtx
*operands
)
3320 register int logval
;
3321 if (GET_CODE (operands
[2]) == CONST_INT
3322 && INTVAL (operands
[2]) >> 16 == 0
3323 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3324 && !TARGET_COLDFIRE
)
3326 if (! DATA_REG_P (operands
[0]))
3327 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3328 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3330 if (INTVAL (operands
[2]) == 0xffff)
3332 return "eor%.w %2,%0";
3334 if (GET_CODE (operands
[2]) == CONST_INT
3335 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3336 && (DATA_REG_P (operands
[0])
3337 || offsettable_memref_p (operands
[0])))
3339 if (DATA_REG_P (operands
[0]))
3340 operands
[1] = GEN_INT (logval
);
3343 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3344 operands
[1] = GEN_INT (logval
% 8);
3347 return "bchg %1,%0";
3349 return "eor%.l %2,%0";
3352 #ifdef M68K_TARGET_COFF
3354 /* Output assembly to switch to section NAME with attribute FLAGS. */
3357 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3361 if (flags
& SECTION_WRITE
)
3366 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3369 #endif /* M68K_TARGET_COFF */
3372 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3373 HOST_WIDE_INT delta
,
3374 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3380 if (delta
> 0 && delta
<= 8)
3381 asm_fprintf (file
, MOTOROLA
?
3382 "\taddq.l %I%d,4(%Rsp)\n" :
3383 "\taddql %I%d,%Rsp@(4)\n",
3385 else if (delta
< 0 && delta
>= -8)
3386 asm_fprintf (file
, MOTOROLA
?
3387 "\tsubq.l %I%d,4(%Rsp)\n" :
3388 "\tsubql %I%d,%Rsp@(4)\n",
3391 asm_fprintf (file
, MOTOROLA
?
3392 "\tadd.l %I%wd,4(%Rsp)\n" :
3393 "\taddl %I%wd,%Rsp@(4)\n",
3396 xops
[0] = DECL_RTL (function
);
3398 /* Logic taken from call patterns in m68k.md. */
3403 else if ((flag_pic
== 1) || TARGET_68020
)
3406 #if defined(USE_GAS)
3407 fmt
= "bra.l %0@PLTPC";
3409 fmt
= "bra %0@PLTPC";
3411 else /* !MOTOROLA */
3418 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3419 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3421 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3425 #if MOTOROLA && !defined (USE_GAS)
3432 output_asm_insn (fmt
, xops
);
3435 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3438 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3439 int incoming ATTRIBUTE_UNUSED
)
3441 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);