1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* Base flags for 68k ISAs. */
205 #define FL_FOR_isa_00 FL_ISA_68000
206 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
207 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
208 generated 68881 code for 68020 and 68030 targets unless explicitly told
210 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
211 | FL_BITFIELD | FL_68881)
212 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
213 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
215 /* Base flags for ColdFire ISAs. */
216 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
217 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
218 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
219 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
220 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
224 /* Traditional 68000 instruction sets. */
230 /* ColdFire instruction set variants. */
238 /* Information about one of the -march, -mcpu or -mtune arguments. */
239 struct m68k_target_selection
241 /* The argument being described. */
244 /* For -mcpu, this is the device selected by the option.
245 For -mtune and -march, it is a representative device
246 for the microarchitecture or ISA respectively. */
247 enum target_device device
;
249 /* The M68K_DEVICE fields associated with DEVICE. See the comment
250 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
252 enum uarch_type microarch
;
257 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
258 static const struct m68k_target_selection all_devices
[] =
260 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
261 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
262 #include "m68k-devices.def"
264 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
267 /* A list of all ISAs, mapping each one to a representative device.
268 Used for -march selection. */
269 static const struct m68k_target_selection all_isas
[] =
271 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
272 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
273 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
274 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
275 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
276 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
277 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
278 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
280 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
282 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
283 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
286 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
289 /* A list of all microarchitectures, mapping each one to a representative
290 device. Used for -mtune selection. */
291 static const struct m68k_target_selection all_microarchs
[] =
293 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
294 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
295 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
296 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
297 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
298 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
299 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
300 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
301 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
302 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
303 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
305 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
310 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
313 /* The entries associated with the -mcpu, -march and -mtune settings,
314 or null for options that have not been used. */
315 const struct m68k_target_selection
*m68k_cpu_entry
;
316 const struct m68k_target_selection
*m68k_arch_entry
;
317 const struct m68k_target_selection
*m68k_tune_entry
;
319 /* Which CPU we are generating code for. */
320 enum target_device m68k_cpu
;
322 /* Which microarchitecture to tune for. */
323 enum uarch_type m68k_tune
;
325 /* Which FPU to use. */
326 enum fpu_type m68k_fpu
;
328 /* The set of FL_* flags that apply to the target processor. */
329 unsigned int m68k_cpu_flags
;
331 /* Asm templates for calling or jumping to an arbitrary symbolic address,
332 or NULL if such calls or jumps are not supported. The address is held
334 const char *m68k_symbolic_call
;
335 const char *m68k_symbolic_jump
;
337 /* See whether TABLE has an entry with name NAME. Return true and
338 store the entry in *ENTRY if so, otherwise return false and
339 leave *ENTRY alone. */
342 m68k_find_selection (const struct m68k_target_selection
**entry
,
343 const struct m68k_target_selection
*table
,
348 for (i
= 0; table
[i
].name
; i
++)
349 if (strcmp (table
[i
].name
, name
) == 0)
357 /* Implement TARGET_HANDLE_OPTION. */
360 m68k_handle_option (size_t code
, const char *arg
, int value
)
365 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
368 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
371 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
374 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
377 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
380 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
383 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
386 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
389 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
393 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
396 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
400 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
403 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
405 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
408 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
410 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
419 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
422 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
426 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
428 case OPT_mshared_library_id_
:
429 if (value
> MAX_LIBRARY_ID
)
430 error ("-mshared-library-id=%s is not between 0 and %d",
431 arg
, MAX_LIBRARY_ID
);
433 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
441 /* Sometimes certain combinations of command options do not make
442 sense on a particular target machine. You can define a macro
443 `OVERRIDE_OPTIONS' to take account of this. This macro, if
444 defined, is executed once just after all the command options have
447 Don't use this macro to turn on various extra optimizations for
448 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
451 override_options (void)
453 const struct m68k_target_selection
*entry
;
454 unsigned long target_mask
;
462 -march=ARCH should generate code that runs any processor
463 implementing architecture ARCH. -mcpu=CPU should override -march
464 and should generate code that runs on processor CPU, making free
465 use of any instructions that CPU understands. -mtune=UARCH applies
466 on top of -mcpu or -march and optimises the code for UARCH. It does
467 not change the target architecture. */
470 /* Complain if the -march setting is for a different microarchitecture,
471 or includes flags that the -mcpu setting doesn't. */
473 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
474 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
475 warning (0, "-mcpu=%s conflicts with -march=%s",
476 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
478 entry
= m68k_cpu_entry
;
481 entry
= m68k_arch_entry
;
484 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
486 m68k_cpu_flags
= entry
->flags
;
488 /* Use the architecture setting to derive default values for
491 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
492 target_mask
|= MASK_BITFIELD
;
493 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
494 target_mask
|= MASK_CF_HWDIV
;
495 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
496 target_mask
|= MASK_HARD_FLOAT
;
497 target_flags
|= target_mask
& ~target_flags_explicit
;
499 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
500 m68k_cpu
= entry
->device
;
502 m68k_tune
= m68k_tune_entry
->microarch
;
503 #ifdef M68K_DEFAULT_TUNE
504 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
505 m68k_tune
= M68K_DEFAULT_TUNE
;
508 m68k_tune
= entry
->microarch
;
510 /* Set the type of FPU. */
511 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
512 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
515 /* Sanity check to ensure that msep-data and mid-sahred-library are not
516 * both specified together. Doing so simply doesn't make sense.
518 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
519 error ("cannot specify both -msep-data and -mid-shared-library");
521 /* If we're generating code for a separate A5 relative data segment,
522 * we've got to enable -fPIC as well. This might be relaxable to
523 * -fpic but it hasn't been tested properly.
525 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
528 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
529 error if the target does not support them. */
530 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
531 error ("-mpcrel -fPIC is not currently supported on selected cpu");
533 /* ??? A historic way of turning on pic, or is this intended to
534 be an embedded thing that doesn't have the same name binding
535 significance that it does on hosted ELF systems? */
536 if (TARGET_PCREL
&& flag_pic
== 0)
541 #if MOTOROLA && !defined (USE_GAS)
542 m68k_symbolic_call
= "jsr %a0";
543 m68k_symbolic_jump
= "jmp %a0";
545 m68k_symbolic_call
= "jbsr %a0";
546 m68k_symbolic_jump
= "jra %a0";
549 else if (TARGET_ID_SHARED_LIBRARY
)
550 /* All addresses must be loaded from the GOT. */
552 else if (TARGET_68020
|| TARGET_ISAB
)
556 m68k_symbolic_call
= "bsr.l %c0";
557 m68k_symbolic_jump
= "bra.l %c0";
562 m68k_symbolic_call
= "bsr.l %p0";
563 m68k_symbolic_jump
= "bra.l %p0";
565 m68k_symbolic_call
= "bsr %p0";
566 m68k_symbolic_jump
= "bra %p0";
569 /* Turn off function cse if we are doing PIC. We always want
570 function call to be done as `bsr foo@PLTPC'. */
571 /* ??? It's traditional to do this for -mpcrel too, but it isn't
572 clear how intentional that is. */
573 flag_no_function_cse
= 1;
576 SUBTARGET_OVERRIDE_OPTIONS
;
579 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
580 given argument and NAME is the argument passed to -mcpu. Return NULL
581 if -mcpu was not passed. */
584 m68k_cpp_cpu_ident (const char *prefix
)
588 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
591 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
592 given argument and NAME is the name of the representative device for
593 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
596 m68k_cpp_cpu_family (const char *prefix
)
600 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
603 /* Return nonzero if FUNC is an interrupt function as specified by the
604 "interrupt_handler" attribute. */
606 m68k_interrupt_function_p(tree func
)
610 if (TREE_CODE (func
) != FUNCTION_DECL
)
613 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
614 return (a
!= NULL_TREE
);
617 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
618 struct attribute_spec.handler. */
620 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
621 tree args ATTRIBUTE_UNUSED
,
622 int flags ATTRIBUTE_UNUSED
,
625 if (TREE_CODE (*node
) != FUNCTION_DECL
)
627 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
628 IDENTIFIER_POINTER (name
));
629 *no_add_attrs
= true;
636 m68k_compute_frame_layout (void)
639 unsigned int mask
, rmask
;
640 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
642 /* Only compute the frame once per function.
643 Don't cache information until reload has been completed. */
644 if (current_frame
.funcdef_no
== current_function_funcdef_no
648 current_frame
.size
= (get_frame_size () + 3) & -4;
650 mask
= rmask
= saved
= 0;
651 for (regno
= 0; regno
< 16; regno
++)
652 if (m68k_save_reg (regno
, interrupt_handler
))
655 rmask
|= 1 << (15 - regno
);
658 current_frame
.offset
= saved
* 4;
659 current_frame
.reg_no
= saved
;
660 current_frame
.reg_mask
= mask
;
661 current_frame
.reg_rev_mask
= rmask
;
663 current_frame
.foffset
= 0;
664 mask
= rmask
= saved
= 0;
665 if (TARGET_HARD_FLOAT
)
667 for (regno
= 16; regno
< 24; regno
++)
668 if (m68k_save_reg (regno
, interrupt_handler
))
670 mask
|= 1 << (regno
- 16);
671 rmask
|= 1 << (23 - regno
);
674 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
675 current_frame
.offset
+= current_frame
.foffset
;
677 current_frame
.fpu_no
= saved
;
678 current_frame
.fpu_mask
= mask
;
679 current_frame
.fpu_rev_mask
= rmask
;
681 /* Remember what function this frame refers to. */
682 current_frame
.funcdef_no
= current_function_funcdef_no
;
686 m68k_initial_elimination_offset (int from
, int to
)
689 /* The arg pointer points 8 bytes before the start of the arguments,
690 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
691 frame pointer in most frames. */
692 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
693 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
694 return argptr_offset
;
696 m68k_compute_frame_layout ();
698 gcc_assert (to
== STACK_POINTER_REGNUM
);
701 case ARG_POINTER_REGNUM
:
702 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
703 case FRAME_POINTER_REGNUM
:
704 return current_frame
.offset
+ current_frame
.size
;
710 /* Refer to the array `regs_ever_live' to determine which registers
711 to save; `regs_ever_live[I]' is nonzero if register number I
712 is ever used in the function. This function is responsible for
713 knowing which registers should not be saved even if used.
714 Return true if we need to save REGNO. */
717 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
719 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
721 if (current_function_uses_pic_offset_table
)
723 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
727 if (current_function_calls_eh_return
)
732 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
733 if (test
== INVALID_REGNUM
)
740 /* Fixed regs we never touch. */
741 if (fixed_regs
[regno
])
744 /* The frame pointer (if it is such) is handled specially. */
745 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
748 /* Interrupt handlers must also save call_used_regs
749 if they are live or when calling nested functions. */
750 if (interrupt_handler
)
752 if (regs_ever_live
[regno
])
755 if (!current_function_is_leaf
&& call_used_regs
[regno
])
759 /* Never need to save registers that aren't touched. */
760 if (!regs_ever_live
[regno
])
763 /* Otherwise save everything that isn't call-clobbered. */
764 return !call_used_regs
[regno
];
767 /* This function generates the assembly code for function entry.
768 STREAM is a stdio stream to output the code to.
769 SIZE is an int: how many units of temporary storage to allocate. */
772 m68k_output_function_prologue (FILE *stream
,
773 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
775 HOST_WIDE_INT fsize_with_regs
;
776 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
778 m68k_compute_frame_layout();
780 /* If the stack limit is a symbol, we can check it here,
781 before actually allocating the space. */
782 if (current_function_limit_stack
783 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
784 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
785 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
787 /* On ColdFire add register save into initial stack frame setup, if possible. */
788 fsize_with_regs
= current_frame
.size
;
791 if (current_frame
.reg_no
> 2)
792 fsize_with_regs
+= current_frame
.reg_no
* 4;
793 if (current_frame
.fpu_no
)
794 fsize_with_regs
+= current_frame
.fpu_no
* 8;
797 if (frame_pointer_needed
)
799 if (current_frame
.size
== 0 && TUNE_68040
)
800 /* on the 68040, pea + move is faster than link.w 0 */
801 fprintf (stream
, (MOTOROLA
802 ? "\tpea (%s)\n\tmove.l %s,%s\n"
803 : "\tpea %s@\n\tmovel %s,%s\n"),
804 M68K_REGNAME (FRAME_POINTER_REGNUM
),
805 M68K_REGNAME (STACK_POINTER_REGNUM
),
806 M68K_REGNAME (FRAME_POINTER_REGNUM
));
807 else if (fsize_with_regs
< 0x8000)
808 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
809 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
810 else if (TARGET_68020
)
811 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
812 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
814 /* Adding negative number is faster on the 68040. */
816 "\tlink" ASM_DOTW
" %s,%I0\n"
817 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
818 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
820 else if (fsize_with_regs
) /* !frame_pointer_needed */
822 if (fsize_with_regs
< 0x8000)
824 if (fsize_with_regs
<= 8)
826 if (!TARGET_COLDFIRE
)
827 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
830 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
833 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
834 /* On the CPU32 it is faster to use two subqw instructions to
835 subtract a small integer (8 < N <= 16) to a register. */
837 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
838 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
839 fsize_with_regs
- 8);
841 /* Adding negative number is faster on the 68040. */
842 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
845 asm_fprintf (stream
, (MOTOROLA
846 ? "\tlea (%wd,%Rsp),%Rsp\n"
847 : "\tlea %Rsp@(%wd),%Rsp\n"),
850 else /* fsize_with_regs >= 0x8000 */
851 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
853 } /* !frame_pointer_needed */
855 if (dwarf2out_do_frame ())
857 if (frame_pointer_needed
)
860 l
= (char *) dwarf2out_cfi_label ();
862 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
863 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
864 cfa_offset
+= current_frame
.size
;
868 cfa_offset
+= current_frame
.size
;
869 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
873 if (current_frame
.fpu_mask
)
877 asm_fprintf (stream
, (MOTOROLA
878 ? "\tfmovm %I0x%x,-(%Rsp)\n"
879 : "\tfmovem %I0x%x,%Rsp@-\n"),
880 current_frame
.fpu_mask
);
886 /* stack already has registers in it. Find the offset from
887 the bottom of stack to where the FP registers go */
888 if (current_frame
.reg_no
<= 2)
891 offset
= current_frame
.reg_no
* 4;
894 "\tfmovem %I0x%x,%d(%Rsp)\n",
895 current_frame
.fpu_rev_mask
,
899 "\tfmovem %I0x%x,(%Rsp)\n",
900 current_frame
.fpu_rev_mask
);
903 if (dwarf2out_do_frame ())
905 char *l
= (char *) dwarf2out_cfi_label ();
908 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
909 if (! frame_pointer_needed
)
910 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
911 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
912 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
913 dwarf2out_reg_save (l
, regno
, -cfa_offset
914 + n_regs
++ * TARGET_FP_REG_SIZE
);
918 /* If the stack limit is not a symbol, check it here.
919 This has the disadvantage that it may be too late... */
920 if (current_function_limit_stack
)
922 if (REG_P (stack_limit_rtx
))
923 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
924 M68K_REGNAME (REGNO (stack_limit_rtx
)));
925 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
926 warning (0, "stack limit expression is not supported");
929 if (current_frame
.reg_no
<= 2)
931 /* Store each separately in the same order moveml uses.
932 Using two movel instructions instead of a single moveml
933 is about 15% faster for the 68020 and 68030 at no expense
938 for (i
= 0; i
< 16; i
++)
939 if (current_frame
.reg_rev_mask
& (1 << i
))
941 asm_fprintf (stream
, (MOTOROLA
942 ? "\t%Omove.l %s,-(%Rsp)\n"
943 : "\tmovel %s,%Rsp@-\n"),
944 M68K_REGNAME (15 - i
));
945 if (dwarf2out_do_frame ())
947 char *l
= (char *) dwarf2out_cfi_label ();
950 if (! frame_pointer_needed
)
951 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
952 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
956 else if (current_frame
.reg_rev_mask
)
959 /* The ColdFire does not support the predecrement form of the
960 MOVEM instruction, so we must adjust the stack pointer and
961 then use the plain address register indirect mode.
962 The required register save space was combined earlier with
963 the fsize_with_regs amount. */
965 asm_fprintf (stream
, (MOTOROLA
966 ? "\tmovm.l %I0x%x,(%Rsp)\n"
967 : "\tmoveml %I0x%x,%Rsp@\n"),
968 current_frame
.reg_mask
);
970 asm_fprintf (stream
, (MOTOROLA
971 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
972 : "\tmoveml %I0x%x,%Rsp@-\n"),
973 current_frame
.reg_rev_mask
);
974 if (dwarf2out_do_frame ())
976 char *l
= (char *) dwarf2out_cfi_label ();
979 cfa_offset
+= current_frame
.reg_no
* 4;
980 if (! frame_pointer_needed
)
981 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
982 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
983 if (current_frame
.reg_mask
& (1 << regno
))
984 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
987 if (!TARGET_SEP_DATA
&& flag_pic
988 && (current_function_uses_pic_offset_table
989 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
991 if (TARGET_ID_SHARED_LIBRARY
)
993 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
994 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
995 m68k_library_id_string
,
996 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1001 asm_fprintf (stream
,
1002 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
1003 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1006 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
1007 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1008 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
1009 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1010 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1016 /* Return true if this function's epilogue can be output as RTL. */
1019 use_return_insn (void)
1021 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1024 /* We can output the epilogue as RTL only if no registers need to be
1026 m68k_compute_frame_layout ();
1027 return current_frame
.reg_no
? false : true;
1030 /* This function generates the assembly code for function exit,
1031 on machines that need it.
1033 The function epilogue should not depend on the current stack pointer!
1034 It should use the frame pointer only, if there is a frame pointer.
1035 This is mandatory because of alloca; we also take advantage of it to
1036 omit stack adjustments before returning. */
1039 m68k_output_function_epilogue (FILE *stream
,
1040 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1042 HOST_WIDE_INT fsize
, fsize_with_regs
;
1044 bool restore_from_sp
= false;
1045 rtx insn
= get_last_insn ();
1047 m68k_compute_frame_layout ();
1049 /* If the last insn was a BARRIER, we don't have to write any code. */
1050 if (GET_CODE (insn
) == NOTE
)
1051 insn
= prev_nonnote_insn (insn
);
1052 if (insn
&& GET_CODE (insn
) == BARRIER
)
1054 /* Output just a no-op so that debuggers don't get confused
1055 about which function the pc is in at this address. */
1056 fprintf (stream
, "\tnop\n");
1060 #ifdef FUNCTION_EXTRA_EPILOGUE
1061 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
1064 fsize
= current_frame
.size
;
1066 /* FIXME: leaf_function_p below is too strong.
1067 What we really need to know there is if there could be pending
1068 stack adjustment needed at that point. */
1070 = (! frame_pointer_needed
1071 || (! current_function_calls_alloca
&& leaf_function_p ()));
1073 /* fsize_with_regs is the size we need to adjust the sp when
1074 popping the frame. */
1075 fsize_with_regs
= fsize
;
1077 /* Because the ColdFire doesn't support moveml with
1078 complex address modes, we must adjust the stack manually
1079 after restoring registers. When the frame pointer isn't used,
1080 we can merge movem adjustment into frame unlinking
1081 made immediately after it. */
1082 if (TARGET_COLDFIRE
&& restore_from_sp
)
1084 if (current_frame
.reg_no
> 2)
1085 fsize_with_regs
+= current_frame
.reg_no
* 4;
1086 if (current_frame
.fpu_no
)
1087 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1090 if (current_frame
.offset
+ fsize
>= 0x8000
1091 && ! restore_from_sp
1092 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1094 /* Because the ColdFire doesn't support moveml with
1095 complex address modes we make an extra correction here. */
1096 if (TARGET_COLDFIRE
)
1097 fsize
+= current_frame
.offset
;
1099 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1100 fsize
= 0, big
= true;
1102 if (current_frame
.reg_no
<= 2)
1104 /* Restore each separately in the same order moveml does.
1105 Using two movel instructions instead of a single moveml
1106 is about 15% faster for the 68020 and 68030 at no expense
1110 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1112 for (i
= 0; i
< 16; i
++)
1113 if (current_frame
.reg_mask
& (1 << i
))
1118 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1120 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1123 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1124 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1128 else if (restore_from_sp
)
1129 asm_fprintf (stream
, (MOTOROLA
1130 ? "\t%Omove.l (%Rsp)+,%s\n"
1131 : "\tmovel %Rsp@+,%s\n"),
1136 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1138 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1141 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1142 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1149 else if (current_frame
.reg_mask
)
1151 /* The ColdFire requires special handling due to its limited moveml
1153 if (TARGET_COLDFIRE
)
1157 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1158 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1159 asm_fprintf (stream
, (MOTOROLA
1160 ? "\tmovm.l (%Ra1),%I0x%x\n"
1161 : "\tmoveml %Ra1@,%I0x%x\n"),
1162 current_frame
.reg_mask
);
1164 else if (restore_from_sp
)
1165 asm_fprintf (stream
, (MOTOROLA
1166 ? "\tmovm.l (%Rsp),%I0x%x\n"
1167 : "\tmoveml %Rsp@,%I0x%x\n"),
1168 current_frame
.reg_mask
);
1172 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1173 current_frame
.offset
+ fsize
,
1174 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1175 current_frame
.reg_mask
);
1177 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1178 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1179 current_frame
.offset
+ fsize
,
1180 current_frame
.reg_mask
);
1183 else /* !TARGET_COLDFIRE */
1188 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1189 current_frame
.offset
+ fsize
,
1190 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1191 current_frame
.reg_mask
);
1193 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1194 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1195 current_frame
.offset
+ fsize
,
1196 current_frame
.reg_mask
);
1198 else if (restore_from_sp
)
1200 asm_fprintf (stream
, (MOTOROLA
1201 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1202 : "\tmoveml %Rsp@+,%I0x%x\n"),
1203 current_frame
.reg_mask
);
1208 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1209 current_frame
.offset
+ fsize
,
1210 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1211 current_frame
.reg_mask
);
1213 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1214 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1215 current_frame
.offset
+ fsize
,
1216 current_frame
.reg_mask
);
1220 if (current_frame
.fpu_rev_mask
)
1224 if (TARGET_COLDFIRE
)
1226 if (current_frame
.reg_no
)
1227 asm_fprintf (stream
, MOTOROLA
?
1228 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1229 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1230 current_frame
.reg_no
* 4,
1231 current_frame
.fpu_rev_mask
);
1233 asm_fprintf (stream
, MOTOROLA
?
1234 "\tfmovem.d (%Ra1),%I0x%x\n" :
1235 "\tfmovmd (%Ra1),%I0x%x\n",
1236 current_frame
.fpu_rev_mask
);
1239 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1240 current_frame
.foffset
+ fsize
,
1241 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1242 current_frame
.fpu_rev_mask
);
1244 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1245 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1246 current_frame
.foffset
+ fsize
,
1247 current_frame
.fpu_rev_mask
);
1249 else if (restore_from_sp
)
1251 if (TARGET_COLDFIRE
)
1255 /* Stack already has registers in it. Find the offset from
1256 the bottom of stack to where the FP registers go. */
1257 if (current_frame
.reg_no
<= 2)
1260 offset
= current_frame
.reg_no
* 4;
1262 asm_fprintf (stream
,
1263 "\tfmovem %Rsp@(%d), %I0x%x\n",
1264 offset
, current_frame
.fpu_rev_mask
);
1266 asm_fprintf (stream
,
1267 "\tfmovem %Rsp@, %I0x%x\n",
1268 current_frame
.fpu_rev_mask
);
1271 asm_fprintf (stream
, MOTOROLA
?
1272 "\tfmovm (%Rsp)+,%I0x%x\n" :
1273 "\tfmovem %Rsp@+,%I0x%x\n",
1274 current_frame
.fpu_rev_mask
);
1278 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1279 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1280 current_frame
.foffset
+ fsize
,
1281 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1282 current_frame
.fpu_rev_mask
);
1284 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1285 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1286 current_frame
.foffset
+ fsize
,
1287 current_frame
.fpu_rev_mask
);
1290 if (frame_pointer_needed
)
1291 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1292 else if (fsize_with_regs
)
1294 if (fsize_with_regs
<= 8)
1296 if (!TARGET_COLDFIRE
)
1297 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1300 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1303 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1305 /* On the CPU32 it is faster to use two addqw instructions to
1306 add a small integer (8 < N <= 16) to a register. */
1307 asm_fprintf (stream
,
1308 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1309 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1310 fsize_with_regs
- 8);
1312 else if (fsize_with_regs
< 0x8000)
1315 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1318 asm_fprintf (stream
, (MOTOROLA
1319 ? "\tlea (%wd,%Rsp),%Rsp\n"
1320 : "\tlea %Rsp@(%wd),%Rsp\n"),
1324 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1326 if (current_function_calls_eh_return
)
1327 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1328 if (m68k_interrupt_function_p (current_function_decl
))
1329 fprintf (stream
, "\trte\n");
1330 else if (current_function_pops_args
)
1331 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1333 fprintf (stream
, "\trts\n");
1336 /* Return true if X is a valid comparison operator for the dbcc
1339 Note it rejects floating point comparison operators.
1340 (In the future we could use Fdbcc).
1342 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1345 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1347 switch (GET_CODE (x
))
1349 case EQ
: case NE
: case GTU
: case LTU
:
1353 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1355 case GT
: case LT
: case GE
: case LE
:
1356 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1362 /* Return nonzero if flags are currently in the 68881 flag register. */
1364 flags_in_68881 (void)
1366 /* We could add support for these in the future */
1367 return cc_status
.flags
& CC_IN_68881
;
1370 /* Convert X to a legitimate function call memory reference and return the
1374 m68k_legitimize_call_address (rtx x
)
1376 gcc_assert (MEM_P (x
));
1377 if (call_operand (XEXP (x
, 0), VOIDmode
))
1379 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1382 /* Output a dbCC; jCC sequence. Note we do not handle the
1383 floating point version of this sequence (Fdbcc). We also
1384 do not handle alternative conditions when CC_NO_OVERFLOW is
1385 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1386 kick those out before we get here. */
1389 output_dbcc_and_branch (rtx
*operands
)
1391 switch (GET_CODE (operands
[3]))
1394 output_asm_insn (MOTOROLA
1395 ? "dbeq %0,%l1\n\tjbeq %l2"
1396 : "dbeq %0,%l1\n\tjeq %l2",
1401 output_asm_insn (MOTOROLA
1402 ? "dbne %0,%l1\n\tjbne %l2"
1403 : "dbne %0,%l1\n\tjne %l2",
1408 output_asm_insn (MOTOROLA
1409 ? "dbgt %0,%l1\n\tjbgt %l2"
1410 : "dbgt %0,%l1\n\tjgt %l2",
1415 output_asm_insn (MOTOROLA
1416 ? "dbhi %0,%l1\n\tjbhi %l2"
1417 : "dbhi %0,%l1\n\tjhi %l2",
1422 output_asm_insn (MOTOROLA
1423 ? "dblt %0,%l1\n\tjblt %l2"
1424 : "dblt %0,%l1\n\tjlt %l2",
1429 output_asm_insn (MOTOROLA
1430 ? "dbcs %0,%l1\n\tjbcs %l2"
1431 : "dbcs %0,%l1\n\tjcs %l2",
1436 output_asm_insn (MOTOROLA
1437 ? "dbge %0,%l1\n\tjbge %l2"
1438 : "dbge %0,%l1\n\tjge %l2",
1443 output_asm_insn (MOTOROLA
1444 ? "dbcc %0,%l1\n\tjbcc %l2"
1445 : "dbcc %0,%l1\n\tjcc %l2",
1450 output_asm_insn (MOTOROLA
1451 ? "dble %0,%l1\n\tjble %l2"
1452 : "dble %0,%l1\n\tjle %l2",
1457 output_asm_insn (MOTOROLA
1458 ? "dbls %0,%l1\n\tjbls %l2"
1459 : "dbls %0,%l1\n\tjls %l2",
1467 /* If the decrement is to be done in SImode, then we have
1468 to compensate for the fact that dbcc decrements in HImode. */
1469 switch (GET_MODE (operands
[0]))
1472 output_asm_insn (MOTOROLA
1473 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1474 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1487 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1490 enum rtx_code op_code
= GET_CODE (op
);
1492 /* This does not produce a useful cc. */
1495 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1496 below. Swap the operands and change the op if these requirements
1497 are not fulfilled. */
1498 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1502 operand1
= operand2
;
1504 op_code
= swap_condition (op_code
);
1506 loperands
[0] = operand1
;
1507 if (GET_CODE (operand1
) == REG
)
1508 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1510 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1511 if (operand2
!= const0_rtx
)
1513 loperands
[2] = operand2
;
1514 if (GET_CODE (operand2
) == REG
)
1515 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1517 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1519 loperands
[4] = gen_label_rtx ();
1520 if (operand2
!= const0_rtx
)
1522 output_asm_insn (MOTOROLA
1523 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1524 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1529 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1530 output_asm_insn ("tst%.l %0", loperands
);
1532 output_asm_insn ("cmp%.w #0,%0", loperands
);
1534 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1536 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1537 output_asm_insn ("tst%.l %1", loperands
);
1539 output_asm_insn ("cmp%.w #0,%1", loperands
);
1542 loperands
[5] = dest
;
1547 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1548 CODE_LABEL_NUMBER (loperands
[4]));
1549 output_asm_insn ("seq %5", loperands
);
1553 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1554 CODE_LABEL_NUMBER (loperands
[4]));
1555 output_asm_insn ("sne %5", loperands
);
1559 loperands
[6] = gen_label_rtx ();
1560 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1562 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1563 CODE_LABEL_NUMBER (loperands
[4]));
1564 output_asm_insn ("sgt %5", loperands
);
1565 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1566 CODE_LABEL_NUMBER (loperands
[6]));
1570 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1571 CODE_LABEL_NUMBER (loperands
[4]));
1572 output_asm_insn ("shi %5", loperands
);
1576 loperands
[6] = gen_label_rtx ();
1577 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1579 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1580 CODE_LABEL_NUMBER (loperands
[4]));
1581 output_asm_insn ("slt %5", loperands
);
1582 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1583 CODE_LABEL_NUMBER (loperands
[6]));
1587 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1588 CODE_LABEL_NUMBER (loperands
[4]));
1589 output_asm_insn ("scs %5", loperands
);
1593 loperands
[6] = gen_label_rtx ();
1594 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1596 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1597 CODE_LABEL_NUMBER (loperands
[4]));
1598 output_asm_insn ("sge %5", loperands
);
1599 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1600 CODE_LABEL_NUMBER (loperands
[6]));
1604 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1605 CODE_LABEL_NUMBER (loperands
[4]));
1606 output_asm_insn ("scc %5", loperands
);
1610 loperands
[6] = gen_label_rtx ();
1611 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1613 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1614 CODE_LABEL_NUMBER (loperands
[4]));
1615 output_asm_insn ("sle %5", loperands
);
1616 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1617 CODE_LABEL_NUMBER (loperands
[6]));
1621 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1622 CODE_LABEL_NUMBER (loperands
[4]));
1623 output_asm_insn ("sls %5", loperands
);
1633 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1635 operands
[0] = countop
;
1636 operands
[1] = dataop
;
1638 if (GET_CODE (countop
) == CONST_INT
)
1640 register int count
= INTVAL (countop
);
1641 /* If COUNT is bigger than size of storage unit in use,
1642 advance to the containing unit of same size. */
1643 if (count
> signpos
)
1645 int offset
= (count
& ~signpos
) / 8;
1646 count
= count
& signpos
;
1647 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1649 if (count
== signpos
)
1650 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1652 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1654 /* These three statements used to use next_insns_test_no...
1655 but it appears that this should do the same job. */
1657 && next_insn_tests_no_inequality (insn
))
1660 && next_insn_tests_no_inequality (insn
))
1663 && next_insn_tests_no_inequality (insn
))
1666 cc_status
.flags
= CC_NOT_NEGATIVE
;
1668 return "btst %0,%1";
1671 /* Legitimize PIC addresses. If the address is already
1672 position-independent, we return ORIG. Newly generated
1673 position-independent addresses go to REG. If we need more
1674 than one register, we lose.
1676 An address is legitimized by making an indirect reference
1677 through the Global Offset Table with the name of the symbol
1680 The assembler and linker are responsible for placing the
1681 address of the symbol in the GOT. The function prologue
1682 is responsible for initializing a5 to the starting address
1685 The assembler is also responsible for translating a symbol name
1686 into a constant displacement from the start of the GOT.
1688 A quick example may make things a little clearer:
1690 When not generating PIC code to store the value 12345 into _foo
1691 we would generate the following code:
1695 When generating PIC two transformations are made. First, the compiler
1696 loads the address of foo into a register. So the first transformation makes:
1701 The code in movsi will intercept the lea instruction and call this
1702 routine which will transform the instructions into:
1704 movel a5@(_foo:w), a0
1708 That (in a nutshell) is how *all* symbol and label references are
1712 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1717 /* First handle a simple SYMBOL_REF or LABEL_REF */
1718 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1722 pic_ref
= gen_rtx_MEM (Pmode
,
1723 gen_rtx_PLUS (Pmode
,
1724 pic_offset_table_rtx
, orig
));
1725 current_function_uses_pic_offset_table
= 1;
1726 MEM_READONLY_P (pic_ref
) = 1;
1727 emit_move_insn (reg
, pic_ref
);
1730 else if (GET_CODE (orig
) == CONST
)
1734 /* Make sure this has not already been legitimized. */
1735 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1736 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1741 /* legitimize both operands of the PLUS */
1742 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1744 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1745 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1746 base
== reg
? 0 : reg
);
1748 if (GET_CODE (orig
) == CONST_INT
)
1749 return plus_constant (base
, INTVAL (orig
));
1750 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1751 /* Likewise, should we set special REG_NOTEs here? */
1757 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1759 static CONST_METHOD
const_method (rtx
);
1761 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1764 const_method (rtx constant
)
1769 i
= INTVAL (constant
);
1773 /* The ColdFire doesn't have byte or word operations. */
1774 /* FIXME: This may not be useful for the m68060 either. */
1775 if (!TARGET_COLDFIRE
)
1777 /* if -256 < N < 256 but N is not in range for a moveq
1778 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1779 if (USE_MOVQ (i
^ 0xff))
1781 /* Likewise, try with not.w */
1782 if (USE_MOVQ (i
^ 0xffff))
1784 /* This is the only value where neg.w is useful */
1789 /* Try also with swap. */
1791 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1796 /* Try using MVZ/MVS with an immediate value to load constants. */
1797 if (i
>= 0 && i
<= 65535)
1799 if (i
>= -32768 && i
<= 32767)
1803 /* Otherwise, use move.l */
1808 const_int_cost (rtx constant
)
1810 switch (const_method (constant
))
1813 /* Constants between -128 and 127 are cheap due to moveq. */
1821 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1831 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1836 /* Constant zero is super cheap due to clr instruction. */
1837 if (x
== const0_rtx
)
1840 *total
= const_int_cost (x
);
1850 /* Make 0.0 cheaper than other floating constants to
1851 encourage creating tstsf and tstdf insns. */
1852 if (outer_code
== COMPARE
1853 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1859 /* These are vaguely right for a 68020. */
1860 /* The costs for long multiply have been adjusted to work properly
1861 in synth_mult on the 68020, relative to an average of the time
1862 for add and the time for shift, taking away a little more because
1863 sometimes move insns are needed. */
1864 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1870 : TARGET_COLDFIRE ? 3 : 13)
1875 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1876 : TARGET_COLDFIRE ? 2 : 8)
1879 (TARGET_CF_HWDIV ? 11 \
1880 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1883 /* An lea costs about three times as much as a simple add. */
1884 if (GET_MODE (x
) == SImode
1885 && GET_CODE (XEXP (x
, 1)) == REG
1886 && GET_CODE (XEXP (x
, 0)) == MULT
1887 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1888 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1889 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1890 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1891 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1893 /* lea an@(dx:l:i),am */
1894 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1904 *total
= COSTS_N_INSNS(1);
1909 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1911 if (INTVAL (XEXP (x
, 1)) < 16)
1912 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1914 /* We're using clrw + swap for these cases. */
1915 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1918 *total
= COSTS_N_INSNS (10); /* Worst case. */
1921 /* A shift by a big integer takes an extra instruction. */
1922 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1923 && (INTVAL (XEXP (x
, 1)) == 16))
1925 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1928 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1929 && !(INTVAL (XEXP (x
, 1)) > 0
1930 && INTVAL (XEXP (x
, 1)) <= 8))
1932 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1938 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1939 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1940 && GET_MODE (x
) == SImode
)
1941 *total
= COSTS_N_INSNS (MULW_COST
);
1942 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1943 *total
= COSTS_N_INSNS (MULW_COST
);
1945 *total
= COSTS_N_INSNS (MULL_COST
);
1952 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1953 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1954 else if (TARGET_CF_HWDIV
)
1955 *total
= COSTS_N_INSNS (18);
1957 *total
= COSTS_N_INSNS (43); /* div.l */
1966 output_move_const_into_data_reg (rtx
*operands
)
1970 i
= INTVAL (operands
[1]);
1971 switch (const_method (operands
[1]))
1974 return "mvzw %1,%0";
1976 return "mvsw %1,%0";
1978 return "moveq %1,%0";
1981 operands
[1] = GEN_INT (i
^ 0xff);
1982 return "moveq %1,%0\n\tnot%.b %0";
1985 operands
[1] = GEN_INT (i
^ 0xffff);
1986 return "moveq %1,%0\n\tnot%.w %0";
1989 return "moveq #-128,%0\n\tneg%.w %0";
1994 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1995 return "moveq %1,%0\n\tswap %0";
1998 return "move%.l %1,%0";
2004 /* Return 1 if 'constant' can be represented by
2005 mov3q on a ColdFire V4 core. */
2007 valid_mov3q_const (rtx constant
)
2011 if (TARGET_ISAB
&& GET_CODE (constant
) == CONST_INT
)
2013 i
= INTVAL (constant
);
2014 if (i
== -1 || (i
>= 1 && i
<= 7))
2022 output_move_simode_const (rtx
*operands
)
2024 if (operands
[1] == const0_rtx
2025 && (DATA_REG_P (operands
[0])
2026 || GET_CODE (operands
[0]) == MEM
)
2027 /* clr insns on 68000 read before writing. */
2028 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2029 || !(GET_CODE (operands
[0]) == MEM
2030 && MEM_VOLATILE_P (operands
[0]))))
2032 else if ((GET_MODE (operands
[0]) == SImode
)
2033 && valid_mov3q_const (operands
[1]))
2034 return "mov3q%.l %1,%0";
2035 else if (operands
[1] == const0_rtx
2036 && ADDRESS_REG_P (operands
[0]))
2037 return "sub%.l %0,%0";
2038 else if (DATA_REG_P (operands
[0]))
2039 return output_move_const_into_data_reg (operands
);
2040 else if (ADDRESS_REG_P (operands
[0])
2041 && INTVAL (operands
[1]) < 0x8000
2042 && INTVAL (operands
[1]) >= -0x8000)
2044 if (valid_mov3q_const (operands
[1]))
2045 return "mov3q%.l %1,%0";
2046 return "move%.w %1,%0";
2048 else if (GET_CODE (operands
[0]) == MEM
2049 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2050 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2051 && INTVAL (operands
[1]) < 0x8000
2052 && INTVAL (operands
[1]) >= -0x8000)
2054 if (valid_mov3q_const (operands
[1]))
2055 return "mov3q%.l %1,%-";
2058 return "move%.l %1,%0";
2062 output_move_simode (rtx
*operands
)
2064 if (GET_CODE (operands
[1]) == CONST_INT
)
2065 return output_move_simode_const (operands
);
2066 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2067 || GET_CODE (operands
[1]) == CONST
)
2068 && push_operand (operands
[0], SImode
))
2070 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2071 || GET_CODE (operands
[1]) == CONST
)
2072 && ADDRESS_REG_P (operands
[0]))
2073 return "lea %a1,%0";
2074 return "move%.l %1,%0";
2078 output_move_himode (rtx
*operands
)
2080 if (GET_CODE (operands
[1]) == CONST_INT
)
2082 if (operands
[1] == const0_rtx
2083 && (DATA_REG_P (operands
[0])
2084 || GET_CODE (operands
[0]) == MEM
)
2085 /* clr insns on 68000 read before writing. */
2086 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2087 || !(GET_CODE (operands
[0]) == MEM
2088 && MEM_VOLATILE_P (operands
[0]))))
2090 else if (operands
[1] == const0_rtx
2091 && ADDRESS_REG_P (operands
[0]))
2092 return "sub%.l %0,%0";
2093 else if (DATA_REG_P (operands
[0])
2094 && INTVAL (operands
[1]) < 128
2095 && INTVAL (operands
[1]) >= -128)
2096 return "moveq %1,%0";
2097 else if (INTVAL (operands
[1]) < 0x8000
2098 && INTVAL (operands
[1]) >= -0x8000)
2099 return "move%.w %1,%0";
2101 else if (CONSTANT_P (operands
[1]))
2102 return "move%.l %1,%0";
2103 /* Recognize the insn before a tablejump, one that refers
2104 to a table of offsets. Such an insn will need to refer
2105 to a label on the insn. So output one. Use the label-number
2106 of the table of offsets to generate this label. This code,
2107 and similar code below, assumes that there will be at most one
2108 reference to each table. */
2109 if (GET_CODE (operands
[1]) == MEM
2110 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2111 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2112 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2114 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2116 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2117 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2119 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2120 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2122 return "move%.w %1,%0";
2126 output_move_qimode (rtx
*operands
)
2128 /* 68k family always modifies the stack pointer by at least 2, even for
2129 byte pushes. The 5200 (ColdFire) does not do this. */
2131 /* This case is generated by pushqi1 pattern now. */
2132 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2133 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2134 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2135 && ! ADDRESS_REG_P (operands
[1])
2136 && ! TARGET_COLDFIRE
));
2138 /* clr and st insns on 68000 read before writing. */
2139 if (!ADDRESS_REG_P (operands
[0])
2140 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2141 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2143 if (operands
[1] == const0_rtx
)
2145 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2146 && GET_CODE (operands
[1]) == CONST_INT
2147 && (INTVAL (operands
[1]) & 255) == 255)
2153 if (GET_CODE (operands
[1]) == CONST_INT
2154 && DATA_REG_P (operands
[0])
2155 && INTVAL (operands
[1]) < 128
2156 && INTVAL (operands
[1]) >= -128)
2157 return "moveq %1,%0";
2158 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2159 return "sub%.l %0,%0";
2160 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2161 return "move%.l %1,%0";
2162 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2163 from address registers. */
2164 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2165 return "move%.w %1,%0";
2166 return "move%.b %1,%0";
2170 output_move_stricthi (rtx
*operands
)
2172 if (operands
[1] == const0_rtx
2173 /* clr insns on 68000 read before writing. */
2174 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2175 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2177 return "move%.w %1,%0";
2181 output_move_strictqi (rtx
*operands
)
2183 if (operands
[1] == const0_rtx
2184 /* clr insns on 68000 read before writing. */
2185 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2186 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2188 return "move%.b %1,%0";
2191 /* Return the best assembler insn template
2192 for moving operands[1] into operands[0] as a fullword. */
2195 singlemove_string (rtx
*operands
)
2197 if (GET_CODE (operands
[1]) == CONST_INT
)
2198 return output_move_simode_const (operands
);
2199 return "move%.l %1,%0";
2203 /* Output assembler code to perform a doubleword move insn
2204 with operands OPERANDS. */
2207 output_move_double (rtx
*operands
)
2211 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2216 rtx addreg0
= 0, addreg1
= 0;
2217 int dest_overlapped_low
= 0;
2218 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2223 /* First classify both operands. */
2225 if (REG_P (operands
[0]))
2227 else if (offsettable_memref_p (operands
[0]))
2229 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2231 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2233 else if (GET_CODE (operands
[0]) == MEM
)
2238 if (REG_P (operands
[1]))
2240 else if (CONSTANT_P (operands
[1]))
2242 else if (offsettable_memref_p (operands
[1]))
2244 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2246 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2248 else if (GET_CODE (operands
[1]) == MEM
)
2253 /* Check for the cases that the operand constraints are not supposed
2254 to allow to happen. Generating code for these cases is
2256 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2258 /* If one operand is decrementing and one is incrementing
2259 decrement the former register explicitly
2260 and change that operand into ordinary indexing. */
2262 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2264 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2266 output_asm_insn ("sub%.l #12,%0", operands
);
2268 output_asm_insn ("subq%.l #8,%0", operands
);
2269 if (GET_MODE (operands
[1]) == XFmode
)
2270 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2271 else if (GET_MODE (operands
[0]) == DFmode
)
2272 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2274 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2277 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2279 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2281 output_asm_insn ("sub%.l #12,%1", operands
);
2283 output_asm_insn ("subq%.l #8,%1", operands
);
2284 if (GET_MODE (operands
[1]) == XFmode
)
2285 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2286 else if (GET_MODE (operands
[1]) == DFmode
)
2287 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2289 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2293 /* If an operand is an unoffsettable memory ref, find a register
2294 we can increment temporarily to make it refer to the second word. */
2296 if (optype0
== MEMOP
)
2297 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2299 if (optype1
== MEMOP
)
2300 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2302 /* Ok, we can do one word at a time.
2303 Normally we do the low-numbered word first,
2304 but if either operand is autodecrementing then we
2305 do the high-numbered word first.
2307 In either case, set up in LATEHALF the operands to use
2308 for the high-numbered word and in some cases alter the
2309 operands in OPERANDS to be suitable for the low-numbered word. */
2313 if (optype0
== REGOP
)
2315 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2316 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2318 else if (optype0
== OFFSOP
)
2320 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2321 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2325 middlehalf
[0] = operands
[0];
2326 latehalf
[0] = operands
[0];
2329 if (optype1
== REGOP
)
2331 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2332 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2334 else if (optype1
== OFFSOP
)
2336 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2337 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2339 else if (optype1
== CNSTOP
)
2341 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2346 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2347 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2348 operands
[1] = GEN_INT (l
[0]);
2349 middlehalf
[1] = GEN_INT (l
[1]);
2350 latehalf
[1] = GEN_INT (l
[2]);
2354 /* No non-CONST_DOUBLE constant should ever appear
2356 gcc_assert (!CONSTANT_P (operands
[1]));
2361 middlehalf
[1] = operands
[1];
2362 latehalf
[1] = operands
[1];
2366 /* size is not 12: */
2368 if (optype0
== REGOP
)
2369 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2370 else if (optype0
== OFFSOP
)
2371 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2373 latehalf
[0] = operands
[0];
2375 if (optype1
== REGOP
)
2376 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2377 else if (optype1
== OFFSOP
)
2378 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2379 else if (optype1
== CNSTOP
)
2380 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2382 latehalf
[1] = operands
[1];
2385 /* If insn is effectively movd N(sp),-(sp) then we will do the
2386 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2387 for the low word as well, to compensate for the first decrement of sp. */
2388 if (optype0
== PUSHOP
2389 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2390 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2391 operands
[1] = middlehalf
[1] = latehalf
[1];
2393 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2394 if the upper part of reg N does not appear in the MEM, arrange to
2395 emit the move late-half first. Otherwise, compute the MEM address
2396 into the upper part of N and use that as a pointer to the memory
2398 if (optype0
== REGOP
2399 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2401 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2403 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2404 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2406 /* If both halves of dest are used in the src memory address,
2407 compute the address into latehalf of dest.
2408 Note that this can't happen if the dest is two data regs. */
2410 xops
[0] = latehalf
[0];
2411 xops
[1] = XEXP (operands
[1], 0);
2412 output_asm_insn ("lea %a1,%0", xops
);
2413 if (GET_MODE (operands
[1]) == XFmode
)
2415 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2416 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2417 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2421 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2422 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2426 && reg_overlap_mentioned_p (middlehalf
[0],
2427 XEXP (operands
[1], 0)))
2429 /* Check for two regs used by both source and dest.
2430 Note that this can't happen if the dest is all data regs.
2431 It can happen if the dest is d6, d7, a0.
2432 But in that case, latehalf is an addr reg, so
2433 the code at compadr does ok. */
2435 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2436 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2439 /* JRV says this can't happen: */
2440 gcc_assert (!addreg0
&& !addreg1
);
2442 /* Only the middle reg conflicts; simply put it last. */
2443 output_asm_insn (singlemove_string (operands
), operands
);
2444 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2445 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2448 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2449 /* If the low half of dest is mentioned in the source memory
2450 address, the arrange to emit the move late half first. */
2451 dest_overlapped_low
= 1;
2454 /* If one or both operands autodecrementing,
2455 do the two words, high-numbered first. */
2457 /* Likewise, the first move would clobber the source of the second one,
2458 do them in the other order. This happens only for registers;
2459 such overlap can't happen in memory unless the user explicitly
2460 sets it up, and that is an undefined circumstance. */
2462 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2463 || (optype0
== REGOP
&& optype1
== REGOP
2464 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2465 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2466 || dest_overlapped_low
)
2468 /* Make any unoffsettable addresses point at high-numbered word. */
2472 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2474 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2479 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2481 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2485 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2487 /* Undo the adds we just did. */
2489 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2491 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2495 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2497 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2499 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2502 /* Do low-numbered word. */
2503 return singlemove_string (operands
);
2506 /* Normal case: do the two words, low-numbered first. */
2508 output_asm_insn (singlemove_string (operands
), operands
);
2510 /* Do the middle one of the three words for long double */
2514 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2516 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2518 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2521 /* Make any unoffsettable addresses point at high-numbered word. */
2523 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2525 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2528 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2530 /* Undo the adds we just did. */
2534 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2536 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2541 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2543 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2550 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2551 new rtx with the correct mode. */
2554 force_mode (enum machine_mode mode
, rtx orig
)
2556 if (mode
== GET_MODE (orig
))
2559 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2562 return gen_rtx_REG (mode
, REGNO (orig
));
2566 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2568 return reg_renumber
&& FP_REG_P (op
);
2571 /* Emit insns to move operands[1] into operands[0].
2573 Return 1 if we have written out everything that needs to be done to
2574 do the move. Otherwise, return 0 and the caller will emit the move
2577 Note SCRATCH_REG may not be in the proper mode depending on how it
2578 will be used. This routine is responsible for creating a new copy
2579 of SCRATCH_REG in the proper mode. */
2582 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2584 register rtx operand0
= operands
[0];
2585 register rtx operand1
= operands
[1];
2589 && reload_in_progress
&& GET_CODE (operand0
) == REG
2590 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2591 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2592 else if (scratch_reg
2593 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2594 && GET_CODE (SUBREG_REG (operand0
)) == REG
2595 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2597 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2598 the code which tracks sets/uses for delete_output_reload. */
2599 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2600 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2601 SUBREG_BYTE (operand0
));
2602 operand0
= alter_subreg (&temp
);
2606 && reload_in_progress
&& GET_CODE (operand1
) == REG
2607 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2608 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2609 else if (scratch_reg
2610 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2611 && GET_CODE (SUBREG_REG (operand1
)) == REG
2612 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2614 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2615 the code which tracks sets/uses for delete_output_reload. */
2616 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2617 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2618 SUBREG_BYTE (operand1
));
2619 operand1
= alter_subreg (&temp
);
2622 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2623 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2624 != XEXP (operand0
, 0)))
2625 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2626 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2627 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2628 != XEXP (operand1
, 0)))
2629 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2631 /* Handle secondary reloads for loads/stores of FP registers where
2632 the address is symbolic by using the scratch register */
2633 if (fp_reg_operand (operand0
, mode
)
2634 && ((GET_CODE (operand1
) == MEM
2635 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2636 || ((GET_CODE (operand1
) == SUBREG
2637 && GET_CODE (XEXP (operand1
, 0)) == MEM
2638 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2641 if (GET_CODE (operand1
) == SUBREG
)
2642 operand1
= XEXP (operand1
, 0);
2644 /* SCRATCH_REG will hold an address. We want
2645 it in SImode regardless of what mode it was originally given
2647 scratch_reg
= force_mode (SImode
, scratch_reg
);
2649 /* D might not fit in 14 bits either; for such cases load D into
2651 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2653 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2654 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2656 XEXP (XEXP (operand1
, 0), 0),
2660 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2661 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2662 gen_rtx_MEM (mode
, scratch_reg
)));
2665 else if (fp_reg_operand (operand1
, mode
)
2666 && ((GET_CODE (operand0
) == MEM
2667 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2668 || ((GET_CODE (operand0
) == SUBREG
)
2669 && GET_CODE (XEXP (operand0
, 0)) == MEM
2670 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2673 if (GET_CODE (operand0
) == SUBREG
)
2674 operand0
= XEXP (operand0
, 0);
2676 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2677 it in SIMODE regardless of what mode it was originally given
2679 scratch_reg
= force_mode (SImode
, scratch_reg
);
2681 /* D might not fit in 14 bits either; for such cases load D into
2683 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2685 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2686 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2689 XEXP (XEXP (operand0
, 0),
2694 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2695 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2699 /* Handle secondary reloads for loads of FP registers from constant
2700 expressions by forcing the constant into memory.
2702 use scratch_reg to hold the address of the memory location.
2704 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2705 NO_REGS when presented with a const_int and an register class
2706 containing only FP registers. Doing so unfortunately creates
2707 more problems than it solves. Fix this for 2.5. */
2708 else if (fp_reg_operand (operand0
, mode
)
2709 && CONSTANT_P (operand1
)
2714 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2715 it in SIMODE regardless of what mode it was originally given
2717 scratch_reg
= force_mode (SImode
, scratch_reg
);
2719 /* Force the constant into memory and put the address of the
2720 memory location into scratch_reg. */
2721 xoperands
[0] = scratch_reg
;
2722 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2723 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2725 /* Now load the destination register. */
2726 emit_insn (gen_rtx_SET (mode
, operand0
,
2727 gen_rtx_MEM (mode
, scratch_reg
)));
2731 /* Now have insn-emit do whatever it normally does. */
2735 /* Return a REG that occurs in ADDR with coefficient 1.
2736 ADDR can be effectively incremented by incrementing REG. */
2739 find_addr_reg (rtx addr
)
2741 while (GET_CODE (addr
) == PLUS
)
2743 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2744 addr
= XEXP (addr
, 0);
2745 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2746 addr
= XEXP (addr
, 1);
2747 else if (CONSTANT_P (XEXP (addr
, 0)))
2748 addr
= XEXP (addr
, 1);
2749 else if (CONSTANT_P (XEXP (addr
, 1)))
2750 addr
= XEXP (addr
, 0);
2754 gcc_assert (GET_CODE (addr
) == REG
);
2758 /* Output assembler code to perform a 32-bit 3-operand add. */
2761 output_addsi3 (rtx
*operands
)
2763 if (! operands_match_p (operands
[0], operands
[1]))
2765 if (!ADDRESS_REG_P (operands
[1]))
2767 rtx tmp
= operands
[1];
2769 operands
[1] = operands
[2];
2773 /* These insns can result from reloads to access
2774 stack slots over 64k from the frame pointer. */
2775 if (GET_CODE (operands
[2]) == CONST_INT
2776 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2777 return "move%.l %2,%0\n\tadd%.l %1,%0";
2778 if (GET_CODE (operands
[2]) == REG
)
2779 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2780 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2782 if (GET_CODE (operands
[2]) == CONST_INT
)
2784 if (INTVAL (operands
[2]) > 0
2785 && INTVAL (operands
[2]) <= 8)
2786 return "addq%.l %2,%0";
2787 if (INTVAL (operands
[2]) < 0
2788 && INTVAL (operands
[2]) >= -8)
2790 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2791 return "subq%.l %2,%0";
2793 /* On the CPU32 it is faster to use two addql instructions to
2794 add a small integer (8 < N <= 16) to a register.
2795 Likewise for subql. */
2796 if (TUNE_CPU32
&& REG_P (operands
[0]))
2798 if (INTVAL (operands
[2]) > 8
2799 && INTVAL (operands
[2]) <= 16)
2801 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2802 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2804 if (INTVAL (operands
[2]) < -8
2805 && INTVAL (operands
[2]) >= -16)
2807 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2808 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2811 if (ADDRESS_REG_P (operands
[0])
2812 && INTVAL (operands
[2]) >= -0x8000
2813 && INTVAL (operands
[2]) < 0x8000)
2816 return "add%.w %2,%0";
2818 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2821 return "add%.l %2,%0";
2824 /* Store in cc_status the expressions that the condition codes will
2825 describe after execution of an instruction whose pattern is EXP.
2826 Do not alter them if the instruction would not alter the cc's. */
2828 /* On the 68000, all the insns to store in an address register fail to
2829 set the cc's. However, in some cases these instructions can make it
2830 possibly invalid to use the saved cc's. In those cases we clear out
2831 some or all of the saved cc's so they won't be used. */
2834 notice_update_cc (rtx exp
, rtx insn
)
2836 if (GET_CODE (exp
) == SET
)
2838 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2840 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2842 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2843 cc_status
.value1
= 0;
2844 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2845 cc_status
.value2
= 0;
2847 else if (!FP_REG_P (SET_DEST (exp
))
2848 && SET_DEST (exp
) != cc0_rtx
2849 && (FP_REG_P (SET_SRC (exp
))
2850 || GET_CODE (SET_SRC (exp
)) == FIX
2851 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2852 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2854 /* A pair of move insns doesn't produce a useful overall cc. */
2855 else if (!FP_REG_P (SET_DEST (exp
))
2856 && !FP_REG_P (SET_SRC (exp
))
2857 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2858 && (GET_CODE (SET_SRC (exp
)) == REG
2859 || GET_CODE (SET_SRC (exp
)) == MEM
2860 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2862 else if (SET_DEST (exp
) != pc_rtx
)
2864 cc_status
.flags
= 0;
2865 cc_status
.value1
= SET_DEST (exp
);
2866 cc_status
.value2
= SET_SRC (exp
);
2869 else if (GET_CODE (exp
) == PARALLEL
2870 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2872 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2873 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2875 if (ADDRESS_REG_P (dest
))
2877 else if (dest
!= pc_rtx
)
2879 cc_status
.flags
= 0;
2880 cc_status
.value1
= dest
;
2881 cc_status
.value2
= src
;
2886 if (cc_status
.value2
!= 0
2887 && ADDRESS_REG_P (cc_status
.value2
)
2888 && GET_MODE (cc_status
.value2
) == QImode
)
2890 if (cc_status
.value2
!= 0)
2891 switch (GET_CODE (cc_status
.value2
))
2893 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2894 case ROTATE
: case ROTATERT
:
2895 /* These instructions always clear the overflow bit, and set
2896 the carry to the bit shifted out. */
2897 /* ??? We don't currently have a way to signal carry not valid,
2898 nor do we check for it in the branch insns. */
2902 case PLUS
: case MINUS
: case MULT
:
2903 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2904 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2905 cc_status
.flags
|= CC_NO_OVERFLOW
;
2908 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2909 ends with a move insn moving r2 in r2's mode.
2910 Thus, the cc's are set for r2.
2911 This can set N bit spuriously. */
2912 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2917 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2919 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2920 cc_status
.value2
= 0;
2921 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2922 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2923 cc_status
.flags
= CC_IN_68881
;
2927 output_move_const_double (rtx
*operands
)
2929 int code
= standard_68881_constant_p (operands
[1]);
2933 static char buf
[40];
2935 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2938 return "fmove%.d %1,%0";
2942 output_move_const_single (rtx
*operands
)
2944 int code
= standard_68881_constant_p (operands
[1]);
2948 static char buf
[40];
2950 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2953 return "fmove%.s %f1,%0";
2956 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2957 from the "fmovecr" instruction.
2958 The value, anded with 0xff, gives the code to use in fmovecr
2959 to get the desired constant. */
2961 /* This code has been fixed for cross-compilation. */
2963 static int inited_68881_table
= 0;
2965 static const char *const strings_68881
[7] = {
2975 static const int codes_68881
[7] = {
2985 REAL_VALUE_TYPE values_68881
[7];
2987 /* Set up values_68881 array by converting the decimal values
2988 strings_68881 to binary. */
2991 init_68881_table (void)
2995 enum machine_mode mode
;
2998 for (i
= 0; i
< 7; i
++)
3002 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3003 values_68881
[i
] = r
;
3005 inited_68881_table
= 1;
3009 standard_68881_constant_p (rtx x
)
3014 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3015 used at all on those chips. */
3019 if (! inited_68881_table
)
3020 init_68881_table ();
3022 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3024 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3026 for (i
= 0; i
< 6; i
++)
3028 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3029 return (codes_68881
[i
]);
3032 if (GET_MODE (x
) == SFmode
)
3035 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3036 return (codes_68881
[6]);
3038 /* larger powers of ten in the constants ram are not used
3039 because they are not equal to a `double' C constant. */
3043 /* If X is a floating-point constant, return the logarithm of X base 2,
3044 or 0 if X is not a power of 2. */
3047 floating_exact_log2 (rtx x
)
3049 REAL_VALUE_TYPE r
, r1
;
3052 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3054 if (REAL_VALUES_LESS (r
, dconst1
))
3057 exp
= real_exponent (&r
);
3058 real_2expN (&r1
, exp
);
3059 if (REAL_VALUES_EQUAL (r1
, r
))
3065 /* A C compound statement to output to stdio stream STREAM the
3066 assembler syntax for an instruction operand X. X is an RTL
3069 CODE is a value that can be used to specify one of several ways
3070 of printing the operand. It is used when identical operands
3071 must be printed differently depending on the context. CODE
3072 comes from the `%' specification that was used to request
3073 printing of the operand. If the specification was just `%DIGIT'
3074 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3075 is the ASCII code for LTR.
3077 If X is a register, this macro should print the register's name.
3078 The names can be found in an array `reg_names' whose type is
3079 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3081 When the machine description has a specification `%PUNCT' (a `%'
3082 followed by a punctuation character), this macro is called with
3083 a null pointer for X and the punctuation character for CODE.
3085 The m68k specific codes are:
3087 '.' for dot needed in Motorola-style opcode names.
3088 '-' for an operand pushing on the stack:
3089 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3090 '+' for an operand pushing on the stack:
3091 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3092 '@' for a reference to the top word on the stack:
3093 sp@, (sp) or (%sp) depending on the style of syntax.
3094 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3095 but & in SGS syntax).
3096 '!' for the cc register (used in an `and to cc' insn).
3097 '$' for the letter `s' in an op code, but only on the 68040.
3098 '&' for the letter `d' in an op code, but only on the 68040.
3099 '/' for register prefix needed by longlong.h.
3101 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3102 'd' to force memory addressing to be absolute, not relative.
3103 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3104 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3105 or print pair of registers as rx:ry.
3106 'p' print an address with @PLTPC attached, but only if the operand
3107 is not locally-bound. */
3110 print_operand (FILE *file
, rtx op
, int letter
)
3115 fprintf (file
, ".");
3117 else if (letter
== '#')
3118 asm_fprintf (file
, "%I");
3119 else if (letter
== '-')
3120 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3121 else if (letter
== '+')
3122 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3123 else if (letter
== '@')
3124 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3125 else if (letter
== '!')
3126 asm_fprintf (file
, "%Rfpcr");
3127 else if (letter
== '$')
3130 fprintf (file
, "s");
3132 else if (letter
== '&')
3135 fprintf (file
, "d");
3137 else if (letter
== '/')
3138 asm_fprintf (file
, "%R");
3139 else if (letter
== 'p')
3141 output_addr_const (file
, op
);
3142 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3143 fprintf (file
, "@PLTPC");
3145 else if (GET_CODE (op
) == REG
)
3148 /* Print out the second register name of a register pair.
3149 I.e., R (6) => 7. */
3150 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3152 fputs (M68K_REGNAME(REGNO (op
)), file
);
3154 else if (GET_CODE (op
) == MEM
)
3156 output_address (XEXP (op
, 0));
3157 if (letter
== 'd' && ! TARGET_68020
3158 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3159 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3160 && INTVAL (XEXP (op
, 0)) < 0x8000
3161 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3162 fprintf (file
, MOTOROLA
? ".l" : ":l");
3164 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3167 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3168 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3170 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3173 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3174 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3176 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3179 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3180 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3184 /* Use `print_operand_address' instead of `output_addr_const'
3185 to ensure that we print relevant PIC stuff. */
3186 asm_fprintf (file
, "%I");
3188 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3189 print_operand_address (file
, op
);
3191 output_addr_const (file
, op
);
3196 /* A C compound statement to output to stdio stream STREAM the
3197 assembler syntax for an instruction operand that is a memory
3198 reference whose address is ADDR. ADDR is an RTL expression.
3200 Note that this contains a kludge that knows that the only reason
3201 we have an address (plus (label_ref...) (reg...)) when not generating
3202 PIC code is in the insn before a tablejump, and we know that m68k.md
3203 generates a label LInnn: on such an insn.
3205 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3206 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3208 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3209 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3210 we want. This difference can be accommodated by using an assembler
3211 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3212 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3213 macro. See m68k/sgs.h for an example; for versions without the bug.
3214 Some assemblers refuse all the above solutions. The workaround is to
3215 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3218 They also do not like things like "pea 1.w", so we simple leave off
3219 the .w on small constants.
3221 This routine is responsible for distinguishing between -fpic and -fPIC
3222 style relocations in an address. When generating -fpic code the
3223 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3224 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3227 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3228 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3229 #else /* !MOTOROLA */
3230 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3231 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3232 #endif /* !MOTOROLA */
3235 print_operand_address (FILE *file
, rtx addr
)
3237 register rtx reg1
, reg2
, breg
, ireg
;
3240 switch (GET_CODE (addr
))
3243 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3246 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3247 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3250 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3251 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3254 reg1
= reg2
= ireg
= breg
= offset
= 0;
3255 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3257 offset
= XEXP (addr
, 0);
3258 addr
= XEXP (addr
, 1);
3260 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3262 offset
= XEXP (addr
, 1);
3263 addr
= XEXP (addr
, 0);
3265 if (GET_CODE (addr
) != PLUS
)
3269 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3271 reg1
= XEXP (addr
, 0);
3272 addr
= XEXP (addr
, 1);
3274 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3276 reg1
= XEXP (addr
, 1);
3277 addr
= XEXP (addr
, 0);
3279 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3281 reg1
= XEXP (addr
, 0);
3282 addr
= XEXP (addr
, 1);
3284 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3286 reg1
= XEXP (addr
, 1);
3287 addr
= XEXP (addr
, 0);
3289 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3291 reg1
= XEXP (addr
, 0);
3292 addr
= XEXP (addr
, 1);
3294 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3296 reg1
= XEXP (addr
, 1);
3297 addr
= XEXP (addr
, 0);
3299 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3300 || GET_CODE (addr
) == SIGN_EXTEND
)
3308 #if 0 /* for OLD_INDEXING */
3309 else if (GET_CODE (addr
) == PLUS
)
3311 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3313 reg2
= XEXP (addr
, 0);
3314 addr
= XEXP (addr
, 1);
3316 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3318 reg2
= XEXP (addr
, 1);
3319 addr
= XEXP (addr
, 0);
3328 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3329 || GET_CODE (reg1
) == MULT
))
3330 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3335 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3340 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3341 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3344 if (GET_CODE (ireg
) == MULT
)
3346 scale
= INTVAL (XEXP (ireg
, 1));
3347 ireg
= XEXP (ireg
, 0);
3349 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3351 ASM_OUTPUT_CASE_FETCH (file
,
3352 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3353 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3354 fprintf (file
, "w");
3358 ASM_OUTPUT_CASE_FETCH (file
,
3359 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3360 M68K_REGNAME (REGNO (ireg
)));
3361 fprintf (file
, "l");
3364 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3368 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3369 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3371 ASM_OUTPUT_CASE_FETCH (file
,
3372 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3373 M68K_REGNAME (REGNO (breg
)));
3374 fprintf (file
, "l)");
3377 if (ireg
!= 0 || breg
!= 0)
3382 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3388 output_addr_const (file
, addr
);
3389 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3391 fprintf (file
, "@GOT");
3393 fprintf (file
, ".w");
3396 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3400 else /* !MOTOROLA */
3402 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3405 output_addr_const (file
, addr
);
3406 if (breg
== pic_offset_table_rtx
)
3410 fprintf (file
, ":w");
3413 fprintf (file
, ":l");
3422 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3424 scale
= INTVAL (XEXP (ireg
, 1));
3425 ireg
= XEXP (ireg
, 0);
3427 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3428 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3429 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3431 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3432 M68K_REGNAME (REGNO (ireg
)));
3434 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3438 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3439 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3441 ASM_OUTPUT_CASE_FETCH (file
,
3442 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3443 M68K_REGNAME (REGNO (reg1
)));
3444 fprintf (file
, "l)");
3447 /* FALL-THROUGH (is this really what we want?) */
3449 if (GET_CODE (addr
) == CONST_INT
3450 && INTVAL (addr
) < 0x8000
3451 && INTVAL (addr
) >= -0x8000)
3453 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3455 else if (GET_CODE (addr
) == CONST_INT
)
3457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3459 else if (TARGET_PCREL
)
3462 output_addr_const (file
, addr
);
3464 asm_fprintf (file
, ":w,%Rpc)");
3466 asm_fprintf (file
, ":l,%Rpc)");
3470 /* Special case for SYMBOL_REF if the symbol name ends in
3471 `.<letter>', this can be mistaken as a size suffix. Put
3472 the name in parentheses. */
3473 if (GET_CODE (addr
) == SYMBOL_REF
3474 && strlen (XSTR (addr
, 0)) > 2
3475 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3478 output_addr_const (file
, addr
);
3482 output_addr_const (file
, addr
);
3488 /* Check for cases where a clr insns can be omitted from code using
3489 strict_low_part sets. For example, the second clrl here is not needed:
3490 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3492 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3493 insn we are checking for redundancy. TARGET is the register set by the
3497 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3502 p
= prev_nonnote_insn (first_insn
);
3506 /* If it isn't an insn, then give up. */
3507 if (GET_CODE (p
) != INSN
)
3510 if (reg_set_p (target
, p
))
3512 rtx set
= single_set (p
);
3515 /* If it isn't an easy to recognize insn, then give up. */
3519 dest
= SET_DEST (set
);
3521 /* If this sets the entire target register to zero, then our
3522 first_insn is redundant. */
3523 if (rtx_equal_p (dest
, target
)
3524 && SET_SRC (set
) == const0_rtx
)
3526 else if (GET_CODE (dest
) == STRICT_LOW_PART
3527 && GET_CODE (XEXP (dest
, 0)) == REG
3528 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3529 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3530 <= GET_MODE_SIZE (mode
)))
3531 /* This is a strict low part set which modifies less than
3532 we are using, so it is safe. */
3538 p
= prev_nonnote_insn (p
);
3544 /* Operand predicates for implementing asymmetric pc-relative addressing
3545 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3546 when used as a source operand, but not as a destination operand.
3548 We model this by restricting the meaning of the basic predicates
3549 (general_operand, memory_operand, etc) to forbid the use of this
3550 addressing mode, and then define the following predicates that permit
3551 this addressing mode. These predicates can then be used for the
3552 source operands of the appropriate instructions.
3554 n.b. While it is theoretically possible to change all machine patterns
3555 to use this addressing more where permitted by the architecture,
3556 it has only been implemented for "common" cases: SImode, HImode, and
3557 QImode operands, and only for the principle operations that would
3558 require this addressing mode: data movement and simple integer operations.
3560 In parallel with these new predicates, two new constraint letters
3561 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3562 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3563 In the pcrel case 's' is only valid in combination with 'a' registers.
3564 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3565 of how these constraints are used.
3567 The use of these predicates is strictly optional, though patterns that
3568 don't will cause an extra reload register to be allocated where one
3571 lea (abc:w,%pc),%a0 ; need to reload address
3572 moveq &1,%d1 ; since write to pc-relative space
3573 movel %d1,%a0@ ; is not allowed
3575 lea (abc:w,%pc),%a1 ; no need to reload address here
3576 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3578 For more info, consult tiemann@cygnus.com.
3581 All of the ugliness with predicates and constraints is due to the
3582 simple fact that the m68k does not allow a pc-relative addressing
3583 mode as a destination. gcc does not distinguish between source and
3584 destination addresses. Hence, if we claim that pc-relative address
3585 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3586 end up with invalid code. To get around this problem, we left
3587 pc-relative modes as invalid addresses, and then added special
3588 predicates and constraints to accept them.
3590 A cleaner way to handle this is to modify gcc to distinguish
3591 between source and destination addresses. We can then say that
3592 pc-relative is a valid source address but not a valid destination
3593 address, and hopefully avoid a lot of the predicate and constraint
3594 hackery. Unfortunately, this would be a pretty big change. It would
3595 be a useful change for a number of ports, but there aren't any current
3596 plans to undertake this.
3598 ***************************************************************************/
3602 output_andsi3 (rtx
*operands
)
3605 if (GET_CODE (operands
[2]) == CONST_INT
3606 && (INTVAL (operands
[2]) | 0xffff) == -1
3607 && (DATA_REG_P (operands
[0])
3608 || offsettable_memref_p (operands
[0]))
3609 && !TARGET_COLDFIRE
)
3611 if (GET_CODE (operands
[0]) != REG
)
3612 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3613 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3614 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3616 if (operands
[2] == const0_rtx
)
3618 return "and%.w %2,%0";
3620 if (GET_CODE (operands
[2]) == CONST_INT
3621 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3622 && (DATA_REG_P (operands
[0])
3623 || offsettable_memref_p (operands
[0])))
3625 if (DATA_REG_P (operands
[0]))
3626 operands
[1] = GEN_INT (logval
);
3629 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3630 operands
[1] = GEN_INT (logval
% 8);
3632 /* This does not set condition codes in a standard way. */
3634 return "bclr %1,%0";
3636 return "and%.l %2,%0";
3640 output_iorsi3 (rtx
*operands
)
3642 register int logval
;
3643 if (GET_CODE (operands
[2]) == CONST_INT
3644 && INTVAL (operands
[2]) >> 16 == 0
3645 && (DATA_REG_P (operands
[0])
3646 || offsettable_memref_p (operands
[0]))
3647 && !TARGET_COLDFIRE
)
3649 if (GET_CODE (operands
[0]) != REG
)
3650 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3651 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3653 if (INTVAL (operands
[2]) == 0xffff)
3654 return "mov%.w %2,%0";
3655 return "or%.w %2,%0";
3657 if (GET_CODE (operands
[2]) == CONST_INT
3658 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3659 && (DATA_REG_P (operands
[0])
3660 || offsettable_memref_p (operands
[0])))
3662 if (DATA_REG_P (operands
[0]))
3663 operands
[1] = GEN_INT (logval
);
3666 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3667 operands
[1] = GEN_INT (logval
% 8);
3670 return "bset %1,%0";
3672 return "or%.l %2,%0";
3676 output_xorsi3 (rtx
*operands
)
3678 register int logval
;
3679 if (GET_CODE (operands
[2]) == CONST_INT
3680 && INTVAL (operands
[2]) >> 16 == 0
3681 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3682 && !TARGET_COLDFIRE
)
3684 if (! DATA_REG_P (operands
[0]))
3685 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3686 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3688 if (INTVAL (operands
[2]) == 0xffff)
3690 return "eor%.w %2,%0";
3692 if (GET_CODE (operands
[2]) == CONST_INT
3693 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3694 && (DATA_REG_P (operands
[0])
3695 || offsettable_memref_p (operands
[0])))
3697 if (DATA_REG_P (operands
[0]))
3698 operands
[1] = GEN_INT (logval
);
3701 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3702 operands
[1] = GEN_INT (logval
% 8);
3705 return "bchg %1,%0";
3707 return "eor%.l %2,%0";
3710 /* Return the instruction that should be used for a call to address X,
3711 which is known to be in operand 0. */
3716 if (symbolic_operand (x
, VOIDmode
))
3717 return m68k_symbolic_call
;
3722 #ifdef M68K_TARGET_COFF
3724 /* Output assembly to switch to section NAME with attribute FLAGS. */
3727 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3728 tree decl ATTRIBUTE_UNUSED
)
3732 if (flags
& SECTION_WRITE
)
3737 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3740 #endif /* M68K_TARGET_COFF */
3743 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3744 HOST_WIDE_INT delta
,
3745 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3751 if (delta
> 0 && delta
<= 8)
3752 asm_fprintf (file
, (MOTOROLA
3753 ? "\taddq.l %I%d,4(%Rsp)\n"
3754 : "\taddql %I%d,%Rsp@(4)\n"),
3756 else if (delta
< 0 && delta
>= -8)
3757 asm_fprintf (file
, (MOTOROLA
3758 ? "\tsubq.l %I%d,4(%Rsp)\n"
3759 : "\tsubql %I%d,%Rsp@(4)\n"),
3761 else if (TARGET_COLDFIRE
)
3763 /* ColdFire can't add/sub a constant to memory unless it is in
3764 the range of addq/subq. So load the value into %d0 and
3765 then add it to 4(%sp). */
3766 if (delta
>= -128 && delta
<= 127)
3767 asm_fprintf (file
, (MOTOROLA
3768 ? "\tmoveq.l %I%wd,%Rd0\n"
3769 : "\tmoveql %I%wd,%Rd0\n"),
3772 asm_fprintf (file
, (MOTOROLA
3773 ? "\tmove.l %I%wd,%Rd0\n"
3774 : "\tmovel %I%wd,%Rd0\n"),
3776 asm_fprintf (file
, (MOTOROLA
3777 ? "\tadd.l %Rd0,4(%Rsp)\n"
3778 : "\taddl %Rd0,%Rsp@(4)\n"));
3781 asm_fprintf (file
, (MOTOROLA
3782 ? "\tadd.l %I%wd,4(%Rsp)\n"
3783 : "\taddl %I%wd,%Rsp@(4)\n"),
3786 xops
[0] = DECL_RTL (function
);
3788 gcc_assert (MEM_P (xops
[0])
3789 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
3790 xops
[0] = XEXP (xops
[0], 0);
3792 fmt
= m68k_symbolic_jump
;
3793 if (m68k_symbolic_jump
== NULL
)
3794 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3796 output_asm_insn (fmt
, xops
);
3799 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3802 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3803 int incoming ATTRIBUTE_UNUSED
)
3805 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3808 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3810 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3811 unsigned int new_reg
)
3814 /* Interrupt functions can only use registers that have already been
3815 saved by the prologue, even if they would normally be
3818 if (m68k_interrupt_function_p (current_function_decl
)
3819 && !regs_ever_live
[new_reg
])
3825 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3826 On the 68000, the cpu registers can hold any mode except bytes in address
3827 registers, but the 68881 registers can hold only SFmode or DFmode. */
3829 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3831 if (DATA_REGNO_P (regno
))
3833 /* Data Registers, can hold aggregate if fits in. */
3834 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3837 else if (ADDRESS_REGNO_P (regno
))
3839 /* Address Registers, can't hold bytes, can hold aggregate if
3841 if (GET_MODE_SIZE (mode
) == 1)
3843 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3846 else if (FP_REGNO_P (regno
))
3848 /* FPU registers, hold float or complex float of long double or
3850 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3851 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3852 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3858 /* Return floating point values in a 68881 register. This makes 68881 code
3859 a little bit faster. It also makes -msoft-float code incompatible with
3860 hard-float code, so people have to be careful not to mix the two.
3861 For ColdFire it was decided the ABI incompatibility is undesirable.
3862 If there is need for a hard-float ABI it is probably worth doing it
3863 properly and also passing function arguments in FP registers. */
3865 m68k_libcall_value (enum machine_mode mode
)
3872 return gen_rtx_REG (mode
, 16);
3877 return gen_rtx_REG (mode
, 0);
3881 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3883 enum machine_mode mode
;
3885 mode
= TYPE_MODE (valtype
);
3891 return gen_rtx_REG (mode
, 16);
3897 /* If the function returns a pointer, push that into %a0 */
3898 if (POINTER_TYPE_P (valtype
))
3899 return gen_rtx_REG (mode
, 8);
3901 return gen_rtx_REG (mode
, 0);