1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* These bits are controlled by all CPU selection options. Many options
205 also control MASK_68881, but some (notably -m68020) leave it alone. */
207 #define MASK_ALL_CPU_BITS \
208 (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
209 | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_BITFIELD)
211 /* Implement TARGET_HANDLE_OPTION. */
214 m68k_handle_option (size_t code
, const char *arg
, int value
)
219 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
220 target_flags
|= MASK_5200
;
224 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
225 target_flags
|= MASK_5200
| MASK_CF_HWDIV
;
229 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
230 target_flags
|= MASK_528x
| MASK_CF_HWDIV
;
234 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
235 target_flags
|= MASK_CFV3
| MASK_CF_HWDIV
;
239 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
240 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
;
245 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
250 target_flags
&= ~MASK_ALL_CPU_BITS
;
251 target_flags
|= MASK_68020
| MASK_BITFIELD
;
255 target_flags
&= ~MASK_ALL_CPU_BITS
;
256 target_flags
|= MASK_BITFIELD
| MASK_68881
| MASK_68020
| MASK_68040
;
260 target_flags
&= ~MASK_ALL_CPU_BITS
;
261 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68020
262 | MASK_68040
| MASK_68060
);
266 target_flags
&= ~MASK_ALL_CPU_BITS
;
267 target_flags
|= MASK_68020
| MASK_68030
| MASK_BITFIELD
;
271 target_flags
&= ~MASK_ALL_CPU_BITS
;
272 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
273 | MASK_68040_ONLY
| MASK_68040
);
277 target_flags
&= ~MASK_ALL_CPU_BITS
;
278 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
279 | MASK_68040_ONLY
| MASK_68060
);
283 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
288 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
289 target_flags
|= MASK_68020
;
292 case OPT_mshared_library_id_
:
293 if (value
> MAX_LIBRARY_ID
)
294 error ("-mshared-library-id=%s is not between 0 and %d",
295 arg
, MAX_LIBRARY_ID
);
297 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
305 /* Sometimes certain combinations of command options do not make
306 sense on a particular target machine. You can define a macro
307 `OVERRIDE_OPTIONS' to take account of this. This macro, if
308 defined, is executed once just after all the command options have
311 Don't use this macro to turn on various extra optimizations for
312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
315 override_options (void)
317 /* Sanity check to ensure that msep-data and mid-sahred-library are not
318 * both specified together. Doing so simply doesn't make sense.
320 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
321 error ("cannot specify both -msep-data and -mid-shared-library");
323 /* If we're generating code for a separate A5 relative data segment,
324 * we've got to enable -fPIC as well. This might be relaxable to
325 * -fpic but it hasn't been tested properly.
327 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
330 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
332 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
333 error ("-fPIC is not currently supported on the 68000 or 68010");
335 /* ??? A historic way of turning on pic, or is this intended to
336 be an embedded thing that doesn't have the same name binding
337 significance that it does on hosted ELF systems? */
338 if (TARGET_PCREL
&& flag_pic
== 0)
341 /* Turn off function cse if we are doing PIC. We always want function call
342 to be done as `bsr foo@PLTPC', so it will force the assembler to create
343 the PLT entry for `foo'. Doing function cse will cause the address of
344 `foo' to be loaded into a register, which is exactly what we want to
345 avoid when we are doing PIC on svr4 m68k. */
347 flag_no_function_cse
= 1;
349 SUBTARGET_OVERRIDE_OPTIONS
;
352 /* Return nonzero if FUNC is an interrupt function as specified by the
353 "interrupt_handler" attribute. */
355 m68k_interrupt_function_p(tree func
)
359 if (TREE_CODE (func
) != FUNCTION_DECL
)
362 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
363 return (a
!= NULL_TREE
);
366 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
367 struct attribute_spec.handler. */
369 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
370 tree args ATTRIBUTE_UNUSED
,
371 int flags ATTRIBUTE_UNUSED
,
374 if (TREE_CODE (*node
) != FUNCTION_DECL
)
376 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
377 IDENTIFIER_POINTER (name
));
378 *no_add_attrs
= true;
385 m68k_compute_frame_layout (void)
388 unsigned int mask
, rmask
;
389 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
391 /* Only compute the frame once per function.
392 Don't cache information until reload has been completed. */
393 if (current_frame
.funcdef_no
== current_function_funcdef_no
397 current_frame
.size
= (get_frame_size () + 3) & -4;
399 mask
= rmask
= saved
= 0;
400 for (regno
= 0; regno
< 16; regno
++)
401 if (m68k_save_reg (regno
, interrupt_handler
))
404 rmask
|= 1 << (15 - regno
);
407 current_frame
.offset
= saved
* 4;
408 current_frame
.reg_no
= saved
;
409 current_frame
.reg_mask
= mask
;
410 current_frame
.reg_rev_mask
= rmask
;
412 current_frame
.foffset
= 0;
413 mask
= rmask
= saved
= 0;
414 if (TARGET_68881
/* || TARGET_CFV4E */)
416 for (regno
= 16; regno
< 24; regno
++)
417 if (m68k_save_reg (regno
, interrupt_handler
))
419 mask
|= 1 << (regno
- 16);
420 rmask
|= 1 << (23 - regno
);
423 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
424 current_frame
.offset
+= current_frame
.foffset
;
426 current_frame
.fpu_no
= saved
;
427 current_frame
.fpu_mask
= mask
;
428 current_frame
.fpu_rev_mask
= rmask
;
430 /* Remember what function this frame refers to. */
431 current_frame
.funcdef_no
= current_function_funcdef_no
;
435 m68k_initial_elimination_offset (int from
, int to
)
437 /* FIXME: The correct offset to compute here would appear to be
438 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
439 but for some obscure reason, this must be 0 to get correct code. */
440 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
443 m68k_compute_frame_layout ();
445 gcc_assert (to
== STACK_POINTER_REGNUM
);
448 case ARG_POINTER_REGNUM
:
449 return (current_frame
.offset
+ current_frame
.size
450 + (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
));
451 case FRAME_POINTER_REGNUM
:
452 return current_frame
.offset
+ current_frame
.size
;
458 /* Refer to the array `regs_ever_live' to determine which registers
459 to save; `regs_ever_live[I]' is nonzero if register number I
460 is ever used in the function. This function is responsible for
461 knowing which registers should not be saved even if used.
462 Return true if we need to save REGNO. */
465 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
467 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
469 if (current_function_uses_pic_offset_table
)
471 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
475 if (current_function_calls_eh_return
)
480 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
481 if (test
== INVALID_REGNUM
)
488 /* Fixed regs we never touch. */
489 if (fixed_regs
[regno
])
492 /* The frame pointer (if it is such) is handled specially. */
493 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
496 /* Interrupt handlers must also save call_used_regs
497 if they are live or when calling nested functions. */
498 if (interrupt_handler
)
500 if (regs_ever_live
[regno
])
503 if (!current_function_is_leaf
&& call_used_regs
[regno
])
507 /* Never need to save registers that aren't touched. */
508 if (!regs_ever_live
[regno
])
511 /* Otherwise save everything that isn't call-clobbered. */
512 return !call_used_regs
[regno
];
515 /* This function generates the assembly code for function entry.
516 STREAM is a stdio stream to output the code to.
517 SIZE is an int: how many units of temporary storage to allocate. */
520 m68k_output_function_prologue (FILE *stream
,
521 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
523 HOST_WIDE_INT fsize_with_regs
;
524 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
526 m68k_compute_frame_layout();
528 /* If the stack limit is a symbol, we can check it here,
529 before actually allocating the space. */
530 if (current_function_limit_stack
531 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
532 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
533 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
535 /* On ColdFire add register save into initial stack frame setup, if possible. */
536 fsize_with_regs
= current_frame
.size
;
537 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
538 fsize_with_regs
+= current_frame
.reg_no
* 4;
540 if (frame_pointer_needed
)
542 if (current_frame
.size
== 0 && TARGET_68040
)
543 /* on the 68040, pea + move is faster than link.w 0 */
544 fprintf (stream
, (MOTOROLA
545 ? "\tpea (%s)\n\tmove.l %s,%s\n"
546 : "\tpea %s@\n\tmovel %s,%s\n"),
547 M68K_REGNAME (FRAME_POINTER_REGNUM
),
548 M68K_REGNAME (STACK_POINTER_REGNUM
),
549 M68K_REGNAME (FRAME_POINTER_REGNUM
));
550 else if (fsize_with_regs
< 0x8000)
551 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
552 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
553 else if (TARGET_68020
)
554 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
555 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
557 /* Adding negative number is faster on the 68040. */
559 "\tlink" ASM_DOTW
" %s,%I0\n"
560 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
561 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
563 if (dwarf2out_do_frame ())
566 l
= (char *) dwarf2out_cfi_label ();
568 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
569 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
570 cfa_offset
+= current_frame
.size
;
573 else if (fsize_with_regs
) /* !frame_pointer_needed */
575 if (fsize_with_regs
< 0x8000)
577 if (fsize_with_regs
<= 8)
579 if (!TARGET_COLDFIRE
)
580 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
583 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
586 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
587 /* On the CPU32 it is faster to use two subqw instructions to
588 subtract a small integer (8 < N <= 16) to a register. */
590 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
591 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
592 fsize_with_regs
- 8);
593 else if (TARGET_68040
)
594 /* Adding negative number is faster on the 68040. */
595 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
598 asm_fprintf (stream
, (MOTOROLA
599 ? "\tlea (%wd,%Rsp),%Rsp\n"
600 : "\tlea %Rsp@(%wd),%Rsp\n"),
603 else /* fsize_with_regs >= 0x8000 */
604 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
607 if (dwarf2out_do_frame ())
609 cfa_offset
+= current_frame
.size
+ 4;
610 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
612 } /* !frame_pointer_needed */
614 if (current_frame
.fpu_mask
)
616 asm_fprintf (stream
, (MOTOROLA
617 ? "\tfmovm %I0x%x,-(%Rsp)\n"
618 : "\tfmovem %I0x%x,%Rsp@-\n"),
619 current_frame
.fpu_mask
);
621 if (dwarf2out_do_frame ())
623 char *l
= (char *) dwarf2out_cfi_label ();
626 cfa_offset
+= current_frame
.fpu_no
* 12;
627 if (! frame_pointer_needed
)
628 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
629 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
630 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
631 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
635 /* If the stack limit is not a symbol, check it here.
636 This has the disadvantage that it may be too late... */
637 if (current_function_limit_stack
)
639 if (REG_P (stack_limit_rtx
))
640 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
641 M68K_REGNAME (REGNO (stack_limit_rtx
)));
642 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
643 warning (0, "stack limit expression is not supported");
646 if (current_frame
.reg_no
<= 2)
648 /* Store each separately in the same order moveml uses.
649 Using two movel instructions instead of a single moveml
650 is about 15% faster for the 68020 and 68030 at no expense
655 for (i
= 0; i
< 16; i
++)
656 if (current_frame
.reg_rev_mask
& (1 << i
))
658 asm_fprintf (stream
, (MOTOROLA
659 ? "\t%Omove.l %s,-(%Rsp)\n"
660 : "\tmovel %s,%Rsp@-\n"),
661 M68K_REGNAME (15 - i
));
662 if (dwarf2out_do_frame ())
664 char *l
= (char *) dwarf2out_cfi_label ();
667 if (! frame_pointer_needed
)
668 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
669 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
673 else if (current_frame
.reg_rev_mask
)
676 /* The ColdFire does not support the predecrement form of the
677 MOVEM instruction, so we must adjust the stack pointer and
678 then use the plain address register indirect mode.
679 The required register save space was combined earlier with
680 the fsize_with_regs amount. */
682 asm_fprintf (stream
, (MOTOROLA
683 ? "\tmovm.l %I0x%x,(%Rsp)\n"
684 : "\tmoveml %I0x%x,%Rsp@\n"),
685 current_frame
.reg_mask
);
687 asm_fprintf (stream
, (MOTOROLA
688 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
689 : "\tmoveml %I0x%x,%Rsp@-\n"),
690 current_frame
.reg_rev_mask
);
691 if (dwarf2out_do_frame ())
693 char *l
= (char *) dwarf2out_cfi_label ();
696 cfa_offset
+= current_frame
.reg_no
* 4;
697 if (! frame_pointer_needed
)
698 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
699 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
700 if (current_frame
.reg_mask
& (1 << regno
))
701 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
704 if (!TARGET_SEP_DATA
&& flag_pic
705 && (current_function_uses_pic_offset_table
706 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
708 if (TARGET_ID_SHARED_LIBRARY
)
710 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
711 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
712 m68k_library_id_string
,
713 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
719 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
720 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
723 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
724 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
725 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
726 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
727 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
733 /* Return true if this function's epilogue can be output as RTL. */
736 use_return_insn (void)
738 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
741 /* We can output the epilogue as RTL only if no registers need to be
743 m68k_compute_frame_layout ();
744 return current_frame
.reg_no
? false : true;
747 /* This function generates the assembly code for function exit,
748 on machines that need it.
750 The function epilogue should not depend on the current stack pointer!
751 It should use the frame pointer only, if there is a frame pointer.
752 This is mandatory because of alloca; we also take advantage of it to
753 omit stack adjustments before returning. */
756 m68k_output_function_epilogue (FILE *stream
,
757 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
759 HOST_WIDE_INT fsize
, fsize_with_regs
;
761 bool restore_from_sp
= false;
762 rtx insn
= get_last_insn ();
764 m68k_compute_frame_layout ();
766 /* If the last insn was a BARRIER, we don't have to write any code. */
767 if (GET_CODE (insn
) == NOTE
)
768 insn
= prev_nonnote_insn (insn
);
769 if (insn
&& GET_CODE (insn
) == BARRIER
)
771 /* Output just a no-op so that debuggers don't get confused
772 about which function the pc is in at this address. */
773 fprintf (stream
, "\tnop\n");
777 #ifdef FUNCTION_EXTRA_EPILOGUE
778 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
781 fsize
= current_frame
.size
;
783 /* FIXME: leaf_function_p below is too strong.
784 What we really need to know there is if there could be pending
785 stack adjustment needed at that point. */
787 = (! frame_pointer_needed
788 || (! current_function_calls_alloca
&& leaf_function_p ()));
790 /* fsize_with_regs is the size we need to adjust the sp when
791 popping the frame. */
792 fsize_with_regs
= fsize
;
794 /* Because the ColdFire doesn't support moveml with
795 complex address modes, we must adjust the stack manually
796 after restoring registers. When the frame pointer isn't used,
797 we can merge movem adjustment into frame unlinking
798 made immediately after it. */
799 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
800 fsize_with_regs
+= current_frame
.reg_no
* 4;
802 if (current_frame
.offset
+ fsize
>= 0x8000
804 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
806 /* Because the ColdFire doesn't support moveml with
807 complex address modes we make an extra correction here. */
809 fsize
+= current_frame
.offset
;
811 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
812 fsize
= 0, big
= true;
814 if (current_frame
.reg_no
<= 2)
816 /* Restore each separately in the same order moveml does.
817 Using two movel instructions instead of a single moveml
818 is about 15% faster for the 68020 and 68030 at no expense
822 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
824 for (i
= 0; i
< 16; i
++)
825 if (current_frame
.reg_mask
& (1 << i
))
830 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
832 M68K_REGNAME (FRAME_POINTER_REGNUM
),
835 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
836 M68K_REGNAME (FRAME_POINTER_REGNUM
),
840 else if (restore_from_sp
)
841 asm_fprintf (stream
, (MOTOROLA
842 ? "\t%Omove.l (%Rsp)+,%s\n"
843 : "\tmovel %Rsp@+,%s\n"),
848 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
850 M68K_REGNAME (FRAME_POINTER_REGNUM
),
853 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
854 M68K_REGNAME (FRAME_POINTER_REGNUM
),
861 else if (current_frame
.reg_mask
)
863 /* The ColdFire requires special handling due to its limited moveml
869 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
870 M68K_REGNAME (FRAME_POINTER_REGNUM
));
871 asm_fprintf (stream
, (MOTOROLA
872 ? "\tmovm.l (%Ra1),%I0x%x\n"
873 : "\tmoveml %Ra1@,%I0x%x\n"),
874 current_frame
.reg_mask
);
876 else if (restore_from_sp
)
877 asm_fprintf (stream
, (MOTOROLA
878 ? "\tmovm.l (%Rsp),%I0x%x\n"
879 : "\tmoveml %Rsp@,%I0x%x\n"),
880 current_frame
.reg_mask
);
884 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
885 current_frame
.offset
+ fsize
,
886 M68K_REGNAME (FRAME_POINTER_REGNUM
),
887 current_frame
.reg_mask
);
889 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
890 M68K_REGNAME (FRAME_POINTER_REGNUM
),
891 current_frame
.offset
+ fsize
,
892 current_frame
.reg_mask
);
895 else /* !TARGET_COLDFIRE */
900 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
901 current_frame
.offset
+ fsize
,
902 M68K_REGNAME (FRAME_POINTER_REGNUM
),
903 current_frame
.reg_mask
);
905 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
906 M68K_REGNAME (FRAME_POINTER_REGNUM
),
907 current_frame
.offset
+ fsize
,
908 current_frame
.reg_mask
);
910 else if (restore_from_sp
)
912 asm_fprintf (stream
, (MOTOROLA
913 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
914 : "\tmoveml %Rsp@+,%I0x%x\n"),
915 current_frame
.reg_mask
);
920 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
921 current_frame
.offset
+ fsize
,
922 M68K_REGNAME (FRAME_POINTER_REGNUM
),
923 current_frame
.reg_mask
);
925 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
926 M68K_REGNAME (FRAME_POINTER_REGNUM
),
927 current_frame
.offset
+ fsize
,
928 current_frame
.reg_mask
);
932 if (current_frame
.fpu_rev_mask
)
937 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
938 current_frame
.foffset
+ fsize
,
939 M68K_REGNAME (FRAME_POINTER_REGNUM
),
940 current_frame
.fpu_rev_mask
);
942 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
943 M68K_REGNAME (FRAME_POINTER_REGNUM
),
944 current_frame
.foffset
+ fsize
,
945 current_frame
.fpu_rev_mask
);
947 else if (restore_from_sp
)
950 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
951 current_frame
.fpu_rev_mask
);
953 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
954 current_frame
.fpu_rev_mask
);
959 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
960 current_frame
.foffset
+ fsize
,
961 M68K_REGNAME (FRAME_POINTER_REGNUM
),
962 current_frame
.fpu_rev_mask
);
964 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
965 M68K_REGNAME (FRAME_POINTER_REGNUM
),
966 current_frame
.foffset
+ fsize
,
967 current_frame
.fpu_rev_mask
);
970 if (frame_pointer_needed
)
971 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
972 else if (fsize_with_regs
)
974 if (fsize_with_regs
<= 8)
976 if (!TARGET_COLDFIRE
)
977 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
980 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
983 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
985 /* On the CPU32 it is faster to use two addqw instructions to
986 add a small integer (8 < N <= 16) to a register. */
988 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
989 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
990 fsize_with_regs
- 8);
992 else if (fsize_with_regs
< 0x8000)
995 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
998 asm_fprintf (stream
, (MOTOROLA
999 ? "\tlea (%wd,%Rsp),%Rsp\n"
1000 : "\tlea %Rsp@(%wd),%Rsp\n"),
1004 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1006 if (current_function_calls_eh_return
)
1007 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1008 if (m68k_interrupt_function_p (current_function_decl
))
1009 fprintf (stream
, "\trte\n");
1010 else if (current_function_pops_args
)
1011 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1013 fprintf (stream
, "\trts\n");
1016 /* Return true if X is a valid comparison operator for the dbcc
1019 Note it rejects floating point comparison operators.
1020 (In the future we could use Fdbcc).
1022 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1025 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1027 switch (GET_CODE (x
))
1029 case EQ
: case NE
: case GTU
: case LTU
:
1033 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1035 case GT
: case LT
: case GE
: case LE
:
1036 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1042 /* Return nonzero if flags are currently in the 68881 flag register. */
1044 flags_in_68881 (void)
1046 /* We could add support for these in the future */
1047 return cc_status
.flags
& CC_IN_68881
;
1050 /* Output a BSR instruction suitable for PIC code. */
1052 m68k_output_pic_call (rtx dest
)
1056 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1058 /* We output a BSR instruction if we're using -fpic or we're building for
1059 a target that supports long branches. If we're building -fPIC on the
1060 68000, 68010 or ColdFire we generate one of two sequences:
1061 a shorter one that uses a GOT entry or a longer one that doesn't.
1062 We'll use the -Os command-line flag to decide which to generate.
1063 Both sequences take the same time to execute on the ColdFire. */
1064 else if (TARGET_PCREL
)
1066 else if (flag_pic
== 1 || TARGET_68020
)
1067 #if defined(USE_GAS)
1068 out
= "bsr.l %0@PLTPC";
1070 out
= "bsr %0@PLTPC";
1072 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1073 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1075 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1077 output_asm_insn (out
, &dest
);
1080 /* Output a dbCC; jCC sequence. Note we do not handle the
1081 floating point version of this sequence (Fdbcc). We also
1082 do not handle alternative conditions when CC_NO_OVERFLOW is
1083 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1084 kick those out before we get here. */
1087 output_dbcc_and_branch (rtx
*operands
)
1089 switch (GET_CODE (operands
[3]))
1092 output_asm_insn (MOTOROLA
1093 ? "dbeq %0,%l1\n\tjbeq %l2"
1094 : "dbeq %0,%l1\n\tjeq %l2",
1099 output_asm_insn (MOTOROLA
1100 ? "dbne %0,%l1\n\tjbne %l2"
1101 : "dbne %0,%l1\n\tjne %l2",
1106 output_asm_insn (MOTOROLA
1107 ? "dbgt %0,%l1\n\tjbgt %l2"
1108 : "dbgt %0,%l1\n\tjgt %l2",
1113 output_asm_insn (MOTOROLA
1114 ? "dbhi %0,%l1\n\tjbhi %l2"
1115 : "dbhi %0,%l1\n\tjhi %l2",
1120 output_asm_insn (MOTOROLA
1121 ? "dblt %0,%l1\n\tjblt %l2"
1122 : "dblt %0,%l1\n\tjlt %l2",
1127 output_asm_insn (MOTOROLA
1128 ? "dbcs %0,%l1\n\tjbcs %l2"
1129 : "dbcs %0,%l1\n\tjcs %l2",
1134 output_asm_insn (MOTOROLA
1135 ? "dbge %0,%l1\n\tjbge %l2"
1136 : "dbge %0,%l1\n\tjge %l2",
1141 output_asm_insn (MOTOROLA
1142 ? "dbcc %0,%l1\n\tjbcc %l2"
1143 : "dbcc %0,%l1\n\tjcc %l2",
1148 output_asm_insn (MOTOROLA
1149 ? "dble %0,%l1\n\tjble %l2"
1150 : "dble %0,%l1\n\tjle %l2",
1155 output_asm_insn (MOTOROLA
1156 ? "dbls %0,%l1\n\tjbls %l2"
1157 : "dbls %0,%l1\n\tjls %l2",
1165 /* If the decrement is to be done in SImode, then we have
1166 to compensate for the fact that dbcc decrements in HImode. */
1167 switch (GET_MODE (operands
[0]))
1170 output_asm_insn (MOTOROLA
1171 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1172 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1185 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1188 enum rtx_code op_code
= GET_CODE (op
);
1190 /* This does not produce a useful cc. */
1193 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1194 below. Swap the operands and change the op if these requirements
1195 are not fulfilled. */
1196 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1200 operand1
= operand2
;
1202 op_code
= swap_condition (op_code
);
1204 loperands
[0] = operand1
;
1205 if (GET_CODE (operand1
) == REG
)
1206 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1208 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1209 if (operand2
!= const0_rtx
)
1211 loperands
[2] = operand2
;
1212 if (GET_CODE (operand2
) == REG
)
1213 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1215 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1217 loperands
[4] = gen_label_rtx ();
1218 if (operand2
!= const0_rtx
)
1220 output_asm_insn (MOTOROLA
1221 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1222 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1227 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1228 output_asm_insn ("tst%.l %0", loperands
);
1230 output_asm_insn ("cmp%.w #0,%0", loperands
);
1232 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1234 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1235 output_asm_insn ("tst%.l %1", loperands
);
1237 output_asm_insn ("cmp%.w #0,%1", loperands
);
1240 loperands
[5] = dest
;
1245 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1246 CODE_LABEL_NUMBER (loperands
[4]));
1247 output_asm_insn ("seq %5", loperands
);
1251 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1252 CODE_LABEL_NUMBER (loperands
[4]));
1253 output_asm_insn ("sne %5", loperands
);
1257 loperands
[6] = gen_label_rtx ();
1258 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1260 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1261 CODE_LABEL_NUMBER (loperands
[4]));
1262 output_asm_insn ("sgt %5", loperands
);
1263 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1264 CODE_LABEL_NUMBER (loperands
[6]));
1268 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1269 CODE_LABEL_NUMBER (loperands
[4]));
1270 output_asm_insn ("shi %5", loperands
);
1274 loperands
[6] = gen_label_rtx ();
1275 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1277 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1278 CODE_LABEL_NUMBER (loperands
[4]));
1279 output_asm_insn ("slt %5", loperands
);
1280 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1281 CODE_LABEL_NUMBER (loperands
[6]));
1285 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1286 CODE_LABEL_NUMBER (loperands
[4]));
1287 output_asm_insn ("scs %5", loperands
);
1291 loperands
[6] = gen_label_rtx ();
1292 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1294 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1295 CODE_LABEL_NUMBER (loperands
[4]));
1296 output_asm_insn ("sge %5", loperands
);
1297 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1298 CODE_LABEL_NUMBER (loperands
[6]));
1302 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1303 CODE_LABEL_NUMBER (loperands
[4]));
1304 output_asm_insn ("scc %5", loperands
);
1308 loperands
[6] = gen_label_rtx ();
1309 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1311 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1312 CODE_LABEL_NUMBER (loperands
[4]));
1313 output_asm_insn ("sle %5", loperands
);
1314 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1315 CODE_LABEL_NUMBER (loperands
[6]));
1319 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1320 CODE_LABEL_NUMBER (loperands
[4]));
1321 output_asm_insn ("sls %5", loperands
);
1331 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1333 operands
[0] = countop
;
1334 operands
[1] = dataop
;
1336 if (GET_CODE (countop
) == CONST_INT
)
1338 register int count
= INTVAL (countop
);
1339 /* If COUNT is bigger than size of storage unit in use,
1340 advance to the containing unit of same size. */
1341 if (count
> signpos
)
1343 int offset
= (count
& ~signpos
) / 8;
1344 count
= count
& signpos
;
1345 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1347 if (count
== signpos
)
1348 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1350 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1352 /* These three statements used to use next_insns_test_no...
1353 but it appears that this should do the same job. */
1355 && next_insn_tests_no_inequality (insn
))
1358 && next_insn_tests_no_inequality (insn
))
1361 && next_insn_tests_no_inequality (insn
))
1364 cc_status
.flags
= CC_NOT_NEGATIVE
;
1366 return "btst %0,%1";
1369 /* Legitimize PIC addresses. If the address is already
1370 position-independent, we return ORIG. Newly generated
1371 position-independent addresses go to REG. If we need more
1372 than one register, we lose.
1374 An address is legitimized by making an indirect reference
1375 through the Global Offset Table with the name of the symbol
1378 The assembler and linker are responsible for placing the
1379 address of the symbol in the GOT. The function prologue
1380 is responsible for initializing a5 to the starting address
1383 The assembler is also responsible for translating a symbol name
1384 into a constant displacement from the start of the GOT.
1386 A quick example may make things a little clearer:
1388 When not generating PIC code to store the value 12345 into _foo
1389 we would generate the following code:
1393 When generating PIC two transformations are made. First, the compiler
1394 loads the address of foo into a register. So the first transformation makes:
1399 The code in movsi will intercept the lea instruction and call this
1400 routine which will transform the instructions into:
1402 movel a5@(_foo:w), a0
1406 That (in a nutshell) is how *all* symbol and label references are
1410 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1415 /* First handle a simple SYMBOL_REF or LABEL_REF */
1416 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1420 pic_ref
= gen_rtx_MEM (Pmode
,
1421 gen_rtx_PLUS (Pmode
,
1422 pic_offset_table_rtx
, orig
));
1423 current_function_uses_pic_offset_table
= 1;
1424 MEM_READONLY_P (pic_ref
) = 1;
1425 emit_move_insn (reg
, pic_ref
);
1428 else if (GET_CODE (orig
) == CONST
)
1432 /* Make sure this has not already been legitimized. */
1433 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1434 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1439 /* legitimize both operands of the PLUS */
1440 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1442 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1443 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1444 base
== reg
? 0 : reg
);
1446 if (GET_CODE (orig
) == CONST_INT
)
1447 return plus_constant (base
, INTVAL (orig
));
1448 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1449 /* Likewise, should we set special REG_NOTEs here? */
1455 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1457 static CONST_METHOD
const_method (rtx
);
1459 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1462 const_method (rtx constant
)
1467 i
= INTVAL (constant
);
1471 /* The ColdFire doesn't have byte or word operations. */
1472 /* FIXME: This may not be useful for the m68060 either. */
1473 if (!TARGET_COLDFIRE
)
1475 /* if -256 < N < 256 but N is not in range for a moveq
1476 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1477 if (USE_MOVQ (i
^ 0xff))
1479 /* Likewise, try with not.w */
1480 if (USE_MOVQ (i
^ 0xffff))
1482 /* This is the only value where neg.w is useful */
1487 /* Try also with swap. */
1489 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1494 /* Try using MVZ/MVS with an immediate value to load constants. */
1495 if (i
>= 0 && i
<= 65535)
1497 if (i
>= -32768 && i
<= 32767)
1501 /* Otherwise, use move.l */
1506 const_int_cost (rtx constant
)
1508 switch (const_method (constant
))
1511 /* Constants between -128 and 127 are cheap due to moveq. */
1519 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1529 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1534 /* Constant zero is super cheap due to clr instruction. */
1535 if (x
== const0_rtx
)
1538 *total
= const_int_cost (x
);
1548 /* Make 0.0 cheaper than other floating constants to
1549 encourage creating tstsf and tstdf insns. */
1550 if (outer_code
== COMPARE
1551 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1557 /* These are vaguely right for a 68020. */
1558 /* The costs for long multiply have been adjusted to work properly
1559 in synth_mult on the 68020, relative to an average of the time
1560 for add and the time for shift, taking away a little more because
1561 sometimes move insns are needed. */
1562 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1564 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 \
1565 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 \
1566 : TARGET_COLDFIRE ? 10 : 13)
1567 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 \
1568 : (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
1569 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1572 /* An lea costs about three times as much as a simple add. */
1573 if (GET_MODE (x
) == SImode
1574 && GET_CODE (XEXP (x
, 1)) == REG
1575 && GET_CODE (XEXP (x
, 0)) == MULT
1576 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1577 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1578 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1579 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1580 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1582 /* lea an@(dx:l:i),am */
1583 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1593 *total
= COSTS_N_INSNS(1);
1596 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1598 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1600 if (INTVAL (XEXP (x
, 1)) < 16)
1601 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1603 /* We're using clrw + swap for these cases. */
1604 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1607 *total
= COSTS_N_INSNS (10); /* Worst case. */
1610 /* A shift by a big integer takes an extra instruction. */
1611 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1612 && (INTVAL (XEXP (x
, 1)) == 16))
1614 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1617 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1618 && !(INTVAL (XEXP (x
, 1)) > 0
1619 && INTVAL (XEXP (x
, 1)) <= 8))
1621 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1627 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1628 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1629 && GET_MODE (x
) == SImode
)
1630 *total
= COSTS_N_INSNS (MULW_COST
);
1631 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1632 *total
= COSTS_N_INSNS (MULW_COST
);
1634 *total
= COSTS_N_INSNS (MULL_COST
);
1641 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1642 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1643 else if (TARGET_CF_HWDIV
)
1644 *total
= COSTS_N_INSNS (18);
1646 *total
= COSTS_N_INSNS (43); /* div.l */
1655 output_move_const_into_data_reg (rtx
*operands
)
1659 i
= INTVAL (operands
[1]);
1660 switch (const_method (operands
[1]))
1663 return "mvsw %1,%0";
1665 return "mvzw %1,%0";
1667 return "moveq %1,%0";
1670 operands
[1] = GEN_INT (i
^ 0xff);
1671 return "moveq %1,%0\n\tnot%.b %0";
1674 operands
[1] = GEN_INT (i
^ 0xffff);
1675 return "moveq %1,%0\n\tnot%.w %0";
1678 return "moveq #-128,%0\n\tneg%.w %0";
1683 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1684 return "moveq %1,%0\n\tswap %0";
1687 return "move%.l %1,%0";
1693 /* Return 1 if 'constant' can be represented by
1694 mov3q on a ColdFire V4 core. */
1696 valid_mov3q_const (rtx constant
)
1700 if (TARGET_CFV4
&& GET_CODE (constant
) == CONST_INT
)
1702 i
= INTVAL (constant
);
1703 if (i
== -1 || (i
>= 1 && i
<= 7))
1711 output_move_simode_const (rtx
*operands
)
1713 if (operands
[1] == const0_rtx
1714 && (DATA_REG_P (operands
[0])
1715 || GET_CODE (operands
[0]) == MEM
)
1716 /* clr insns on 68000 read before writing.
1717 This isn't so on the 68010, but we have no TARGET_68010. */
1718 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1719 || !(GET_CODE (operands
[0]) == MEM
1720 && MEM_VOLATILE_P (operands
[0]))))
1722 else if ((GET_MODE (operands
[0]) == SImode
)
1723 && valid_mov3q_const (operands
[1]))
1724 return "mov3q%.l %1,%0";
1725 else if (operands
[1] == const0_rtx
1726 && ADDRESS_REG_P (operands
[0]))
1727 return "sub%.l %0,%0";
1728 else if (DATA_REG_P (operands
[0]))
1729 return output_move_const_into_data_reg (operands
);
1730 else if (ADDRESS_REG_P (operands
[0])
1731 && INTVAL (operands
[1]) < 0x8000
1732 && INTVAL (operands
[1]) >= -0x8000)
1734 if (valid_mov3q_const (operands
[1]))
1735 return "mov3q%.l %1,%0";
1736 return "move%.w %1,%0";
1738 else if (GET_CODE (operands
[0]) == MEM
1739 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1740 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1741 && INTVAL (operands
[1]) < 0x8000
1742 && INTVAL (operands
[1]) >= -0x8000)
1744 if (valid_mov3q_const (operands
[1]))
1745 return "mov3q%.l %1,%-";
1748 return "move%.l %1,%0";
1752 output_move_simode (rtx
*operands
)
1754 if (GET_CODE (operands
[1]) == CONST_INT
)
1755 return output_move_simode_const (operands
);
1756 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1757 || GET_CODE (operands
[1]) == CONST
)
1758 && push_operand (operands
[0], SImode
))
1760 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1761 || GET_CODE (operands
[1]) == CONST
)
1762 && ADDRESS_REG_P (operands
[0]))
1763 return "lea %a1,%0";
1764 return "move%.l %1,%0";
1768 output_move_himode (rtx
*operands
)
1770 if (GET_CODE (operands
[1]) == CONST_INT
)
1772 if (operands
[1] == const0_rtx
1773 && (DATA_REG_P (operands
[0])
1774 || GET_CODE (operands
[0]) == MEM
)
1775 /* clr insns on 68000 read before writing.
1776 This isn't so on the 68010, but we have no TARGET_68010. */
1777 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1778 || !(GET_CODE (operands
[0]) == MEM
1779 && MEM_VOLATILE_P (operands
[0]))))
1781 else if (operands
[1] == const0_rtx
1782 && ADDRESS_REG_P (operands
[0]))
1783 return "sub%.l %0,%0";
1784 else if (DATA_REG_P (operands
[0])
1785 && INTVAL (operands
[1]) < 128
1786 && INTVAL (operands
[1]) >= -128)
1787 return "moveq %1,%0";
1788 else if (INTVAL (operands
[1]) < 0x8000
1789 && INTVAL (operands
[1]) >= -0x8000)
1790 return "move%.w %1,%0";
1792 else if (CONSTANT_P (operands
[1]))
1793 return "move%.l %1,%0";
1794 /* Recognize the insn before a tablejump, one that refers
1795 to a table of offsets. Such an insn will need to refer
1796 to a label on the insn. So output one. Use the label-number
1797 of the table of offsets to generate this label. This code,
1798 and similar code below, assumes that there will be at most one
1799 reference to each table. */
1800 if (GET_CODE (operands
[1]) == MEM
1801 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1802 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1803 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1805 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1807 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1808 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1810 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1811 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1813 return "move%.w %1,%0";
1817 output_move_qimode (rtx
*operands
)
1819 /* 68k family always modifies the stack pointer by at least 2, even for
1820 byte pushes. The 5200 (ColdFire) does not do this. */
1822 /* This case is generated by pushqi1 pattern now. */
1823 gcc_assert (!(GET_CODE (operands
[0]) == MEM
1824 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1825 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1826 && ! ADDRESS_REG_P (operands
[1])
1827 && ! TARGET_COLDFIRE
));
1829 /* clr and st insns on 68000 read before writing.
1830 This isn't so on the 68010, but we have no TARGET_68010. */
1831 if (!ADDRESS_REG_P (operands
[0])
1832 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1833 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1835 if (operands
[1] == const0_rtx
)
1837 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1838 && GET_CODE (operands
[1]) == CONST_INT
1839 && (INTVAL (operands
[1]) & 255) == 255)
1845 if (GET_CODE (operands
[1]) == CONST_INT
1846 && DATA_REG_P (operands
[0])
1847 && INTVAL (operands
[1]) < 128
1848 && INTVAL (operands
[1]) >= -128)
1849 return "moveq %1,%0";
1850 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1851 return "sub%.l %0,%0";
1852 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1853 return "move%.l %1,%0";
1854 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1855 from address registers. */
1856 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1857 return "move%.w %1,%0";
1858 return "move%.b %1,%0";
1862 output_move_stricthi (rtx
*operands
)
1864 if (operands
[1] == const0_rtx
1865 /* clr insns on 68000 read before writing.
1866 This isn't so on the 68010, but we have no TARGET_68010. */
1867 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1868 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1870 return "move%.w %1,%0";
1874 output_move_strictqi (rtx
*operands
)
1876 if (operands
[1] == const0_rtx
1877 /* clr insns on 68000 read before writing.
1878 This isn't so on the 68010, but we have no TARGET_68010. */
1879 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1880 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1882 return "move%.b %1,%0";
1885 /* Return the best assembler insn template
1886 for moving operands[1] into operands[0] as a fullword. */
1889 singlemove_string (rtx
*operands
)
1891 if (GET_CODE (operands
[1]) == CONST_INT
)
1892 return output_move_simode_const (operands
);
1893 return "move%.l %1,%0";
1897 /* Output assembler code to perform a doubleword move insn
1898 with operands OPERANDS. */
1901 output_move_double (rtx
*operands
)
1905 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1910 rtx addreg0
= 0, addreg1
= 0;
1911 int dest_overlapped_low
= 0;
1912 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1917 /* First classify both operands. */
1919 if (REG_P (operands
[0]))
1921 else if (offsettable_memref_p (operands
[0]))
1923 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1925 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1927 else if (GET_CODE (operands
[0]) == MEM
)
1932 if (REG_P (operands
[1]))
1934 else if (CONSTANT_P (operands
[1]))
1936 else if (offsettable_memref_p (operands
[1]))
1938 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1940 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1942 else if (GET_CODE (operands
[1]) == MEM
)
1947 /* Check for the cases that the operand constraints are not supposed
1948 to allow to happen. Generating code for these cases is
1950 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
1952 /* If one operand is decrementing and one is incrementing
1953 decrement the former register explicitly
1954 and change that operand into ordinary indexing. */
1956 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1958 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1960 output_asm_insn ("sub%.l #12,%0", operands
);
1962 output_asm_insn ("subq%.l #8,%0", operands
);
1963 if (GET_MODE (operands
[1]) == XFmode
)
1964 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1965 else if (GET_MODE (operands
[0]) == DFmode
)
1966 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1968 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1971 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1973 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1975 output_asm_insn ("sub%.l #12,%1", operands
);
1977 output_asm_insn ("subq%.l #8,%1", operands
);
1978 if (GET_MODE (operands
[1]) == XFmode
)
1979 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1980 else if (GET_MODE (operands
[1]) == DFmode
)
1981 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1983 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1987 /* If an operand is an unoffsettable memory ref, find a register
1988 we can increment temporarily to make it refer to the second word. */
1990 if (optype0
== MEMOP
)
1991 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1993 if (optype1
== MEMOP
)
1994 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1996 /* Ok, we can do one word at a time.
1997 Normally we do the low-numbered word first,
1998 but if either operand is autodecrementing then we
1999 do the high-numbered word first.
2001 In either case, set up in LATEHALF the operands to use
2002 for the high-numbered word and in some cases alter the
2003 operands in OPERANDS to be suitable for the low-numbered word. */
2007 if (optype0
== REGOP
)
2009 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2010 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2012 else if (optype0
== OFFSOP
)
2014 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2015 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2019 middlehalf
[0] = operands
[0];
2020 latehalf
[0] = operands
[0];
2023 if (optype1
== REGOP
)
2025 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2026 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2028 else if (optype1
== OFFSOP
)
2030 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2031 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2033 else if (optype1
== CNSTOP
)
2035 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2040 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2041 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2042 operands
[1] = GEN_INT (l
[0]);
2043 middlehalf
[1] = GEN_INT (l
[1]);
2044 latehalf
[1] = GEN_INT (l
[2]);
2048 /* No non-CONST_DOUBLE constant should ever appear
2050 gcc_assert (!CONSTANT_P (operands
[1]));
2055 middlehalf
[1] = operands
[1];
2056 latehalf
[1] = operands
[1];
2060 /* size is not 12: */
2062 if (optype0
== REGOP
)
2063 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2064 else if (optype0
== OFFSOP
)
2065 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2067 latehalf
[0] = operands
[0];
2069 if (optype1
== REGOP
)
2070 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2071 else if (optype1
== OFFSOP
)
2072 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2073 else if (optype1
== CNSTOP
)
2074 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2076 latehalf
[1] = operands
[1];
2079 /* If insn is effectively movd N(sp),-(sp) then we will do the
2080 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2081 for the low word as well, to compensate for the first decrement of sp. */
2082 if (optype0
== PUSHOP
2083 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2084 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2085 operands
[1] = middlehalf
[1] = latehalf
[1];
2087 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2088 if the upper part of reg N does not appear in the MEM, arrange to
2089 emit the move late-half first. Otherwise, compute the MEM address
2090 into the upper part of N and use that as a pointer to the memory
2092 if (optype0
== REGOP
2093 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2095 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2097 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2098 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2100 /* If both halves of dest are used in the src memory address,
2101 compute the address into latehalf of dest.
2102 Note that this can't happen if the dest is two data regs. */
2104 xops
[0] = latehalf
[0];
2105 xops
[1] = XEXP (operands
[1], 0);
2106 output_asm_insn ("lea %a1,%0", xops
);
2107 if (GET_MODE (operands
[1]) == XFmode
)
2109 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2110 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2111 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2115 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2116 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2120 && reg_overlap_mentioned_p (middlehalf
[0],
2121 XEXP (operands
[1], 0)))
2123 /* Check for two regs used by both source and dest.
2124 Note that this can't happen if the dest is all data regs.
2125 It can happen if the dest is d6, d7, a0.
2126 But in that case, latehalf is an addr reg, so
2127 the code at compadr does ok. */
2129 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2130 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2133 /* JRV says this can't happen: */
2134 gcc_assert (!addreg0
&& !addreg1
);
2136 /* Only the middle reg conflicts; simply put it last. */
2137 output_asm_insn (singlemove_string (operands
), operands
);
2138 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2139 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2142 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2143 /* If the low half of dest is mentioned in the source memory
2144 address, the arrange to emit the move late half first. */
2145 dest_overlapped_low
= 1;
2148 /* If one or both operands autodecrementing,
2149 do the two words, high-numbered first. */
2151 /* Likewise, the first move would clobber the source of the second one,
2152 do them in the other order. This happens only for registers;
2153 such overlap can't happen in memory unless the user explicitly
2154 sets it up, and that is an undefined circumstance. */
2156 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2157 || (optype0
== REGOP
&& optype1
== REGOP
2158 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2159 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2160 || dest_overlapped_low
)
2162 /* Make any unoffsettable addresses point at high-numbered word. */
2166 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2168 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2173 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2175 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2179 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2181 /* Undo the adds we just did. */
2183 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2185 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2189 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2191 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2193 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2196 /* Do low-numbered word. */
2197 return singlemove_string (operands
);
2200 /* Normal case: do the two words, low-numbered first. */
2202 output_asm_insn (singlemove_string (operands
), operands
);
2204 /* Do the middle one of the three words for long double */
2208 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2210 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2212 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2215 /* Make any unoffsettable addresses point at high-numbered word. */
2217 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2219 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2222 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2224 /* Undo the adds we just did. */
2228 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2230 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2235 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2237 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2243 /* Return a REG that occurs in ADDR with coefficient 1.
2244 ADDR can be effectively incremented by incrementing REG. */
2247 find_addr_reg (rtx addr
)
2249 while (GET_CODE (addr
) == PLUS
)
2251 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2252 addr
= XEXP (addr
, 0);
2253 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2254 addr
= XEXP (addr
, 1);
2255 else if (CONSTANT_P (XEXP (addr
, 0)))
2256 addr
= XEXP (addr
, 1);
2257 else if (CONSTANT_P (XEXP (addr
, 1)))
2258 addr
= XEXP (addr
, 0);
2262 gcc_assert (GET_CODE (addr
) == REG
);
2266 /* Output assembler code to perform a 32-bit 3-operand add. */
2269 output_addsi3 (rtx
*operands
)
2271 if (! operands_match_p (operands
[0], operands
[1]))
2273 if (!ADDRESS_REG_P (operands
[1]))
2275 rtx tmp
= operands
[1];
2277 operands
[1] = operands
[2];
2281 /* These insns can result from reloads to access
2282 stack slots over 64k from the frame pointer. */
2283 if (GET_CODE (operands
[2]) == CONST_INT
2284 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2285 return "move%.l %2,%0\n\tadd%.l %1,%0";
2286 if (GET_CODE (operands
[2]) == REG
)
2287 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2288 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2290 if (GET_CODE (operands
[2]) == CONST_INT
)
2292 if (INTVAL (operands
[2]) > 0
2293 && INTVAL (operands
[2]) <= 8)
2294 return "addq%.l %2,%0";
2295 if (INTVAL (operands
[2]) < 0
2296 && INTVAL (operands
[2]) >= -8)
2298 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2299 return "subq%.l %2,%0";
2301 /* On the CPU32 it is faster to use two addql instructions to
2302 add a small integer (8 < N <= 16) to a register.
2303 Likewise for subql. */
2304 if (TARGET_CPU32
&& REG_P (operands
[0]))
2306 if (INTVAL (operands
[2]) > 8
2307 && INTVAL (operands
[2]) <= 16)
2309 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2310 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2312 if (INTVAL (operands
[2]) < -8
2313 && INTVAL (operands
[2]) >= -16)
2315 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2316 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2319 if (ADDRESS_REG_P (operands
[0])
2320 && INTVAL (operands
[2]) >= -0x8000
2321 && INTVAL (operands
[2]) < 0x8000)
2324 return "add%.w %2,%0";
2326 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2329 return "add%.l %2,%0";
2332 /* Store in cc_status the expressions that the condition codes will
2333 describe after execution of an instruction whose pattern is EXP.
2334 Do not alter them if the instruction would not alter the cc's. */
2336 /* On the 68000, all the insns to store in an address register fail to
2337 set the cc's. However, in some cases these instructions can make it
2338 possibly invalid to use the saved cc's. In those cases we clear out
2339 some or all of the saved cc's so they won't be used. */
2342 notice_update_cc (rtx exp
, rtx insn
)
2344 if (GET_CODE (exp
) == SET
)
2346 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2348 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2350 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2351 cc_status
.value1
= 0;
2352 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2353 cc_status
.value2
= 0;
2355 else if (!FP_REG_P (SET_DEST (exp
))
2356 && SET_DEST (exp
) != cc0_rtx
2357 && (FP_REG_P (SET_SRC (exp
))
2358 || GET_CODE (SET_SRC (exp
)) == FIX
2359 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2360 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2362 /* A pair of move insns doesn't produce a useful overall cc. */
2363 else if (!FP_REG_P (SET_DEST (exp
))
2364 && !FP_REG_P (SET_SRC (exp
))
2365 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2366 && (GET_CODE (SET_SRC (exp
)) == REG
2367 || GET_CODE (SET_SRC (exp
)) == MEM
2368 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2370 else if (XEXP (exp
, 0) != pc_rtx
)
2372 cc_status
.flags
= 0;
2373 cc_status
.value1
= XEXP (exp
, 0);
2374 cc_status
.value2
= XEXP (exp
, 1);
2377 else if (GET_CODE (exp
) == PARALLEL
2378 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2380 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2382 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2384 cc_status
.flags
= 0;
2385 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2386 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2391 if (cc_status
.value2
!= 0
2392 && ADDRESS_REG_P (cc_status
.value2
)
2393 && GET_MODE (cc_status
.value2
) == QImode
)
2395 if (cc_status
.value2
!= 0)
2396 switch (GET_CODE (cc_status
.value2
))
2398 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2399 case ROTATE
: case ROTATERT
:
2400 /* These instructions always clear the overflow bit, and set
2401 the carry to the bit shifted out. */
2402 /* ??? We don't currently have a way to signal carry not valid,
2403 nor do we check for it in the branch insns. */
2407 case PLUS
: case MINUS
: case MULT
:
2408 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2409 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2410 cc_status
.flags
|= CC_NO_OVERFLOW
;
2413 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2414 ends with a move insn moving r2 in r2's mode.
2415 Thus, the cc's are set for r2.
2416 This can set N bit spuriously. */
2417 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2422 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2424 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2425 cc_status
.value2
= 0;
2426 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2427 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2428 cc_status
.flags
= CC_IN_68881
;
2432 output_move_const_double (rtx
*operands
)
2434 int code
= standard_68881_constant_p (operands
[1]);
2438 static char buf
[40];
2440 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2443 return "fmove%.d %1,%0";
2447 output_move_const_single (rtx
*operands
)
2449 int code
= standard_68881_constant_p (operands
[1]);
2453 static char buf
[40];
2455 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2458 return "fmove%.s %f1,%0";
2461 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2462 from the "fmovecr" instruction.
2463 The value, anded with 0xff, gives the code to use in fmovecr
2464 to get the desired constant. */
2466 /* This code has been fixed for cross-compilation. */
2468 static int inited_68881_table
= 0;
2470 static const char *const strings_68881
[7] = {
2480 static const int codes_68881
[7] = {
2490 REAL_VALUE_TYPE values_68881
[7];
2492 /* Set up values_68881 array by converting the decimal values
2493 strings_68881 to binary. */
2496 init_68881_table (void)
2500 enum machine_mode mode
;
2503 for (i
= 0; i
< 7; i
++)
2507 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2508 values_68881
[i
] = r
;
2510 inited_68881_table
= 1;
2514 standard_68881_constant_p (rtx x
)
2519 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2520 used at all on those chips. */
2521 if (TARGET_68040
|| TARGET_68060
)
2524 if (! inited_68881_table
)
2525 init_68881_table ();
2527 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2529 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2531 for (i
= 0; i
< 6; i
++)
2533 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2534 return (codes_68881
[i
]);
2537 if (GET_MODE (x
) == SFmode
)
2540 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2541 return (codes_68881
[6]);
2543 /* larger powers of ten in the constants ram are not used
2544 because they are not equal to a `double' C constant. */
2548 /* If X is a floating-point constant, return the logarithm of X base 2,
2549 or 0 if X is not a power of 2. */
2552 floating_exact_log2 (rtx x
)
2554 REAL_VALUE_TYPE r
, r1
;
2557 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2559 if (REAL_VALUES_LESS (r
, dconst1
))
2562 exp
= real_exponent (&r
);
2563 real_2expN (&r1
, exp
);
2564 if (REAL_VALUES_EQUAL (r1
, r
))
2570 /* A C compound statement to output to stdio stream STREAM the
2571 assembler syntax for an instruction operand X. X is an RTL
2574 CODE is a value that can be used to specify one of several ways
2575 of printing the operand. It is used when identical operands
2576 must be printed differently depending on the context. CODE
2577 comes from the `%' specification that was used to request
2578 printing of the operand. If the specification was just `%DIGIT'
2579 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2580 is the ASCII code for LTR.
2582 If X is a register, this macro should print the register's name.
2583 The names can be found in an array `reg_names' whose type is
2584 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2586 When the machine description has a specification `%PUNCT' (a `%'
2587 followed by a punctuation character), this macro is called with
2588 a null pointer for X and the punctuation character for CODE.
2590 The m68k specific codes are:
2592 '.' for dot needed in Motorola-style opcode names.
2593 '-' for an operand pushing on the stack:
2594 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2595 '+' for an operand pushing on the stack:
2596 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2597 '@' for a reference to the top word on the stack:
2598 sp@, (sp) or (%sp) depending on the style of syntax.
2599 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2600 but & in SGS syntax).
2601 '!' for the cc register (used in an `and to cc' insn).
2602 '$' for the letter `s' in an op code, but only on the 68040.
2603 '&' for the letter `d' in an op code, but only on the 68040.
2604 '/' for register prefix needed by longlong.h.
2606 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2607 'd' to force memory addressing to be absolute, not relative.
2608 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2609 'o' for operands to go directly to output_operand_address (bypassing
2610 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2611 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2612 or print pair of registers as rx:ry.
2617 print_operand (FILE *file
, rtx op
, int letter
)
2622 fprintf (file
, ".");
2624 else if (letter
== '#')
2625 asm_fprintf (file
, "%I");
2626 else if (letter
== '-')
2627 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2628 else if (letter
== '+')
2629 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2630 else if (letter
== '@')
2631 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2632 else if (letter
== '!')
2633 asm_fprintf (file
, "%Rfpcr");
2634 else if (letter
== '$')
2636 if (TARGET_68040_ONLY
)
2637 fprintf (file
, "s");
2639 else if (letter
== '&')
2641 if (TARGET_68040_ONLY
)
2642 fprintf (file
, "d");
2644 else if (letter
== '/')
2645 asm_fprintf (file
, "%R");
2646 else if (letter
== 'o')
2648 /* This is only for direct addresses with TARGET_PCREL */
2649 gcc_assert (GET_CODE (op
) == MEM
2650 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
2652 output_addr_const (file
, XEXP (op
, 0));
2654 else if (GET_CODE (op
) == REG
)
2657 /* Print out the second register name of a register pair.
2658 I.e., R (6) => 7. */
2659 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2661 fputs (M68K_REGNAME(REGNO (op
)), file
);
2663 else if (GET_CODE (op
) == MEM
)
2665 output_address (XEXP (op
, 0));
2666 if (letter
== 'd' && ! TARGET_68020
2667 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2668 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2669 && INTVAL (XEXP (op
, 0)) < 0x8000
2670 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2671 fprintf (file
, MOTOROLA
? ".l" : ":l");
2673 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2676 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2677 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2679 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2682 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2683 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2685 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2688 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2689 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2693 /* Use `print_operand_address' instead of `output_addr_const'
2694 to ensure that we print relevant PIC stuff. */
2695 asm_fprintf (file
, "%I");
2697 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2698 print_operand_address (file
, op
);
2700 output_addr_const (file
, op
);
2705 /* A C compound statement to output to stdio stream STREAM the
2706 assembler syntax for an instruction operand that is a memory
2707 reference whose address is ADDR. ADDR is an RTL expression.
2709 Note that this contains a kludge that knows that the only reason
2710 we have an address (plus (label_ref...) (reg...)) when not generating
2711 PIC code is in the insn before a tablejump, and we know that m68k.md
2712 generates a label LInnn: on such an insn.
2714 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2715 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2717 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2718 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2719 we want. This difference can be accommodated by using an assembler
2720 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2721 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2722 macro. See m68k/sgs.h for an example; for versions without the bug.
2723 Some assemblers refuse all the above solutions. The workaround is to
2724 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2727 They also do not like things like "pea 1.w", so we simple leave off
2728 the .w on small constants.
2730 This routine is responsible for distinguishing between -fpic and -fPIC
2731 style relocations in an address. When generating -fpic code the
2732 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
2733 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
2736 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
2737 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2738 #else /* !MOTOROLA */
2739 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
2740 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2741 #endif /* !MOTOROLA */
2744 print_operand_address (FILE *file
, rtx addr
)
2746 register rtx reg1
, reg2
, breg
, ireg
;
2749 switch (GET_CODE (addr
))
2752 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
2755 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2756 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
2759 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2760 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
2763 reg1
= reg2
= ireg
= breg
= offset
= 0;
2764 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2766 offset
= XEXP (addr
, 0);
2767 addr
= XEXP (addr
, 1);
2769 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2771 offset
= XEXP (addr
, 1);
2772 addr
= XEXP (addr
, 0);
2774 if (GET_CODE (addr
) != PLUS
)
2778 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2780 reg1
= XEXP (addr
, 0);
2781 addr
= XEXP (addr
, 1);
2783 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2785 reg1
= XEXP (addr
, 1);
2786 addr
= XEXP (addr
, 0);
2788 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2790 reg1
= XEXP (addr
, 0);
2791 addr
= XEXP (addr
, 1);
2793 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2795 reg1
= XEXP (addr
, 1);
2796 addr
= XEXP (addr
, 0);
2798 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2800 reg1
= XEXP (addr
, 0);
2801 addr
= XEXP (addr
, 1);
2803 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2805 reg1
= XEXP (addr
, 1);
2806 addr
= XEXP (addr
, 0);
2808 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2809 || GET_CODE (addr
) == SIGN_EXTEND
)
2817 #if 0 /* for OLD_INDEXING */
2818 else if (GET_CODE (addr
) == PLUS
)
2820 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2822 reg2
= XEXP (addr
, 0);
2823 addr
= XEXP (addr
, 1);
2825 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2827 reg2
= XEXP (addr
, 1);
2828 addr
= XEXP (addr
, 0);
2837 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2838 || GET_CODE (reg1
) == MULT
))
2839 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2844 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2849 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2850 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2853 if (GET_CODE (ireg
) == MULT
)
2855 scale
= INTVAL (XEXP (ireg
, 1));
2856 ireg
= XEXP (ireg
, 0);
2858 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2860 ASM_OUTPUT_CASE_FETCH (file
,
2861 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2862 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
2863 fprintf (file
, "w");
2867 ASM_OUTPUT_CASE_FETCH (file
,
2868 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2869 M68K_REGNAME (REGNO (ireg
)));
2870 fprintf (file
, "l");
2873 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2877 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2878 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2880 ASM_OUTPUT_CASE_FETCH (file
,
2881 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2882 M68K_REGNAME (REGNO (breg
)));
2883 fprintf (file
, "l)");
2886 if (ireg
!= 0 || breg
!= 0)
2891 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
2897 output_addr_const (file
, addr
);
2898 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2900 fprintf (file
, "@GOT");
2902 fprintf (file
, ".w");
2905 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
2909 else /* !MOTOROLA */
2911 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
2914 output_addr_const (file
, addr
);
2915 if (breg
== pic_offset_table_rtx
)
2919 fprintf (file
, ":w");
2922 fprintf (file
, ":l");
2931 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2933 scale
= INTVAL (XEXP (ireg
, 1));
2934 ireg
= XEXP (ireg
, 0);
2936 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2937 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2938 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
2940 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2941 M68K_REGNAME (REGNO (ireg
)));
2943 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2947 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2948 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2950 ASM_OUTPUT_CASE_FETCH (file
,
2951 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2952 M68K_REGNAME (REGNO (reg1
)));
2953 fprintf (file
, "l)");
2956 /* FALL-THROUGH (is this really what we want?) */
2958 if (GET_CODE (addr
) == CONST_INT
2959 && INTVAL (addr
) < 0x8000
2960 && INTVAL (addr
) >= -0x8000)
2962 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2964 else if (GET_CODE (addr
) == CONST_INT
)
2966 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2968 else if (TARGET_PCREL
)
2971 output_addr_const (file
, addr
);
2973 asm_fprintf (file
, ":w,%Rpc)");
2975 asm_fprintf (file
, ":l,%Rpc)");
2979 /* Special case for SYMBOL_REF if the symbol name ends in
2980 `.<letter>', this can be mistaken as a size suffix. Put
2981 the name in parentheses. */
2982 if (GET_CODE (addr
) == SYMBOL_REF
2983 && strlen (XSTR (addr
, 0)) > 2
2984 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
2987 output_addr_const (file
, addr
);
2991 output_addr_const (file
, addr
);
2997 /* Check for cases where a clr insns can be omitted from code using
2998 strict_low_part sets. For example, the second clrl here is not needed:
2999 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3001 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3002 insn we are checking for redundancy. TARGET is the register set by the
3006 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3011 p
= prev_nonnote_insn (first_insn
);
3015 /* If it isn't an insn, then give up. */
3016 if (GET_CODE (p
) != INSN
)
3019 if (reg_set_p (target
, p
))
3021 rtx set
= single_set (p
);
3024 /* If it isn't an easy to recognize insn, then give up. */
3028 dest
= SET_DEST (set
);
3030 /* If this sets the entire target register to zero, then our
3031 first_insn is redundant. */
3032 if (rtx_equal_p (dest
, target
)
3033 && SET_SRC (set
) == const0_rtx
)
3035 else if (GET_CODE (dest
) == STRICT_LOW_PART
3036 && GET_CODE (XEXP (dest
, 0)) == REG
3037 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3038 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3039 <= GET_MODE_SIZE (mode
)))
3040 /* This is a strict low part set which modifies less than
3041 we are using, so it is safe. */
3047 p
= prev_nonnote_insn (p
);
3053 /* Operand predicates for implementing asymmetric pc-relative addressing
3054 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3055 when used as a source operand, but not as a destination operand.
3057 We model this by restricting the meaning of the basic predicates
3058 (general_operand, memory_operand, etc) to forbid the use of this
3059 addressing mode, and then define the following predicates that permit
3060 this addressing mode. These predicates can then be used for the
3061 source operands of the appropriate instructions.
3063 n.b. While it is theoretically possible to change all machine patterns
3064 to use this addressing more where permitted by the architecture,
3065 it has only been implemented for "common" cases: SImode, HImode, and
3066 QImode operands, and only for the principle operations that would
3067 require this addressing mode: data movement and simple integer operations.
3069 In parallel with these new predicates, two new constraint letters
3070 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3071 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3072 In the pcrel case 's' is only valid in combination with 'a' registers.
3073 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3074 of how these constraints are used.
3076 The use of these predicates is strictly optional, though patterns that
3077 don't will cause an extra reload register to be allocated where one
3080 lea (abc:w,%pc),%a0 ; need to reload address
3081 moveq &1,%d1 ; since write to pc-relative space
3082 movel %d1,%a0@ ; is not allowed
3084 lea (abc:w,%pc),%a1 ; no need to reload address here
3085 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3087 For more info, consult tiemann@cygnus.com.
3090 All of the ugliness with predicates and constraints is due to the
3091 simple fact that the m68k does not allow a pc-relative addressing
3092 mode as a destination. gcc does not distinguish between source and
3093 destination addresses. Hence, if we claim that pc-relative address
3094 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3095 end up with invalid code. To get around this problem, we left
3096 pc-relative modes as invalid addresses, and then added special
3097 predicates and constraints to accept them.
3099 A cleaner way to handle this is to modify gcc to distinguish
3100 between source and destination addresses. We can then say that
3101 pc-relative is a valid source address but not a valid destination
3102 address, and hopefully avoid a lot of the predicate and constraint
3103 hackery. Unfortunately, this would be a pretty big change. It would
3104 be a useful change for a number of ports, but there aren't any current
3105 plans to undertake this.
3107 ***************************************************************************/
3111 output_andsi3 (rtx
*operands
)
3114 if (GET_CODE (operands
[2]) == CONST_INT
3115 && (INTVAL (operands
[2]) | 0xffff) == -1
3116 && (DATA_REG_P (operands
[0])
3117 || offsettable_memref_p (operands
[0]))
3118 && !TARGET_COLDFIRE
)
3120 if (GET_CODE (operands
[0]) != REG
)
3121 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3122 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3123 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3125 if (operands
[2] == const0_rtx
)
3127 return "and%.w %2,%0";
3129 if (GET_CODE (operands
[2]) == CONST_INT
3130 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3131 && (DATA_REG_P (operands
[0])
3132 || offsettable_memref_p (operands
[0])))
3134 if (DATA_REG_P (operands
[0]))
3135 operands
[1] = GEN_INT (logval
);
3138 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3139 operands
[1] = GEN_INT (logval
% 8);
3141 /* This does not set condition codes in a standard way. */
3143 return "bclr %1,%0";
3145 return "and%.l %2,%0";
3149 output_iorsi3 (rtx
*operands
)
3151 register int logval
;
3152 if (GET_CODE (operands
[2]) == CONST_INT
3153 && INTVAL (operands
[2]) >> 16 == 0
3154 && (DATA_REG_P (operands
[0])
3155 || offsettable_memref_p (operands
[0]))
3156 && !TARGET_COLDFIRE
)
3158 if (GET_CODE (operands
[0]) != REG
)
3159 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3160 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3162 if (INTVAL (operands
[2]) == 0xffff)
3163 return "mov%.w %2,%0";
3164 return "or%.w %2,%0";
3166 if (GET_CODE (operands
[2]) == CONST_INT
3167 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3168 && (DATA_REG_P (operands
[0])
3169 || offsettable_memref_p (operands
[0])))
3171 if (DATA_REG_P (operands
[0]))
3172 operands
[1] = GEN_INT (logval
);
3175 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3176 operands
[1] = GEN_INT (logval
% 8);
3179 return "bset %1,%0";
3181 return "or%.l %2,%0";
3185 output_xorsi3 (rtx
*operands
)
3187 register int logval
;
3188 if (GET_CODE (operands
[2]) == CONST_INT
3189 && INTVAL (operands
[2]) >> 16 == 0
3190 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3191 && !TARGET_COLDFIRE
)
3193 if (! DATA_REG_P (operands
[0]))
3194 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3195 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3197 if (INTVAL (operands
[2]) == 0xffff)
3199 return "eor%.w %2,%0";
3201 if (GET_CODE (operands
[2]) == CONST_INT
3202 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3203 && (DATA_REG_P (operands
[0])
3204 || offsettable_memref_p (operands
[0])))
3206 if (DATA_REG_P (operands
[0]))
3207 operands
[1] = GEN_INT (logval
);
3210 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3211 operands
[1] = GEN_INT (logval
% 8);
3214 return "bchg %1,%0";
3216 return "eor%.l %2,%0";
3219 #ifdef M68K_TARGET_COFF
3221 /* Output assembly to switch to section NAME with attribute FLAGS. */
3224 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3225 tree decl ATTRIBUTE_UNUSED
)
3229 if (flags
& SECTION_WRITE
)
3234 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3237 #endif /* M68K_TARGET_COFF */
3240 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3241 HOST_WIDE_INT delta
,
3242 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3248 if (delta
> 0 && delta
<= 8)
3249 asm_fprintf (file
, (MOTOROLA
3250 ? "\taddq.l %I%d,4(%Rsp)\n"
3251 : "\taddql %I%d,%Rsp@(4)\n"),
3253 else if (delta
< 0 && delta
>= -8)
3254 asm_fprintf (file
, (MOTOROLA
3255 ? "\tsubq.l %I%d,4(%Rsp)\n"
3256 : "\tsubql %I%d,%Rsp@(4)\n"),
3258 else if (TARGET_COLDFIRE
)
3260 /* ColdFire can't add/sub a constant to memory unless it is in
3261 the range of addq/subq. So load the value into %d0 and
3262 then add it to 4(%sp). */
3263 if (delta
>= -128 && delta
<= 127)
3264 asm_fprintf (file
, (MOTOROLA
3265 ? "\tmoveq.l %I%wd,%Rd0\n"
3266 : "\tmoveql %I%wd,%Rd0\n"),
3269 asm_fprintf (file
, (MOTOROLA
3270 ? "\tmove.l %I%wd,%Rd0\n"
3271 : "\tmovel %I%wd,%Rd0\n"),
3273 asm_fprintf (file
, (MOTOROLA
3274 ? "\tadd.l %Rd0,4(%Rsp)\n"
3275 : "\taddl %Rd0,%Rsp@(4)\n"));
3278 asm_fprintf (file
, (MOTOROLA
3279 ? "\tadd.l %I%wd,4(%Rsp)\n"
3280 : "\taddl %I%wd,%Rsp@(4)\n"),
3283 xops
[0] = DECL_RTL (function
);
3285 /* Logic taken from call patterns in m68k.md. */
3290 else if (flag_pic
== 1 || TARGET_68020
)
3294 #if defined (USE_GAS)
3295 fmt
= "bra.l %0@PLTPC";
3297 fmt
= "bra %0@PLTPC";
3300 else /* !MOTOROLA */
3309 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3310 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3312 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3316 #if MOTOROLA && !defined (USE_GAS)
3323 output_asm_insn (fmt
, xops
);
3326 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3329 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3330 int incoming ATTRIBUTE_UNUSED
)
3332 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3335 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3337 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3338 unsigned int new_reg
)
3341 /* Interrupt functions can only use registers that have already been
3342 saved by the prologue, even if they would normally be
3345 if (m68k_interrupt_function_p (current_function_decl
)
3346 && !regs_ever_live
[new_reg
])
3352 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3353 On the 68000, the cpu registers can hold any mode except bytes in address
3354 registers, but the 68881 registers can hold only SFmode or DFmode. */
3356 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3360 /* Data Registers, can hold aggregate if fits in. */
3361 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3364 else if (regno
< 16)
3366 /* Address Registers, can't hold bytes, can hold aggregate if
3368 if (GET_MODE_SIZE (mode
) == 1)
3370 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3373 else if (regno
< 24)
3375 /* FPU registers, hold float or complex float of long double or
3377 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3378 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3379 && GET_MODE_UNIT_SIZE (mode
) <= 12)