1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string
;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string
;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string
;
64 /* Specify power of two alignment used for loops. */
66 /* Specify power of two alignment used for non-loop jumps. */
68 /* Specify power of two alignment used for functions. */
71 /* Nonzero if the last compare/test insn had FP operands. The
72 sCC expanders peek at this to determine what to do for the
73 68060, which has no fsCC instructions. */
74 int m68k_last_compare_had_fp_operands
;
76 /* Sometimes certain combinations of command options do not make
77 sense on a particular target machine. You can define a macro
78 `OVERRIDE_OPTIONS' to take account of this. This macro, if
79 defined, is executed once just after all the command options have
82 Don't use this macro to turn on various extra optimizations for
83 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
92 /* Validate -malign-loops= value, or provide default */
93 if (m68k_align_loops_string
)
95 m68k_align_loops
= atoi (m68k_align_loops_string
);
96 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
97 fatal ("-malign-loops=%d is not between 1 and %d",
98 m68k_align_loops
, MAX_CODE_ALIGN
);
101 m68k_align_loops
= def_align
;
103 /* Validate -malign-jumps= value, or provide default */
104 if (m68k_align_jumps_string
)
106 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
107 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
108 fatal ("-malign-jumps=%d is not between 1 and %d",
109 m68k_align_jumps
, MAX_CODE_ALIGN
);
112 m68k_align_jumps
= def_align
;
114 /* Validate -malign-functions= value, or provide default */
115 if (m68k_align_funcs_string
)
117 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
118 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
119 fatal ("-malign-functions=%d is not between 1 and %d",
120 m68k_align_funcs
, MAX_CODE_ALIGN
);
123 m68k_align_funcs
= def_align
;
126 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
127 function at any time during the compilation process. In the future
128 we should try and eliminate the USE if we can easily determine that
129 all PIC references were deleted from the current function. That would
130 save an address register */
135 if (flag_pic
&& current_function_uses_pic_offset_table
)
137 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
138 emit_insn_after (insn
, get_insns ());
144 /* This function generates the assembly code for function entry.
145 STREAM is a stdio stream to output the code to.
146 SIZE is an int: how many units of temporary storage to allocate.
147 Refer to the array `regs_ever_live' to determine which registers
148 to save; `regs_ever_live[I]' is nonzero if register number I
149 is ever used in the function. This function is responsible for
150 knowing which registers should not be saved even if used. */
153 /* Note that the order of the bit mask for fmovem is the opposite
154 of the order for movem! */
158 output_function_prologue (stream
, size
)
163 register int mask
= 0;
164 int num_saved_regs
= 0;
165 extern char call_used_regs
[];
166 int fsize
= (size
+ 3) & -4;
169 if (frame_pointer_needed
)
171 if (fsize
== 0 && TARGET_68040
)
173 /* on the 68040, pea + move is faster than link.w 0 */
175 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
176 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
177 reg_names
[FRAME_POINTER_REGNUM
]);
179 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
180 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
181 reg_names
[FRAME_POINTER_REGNUM
]);
184 else if (fsize
< 0x8000)
187 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
188 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
190 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
191 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
194 else if (TARGET_68020
)
197 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
198 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
200 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
201 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
206 /* Adding negative number is faster on the 68040. */
208 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
209 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
211 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
212 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
218 if (fsize
+ 4 < 0x8000)
225 /* asm_fprintf() cannot handle %. */
227 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
229 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
234 /* asm_fprintf() cannot handle %. */
236 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
238 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
242 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
244 /* On the CPU32 it is faster to use two subqw instructions to
245 subtract a small integer (8 < N <= 16) to a register. */
246 /* asm_fprintf() cannot handle %. */
248 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
251 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
256 #endif /* NO_ADDSUB_Q */
259 /* Adding negative number is faster on the 68040. */
260 /* asm_fprintf() cannot handle %. */
262 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
264 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
270 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
272 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
278 /* asm_fprintf() cannot handle %. */
280 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
282 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
286 #ifdef SUPPORT_SUN_FPA
287 for (regno
= 24; regno
< 56; regno
++)
288 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
291 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
294 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
301 for (regno
= 16; regno
< 24; regno
++)
302 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
303 mask
|= 1 << (regno
- 16);
304 if ((mask
& 0xff) != 0)
307 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
309 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
314 for (regno
= 0; regno
< 16; regno
++)
315 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
317 mask
|= 1 << (15 - regno
);
320 if (frame_pointer_needed
)
322 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
329 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
331 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
334 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
338 if (num_saved_regs
<= 2)
340 /* Store each separately in the same order moveml uses.
341 Using two movel instructions instead of a single moveml
342 is about 15% faster for the 68020 and 68030 at no expense
347 /* Undo the work from above. */
348 for (i
= 0; i
< 16; i
++)
352 "\t%Omove.l %s,-(%Rsp)\n",
354 "\tmovel %s,%Rsp@-\n",
362 /* The coldfire does not support the predecrement form of the
363 movml instruction, so we must adjust the stack pointer and
364 then use the plain address register indirect mode. We also
365 have to invert the register save mask to use the new mode.
367 FIXME: if num_saved_regs was calculated earlier, we could
368 combine the stack pointer adjustment with any adjustment
369 done when the initial stack frame is created. This would
370 save an instruction */
375 for (i
= 0; i
< 16; i
++)
377 newmask
|= (1 << (15-i
));
380 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
381 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
383 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
384 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
390 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
392 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
396 if (flag_pic
&& current_function_uses_pic_offset_table
)
399 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
400 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
402 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
403 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
404 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
405 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
406 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
411 /* Return true if this function's epilogue can be output as RTL. */
418 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
421 /* Copied from output_function_epilogue (). We should probably create a
422 separate layout routine to perform the common work. */
424 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
425 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
431 /* This function generates the assembly code for function exit,
432 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
434 The function epilogue should not depend on the current stack pointer!
435 It should use the frame pointer only, if there is a frame pointer.
436 This is mandatory because of alloca; we also take advantage of it to
437 omit stack adjustments before returning. */
440 output_function_epilogue (stream
, size
)
445 register int mask
, fmask
;
447 int offset
, foffset
, fpoffset
;
448 extern char call_used_regs
[];
449 int fsize
= (size
+ 3) & -4;
451 rtx insn
= get_last_insn ();
452 int restore_from_sp
= 0;
454 /* If the last insn was a BARRIER, we don't have to write any code. */
455 if (GET_CODE (insn
) == NOTE
)
456 insn
= prev_nonnote_insn (insn
);
457 if (insn
&& GET_CODE (insn
) == BARRIER
)
459 /* Output just a no-op so that debuggers don't get confused
460 about which function the pc is in at this address. */
461 asm_fprintf (stream
, "\tnop\n");
465 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
466 if (profile_block_flag
== 2)
468 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
472 #ifdef FUNCTION_EXTRA_EPILOGUE
473 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
475 nregs
= 0; fmask
= 0; fpoffset
= 0;
476 #ifdef SUPPORT_SUN_FPA
477 for (regno
= 24 ; regno
< 56 ; regno
++)
478 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
480 fpoffset
= nregs
* 8;
485 for (regno
= 16; regno
< 24; regno
++)
486 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
489 fmask
|= 1 << (23 - regno
);
492 foffset
= fpoffset
+ nregs
* 12;
494 if (frame_pointer_needed
)
495 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
496 for (regno
= 0; regno
< 16; regno
++)
497 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
502 offset
= foffset
+ nregs
* 4;
503 /* FIXME : leaf_function_p below is too strong.
504 What we really need to know there is if there could be pending
505 stack adjustment needed at that point. */
506 restore_from_sp
= ! frame_pointer_needed
507 || (! current_function_calls_alloca
&& leaf_function_p ());
508 if (offset
+ fsize
>= 0x8000
510 && (mask
|| fmask
|| fpoffset
))
513 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
515 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
519 if (TARGET_5200
|| nregs
<= 2)
521 /* Restore each separately in the same order moveml does.
522 Using two movel instructions instead of a single moveml
523 is about 15% faster for the 68020 and 68030 at no expense
528 /* Undo the work from above. */
529 for (i
= 0; i
< 16; i
++)
535 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
537 reg_names
[FRAME_POINTER_REGNUM
],
540 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
541 reg_names
[FRAME_POINTER_REGNUM
],
542 offset
+ fsize
, reg_names
[i
]);
545 else if (restore_from_sp
)
548 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
551 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
558 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
560 reg_names
[FRAME_POINTER_REGNUM
],
563 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
564 reg_names
[FRAME_POINTER_REGNUM
],
565 offset
+ fsize
, reg_names
[i
]);
576 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
578 reg_names
[FRAME_POINTER_REGNUM
],
581 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
582 reg_names
[FRAME_POINTER_REGNUM
],
583 offset
+ fsize
, mask
);
586 else if (restore_from_sp
)
589 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
591 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
597 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
599 reg_names
[FRAME_POINTER_REGNUM
],
602 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
603 reg_names
[FRAME_POINTER_REGNUM
],
604 offset
+ fsize
, mask
);
613 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
615 reg_names
[FRAME_POINTER_REGNUM
],
618 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
619 reg_names
[FRAME_POINTER_REGNUM
],
620 foffset
+ fsize
, fmask
);
623 else if (restore_from_sp
)
626 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
628 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
634 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
636 reg_names
[FRAME_POINTER_REGNUM
],
639 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
640 reg_names
[FRAME_POINTER_REGNUM
],
641 foffset
+ fsize
, fmask
);
646 for (regno
= 55; regno
>= 24; regno
--)
647 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
652 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
654 reg_names
[FRAME_POINTER_REGNUM
],
657 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
658 reg_names
[FRAME_POINTER_REGNUM
],
659 fpoffset
+ fsize
, reg_names
[regno
]);
662 else if (restore_from_sp
)
665 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
668 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
675 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
677 reg_names
[FRAME_POINTER_REGNUM
],
680 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
681 reg_names
[FRAME_POINTER_REGNUM
],
682 fpoffset
+ fsize
, reg_names
[regno
]);
687 if (frame_pointer_needed
)
688 fprintf (stream
, "\tunlk %s\n",
689 reg_names
[FRAME_POINTER_REGNUM
]);
698 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
700 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
706 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
708 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
712 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
714 /* On the CPU32 it is faster to use two addqw instructions to
715 add a small integer (8 < N <= 16) to a register. */
716 /* asm_fprintf() cannot handle %. */
718 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
721 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
726 #endif /* NO_ADDSUB_Q */
727 if (fsize
+ 4 < 0x8000)
731 /* asm_fprintf() cannot handle %. */
733 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
735 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
741 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
743 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
749 /* asm_fprintf() cannot handle %. */
751 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
753 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
757 if (current_function_pops_args
)
758 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
760 fprintf (stream
, "\trts\n");
763 /* Similar to general_operand, but exclude stack_pointer_rtx. */
766 not_sp_operand (op
, mode
)
768 enum machine_mode mode
;
770 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
773 /* Return TRUE if X is a valid comparison operator for the dbcc
776 Note it rejects floating point comparison operators.
777 (In the future we could use Fdbcc).
779 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
782 valid_dbcc_comparison_p (x
, mode
)
784 enum machine_mode mode
;
786 switch (GET_CODE (x
))
788 case EQ
: case NE
: case GTU
: case LTU
:
792 /* Reject some when CC_NO_OVERFLOW is set. This may be over
794 case GT
: case LT
: case GE
: case LE
:
795 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
801 /* Return non-zero if flags are currently in the 68881 flag register. */
805 /* We could add support for these in the future */
806 return cc_status
.flags
& CC_IN_68881
;
809 /* Output a dbCC; jCC sequence. Note we do not handle the
810 floating point version of this sequence (Fdbcc). We also
811 do not handle alternative conditions when CC_NO_OVERFLOW is
812 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
813 kick those out before we get here. */
815 output_dbcc_and_branch (operands
)
818 switch (GET_CODE (operands
[3]))
822 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
824 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
830 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
832 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
838 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
840 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
846 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
848 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
854 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
856 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
862 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
864 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
870 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
872 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
878 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
880 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
886 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
888 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
894 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
896 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
904 /* If the decrement is to be done in SImode, then we have
905 to compensate for the fact that dbcc decrements in HImode. */
906 switch (GET_MODE (operands
[0]))
910 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
912 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
925 output_scc_di(op
, operand1
, operand2
, dest
)
932 enum rtx_code op_code
= GET_CODE (op
);
934 /* This does not produce a usefull cc. */
937 /* The m68k cmp.l instruction requires operand1 to be a reg as used
938 below. Swap the operands and change the op if these requirements
939 are not fulfilled. */
940 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
946 op_code
= swap_condition (op_code
);
948 loperands
[0] = operand1
;
949 if (GET_CODE (operand1
) == REG
)
950 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
952 loperands
[1] = adj_offsettable_operand (operand1
, 4);
953 if (operand2
!= const0_rtx
)
955 loperands
[2] = operand2
;
956 if (GET_CODE (operand2
) == REG
)
957 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
959 loperands
[3] = adj_offsettable_operand (operand2
, 4);
961 loperands
[4] = gen_label_rtx();
962 if (operand2
!= const0_rtx
)
965 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
967 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
971 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
973 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
978 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
980 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
987 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
988 CODE_LABEL_NUMBER (loperands
[4]));
989 output_asm_insn ("seq %5", loperands
);
993 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
994 CODE_LABEL_NUMBER (loperands
[4]));
995 output_asm_insn ("sne %5", loperands
);
999 loperands
[6] = gen_label_rtx();
1001 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1003 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1005 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1006 CODE_LABEL_NUMBER (loperands
[4]));
1007 output_asm_insn ("sgt %5", loperands
);
1008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1009 CODE_LABEL_NUMBER (loperands
[6]));
1013 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1014 CODE_LABEL_NUMBER (loperands
[4]));
1015 output_asm_insn ("shi %5", loperands
);
1019 loperands
[6] = gen_label_rtx();
1021 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1023 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1025 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1026 CODE_LABEL_NUMBER (loperands
[4]));
1027 output_asm_insn ("slt %5", loperands
);
1028 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1029 CODE_LABEL_NUMBER (loperands
[6]));
1033 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1034 CODE_LABEL_NUMBER (loperands
[4]));
1035 output_asm_insn ("scs %5", loperands
);
1039 loperands
[6] = gen_label_rtx();
1041 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1043 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1045 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1046 CODE_LABEL_NUMBER (loperands
[4]));
1047 output_asm_insn ("sge %5", loperands
);
1048 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1049 CODE_LABEL_NUMBER (loperands
[6]));
1053 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1054 CODE_LABEL_NUMBER (loperands
[4]));
1055 output_asm_insn ("scc %5", loperands
);
1059 loperands
[6] = gen_label_rtx();
1061 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1063 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1066 CODE_LABEL_NUMBER (loperands
[4]));
1067 output_asm_insn ("sle %5", loperands
);
1068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1069 CODE_LABEL_NUMBER (loperands
[6]));
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1074 CODE_LABEL_NUMBER (loperands
[4]));
1075 output_asm_insn ("sls %5", loperands
);
1085 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1087 rtx countop
, dataop
;
1091 operands
[0] = countop
;
1092 operands
[1] = dataop
;
1094 if (GET_CODE (countop
) == CONST_INT
)
1096 register int count
= INTVAL (countop
);
1097 /* If COUNT is bigger than size of storage unit in use,
1098 advance to the containing unit of same size. */
1099 if (count
> signpos
)
1101 int offset
= (count
& ~signpos
) / 8;
1102 count
= count
& signpos
;
1103 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1105 if (count
== signpos
)
1106 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1108 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1110 /* These three statements used to use next_insns_test_no...
1111 but it appears that this should do the same job. */
1113 && next_insn_tests_no_inequality (insn
))
1116 && next_insn_tests_no_inequality (insn
))
1119 && next_insn_tests_no_inequality (insn
))
1122 cc_status
.flags
= CC_NOT_NEGATIVE
;
1124 return "btst %0,%1";
1127 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1128 reference and a constant. */
1131 symbolic_operand (op
, mode
)
1133 enum machine_mode mode
;
1135 switch (GET_CODE (op
))
1143 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1144 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1145 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1147 #if 0 /* Deleted, with corresponding change in m68k.h,
1148 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1150 return GET_MODE (op
) == mode
;
1158 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1161 extend_operator(x
, mode
)
1163 enum machine_mode mode
;
1165 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1167 switch (GET_CODE(x
))
1178 /* Legitimize PIC addresses. If the address is already
1179 position-independent, we return ORIG. Newly generated
1180 position-independent addresses go to REG. If we need more
1181 than one register, we lose.
1183 An address is legitimized by making an indirect reference
1184 through the Global Offset Table with the name of the symbol
1187 The assembler and linker are responsible for placing the
1188 address of the symbol in the GOT. The function prologue
1189 is responsible for initializing a5 to the starting address
1192 The assembler is also responsible for translating a symbol name
1193 into a constant displacement from the start of the GOT.
1195 A quick example may make things a little clearer:
1197 When not generating PIC code to store the value 12345 into _foo
1198 we would generate the following code:
1202 When generating PIC two transformations are made. First, the compiler
1203 loads the address of foo into a register. So the first transformation makes:
1208 The code in movsi will intercept the lea instruction and call this
1209 routine which will transform the instructions into:
1211 movel a5@(_foo:w), a0
1215 That (in a nutshell) is how *all* symbol and label references are
1219 legitimize_pic_address (orig
, mode
, reg
)
1221 enum machine_mode mode
;
1225 /* First handle a simple SYMBOL_REF or LABEL_REF */
1226 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1231 pic_ref
= gen_rtx (MEM
, Pmode
,
1232 gen_rtx (PLUS
, Pmode
,
1233 pic_offset_table_rtx
, orig
));
1234 current_function_uses_pic_offset_table
= 1;
1235 RTX_UNCHANGING_P (pic_ref
) = 1;
1236 emit_move_insn (reg
, pic_ref
);
1239 else if (GET_CODE (orig
) == CONST
)
1243 /* Make sure this is CONST has not already been legitimized */
1244 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1245 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1251 /* legitimize both operands of the PLUS */
1252 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1254 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1255 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1256 base
== reg
? 0 : reg
);
1260 if (GET_CODE (orig
) == CONST_INT
)
1261 return plus_constant_for_output (base
, INTVAL (orig
));
1262 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1263 /* Likewise, should we set special REG_NOTEs here? */
1269 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1271 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1274 const_method (constant
)
1280 i
= INTVAL (constant
);
1284 /* The Coldfire doesn't have byte or word operations. */
1285 /* FIXME: This may not be useful for the m68060 either */
1288 /* if -256 < N < 256 but N is not in range for a moveq
1289 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1290 if (USE_MOVQ (i
^ 0xff))
1292 /* Likewise, try with not.w */
1293 if (USE_MOVQ (i
^ 0xffff))
1295 /* This is the only value where neg.w is useful */
1298 /* Try also with swap */
1300 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1303 /* Otherwise, use move.l */
1307 const_int_cost (constant
)
1310 switch (const_method (constant
))
1313 /* Constants between -128 and 127 are cheap due to moveq */
1319 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1329 output_move_const_into_data_reg (operands
)
1334 i
= INTVAL (operands
[1]);
1335 switch (const_method (operands
[1]))
1338 #if defined (MOTOROLA) && !defined (CRDS)
1339 return "moveq%.l %1,%0";
1341 return "moveq %1,%0";
1344 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1345 #if defined (MOTOROLA) && !defined (CRDS)
1346 return "moveq%.l %1,%0\n\tnot%.b %0";
1348 return "moveq %1,%0\n\tnot%.b %0";
1351 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1352 #if defined (MOTOROLA) && !defined (CRDS)
1353 return "moveq%.l %1,%0\n\tnot%.w %0";
1355 return "moveq %1,%0\n\tnot%.w %0";
1358 #if defined (MOTOROLA) && !defined (CRDS)
1359 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1361 return "moveq %#-128,%0\n\tneg%.w %0";
1367 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1368 #if defined (MOTOROLA) && !defined (CRDS)
1369 return "moveq%.l %1,%0\n\tswap %0";
1371 return "moveq %1,%0\n\tswap %0";
1375 return "move%.l %1,%0";
1382 output_move_simode_const (operands
)
1385 if (operands
[1] == const0_rtx
1386 && (DATA_REG_P (operands
[0])
1387 || GET_CODE (operands
[0]) == MEM
)
1388 /* clr insns on 68000 read before writing.
1389 This isn't so on the 68010, but we have no TARGET_68010. */
1390 && ((TARGET_68020
|| TARGET_5200
)
1391 || !(GET_CODE (operands
[0]) == MEM
1392 && MEM_VOLATILE_P (operands
[0]))))
1394 else if (DATA_REG_P (operands
[0]))
1395 return output_move_const_into_data_reg (operands
);
1396 else if (ADDRESS_REG_P (operands
[0])
1397 && INTVAL (operands
[1]) < 0x8000
1398 && INTVAL (operands
[1]) >= -0x8000)
1399 return "move%.w %1,%0";
1400 else if (GET_CODE (operands
[0]) == MEM
1401 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1402 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1403 && INTVAL (operands
[1]) < 0x8000
1404 && INTVAL (operands
[1]) >= -0x8000)
1406 return "move%.l %1,%0";
1409 /* Return the best assembler insn template
1410 for moving operands[1] into operands[0] as a fullword. */
1413 singlemove_string (operands
)
1416 #ifdef SUPPORT_SUN_FPA
1417 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1418 return "fpmoves %1,%0";
1420 if (GET_CODE (operands
[1]) == CONST_INT
)
1421 return output_move_simode_const (operands
);
1422 return "move%.l %1,%0";
1426 /* Output assembler code to perform a doubleword move insn
1427 with operands OPERANDS. */
1430 output_move_double (operands
)
1435 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1440 rtx addreg0
= 0, addreg1
= 0;
1441 int dest_overlapped_low
= 0;
1442 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1447 /* First classify both operands. */
1449 if (REG_P (operands
[0]))
1451 else if (offsettable_memref_p (operands
[0]))
1453 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1455 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1457 else if (GET_CODE (operands
[0]) == MEM
)
1462 if (REG_P (operands
[1]))
1464 else if (CONSTANT_P (operands
[1]))
1466 else if (offsettable_memref_p (operands
[1]))
1468 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1470 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1472 else if (GET_CODE (operands
[1]) == MEM
)
1477 /* Check for the cases that the operand constraints are not
1478 supposed to allow to happen. Abort if we get one,
1479 because generating code for these cases is painful. */
1481 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1484 /* If one operand is decrementing and one is incrementing
1485 decrement the former register explicitly
1486 and change that operand into ordinary indexing. */
1488 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1490 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1492 output_asm_insn ("sub%.l %#12,%0", operands
);
1494 output_asm_insn ("subq%.l %#8,%0", operands
);
1495 if (GET_MODE (operands
[1]) == XFmode
)
1496 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1497 else if (GET_MODE (operands
[0]) == DFmode
)
1498 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1500 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1503 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1505 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1507 output_asm_insn ("sub%.l %#12,%1", operands
);
1509 output_asm_insn ("subq%.l %#8,%1", operands
);
1510 if (GET_MODE (operands
[1]) == XFmode
)
1511 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1512 else if (GET_MODE (operands
[1]) == DFmode
)
1513 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1515 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1519 /* If an operand is an unoffsettable memory ref, find a register
1520 we can increment temporarily to make it refer to the second word. */
1522 if (optype0
== MEMOP
)
1523 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1525 if (optype1
== MEMOP
)
1526 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1528 /* Ok, we can do one word at a time.
1529 Normally we do the low-numbered word first,
1530 but if either operand is autodecrementing then we
1531 do the high-numbered word first.
1533 In either case, set up in LATEHALF the operands to use
1534 for the high-numbered word and in some cases alter the
1535 operands in OPERANDS to be suitable for the low-numbered word. */
1539 if (optype0
== REGOP
)
1541 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1542 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1544 else if (optype0
== OFFSOP
)
1546 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1547 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1551 middlehalf
[0] = operands
[0];
1552 latehalf
[0] = operands
[0];
1555 if (optype1
== REGOP
)
1557 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1558 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1560 else if (optype1
== OFFSOP
)
1562 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1563 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1565 else if (optype1
== CNSTOP
)
1567 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1572 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1573 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1574 operands
[1] = GEN_INT (l
[0]);
1575 middlehalf
[1] = GEN_INT (l
[1]);
1576 latehalf
[1] = GEN_INT (l
[2]);
1578 else if (CONSTANT_P (operands
[1]))
1580 /* actually, no non-CONST_DOUBLE constant should ever
1583 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1584 latehalf
[1] = constm1_rtx
;
1586 latehalf
[1] = const0_rtx
;
1591 middlehalf
[1] = operands
[1];
1592 latehalf
[1] = operands
[1];
1596 /* size is not 12: */
1598 if (optype0
== REGOP
)
1599 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1600 else if (optype0
== OFFSOP
)
1601 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1603 latehalf
[0] = operands
[0];
1605 if (optype1
== REGOP
)
1606 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1607 else if (optype1
== OFFSOP
)
1608 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1609 else if (optype1
== CNSTOP
)
1610 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1612 latehalf
[1] = operands
[1];
1615 /* If insn is effectively movd N(sp),-(sp) then we will do the
1616 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1617 for the low word as well, to compensate for the first decrement of sp. */
1618 if (optype0
== PUSHOP
1619 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1620 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1621 operands
[1] = middlehalf
[1] = latehalf
[1];
1623 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1624 if the upper part of reg N does not appear in the MEM, arrange to
1625 emit the move late-half first. Otherwise, compute the MEM address
1626 into the upper part of N and use that as a pointer to the memory
1628 if (optype0
== REGOP
1629 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1631 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1633 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1634 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1636 /* If both halves of dest are used in the src memory address,
1637 compute the address into latehalf of dest.
1638 Note that this can't happen if the dest is two data regs. */
1640 xops
[0] = latehalf
[0];
1641 xops
[1] = XEXP (operands
[1], 0);
1642 output_asm_insn ("lea %a1,%0", xops
);
1643 if( GET_MODE (operands
[1]) == XFmode
)
1645 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1646 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1647 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1651 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1652 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1656 && reg_overlap_mentioned_p (middlehalf
[0],
1657 XEXP (operands
[1], 0)))
1659 /* Check for two regs used by both source and dest.
1660 Note that this can't happen if the dest is all data regs.
1661 It can happen if the dest is d6, d7, a0.
1662 But in that case, latehalf is an addr reg, so
1663 the code at compadr does ok. */
1665 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1666 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1669 /* JRV says this can't happen: */
1670 if (addreg0
|| addreg1
)
1673 /* Only the middle reg conflicts; simply put it last. */
1674 output_asm_insn (singlemove_string (operands
), operands
);
1675 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1676 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1679 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1680 /* If the low half of dest is mentioned in the source memory
1681 address, the arrange to emit the move late half first. */
1682 dest_overlapped_low
= 1;
1685 /* If one or both operands autodecrementing,
1686 do the two words, high-numbered first. */
1688 /* Likewise, the first move would clobber the source of the second one,
1689 do them in the other order. This happens only for registers;
1690 such overlap can't happen in memory unless the user explicitly
1691 sets it up, and that is an undefined circumstance. */
1693 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1694 || (optype0
== REGOP
&& optype1
== REGOP
1695 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1696 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1697 || dest_overlapped_low
)
1699 /* Make any unoffsettable addresses point at high-numbered word. */
1703 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1705 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1710 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1712 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1716 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1718 /* Undo the adds we just did. */
1720 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1722 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1726 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1728 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1730 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1733 /* Do low-numbered word. */
1734 return singlemove_string (operands
);
1737 /* Normal case: do the two words, low-numbered first. */
1739 output_asm_insn (singlemove_string (operands
), operands
);
1741 /* Do the middle one of the three words for long double */
1745 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1747 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1749 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1752 /* Make any unoffsettable addresses point at high-numbered word. */
1754 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1756 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1759 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1761 /* Undo the adds we just did. */
1765 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1767 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1772 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1774 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1780 /* Return a REG that occurs in ADDR with coefficient 1.
1781 ADDR can be effectively incremented by incrementing REG. */
1784 find_addr_reg (addr
)
1787 while (GET_CODE (addr
) == PLUS
)
1789 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1790 addr
= XEXP (addr
, 0);
1791 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1792 addr
= XEXP (addr
, 1);
1793 else if (CONSTANT_P (XEXP (addr
, 0)))
1794 addr
= XEXP (addr
, 1);
1795 else if (CONSTANT_P (XEXP (addr
, 1)))
1796 addr
= XEXP (addr
, 0);
1800 if (GET_CODE (addr
) == REG
)
1805 /* Store in cc_status the expressions that the condition codes will
1806 describe after execution of an instruction whose pattern is EXP.
1807 Do not alter them if the instruction would not alter the cc's. */
1809 /* On the 68000, all the insns to store in an address register fail to
1810 set the cc's. However, in some cases these instructions can make it
1811 possibly invalid to use the saved cc's. In those cases we clear out
1812 some or all of the saved cc's so they won't be used. */
1814 notice_update_cc (exp
, insn
)
1818 /* If the cc is being set from the fpa and the expression is not an
1819 explicit floating point test instruction (which has code to deal with
1820 this), reinit the CC. */
1821 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1822 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1823 && !(GET_CODE (exp
) == PARALLEL
1824 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1825 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1829 else if (GET_CODE (exp
) == SET
)
1831 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1835 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1837 if (cc_status
.value1
1838 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1839 cc_status
.value1
= 0;
1840 if (cc_status
.value2
1841 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1842 cc_status
.value2
= 0;
1844 else if (!FP_REG_P (SET_DEST (exp
))
1845 && SET_DEST (exp
) != cc0_rtx
1846 && (FP_REG_P (SET_SRC (exp
))
1847 || GET_CODE (SET_SRC (exp
)) == FIX
1848 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1849 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1853 /* A pair of move insns doesn't produce a useful overall cc. */
1854 else if (!FP_REG_P (SET_DEST (exp
))
1855 && !FP_REG_P (SET_SRC (exp
))
1856 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1857 && (GET_CODE (SET_SRC (exp
)) == REG
1858 || GET_CODE (SET_SRC (exp
)) == MEM
1859 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1863 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1867 else if (XEXP (exp
, 0) != pc_rtx
)
1869 cc_status
.flags
= 0;
1870 cc_status
.value1
= XEXP (exp
, 0);
1871 cc_status
.value2
= XEXP (exp
, 1);
1874 else if (GET_CODE (exp
) == PARALLEL
1875 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1877 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1879 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1881 cc_status
.flags
= 0;
1882 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1883 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1888 if (cc_status
.value2
!= 0
1889 && ADDRESS_REG_P (cc_status
.value2
)
1890 && GET_MODE (cc_status
.value2
) == QImode
)
1892 if (cc_status
.value2
!= 0
1893 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1894 switch (GET_CODE (cc_status
.value2
))
1896 case PLUS
: case MINUS
: case MULT
:
1897 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1898 #if 0 /* These instructions always clear the overflow bit */
1899 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1900 case ROTATE
: case ROTATERT
:
1902 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1903 cc_status
.flags
|= CC_NO_OVERFLOW
;
1906 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1907 ends with a move insn moving r2 in r2's mode.
1908 Thus, the cc's are set for r2.
1909 This can set N bit spuriously. */
1910 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1912 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1914 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1915 cc_status
.value2
= 0;
1916 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1917 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1918 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1919 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1920 cc_status
.flags
= CC_IN_68881
;
1924 output_move_const_double (operands
)
1927 #ifdef SUPPORT_SUN_FPA
1928 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1930 int code
= standard_sun_fpa_constant_p (operands
[1]);
1934 static char buf
[40];
1936 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1939 return "fpmove%.d %1,%0";
1944 int code
= standard_68881_constant_p (operands
[1]);
1948 static char buf
[40];
1950 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1953 return "fmove%.d %1,%0";
1958 output_move_const_single (operands
)
1961 #ifdef SUPPORT_SUN_FPA
1964 int code
= standard_sun_fpa_constant_p (operands
[1]);
1968 static char buf
[40];
1970 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1973 return "fpmove%.s %1,%0";
1976 #endif /* defined SUPPORT_SUN_FPA */
1978 int code
= standard_68881_constant_p (operands
[1]);
1982 static char buf
[40];
1984 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1987 return "fmove%.s %f1,%0";
1991 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1992 from the "fmovecr" instruction.
1993 The value, anded with 0xff, gives the code to use in fmovecr
1994 to get the desired constant. */
1996 /* This code has been fixed for cross-compilation. */
1998 static int inited_68881_table
= 0;
2000 char *strings_68881
[7] = {
2010 int codes_68881
[7] = {
2020 REAL_VALUE_TYPE values_68881
[7];
2022 /* Set up values_68881 array by converting the decimal values
2023 strings_68881 to binary. */
2030 enum machine_mode mode
;
2033 for (i
= 0; i
< 7; i
++)
2037 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2038 values_68881
[i
] = r
;
2040 inited_68881_table
= 1;
2044 standard_68881_constant_p (x
)
2049 enum machine_mode mode
;
2051 #ifdef NO_ASM_FMOVECR
2055 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2059 #ifndef REAL_ARITHMETIC
2060 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2061 if (! flag_pretend_float
)
2066 if (! inited_68881_table
)
2067 init_68881_table ();
2069 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2071 for (i
= 0; i
< 6; i
++)
2073 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2074 return (codes_68881
[i
]);
2077 if (GET_MODE (x
) == SFmode
)
2080 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2081 return (codes_68881
[6]);
2083 /* larger powers of ten in the constants ram are not used
2084 because they are not equal to a `double' C constant. */
2088 /* If X is a floating-point constant, return the logarithm of X base 2,
2089 or 0 if X is not a power of 2. */
2092 floating_exact_log2 (x
)
2095 REAL_VALUE_TYPE r
, r1
;
2098 #ifndef REAL_ARITHMETIC
2099 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2100 if (! flag_pretend_float
)
2105 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2107 if (REAL_VALUES_LESS (r
, dconst0
))
2112 while (REAL_VALUES_LESS (r1
, r
))
2114 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2115 if (REAL_VALUES_EQUAL (r1
, r
))
2122 #ifdef SUPPORT_SUN_FPA
2123 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2124 from the Sun FPA's constant RAM.
2125 The value returned, anded with 0x1ff, gives the code to use in fpmove
2126 to get the desired constant. */
2128 static int inited_FPA_table
= 0;
2130 char *strings_FPA
[38] = {
2131 /* small rationals */
2144 /* Decimal equivalents of double precision values */
2145 "2.718281828459045091", /* D_E */
2146 "6.283185307179586477", /* 2 pi */
2147 "3.141592653589793116", /* D_PI */
2148 "1.570796326794896619", /* pi/2 */
2149 "1.414213562373095145", /* D_SQRT2 */
2150 "0.7071067811865475244", /* 1/sqrt(2) */
2151 "-1.570796326794896619", /* -pi/2 */
2152 "1.442695040888963387", /* D_LOG2ofE */
2153 "3.321928024887362182", /* D_LOG2of10 */
2154 "0.6931471805599452862", /* D_LOGEof2 */
2155 "2.302585092994045901", /* D_LOGEof10 */
2156 "0.3010299956639811980", /* D_LOG10of2 */
2157 "0.4342944819032518167", /* D_LOG10ofE */
2158 /* Decimal equivalents of single precision values */
2159 "2.718281745910644531", /* S_E */
2160 "6.283185307179586477", /* 2 pi */
2161 "3.141592741012573242", /* S_PI */
2162 "1.570796326794896619", /* pi/2 */
2163 "1.414213538169860840", /* S_SQRT2 */
2164 "0.7071067811865475244", /* 1/sqrt(2) */
2165 "-1.570796326794896619", /* -pi/2 */
2166 "1.442695021629333496", /* S_LOG2ofE */
2167 "3.321928024291992188", /* S_LOG2of10 */
2168 "0.6931471824645996094", /* S_LOGEof2 */
2169 "2.302585124969482442", /* S_LOGEof10 */
2170 "0.3010300099849700928", /* S_LOG10of2 */
2171 "0.4342944920063018799", /* S_LOG10ofE */
2175 int codes_FPA
[38] = {
2176 /* small rationals */
2189 /* double precision */
2203 /* single precision */
2219 REAL_VALUE_TYPE values_FPA
[38];
2221 /* This code has been fixed for cross-compilation. */
2226 enum machine_mode mode
;
2231 for (i
= 0; i
< 38; i
++)
2235 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2238 inited_FPA_table
= 1;
2243 standard_sun_fpa_constant_p (x
)
2249 #ifndef REAL_ARITHMETIC
2250 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2251 if (! flag_pretend_float
)
2256 if (! inited_FPA_table
)
2259 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2261 for (i
=0; i
<12; i
++)
2263 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2264 return (codes_FPA
[i
]);
2267 if (GET_MODE (x
) == SFmode
)
2269 for (i
=25; i
<38; i
++)
2271 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2272 return (codes_FPA
[i
]);
2277 for (i
=12; i
<25; i
++)
2279 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2280 return (codes_FPA
[i
]);
2285 #endif /* define SUPPORT_SUN_FPA */
2287 /* A C compound statement to output to stdio stream STREAM the
2288 assembler syntax for an instruction operand X. X is an RTL
2291 CODE is a value that can be used to specify one of several ways
2292 of printing the operand. It is used when identical operands
2293 must be printed differently depending on the context. CODE
2294 comes from the `%' specification that was used to request
2295 printing of the operand. If the specification was just `%DIGIT'
2296 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2297 is the ASCII code for LTR.
2299 If X is a register, this macro should print the register's name.
2300 The names can be found in an array `reg_names' whose type is
2301 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2303 When the machine description has a specification `%PUNCT' (a `%'
2304 followed by a punctuation character), this macro is called with
2305 a null pointer for X and the punctuation character for CODE.
2307 The m68k specific codes are:
2309 '.' for dot needed in Motorola-style opcode names.
2310 '-' for an operand pushing on the stack:
2311 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2312 '+' for an operand pushing on the stack:
2313 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2314 '@' for a reference to the top word on the stack:
2315 sp@, (sp) or (%sp) depending on the style of syntax.
2316 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2317 but & in SGS syntax, $ in CRDS/UNOS syntax).
2318 '!' for the cc register (used in an `and to cc' insn).
2319 '$' for the letter `s' in an op code, but only on the 68040.
2320 '&' for the letter `d' in an op code, but only on the 68040.
2321 '/' for register prefix needed by longlong.h.
2323 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2324 'd' to force memory addressing to be absolute, not relative.
2325 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2326 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2327 than directly). Second part of 'y' below.
2328 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2329 or print pair of registers as rx:ry.
2330 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2331 CONST_DOUBLE's as SunFPA constant RAM registers if
2332 possible, so it should not be used except for the SunFPA.
2337 print_operand (file
, op
, letter
)
2338 FILE *file
; /* file to write to */
2339 rtx op
; /* operand to print */
2340 int letter
; /* %<letter> or 0 */
2346 #if defined (MOTOROLA) && !defined (CRDS)
2347 asm_fprintf (file
, ".");
2350 else if (letter
== '#')
2352 asm_fprintf (file
, "%0I");
2354 else if (letter
== '-')
2357 asm_fprintf (file
, "-(%Rsp)");
2359 asm_fprintf (file
, "%Rsp@-");
2362 else if (letter
== '+')
2365 asm_fprintf (file
, "(%Rsp)+");
2367 asm_fprintf (file
, "%Rsp@+");
2370 else if (letter
== '@')
2373 asm_fprintf (file
, "(%Rsp)");
2375 asm_fprintf (file
, "%Rsp@");
2378 else if (letter
== '!')
2380 asm_fprintf (file
, "%Rfpcr");
2382 else if (letter
== '$')
2384 if (TARGET_68040_ONLY
)
2386 fprintf (file
, "s");
2389 else if (letter
== '&')
2391 if (TARGET_68040_ONLY
)
2393 fprintf (file
, "d");
2396 else if (letter
== '/')
2398 asm_fprintf (file
, "%R");
2400 else if (GET_CODE (op
) == REG
)
2402 #ifdef SUPPORT_SUN_FPA
2404 && (letter
== 'y' || letter
== 'x')
2405 && GET_MODE (op
) == DFmode
)
2407 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2408 reg_names
[REGNO (op
)+1]);
2414 /* Print out the second register name of a register pair.
2415 I.e., R (6) => 7. */
2416 fputs (reg_names
[REGNO (op
) + 1], file
);
2418 fputs (reg_names
[REGNO (op
)], file
);
2421 else if (GET_CODE (op
) == MEM
)
2423 output_address (XEXP (op
, 0));
2424 if (letter
== 'd' && ! TARGET_68020
2425 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2426 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2427 && INTVAL (XEXP (op
, 0)) < 0x8000
2428 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2431 fprintf (file
, ".l");
2433 fprintf (file
, ":l");
2437 #ifdef SUPPORT_SUN_FPA
2438 else if ((letter
== 'y' || letter
== 'w')
2439 && GET_CODE (op
) == CONST_DOUBLE
2440 && (i
= standard_sun_fpa_constant_p (op
)))
2442 fprintf (file
, "%%%d", i
& 0x1ff);
2445 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2448 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2449 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2451 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2454 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2455 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2457 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2460 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2461 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2465 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2470 /* A C compound statement to output to stdio stream STREAM the
2471 assembler syntax for an instruction operand that is a memory
2472 reference whose address is ADDR. ADDR is an RTL expression.
2474 Note that this contains a kludge that knows that the only reason
2475 we have an address (plus (label_ref...) (reg...)) when not generating
2476 PIC code is in the insn before a tablejump, and we know that m68k.md
2477 generates a label LInnn: on such an insn.
2479 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2480 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2482 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2483 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2484 we want. This difference can be accommodated by using an assembler
2485 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2486 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2487 macro. See m68k/sgs.h for an example; for versions without the bug.
2488 Some assemblers refuse all the above solutions. The workaround is to
2489 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2492 They also do not like things like "pea 1.w", so we simple leave off
2493 the .w on small constants.
2495 This routine is responsible for distinguishing between -fpic and -fPIC
2496 style relocations in an address. When generating -fpic code the
2497 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2498 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2500 #ifndef ASM_OUTPUT_CASE_FETCH
2503 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2504 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2506 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2507 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2510 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2511 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2513 #endif /* ASM_OUTPUT_CASE_FETCH */
2516 print_operand_address (file
, addr
)
2520 register rtx reg1
, reg2
, breg
, ireg
;
2523 switch (GET_CODE (addr
))
2527 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2529 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2534 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2536 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2541 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2543 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2547 reg1
= reg2
= ireg
= breg
= offset
= 0;
2548 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2550 offset
= XEXP (addr
, 0);
2551 addr
= XEXP (addr
, 1);
2553 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2555 offset
= XEXP (addr
, 1);
2556 addr
= XEXP (addr
, 0);
2558 if (GET_CODE (addr
) != PLUS
)
2562 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2564 reg1
= XEXP (addr
, 0);
2565 addr
= XEXP (addr
, 1);
2567 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2569 reg1
= XEXP (addr
, 1);
2570 addr
= XEXP (addr
, 0);
2572 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2574 reg1
= XEXP (addr
, 0);
2575 addr
= XEXP (addr
, 1);
2577 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2579 reg1
= XEXP (addr
, 1);
2580 addr
= XEXP (addr
, 0);
2582 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2584 reg1
= XEXP (addr
, 0);
2585 addr
= XEXP (addr
, 1);
2587 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2589 reg1
= XEXP (addr
, 1);
2590 addr
= XEXP (addr
, 0);
2592 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2593 || GET_CODE (addr
) == SIGN_EXTEND
)
2605 #if 0 /* for OLD_INDEXING */
2606 else if (GET_CODE (addr
) == PLUS
)
2608 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2610 reg2
= XEXP (addr
, 0);
2611 addr
= XEXP (addr
, 1);
2613 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2615 reg2
= XEXP (addr
, 1);
2616 addr
= XEXP (addr
, 0);
2628 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2629 || GET_CODE (reg1
) == MULT
))
2630 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2635 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2640 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2641 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2644 if (GET_CODE (ireg
) == MULT
)
2646 scale
= INTVAL (XEXP (ireg
, 1));
2647 ireg
= XEXP (ireg
, 0);
2649 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2651 ASM_OUTPUT_CASE_FETCH (file
,
2652 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2653 reg_names
[REGNO (XEXP (ireg
, 0))]);
2654 fprintf (file
, "w");
2658 ASM_OUTPUT_CASE_FETCH (file
,
2659 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2660 reg_names
[REGNO (ireg
)]);
2661 fprintf (file
, "l");
2666 fprintf (file
, "*%d", scale
);
2668 fprintf (file
, ":%d", scale
);
2674 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2675 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2677 ASM_OUTPUT_CASE_FETCH (file
,
2678 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2679 reg_names
[REGNO (breg
)]);
2680 fprintf (file
, "l)");
2683 if (ireg
!= 0 || breg
!= 0)
2690 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2697 output_addr_const (file
, addr
);
2698 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2699 fprintf (file
, "@GOT");
2701 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2707 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2710 output_addr_const (file
, addr
);
2711 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2712 fprintf (file
, ":w");
2713 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2714 fprintf (file
, ":l");
2716 if (addr
!= 0 && ireg
!= 0)
2721 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2723 scale
= INTVAL (XEXP (ireg
, 1));
2724 ireg
= XEXP (ireg
, 0);
2726 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2729 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2731 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2737 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2739 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2745 fprintf (file
, "*%d", scale
);
2747 fprintf (file
, ":%d", scale
);
2753 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2754 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2756 ASM_OUTPUT_CASE_FETCH (file
,
2757 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2758 reg_names
[REGNO (reg1
)]);
2759 fprintf (file
, "l)");
2762 /* FALL-THROUGH (is this really what we want? */
2764 if (GET_CODE (addr
) == CONST_INT
2765 && INTVAL (addr
) < 0x8000
2766 && INTVAL (addr
) >= -0x8000)
2770 /* Many SGS assemblers croak on size specifiers for constants. */
2771 fprintf (file
, "%d", INTVAL (addr
));
2773 fprintf (file
, "%d.w", INTVAL (addr
));
2776 fprintf (file
, "%d:w", INTVAL (addr
));
2781 output_addr_const (file
, addr
);
2787 /* Check for cases where a clr insns can be omitted from code using
2788 strict_low_part sets. For example, the second clrl here is not needed:
2789 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2791 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2792 insn we are checking for redundancy. TARGET is the register set by the
2796 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2797 enum machine_mode mode
;
2803 p
= prev_nonnote_insn (first_insn
);
2807 /* If it isn't an insn, then give up. */
2808 if (GET_CODE (p
) != INSN
)
2811 if (reg_set_p (target
, p
))
2813 rtx set
= single_set (p
);
2816 /* If it isn't an easy to recognize insn, then give up. */
2820 dest
= SET_DEST (set
);
2822 /* If this sets the entire target register to zero, then our
2823 first_insn is redundant. */
2824 if (rtx_equal_p (dest
, target
)
2825 && SET_SRC (set
) == const0_rtx
)
2827 else if (GET_CODE (dest
) == STRICT_LOW_PART
2828 && GET_CODE (XEXP (dest
, 0)) == REG
2829 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2830 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2831 <= GET_MODE_SIZE (mode
)))
2832 /* This is a strict low part set which modifies less than
2833 we are using, so it is safe. */
2839 p
= prev_nonnote_insn (p
);
2846 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2847 range carefully since this predicate is used in DImode contexts. Also, we
2848 need some extra crud to make it work when hosted on 64-bit machines. */
2851 const_uint32_operand (op
, mode
)
2853 enum machine_mode mode
;
2855 #if HOST_BITS_PER_WIDE_INT > 32
2856 /* All allowed constants will fit a CONST_INT. */
2857 return (GET_CODE (op
) == CONST_INT
2858 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
2860 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
2861 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
2865 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2866 to check the range carefully since this predicate is used in DImode
2870 const_sint32_operand (op
, mode
)
2872 enum machine_mode mode
;
2874 /* All allowed constants will fit a CONST_INT. */
2875 return (GET_CODE (op
) == CONST_INT
2876 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));