1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* These bits are controlled by all CPU selection options. Many options
205 also control MASK_68881, but some (notably -m68020) leave it alone. */
207 #define MASK_ALL_CPU_BITS \
208 (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
209 | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_68010 | MASK_BITFIELD)
211 /* Implement TARGET_HANDLE_OPTION. */
214 m68k_handle_option (size_t code
, const char *arg
, int value
)
219 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
220 target_flags
|= MASK_5200
;
224 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
225 target_flags
|= MASK_5200
| MASK_CF_HWDIV
;
229 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
230 target_flags
|= MASK_528x
| MASK_CF_HWDIV
;
234 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
235 target_flags
|= MASK_CFV3
| MASK_CF_HWDIV
;
239 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
240 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
;
244 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
245 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
| MASK_CFV4E
;
250 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
254 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
255 target_flags
|= MASK_68010
;
260 target_flags
&= ~MASK_ALL_CPU_BITS
;
261 target_flags
|= MASK_68010
| MASK_68020
| MASK_BITFIELD
;
265 target_flags
&= ~MASK_ALL_CPU_BITS
;
266 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68010
267 | MASK_68020
| MASK_68040
);
271 target_flags
&= ~MASK_ALL_CPU_BITS
;
272 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68010
273 | MASK_68020
| MASK_68040
| MASK_68060
);
277 target_flags
&= ~MASK_ALL_CPU_BITS
;
278 target_flags
|= MASK_68010
| MASK_68020
| MASK_68030
| MASK_BITFIELD
;
282 target_flags
&= ~MASK_ALL_CPU_BITS
;
283 target_flags
|= (MASK_68010
| MASK_68020
| MASK_68881
| MASK_BITFIELD
284 | MASK_68040_ONLY
| MASK_68040
);
288 target_flags
&= ~MASK_ALL_CPU_BITS
;
289 target_flags
|= (MASK_68010
| MASK_68020
| MASK_68881
| MASK_BITFIELD
290 | MASK_68040_ONLY
| MASK_68060
);
294 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
299 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
300 target_flags
|= MASK_68010
| MASK_68020
;
303 case OPT_mshared_library_id_
:
304 if (value
> MAX_LIBRARY_ID
)
305 error ("-mshared-library-id=%s is not between 0 and %d",
306 arg
, MAX_LIBRARY_ID
);
308 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
316 /* Sometimes certain combinations of command options do not make
317 sense on a particular target machine. You can define a macro
318 `OVERRIDE_OPTIONS' to take account of this. This macro, if
319 defined, is executed once just after all the command options have
322 Don't use this macro to turn on various extra optimizations for
323 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
326 override_options (void)
328 /* Sanity check to ensure that msep-data and mid-sahred-library are not
329 * both specified together. Doing so simply doesn't make sense.
331 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
332 error ("cannot specify both -msep-data and -mid-shared-library");
334 /* If we're generating code for a separate A5 relative data segment,
335 * we've got to enable -fPIC as well. This might be relaxable to
336 * -fpic but it hasn't been tested properly.
338 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
341 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
343 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
344 error ("-fPIC is not currently supported on the 68000 or 68010");
346 /* ??? A historic way of turning on pic, or is this intended to
347 be an embedded thing that doesn't have the same name binding
348 significance that it does on hosted ELF systems? */
349 if (TARGET_PCREL
&& flag_pic
== 0)
352 /* Turn off function cse if we are doing PIC. We always want function call
353 to be done as `bsr foo@PLTPC', so it will force the assembler to create
354 the PLT entry for `foo'. Doing function cse will cause the address of
355 `foo' to be loaded into a register, which is exactly what we want to
356 avoid when we are doing PIC on svr4 m68k. */
358 flag_no_function_cse
= 1;
360 SUBTARGET_OVERRIDE_OPTIONS
;
363 /* Return nonzero if FUNC is an interrupt function as specified by the
364 "interrupt_handler" attribute. */
366 m68k_interrupt_function_p(tree func
)
370 if (TREE_CODE (func
) != FUNCTION_DECL
)
373 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
374 return (a
!= NULL_TREE
);
377 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
378 struct attribute_spec.handler. */
380 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
381 tree args ATTRIBUTE_UNUSED
,
382 int flags ATTRIBUTE_UNUSED
,
385 if (TREE_CODE (*node
) != FUNCTION_DECL
)
387 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
388 IDENTIFIER_POINTER (name
));
389 *no_add_attrs
= true;
396 m68k_compute_frame_layout (void)
399 unsigned int mask
, rmask
;
400 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
402 /* Only compute the frame once per function.
403 Don't cache information until reload has been completed. */
404 if (current_frame
.funcdef_no
== current_function_funcdef_no
408 current_frame
.size
= (get_frame_size () + 3) & -4;
410 mask
= rmask
= saved
= 0;
411 for (regno
= 0; regno
< 16; regno
++)
412 if (m68k_save_reg (regno
, interrupt_handler
))
415 rmask
|= 1 << (15 - regno
);
418 current_frame
.offset
= saved
* 4;
419 current_frame
.reg_no
= saved
;
420 current_frame
.reg_mask
= mask
;
421 current_frame
.reg_rev_mask
= rmask
;
423 current_frame
.foffset
= 0;
424 mask
= rmask
= saved
= 0;
425 if (TARGET_HARD_FLOAT
)
427 for (regno
= 16; regno
< 24; regno
++)
428 if (m68k_save_reg (regno
, interrupt_handler
))
430 mask
|= 1 << (regno
- 16);
431 rmask
|= 1 << (23 - regno
);
434 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
435 current_frame
.offset
+= current_frame
.foffset
;
437 current_frame
.fpu_no
= saved
;
438 current_frame
.fpu_mask
= mask
;
439 current_frame
.fpu_rev_mask
= rmask
;
441 /* Remember what function this frame refers to. */
442 current_frame
.funcdef_no
= current_function_funcdef_no
;
446 m68k_initial_elimination_offset (int from
, int to
)
449 /* The arg pointer points 8 bytes before the start of the arguments,
450 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
451 frame pointer in most frames. */
452 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
453 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
454 return argptr_offset
;
456 m68k_compute_frame_layout ();
458 gcc_assert (to
== STACK_POINTER_REGNUM
);
461 case ARG_POINTER_REGNUM
:
462 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
463 case FRAME_POINTER_REGNUM
:
464 return current_frame
.offset
+ current_frame
.size
;
470 /* Refer to the array `regs_ever_live' to determine which registers
471 to save; `regs_ever_live[I]' is nonzero if register number I
472 is ever used in the function. This function is responsible for
473 knowing which registers should not be saved even if used.
474 Return true if we need to save REGNO. */
477 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
479 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
481 if (current_function_uses_pic_offset_table
)
483 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
487 if (current_function_calls_eh_return
)
492 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
493 if (test
== INVALID_REGNUM
)
500 /* Fixed regs we never touch. */
501 if (fixed_regs
[regno
])
504 /* The frame pointer (if it is such) is handled specially. */
505 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
508 /* Interrupt handlers must also save call_used_regs
509 if they are live or when calling nested functions. */
510 if (interrupt_handler
)
512 if (regs_ever_live
[regno
])
515 if (!current_function_is_leaf
&& call_used_regs
[regno
])
519 /* Never need to save registers that aren't touched. */
520 if (!regs_ever_live
[regno
])
523 /* Otherwise save everything that isn't call-clobbered. */
524 return !call_used_regs
[regno
];
527 /* This function generates the assembly code for function entry.
528 STREAM is a stdio stream to output the code to.
529 SIZE is an int: how many units of temporary storage to allocate. */
532 m68k_output_function_prologue (FILE *stream
,
533 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
535 HOST_WIDE_INT fsize_with_regs
;
536 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
538 m68k_compute_frame_layout();
540 /* If the stack limit is a symbol, we can check it here,
541 before actually allocating the space. */
542 if (current_function_limit_stack
543 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
544 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
545 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
547 /* On ColdFire add register save into initial stack frame setup, if possible. */
548 fsize_with_regs
= current_frame
.size
;
551 if (current_frame
.reg_no
> 2)
552 fsize_with_regs
+= current_frame
.reg_no
* 4;
553 if (current_frame
.fpu_no
)
554 fsize_with_regs
+= current_frame
.fpu_no
* 8;
557 if (frame_pointer_needed
)
559 if (current_frame
.size
== 0 && TUNE_68040
)
560 /* on the 68040, pea + move is faster than link.w 0 */
561 fprintf (stream
, (MOTOROLA
562 ? "\tpea (%s)\n\tmove.l %s,%s\n"
563 : "\tpea %s@\n\tmovel %s,%s\n"),
564 M68K_REGNAME (FRAME_POINTER_REGNUM
),
565 M68K_REGNAME (STACK_POINTER_REGNUM
),
566 M68K_REGNAME (FRAME_POINTER_REGNUM
));
567 else if (fsize_with_regs
< 0x8000)
568 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
569 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
570 else if (TARGET_68020
)
571 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
572 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
574 /* Adding negative number is faster on the 68040. */
576 "\tlink" ASM_DOTW
" %s,%I0\n"
577 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
578 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
580 else if (fsize_with_regs
) /* !frame_pointer_needed */
582 if (fsize_with_regs
< 0x8000)
584 if (fsize_with_regs
<= 8)
586 if (!TARGET_COLDFIRE
)
587 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
590 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
593 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
594 /* On the CPU32 it is faster to use two subqw instructions to
595 subtract a small integer (8 < N <= 16) to a register. */
597 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
598 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
599 fsize_with_regs
- 8);
601 /* Adding negative number is faster on the 68040. */
602 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
605 asm_fprintf (stream
, (MOTOROLA
606 ? "\tlea (%wd,%Rsp),%Rsp\n"
607 : "\tlea %Rsp@(%wd),%Rsp\n"),
610 else /* fsize_with_regs >= 0x8000 */
611 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
613 } /* !frame_pointer_needed */
615 if (dwarf2out_do_frame ())
617 if (frame_pointer_needed
)
620 l
= (char *) dwarf2out_cfi_label ();
622 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
623 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
624 cfa_offset
+= current_frame
.size
;
628 cfa_offset
+= current_frame
.size
;
629 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
633 if (current_frame
.fpu_mask
)
637 asm_fprintf (stream
, (MOTOROLA
638 ? "\tfmovm %I0x%x,-(%Rsp)\n"
639 : "\tfmovem %I0x%x,%Rsp@-\n"),
640 current_frame
.fpu_mask
);
646 /* stack already has registers in it. Find the offset from
647 the bottom of stack to where the FP registers go */
648 if (current_frame
.reg_no
<= 2)
651 offset
= current_frame
.reg_no
* 4;
654 "\tfmovem %I0x%x,%d(%Rsp)\n",
655 current_frame
.fpu_rev_mask
,
659 "\tfmovem %I0x%x,(%Rsp)\n",
660 current_frame
.fpu_rev_mask
);
663 if (dwarf2out_do_frame ())
665 char *l
= (char *) dwarf2out_cfi_label ();
668 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
669 if (! frame_pointer_needed
)
670 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
671 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
672 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
673 dwarf2out_reg_save (l
, regno
, -cfa_offset
674 + n_regs
++ * TARGET_FP_REG_SIZE
);
678 /* If the stack limit is not a symbol, check it here.
679 This has the disadvantage that it may be too late... */
680 if (current_function_limit_stack
)
682 if (REG_P (stack_limit_rtx
))
683 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
684 M68K_REGNAME (REGNO (stack_limit_rtx
)));
685 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
686 warning (0, "stack limit expression is not supported");
689 if (current_frame
.reg_no
<= 2)
691 /* Store each separately in the same order moveml uses.
692 Using two movel instructions instead of a single moveml
693 is about 15% faster for the 68020 and 68030 at no expense
698 for (i
= 0; i
< 16; i
++)
699 if (current_frame
.reg_rev_mask
& (1 << i
))
701 asm_fprintf (stream
, (MOTOROLA
702 ? "\t%Omove.l %s,-(%Rsp)\n"
703 : "\tmovel %s,%Rsp@-\n"),
704 M68K_REGNAME (15 - i
));
705 if (dwarf2out_do_frame ())
707 char *l
= (char *) dwarf2out_cfi_label ();
710 if (! frame_pointer_needed
)
711 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
712 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
716 else if (current_frame
.reg_rev_mask
)
719 /* The ColdFire does not support the predecrement form of the
720 MOVEM instruction, so we must adjust the stack pointer and
721 then use the plain address register indirect mode.
722 The required register save space was combined earlier with
723 the fsize_with_regs amount. */
725 asm_fprintf (stream
, (MOTOROLA
726 ? "\tmovm.l %I0x%x,(%Rsp)\n"
727 : "\tmoveml %I0x%x,%Rsp@\n"),
728 current_frame
.reg_mask
);
730 asm_fprintf (stream
, (MOTOROLA
731 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
732 : "\tmoveml %I0x%x,%Rsp@-\n"),
733 current_frame
.reg_rev_mask
);
734 if (dwarf2out_do_frame ())
736 char *l
= (char *) dwarf2out_cfi_label ();
739 cfa_offset
+= current_frame
.reg_no
* 4;
740 if (! frame_pointer_needed
)
741 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
742 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
743 if (current_frame
.reg_mask
& (1 << regno
))
744 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
747 if (!TARGET_SEP_DATA
&& flag_pic
748 && (current_function_uses_pic_offset_table
749 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
751 if (TARGET_ID_SHARED_LIBRARY
)
753 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
754 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
755 m68k_library_id_string
,
756 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
762 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
763 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
766 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
767 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
768 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
769 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
770 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
776 /* Return true if this function's epilogue can be output as RTL. */
779 use_return_insn (void)
781 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
784 /* We can output the epilogue as RTL only if no registers need to be
786 m68k_compute_frame_layout ();
787 return current_frame
.reg_no
? false : true;
790 /* This function generates the assembly code for function exit,
791 on machines that need it.
793 The function epilogue should not depend on the current stack pointer!
794 It should use the frame pointer only, if there is a frame pointer.
795 This is mandatory because of alloca; we also take advantage of it to
796 omit stack adjustments before returning. */
799 m68k_output_function_epilogue (FILE *stream
,
800 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
802 HOST_WIDE_INT fsize
, fsize_with_regs
;
804 bool restore_from_sp
= false;
805 rtx insn
= get_last_insn ();
807 m68k_compute_frame_layout ();
809 /* If the last insn was a BARRIER, we don't have to write any code. */
810 if (GET_CODE (insn
) == NOTE
)
811 insn
= prev_nonnote_insn (insn
);
812 if (insn
&& GET_CODE (insn
) == BARRIER
)
814 /* Output just a no-op so that debuggers don't get confused
815 about which function the pc is in at this address. */
816 fprintf (stream
, "\tnop\n");
820 #ifdef FUNCTION_EXTRA_EPILOGUE
821 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
824 fsize
= current_frame
.size
;
826 /* FIXME: leaf_function_p below is too strong.
827 What we really need to know there is if there could be pending
828 stack adjustment needed at that point. */
830 = (! frame_pointer_needed
831 || (! current_function_calls_alloca
&& leaf_function_p ()));
833 /* fsize_with_regs is the size we need to adjust the sp when
834 popping the frame. */
835 fsize_with_regs
= fsize
;
837 /* Because the ColdFire doesn't support moveml with
838 complex address modes, we must adjust the stack manually
839 after restoring registers. When the frame pointer isn't used,
840 we can merge movem adjustment into frame unlinking
841 made immediately after it. */
842 if (TARGET_COLDFIRE
&& restore_from_sp
)
844 if (current_frame
.reg_no
> 2)
845 fsize_with_regs
+= current_frame
.reg_no
* 4;
846 if (current_frame
.fpu_no
)
847 fsize_with_regs
+= current_frame
.fpu_no
* 8;
850 if (current_frame
.offset
+ fsize
>= 0x8000
852 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
854 /* Because the ColdFire doesn't support moveml with
855 complex address modes we make an extra correction here. */
857 fsize
+= current_frame
.offset
;
859 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
860 fsize
= 0, big
= true;
862 if (current_frame
.reg_no
<= 2)
864 /* Restore each separately in the same order moveml does.
865 Using two movel instructions instead of a single moveml
866 is about 15% faster for the 68020 and 68030 at no expense
870 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
872 for (i
= 0; i
< 16; i
++)
873 if (current_frame
.reg_mask
& (1 << i
))
878 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
880 M68K_REGNAME (FRAME_POINTER_REGNUM
),
883 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
884 M68K_REGNAME (FRAME_POINTER_REGNUM
),
888 else if (restore_from_sp
)
889 asm_fprintf (stream
, (MOTOROLA
890 ? "\t%Omove.l (%Rsp)+,%s\n"
891 : "\tmovel %Rsp@+,%s\n"),
896 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
898 M68K_REGNAME (FRAME_POINTER_REGNUM
),
901 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
902 M68K_REGNAME (FRAME_POINTER_REGNUM
),
909 else if (current_frame
.reg_mask
)
911 /* The ColdFire requires special handling due to its limited moveml
917 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
918 M68K_REGNAME (FRAME_POINTER_REGNUM
));
919 asm_fprintf (stream
, (MOTOROLA
920 ? "\tmovm.l (%Ra1),%I0x%x\n"
921 : "\tmoveml %Ra1@,%I0x%x\n"),
922 current_frame
.reg_mask
);
924 else if (restore_from_sp
)
925 asm_fprintf (stream
, (MOTOROLA
926 ? "\tmovm.l (%Rsp),%I0x%x\n"
927 : "\tmoveml %Rsp@,%I0x%x\n"),
928 current_frame
.reg_mask
);
932 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
933 current_frame
.offset
+ fsize
,
934 M68K_REGNAME (FRAME_POINTER_REGNUM
),
935 current_frame
.reg_mask
);
937 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
938 M68K_REGNAME (FRAME_POINTER_REGNUM
),
939 current_frame
.offset
+ fsize
,
940 current_frame
.reg_mask
);
943 else /* !TARGET_COLDFIRE */
948 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
949 current_frame
.offset
+ fsize
,
950 M68K_REGNAME (FRAME_POINTER_REGNUM
),
951 current_frame
.reg_mask
);
953 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
954 M68K_REGNAME (FRAME_POINTER_REGNUM
),
955 current_frame
.offset
+ fsize
,
956 current_frame
.reg_mask
);
958 else if (restore_from_sp
)
960 asm_fprintf (stream
, (MOTOROLA
961 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
962 : "\tmoveml %Rsp@+,%I0x%x\n"),
963 current_frame
.reg_mask
);
968 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
969 current_frame
.offset
+ fsize
,
970 M68K_REGNAME (FRAME_POINTER_REGNUM
),
971 current_frame
.reg_mask
);
973 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
974 M68K_REGNAME (FRAME_POINTER_REGNUM
),
975 current_frame
.offset
+ fsize
,
976 current_frame
.reg_mask
);
980 if (current_frame
.fpu_rev_mask
)
986 if (current_frame
.reg_no
)
987 asm_fprintf (stream
, MOTOROLA
?
988 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
989 "\tfmovmd (%d,%Ra1),%I0x%x\n",
990 current_frame
.reg_no
* 4,
991 current_frame
.fpu_rev_mask
);
993 asm_fprintf (stream
, MOTOROLA
?
994 "\tfmovem.d (%Ra1),%I0x%x\n" :
995 "\tfmovmd (%Ra1),%I0x%x\n",
996 current_frame
.fpu_rev_mask
);
999 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1000 current_frame
.foffset
+ fsize
,
1001 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1002 current_frame
.fpu_rev_mask
);
1004 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1005 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1006 current_frame
.foffset
+ fsize
,
1007 current_frame
.fpu_rev_mask
);
1009 else if (restore_from_sp
)
1011 if (TARGET_COLDFIRE
)
1015 /* Stack already has registers in it. Find the offset from
1016 the bottom of stack to where the FP registers go. */
1017 if (current_frame
.reg_no
<= 2)
1020 offset
= current_frame
.reg_no
* 4;
1022 asm_fprintf (stream
,
1023 "\tfmovem %Rsp@(%d), %I0x%x\n",
1024 offset
, current_frame
.fpu_rev_mask
);
1026 asm_fprintf (stream
,
1027 "\tfmovem %Rsp@, %I0x%x\n",
1028 current_frame
.fpu_rev_mask
);
1031 asm_fprintf (stream
, MOTOROLA
?
1032 "\tfmovm (%Rsp)+,%I0x%x\n" :
1033 "\tfmovem %Rsp@+,%I0x%x\n",
1034 current_frame
.fpu_rev_mask
);
1038 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1039 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1040 current_frame
.foffset
+ fsize
,
1041 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1042 current_frame
.fpu_rev_mask
);
1044 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1045 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1046 current_frame
.foffset
+ fsize
,
1047 current_frame
.fpu_rev_mask
);
1050 if (frame_pointer_needed
)
1051 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1052 else if (fsize_with_regs
)
1054 if (fsize_with_regs
<= 8)
1056 if (!TARGET_COLDFIRE
)
1057 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1060 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1063 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1065 /* On the CPU32 it is faster to use two addqw instructions to
1066 add a small integer (8 < N <= 16) to a register. */
1067 asm_fprintf (stream
,
1068 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1069 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1070 fsize_with_regs
- 8);
1072 else if (fsize_with_regs
< 0x8000)
1075 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1078 asm_fprintf (stream
, (MOTOROLA
1079 ? "\tlea (%wd,%Rsp),%Rsp\n"
1080 : "\tlea %Rsp@(%wd),%Rsp\n"),
1084 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1086 if (current_function_calls_eh_return
)
1087 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1088 if (m68k_interrupt_function_p (current_function_decl
))
1089 fprintf (stream
, "\trte\n");
1090 else if (current_function_pops_args
)
1091 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1093 fprintf (stream
, "\trts\n");
1096 /* Return true if X is a valid comparison operator for the dbcc
1099 Note it rejects floating point comparison operators.
1100 (In the future we could use Fdbcc).
1102 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1105 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1107 switch (GET_CODE (x
))
1109 case EQ
: case NE
: case GTU
: case LTU
:
1113 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1115 case GT
: case LT
: case GE
: case LE
:
1116 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1122 /* Return nonzero if flags are currently in the 68881 flag register. */
1124 flags_in_68881 (void)
1126 /* We could add support for these in the future */
1127 return cc_status
.flags
& CC_IN_68881
;
1130 /* Output a BSR instruction suitable for PIC code. */
1132 m68k_output_pic_call (rtx dest
)
1136 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1138 /* We output a BSR instruction if we're building for a target that
1139 supports long branches. Otherwise we generate one of two sequences:
1140 a shorter one that uses a GOT entry or a longer one that doesn't.
1141 We'll use the -Os command-line flag to decide which to generate.
1142 Both sequences take the same time to execute on the ColdFire. */
1143 else if (TARGET_PCREL
)
1145 else if (TARGET_68020
)
1146 #if defined(USE_GAS)
1147 out
= "bsr.l %0@PLTPC";
1149 out
= "bsr %0@PLTPC";
1151 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1152 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1154 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1156 output_asm_insn (out
, &dest
);
1159 /* Output a dbCC; jCC sequence. Note we do not handle the
1160 floating point version of this sequence (Fdbcc). We also
1161 do not handle alternative conditions when CC_NO_OVERFLOW is
1162 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1163 kick those out before we get here. */
1166 output_dbcc_and_branch (rtx
*operands
)
1168 switch (GET_CODE (operands
[3]))
1171 output_asm_insn (MOTOROLA
1172 ? "dbeq %0,%l1\n\tjbeq %l2"
1173 : "dbeq %0,%l1\n\tjeq %l2",
1178 output_asm_insn (MOTOROLA
1179 ? "dbne %0,%l1\n\tjbne %l2"
1180 : "dbne %0,%l1\n\tjne %l2",
1185 output_asm_insn (MOTOROLA
1186 ? "dbgt %0,%l1\n\tjbgt %l2"
1187 : "dbgt %0,%l1\n\tjgt %l2",
1192 output_asm_insn (MOTOROLA
1193 ? "dbhi %0,%l1\n\tjbhi %l2"
1194 : "dbhi %0,%l1\n\tjhi %l2",
1199 output_asm_insn (MOTOROLA
1200 ? "dblt %0,%l1\n\tjblt %l2"
1201 : "dblt %0,%l1\n\tjlt %l2",
1206 output_asm_insn (MOTOROLA
1207 ? "dbcs %0,%l1\n\tjbcs %l2"
1208 : "dbcs %0,%l1\n\tjcs %l2",
1213 output_asm_insn (MOTOROLA
1214 ? "dbge %0,%l1\n\tjbge %l2"
1215 : "dbge %0,%l1\n\tjge %l2",
1220 output_asm_insn (MOTOROLA
1221 ? "dbcc %0,%l1\n\tjbcc %l2"
1222 : "dbcc %0,%l1\n\tjcc %l2",
1227 output_asm_insn (MOTOROLA
1228 ? "dble %0,%l1\n\tjble %l2"
1229 : "dble %0,%l1\n\tjle %l2",
1234 output_asm_insn (MOTOROLA
1235 ? "dbls %0,%l1\n\tjbls %l2"
1236 : "dbls %0,%l1\n\tjls %l2",
1244 /* If the decrement is to be done in SImode, then we have
1245 to compensate for the fact that dbcc decrements in HImode. */
1246 switch (GET_MODE (operands
[0]))
1249 output_asm_insn (MOTOROLA
1250 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1251 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1264 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1267 enum rtx_code op_code
= GET_CODE (op
);
1269 /* This does not produce a useful cc. */
1272 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1273 below. Swap the operands and change the op if these requirements
1274 are not fulfilled. */
1275 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1279 operand1
= operand2
;
1281 op_code
= swap_condition (op_code
);
1283 loperands
[0] = operand1
;
1284 if (GET_CODE (operand1
) == REG
)
1285 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1287 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1288 if (operand2
!= const0_rtx
)
1290 loperands
[2] = operand2
;
1291 if (GET_CODE (operand2
) == REG
)
1292 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1294 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1296 loperands
[4] = gen_label_rtx ();
1297 if (operand2
!= const0_rtx
)
1299 output_asm_insn (MOTOROLA
1300 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1301 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1306 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1307 output_asm_insn ("tst%.l %0", loperands
);
1309 output_asm_insn ("cmp%.w #0,%0", loperands
);
1311 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1313 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1314 output_asm_insn ("tst%.l %1", loperands
);
1316 output_asm_insn ("cmp%.w #0,%1", loperands
);
1319 loperands
[5] = dest
;
1324 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1325 CODE_LABEL_NUMBER (loperands
[4]));
1326 output_asm_insn ("seq %5", loperands
);
1330 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1331 CODE_LABEL_NUMBER (loperands
[4]));
1332 output_asm_insn ("sne %5", loperands
);
1336 loperands
[6] = gen_label_rtx ();
1337 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1339 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1340 CODE_LABEL_NUMBER (loperands
[4]));
1341 output_asm_insn ("sgt %5", loperands
);
1342 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1343 CODE_LABEL_NUMBER (loperands
[6]));
1347 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1348 CODE_LABEL_NUMBER (loperands
[4]));
1349 output_asm_insn ("shi %5", loperands
);
1353 loperands
[6] = gen_label_rtx ();
1354 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1356 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1357 CODE_LABEL_NUMBER (loperands
[4]));
1358 output_asm_insn ("slt %5", loperands
);
1359 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1360 CODE_LABEL_NUMBER (loperands
[6]));
1364 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1365 CODE_LABEL_NUMBER (loperands
[4]));
1366 output_asm_insn ("scs %5", loperands
);
1370 loperands
[6] = gen_label_rtx ();
1371 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1373 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1374 CODE_LABEL_NUMBER (loperands
[4]));
1375 output_asm_insn ("sge %5", loperands
);
1376 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1377 CODE_LABEL_NUMBER (loperands
[6]));
1381 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1382 CODE_LABEL_NUMBER (loperands
[4]));
1383 output_asm_insn ("scc %5", loperands
);
1387 loperands
[6] = gen_label_rtx ();
1388 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1390 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1391 CODE_LABEL_NUMBER (loperands
[4]));
1392 output_asm_insn ("sle %5", loperands
);
1393 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1394 CODE_LABEL_NUMBER (loperands
[6]));
1398 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1399 CODE_LABEL_NUMBER (loperands
[4]));
1400 output_asm_insn ("sls %5", loperands
);
1410 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1412 operands
[0] = countop
;
1413 operands
[1] = dataop
;
1415 if (GET_CODE (countop
) == CONST_INT
)
1417 register int count
= INTVAL (countop
);
1418 /* If COUNT is bigger than size of storage unit in use,
1419 advance to the containing unit of same size. */
1420 if (count
> signpos
)
1422 int offset
= (count
& ~signpos
) / 8;
1423 count
= count
& signpos
;
1424 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1426 if (count
== signpos
)
1427 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1429 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1431 /* These three statements used to use next_insns_test_no...
1432 but it appears that this should do the same job. */
1434 && next_insn_tests_no_inequality (insn
))
1437 && next_insn_tests_no_inequality (insn
))
1440 && next_insn_tests_no_inequality (insn
))
1443 cc_status
.flags
= CC_NOT_NEGATIVE
;
1445 return "btst %0,%1";
1448 /* Legitimize PIC addresses. If the address is already
1449 position-independent, we return ORIG. Newly generated
1450 position-independent addresses go to REG. If we need more
1451 than one register, we lose.
1453 An address is legitimized by making an indirect reference
1454 through the Global Offset Table with the name of the symbol
1457 The assembler and linker are responsible for placing the
1458 address of the symbol in the GOT. The function prologue
1459 is responsible for initializing a5 to the starting address
1462 The assembler is also responsible for translating a symbol name
1463 into a constant displacement from the start of the GOT.
1465 A quick example may make things a little clearer:
1467 When not generating PIC code to store the value 12345 into _foo
1468 we would generate the following code:
1472 When generating PIC two transformations are made. First, the compiler
1473 loads the address of foo into a register. So the first transformation makes:
1478 The code in movsi will intercept the lea instruction and call this
1479 routine which will transform the instructions into:
1481 movel a5@(_foo:w), a0
1485 That (in a nutshell) is how *all* symbol and label references are
1489 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1494 /* First handle a simple SYMBOL_REF or LABEL_REF */
1495 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1499 pic_ref
= gen_rtx_MEM (Pmode
,
1500 gen_rtx_PLUS (Pmode
,
1501 pic_offset_table_rtx
, orig
));
1502 current_function_uses_pic_offset_table
= 1;
1503 MEM_READONLY_P (pic_ref
) = 1;
1504 emit_move_insn (reg
, pic_ref
);
1507 else if (GET_CODE (orig
) == CONST
)
1511 /* Make sure this has not already been legitimized. */
1512 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1513 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1518 /* legitimize both operands of the PLUS */
1519 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1521 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1522 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1523 base
== reg
? 0 : reg
);
1525 if (GET_CODE (orig
) == CONST_INT
)
1526 return plus_constant (base
, INTVAL (orig
));
1527 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1528 /* Likewise, should we set special REG_NOTEs here? */
1534 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1536 static CONST_METHOD
const_method (rtx
);
1538 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1541 const_method (rtx constant
)
1546 i
= INTVAL (constant
);
1550 /* The ColdFire doesn't have byte or word operations. */
1551 /* FIXME: This may not be useful for the m68060 either. */
1552 if (!TARGET_COLDFIRE
)
1554 /* if -256 < N < 256 but N is not in range for a moveq
1555 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1556 if (USE_MOVQ (i
^ 0xff))
1558 /* Likewise, try with not.w */
1559 if (USE_MOVQ (i
^ 0xffff))
1561 /* This is the only value where neg.w is useful */
1566 /* Try also with swap. */
1568 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1573 /* Try using MVZ/MVS with an immediate value to load constants. */
1574 if (i
>= 0 && i
<= 65535)
1576 if (i
>= -32768 && i
<= 32767)
1580 /* Otherwise, use move.l */
1585 const_int_cost (rtx constant
)
1587 switch (const_method (constant
))
1590 /* Constants between -128 and 127 are cheap due to moveq. */
1598 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1608 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1613 /* Constant zero is super cheap due to clr instruction. */
1614 if (x
== const0_rtx
)
1617 *total
= const_int_cost (x
);
1627 /* Make 0.0 cheaper than other floating constants to
1628 encourage creating tstsf and tstdf insns. */
1629 if (outer_code
== COMPARE
1630 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1636 /* These are vaguely right for a 68020. */
1637 /* The costs for long multiply have been adjusted to work properly
1638 in synth_mult on the 68020, relative to an average of the time
1639 for add and the time for shift, taking away a little more because
1640 sometimes move insns are needed. */
1641 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1647 : TARGET_COLDFIRE ? 3 : 13)
1652 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1653 : TARGET_COLDFIRE ? 2 : 8)
1656 (TARGET_CF_HWDIV ? 11 \
1657 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1660 /* An lea costs about three times as much as a simple add. */
1661 if (GET_MODE (x
) == SImode
1662 && GET_CODE (XEXP (x
, 1)) == REG
1663 && GET_CODE (XEXP (x
, 0)) == MULT
1664 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1665 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1666 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1667 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1668 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1670 /* lea an@(dx:l:i),am */
1671 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1681 *total
= COSTS_N_INSNS(1);
1686 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1688 if (INTVAL (XEXP (x
, 1)) < 16)
1689 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1691 /* We're using clrw + swap for these cases. */
1692 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1695 *total
= COSTS_N_INSNS (10); /* Worst case. */
1698 /* A shift by a big integer takes an extra instruction. */
1699 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1700 && (INTVAL (XEXP (x
, 1)) == 16))
1702 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1705 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1706 && !(INTVAL (XEXP (x
, 1)) > 0
1707 && INTVAL (XEXP (x
, 1)) <= 8))
1709 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1715 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1716 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1717 && GET_MODE (x
) == SImode
)
1718 *total
= COSTS_N_INSNS (MULW_COST
);
1719 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1720 *total
= COSTS_N_INSNS (MULW_COST
);
1722 *total
= COSTS_N_INSNS (MULL_COST
);
1729 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1730 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1731 else if (TARGET_CF_HWDIV
)
1732 *total
= COSTS_N_INSNS (18);
1734 *total
= COSTS_N_INSNS (43); /* div.l */
1743 output_move_const_into_data_reg (rtx
*operands
)
1747 i
= INTVAL (operands
[1]);
1748 switch (const_method (operands
[1]))
1751 return "mvzw %1,%0";
1753 return "mvsw %1,%0";
1755 return "moveq %1,%0";
1758 operands
[1] = GEN_INT (i
^ 0xff);
1759 return "moveq %1,%0\n\tnot%.b %0";
1762 operands
[1] = GEN_INT (i
^ 0xffff);
1763 return "moveq %1,%0\n\tnot%.w %0";
1766 return "moveq #-128,%0\n\tneg%.w %0";
1771 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1772 return "moveq %1,%0\n\tswap %0";
1775 return "move%.l %1,%0";
1781 /* Return 1 if 'constant' can be represented by
1782 mov3q on a ColdFire V4 core. */
1784 valid_mov3q_const (rtx constant
)
1788 if (TARGET_ISAB
&& GET_CODE (constant
) == CONST_INT
)
1790 i
= INTVAL (constant
);
1791 if (i
== -1 || (i
>= 1 && i
<= 7))
1799 output_move_simode_const (rtx
*operands
)
1801 if (operands
[1] == const0_rtx
1802 && (DATA_REG_P (operands
[0])
1803 || GET_CODE (operands
[0]) == MEM
)
1804 /* clr insns on 68000 read before writing. */
1805 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1806 || !(GET_CODE (operands
[0]) == MEM
1807 && MEM_VOLATILE_P (operands
[0]))))
1809 else if ((GET_MODE (operands
[0]) == SImode
)
1810 && valid_mov3q_const (operands
[1]))
1811 return "mov3q%.l %1,%0";
1812 else if (operands
[1] == const0_rtx
1813 && ADDRESS_REG_P (operands
[0]))
1814 return "sub%.l %0,%0";
1815 else if (DATA_REG_P (operands
[0]))
1816 return output_move_const_into_data_reg (operands
);
1817 else if (ADDRESS_REG_P (operands
[0])
1818 && INTVAL (operands
[1]) < 0x8000
1819 && INTVAL (operands
[1]) >= -0x8000)
1821 if (valid_mov3q_const (operands
[1]))
1822 return "mov3q%.l %1,%0";
1823 return "move%.w %1,%0";
1825 else if (GET_CODE (operands
[0]) == MEM
1826 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1827 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1828 && INTVAL (operands
[1]) < 0x8000
1829 && INTVAL (operands
[1]) >= -0x8000)
1831 if (valid_mov3q_const (operands
[1]))
1832 return "mov3q%.l %1,%-";
1835 return "move%.l %1,%0";
1839 output_move_simode (rtx
*operands
)
1841 if (GET_CODE (operands
[1]) == CONST_INT
)
1842 return output_move_simode_const (operands
);
1843 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1844 || GET_CODE (operands
[1]) == CONST
)
1845 && push_operand (operands
[0], SImode
))
1847 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1848 || GET_CODE (operands
[1]) == CONST
)
1849 && ADDRESS_REG_P (operands
[0]))
1850 return "lea %a1,%0";
1851 return "move%.l %1,%0";
1855 output_move_himode (rtx
*operands
)
1857 if (GET_CODE (operands
[1]) == CONST_INT
)
1859 if (operands
[1] == const0_rtx
1860 && (DATA_REG_P (operands
[0])
1861 || GET_CODE (operands
[0]) == MEM
)
1862 /* clr insns on 68000 read before writing. */
1863 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1864 || !(GET_CODE (operands
[0]) == MEM
1865 && MEM_VOLATILE_P (operands
[0]))))
1867 else if (operands
[1] == const0_rtx
1868 && ADDRESS_REG_P (operands
[0]))
1869 return "sub%.l %0,%0";
1870 else if (DATA_REG_P (operands
[0])
1871 && INTVAL (operands
[1]) < 128
1872 && INTVAL (operands
[1]) >= -128)
1873 return "moveq %1,%0";
1874 else if (INTVAL (operands
[1]) < 0x8000
1875 && INTVAL (operands
[1]) >= -0x8000)
1876 return "move%.w %1,%0";
1878 else if (CONSTANT_P (operands
[1]))
1879 return "move%.l %1,%0";
1880 /* Recognize the insn before a tablejump, one that refers
1881 to a table of offsets. Such an insn will need to refer
1882 to a label on the insn. So output one. Use the label-number
1883 of the table of offsets to generate this label. This code,
1884 and similar code below, assumes that there will be at most one
1885 reference to each table. */
1886 if (GET_CODE (operands
[1]) == MEM
1887 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1888 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1889 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1891 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1893 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1894 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1896 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1897 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1899 return "move%.w %1,%0";
1903 output_move_qimode (rtx
*operands
)
1905 /* 68k family always modifies the stack pointer by at least 2, even for
1906 byte pushes. The 5200 (ColdFire) does not do this. */
1908 /* This case is generated by pushqi1 pattern now. */
1909 gcc_assert (!(GET_CODE (operands
[0]) == MEM
1910 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1911 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1912 && ! ADDRESS_REG_P (operands
[1])
1913 && ! TARGET_COLDFIRE
));
1915 /* clr and st insns on 68000 read before writing. */
1916 if (!ADDRESS_REG_P (operands
[0])
1917 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1918 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1920 if (operands
[1] == const0_rtx
)
1922 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1923 && GET_CODE (operands
[1]) == CONST_INT
1924 && (INTVAL (operands
[1]) & 255) == 255)
1930 if (GET_CODE (operands
[1]) == CONST_INT
1931 && DATA_REG_P (operands
[0])
1932 && INTVAL (operands
[1]) < 128
1933 && INTVAL (operands
[1]) >= -128)
1934 return "moveq %1,%0";
1935 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1936 return "sub%.l %0,%0";
1937 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1938 return "move%.l %1,%0";
1939 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1940 from address registers. */
1941 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1942 return "move%.w %1,%0";
1943 return "move%.b %1,%0";
1947 output_move_stricthi (rtx
*operands
)
1949 if (operands
[1] == const0_rtx
1950 /* clr insns on 68000 read before writing. */
1951 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1952 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1954 return "move%.w %1,%0";
1958 output_move_strictqi (rtx
*operands
)
1960 if (operands
[1] == const0_rtx
1961 /* clr insns on 68000 read before writing. */
1962 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1963 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1965 return "move%.b %1,%0";
1968 /* Return the best assembler insn template
1969 for moving operands[1] into operands[0] as a fullword. */
1972 singlemove_string (rtx
*operands
)
1974 if (GET_CODE (operands
[1]) == CONST_INT
)
1975 return output_move_simode_const (operands
);
1976 return "move%.l %1,%0";
1980 /* Output assembler code to perform a doubleword move insn
1981 with operands OPERANDS. */
1984 output_move_double (rtx
*operands
)
1988 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1993 rtx addreg0
= 0, addreg1
= 0;
1994 int dest_overlapped_low
= 0;
1995 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2000 /* First classify both operands. */
2002 if (REG_P (operands
[0]))
2004 else if (offsettable_memref_p (operands
[0]))
2006 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2008 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2010 else if (GET_CODE (operands
[0]) == MEM
)
2015 if (REG_P (operands
[1]))
2017 else if (CONSTANT_P (operands
[1]))
2019 else if (offsettable_memref_p (operands
[1]))
2021 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2023 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2025 else if (GET_CODE (operands
[1]) == MEM
)
2030 /* Check for the cases that the operand constraints are not supposed
2031 to allow to happen. Generating code for these cases is
2033 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2035 /* If one operand is decrementing and one is incrementing
2036 decrement the former register explicitly
2037 and change that operand into ordinary indexing. */
2039 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2041 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2043 output_asm_insn ("sub%.l #12,%0", operands
);
2045 output_asm_insn ("subq%.l #8,%0", operands
);
2046 if (GET_MODE (operands
[1]) == XFmode
)
2047 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2048 else if (GET_MODE (operands
[0]) == DFmode
)
2049 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2051 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2054 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2056 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2058 output_asm_insn ("sub%.l #12,%1", operands
);
2060 output_asm_insn ("subq%.l #8,%1", operands
);
2061 if (GET_MODE (operands
[1]) == XFmode
)
2062 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2063 else if (GET_MODE (operands
[1]) == DFmode
)
2064 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2066 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2070 /* If an operand is an unoffsettable memory ref, find a register
2071 we can increment temporarily to make it refer to the second word. */
2073 if (optype0
== MEMOP
)
2074 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2076 if (optype1
== MEMOP
)
2077 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2079 /* Ok, we can do one word at a time.
2080 Normally we do the low-numbered word first,
2081 but if either operand is autodecrementing then we
2082 do the high-numbered word first.
2084 In either case, set up in LATEHALF the operands to use
2085 for the high-numbered word and in some cases alter the
2086 operands in OPERANDS to be suitable for the low-numbered word. */
2090 if (optype0
== REGOP
)
2092 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2093 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2095 else if (optype0
== OFFSOP
)
2097 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2098 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2102 middlehalf
[0] = operands
[0];
2103 latehalf
[0] = operands
[0];
2106 if (optype1
== REGOP
)
2108 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2109 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2111 else if (optype1
== OFFSOP
)
2113 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2114 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2116 else if (optype1
== CNSTOP
)
2118 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2123 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2124 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2125 operands
[1] = GEN_INT (l
[0]);
2126 middlehalf
[1] = GEN_INT (l
[1]);
2127 latehalf
[1] = GEN_INT (l
[2]);
2131 /* No non-CONST_DOUBLE constant should ever appear
2133 gcc_assert (!CONSTANT_P (operands
[1]));
2138 middlehalf
[1] = operands
[1];
2139 latehalf
[1] = operands
[1];
2143 /* size is not 12: */
2145 if (optype0
== REGOP
)
2146 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2147 else if (optype0
== OFFSOP
)
2148 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2150 latehalf
[0] = operands
[0];
2152 if (optype1
== REGOP
)
2153 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2154 else if (optype1
== OFFSOP
)
2155 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2156 else if (optype1
== CNSTOP
)
2157 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2159 latehalf
[1] = operands
[1];
2162 /* If insn is effectively movd N(sp),-(sp) then we will do the
2163 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2164 for the low word as well, to compensate for the first decrement of sp. */
2165 if (optype0
== PUSHOP
2166 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2167 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2168 operands
[1] = middlehalf
[1] = latehalf
[1];
2170 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2171 if the upper part of reg N does not appear in the MEM, arrange to
2172 emit the move late-half first. Otherwise, compute the MEM address
2173 into the upper part of N and use that as a pointer to the memory
2175 if (optype0
== REGOP
2176 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2178 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2180 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2181 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2183 /* If both halves of dest are used in the src memory address,
2184 compute the address into latehalf of dest.
2185 Note that this can't happen if the dest is two data regs. */
2187 xops
[0] = latehalf
[0];
2188 xops
[1] = XEXP (operands
[1], 0);
2189 output_asm_insn ("lea %a1,%0", xops
);
2190 if (GET_MODE (operands
[1]) == XFmode
)
2192 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2193 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2194 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2198 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2199 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2203 && reg_overlap_mentioned_p (middlehalf
[0],
2204 XEXP (operands
[1], 0)))
2206 /* Check for two regs used by both source and dest.
2207 Note that this can't happen if the dest is all data regs.
2208 It can happen if the dest is d6, d7, a0.
2209 But in that case, latehalf is an addr reg, so
2210 the code at compadr does ok. */
2212 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2213 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2216 /* JRV says this can't happen: */
2217 gcc_assert (!addreg0
&& !addreg1
);
2219 /* Only the middle reg conflicts; simply put it last. */
2220 output_asm_insn (singlemove_string (operands
), operands
);
2221 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2222 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2225 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2226 /* If the low half of dest is mentioned in the source memory
2227 address, the arrange to emit the move late half first. */
2228 dest_overlapped_low
= 1;
2231 /* If one or both operands autodecrementing,
2232 do the two words, high-numbered first. */
2234 /* Likewise, the first move would clobber the source of the second one,
2235 do them in the other order. This happens only for registers;
2236 such overlap can't happen in memory unless the user explicitly
2237 sets it up, and that is an undefined circumstance. */
2239 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2240 || (optype0
== REGOP
&& optype1
== REGOP
2241 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2242 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2243 || dest_overlapped_low
)
2245 /* Make any unoffsettable addresses point at high-numbered word. */
2249 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2251 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2256 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2258 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2262 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2264 /* Undo the adds we just did. */
2266 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2268 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2272 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2274 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2276 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2279 /* Do low-numbered word. */
2280 return singlemove_string (operands
);
2283 /* Normal case: do the two words, low-numbered first. */
2285 output_asm_insn (singlemove_string (operands
), operands
);
2287 /* Do the middle one of the three words for long double */
2291 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2293 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2295 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2298 /* Make any unoffsettable addresses point at high-numbered word. */
2300 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2302 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2305 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2307 /* Undo the adds we just did. */
2311 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2313 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2318 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2320 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2327 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2328 new rtx with the correct mode. */
2331 force_mode (enum machine_mode mode
, rtx orig
)
2333 if (mode
== GET_MODE (orig
))
2336 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2339 return gen_rtx_REG (mode
, REGNO (orig
));
2343 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2345 return reg_renumber
&& FP_REG_P (op
);
2348 /* Emit insns to move operands[1] into operands[0].
2350 Return 1 if we have written out everything that needs to be done to
2351 do the move. Otherwise, return 0 and the caller will emit the move
2354 Note SCRATCH_REG may not be in the proper mode depending on how it
2355 will be used. This routine is responsible for creating a new copy
2356 of SCRATCH_REG in the proper mode. */
2359 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2361 register rtx operand0
= operands
[0];
2362 register rtx operand1
= operands
[1];
2366 && reload_in_progress
&& GET_CODE (operand0
) == REG
2367 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2368 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2369 else if (scratch_reg
2370 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2371 && GET_CODE (SUBREG_REG (operand0
)) == REG
2372 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2374 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2375 the code which tracks sets/uses for delete_output_reload. */
2376 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2377 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2378 SUBREG_BYTE (operand0
));
2379 operand0
= alter_subreg (&temp
);
2383 && reload_in_progress
&& GET_CODE (operand1
) == REG
2384 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2385 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2386 else if (scratch_reg
2387 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2388 && GET_CODE (SUBREG_REG (operand1
)) == REG
2389 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2391 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2392 the code which tracks sets/uses for delete_output_reload. */
2393 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2394 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2395 SUBREG_BYTE (operand1
));
2396 operand1
= alter_subreg (&temp
);
2399 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2400 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2401 != XEXP (operand0
, 0)))
2402 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2403 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2404 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2405 != XEXP (operand1
, 0)))
2406 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2408 /* Handle secondary reloads for loads/stores of FP registers where
2409 the address is symbolic by using the scratch register */
2410 if (fp_reg_operand (operand0
, mode
)
2411 && ((GET_CODE (operand1
) == MEM
2412 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2413 || ((GET_CODE (operand1
) == SUBREG
2414 && GET_CODE (XEXP (operand1
, 0)) == MEM
2415 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2418 if (GET_CODE (operand1
) == SUBREG
)
2419 operand1
= XEXP (operand1
, 0);
2421 /* SCRATCH_REG will hold an address. We want
2422 it in SImode regardless of what mode it was originally given
2424 scratch_reg
= force_mode (SImode
, scratch_reg
);
2426 /* D might not fit in 14 bits either; for such cases load D into
2428 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2430 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2431 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2433 XEXP (XEXP (operand1
, 0), 0),
2437 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2438 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2439 gen_rtx_MEM (mode
, scratch_reg
)));
2442 else if (fp_reg_operand (operand1
, mode
)
2443 && ((GET_CODE (operand0
) == MEM
2444 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2445 || ((GET_CODE (operand0
) == SUBREG
)
2446 && GET_CODE (XEXP (operand0
, 0)) == MEM
2447 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2450 if (GET_CODE (operand0
) == SUBREG
)
2451 operand0
= XEXP (operand0
, 0);
2453 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2454 it in SIMODE regardless of what mode it was originally given
2456 scratch_reg
= force_mode (SImode
, scratch_reg
);
2458 /* D might not fit in 14 bits either; for such cases load D into
2460 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2462 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2463 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2466 XEXP (XEXP (operand0
, 0),
2471 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2472 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2476 /* Handle secondary reloads for loads of FP registers from constant
2477 expressions by forcing the constant into memory.
2479 use scratch_reg to hold the address of the memory location.
2481 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2482 NO_REGS when presented with a const_int and an register class
2483 containing only FP registers. Doing so unfortunately creates
2484 more problems than it solves. Fix this for 2.5. */
2485 else if (fp_reg_operand (operand0
, mode
)
2486 && CONSTANT_P (operand1
)
2491 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2492 it in SIMODE regardless of what mode it was originally given
2494 scratch_reg
= force_mode (SImode
, scratch_reg
);
2496 /* Force the constant into memory and put the address of the
2497 memory location into scratch_reg. */
2498 xoperands
[0] = scratch_reg
;
2499 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2500 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2502 /* Now load the destination register. */
2503 emit_insn (gen_rtx_SET (mode
, operand0
,
2504 gen_rtx_MEM (mode
, scratch_reg
)));
2508 /* Now have insn-emit do whatever it normally does. */
2512 /* Return a REG that occurs in ADDR with coefficient 1.
2513 ADDR can be effectively incremented by incrementing REG. */
2516 find_addr_reg (rtx addr
)
2518 while (GET_CODE (addr
) == PLUS
)
2520 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2521 addr
= XEXP (addr
, 0);
2522 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2523 addr
= XEXP (addr
, 1);
2524 else if (CONSTANT_P (XEXP (addr
, 0)))
2525 addr
= XEXP (addr
, 1);
2526 else if (CONSTANT_P (XEXP (addr
, 1)))
2527 addr
= XEXP (addr
, 0);
2531 gcc_assert (GET_CODE (addr
) == REG
);
2535 /* Output assembler code to perform a 32-bit 3-operand add. */
2538 output_addsi3 (rtx
*operands
)
2540 if (! operands_match_p (operands
[0], operands
[1]))
2542 if (!ADDRESS_REG_P (operands
[1]))
2544 rtx tmp
= operands
[1];
2546 operands
[1] = operands
[2];
2550 /* These insns can result from reloads to access
2551 stack slots over 64k from the frame pointer. */
2552 if (GET_CODE (operands
[2]) == CONST_INT
2553 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2554 return "move%.l %2,%0\n\tadd%.l %1,%0";
2555 if (GET_CODE (operands
[2]) == REG
)
2556 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2557 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2559 if (GET_CODE (operands
[2]) == CONST_INT
)
2561 if (INTVAL (operands
[2]) > 0
2562 && INTVAL (operands
[2]) <= 8)
2563 return "addq%.l %2,%0";
2564 if (INTVAL (operands
[2]) < 0
2565 && INTVAL (operands
[2]) >= -8)
2567 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2568 return "subq%.l %2,%0";
2570 /* On the CPU32 it is faster to use two addql instructions to
2571 add a small integer (8 < N <= 16) to a register.
2572 Likewise for subql. */
2573 if (TUNE_CPU32
&& REG_P (operands
[0]))
2575 if (INTVAL (operands
[2]) > 8
2576 && INTVAL (operands
[2]) <= 16)
2578 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2579 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2581 if (INTVAL (operands
[2]) < -8
2582 && INTVAL (operands
[2]) >= -16)
2584 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2585 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2588 if (ADDRESS_REG_P (operands
[0])
2589 && INTVAL (operands
[2]) >= -0x8000
2590 && INTVAL (operands
[2]) < 0x8000)
2593 return "add%.w %2,%0";
2595 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2598 return "add%.l %2,%0";
2601 /* Store in cc_status the expressions that the condition codes will
2602 describe after execution of an instruction whose pattern is EXP.
2603 Do not alter them if the instruction would not alter the cc's. */
2605 /* On the 68000, all the insns to store in an address register fail to
2606 set the cc's. However, in some cases these instructions can make it
2607 possibly invalid to use the saved cc's. In those cases we clear out
2608 some or all of the saved cc's so they won't be used. */
2611 notice_update_cc (rtx exp
, rtx insn
)
2613 if (GET_CODE (exp
) == SET
)
2615 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2617 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2619 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2620 cc_status
.value1
= 0;
2621 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2622 cc_status
.value2
= 0;
2624 else if (!FP_REG_P (SET_DEST (exp
))
2625 && SET_DEST (exp
) != cc0_rtx
2626 && (FP_REG_P (SET_SRC (exp
))
2627 || GET_CODE (SET_SRC (exp
)) == FIX
2628 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2629 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2631 /* A pair of move insns doesn't produce a useful overall cc. */
2632 else if (!FP_REG_P (SET_DEST (exp
))
2633 && !FP_REG_P (SET_SRC (exp
))
2634 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2635 && (GET_CODE (SET_SRC (exp
)) == REG
2636 || GET_CODE (SET_SRC (exp
)) == MEM
2637 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2639 else if (SET_DEST (exp
) != pc_rtx
)
2641 cc_status
.flags
= 0;
2642 cc_status
.value1
= SET_DEST (exp
);
2643 cc_status
.value2
= SET_SRC (exp
);
2646 else if (GET_CODE (exp
) == PARALLEL
2647 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2649 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2650 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2652 if (ADDRESS_REG_P (dest
))
2654 else if (dest
!= pc_rtx
)
2656 cc_status
.flags
= 0;
2657 cc_status
.value1
= dest
;
2658 cc_status
.value2
= src
;
2663 if (cc_status
.value2
!= 0
2664 && ADDRESS_REG_P (cc_status
.value2
)
2665 && GET_MODE (cc_status
.value2
) == QImode
)
2667 if (cc_status
.value2
!= 0)
2668 switch (GET_CODE (cc_status
.value2
))
2670 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2671 case ROTATE
: case ROTATERT
:
2672 /* These instructions always clear the overflow bit, and set
2673 the carry to the bit shifted out. */
2674 /* ??? We don't currently have a way to signal carry not valid,
2675 nor do we check for it in the branch insns. */
2679 case PLUS
: case MINUS
: case MULT
:
2680 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2681 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2682 cc_status
.flags
|= CC_NO_OVERFLOW
;
2685 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2686 ends with a move insn moving r2 in r2's mode.
2687 Thus, the cc's are set for r2.
2688 This can set N bit spuriously. */
2689 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2694 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2696 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2697 cc_status
.value2
= 0;
2698 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2699 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2700 cc_status
.flags
= CC_IN_68881
;
2704 output_move_const_double (rtx
*operands
)
2706 int code
= standard_68881_constant_p (operands
[1]);
2710 static char buf
[40];
2712 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2715 return "fmove%.d %1,%0";
2719 output_move_const_single (rtx
*operands
)
2721 int code
= standard_68881_constant_p (operands
[1]);
2725 static char buf
[40];
2727 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2730 return "fmove%.s %f1,%0";
2733 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2734 from the "fmovecr" instruction.
2735 The value, anded with 0xff, gives the code to use in fmovecr
2736 to get the desired constant. */
2738 /* This code has been fixed for cross-compilation. */
2740 static int inited_68881_table
= 0;
2742 static const char *const strings_68881
[7] = {
2752 static const int codes_68881
[7] = {
2762 REAL_VALUE_TYPE values_68881
[7];
2764 /* Set up values_68881 array by converting the decimal values
2765 strings_68881 to binary. */
2768 init_68881_table (void)
2772 enum machine_mode mode
;
2775 for (i
= 0; i
< 7; i
++)
2779 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2780 values_68881
[i
] = r
;
2782 inited_68881_table
= 1;
2786 standard_68881_constant_p (rtx x
)
2791 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2792 used at all on those chips. */
2796 if (! inited_68881_table
)
2797 init_68881_table ();
2799 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2801 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2803 for (i
= 0; i
< 6; i
++)
2805 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2806 return (codes_68881
[i
]);
2809 if (GET_MODE (x
) == SFmode
)
2812 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2813 return (codes_68881
[6]);
2815 /* larger powers of ten in the constants ram are not used
2816 because they are not equal to a `double' C constant. */
2820 /* If X is a floating-point constant, return the logarithm of X base 2,
2821 or 0 if X is not a power of 2. */
2824 floating_exact_log2 (rtx x
)
2826 REAL_VALUE_TYPE r
, r1
;
2829 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2831 if (REAL_VALUES_LESS (r
, dconst1
))
2834 exp
= real_exponent (&r
);
2835 real_2expN (&r1
, exp
);
2836 if (REAL_VALUES_EQUAL (r1
, r
))
2842 /* A C compound statement to output to stdio stream STREAM the
2843 assembler syntax for an instruction operand X. X is an RTL
2846 CODE is a value that can be used to specify one of several ways
2847 of printing the operand. It is used when identical operands
2848 must be printed differently depending on the context. CODE
2849 comes from the `%' specification that was used to request
2850 printing of the operand. If the specification was just `%DIGIT'
2851 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2852 is the ASCII code for LTR.
2854 If X is a register, this macro should print the register's name.
2855 The names can be found in an array `reg_names' whose type is
2856 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2858 When the machine description has a specification `%PUNCT' (a `%'
2859 followed by a punctuation character), this macro is called with
2860 a null pointer for X and the punctuation character for CODE.
2862 The m68k specific codes are:
2864 '.' for dot needed in Motorola-style opcode names.
2865 '-' for an operand pushing on the stack:
2866 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2867 '+' for an operand pushing on the stack:
2868 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2869 '@' for a reference to the top word on the stack:
2870 sp@, (sp) or (%sp) depending on the style of syntax.
2871 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2872 but & in SGS syntax).
2873 '!' for the cc register (used in an `and to cc' insn).
2874 '$' for the letter `s' in an op code, but only on the 68040.
2875 '&' for the letter `d' in an op code, but only on the 68040.
2876 '/' for register prefix needed by longlong.h.
2878 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2879 'd' to force memory addressing to be absolute, not relative.
2880 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2881 'o' for operands to go directly to output_operand_address (bypassing
2882 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2883 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2884 or print pair of registers as rx:ry.
2889 print_operand (FILE *file
, rtx op
, int letter
)
2894 fprintf (file
, ".");
2896 else if (letter
== '#')
2897 asm_fprintf (file
, "%I");
2898 else if (letter
== '-')
2899 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2900 else if (letter
== '+')
2901 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2902 else if (letter
== '@')
2903 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2904 else if (letter
== '!')
2905 asm_fprintf (file
, "%Rfpcr");
2906 else if (letter
== '$')
2908 if (TARGET_68040_ONLY
)
2909 fprintf (file
, "s");
2911 else if (letter
== '&')
2913 if (TARGET_68040_ONLY
)
2914 fprintf (file
, "d");
2916 else if (letter
== '/')
2917 asm_fprintf (file
, "%R");
2918 else if (letter
== 'o')
2920 /* This is only for direct addresses with TARGET_PCREL */
2921 gcc_assert (GET_CODE (op
) == MEM
2922 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
2924 output_addr_const (file
, XEXP (op
, 0));
2926 else if (GET_CODE (op
) == REG
)
2929 /* Print out the second register name of a register pair.
2930 I.e., R (6) => 7. */
2931 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2933 fputs (M68K_REGNAME(REGNO (op
)), file
);
2935 else if (GET_CODE (op
) == MEM
)
2937 output_address (XEXP (op
, 0));
2938 if (letter
== 'd' && ! TARGET_68020
2939 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2940 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2941 && INTVAL (XEXP (op
, 0)) < 0x8000
2942 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2943 fprintf (file
, MOTOROLA
? ".l" : ":l");
2945 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2948 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2949 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2951 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2954 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2955 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2957 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2960 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2961 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2965 /* Use `print_operand_address' instead of `output_addr_const'
2966 to ensure that we print relevant PIC stuff. */
2967 asm_fprintf (file
, "%I");
2969 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2970 print_operand_address (file
, op
);
2972 output_addr_const (file
, op
);
2977 /* A C compound statement to output to stdio stream STREAM the
2978 assembler syntax for an instruction operand that is a memory
2979 reference whose address is ADDR. ADDR is an RTL expression.
2981 Note that this contains a kludge that knows that the only reason
2982 we have an address (plus (label_ref...) (reg...)) when not generating
2983 PIC code is in the insn before a tablejump, and we know that m68k.md
2984 generates a label LInnn: on such an insn.
2986 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2987 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2989 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2990 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2991 we want. This difference can be accommodated by using an assembler
2992 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2993 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2994 macro. See m68k/sgs.h for an example; for versions without the bug.
2995 Some assemblers refuse all the above solutions. The workaround is to
2996 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2999 They also do not like things like "pea 1.w", so we simple leave off
3000 the .w on small constants.
3002 This routine is responsible for distinguishing between -fpic and -fPIC
3003 style relocations in an address. When generating -fpic code the
3004 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3005 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3008 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3009 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3010 #else /* !MOTOROLA */
3011 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3012 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3013 #endif /* !MOTOROLA */
3016 print_operand_address (FILE *file
, rtx addr
)
3018 register rtx reg1
, reg2
, breg
, ireg
;
3021 switch (GET_CODE (addr
))
3024 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3027 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3028 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3031 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3032 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3035 reg1
= reg2
= ireg
= breg
= offset
= 0;
3036 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3038 offset
= XEXP (addr
, 0);
3039 addr
= XEXP (addr
, 1);
3041 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3043 offset
= XEXP (addr
, 1);
3044 addr
= XEXP (addr
, 0);
3046 if (GET_CODE (addr
) != PLUS
)
3050 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3052 reg1
= XEXP (addr
, 0);
3053 addr
= XEXP (addr
, 1);
3055 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3057 reg1
= XEXP (addr
, 1);
3058 addr
= XEXP (addr
, 0);
3060 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3062 reg1
= XEXP (addr
, 0);
3063 addr
= XEXP (addr
, 1);
3065 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3067 reg1
= XEXP (addr
, 1);
3068 addr
= XEXP (addr
, 0);
3070 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3072 reg1
= XEXP (addr
, 0);
3073 addr
= XEXP (addr
, 1);
3075 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3077 reg1
= XEXP (addr
, 1);
3078 addr
= XEXP (addr
, 0);
3080 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3081 || GET_CODE (addr
) == SIGN_EXTEND
)
3089 #if 0 /* for OLD_INDEXING */
3090 else if (GET_CODE (addr
) == PLUS
)
3092 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3094 reg2
= XEXP (addr
, 0);
3095 addr
= XEXP (addr
, 1);
3097 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3099 reg2
= XEXP (addr
, 1);
3100 addr
= XEXP (addr
, 0);
3109 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3110 || GET_CODE (reg1
) == MULT
))
3111 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3116 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3121 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3122 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3125 if (GET_CODE (ireg
) == MULT
)
3127 scale
= INTVAL (XEXP (ireg
, 1));
3128 ireg
= XEXP (ireg
, 0);
3130 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3132 ASM_OUTPUT_CASE_FETCH (file
,
3133 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3134 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3135 fprintf (file
, "w");
3139 ASM_OUTPUT_CASE_FETCH (file
,
3140 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3141 M68K_REGNAME (REGNO (ireg
)));
3142 fprintf (file
, "l");
3145 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3149 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3150 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3152 ASM_OUTPUT_CASE_FETCH (file
,
3153 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3154 M68K_REGNAME (REGNO (breg
)));
3155 fprintf (file
, "l)");
3158 if (ireg
!= 0 || breg
!= 0)
3163 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3169 output_addr_const (file
, addr
);
3170 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3172 fprintf (file
, "@GOT");
3174 fprintf (file
, ".w");
3177 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3181 else /* !MOTOROLA */
3183 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3186 output_addr_const (file
, addr
);
3187 if (breg
== pic_offset_table_rtx
)
3191 fprintf (file
, ":w");
3194 fprintf (file
, ":l");
3203 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3205 scale
= INTVAL (XEXP (ireg
, 1));
3206 ireg
= XEXP (ireg
, 0);
3208 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3209 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3210 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3212 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3213 M68K_REGNAME (REGNO (ireg
)));
3215 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3219 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3220 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3222 ASM_OUTPUT_CASE_FETCH (file
,
3223 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3224 M68K_REGNAME (REGNO (reg1
)));
3225 fprintf (file
, "l)");
3228 /* FALL-THROUGH (is this really what we want?) */
3230 if (GET_CODE (addr
) == CONST_INT
3231 && INTVAL (addr
) < 0x8000
3232 && INTVAL (addr
) >= -0x8000)
3234 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3236 else if (GET_CODE (addr
) == CONST_INT
)
3238 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3240 else if (TARGET_PCREL
)
3243 output_addr_const (file
, addr
);
3245 asm_fprintf (file
, ":w,%Rpc)");
3247 asm_fprintf (file
, ":l,%Rpc)");
3251 /* Special case for SYMBOL_REF if the symbol name ends in
3252 `.<letter>', this can be mistaken as a size suffix. Put
3253 the name in parentheses. */
3254 if (GET_CODE (addr
) == SYMBOL_REF
3255 && strlen (XSTR (addr
, 0)) > 2
3256 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3259 output_addr_const (file
, addr
);
3263 output_addr_const (file
, addr
);
3269 /* Check for cases where a clr insns can be omitted from code using
3270 strict_low_part sets. For example, the second clrl here is not needed:
3271 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3273 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3274 insn we are checking for redundancy. TARGET is the register set by the
3278 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3283 p
= prev_nonnote_insn (first_insn
);
3287 /* If it isn't an insn, then give up. */
3288 if (GET_CODE (p
) != INSN
)
3291 if (reg_set_p (target
, p
))
3293 rtx set
= single_set (p
);
3296 /* If it isn't an easy to recognize insn, then give up. */
3300 dest
= SET_DEST (set
);
3302 /* If this sets the entire target register to zero, then our
3303 first_insn is redundant. */
3304 if (rtx_equal_p (dest
, target
)
3305 && SET_SRC (set
) == const0_rtx
)
3307 else if (GET_CODE (dest
) == STRICT_LOW_PART
3308 && GET_CODE (XEXP (dest
, 0)) == REG
3309 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3310 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3311 <= GET_MODE_SIZE (mode
)))
3312 /* This is a strict low part set which modifies less than
3313 we are using, so it is safe. */
3319 p
= prev_nonnote_insn (p
);
3325 /* Operand predicates for implementing asymmetric pc-relative addressing
3326 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3327 when used as a source operand, but not as a destination operand.
3329 We model this by restricting the meaning of the basic predicates
3330 (general_operand, memory_operand, etc) to forbid the use of this
3331 addressing mode, and then define the following predicates that permit
3332 this addressing mode. These predicates can then be used for the
3333 source operands of the appropriate instructions.
3335 n.b. While it is theoretically possible to change all machine patterns
3336 to use this addressing more where permitted by the architecture,
3337 it has only been implemented for "common" cases: SImode, HImode, and
3338 QImode operands, and only for the principle operations that would
3339 require this addressing mode: data movement and simple integer operations.
3341 In parallel with these new predicates, two new constraint letters
3342 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3343 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3344 In the pcrel case 's' is only valid in combination with 'a' registers.
3345 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3346 of how these constraints are used.
3348 The use of these predicates is strictly optional, though patterns that
3349 don't will cause an extra reload register to be allocated where one
3352 lea (abc:w,%pc),%a0 ; need to reload address
3353 moveq &1,%d1 ; since write to pc-relative space
3354 movel %d1,%a0@ ; is not allowed
3356 lea (abc:w,%pc),%a1 ; no need to reload address here
3357 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3359 For more info, consult tiemann@cygnus.com.
3362 All of the ugliness with predicates and constraints is due to the
3363 simple fact that the m68k does not allow a pc-relative addressing
3364 mode as a destination. gcc does not distinguish between source and
3365 destination addresses. Hence, if we claim that pc-relative address
3366 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3367 end up with invalid code. To get around this problem, we left
3368 pc-relative modes as invalid addresses, and then added special
3369 predicates and constraints to accept them.
3371 A cleaner way to handle this is to modify gcc to distinguish
3372 between source and destination addresses. We can then say that
3373 pc-relative is a valid source address but not a valid destination
3374 address, and hopefully avoid a lot of the predicate and constraint
3375 hackery. Unfortunately, this would be a pretty big change. It would
3376 be a useful change for a number of ports, but there aren't any current
3377 plans to undertake this.
3379 ***************************************************************************/
3383 output_andsi3 (rtx
*operands
)
3386 if (GET_CODE (operands
[2]) == CONST_INT
3387 && (INTVAL (operands
[2]) | 0xffff) == -1
3388 && (DATA_REG_P (operands
[0])
3389 || offsettable_memref_p (operands
[0]))
3390 && !TARGET_COLDFIRE
)
3392 if (GET_CODE (operands
[0]) != REG
)
3393 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3394 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3395 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3397 if (operands
[2] == const0_rtx
)
3399 return "and%.w %2,%0";
3401 if (GET_CODE (operands
[2]) == CONST_INT
3402 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3403 && (DATA_REG_P (operands
[0])
3404 || offsettable_memref_p (operands
[0])))
3406 if (DATA_REG_P (operands
[0]))
3407 operands
[1] = GEN_INT (logval
);
3410 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3411 operands
[1] = GEN_INT (logval
% 8);
3413 /* This does not set condition codes in a standard way. */
3415 return "bclr %1,%0";
3417 return "and%.l %2,%0";
3421 output_iorsi3 (rtx
*operands
)
3423 register int logval
;
3424 if (GET_CODE (operands
[2]) == CONST_INT
3425 && INTVAL (operands
[2]) >> 16 == 0
3426 && (DATA_REG_P (operands
[0])
3427 || offsettable_memref_p (operands
[0]))
3428 && !TARGET_COLDFIRE
)
3430 if (GET_CODE (operands
[0]) != REG
)
3431 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3432 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3434 if (INTVAL (operands
[2]) == 0xffff)
3435 return "mov%.w %2,%0";
3436 return "or%.w %2,%0";
3438 if (GET_CODE (operands
[2]) == CONST_INT
3439 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3440 && (DATA_REG_P (operands
[0])
3441 || offsettable_memref_p (operands
[0])))
3443 if (DATA_REG_P (operands
[0]))
3444 operands
[1] = GEN_INT (logval
);
3447 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3448 operands
[1] = GEN_INT (logval
% 8);
3451 return "bset %1,%0";
3453 return "or%.l %2,%0";
3457 output_xorsi3 (rtx
*operands
)
3459 register int logval
;
3460 if (GET_CODE (operands
[2]) == CONST_INT
3461 && INTVAL (operands
[2]) >> 16 == 0
3462 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3463 && !TARGET_COLDFIRE
)
3465 if (! DATA_REG_P (operands
[0]))
3466 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3467 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3469 if (INTVAL (operands
[2]) == 0xffff)
3471 return "eor%.w %2,%0";
3473 if (GET_CODE (operands
[2]) == CONST_INT
3474 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3475 && (DATA_REG_P (operands
[0])
3476 || offsettable_memref_p (operands
[0])))
3478 if (DATA_REG_P (operands
[0]))
3479 operands
[1] = GEN_INT (logval
);
3482 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3483 operands
[1] = GEN_INT (logval
% 8);
3486 return "bchg %1,%0";
3488 return "eor%.l %2,%0";
3491 #ifdef M68K_TARGET_COFF
3493 /* Output assembly to switch to section NAME with attribute FLAGS. */
3496 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3497 tree decl ATTRIBUTE_UNUSED
)
3501 if (flags
& SECTION_WRITE
)
3506 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3509 #endif /* M68K_TARGET_COFF */
3512 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3513 HOST_WIDE_INT delta
,
3514 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3520 if (delta
> 0 && delta
<= 8)
3521 asm_fprintf (file
, (MOTOROLA
3522 ? "\taddq.l %I%d,4(%Rsp)\n"
3523 : "\taddql %I%d,%Rsp@(4)\n"),
3525 else if (delta
< 0 && delta
>= -8)
3526 asm_fprintf (file
, (MOTOROLA
3527 ? "\tsubq.l %I%d,4(%Rsp)\n"
3528 : "\tsubql %I%d,%Rsp@(4)\n"),
3530 else if (TARGET_COLDFIRE
)
3532 /* ColdFire can't add/sub a constant to memory unless it is in
3533 the range of addq/subq. So load the value into %d0 and
3534 then add it to 4(%sp). */
3535 if (delta
>= -128 && delta
<= 127)
3536 asm_fprintf (file
, (MOTOROLA
3537 ? "\tmoveq.l %I%wd,%Rd0\n"
3538 : "\tmoveql %I%wd,%Rd0\n"),
3541 asm_fprintf (file
, (MOTOROLA
3542 ? "\tmove.l %I%wd,%Rd0\n"
3543 : "\tmovel %I%wd,%Rd0\n"),
3545 asm_fprintf (file
, (MOTOROLA
3546 ? "\tadd.l %Rd0,4(%Rsp)\n"
3547 : "\taddl %Rd0,%Rsp@(4)\n"));
3550 asm_fprintf (file
, (MOTOROLA
3551 ? "\tadd.l %I%wd,4(%Rsp)\n"
3552 : "\taddl %I%wd,%Rsp@(4)\n"),
3555 xops
[0] = DECL_RTL (function
);
3557 /* Logic taken from call patterns in m68k.md. */
3562 else if (flag_pic
== 1 || TARGET_68020
)
3566 #if defined (USE_GAS)
3567 fmt
= "bra.l %0@PLTPC";
3569 fmt
= "bra %0@PLTPC";
3572 else /* !MOTOROLA */
3581 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3582 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3584 fmt
= "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)";
3588 #if MOTOROLA && !defined (USE_GAS)
3595 output_asm_insn (fmt
, xops
);
3598 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3601 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3602 int incoming ATTRIBUTE_UNUSED
)
3604 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3607 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3609 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3610 unsigned int new_reg
)
3613 /* Interrupt functions can only use registers that have already been
3614 saved by the prologue, even if they would normally be
3617 if (m68k_interrupt_function_p (current_function_decl
)
3618 && !regs_ever_live
[new_reg
])
3624 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3625 On the 68000, the cpu registers can hold any mode except bytes in address
3626 registers, but the 68881 registers can hold only SFmode or DFmode. */
3628 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3632 /* Data Registers, can hold aggregate if fits in. */
3633 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3636 else if (regno
< 16)
3638 /* Address Registers, can't hold bytes, can hold aggregate if
3640 if (GET_MODE_SIZE (mode
) == 1)
3642 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3645 else if (regno
< 24)
3647 /* FPU registers, hold float or complex float of long double or
3649 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3650 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3651 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3657 /* Return floating point values in a 68881 register. This makes 68881 code
3658 a little bit faster. It also makes -msoft-float code incompatible with
3659 hard-float code, so people have to be careful not to mix the two.
3660 For ColdFire it was decided the ABI incompatibility is undesirable.
3661 If there is need for a hard-float ABI it is probably worth doing it
3662 properly and also passing function arguments in FP registers. */
3664 m68k_libcall_value (enum machine_mode mode
)
3671 return gen_rtx_REG (mode
, 16);
3676 return gen_rtx_REG (mode
, 0);
3680 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3682 enum machine_mode mode
;
3684 mode
= TYPE_MODE (valtype
);
3690 return gen_rtx_REG (mode
, 16);
3696 /* If the function returns a pointer, push that into %a0 */
3697 if (POINTER_TYPE_P (valtype
))
3698 return gen_rtx_REG (mode
, 8);
3700 return gen_rtx_REG (mode
, 0);