1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 /* The ASM_DOT macro allows easy string pasting to handle the differences
48 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
49 support the %. option. */
52 # define ASM_DOTW ".w"
53 # define ASM_DOTL ".l"
61 /* Structure describing stack frame layout. */
64 /* Stack pointer to frame pointer offset. */
67 /* Offset of FPU registers. */
68 HOST_WIDE_INT foffset
;
70 /* Frame size in bytes (rounded up). */
73 /* Data and address register. */
75 unsigned int reg_mask
;
76 unsigned int reg_rev_mask
;
80 unsigned int fpu_mask
;
81 unsigned int fpu_rev_mask
;
83 /* Offsets relative to ARG_POINTER. */
84 HOST_WIDE_INT frame_pointer_offset
;
85 HOST_WIDE_INT stack_pointer_offset
;
87 /* Function which the above information refers to. */
91 /* Current frame information calculated by m68k_compute_frame_layout(). */
92 static struct m68k_frame current_frame
;
94 static rtx
find_addr_reg (rtx
);
95 static const char *singlemove_string (rtx
*);
96 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
97 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
98 #ifdef M68K_TARGET_COFF
99 static void m68k_coff_asm_named_section (const char *, unsigned int);
100 #endif /* M68K_TARGET_COFF */
102 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
103 static void m68k_hp320_file_start (void);
105 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
106 HOST_WIDE_INT
, tree
);
107 static rtx
m68k_struct_value_rtx (tree
, int);
108 static bool m68k_interrupt_function_p (tree func
);
109 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
110 tree args
, int flags
,
112 static void m68k_compute_frame_layout (void);
113 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
114 static int const_int_cost (rtx
);
115 static bool m68k_rtx_costs (rtx
, int, int, int *);
118 /* Alignment to use for loops and jumps */
119 /* Specify power of two alignment used for loops. */
120 const char *m68k_align_loops_string
;
121 /* Specify power of two alignment used for non-loop jumps. */
122 const char *m68k_align_jumps_string
;
123 /* Specify power of two alignment used for functions. */
124 const char *m68k_align_funcs_string
;
125 /* Specify the identification number of the library being built */
126 const char *m68k_library_id_string
;
128 /* Specify power of two alignment used for loops. */
129 int m68k_align_loops
;
130 /* Specify power of two alignment used for non-loop jumps. */
131 int m68k_align_jumps
;
132 /* Specify power of two alignment used for functions. */
133 int m68k_align_funcs
;
135 /* Nonzero if the last compare/test insn had FP operands. The
136 sCC expanders peek at this to determine what to do for the
137 68060, which has no fsCC instructions. */
138 int m68k_last_compare_had_fp_operands
;
140 /* Initialize the GCC target structure. */
142 #if INT_OP_GROUP == INT_OP_DOT_WORD
143 #undef TARGET_ASM_ALIGNED_HI_OP
144 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
147 #if INT_OP_GROUP == INT_OP_NO_DOT
148 #undef TARGET_ASM_BYTE_OP
149 #define TARGET_ASM_BYTE_OP "\tbyte\t"
150 #undef TARGET_ASM_ALIGNED_HI_OP
151 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
152 #undef TARGET_ASM_ALIGNED_SI_OP
153 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
156 #if INT_OP_GROUP == INT_OP_DC
157 #undef TARGET_ASM_BYTE_OP
158 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
159 #undef TARGET_ASM_ALIGNED_HI_OP
160 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
161 #undef TARGET_ASM_ALIGNED_SI_OP
162 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
165 #undef TARGET_ASM_UNALIGNED_HI_OP
166 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
167 #undef TARGET_ASM_UNALIGNED_SI_OP
168 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
170 #undef TARGET_ASM_FUNCTION_PROLOGUE
171 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
172 #undef TARGET_ASM_FUNCTION_EPILOGUE
173 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
175 #undef TARGET_ASM_INTERNAL_LABEL
176 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
179 #undef TARGET_ASM_OUTPUT_MI_THUNK
180 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
181 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
182 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
184 #undef TARGET_ASM_FILE_START_APP_OFF
185 #define TARGET_ASM_FILE_START_APP_OFF true
187 #undef TARGET_RTX_COSTS
188 #define TARGET_RTX_COSTS m68k_rtx_costs
190 #undef TARGET_ATTRIBUTE_TABLE
191 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
193 #undef TARGET_PROMOTE_PROTOTYPES
194 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
196 #undef TARGET_STRUCT_VALUE_RTX
197 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
199 static const struct attribute_spec m68k_attribute_table
[] =
201 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
202 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
203 { NULL
, 0, 0, false, false, false, NULL
}
206 struct gcc_target targetm
= TARGET_INITIALIZER
;
208 /* Sometimes certain combinations of command options do not make
209 sense on a particular target machine. You can define a macro
210 `OVERRIDE_OPTIONS' to take account of this. This macro, if
211 defined, is executed once just after all the command options have
214 Don't use this macro to turn on various extra optimizations for
215 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
218 override_options (void)
225 /* Validate -malign-loops= value, or provide default */
226 m68k_align_loops
= def_align
;
227 if (m68k_align_loops_string
)
229 i
= atoi (m68k_align_loops_string
);
230 if (i
< 1 || i
> MAX_CODE_ALIGN
)
231 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
233 m68k_align_loops
= i
;
236 /* Library identification */
237 if (m68k_library_id_string
)
241 if (! TARGET_ID_SHARED_LIBRARY
)
242 error ("-mshared-library-id= specified without -mid-shared-library");
243 id
= atoi (m68k_library_id_string
);
244 if (id
< 0 || id
> MAX_LIBRARY_ID
)
245 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
247 /* From now on, m68k_library_id_string will contain the library offset. */
248 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
251 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
253 m68k_library_id_string
= "_current_shared_library_a5_offset_";
255 /* Sanity check to ensure that msep-data and mid-sahred-library are not
256 * both specified together. Doing so simply doesn't make sense.
258 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
259 error ("cannot specify both -msep-data and -mid-shared-library");
261 /* If we're generating code for a separate A5 relative data segment,
262 * we've got to enable -fPIC as well. This might be relaxable to
263 * -fpic but it hasn't been tested properly.
265 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
268 /* Validate -malign-jumps= value, or provide default */
269 m68k_align_jumps
= def_align
;
270 if (m68k_align_jumps_string
)
272 i
= atoi (m68k_align_jumps_string
);
273 if (i
< 1 || i
> MAX_CODE_ALIGN
)
274 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
276 m68k_align_jumps
= i
;
279 /* Validate -malign-functions= value, or provide default */
280 m68k_align_funcs
= def_align
;
281 if (m68k_align_funcs_string
)
283 i
= atoi (m68k_align_funcs_string
);
284 if (i
< 1 || i
> MAX_CODE_ALIGN
)
285 error ("-malign-functions=%d is not between 1 and %d",
288 m68k_align_funcs
= i
;
291 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
293 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
294 error("-fPIC is not currently supported on the 68000 or 68010\n");
296 /* ??? A historic way of turning on pic, or is this intended to
297 be an embedded thing that doesn't have the same name binding
298 significance that it does on hosted ELF systems? */
299 if (TARGET_PCREL
&& flag_pic
== 0)
302 /* Turn off function cse if we are doing PIC. We always want function call
303 to be done as `bsr foo@PLTPC', so it will force the assembler to create
304 the PLT entry for `foo'. Doing function cse will cause the address of
305 `foo' to be loaded into a register, which is exactly what we want to
306 avoid when we are doing PIC on svr4 m68k. */
308 flag_no_function_cse
= 1;
310 SUBTARGET_OVERRIDE_OPTIONS
;
313 /* Return nonzero if FUNC is an interrupt function as specified by the
314 "interrupt_handler" attribute. */
316 m68k_interrupt_function_p(tree func
)
320 if (TREE_CODE (func
) != FUNCTION_DECL
)
323 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
324 return (a
!= NULL_TREE
);
327 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
328 struct attribute_spec.handler. */
330 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
331 tree args ATTRIBUTE_UNUSED
,
332 int flags ATTRIBUTE_UNUSED
,
335 if (TREE_CODE (*node
) != FUNCTION_DECL
)
337 warning ("`%s' attribute only applies to functions",
338 IDENTIFIER_POINTER (name
));
339 *no_add_attrs
= true;
346 m68k_compute_frame_layout (void)
349 unsigned int mask
, rmask
;
350 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
352 /* Only compute the frame once per function.
353 Don't cache information until reload has been completed. */
354 if (current_frame
.funcdef_no
== current_function_funcdef_no
358 current_frame
.size
= (get_frame_size () + 3) & -4;
360 mask
= rmask
= saved
= 0;
361 for (regno
= 0; regno
< 16; regno
++)
362 if (m68k_save_reg (regno
, interrupt_handler
))
365 rmask
|= 1 << (15 - regno
);
368 current_frame
.offset
= saved
* 4;
369 current_frame
.reg_no
= saved
;
370 current_frame
.reg_mask
= mask
;
371 current_frame
.reg_rev_mask
= rmask
;
373 current_frame
.foffset
= 0;
374 mask
= rmask
= saved
= 0;
375 if (TARGET_68881
/* || TARGET_CFV4E */)
377 for (regno
= 16; regno
< 24; regno
++)
378 if (m68k_save_reg (regno
, interrupt_handler
))
380 mask
|= 1 << (regno
- 16);
381 rmask
|= 1 << (23 - regno
);
384 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
385 current_frame
.offset
+= current_frame
.foffset
;
387 current_frame
.fpu_no
= saved
;
388 current_frame
.fpu_mask
= mask
;
389 current_frame
.fpu_rev_mask
= rmask
;
391 /* Remember what function this frame refers to. */
392 current_frame
.funcdef_no
= current_function_funcdef_no
;
396 m68k_initial_elimination_offset (int from
, int to
)
398 /* FIXME: The correct offset to compute here would appear to be
399 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
400 but for some obscure reason, this must be 0 to get correct code. */
401 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
404 m68k_compute_frame_layout ();
406 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
407 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
408 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
409 return current_frame
.offset
+ current_frame
.size
;
414 /* Refer to the array `regs_ever_live' to determine which registers
415 to save; `regs_ever_live[I]' is nonzero if register number I
416 is ever used in the function. This function is responsible for
417 knowing which registers should not be saved even if used.
418 Return true if we need to save REGNO. */
421 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
423 if (flag_pic
&& current_function_uses_pic_offset_table
424 && regno
== PIC_OFFSET_TABLE_REGNUM
)
427 if (current_function_calls_eh_return
)
432 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
433 if (test
== INVALID_REGNUM
)
440 /* Fixed regs we never touch. */
441 if (fixed_regs
[regno
])
444 /* The frame pointer (if it is such) is handled specially. */
445 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
448 /* Interrupt handlers must also save call_used_regs
449 if they are live or when calling nested functions. */
450 if (interrupt_handler
)
452 if (regs_ever_live
[regno
])
455 if (!current_function_is_leaf
&& call_used_regs
[regno
])
459 /* Never need to save registers that aren't touched. */
460 if (!regs_ever_live
[regno
])
463 /* Otherwise save everything that isn't call-clobbered. */
464 return !call_used_regs
[regno
];
467 /* This function generates the assembly code for function entry.
468 STREAM is a stdio stream to output the code to.
469 SIZE is an int: how many units of temporary storage to allocate. */
472 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
474 HOST_WIDE_INT fsize_with_regs
;
475 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
477 m68k_compute_frame_layout();
479 /* If the stack limit is a symbol, we can check it here,
480 before actually allocating the space. */
481 if (current_function_limit_stack
482 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
483 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
484 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
486 /* On ColdFire add register save into initial stack frame setup, if possible. */
487 fsize_with_regs
= current_frame
.size
;
488 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
489 fsize_with_regs
+= current_frame
.reg_no
* 4;
491 if (frame_pointer_needed
)
493 if (current_frame
.size
== 0 && TARGET_68040
)
494 /* on the 68040, pea + move is faster than link.w 0 */
495 fprintf (stream
, MOTOROLA
?
496 "\tpea (%s)\n\tmove.l %s,%s\n" :
497 "\tpea %s@\n\tmovel %s,%s\n",
498 M68K_REGNAME(FRAME_POINTER_REGNUM
),
499 M68K_REGNAME(STACK_POINTER_REGNUM
),
500 M68K_REGNAME(FRAME_POINTER_REGNUM
));
501 else if (fsize_with_regs
< 0x8000)
502 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
503 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
504 else if (TARGET_68020
)
505 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
506 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
508 /* Adding negative number is faster on the 68040. */
509 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
510 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
511 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
513 if (dwarf2out_do_frame ())
516 l
= (char *) dwarf2out_cfi_label ();
518 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
519 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
520 cfa_offset
+= current_frame
.size
;
523 else if (fsize_with_regs
) /* !frame_pointer_needed */
525 if (fsize_with_regs
< 0x8000)
527 if (fsize_with_regs
<= 8)
529 if (!TARGET_COLDFIRE
)
530 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
533 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
536 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
537 /* On the CPU32 it is faster to use two subqw instructions to
538 subtract a small integer (8 < N <= 16) to a register. */
540 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
541 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
542 fsize_with_regs
- 8);
543 else if (TARGET_68040
)
544 /* Adding negative number is faster on the 68040. */
545 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
548 asm_fprintf (stream
, MOTOROLA
?
549 "\tlea (%wd,%Rsp),%Rsp\n" :
550 "\tlea %Rsp@(%wd),%Rsp\n",
553 else /* fsize_with_regs >= 0x8000 */
554 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
556 if (dwarf2out_do_frame ())
558 cfa_offset
+= current_frame
.size
+ 4;
559 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
561 } /* !frame_pointer_needed */
563 if (current_frame
.fpu_mask
)
565 asm_fprintf (stream
, MOTOROLA
?
566 "\tfmovm %I0x%x,-(%Rsp)\n" :
567 "\tfmovem %I0x%x,%Rsp@-\n",
568 current_frame
.fpu_mask
);
570 if (dwarf2out_do_frame ())
572 char *l
= (char *) dwarf2out_cfi_label ();
575 cfa_offset
+= current_frame
.fpu_no
* 12;
576 if (! frame_pointer_needed
)
577 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
578 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
579 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
580 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
584 /* If the stack limit is not a symbol, check it here.
585 This has the disadvantage that it may be too late... */
586 if (current_function_limit_stack
)
588 if (REG_P (stack_limit_rtx
))
589 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
590 M68K_REGNAME(REGNO (stack_limit_rtx
)));
591 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
592 warning ("stack limit expression is not supported");
595 if (current_frame
.reg_no
<= 2)
597 /* Store each separately in the same order moveml uses.
598 Using two movel instructions instead of a single moveml
599 is about 15% faster for the 68020 and 68030 at no expense
604 for (i
= 0; i
< 16; i
++)
605 if (current_frame
.reg_rev_mask
& (1 << i
))
607 asm_fprintf (stream
, MOTOROLA
?
608 "\t%Omove.l %s,-(%Rsp)\n" :
609 "\tmovel %s,%Rsp@-\n",
610 M68K_REGNAME(15 - i
));
611 if (dwarf2out_do_frame ())
613 char *l
= (char *) dwarf2out_cfi_label ();
616 if (! frame_pointer_needed
)
617 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
618 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
622 else if (current_frame
.reg_rev_mask
)
625 /* The ColdFire does not support the predecrement form of the
626 MOVEM instruction, so we must adjust the stack pointer and
627 then use the plain address register indirect mode.
628 The required register save space was combined earlier with
629 the fsize_with_regs amount. */
631 asm_fprintf (stream
, MOTOROLA
?
632 "\tmovm.l %I0x%x,(%Rsp)\n" :
633 "\tmoveml %I0x%x,%Rsp@\n",
634 current_frame
.reg_mask
);
636 asm_fprintf (stream
, MOTOROLA
?
637 "\tmovm.l %I0x%x,-(%Rsp)\n" :
638 "\tmoveml %I0x%x,%Rsp@-\n",
639 current_frame
.reg_rev_mask
);
640 if (dwarf2out_do_frame ())
642 char *l
= (char *) dwarf2out_cfi_label ();
645 cfa_offset
+= current_frame
.reg_no
* 4;
646 if (! frame_pointer_needed
)
647 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
648 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
649 if (current_frame
.reg_mask
& (1 << regno
))
650 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
653 if (!TARGET_SEP_DATA
&& flag_pic
&&
654 (current_function_uses_pic_offset_table
||
655 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
657 if (TARGET_ID_SHARED_LIBRARY
)
659 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
660 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
661 m68k_library_id_string
,
662 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
667 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
668 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
671 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
672 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
673 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
674 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
675 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
681 /* Return true if this function's epilogue can be output as RTL. */
684 use_return_insn (void)
686 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
689 /* We can output the epilogue as RTL only if no registers need to be
691 m68k_compute_frame_layout();
692 return current_frame
.reg_no
? false : true;
695 /* This function generates the assembly code for function exit,
696 on machines that need it.
698 The function epilogue should not depend on the current stack pointer!
699 It should use the frame pointer only, if there is a frame pointer.
700 This is mandatory because of alloca; we also take advantage of it to
701 omit stack adjustments before returning. */
704 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
706 HOST_WIDE_INT fsize
, fsize_with_regs
;
708 bool restore_from_sp
= false;
709 rtx insn
= get_last_insn ();
711 m68k_compute_frame_layout();
713 /* If the last insn was a BARRIER, we don't have to write any code. */
714 if (GET_CODE (insn
) == NOTE
)
715 insn
= prev_nonnote_insn (insn
);
716 if (insn
&& GET_CODE (insn
) == BARRIER
)
718 /* Output just a no-op so that debuggers don't get confused
719 about which function the pc is in at this address. */
720 fprintf (stream
, "\tnop\n");
724 #ifdef FUNCTION_EXTRA_EPILOGUE
725 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
728 fsize
= current_frame
.size
;
730 /* FIXME : leaf_function_p below is too strong.
731 What we really need to know there is if there could be pending
732 stack adjustment needed at that point. */
733 restore_from_sp
= ! frame_pointer_needed
734 || (! current_function_calls_alloca
&& leaf_function_p ());
736 /* fsize_with_regs is the size we need to adjust the sp when
737 popping the frame. */
738 fsize_with_regs
= fsize
;
740 /* Because the ColdFire doesn't support moveml with
741 complex address modes, we must adjust the stack manually
742 after restoring registers. When the frame pointer isn't used,
743 we can merge movem adjustment into frame unlinking
744 made immediately after it. */
745 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
746 fsize_with_regs
+= current_frame
.reg_no
* 4;
748 if (current_frame
.offset
+ fsize
>= 0x8000
750 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
752 /* Because the ColdFire doesn't support moveml with
753 complex address modes we make an extra correction here. */
755 fsize
+= current_frame
.offset
;
757 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
758 fsize
= 0, big
= true;
760 if (current_frame
.reg_no
<= 2)
762 /* Restore each separately in the same order moveml does.
763 Using two movel instructions instead of a single moveml
764 is about 15% faster for the 68020 and 68030 at no expense
768 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
770 for (i
= 0; i
< 16; i
++)
771 if (current_frame
.reg_mask
& (1 << i
))
776 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
778 M68K_REGNAME(FRAME_POINTER_REGNUM
),
781 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
782 M68K_REGNAME(FRAME_POINTER_REGNUM
),
786 else if (restore_from_sp
)
787 asm_fprintf (stream
, MOTOROLA
?
788 "\t%Omove.l (%Rsp)+,%s\n" :
789 "\tmovel %Rsp@+,%s\n",
794 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
796 M68K_REGNAME(FRAME_POINTER_REGNUM
),
799 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
800 M68K_REGNAME(FRAME_POINTER_REGNUM
),
807 else if (current_frame
.reg_mask
)
809 /* The ColdFire requires special handling due to its limited moveml insn. */
814 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
815 M68K_REGNAME(FRAME_POINTER_REGNUM
));
816 asm_fprintf (stream
, MOTOROLA
?
817 "\tmovm.l (%Ra1),%I0x%x\n" :
818 "\tmoveml %Ra1@,%I0x%x\n",
819 current_frame
.reg_mask
);
821 else if (restore_from_sp
)
822 asm_fprintf (stream
, MOTOROLA
?
823 "\tmovm.l (%Rsp),%I0x%x\n" :
824 "\tmoveml %Rsp@,%I0x%x\n",
825 current_frame
.reg_mask
);
829 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
830 current_frame
.offset
+ fsize
,
831 M68K_REGNAME(FRAME_POINTER_REGNUM
),
832 current_frame
.reg_mask
);
834 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
835 M68K_REGNAME(FRAME_POINTER_REGNUM
),
836 current_frame
.offset
+ fsize
,
837 current_frame
.reg_mask
);
840 else /* !TARGET_COLDFIRE */
845 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
846 current_frame
.offset
+ fsize
,
847 M68K_REGNAME(FRAME_POINTER_REGNUM
),
848 current_frame
.reg_mask
);
850 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
851 M68K_REGNAME(FRAME_POINTER_REGNUM
),
852 current_frame
.offset
+ fsize
,
853 current_frame
.reg_mask
);
855 else if (restore_from_sp
)
857 asm_fprintf (stream
, MOTOROLA
?
858 "\tmovm.l (%Rsp)+,%I0x%x\n" :
859 "\tmoveml %Rsp@+,%I0x%x\n",
860 current_frame
.reg_mask
);
865 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
866 current_frame
.offset
+ fsize
,
867 M68K_REGNAME(FRAME_POINTER_REGNUM
),
868 current_frame
.reg_mask
);
870 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
871 M68K_REGNAME(FRAME_POINTER_REGNUM
),
872 current_frame
.offset
+ fsize
,
873 current_frame
.reg_mask
);
877 if (current_frame
.fpu_rev_mask
)
882 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
883 current_frame
.foffset
+ fsize
,
884 M68K_REGNAME(FRAME_POINTER_REGNUM
),
885 current_frame
.fpu_rev_mask
);
887 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
888 M68K_REGNAME(FRAME_POINTER_REGNUM
),
889 current_frame
.foffset
+ fsize
,
890 current_frame
.fpu_rev_mask
);
892 else if (restore_from_sp
)
895 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
896 current_frame
.fpu_rev_mask
);
898 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
899 current_frame
.fpu_rev_mask
);
904 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
905 current_frame
.foffset
+ fsize
,
906 M68K_REGNAME(FRAME_POINTER_REGNUM
),
907 current_frame
.fpu_rev_mask
);
909 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
910 M68K_REGNAME(FRAME_POINTER_REGNUM
),
911 current_frame
.foffset
+ fsize
,
912 current_frame
.fpu_rev_mask
);
915 if (frame_pointer_needed
)
916 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
917 else if (fsize_with_regs
)
919 if (fsize_with_regs
<= 8)
921 if (!TARGET_COLDFIRE
)
922 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
925 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
928 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
930 /* On the CPU32 it is faster to use two addqw instructions to
931 add a small integer (8 < N <= 16) to a register. */
932 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
933 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
934 fsize_with_regs
- 8);
936 else if (fsize_with_regs
< 0x8000)
939 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
942 asm_fprintf (stream
, MOTOROLA
?
943 "\tlea (%wd,%Rsp),%Rsp\n" :
944 "\tlea %Rsp@(%wd),%Rsp\n",
948 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
950 if (current_function_calls_eh_return
)
951 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
952 if (m68k_interrupt_function_p (current_function_decl
))
953 fprintf (stream
, "\trte\n");
954 else if (current_function_pops_args
)
955 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
957 fprintf (stream
, "\trts\n");
960 /* Similar to general_operand, but exclude stack_pointer_rtx. */
963 not_sp_operand (rtx op
, enum machine_mode mode
)
965 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
968 /* Return true if X is a valid comparison operator for the dbcc
971 Note it rejects floating point comparison operators.
972 (In the future we could use Fdbcc).
974 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
977 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
979 switch (GET_CODE (x
))
981 case EQ
: case NE
: case GTU
: case LTU
:
985 /* Reject some when CC_NO_OVERFLOW is set. This may be over
987 case GT
: case LT
: case GE
: case LE
:
988 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
994 /* Return nonzero if flags are currently in the 68881 flag register. */
996 flags_in_68881 (void)
998 /* We could add support for these in the future */
999 return cc_status
.flags
& CC_IN_68881
;
1002 /* Output a BSR instruction suitable for PIC code. */
1004 m68k_output_pic_call(rtx dest
)
1008 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1010 /* We output a BSR instruction if we're using -fpic or we're building for
1011 * a target that supports long branches. If we're building -fPIC on the
1012 * 68000, 68010 or ColdFire we generate one of two sequences:
1013 * a shorter one that uses a GOT entry or a longer one that doesn't.
1014 * We'll use the -Os command-line flag to decide which to generate.
1015 * Both sequences take the same time to execute on the ColdFire.
1017 else if (TARGET_PCREL
)
1019 else if ((flag_pic
== 1) || TARGET_68020
)
1022 #elif defined(USE_GAS)
1023 out
= "bsr.l %0@PLTPC";
1025 out
= "bsr %0@PLTPC";
1027 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1028 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1030 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1032 output_asm_insn(out
, &dest
);
1035 /* Output a dbCC; jCC sequence. Note we do not handle the
1036 floating point version of this sequence (Fdbcc). We also
1037 do not handle alternative conditions when CC_NO_OVERFLOW is
1038 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1039 kick those out before we get here. */
1042 output_dbcc_and_branch (rtx
*operands
)
1044 switch (GET_CODE (operands
[3]))
1047 output_asm_insn (MOTOROLA
?
1048 "dbeq %0,%l1\n\tjbeq %l2" :
1049 "dbeq %0,%l1\n\tjeq %l2",
1054 output_asm_insn (MOTOROLA
?
1055 "dbne %0,%l1\n\tjbne %l2" :
1056 "dbne %0,%l1\n\tjne %l2",
1061 output_asm_insn (MOTOROLA
?
1062 "dbgt %0,%l1\n\tjbgt %l2" :
1063 "dbgt %0,%l1\n\tjgt %l2",
1068 output_asm_insn (MOTOROLA
?
1069 "dbhi %0,%l1\n\tjbhi %l2" :
1070 "dbhi %0,%l1\n\tjhi %l2",
1075 output_asm_insn (MOTOROLA
?
1076 "dblt %0,%l1\n\tjblt %l2" :
1077 "dblt %0,%l1\n\tjlt %l2",
1082 output_asm_insn (MOTOROLA
?
1083 "dbcs %0,%l1\n\tjbcs %l2" :
1084 "dbcs %0,%l1\n\tjcs %l2",
1089 output_asm_insn (MOTOROLA
?
1090 "dbge %0,%l1\n\tjbge %l2" :
1091 "dbge %0,%l1\n\tjge %l2",
1096 output_asm_insn (MOTOROLA
?
1097 "dbcc %0,%l1\n\tjbcc %l2" :
1098 "dbcc %0,%l1\n\tjcc %l2",
1103 output_asm_insn (MOTOROLA
?
1104 "dble %0,%l1\n\tjble %l2" :
1105 "dble %0,%l1\n\tjle %l2",
1110 output_asm_insn (MOTOROLA
?
1111 "dbls %0,%l1\n\tjbls %l2" :
1112 "dbls %0,%l1\n\tjls %l2",
1120 /* If the decrement is to be done in SImode, then we have
1121 to compensate for the fact that dbcc decrements in HImode. */
1122 switch (GET_MODE (operands
[0]))
1125 output_asm_insn (MOTOROLA
?
1126 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1127 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1140 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1143 enum rtx_code op_code
= GET_CODE (op
);
1145 /* This does not produce a useful cc. */
1148 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1149 below. Swap the operands and change the op if these requirements
1150 are not fulfilled. */
1151 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1155 operand1
= operand2
;
1157 op_code
= swap_condition (op_code
);
1159 loperands
[0] = operand1
;
1160 if (GET_CODE (operand1
) == REG
)
1161 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1163 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1164 if (operand2
!= const0_rtx
)
1166 loperands
[2] = operand2
;
1167 if (GET_CODE (operand2
) == REG
)
1168 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1170 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1172 loperands
[4] = gen_label_rtx();
1173 if (operand2
!= const0_rtx
)
1175 output_asm_insn (MOTOROLA
?
1176 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1177 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1182 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1183 output_asm_insn ("tst%.l %0", loperands
);
1186 output_asm_insn ("cmp%.w #0,%0", loperands
);
1189 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1191 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1192 output_asm_insn ("tst%.l %1", loperands
);
1194 output_asm_insn ("cmp%.w #0,%1", loperands
);
1197 loperands
[5] = dest
;
1202 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1203 CODE_LABEL_NUMBER (loperands
[4]));
1204 output_asm_insn ("seq %5", loperands
);
1208 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1209 CODE_LABEL_NUMBER (loperands
[4]));
1210 output_asm_insn ("sne %5", loperands
);
1214 loperands
[6] = gen_label_rtx();
1215 output_asm_insn (MOTOROLA
?
1216 "shi %5\n\tjbra %l6" :
1217 "shi %5\n\tjra %l6",
1219 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1220 CODE_LABEL_NUMBER (loperands
[4]));
1221 output_asm_insn ("sgt %5", loperands
);
1222 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1223 CODE_LABEL_NUMBER (loperands
[6]));
1227 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1228 CODE_LABEL_NUMBER (loperands
[4]));
1229 output_asm_insn ("shi %5", loperands
);
1233 loperands
[6] = gen_label_rtx();
1234 output_asm_insn (MOTOROLA
?
1235 "scs %5\n\tjbra %l6" :
1236 "scs %5\n\tjra %l6",
1238 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1239 CODE_LABEL_NUMBER (loperands
[4]));
1240 output_asm_insn ("slt %5", loperands
);
1241 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1242 CODE_LABEL_NUMBER (loperands
[6]));
1246 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1247 CODE_LABEL_NUMBER (loperands
[4]));
1248 output_asm_insn ("scs %5", loperands
);
1252 loperands
[6] = gen_label_rtx();
1253 output_asm_insn (MOTOROLA
?
1254 "scc %5\n\tjbra %l6" :
1255 "scc %5\n\tjra %l6",
1257 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1258 CODE_LABEL_NUMBER (loperands
[4]));
1259 output_asm_insn ("sge %5", loperands
);
1260 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1261 CODE_LABEL_NUMBER (loperands
[6]));
1265 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1266 CODE_LABEL_NUMBER (loperands
[4]));
1267 output_asm_insn ("scc %5", loperands
);
1271 loperands
[6] = gen_label_rtx();
1272 output_asm_insn (MOTOROLA
?
1273 "sls %5\n\tjbra %l6" :
1274 "sls %5\n\tjra %l6",
1276 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1277 CODE_LABEL_NUMBER (loperands
[4]));
1278 output_asm_insn ("sle %5", loperands
);
1279 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1280 CODE_LABEL_NUMBER (loperands
[6]));
1284 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1285 CODE_LABEL_NUMBER (loperands
[4]));
1286 output_asm_insn ("sls %5", loperands
);
1296 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1298 operands
[0] = countop
;
1299 operands
[1] = dataop
;
1301 if (GET_CODE (countop
) == CONST_INT
)
1303 register int count
= INTVAL (countop
);
1304 /* If COUNT is bigger than size of storage unit in use,
1305 advance to the containing unit of same size. */
1306 if (count
> signpos
)
1308 int offset
= (count
& ~signpos
) / 8;
1309 count
= count
& signpos
;
1310 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1312 if (count
== signpos
)
1313 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1315 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1317 /* These three statements used to use next_insns_test_no...
1318 but it appears that this should do the same job. */
1320 && next_insn_tests_no_inequality (insn
))
1323 && next_insn_tests_no_inequality (insn
))
1326 && next_insn_tests_no_inequality (insn
))
1329 cc_status
.flags
= CC_NOT_NEGATIVE
;
1331 return "btst %0,%1";
1334 /* Returns true if OP is either a symbol reference or a sum of a symbol
1335 reference and a constant. */
1338 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1340 switch (GET_CODE (op
))
1348 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1349 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1350 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1352 #if 0 /* Deleted, with corresponding change in m68k.h,
1353 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1355 return GET_MODE (op
) == mode
;
1363 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1366 extend_operator(rtx x
, enum machine_mode mode
)
1368 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1370 switch (GET_CODE(x
))
1381 /* Legitimize PIC addresses. If the address is already
1382 position-independent, we return ORIG. Newly generated
1383 position-independent addresses go to REG. If we need more
1384 than one register, we lose.
1386 An address is legitimized by making an indirect reference
1387 through the Global Offset Table with the name of the symbol
1390 The assembler and linker are responsible for placing the
1391 address of the symbol in the GOT. The function prologue
1392 is responsible for initializing a5 to the starting address
1395 The assembler is also responsible for translating a symbol name
1396 into a constant displacement from the start of the GOT.
1398 A quick example may make things a little clearer:
1400 When not generating PIC code to store the value 12345 into _foo
1401 we would generate the following code:
1405 When generating PIC two transformations are made. First, the compiler
1406 loads the address of foo into a register. So the first transformation makes:
1411 The code in movsi will intercept the lea instruction and call this
1412 routine which will transform the instructions into:
1414 movel a5@(_foo:w), a0
1418 That (in a nutshell) is how *all* symbol and label references are
1422 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1427 /* First handle a simple SYMBOL_REF or LABEL_REF */
1428 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1433 pic_ref
= gen_rtx_MEM (Pmode
,
1434 gen_rtx_PLUS (Pmode
,
1435 pic_offset_table_rtx
, orig
));
1436 current_function_uses_pic_offset_table
= 1;
1437 RTX_UNCHANGING_P (pic_ref
) = 1;
1438 emit_move_insn (reg
, pic_ref
);
1441 else if (GET_CODE (orig
) == CONST
)
1445 /* Make sure this has not already been legitimized. */
1446 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1447 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1453 /* legitimize both operands of the PLUS */
1454 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1456 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1457 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1458 base
== reg
? 0 : reg
);
1462 if (GET_CODE (orig
) == CONST_INT
)
1463 return plus_constant (base
, INTVAL (orig
));
1464 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1465 /* Likewise, should we set special REG_NOTEs here? */
1471 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1473 static CONST_METHOD
const_method (rtx
);
1475 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1478 const_method (rtx constant
)
1483 i
= INTVAL (constant
);
1487 /* The ColdFire doesn't have byte or word operations. */
1488 /* FIXME: This may not be useful for the m68060 either. */
1489 if (!TARGET_COLDFIRE
)
1491 /* if -256 < N < 256 but N is not in range for a moveq
1492 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1493 if (USE_MOVQ (i
^ 0xff))
1495 /* Likewise, try with not.w */
1496 if (USE_MOVQ (i
^ 0xffff))
1498 /* This is the only value where neg.w is useful */
1501 /* Try also with swap */
1503 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1506 /* Otherwise, use move.l */
1511 const_int_cost (rtx constant
)
1513 switch (const_method (constant
))
1516 /* Constants between -128 and 127 are cheap due to moveq */
1522 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1532 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1537 /* Constant zero is super cheap due to clr instruction. */
1538 if (x
== const0_rtx
)
1541 *total
= const_int_cost (x
);
1551 /* Make 0.0 cheaper than other floating constants to
1552 encourage creating tstsf and tstdf insns. */
1553 if (outer_code
== COMPARE
1554 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1560 /* These are vaguely right for a 68020. */
1561 /* The costs for long multiply have been adjusted to work properly
1562 in synth_mult on the 68020, relative to an average of the time
1563 for add and the time for shift, taking away a little more because
1564 sometimes move insns are needed. */
1565 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1566 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1567 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1568 TARGET_CFV3 ? 2 : 5)
1569 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1572 /* An lea costs about three times as much as a simple add. */
1573 if (GET_MODE (x
) == SImode
1574 && GET_CODE (XEXP (x
, 1)) == REG
1575 && GET_CODE (XEXP (x
, 0)) == MULT
1576 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1577 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1578 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1579 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1580 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1582 /* lea an@(dx:l:i),am */
1583 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1593 *total
= COSTS_N_INSNS(1);
1596 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1598 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1600 if (INTVAL (XEXP (x
, 1)) < 16)
1601 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1603 /* We're using clrw + swap for these cases. */
1604 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1607 *total
= COSTS_N_INSNS (10); /* worst case */
1610 /* A shift by a big integer takes an extra instruction. */
1611 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1612 && (INTVAL (XEXP (x
, 1)) == 16))
1614 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1617 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1618 && !(INTVAL (XEXP (x
, 1)) > 0
1619 && INTVAL (XEXP (x
, 1)) <= 8))
1621 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1627 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1628 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1629 && GET_MODE (x
) == SImode
)
1630 *total
= COSTS_N_INSNS (MULW_COST
);
1631 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1632 *total
= COSTS_N_INSNS (MULW_COST
);
1634 *total
= COSTS_N_INSNS (MULL_COST
);
1641 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1642 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1643 else if (TARGET_CF_HWDIV
)
1644 *total
= COSTS_N_INSNS (18);
1646 *total
= COSTS_N_INSNS (43); /* div.l */
1655 output_move_const_into_data_reg (rtx
*operands
)
1659 i
= INTVAL (operands
[1]);
1660 switch (const_method (operands
[1]))
1663 return "moveq %1,%0";
1666 operands
[1] = GEN_INT (i
^ 0xff);
1667 return "moveq %1,%0\n\tnot%.b %0";
1670 operands
[1] = GEN_INT (i
^ 0xffff);
1671 return "moveq %1,%0\n\tnot%.w %0";
1674 return "moveq #-128,%0\n\tneg%.w %0";
1679 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1680 return "moveq %1,%0\n\tswap %0";
1683 return "move%.l %1,%0";
1690 output_move_simode_const (rtx
*operands
)
1692 if (operands
[1] == const0_rtx
1693 && (DATA_REG_P (operands
[0])
1694 || GET_CODE (operands
[0]) == MEM
)
1695 /* clr insns on 68000 read before writing.
1696 This isn't so on the 68010, but we have no TARGET_68010. */
1697 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1698 || !(GET_CODE (operands
[0]) == MEM
1699 && MEM_VOLATILE_P (operands
[0]))))
1701 else if (operands
[1] == const0_rtx
1702 && ADDRESS_REG_P (operands
[0]))
1703 return "sub%.l %0,%0";
1704 else if (DATA_REG_P (operands
[0]))
1705 return output_move_const_into_data_reg (operands
);
1706 else if (ADDRESS_REG_P (operands
[0])
1707 && INTVAL (operands
[1]) < 0x8000
1708 && INTVAL (operands
[1]) >= -0x8000)
1709 return "move%.w %1,%0";
1710 else if (GET_CODE (operands
[0]) == MEM
1711 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1712 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1713 && INTVAL (operands
[1]) < 0x8000
1714 && INTVAL (operands
[1]) >= -0x8000)
1716 return "move%.l %1,%0";
1720 output_move_simode (rtx
*operands
)
1722 if (GET_CODE (operands
[1]) == CONST_INT
)
1723 return output_move_simode_const (operands
);
1724 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1725 || GET_CODE (operands
[1]) == CONST
)
1726 && push_operand (operands
[0], SImode
))
1728 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1729 || GET_CODE (operands
[1]) == CONST
)
1730 && ADDRESS_REG_P (operands
[0]))
1731 return "lea %a1,%0";
1732 return "move%.l %1,%0";
1736 output_move_himode (rtx
*operands
)
1738 if (GET_CODE (operands
[1]) == CONST_INT
)
1740 if (operands
[1] == const0_rtx
1741 && (DATA_REG_P (operands
[0])
1742 || GET_CODE (operands
[0]) == MEM
)
1743 /* clr insns on 68000 read before writing.
1744 This isn't so on the 68010, but we have no TARGET_68010. */
1745 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1746 || !(GET_CODE (operands
[0]) == MEM
1747 && MEM_VOLATILE_P (operands
[0]))))
1749 else if (operands
[1] == const0_rtx
1750 && ADDRESS_REG_P (operands
[0]))
1751 return "sub%.l %0,%0";
1752 else if (DATA_REG_P (operands
[0])
1753 && INTVAL (operands
[1]) < 128
1754 && INTVAL (operands
[1]) >= -128)
1756 return "moveq %1,%0";
1758 else if (INTVAL (operands
[1]) < 0x8000
1759 && INTVAL (operands
[1]) >= -0x8000)
1760 return "move%.w %1,%0";
1762 else if (CONSTANT_P (operands
[1]))
1763 return "move%.l %1,%0";
1764 /* Recognize the insn before a tablejump, one that refers
1765 to a table of offsets. Such an insn will need to refer
1766 to a label on the insn. So output one. Use the label-number
1767 of the table of offsets to generate this label. This code,
1768 and similar code below, assumes that there will be at most one
1769 reference to each table. */
1770 if (GET_CODE (operands
[1]) == MEM
1771 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1772 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1773 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1775 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1777 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1778 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1780 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1781 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1783 return "move%.w %1,%0";
1787 output_move_qimode (rtx
*operands
)
1791 /* This is probably useless, since it loses for pushing a struct
1792 of several bytes a byte at a time. */
1793 /* 68k family always modifies the stack pointer by at least 2, even for
1794 byte pushes. The 5200 (ColdFire) does not do this. */
1795 if (GET_CODE (operands
[0]) == MEM
1796 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1797 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1798 && ! ADDRESS_REG_P (operands
[1])
1799 && ! TARGET_COLDFIRE
)
1801 xoperands
[1] = operands
[1];
1803 = gen_rtx_MEM (QImode
,
1804 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1805 /* Just pushing a byte puts it in the high byte of the halfword. */
1806 /* We must put it in the low-order, high-numbered byte. */
1807 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1809 xoperands
[3] = stack_pointer_rtx
;
1810 output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands
);
1813 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1817 /* clr and st insns on 68000 read before writing.
1818 This isn't so on the 68010, but we have no TARGET_68010. */
1819 if (!ADDRESS_REG_P (operands
[0])
1820 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1821 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1823 if (operands
[1] == const0_rtx
)
1825 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1826 && GET_CODE (operands
[1]) == CONST_INT
1827 && (INTVAL (operands
[1]) & 255) == 255)
1833 if (GET_CODE (operands
[1]) == CONST_INT
1834 && DATA_REG_P (operands
[0])
1835 && INTVAL (operands
[1]) < 128
1836 && INTVAL (operands
[1]) >= -128)
1838 return "moveq %1,%0";
1840 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1841 return "sub%.l %0,%0";
1842 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1843 return "move%.l %1,%0";
1844 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1845 from address registers. */
1846 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1847 return "move%.w %1,%0";
1848 return "move%.b %1,%0";
1852 output_move_stricthi (rtx
*operands
)
1854 if (operands
[1] == const0_rtx
1855 /* clr insns on 68000 read before writing.
1856 This isn't so on the 68010, but we have no TARGET_68010. */
1857 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1858 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1860 return "move%.w %1,%0";
1864 output_move_strictqi (rtx
*operands
)
1866 if (operands
[1] == const0_rtx
1867 /* clr insns on 68000 read before writing.
1868 This isn't so on the 68010, but we have no TARGET_68010. */
1869 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1870 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1872 return "move%.b %1,%0";
1875 /* Return the best assembler insn template
1876 for moving operands[1] into operands[0] as a fullword. */
1879 singlemove_string (rtx
*operands
)
1881 if (GET_CODE (operands
[1]) == CONST_INT
)
1882 return output_move_simode_const (operands
);
1883 return "move%.l %1,%0";
1887 /* Output assembler code to perform a doubleword move insn
1888 with operands OPERANDS. */
1891 output_move_double (rtx
*operands
)
1895 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1900 rtx addreg0
= 0, addreg1
= 0;
1901 int dest_overlapped_low
= 0;
1902 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1907 /* First classify both operands. */
1909 if (REG_P (operands
[0]))
1911 else if (offsettable_memref_p (operands
[0]))
1913 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1915 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1917 else if (GET_CODE (operands
[0]) == MEM
)
1922 if (REG_P (operands
[1]))
1924 else if (CONSTANT_P (operands
[1]))
1926 else if (offsettable_memref_p (operands
[1]))
1928 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1930 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1932 else if (GET_CODE (operands
[1]) == MEM
)
1937 /* Check for the cases that the operand constraints are not
1938 supposed to allow to happen. Abort if we get one,
1939 because generating code for these cases is painful. */
1941 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1944 /* If one operand is decrementing and one is incrementing
1945 decrement the former register explicitly
1946 and change that operand into ordinary indexing. */
1948 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1950 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1952 output_asm_insn ("sub%.l #12,%0", operands
);
1954 output_asm_insn ("subq%.l #8,%0", operands
);
1955 if (GET_MODE (operands
[1]) == XFmode
)
1956 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1957 else if (GET_MODE (operands
[0]) == DFmode
)
1958 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1960 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1963 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1965 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1967 output_asm_insn ("sub%.l #12,%1", operands
);
1969 output_asm_insn ("subq%.l #8,%1", operands
);
1970 if (GET_MODE (operands
[1]) == XFmode
)
1971 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1972 else if (GET_MODE (operands
[1]) == DFmode
)
1973 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1975 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1979 /* If an operand is an unoffsettable memory ref, find a register
1980 we can increment temporarily to make it refer to the second word. */
1982 if (optype0
== MEMOP
)
1983 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1985 if (optype1
== MEMOP
)
1986 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1988 /* Ok, we can do one word at a time.
1989 Normally we do the low-numbered word first,
1990 but if either operand is autodecrementing then we
1991 do the high-numbered word first.
1993 In either case, set up in LATEHALF the operands to use
1994 for the high-numbered word and in some cases alter the
1995 operands in OPERANDS to be suitable for the low-numbered word. */
1999 if (optype0
== REGOP
)
2001 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2002 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2004 else if (optype0
== OFFSOP
)
2006 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2007 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2011 middlehalf
[0] = operands
[0];
2012 latehalf
[0] = operands
[0];
2015 if (optype1
== REGOP
)
2017 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2018 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2020 else if (optype1
== OFFSOP
)
2022 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2023 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2025 else if (optype1
== CNSTOP
)
2027 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2032 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2033 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2034 operands
[1] = GEN_INT (l
[0]);
2035 middlehalf
[1] = GEN_INT (l
[1]);
2036 latehalf
[1] = GEN_INT (l
[2]);
2038 else if (CONSTANT_P (operands
[1]))
2040 /* actually, no non-CONST_DOUBLE constant should ever
2043 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2044 latehalf
[1] = constm1_rtx
;
2046 latehalf
[1] = const0_rtx
;
2051 middlehalf
[1] = operands
[1];
2052 latehalf
[1] = operands
[1];
2056 /* size is not 12: */
2058 if (optype0
== REGOP
)
2059 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2060 else if (optype0
== OFFSOP
)
2061 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2063 latehalf
[0] = operands
[0];
2065 if (optype1
== REGOP
)
2066 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2067 else if (optype1
== OFFSOP
)
2068 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2069 else if (optype1
== CNSTOP
)
2070 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2072 latehalf
[1] = operands
[1];
2075 /* If insn is effectively movd N(sp),-(sp) then we will do the
2076 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2077 for the low word as well, to compensate for the first decrement of sp. */
2078 if (optype0
== PUSHOP
2079 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2080 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2081 operands
[1] = middlehalf
[1] = latehalf
[1];
2083 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2084 if the upper part of reg N does not appear in the MEM, arrange to
2085 emit the move late-half first. Otherwise, compute the MEM address
2086 into the upper part of N and use that as a pointer to the memory
2088 if (optype0
== REGOP
2089 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2091 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2093 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2094 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2096 /* If both halves of dest are used in the src memory address,
2097 compute the address into latehalf of dest.
2098 Note that this can't happen if the dest is two data regs. */
2100 xops
[0] = latehalf
[0];
2101 xops
[1] = XEXP (operands
[1], 0);
2102 output_asm_insn ("lea %a1,%0", xops
);
2103 if (GET_MODE (operands
[1]) == XFmode
)
2105 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2106 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2107 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2111 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2112 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2116 && reg_overlap_mentioned_p (middlehalf
[0],
2117 XEXP (operands
[1], 0)))
2119 /* Check for two regs used by both source and dest.
2120 Note that this can't happen if the dest is all data regs.
2121 It can happen if the dest is d6, d7, a0.
2122 But in that case, latehalf is an addr reg, so
2123 the code at compadr does ok. */
2125 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2126 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2129 /* JRV says this can't happen: */
2130 if (addreg0
|| addreg1
)
2133 /* Only the middle reg conflicts; simply put it last. */
2134 output_asm_insn (singlemove_string (operands
), operands
);
2135 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2136 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2139 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2140 /* If the low half of dest is mentioned in the source memory
2141 address, the arrange to emit the move late half first. */
2142 dest_overlapped_low
= 1;
2145 /* If one or both operands autodecrementing,
2146 do the two words, high-numbered first. */
2148 /* Likewise, the first move would clobber the source of the second one,
2149 do them in the other order. This happens only for registers;
2150 such overlap can't happen in memory unless the user explicitly
2151 sets it up, and that is an undefined circumstance. */
2153 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2154 || (optype0
== REGOP
&& optype1
== REGOP
2155 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2156 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2157 || dest_overlapped_low
)
2159 /* Make any unoffsettable addresses point at high-numbered word. */
2163 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2165 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2170 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2172 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2176 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2178 /* Undo the adds we just did. */
2180 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2182 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2186 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2188 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2190 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2193 /* Do low-numbered word. */
2194 return singlemove_string (operands
);
2197 /* Normal case: do the two words, low-numbered first. */
2199 output_asm_insn (singlemove_string (operands
), operands
);
2201 /* Do the middle one of the three words for long double */
2205 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2207 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2209 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2212 /* Make any unoffsettable addresses point at high-numbered word. */
2214 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2216 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2219 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2221 /* Undo the adds we just did. */
2225 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2227 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2232 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2234 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2240 /* Return a REG that occurs in ADDR with coefficient 1.
2241 ADDR can be effectively incremented by incrementing REG. */
2244 find_addr_reg (rtx addr
)
2246 while (GET_CODE (addr
) == PLUS
)
2248 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2249 addr
= XEXP (addr
, 0);
2250 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2251 addr
= XEXP (addr
, 1);
2252 else if (CONSTANT_P (XEXP (addr
, 0)))
2253 addr
= XEXP (addr
, 1);
2254 else if (CONSTANT_P (XEXP (addr
, 1)))
2255 addr
= XEXP (addr
, 0);
2259 if (GET_CODE (addr
) == REG
)
2264 /* Output assembler code to perform a 32-bit 3-operand add. */
2267 output_addsi3 (rtx
*operands
)
2269 if (! operands_match_p (operands
[0], operands
[1]))
2271 if (!ADDRESS_REG_P (operands
[1]))
2273 rtx tmp
= operands
[1];
2275 operands
[1] = operands
[2];
2279 /* These insns can result from reloads to access
2280 stack slots over 64k from the frame pointer. */
2281 if (GET_CODE (operands
[2]) == CONST_INT
2282 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2283 return "move%.l %2,%0\n\tadd%.l %1,%0";
2284 if (GET_CODE (operands
[2]) == REG
)
2285 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2286 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2288 if (GET_CODE (operands
[2]) == CONST_INT
)
2290 if (INTVAL (operands
[2]) > 0
2291 && INTVAL (operands
[2]) <= 8)
2292 return "addq%.l %2,%0";
2293 if (INTVAL (operands
[2]) < 0
2294 && INTVAL (operands
[2]) >= -8)
2296 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2297 return "subq%.l %2,%0";
2299 /* On the CPU32 it is faster to use two addql instructions to
2300 add a small integer (8 < N <= 16) to a register.
2301 Likewise for subql. */
2302 if (TARGET_CPU32
&& REG_P (operands
[0]))
2304 if (INTVAL (operands
[2]) > 8
2305 && INTVAL (operands
[2]) <= 16)
2307 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2308 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2310 if (INTVAL (operands
[2]) < -8
2311 && INTVAL (operands
[2]) >= -16)
2313 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2314 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2317 if (ADDRESS_REG_P (operands
[0])
2318 && INTVAL (operands
[2]) >= -0x8000
2319 && INTVAL (operands
[2]) < 0x8000)
2322 return "add%.w %2,%0";
2324 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2327 return "add%.l %2,%0";
2330 /* Store in cc_status the expressions that the condition codes will
2331 describe after execution of an instruction whose pattern is EXP.
2332 Do not alter them if the instruction would not alter the cc's. */
2334 /* On the 68000, all the insns to store in an address register fail to
2335 set the cc's. However, in some cases these instructions can make it
2336 possibly invalid to use the saved cc's. In those cases we clear out
2337 some or all of the saved cc's so they won't be used. */
2340 notice_update_cc (rtx exp
, rtx insn
)
2342 if (GET_CODE (exp
) == SET
)
2344 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2348 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2350 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2351 cc_status
.value1
= 0;
2352 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2353 cc_status
.value2
= 0;
2355 else if (!FP_REG_P (SET_DEST (exp
))
2356 && SET_DEST (exp
) != cc0_rtx
2357 && (FP_REG_P (SET_SRC (exp
))
2358 || GET_CODE (SET_SRC (exp
)) == FIX
2359 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2360 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2364 /* A pair of move insns doesn't produce a useful overall cc. */
2365 else if (!FP_REG_P (SET_DEST (exp
))
2366 && !FP_REG_P (SET_SRC (exp
))
2367 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2368 && (GET_CODE (SET_SRC (exp
)) == REG
2369 || GET_CODE (SET_SRC (exp
)) == MEM
2370 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2374 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2378 else if (XEXP (exp
, 0) != pc_rtx
)
2380 cc_status
.flags
= 0;
2381 cc_status
.value1
= XEXP (exp
, 0);
2382 cc_status
.value2
= XEXP (exp
, 1);
2385 else if (GET_CODE (exp
) == PARALLEL
2386 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2388 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2390 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2392 cc_status
.flags
= 0;
2393 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2394 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2399 if (cc_status
.value2
!= 0
2400 && ADDRESS_REG_P (cc_status
.value2
)
2401 && GET_MODE (cc_status
.value2
) == QImode
)
2403 if (cc_status
.value2
!= 0)
2404 switch (GET_CODE (cc_status
.value2
))
2406 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2407 case ROTATE
: case ROTATERT
:
2408 /* These instructions always clear the overflow bit, and set
2409 the carry to the bit shifted out. */
2410 /* ??? We don't currently have a way to signal carry not valid,
2411 nor do we check for it in the branch insns. */
2415 case PLUS
: case MINUS
: case MULT
:
2416 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2417 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2418 cc_status
.flags
|= CC_NO_OVERFLOW
;
2421 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2422 ends with a move insn moving r2 in r2's mode.
2423 Thus, the cc's are set for r2.
2424 This can set N bit spuriously. */
2425 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2430 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2432 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2433 cc_status
.value2
= 0;
2434 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2435 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2436 cc_status
.flags
= CC_IN_68881
;
2440 output_move_const_double (rtx
*operands
)
2442 int code
= standard_68881_constant_p (operands
[1]);
2446 static char buf
[40];
2448 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2451 return "fmove%.d %1,%0";
2455 output_move_const_single (rtx
*operands
)
2457 int code
= standard_68881_constant_p (operands
[1]);
2461 static char buf
[40];
2463 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2466 return "fmove%.s %f1,%0";
2469 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2470 from the "fmovecr" instruction.
2471 The value, anded with 0xff, gives the code to use in fmovecr
2472 to get the desired constant. */
2474 /* This code has been fixed for cross-compilation. */
2476 static int inited_68881_table
= 0;
2478 static const char *const strings_68881
[7] = {
2488 static const int codes_68881
[7] = {
2498 REAL_VALUE_TYPE values_68881
[7];
2500 /* Set up values_68881 array by converting the decimal values
2501 strings_68881 to binary. */
2504 init_68881_table (void)
2508 enum machine_mode mode
;
2511 for (i
= 0; i
< 7; i
++)
2515 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2516 values_68881
[i
] = r
;
2518 inited_68881_table
= 1;
2522 standard_68881_constant_p (rtx x
)
2527 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2528 used at all on those chips. */
2529 if (TARGET_68040
|| TARGET_68060
)
2532 if (! inited_68881_table
)
2533 init_68881_table ();
2535 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2537 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2539 for (i
= 0; i
< 6; i
++)
2541 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2542 return (codes_68881
[i
]);
2545 if (GET_MODE (x
) == SFmode
)
2548 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2549 return (codes_68881
[6]);
2551 /* larger powers of ten in the constants ram are not used
2552 because they are not equal to a `double' C constant. */
2556 /* If X is a floating-point constant, return the logarithm of X base 2,
2557 or 0 if X is not a power of 2. */
2560 floating_exact_log2 (rtx x
)
2562 REAL_VALUE_TYPE r
, r1
;
2565 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2567 if (REAL_VALUES_LESS (r
, dconst1
))
2570 exp
= real_exponent (&r
);
2571 real_2expN (&r1
, exp
);
2572 if (REAL_VALUES_EQUAL (r1
, r
))
2578 /* A C compound statement to output to stdio stream STREAM the
2579 assembler syntax for an instruction operand X. X is an RTL
2582 CODE is a value that can be used to specify one of several ways
2583 of printing the operand. It is used when identical operands
2584 must be printed differently depending on the context. CODE
2585 comes from the `%' specification that was used to request
2586 printing of the operand. If the specification was just `%DIGIT'
2587 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2588 is the ASCII code for LTR.
2590 If X is a register, this macro should print the register's name.
2591 The names can be found in an array `reg_names' whose type is
2592 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2594 When the machine description has a specification `%PUNCT' (a `%'
2595 followed by a punctuation character), this macro is called with
2596 a null pointer for X and the punctuation character for CODE.
2598 The m68k specific codes are:
2600 '.' for dot needed in Motorola-style opcode names.
2601 '-' for an operand pushing on the stack:
2602 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2603 '+' for an operand pushing on the stack:
2604 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2605 '@' for a reference to the top word on the stack:
2606 sp@, (sp) or (%sp) depending on the style of syntax.
2607 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2608 but & in SGS syntax).
2609 '!' for the cc register (used in an `and to cc' insn).
2610 '$' for the letter `s' in an op code, but only on the 68040.
2611 '&' for the letter `d' in an op code, but only on the 68040.
2612 '/' for register prefix needed by longlong.h.
2614 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2615 'd' to force memory addressing to be absolute, not relative.
2616 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2617 'o' for operands to go directly to output_operand_address (bypassing
2618 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2619 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2620 or print pair of registers as rx:ry.
2625 print_operand (FILE *file
, rtx op
, int letter
)
2630 fprintf (file
, ".");
2632 else if (letter
== '#')
2633 asm_fprintf (file
, "%I");
2634 else if (letter
== '-')
2635 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2636 else if (letter
== '+')
2637 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2638 else if (letter
== '@')
2639 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2640 else if (letter
== '!')
2641 asm_fprintf (file
, "%Rfpcr");
2642 else if (letter
== '$')
2644 if (TARGET_68040_ONLY
)
2645 fprintf (file
, "s");
2647 else if (letter
== '&')
2649 if (TARGET_68040_ONLY
)
2650 fprintf (file
, "d");
2652 else if (letter
== '/')
2653 asm_fprintf (file
, "%R");
2654 else if (letter
== 'o')
2656 /* This is only for direct addresses with TARGET_PCREL */
2657 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2660 output_addr_const (file
, XEXP (op
, 0));
2662 else if (GET_CODE (op
) == REG
)
2665 /* Print out the second register name of a register pair.
2666 I.e., R (6) => 7. */
2667 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2669 fputs (M68K_REGNAME(REGNO (op
)), file
);
2671 else if (GET_CODE (op
) == MEM
)
2673 output_address (XEXP (op
, 0));
2674 if (letter
== 'd' && ! TARGET_68020
2675 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2676 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2677 && INTVAL (XEXP (op
, 0)) < 0x8000
2678 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2679 fprintf (file
, MOTOROLA
? ".l" : ":l");
2681 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2684 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2685 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2687 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2690 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2691 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2693 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2696 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2697 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2701 /* Use `print_operand_address' instead of `output_addr_const'
2702 to ensure that we print relevant PIC stuff. */
2703 asm_fprintf (file
, "%I");
2705 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2706 print_operand_address (file
, op
);
2708 output_addr_const (file
, op
);
2713 /* A C compound statement to output to stdio stream STREAM the
2714 assembler syntax for an instruction operand that is a memory
2715 reference whose address is ADDR. ADDR is an RTL expression.
2717 Note that this contains a kludge that knows that the only reason
2718 we have an address (plus (label_ref...) (reg...)) when not generating
2719 PIC code is in the insn before a tablejump, and we know that m68k.md
2720 generates a label LInnn: on such an insn.
2722 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2723 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2725 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2726 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2727 we want. This difference can be accommodated by using an assembler
2728 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2729 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2730 macro. See m68k/sgs.h for an example; for versions without the bug.
2731 Some assemblers refuse all the above solutions. The workaround is to
2732 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2735 They also do not like things like "pea 1.w", so we simple leave off
2736 the .w on small constants.
2738 This routine is responsible for distinguishing between -fpic and -fPIC
2739 style relocations in an address. When generating -fpic code the
2740 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2741 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2744 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2745 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2746 #else /* !MOTOROLA */
2747 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2748 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2749 #endif /* !MOTOROLA */
2752 print_operand_address (FILE *file
, rtx addr
)
2754 register rtx reg1
, reg2
, breg
, ireg
;
2757 switch (GET_CODE (addr
))
2760 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2763 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2764 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2767 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2768 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2771 reg1
= reg2
= ireg
= breg
= offset
= 0;
2772 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2774 offset
= XEXP (addr
, 0);
2775 addr
= XEXP (addr
, 1);
2777 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2779 offset
= XEXP (addr
, 1);
2780 addr
= XEXP (addr
, 0);
2782 if (GET_CODE (addr
) != PLUS
)
2786 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2788 reg1
= XEXP (addr
, 0);
2789 addr
= XEXP (addr
, 1);
2791 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2793 reg1
= XEXP (addr
, 1);
2794 addr
= XEXP (addr
, 0);
2796 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2798 reg1
= XEXP (addr
, 0);
2799 addr
= XEXP (addr
, 1);
2801 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2803 reg1
= XEXP (addr
, 1);
2804 addr
= XEXP (addr
, 0);
2806 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2808 reg1
= XEXP (addr
, 0);
2809 addr
= XEXP (addr
, 1);
2811 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2813 reg1
= XEXP (addr
, 1);
2814 addr
= XEXP (addr
, 0);
2816 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2817 || GET_CODE (addr
) == SIGN_EXTEND
)
2829 #if 0 /* for OLD_INDEXING */
2830 else if (GET_CODE (addr
) == PLUS
)
2832 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2834 reg2
= XEXP (addr
, 0);
2835 addr
= XEXP (addr
, 1);
2837 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2839 reg2
= XEXP (addr
, 1);
2840 addr
= XEXP (addr
, 0);
2852 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2853 || GET_CODE (reg1
) == MULT
))
2854 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2859 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2864 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2865 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2868 if (GET_CODE (ireg
) == MULT
)
2870 scale
= INTVAL (XEXP (ireg
, 1));
2871 ireg
= XEXP (ireg
, 0);
2873 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2875 ASM_OUTPUT_CASE_FETCH (file
,
2876 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2877 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2878 fprintf (file
, "w");
2882 ASM_OUTPUT_CASE_FETCH (file
,
2883 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2884 M68K_REGNAME(REGNO (ireg
)));
2885 fprintf (file
, "l");
2888 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2892 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2893 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2895 ASM_OUTPUT_CASE_FETCH (file
,
2896 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2897 M68K_REGNAME(REGNO (breg
)));
2898 fprintf (file
, "l)");
2901 if (ireg
!= 0 || breg
!= 0)
2908 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2916 output_addr_const (file
, addr
);
2917 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2919 fprintf (file
, "@GOT");
2921 fprintf (file
, ".w");
2924 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2928 else /* !MOTOROLA */
2930 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2933 output_addr_const (file
, addr
);
2934 if (breg
== pic_offset_table_rtx
)
2938 fprintf (file
, ":w"); break;
2940 fprintf (file
, ":l"); break;
2948 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2950 scale
= INTVAL (XEXP (ireg
, 1));
2951 ireg
= XEXP (ireg
, 0);
2953 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2954 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2955 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2957 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2958 M68K_REGNAME(REGNO (ireg
)));
2960 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2964 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2965 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2967 ASM_OUTPUT_CASE_FETCH (file
,
2968 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2969 M68K_REGNAME(REGNO (reg1
)));
2970 fprintf (file
, "l)");
2973 /* FALL-THROUGH (is this really what we want?) */
2975 if (GET_CODE (addr
) == CONST_INT
2976 && INTVAL (addr
) < 0x8000
2977 && INTVAL (addr
) >= -0x8000)
2979 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2981 else if (GET_CODE (addr
) == CONST_INT
)
2983 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2985 else if (TARGET_PCREL
)
2988 output_addr_const (file
, addr
);
2990 asm_fprintf (file
, ":w,%Rpc)");
2992 asm_fprintf (file
, ":l,%Rpc)");
2996 /* Special case for SYMBOL_REF if the symbol name ends in
2997 `.<letter>', this can be mistaken as a size suffix. Put
2998 the name in parentheses. */
2999 if (GET_CODE (addr
) == SYMBOL_REF
3000 && strlen (XSTR (addr
, 0)) > 2
3001 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3004 output_addr_const (file
, addr
);
3008 output_addr_const (file
, addr
);
3014 /* Check for cases where a clr insns can be omitted from code using
3015 strict_low_part sets. For example, the second clrl here is not needed:
3016 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3018 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3019 insn we are checking for redundancy. TARGET is the register set by the
3023 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3028 p
= prev_nonnote_insn (first_insn
);
3032 /* If it isn't an insn, then give up. */
3033 if (GET_CODE (p
) != INSN
)
3036 if (reg_set_p (target
, p
))
3038 rtx set
= single_set (p
);
3041 /* If it isn't an easy to recognize insn, then give up. */
3045 dest
= SET_DEST (set
);
3047 /* If this sets the entire target register to zero, then our
3048 first_insn is redundant. */
3049 if (rtx_equal_p (dest
, target
)
3050 && SET_SRC (set
) == const0_rtx
)
3052 else if (GET_CODE (dest
) == STRICT_LOW_PART
3053 && GET_CODE (XEXP (dest
, 0)) == REG
3054 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3055 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3056 <= GET_MODE_SIZE (mode
)))
3057 /* This is a strict low part set which modifies less than
3058 we are using, so it is safe. */
3064 p
= prev_nonnote_insn (p
);
3070 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3071 range carefully since this predicate is used in DImode contexts. Also, we
3072 need some extra crud to make it work when hosted on 64-bit machines. */
3075 const_uint32_operand (rtx op
, enum machine_mode mode
)
3077 /* It doesn't make sense to ask this question with a mode that is
3078 not larger than 32 bits. */
3079 if (GET_MODE_BITSIZE (mode
) <= 32)
3082 #if HOST_BITS_PER_WIDE_INT > 32
3083 /* All allowed constants will fit a CONST_INT. */
3084 return (GET_CODE (op
) == CONST_INT
3085 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3087 return (GET_CODE (op
) == CONST_INT
3088 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3092 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3093 to check the range carefully since this predicate is used in DImode
3097 const_sint32_operand (rtx op
, enum machine_mode mode
)
3099 /* It doesn't make sense to ask this question with a mode that is
3100 not larger than 32 bits. */
3101 if (GET_MODE_BITSIZE (mode
) <= 32)
3104 /* All allowed constants will fit a CONST_INT. */
3105 return (GET_CODE (op
) == CONST_INT
3106 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3109 /* Operand predicates for implementing asymmetric pc-relative addressing
3110 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3111 when used as a source operand, but not as a destination operand.
3113 We model this by restricting the meaning of the basic predicates
3114 (general_operand, memory_operand, etc) to forbid the use of this
3115 addressing mode, and then define the following predicates that permit
3116 this addressing mode. These predicates can then be used for the
3117 source operands of the appropriate instructions.
3119 n.b. While it is theoretically possible to change all machine patterns
3120 to use this addressing more where permitted by the architecture,
3121 it has only been implemented for "common" cases: SImode, HImode, and
3122 QImode operands, and only for the principle operations that would
3123 require this addressing mode: data movement and simple integer operations.
3125 In parallel with these new predicates, two new constraint letters
3126 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3127 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3128 In the pcrel case 's' is only valid in combination with 'a' registers.
3129 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3130 of how these constraints are used.
3132 The use of these predicates is strictly optional, though patterns that
3133 don't will cause an extra reload register to be allocated where one
3136 lea (abc:w,%pc),%a0 ; need to reload address
3137 moveq &1,%d1 ; since write to pc-relative space
3138 movel %d1,%a0@ ; is not allowed
3140 lea (abc:w,%pc),%a1 ; no need to reload address here
3141 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3143 For more info, consult tiemann@cygnus.com.
3146 All of the ugliness with predicates and constraints is due to the
3147 simple fact that the m68k does not allow a pc-relative addressing
3148 mode as a destination. gcc does not distinguish between source and
3149 destination addresses. Hence, if we claim that pc-relative address
3150 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3151 end up with invalid code. To get around this problem, we left
3152 pc-relative modes as invalid addresses, and then added special
3153 predicates and constraints to accept them.
3155 A cleaner way to handle this is to modify gcc to distinguish
3156 between source and destination addresses. We can then say that
3157 pc-relative is a valid source address but not a valid destination
3158 address, and hopefully avoid a lot of the predicate and constraint
3159 hackery. Unfortunately, this would be a pretty big change. It would
3160 be a useful change for a number of ports, but there aren't any current
3161 plans to undertake this.
3163 ***************************************************************************/
3166 /* Special case of a general operand that's used as a source operand.
3167 Use this to permit reads from PC-relative memory when -mpcrel
3171 general_src_operand (rtx op
, enum machine_mode mode
)
3174 && GET_CODE (op
) == MEM
3175 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3176 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3177 || GET_CODE (XEXP (op
, 0)) == CONST
))
3179 return general_operand (op
, mode
);
3182 /* Special case of a nonimmediate operand that's used as a source.
3183 Use this to permit reads from PC-relative memory when -mpcrel
3187 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3189 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3190 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3191 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3192 || GET_CODE (XEXP (op
, 0)) == CONST
))
3194 return nonimmediate_operand (op
, mode
);
3197 /* Special case of a memory operand that's used as a source.
3198 Use this to permit reads from PC-relative memory when -mpcrel
3202 memory_src_operand (rtx op
, enum machine_mode mode
)
3204 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3205 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3206 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3207 || GET_CODE (XEXP (op
, 0)) == CONST
))
3209 return memory_operand (op
, mode
);
3212 /* Predicate that accepts only a pc-relative address. This is needed
3213 because pc-relative addresses don't satisfy the predicate
3214 "general_src_operand". */
3217 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3219 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3220 || GET_CODE (op
) == CONST
);
3224 output_andsi3 (rtx
*operands
)
3227 if (GET_CODE (operands
[2]) == CONST_INT
3228 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3229 && (DATA_REG_P (operands
[0])
3230 || offsettable_memref_p (operands
[0]))
3231 && !TARGET_COLDFIRE
)
3233 if (GET_CODE (operands
[0]) != REG
)
3234 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3235 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3236 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3238 if (operands
[2] == const0_rtx
)
3240 return "and%.w %2,%0";
3242 if (GET_CODE (operands
[2]) == CONST_INT
3243 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3244 && (DATA_REG_P (operands
[0])
3245 || offsettable_memref_p (operands
[0])))
3247 if (DATA_REG_P (operands
[0]))
3249 operands
[1] = GEN_INT (logval
);
3253 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3254 operands
[1] = GEN_INT (logval
% 8);
3256 /* This does not set condition codes in a standard way. */
3258 return "bclr %1,%0";
3260 return "and%.l %2,%0";
3264 output_iorsi3 (rtx
*operands
)
3266 register int logval
;
3267 if (GET_CODE (operands
[2]) == CONST_INT
3268 && INTVAL (operands
[2]) >> 16 == 0
3269 && (DATA_REG_P (operands
[0])
3270 || offsettable_memref_p (operands
[0]))
3271 && !TARGET_COLDFIRE
)
3273 if (GET_CODE (operands
[0]) != REG
)
3274 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3275 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3277 if (INTVAL (operands
[2]) == 0xffff)
3278 return "mov%.w %2,%0";
3279 return "or%.w %2,%0";
3281 if (GET_CODE (operands
[2]) == CONST_INT
3282 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3283 && (DATA_REG_P (operands
[0])
3284 || offsettable_memref_p (operands
[0])))
3286 if (DATA_REG_P (operands
[0]))
3287 operands
[1] = GEN_INT (logval
);
3290 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3291 operands
[1] = GEN_INT (logval
% 8);
3294 return "bset %1,%0";
3296 return "or%.l %2,%0";
3300 output_xorsi3 (rtx
*operands
)
3302 register int logval
;
3303 if (GET_CODE (operands
[2]) == CONST_INT
3304 && INTVAL (operands
[2]) >> 16 == 0
3305 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3306 && !TARGET_COLDFIRE
)
3308 if (! DATA_REG_P (operands
[0]))
3309 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3310 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3312 if (INTVAL (operands
[2]) == 0xffff)
3314 return "eor%.w %2,%0";
3316 if (GET_CODE (operands
[2]) == CONST_INT
3317 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3318 && (DATA_REG_P (operands
[0])
3319 || offsettable_memref_p (operands
[0])))
3321 if (DATA_REG_P (operands
[0]))
3322 operands
[1] = GEN_INT (logval
);
3325 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3326 operands
[1] = GEN_INT (logval
% 8);
3329 return "bchg %1,%0";
3331 return "eor%.l %2,%0";
3334 #ifdef M68K_TARGET_COFF
3336 /* Output assembly to switch to section NAME with attribute FLAGS. */
3339 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3343 if (flags
& SECTION_WRITE
)
3348 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3351 #endif /* M68K_TARGET_COFF */
3355 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3356 unsigned long labelno
)
3358 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3359 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3361 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3365 m68k_hp320_file_start (void)
3367 /* version 1: 68010.
3368 2: 68020 without FPU.
3369 3: 68020 with FPU. */
3370 fprintf (asm_out_file
, "\tversion %d\n",
3371 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3376 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3377 HOST_WIDE_INT delta
,
3378 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3384 if (delta
> 0 && delta
<= 8)
3385 asm_fprintf (file
, MOTOROLA
?
3386 "\taddq.l %I%d,4(%Rsp)\n" :
3387 "\taddql %I%d,%Rsp@(4)\n",
3389 else if (delta
< 0 && delta
>= -8)
3390 asm_fprintf (file
, MOTOROLA
?
3391 "\tsubq.l %I%d,4(%Rsp)\n" :
3392 "\tsubql %I%d,%Rsp@(4)\n",
3395 asm_fprintf (file
, MOTOROLA
?
3396 "\tadd.l %I%wd,4(%Rsp)\n" :
3397 "\taddl %I%wd,%Rsp@(4)\n",
3400 xops
[0] = DECL_RTL (function
);
3402 /* Logic taken from call patterns in m68k.md. */
3407 else if ((flag_pic
== 1) || TARGET_68020
)
3412 #elif defined(USE_GAS)
3413 fmt
= "bra.l %0@PLTPC";
3415 fmt
= "bra %0@PLTPC";
3417 else /* !MOTOROLA */
3424 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3425 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3427 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3431 #if MOTOROLA && !defined (USE_GAS)
3438 output_asm_insn (fmt
, xops
);
3441 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3444 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3445 int incoming ATTRIBUTE_UNUSED
)
3447 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);