1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* Base flags for 68k ISAs. */
205 #define FL_FOR_isa_00 FL_ISA_68000
206 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
207 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
208 generated 68881 code for 68020 and 68030 targets unless explicitly told
210 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
211 | FL_BITFIELD | FL_68881)
212 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
213 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
215 /* Base flags for ColdFire ISAs. */
216 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
217 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
218 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
219 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
220 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
224 /* Traditional 68000 instruction sets. */
230 /* ColdFire instruction set variants. */
238 /* Information about one of the -march, -mcpu or -mtune arguments. */
239 struct m68k_target_selection
241 /* The argument being described. */
244 /* For -mcpu, this is the device selected by the option.
245 For -mtune and -march, it is a representative device
246 for the microarchitecture or ISA respectively. */
247 enum target_device device
;
249 /* The M68K_DEVICE fields associated with DEVICE. See the comment
250 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
252 enum uarch_type microarch
;
257 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
258 static const struct m68k_target_selection all_devices
[] =
260 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
261 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
262 #include "m68k-devices.def"
264 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
267 /* A list of all ISAs, mapping each one to a representative device.
268 Used for -march selection. */
269 static const struct m68k_target_selection all_isas
[] =
271 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
272 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
273 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
274 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
275 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
276 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
277 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
278 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
280 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
282 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
283 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
286 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
289 /* A list of all microarchitectures, mapping each one to a representative
290 device. Used for -mtune selection. */
291 static const struct m68k_target_selection all_microarchs
[] =
293 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
294 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
295 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
296 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
297 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
298 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
299 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
300 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
301 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
302 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
303 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
305 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
310 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
313 /* The entries associated with the -mcpu, -march and -mtune settings,
314 or null for options that have not been used. */
315 const struct m68k_target_selection
*m68k_cpu_entry
;
316 const struct m68k_target_selection
*m68k_arch_entry
;
317 const struct m68k_target_selection
*m68k_tune_entry
;
319 /* Which CPU we are generating code for. */
320 enum target_device m68k_cpu
;
322 /* Which microarchitecture to tune for. */
323 enum uarch_type m68k_tune
;
325 /* Which FPU to use. */
326 enum fpu_type m68k_fpu
;
328 /* The set of FL_* flags that apply to the target processor. */
329 unsigned int m68k_cpu_flags
;
331 /* Asm templates for calling or jumping to an arbitrary symbolic address,
332 or NULL if such calls or jumps are not supported. The address is held
334 const char *m68k_symbolic_call
;
335 const char *m68k_symbolic_jump
;
337 /* See whether TABLE has an entry with name NAME. Return true and
338 store the entry in *ENTRY if so, otherwise return false and
339 leave *ENTRY alone. */
342 m68k_find_selection (const struct m68k_target_selection
**entry
,
343 const struct m68k_target_selection
*table
,
348 for (i
= 0; table
[i
].name
; i
++)
349 if (strcmp (table
[i
].name
, name
) == 0)
357 /* Implement TARGET_HANDLE_OPTION. */
360 m68k_handle_option (size_t code
, const char *arg
, int value
)
365 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
368 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
371 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
374 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
377 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
380 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
383 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
386 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
389 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
393 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
396 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
400 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
403 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
405 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
408 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
410 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
419 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
422 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
426 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
428 case OPT_mshared_library_id_
:
429 if (value
> MAX_LIBRARY_ID
)
430 error ("-mshared-library-id=%s is not between 0 and %d",
431 arg
, MAX_LIBRARY_ID
);
433 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
441 /* Sometimes certain combinations of command options do not make
442 sense on a particular target machine. You can define a macro
443 `OVERRIDE_OPTIONS' to take account of this. This macro, if
444 defined, is executed once just after all the command options have
447 Don't use this macro to turn on various extra optimizations for
448 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
451 override_options (void)
453 const struct m68k_target_selection
*entry
;
454 unsigned long target_mask
;
462 -march=ARCH should generate code that runs any processor
463 implementing architecture ARCH. -mcpu=CPU should override -march
464 and should generate code that runs on processor CPU, making free
465 use of any instructions that CPU understands. -mtune=UARCH applies
466 on top of -mcpu or -march and optimises the code for UARCH. It does
467 not change the target architecture. */
470 /* Complain if the -march setting is for a different microarchitecture,
471 or includes flags that the -mcpu setting doesn't. */
473 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
474 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
475 warning (0, "-mcpu=%s conflicts with -march=%s",
476 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
478 entry
= m68k_cpu_entry
;
481 entry
= m68k_arch_entry
;
484 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
486 m68k_cpu_flags
= entry
->flags
;
488 /* Use the architecture setting to derive default values for
491 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
492 target_mask
|= MASK_BITFIELD
;
493 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
494 target_mask
|= MASK_CF_HWDIV
;
495 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
496 target_mask
|= MASK_HARD_FLOAT
;
497 target_flags
|= target_mask
& ~target_flags_explicit
;
499 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
500 m68k_cpu
= entry
->device
;
502 m68k_tune
= m68k_tune_entry
->microarch
;
503 #ifdef M68K_DEFAULT_TUNE
504 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
505 m68k_tune
= M68K_DEFAULT_TUNE
;
508 m68k_tune
= entry
->microarch
;
510 /* Set the type of FPU. */
511 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
512 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
515 if (TARGET_COLDFIRE_FPU
)
517 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
518 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
521 /* Sanity check to ensure that msep-data and mid-sahred-library are not
522 * both specified together. Doing so simply doesn't make sense.
524 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
525 error ("cannot specify both -msep-data and -mid-shared-library");
527 /* If we're generating code for a separate A5 relative data segment,
528 * we've got to enable -fPIC as well. This might be relaxable to
529 * -fpic but it hasn't been tested properly.
531 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
534 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
535 error if the target does not support them. */
536 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
537 error ("-mpcrel -fPIC is not currently supported on selected cpu");
539 /* ??? A historic way of turning on pic, or is this intended to
540 be an embedded thing that doesn't have the same name binding
541 significance that it does on hosted ELF systems? */
542 if (TARGET_PCREL
&& flag_pic
== 0)
547 #if MOTOROLA && !defined (USE_GAS)
548 m68k_symbolic_call
= "jsr %a0";
549 m68k_symbolic_jump
= "jmp %a0";
551 m68k_symbolic_call
= "jbsr %a0";
552 m68k_symbolic_jump
= "jra %a0";
555 else if (TARGET_ID_SHARED_LIBRARY
)
556 /* All addresses must be loaded from the GOT. */
558 else if (TARGET_68020
|| TARGET_ISAB
)
562 m68k_symbolic_call
= "bsr.l %c0";
563 m68k_symbolic_jump
= "bra.l %c0";
568 m68k_symbolic_call
= "bsr.l %p0";
569 m68k_symbolic_jump
= "bra.l %p0";
571 m68k_symbolic_call
= "bsr %p0";
572 m68k_symbolic_jump
= "bra %p0";
575 /* Turn off function cse if we are doing PIC. We always want
576 function call to be done as `bsr foo@PLTPC'. */
577 /* ??? It's traditional to do this for -mpcrel too, but it isn't
578 clear how intentional that is. */
579 flag_no_function_cse
= 1;
582 SUBTARGET_OVERRIDE_OPTIONS
;
585 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
586 given argument and NAME is the argument passed to -mcpu. Return NULL
587 if -mcpu was not passed. */
590 m68k_cpp_cpu_ident (const char *prefix
)
594 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
597 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
598 given argument and NAME is the name of the representative device for
599 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
602 m68k_cpp_cpu_family (const char *prefix
)
606 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
609 /* Return nonzero if FUNC is an interrupt function as specified by the
610 "interrupt_handler" attribute. */
612 m68k_interrupt_function_p(tree func
)
616 if (TREE_CODE (func
) != FUNCTION_DECL
)
619 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
620 return (a
!= NULL_TREE
);
623 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
624 struct attribute_spec.handler. */
626 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
627 tree args ATTRIBUTE_UNUSED
,
628 int flags ATTRIBUTE_UNUSED
,
631 if (TREE_CODE (*node
) != FUNCTION_DECL
)
633 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
634 IDENTIFIER_POINTER (name
));
635 *no_add_attrs
= true;
642 m68k_compute_frame_layout (void)
645 unsigned int mask
, rmask
;
646 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
648 /* Only compute the frame once per function.
649 Don't cache information until reload has been completed. */
650 if (current_frame
.funcdef_no
== current_function_funcdef_no
654 current_frame
.size
= (get_frame_size () + 3) & -4;
656 mask
= rmask
= saved
= 0;
657 for (regno
= 0; regno
< 16; regno
++)
658 if (m68k_save_reg (regno
, interrupt_handler
))
661 rmask
|= 1 << (15 - regno
);
664 current_frame
.offset
= saved
* 4;
665 current_frame
.reg_no
= saved
;
666 current_frame
.reg_mask
= mask
;
667 current_frame
.reg_rev_mask
= rmask
;
669 current_frame
.foffset
= 0;
670 mask
= rmask
= saved
= 0;
671 if (TARGET_HARD_FLOAT
)
673 for (regno
= 16; regno
< 24; regno
++)
674 if (m68k_save_reg (regno
, interrupt_handler
))
676 mask
|= 1 << (regno
- 16);
677 rmask
|= 1 << (23 - regno
);
680 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
681 current_frame
.offset
+= current_frame
.foffset
;
683 current_frame
.fpu_no
= saved
;
684 current_frame
.fpu_mask
= mask
;
685 current_frame
.fpu_rev_mask
= rmask
;
687 /* Remember what function this frame refers to. */
688 current_frame
.funcdef_no
= current_function_funcdef_no
;
692 m68k_initial_elimination_offset (int from
, int to
)
695 /* The arg pointer points 8 bytes before the start of the arguments,
696 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
697 frame pointer in most frames. */
698 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
699 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
700 return argptr_offset
;
702 m68k_compute_frame_layout ();
704 gcc_assert (to
== STACK_POINTER_REGNUM
);
707 case ARG_POINTER_REGNUM
:
708 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
709 case FRAME_POINTER_REGNUM
:
710 return current_frame
.offset
+ current_frame
.size
;
716 /* Refer to the array `regs_ever_live' to determine which registers
717 to save; `regs_ever_live[I]' is nonzero if register number I
718 is ever used in the function. This function is responsible for
719 knowing which registers should not be saved even if used.
720 Return true if we need to save REGNO. */
723 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
725 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
727 if (current_function_uses_pic_offset_table
)
729 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
733 if (current_function_calls_eh_return
)
738 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
739 if (test
== INVALID_REGNUM
)
746 /* Fixed regs we never touch. */
747 if (fixed_regs
[regno
])
750 /* The frame pointer (if it is such) is handled specially. */
751 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
754 /* Interrupt handlers must also save call_used_regs
755 if they are live or when calling nested functions. */
756 if (interrupt_handler
)
758 if (regs_ever_live
[regno
])
761 if (!current_function_is_leaf
&& call_used_regs
[regno
])
765 /* Never need to save registers that aren't touched. */
766 if (!regs_ever_live
[regno
])
769 /* Otherwise save everything that isn't call-clobbered. */
770 return !call_used_regs
[regno
];
773 /* This function generates the assembly code for function entry.
774 STREAM is a stdio stream to output the code to.
775 SIZE is an int: how many units of temporary storage to allocate. */
778 m68k_output_function_prologue (FILE *stream
,
779 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
781 HOST_WIDE_INT fsize_with_regs
;
782 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
784 m68k_compute_frame_layout();
786 /* If the stack limit is a symbol, we can check it here,
787 before actually allocating the space. */
788 if (current_function_limit_stack
789 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
790 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
791 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
793 /* On ColdFire add register save into initial stack frame setup, if possible. */
794 fsize_with_regs
= current_frame
.size
;
797 if (current_frame
.reg_no
> 2)
798 fsize_with_regs
+= current_frame
.reg_no
* 4;
799 if (current_frame
.fpu_no
)
800 fsize_with_regs
+= current_frame
.fpu_no
* 8;
803 if (frame_pointer_needed
)
805 if (current_frame
.size
== 0 && TUNE_68040
)
806 /* on the 68040, pea + move is faster than link.w 0 */
807 fprintf (stream
, (MOTOROLA
808 ? "\tpea (%s)\n\tmove.l %s,%s\n"
809 : "\tpea %s@\n\tmovel %s,%s\n"),
810 M68K_REGNAME (FRAME_POINTER_REGNUM
),
811 M68K_REGNAME (STACK_POINTER_REGNUM
),
812 M68K_REGNAME (FRAME_POINTER_REGNUM
));
813 else if (fsize_with_regs
< 0x8000)
814 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
815 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
816 else if (TARGET_68020
)
817 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
818 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
820 /* Adding negative number is faster on the 68040. */
822 "\tlink" ASM_DOTW
" %s,%I0\n"
823 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
824 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
826 else if (fsize_with_regs
) /* !frame_pointer_needed */
828 if (fsize_with_regs
< 0x8000)
830 if (fsize_with_regs
<= 8)
832 if (!TARGET_COLDFIRE
)
833 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
836 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
839 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
840 /* On the CPU32 it is faster to use two subqw instructions to
841 subtract a small integer (8 < N <= 16) to a register. */
843 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
844 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
845 fsize_with_regs
- 8);
847 /* Adding negative number is faster on the 68040. */
848 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
851 asm_fprintf (stream
, (MOTOROLA
852 ? "\tlea (%wd,%Rsp),%Rsp\n"
853 : "\tlea %Rsp@(%wd),%Rsp\n"),
856 else /* fsize_with_regs >= 0x8000 */
857 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
859 } /* !frame_pointer_needed */
861 if (dwarf2out_do_frame ())
863 if (frame_pointer_needed
)
866 l
= (char *) dwarf2out_cfi_label ();
868 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
869 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
870 cfa_offset
+= current_frame
.size
;
874 cfa_offset
+= current_frame
.size
;
875 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
879 if (current_frame
.fpu_mask
)
883 asm_fprintf (stream
, (MOTOROLA
884 ? "\tfmovm %I0x%x,-(%Rsp)\n"
885 : "\tfmovem %I0x%x,%Rsp@-\n"),
886 current_frame
.fpu_mask
);
892 /* stack already has registers in it. Find the offset from
893 the bottom of stack to where the FP registers go */
894 if (current_frame
.reg_no
<= 2)
897 offset
= current_frame
.reg_no
* 4;
900 "\tfmovem %I0x%x,%d(%Rsp)\n",
901 current_frame
.fpu_rev_mask
,
905 "\tfmovem %I0x%x,(%Rsp)\n",
906 current_frame
.fpu_rev_mask
);
909 if (dwarf2out_do_frame ())
911 char *l
= (char *) dwarf2out_cfi_label ();
914 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
915 if (! frame_pointer_needed
)
916 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
917 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
918 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
919 dwarf2out_reg_save (l
, regno
, -cfa_offset
920 + n_regs
++ * TARGET_FP_REG_SIZE
);
924 /* If the stack limit is not a symbol, check it here.
925 This has the disadvantage that it may be too late... */
926 if (current_function_limit_stack
)
928 if (REG_P (stack_limit_rtx
))
929 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
930 M68K_REGNAME (REGNO (stack_limit_rtx
)));
931 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
932 warning (0, "stack limit expression is not supported");
935 if (current_frame
.reg_no
<= 2)
937 /* Store each separately in the same order moveml uses.
938 Using two movel instructions instead of a single moveml
939 is about 15% faster for the 68020 and 68030 at no expense
944 for (i
= 0; i
< 16; i
++)
945 if (current_frame
.reg_rev_mask
& (1 << i
))
947 asm_fprintf (stream
, (MOTOROLA
948 ? "\t%Omove.l %s,-(%Rsp)\n"
949 : "\tmovel %s,%Rsp@-\n"),
950 M68K_REGNAME (15 - i
));
951 if (dwarf2out_do_frame ())
953 char *l
= (char *) dwarf2out_cfi_label ();
956 if (! frame_pointer_needed
)
957 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
958 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
962 else if (current_frame
.reg_rev_mask
)
965 /* The ColdFire does not support the predecrement form of the
966 MOVEM instruction, so we must adjust the stack pointer and
967 then use the plain address register indirect mode.
968 The required register save space was combined earlier with
969 the fsize_with_regs amount. */
971 asm_fprintf (stream
, (MOTOROLA
972 ? "\tmovm.l %I0x%x,(%Rsp)\n"
973 : "\tmoveml %I0x%x,%Rsp@\n"),
974 current_frame
.reg_mask
);
976 asm_fprintf (stream
, (MOTOROLA
977 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
978 : "\tmoveml %I0x%x,%Rsp@-\n"),
979 current_frame
.reg_rev_mask
);
980 if (dwarf2out_do_frame ())
982 char *l
= (char *) dwarf2out_cfi_label ();
985 cfa_offset
+= current_frame
.reg_no
* 4;
986 if (! frame_pointer_needed
)
987 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
988 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
989 if (current_frame
.reg_mask
& (1 << regno
))
990 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
993 if (!TARGET_SEP_DATA
&& flag_pic
994 && (current_function_uses_pic_offset_table
995 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
997 if (TARGET_ID_SHARED_LIBRARY
)
999 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
1000 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1001 m68k_library_id_string
,
1002 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1007 asm_fprintf (stream
,
1008 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
1009 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1012 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
1013 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1014 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
1015 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1016 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1022 /* Return true if a simple (return) instruction is sufficient for this
1023 instruction (i.e. if no epilogue is needed). */
1026 m68k_use_return_insn (void)
1028 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1031 m68k_compute_frame_layout ();
1032 return current_frame
.offset
== 0;
1035 /* This function generates the assembly code for function exit,
1036 on machines that need it.
1038 The function epilogue should not depend on the current stack pointer!
1039 It should use the frame pointer only, if there is a frame pointer.
1040 This is mandatory because of alloca; we also take advantage of it to
1041 omit stack adjustments before returning. */
1044 m68k_output_function_epilogue (FILE *stream
,
1045 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1047 HOST_WIDE_INT fsize
, fsize_with_regs
;
1049 bool restore_from_sp
= false;
1050 rtx insn
= get_last_insn ();
1052 m68k_compute_frame_layout ();
1054 /* If the last insn was a BARRIER, we don't have to write any code. */
1055 if (GET_CODE (insn
) == NOTE
)
1056 insn
= prev_nonnote_insn (insn
);
1057 if (insn
&& GET_CODE (insn
) == BARRIER
)
1059 /* Output just a no-op so that debuggers don't get confused
1060 about which function the pc is in at this address. */
1061 fprintf (stream
, "\tnop\n");
1065 #ifdef FUNCTION_EXTRA_EPILOGUE
1066 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
1069 fsize
= current_frame
.size
;
1071 /* FIXME: leaf_function_p below is too strong.
1072 What we really need to know there is if there could be pending
1073 stack adjustment needed at that point. */
1075 = (! frame_pointer_needed
1076 || (! current_function_calls_alloca
&& leaf_function_p ()));
1078 /* fsize_with_regs is the size we need to adjust the sp when
1079 popping the frame. */
1080 fsize_with_regs
= fsize
;
1082 /* Because the ColdFire doesn't support moveml with
1083 complex address modes, we must adjust the stack manually
1084 after restoring registers. When the frame pointer isn't used,
1085 we can merge movem adjustment into frame unlinking
1086 made immediately after it. */
1087 if (TARGET_COLDFIRE
&& restore_from_sp
)
1089 if (current_frame
.reg_no
> 2)
1090 fsize_with_regs
+= current_frame
.reg_no
* 4;
1091 if (current_frame
.fpu_no
)
1092 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1095 if (current_frame
.offset
+ fsize
>= 0x8000
1096 && ! restore_from_sp
1097 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1099 /* Because the ColdFire doesn't support moveml with
1100 complex address modes we make an extra correction here. */
1101 if (TARGET_COLDFIRE
)
1102 fsize
+= current_frame
.offset
;
1104 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1105 fsize
= 0, big
= true;
1107 if (current_frame
.reg_no
<= 2)
1109 /* Restore each separately in the same order moveml does.
1110 Using two movel instructions instead of a single moveml
1111 is about 15% faster for the 68020 and 68030 at no expense
1115 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1117 for (i
= 0; i
< 16; i
++)
1118 if (current_frame
.reg_mask
& (1 << i
))
1123 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1125 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1128 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1129 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1133 else if (restore_from_sp
)
1134 asm_fprintf (stream
, (MOTOROLA
1135 ? "\t%Omove.l (%Rsp)+,%s\n"
1136 : "\tmovel %Rsp@+,%s\n"),
1141 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1143 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1146 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1147 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1154 else if (current_frame
.reg_mask
)
1156 /* The ColdFire requires special handling due to its limited moveml
1158 if (TARGET_COLDFIRE
)
1162 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1163 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1164 asm_fprintf (stream
, (MOTOROLA
1165 ? "\tmovm.l (%Ra1),%I0x%x\n"
1166 : "\tmoveml %Ra1@,%I0x%x\n"),
1167 current_frame
.reg_mask
);
1169 else if (restore_from_sp
)
1170 asm_fprintf (stream
, (MOTOROLA
1171 ? "\tmovm.l (%Rsp),%I0x%x\n"
1172 : "\tmoveml %Rsp@,%I0x%x\n"),
1173 current_frame
.reg_mask
);
1177 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1178 current_frame
.offset
+ fsize
,
1179 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1180 current_frame
.reg_mask
);
1182 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1183 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1184 current_frame
.offset
+ fsize
,
1185 current_frame
.reg_mask
);
1188 else /* !TARGET_COLDFIRE */
1193 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1194 current_frame
.offset
+ fsize
,
1195 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1196 current_frame
.reg_mask
);
1198 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1199 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1200 current_frame
.offset
+ fsize
,
1201 current_frame
.reg_mask
);
1203 else if (restore_from_sp
)
1205 asm_fprintf (stream
, (MOTOROLA
1206 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1207 : "\tmoveml %Rsp@+,%I0x%x\n"),
1208 current_frame
.reg_mask
);
1213 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1214 current_frame
.offset
+ fsize
,
1215 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1216 current_frame
.reg_mask
);
1218 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1219 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1220 current_frame
.offset
+ fsize
,
1221 current_frame
.reg_mask
);
1225 if (current_frame
.fpu_rev_mask
)
1229 if (TARGET_COLDFIRE
)
1231 if (current_frame
.reg_no
)
1232 asm_fprintf (stream
, MOTOROLA
?
1233 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1234 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1235 current_frame
.reg_no
* 4,
1236 current_frame
.fpu_rev_mask
);
1238 asm_fprintf (stream
, MOTOROLA
?
1239 "\tfmovem.d (%Ra1),%I0x%x\n" :
1240 "\tfmovmd (%Ra1),%I0x%x\n",
1241 current_frame
.fpu_rev_mask
);
1244 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1245 current_frame
.foffset
+ fsize
,
1246 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1247 current_frame
.fpu_rev_mask
);
1249 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1250 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1251 current_frame
.foffset
+ fsize
,
1252 current_frame
.fpu_rev_mask
);
1254 else if (restore_from_sp
)
1256 if (TARGET_COLDFIRE
)
1260 /* Stack already has registers in it. Find the offset from
1261 the bottom of stack to where the FP registers go. */
1262 if (current_frame
.reg_no
<= 2)
1265 offset
= current_frame
.reg_no
* 4;
1267 asm_fprintf (stream
,
1268 "\tfmovem %Rsp@(%d), %I0x%x\n",
1269 offset
, current_frame
.fpu_rev_mask
);
1271 asm_fprintf (stream
,
1272 "\tfmovem %Rsp@, %I0x%x\n",
1273 current_frame
.fpu_rev_mask
);
1276 asm_fprintf (stream
, MOTOROLA
?
1277 "\tfmovm (%Rsp)+,%I0x%x\n" :
1278 "\tfmovem %Rsp@+,%I0x%x\n",
1279 current_frame
.fpu_rev_mask
);
1283 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1284 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1285 current_frame
.foffset
+ fsize
,
1286 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1287 current_frame
.fpu_rev_mask
);
1289 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1290 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1291 current_frame
.foffset
+ fsize
,
1292 current_frame
.fpu_rev_mask
);
1295 if (frame_pointer_needed
)
1296 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1297 else if (fsize_with_regs
)
1299 if (fsize_with_regs
<= 8)
1301 if (!TARGET_COLDFIRE
)
1302 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1305 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1308 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1310 /* On the CPU32 it is faster to use two addqw instructions to
1311 add a small integer (8 < N <= 16) to a register. */
1312 asm_fprintf (stream
,
1313 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1314 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1315 fsize_with_regs
- 8);
1317 else if (fsize_with_regs
< 0x8000)
1320 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1323 asm_fprintf (stream
, (MOTOROLA
1324 ? "\tlea (%wd,%Rsp),%Rsp\n"
1325 : "\tlea %Rsp@(%wd),%Rsp\n"),
1329 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1331 if (current_function_calls_eh_return
)
1332 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1333 if (m68k_interrupt_function_p (current_function_decl
))
1334 fprintf (stream
, "\trte\n");
1335 else if (current_function_pops_args
)
1336 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1338 fprintf (stream
, "\trts\n");
1341 /* Return true if X is a valid comparison operator for the dbcc
1344 Note it rejects floating point comparison operators.
1345 (In the future we could use Fdbcc).
1347 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1350 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1352 switch (GET_CODE (x
))
1354 case EQ
: case NE
: case GTU
: case LTU
:
1358 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1360 case GT
: case LT
: case GE
: case LE
:
1361 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1367 /* Return nonzero if flags are currently in the 68881 flag register. */
1369 flags_in_68881 (void)
1371 /* We could add support for these in the future */
1372 return cc_status
.flags
& CC_IN_68881
;
1375 /* Convert X to a legitimate function call memory reference and return the
1379 m68k_legitimize_call_address (rtx x
)
1381 gcc_assert (MEM_P (x
));
1382 if (call_operand (XEXP (x
, 0), VOIDmode
))
1384 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1387 /* Output a dbCC; jCC sequence. Note we do not handle the
1388 floating point version of this sequence (Fdbcc). We also
1389 do not handle alternative conditions when CC_NO_OVERFLOW is
1390 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1391 kick those out before we get here. */
1394 output_dbcc_and_branch (rtx
*operands
)
1396 switch (GET_CODE (operands
[3]))
1399 output_asm_insn (MOTOROLA
1400 ? "dbeq %0,%l1\n\tjbeq %l2"
1401 : "dbeq %0,%l1\n\tjeq %l2",
1406 output_asm_insn (MOTOROLA
1407 ? "dbne %0,%l1\n\tjbne %l2"
1408 : "dbne %0,%l1\n\tjne %l2",
1413 output_asm_insn (MOTOROLA
1414 ? "dbgt %0,%l1\n\tjbgt %l2"
1415 : "dbgt %0,%l1\n\tjgt %l2",
1420 output_asm_insn (MOTOROLA
1421 ? "dbhi %0,%l1\n\tjbhi %l2"
1422 : "dbhi %0,%l1\n\tjhi %l2",
1427 output_asm_insn (MOTOROLA
1428 ? "dblt %0,%l1\n\tjblt %l2"
1429 : "dblt %0,%l1\n\tjlt %l2",
1434 output_asm_insn (MOTOROLA
1435 ? "dbcs %0,%l1\n\tjbcs %l2"
1436 : "dbcs %0,%l1\n\tjcs %l2",
1441 output_asm_insn (MOTOROLA
1442 ? "dbge %0,%l1\n\tjbge %l2"
1443 : "dbge %0,%l1\n\tjge %l2",
1448 output_asm_insn (MOTOROLA
1449 ? "dbcc %0,%l1\n\tjbcc %l2"
1450 : "dbcc %0,%l1\n\tjcc %l2",
1455 output_asm_insn (MOTOROLA
1456 ? "dble %0,%l1\n\tjble %l2"
1457 : "dble %0,%l1\n\tjle %l2",
1462 output_asm_insn (MOTOROLA
1463 ? "dbls %0,%l1\n\tjbls %l2"
1464 : "dbls %0,%l1\n\tjls %l2",
1472 /* If the decrement is to be done in SImode, then we have
1473 to compensate for the fact that dbcc decrements in HImode. */
1474 switch (GET_MODE (operands
[0]))
1477 output_asm_insn (MOTOROLA
1478 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1479 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1492 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1495 enum rtx_code op_code
= GET_CODE (op
);
1497 /* This does not produce a useful cc. */
1500 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1501 below. Swap the operands and change the op if these requirements
1502 are not fulfilled. */
1503 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1507 operand1
= operand2
;
1509 op_code
= swap_condition (op_code
);
1511 loperands
[0] = operand1
;
1512 if (GET_CODE (operand1
) == REG
)
1513 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1515 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1516 if (operand2
!= const0_rtx
)
1518 loperands
[2] = operand2
;
1519 if (GET_CODE (operand2
) == REG
)
1520 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1522 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1524 loperands
[4] = gen_label_rtx ();
1525 if (operand2
!= const0_rtx
)
1527 output_asm_insn (MOTOROLA
1528 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1529 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1534 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1535 output_asm_insn ("tst%.l %0", loperands
);
1537 output_asm_insn ("cmp%.w #0,%0", loperands
);
1539 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1541 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1542 output_asm_insn ("tst%.l %1", loperands
);
1544 output_asm_insn ("cmp%.w #0,%1", loperands
);
1547 loperands
[5] = dest
;
1552 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1553 CODE_LABEL_NUMBER (loperands
[4]));
1554 output_asm_insn ("seq %5", loperands
);
1558 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1559 CODE_LABEL_NUMBER (loperands
[4]));
1560 output_asm_insn ("sne %5", loperands
);
1564 loperands
[6] = gen_label_rtx ();
1565 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1567 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1568 CODE_LABEL_NUMBER (loperands
[4]));
1569 output_asm_insn ("sgt %5", loperands
);
1570 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1571 CODE_LABEL_NUMBER (loperands
[6]));
1575 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1576 CODE_LABEL_NUMBER (loperands
[4]));
1577 output_asm_insn ("shi %5", loperands
);
1581 loperands
[6] = gen_label_rtx ();
1582 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1584 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1585 CODE_LABEL_NUMBER (loperands
[4]));
1586 output_asm_insn ("slt %5", loperands
);
1587 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1588 CODE_LABEL_NUMBER (loperands
[6]));
1592 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1593 CODE_LABEL_NUMBER (loperands
[4]));
1594 output_asm_insn ("scs %5", loperands
);
1598 loperands
[6] = gen_label_rtx ();
1599 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1601 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1602 CODE_LABEL_NUMBER (loperands
[4]));
1603 output_asm_insn ("sge %5", loperands
);
1604 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1605 CODE_LABEL_NUMBER (loperands
[6]));
1609 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1610 CODE_LABEL_NUMBER (loperands
[4]));
1611 output_asm_insn ("scc %5", loperands
);
1615 loperands
[6] = gen_label_rtx ();
1616 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1618 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1619 CODE_LABEL_NUMBER (loperands
[4]));
1620 output_asm_insn ("sle %5", loperands
);
1621 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1622 CODE_LABEL_NUMBER (loperands
[6]));
1626 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1627 CODE_LABEL_NUMBER (loperands
[4]));
1628 output_asm_insn ("sls %5", loperands
);
1638 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1640 operands
[0] = countop
;
1641 operands
[1] = dataop
;
1643 if (GET_CODE (countop
) == CONST_INT
)
1645 register int count
= INTVAL (countop
);
1646 /* If COUNT is bigger than size of storage unit in use,
1647 advance to the containing unit of same size. */
1648 if (count
> signpos
)
1650 int offset
= (count
& ~signpos
) / 8;
1651 count
= count
& signpos
;
1652 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1654 if (count
== signpos
)
1655 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1657 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1659 /* These three statements used to use next_insns_test_no...
1660 but it appears that this should do the same job. */
1662 && next_insn_tests_no_inequality (insn
))
1665 && next_insn_tests_no_inequality (insn
))
1668 && next_insn_tests_no_inequality (insn
))
1671 cc_status
.flags
= CC_NOT_NEGATIVE
;
1673 return "btst %0,%1";
1676 /* Legitimize PIC addresses. If the address is already
1677 position-independent, we return ORIG. Newly generated
1678 position-independent addresses go to REG. If we need more
1679 than one register, we lose.
1681 An address is legitimized by making an indirect reference
1682 through the Global Offset Table with the name of the symbol
1685 The assembler and linker are responsible for placing the
1686 address of the symbol in the GOT. The function prologue
1687 is responsible for initializing a5 to the starting address
1690 The assembler is also responsible for translating a symbol name
1691 into a constant displacement from the start of the GOT.
1693 A quick example may make things a little clearer:
1695 When not generating PIC code to store the value 12345 into _foo
1696 we would generate the following code:
1700 When generating PIC two transformations are made. First, the compiler
1701 loads the address of foo into a register. So the first transformation makes:
1706 The code in movsi will intercept the lea instruction and call this
1707 routine which will transform the instructions into:
1709 movel a5@(_foo:w), a0
1713 That (in a nutshell) is how *all* symbol and label references are
1717 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1722 /* First handle a simple SYMBOL_REF or LABEL_REF */
1723 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1727 pic_ref
= gen_rtx_MEM (Pmode
,
1728 gen_rtx_PLUS (Pmode
,
1729 pic_offset_table_rtx
, orig
));
1730 current_function_uses_pic_offset_table
= 1;
1731 MEM_READONLY_P (pic_ref
) = 1;
1732 emit_move_insn (reg
, pic_ref
);
1735 else if (GET_CODE (orig
) == CONST
)
1739 /* Make sure this has not already been legitimized. */
1740 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1741 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1746 /* legitimize both operands of the PLUS */
1747 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1749 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1750 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1751 base
== reg
? 0 : reg
);
1753 if (GET_CODE (orig
) == CONST_INT
)
1754 return plus_constant (base
, INTVAL (orig
));
1755 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1756 /* Likewise, should we set special REG_NOTEs here? */
1762 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1764 static CONST_METHOD
const_method (rtx
);
1766 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1769 const_method (rtx constant
)
1774 i
= INTVAL (constant
);
1778 /* The ColdFire doesn't have byte or word operations. */
1779 /* FIXME: This may not be useful for the m68060 either. */
1780 if (!TARGET_COLDFIRE
)
1782 /* if -256 < N < 256 but N is not in range for a moveq
1783 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1784 if (USE_MOVQ (i
^ 0xff))
1786 /* Likewise, try with not.w */
1787 if (USE_MOVQ (i
^ 0xffff))
1789 /* This is the only value where neg.w is useful */
1794 /* Try also with swap. */
1796 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1801 /* Try using MVZ/MVS with an immediate value to load constants. */
1802 if (i
>= 0 && i
<= 65535)
1804 if (i
>= -32768 && i
<= 32767)
1808 /* Otherwise, use move.l */
1813 const_int_cost (rtx constant
)
1815 switch (const_method (constant
))
1818 /* Constants between -128 and 127 are cheap due to moveq. */
1826 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1836 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1841 /* Constant zero is super cheap due to clr instruction. */
1842 if (x
== const0_rtx
)
1845 *total
= const_int_cost (x
);
1855 /* Make 0.0 cheaper than other floating constants to
1856 encourage creating tstsf and tstdf insns. */
1857 if (outer_code
== COMPARE
1858 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1864 /* These are vaguely right for a 68020. */
1865 /* The costs for long multiply have been adjusted to work properly
1866 in synth_mult on the 68020, relative to an average of the time
1867 for add and the time for shift, taking away a little more because
1868 sometimes move insns are needed. */
1869 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1875 : TARGET_COLDFIRE ? 3 : 13)
1880 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1881 : TARGET_COLDFIRE ? 2 : 8)
1884 (TARGET_CF_HWDIV ? 11 \
1885 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1888 /* An lea costs about three times as much as a simple add. */
1889 if (GET_MODE (x
) == SImode
1890 && GET_CODE (XEXP (x
, 1)) == REG
1891 && GET_CODE (XEXP (x
, 0)) == MULT
1892 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1893 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1894 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1895 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1896 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1898 /* lea an@(dx:l:i),am */
1899 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1909 *total
= COSTS_N_INSNS(1);
1914 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1916 if (INTVAL (XEXP (x
, 1)) < 16)
1917 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1919 /* We're using clrw + swap for these cases. */
1920 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1923 *total
= COSTS_N_INSNS (10); /* Worst case. */
1926 /* A shift by a big integer takes an extra instruction. */
1927 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1928 && (INTVAL (XEXP (x
, 1)) == 16))
1930 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1933 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1934 && !(INTVAL (XEXP (x
, 1)) > 0
1935 && INTVAL (XEXP (x
, 1)) <= 8))
1937 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1943 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1944 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1945 && GET_MODE (x
) == SImode
)
1946 *total
= COSTS_N_INSNS (MULW_COST
);
1947 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1948 *total
= COSTS_N_INSNS (MULW_COST
);
1950 *total
= COSTS_N_INSNS (MULL_COST
);
1957 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1958 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1959 else if (TARGET_CF_HWDIV
)
1960 *total
= COSTS_N_INSNS (18);
1962 *total
= COSTS_N_INSNS (43); /* div.l */
1971 output_move_const_into_data_reg (rtx
*operands
)
1975 i
= INTVAL (operands
[1]);
1976 switch (const_method (operands
[1]))
1979 return "mvzw %1,%0";
1981 return "mvsw %1,%0";
1983 return "moveq %1,%0";
1986 operands
[1] = GEN_INT (i
^ 0xff);
1987 return "moveq %1,%0\n\tnot%.b %0";
1990 operands
[1] = GEN_INT (i
^ 0xffff);
1991 return "moveq %1,%0\n\tnot%.w %0";
1994 return "moveq #-128,%0\n\tneg%.w %0";
1999 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2000 return "moveq %1,%0\n\tswap %0";
2003 return "move%.l %1,%0";
2009 /* Return 1 if 'constant' can be represented by
2010 mov3q on a ColdFire V4 core. */
2012 valid_mov3q_const (rtx constant
)
2016 if (TARGET_ISAB
&& GET_CODE (constant
) == CONST_INT
)
2018 i
= INTVAL (constant
);
2019 if (i
== -1 || (i
>= 1 && i
<= 7))
2027 output_move_simode_const (rtx
*operands
)
2029 if (operands
[1] == const0_rtx
2030 && (DATA_REG_P (operands
[0])
2031 || GET_CODE (operands
[0]) == MEM
)
2032 /* clr insns on 68000 read before writing. */
2033 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2034 || !(GET_CODE (operands
[0]) == MEM
2035 && MEM_VOLATILE_P (operands
[0]))))
2037 else if ((GET_MODE (operands
[0]) == SImode
)
2038 && valid_mov3q_const (operands
[1]))
2039 return "mov3q%.l %1,%0";
2040 else if (operands
[1] == const0_rtx
2041 && ADDRESS_REG_P (operands
[0]))
2042 return "sub%.l %0,%0";
2043 else if (DATA_REG_P (operands
[0]))
2044 return output_move_const_into_data_reg (operands
);
2045 else if (ADDRESS_REG_P (operands
[0])
2046 && INTVAL (operands
[1]) < 0x8000
2047 && INTVAL (operands
[1]) >= -0x8000)
2049 if (valid_mov3q_const (operands
[1]))
2050 return "mov3q%.l %1,%0";
2051 return "move%.w %1,%0";
2053 else if (GET_CODE (operands
[0]) == MEM
2054 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2055 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2056 && INTVAL (operands
[1]) < 0x8000
2057 && INTVAL (operands
[1]) >= -0x8000)
2059 if (valid_mov3q_const (operands
[1]))
2060 return "mov3q%.l %1,%-";
2063 return "move%.l %1,%0";
2067 output_move_simode (rtx
*operands
)
2069 if (GET_CODE (operands
[1]) == CONST_INT
)
2070 return output_move_simode_const (operands
);
2071 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2072 || GET_CODE (operands
[1]) == CONST
)
2073 && push_operand (operands
[0], SImode
))
2075 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2076 || GET_CODE (operands
[1]) == CONST
)
2077 && ADDRESS_REG_P (operands
[0]))
2078 return "lea %a1,%0";
2079 return "move%.l %1,%0";
2083 output_move_himode (rtx
*operands
)
2085 if (GET_CODE (operands
[1]) == CONST_INT
)
2087 if (operands
[1] == const0_rtx
2088 && (DATA_REG_P (operands
[0])
2089 || GET_CODE (operands
[0]) == MEM
)
2090 /* clr insns on 68000 read before writing. */
2091 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2092 || !(GET_CODE (operands
[0]) == MEM
2093 && MEM_VOLATILE_P (operands
[0]))))
2095 else if (operands
[1] == const0_rtx
2096 && ADDRESS_REG_P (operands
[0]))
2097 return "sub%.l %0,%0";
2098 else if (DATA_REG_P (operands
[0])
2099 && INTVAL (operands
[1]) < 128
2100 && INTVAL (operands
[1]) >= -128)
2101 return "moveq %1,%0";
2102 else if (INTVAL (operands
[1]) < 0x8000
2103 && INTVAL (operands
[1]) >= -0x8000)
2104 return "move%.w %1,%0";
2106 else if (CONSTANT_P (operands
[1]))
2107 return "move%.l %1,%0";
2108 /* Recognize the insn before a tablejump, one that refers
2109 to a table of offsets. Such an insn will need to refer
2110 to a label on the insn. So output one. Use the label-number
2111 of the table of offsets to generate this label. This code,
2112 and similar code below, assumes that there will be at most one
2113 reference to each table. */
2114 if (GET_CODE (operands
[1]) == MEM
2115 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2116 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2117 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2119 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2121 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2122 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2124 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2125 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2127 return "move%.w %1,%0";
2131 output_move_qimode (rtx
*operands
)
2133 /* 68k family always modifies the stack pointer by at least 2, even for
2134 byte pushes. The 5200 (ColdFire) does not do this. */
2136 /* This case is generated by pushqi1 pattern now. */
2137 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2138 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2139 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2140 && ! ADDRESS_REG_P (operands
[1])
2141 && ! TARGET_COLDFIRE
));
2143 /* clr and st insns on 68000 read before writing. */
2144 if (!ADDRESS_REG_P (operands
[0])
2145 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2146 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2148 if (operands
[1] == const0_rtx
)
2150 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2151 && GET_CODE (operands
[1]) == CONST_INT
2152 && (INTVAL (operands
[1]) & 255) == 255)
2158 if (GET_CODE (operands
[1]) == CONST_INT
2159 && DATA_REG_P (operands
[0])
2160 && INTVAL (operands
[1]) < 128
2161 && INTVAL (operands
[1]) >= -128)
2162 return "moveq %1,%0";
2163 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2164 return "sub%.l %0,%0";
2165 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2166 return "move%.l %1,%0";
2167 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2168 from address registers. */
2169 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2170 return "move%.w %1,%0";
2171 return "move%.b %1,%0";
2175 output_move_stricthi (rtx
*operands
)
2177 if (operands
[1] == const0_rtx
2178 /* clr insns on 68000 read before writing. */
2179 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2180 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2182 return "move%.w %1,%0";
2186 output_move_strictqi (rtx
*operands
)
2188 if (operands
[1] == const0_rtx
2189 /* clr insns on 68000 read before writing. */
2190 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2191 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2193 return "move%.b %1,%0";
2196 /* Return the best assembler insn template
2197 for moving operands[1] into operands[0] as a fullword. */
2200 singlemove_string (rtx
*operands
)
2202 if (GET_CODE (operands
[1]) == CONST_INT
)
2203 return output_move_simode_const (operands
);
2204 return "move%.l %1,%0";
2208 /* Output assembler code to perform a doubleword move insn
2209 with operands OPERANDS. */
2212 output_move_double (rtx
*operands
)
2216 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2221 rtx addreg0
= 0, addreg1
= 0;
2222 int dest_overlapped_low
= 0;
2223 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2228 /* First classify both operands. */
2230 if (REG_P (operands
[0]))
2232 else if (offsettable_memref_p (operands
[0]))
2234 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2236 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2238 else if (GET_CODE (operands
[0]) == MEM
)
2243 if (REG_P (operands
[1]))
2245 else if (CONSTANT_P (operands
[1]))
2247 else if (offsettable_memref_p (operands
[1]))
2249 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2251 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2253 else if (GET_CODE (operands
[1]) == MEM
)
2258 /* Check for the cases that the operand constraints are not supposed
2259 to allow to happen. Generating code for these cases is
2261 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2263 /* If one operand is decrementing and one is incrementing
2264 decrement the former register explicitly
2265 and change that operand into ordinary indexing. */
2267 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2269 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2271 output_asm_insn ("sub%.l #12,%0", operands
);
2273 output_asm_insn ("subq%.l #8,%0", operands
);
2274 if (GET_MODE (operands
[1]) == XFmode
)
2275 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2276 else if (GET_MODE (operands
[0]) == DFmode
)
2277 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2279 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2282 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2284 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2286 output_asm_insn ("sub%.l #12,%1", operands
);
2288 output_asm_insn ("subq%.l #8,%1", operands
);
2289 if (GET_MODE (operands
[1]) == XFmode
)
2290 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2291 else if (GET_MODE (operands
[1]) == DFmode
)
2292 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2294 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2298 /* If an operand is an unoffsettable memory ref, find a register
2299 we can increment temporarily to make it refer to the second word. */
2301 if (optype0
== MEMOP
)
2302 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2304 if (optype1
== MEMOP
)
2305 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2307 /* Ok, we can do one word at a time.
2308 Normally we do the low-numbered word first,
2309 but if either operand is autodecrementing then we
2310 do the high-numbered word first.
2312 In either case, set up in LATEHALF the operands to use
2313 for the high-numbered word and in some cases alter the
2314 operands in OPERANDS to be suitable for the low-numbered word. */
2318 if (optype0
== REGOP
)
2320 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2321 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2323 else if (optype0
== OFFSOP
)
2325 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2326 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2330 middlehalf
[0] = operands
[0];
2331 latehalf
[0] = operands
[0];
2334 if (optype1
== REGOP
)
2336 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2337 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2339 else if (optype1
== OFFSOP
)
2341 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2342 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2344 else if (optype1
== CNSTOP
)
2346 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2351 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2352 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2353 operands
[1] = GEN_INT (l
[0]);
2354 middlehalf
[1] = GEN_INT (l
[1]);
2355 latehalf
[1] = GEN_INT (l
[2]);
2359 /* No non-CONST_DOUBLE constant should ever appear
2361 gcc_assert (!CONSTANT_P (operands
[1]));
2366 middlehalf
[1] = operands
[1];
2367 latehalf
[1] = operands
[1];
2371 /* size is not 12: */
2373 if (optype0
== REGOP
)
2374 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2375 else if (optype0
== OFFSOP
)
2376 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2378 latehalf
[0] = operands
[0];
2380 if (optype1
== REGOP
)
2381 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2382 else if (optype1
== OFFSOP
)
2383 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2384 else if (optype1
== CNSTOP
)
2385 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2387 latehalf
[1] = operands
[1];
2390 /* If insn is effectively movd N(sp),-(sp) then we will do the
2391 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2392 for the low word as well, to compensate for the first decrement of sp. */
2393 if (optype0
== PUSHOP
2394 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2395 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2396 operands
[1] = middlehalf
[1] = latehalf
[1];
2398 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2399 if the upper part of reg N does not appear in the MEM, arrange to
2400 emit the move late-half first. Otherwise, compute the MEM address
2401 into the upper part of N and use that as a pointer to the memory
2403 if (optype0
== REGOP
2404 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2406 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2408 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2409 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2411 /* If both halves of dest are used in the src memory address,
2412 compute the address into latehalf of dest.
2413 Note that this can't happen if the dest is two data regs. */
2415 xops
[0] = latehalf
[0];
2416 xops
[1] = XEXP (operands
[1], 0);
2417 output_asm_insn ("lea %a1,%0", xops
);
2418 if (GET_MODE (operands
[1]) == XFmode
)
2420 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2421 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2422 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2426 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2427 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2431 && reg_overlap_mentioned_p (middlehalf
[0],
2432 XEXP (operands
[1], 0)))
2434 /* Check for two regs used by both source and dest.
2435 Note that this can't happen if the dest is all data regs.
2436 It can happen if the dest is d6, d7, a0.
2437 But in that case, latehalf is an addr reg, so
2438 the code at compadr does ok. */
2440 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2441 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2444 /* JRV says this can't happen: */
2445 gcc_assert (!addreg0
&& !addreg1
);
2447 /* Only the middle reg conflicts; simply put it last. */
2448 output_asm_insn (singlemove_string (operands
), operands
);
2449 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2450 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2453 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2454 /* If the low half of dest is mentioned in the source memory
2455 address, the arrange to emit the move late half first. */
2456 dest_overlapped_low
= 1;
2459 /* If one or both operands autodecrementing,
2460 do the two words, high-numbered first. */
2462 /* Likewise, the first move would clobber the source of the second one,
2463 do them in the other order. This happens only for registers;
2464 such overlap can't happen in memory unless the user explicitly
2465 sets it up, and that is an undefined circumstance. */
2467 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2468 || (optype0
== REGOP
&& optype1
== REGOP
2469 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2470 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2471 || dest_overlapped_low
)
2473 /* Make any unoffsettable addresses point at high-numbered word. */
2477 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2479 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2484 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2486 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2490 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2492 /* Undo the adds we just did. */
2494 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2496 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2500 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2502 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2504 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2507 /* Do low-numbered word. */
2508 return singlemove_string (operands
);
2511 /* Normal case: do the two words, low-numbered first. */
2513 output_asm_insn (singlemove_string (operands
), operands
);
2515 /* Do the middle one of the three words for long double */
2519 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2521 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2523 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2526 /* Make any unoffsettable addresses point at high-numbered word. */
2528 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2530 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2533 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2535 /* Undo the adds we just did. */
2539 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2541 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2546 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2548 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2555 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2556 new rtx with the correct mode. */
2559 force_mode (enum machine_mode mode
, rtx orig
)
2561 if (mode
== GET_MODE (orig
))
2564 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2567 return gen_rtx_REG (mode
, REGNO (orig
));
2571 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2573 return reg_renumber
&& FP_REG_P (op
);
2576 /* Emit insns to move operands[1] into operands[0].
2578 Return 1 if we have written out everything that needs to be done to
2579 do the move. Otherwise, return 0 and the caller will emit the move
2582 Note SCRATCH_REG may not be in the proper mode depending on how it
2583 will be used. This routine is responsible for creating a new copy
2584 of SCRATCH_REG in the proper mode. */
2587 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2589 register rtx operand0
= operands
[0];
2590 register rtx operand1
= operands
[1];
2594 && reload_in_progress
&& GET_CODE (operand0
) == REG
2595 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2596 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2597 else if (scratch_reg
2598 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2599 && GET_CODE (SUBREG_REG (operand0
)) == REG
2600 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2602 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2603 the code which tracks sets/uses for delete_output_reload. */
2604 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2605 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2606 SUBREG_BYTE (operand0
));
2607 operand0
= alter_subreg (&temp
);
2611 && reload_in_progress
&& GET_CODE (operand1
) == REG
2612 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2613 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2614 else if (scratch_reg
2615 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2616 && GET_CODE (SUBREG_REG (operand1
)) == REG
2617 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2619 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2620 the code which tracks sets/uses for delete_output_reload. */
2621 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2622 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2623 SUBREG_BYTE (operand1
));
2624 operand1
= alter_subreg (&temp
);
2627 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2628 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2629 != XEXP (operand0
, 0)))
2630 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2631 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2632 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2633 != XEXP (operand1
, 0)))
2634 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2636 /* Handle secondary reloads for loads/stores of FP registers where
2637 the address is symbolic by using the scratch register */
2638 if (fp_reg_operand (operand0
, mode
)
2639 && ((GET_CODE (operand1
) == MEM
2640 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2641 || ((GET_CODE (operand1
) == SUBREG
2642 && GET_CODE (XEXP (operand1
, 0)) == MEM
2643 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2646 if (GET_CODE (operand1
) == SUBREG
)
2647 operand1
= XEXP (operand1
, 0);
2649 /* SCRATCH_REG will hold an address. We want
2650 it in SImode regardless of what mode it was originally given
2652 scratch_reg
= force_mode (SImode
, scratch_reg
);
2654 /* D might not fit in 14 bits either; for such cases load D into
2656 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2658 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2659 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2661 XEXP (XEXP (operand1
, 0), 0),
2665 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2666 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2667 gen_rtx_MEM (mode
, scratch_reg
)));
2670 else if (fp_reg_operand (operand1
, mode
)
2671 && ((GET_CODE (operand0
) == MEM
2672 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2673 || ((GET_CODE (operand0
) == SUBREG
)
2674 && GET_CODE (XEXP (operand0
, 0)) == MEM
2675 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2678 if (GET_CODE (operand0
) == SUBREG
)
2679 operand0
= XEXP (operand0
, 0);
2681 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2682 it in SIMODE regardless of what mode it was originally given
2684 scratch_reg
= force_mode (SImode
, scratch_reg
);
2686 /* D might not fit in 14 bits either; for such cases load D into
2688 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2690 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2691 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2694 XEXP (XEXP (operand0
, 0),
2699 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2700 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2704 /* Handle secondary reloads for loads of FP registers from constant
2705 expressions by forcing the constant into memory.
2707 use scratch_reg to hold the address of the memory location.
2709 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2710 NO_REGS when presented with a const_int and an register class
2711 containing only FP registers. Doing so unfortunately creates
2712 more problems than it solves. Fix this for 2.5. */
2713 else if (fp_reg_operand (operand0
, mode
)
2714 && CONSTANT_P (operand1
)
2719 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2720 it in SIMODE regardless of what mode it was originally given
2722 scratch_reg
= force_mode (SImode
, scratch_reg
);
2724 /* Force the constant into memory and put the address of the
2725 memory location into scratch_reg. */
2726 xoperands
[0] = scratch_reg
;
2727 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2728 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2730 /* Now load the destination register. */
2731 emit_insn (gen_rtx_SET (mode
, operand0
,
2732 gen_rtx_MEM (mode
, scratch_reg
)));
2736 /* Now have insn-emit do whatever it normally does. */
2740 /* Return a REG that occurs in ADDR with coefficient 1.
2741 ADDR can be effectively incremented by incrementing REG. */
2744 find_addr_reg (rtx addr
)
2746 while (GET_CODE (addr
) == PLUS
)
2748 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2749 addr
= XEXP (addr
, 0);
2750 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2751 addr
= XEXP (addr
, 1);
2752 else if (CONSTANT_P (XEXP (addr
, 0)))
2753 addr
= XEXP (addr
, 1);
2754 else if (CONSTANT_P (XEXP (addr
, 1)))
2755 addr
= XEXP (addr
, 0);
2759 gcc_assert (GET_CODE (addr
) == REG
);
2763 /* Output assembler code to perform a 32-bit 3-operand add. */
2766 output_addsi3 (rtx
*operands
)
2768 if (! operands_match_p (operands
[0], operands
[1]))
2770 if (!ADDRESS_REG_P (operands
[1]))
2772 rtx tmp
= operands
[1];
2774 operands
[1] = operands
[2];
2778 /* These insns can result from reloads to access
2779 stack slots over 64k from the frame pointer. */
2780 if (GET_CODE (operands
[2]) == CONST_INT
2781 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2782 return "move%.l %2,%0\n\tadd%.l %1,%0";
2783 if (GET_CODE (operands
[2]) == REG
)
2784 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2785 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2787 if (GET_CODE (operands
[2]) == CONST_INT
)
2789 if (INTVAL (operands
[2]) > 0
2790 && INTVAL (operands
[2]) <= 8)
2791 return "addq%.l %2,%0";
2792 if (INTVAL (operands
[2]) < 0
2793 && INTVAL (operands
[2]) >= -8)
2795 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2796 return "subq%.l %2,%0";
2798 /* On the CPU32 it is faster to use two addql instructions to
2799 add a small integer (8 < N <= 16) to a register.
2800 Likewise for subql. */
2801 if (TUNE_CPU32
&& REG_P (operands
[0]))
2803 if (INTVAL (operands
[2]) > 8
2804 && INTVAL (operands
[2]) <= 16)
2806 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2807 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2809 if (INTVAL (operands
[2]) < -8
2810 && INTVAL (operands
[2]) >= -16)
2812 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2813 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2816 if (ADDRESS_REG_P (operands
[0])
2817 && INTVAL (operands
[2]) >= -0x8000
2818 && INTVAL (operands
[2]) < 0x8000)
2821 return "add%.w %2,%0";
2823 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2826 return "add%.l %2,%0";
2829 /* Store in cc_status the expressions that the condition codes will
2830 describe after execution of an instruction whose pattern is EXP.
2831 Do not alter them if the instruction would not alter the cc's. */
2833 /* On the 68000, all the insns to store in an address register fail to
2834 set the cc's. However, in some cases these instructions can make it
2835 possibly invalid to use the saved cc's. In those cases we clear out
2836 some or all of the saved cc's so they won't be used. */
2839 notice_update_cc (rtx exp
, rtx insn
)
2841 if (GET_CODE (exp
) == SET
)
2843 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2845 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2847 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2848 cc_status
.value1
= 0;
2849 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2850 cc_status
.value2
= 0;
2852 else if (!FP_REG_P (SET_DEST (exp
))
2853 && SET_DEST (exp
) != cc0_rtx
2854 && (FP_REG_P (SET_SRC (exp
))
2855 || GET_CODE (SET_SRC (exp
)) == FIX
2856 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2857 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2859 /* A pair of move insns doesn't produce a useful overall cc. */
2860 else if (!FP_REG_P (SET_DEST (exp
))
2861 && !FP_REG_P (SET_SRC (exp
))
2862 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2863 && (GET_CODE (SET_SRC (exp
)) == REG
2864 || GET_CODE (SET_SRC (exp
)) == MEM
2865 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2867 else if (SET_DEST (exp
) != pc_rtx
)
2869 cc_status
.flags
= 0;
2870 cc_status
.value1
= SET_DEST (exp
);
2871 cc_status
.value2
= SET_SRC (exp
);
2874 else if (GET_CODE (exp
) == PARALLEL
2875 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2877 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2878 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2880 if (ADDRESS_REG_P (dest
))
2882 else if (dest
!= pc_rtx
)
2884 cc_status
.flags
= 0;
2885 cc_status
.value1
= dest
;
2886 cc_status
.value2
= src
;
2891 if (cc_status
.value2
!= 0
2892 && ADDRESS_REG_P (cc_status
.value2
)
2893 && GET_MODE (cc_status
.value2
) == QImode
)
2895 if (cc_status
.value2
!= 0)
2896 switch (GET_CODE (cc_status
.value2
))
2898 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2899 case ROTATE
: case ROTATERT
:
2900 /* These instructions always clear the overflow bit, and set
2901 the carry to the bit shifted out. */
2902 /* ??? We don't currently have a way to signal carry not valid,
2903 nor do we check for it in the branch insns. */
2907 case PLUS
: case MINUS
: case MULT
:
2908 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2909 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2910 cc_status
.flags
|= CC_NO_OVERFLOW
;
2913 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2914 ends with a move insn moving r2 in r2's mode.
2915 Thus, the cc's are set for r2.
2916 This can set N bit spuriously. */
2917 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2922 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2924 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2925 cc_status
.value2
= 0;
2926 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2927 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2928 cc_status
.flags
= CC_IN_68881
;
2932 output_move_const_double (rtx
*operands
)
2934 int code
= standard_68881_constant_p (operands
[1]);
2938 static char buf
[40];
2940 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2943 return "fmove%.d %1,%0";
2947 output_move_const_single (rtx
*operands
)
2949 int code
= standard_68881_constant_p (operands
[1]);
2953 static char buf
[40];
2955 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2958 return "fmove%.s %f1,%0";
2961 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2962 from the "fmovecr" instruction.
2963 The value, anded with 0xff, gives the code to use in fmovecr
2964 to get the desired constant. */
2966 /* This code has been fixed for cross-compilation. */
2968 static int inited_68881_table
= 0;
2970 static const char *const strings_68881
[7] = {
2980 static const int codes_68881
[7] = {
2990 REAL_VALUE_TYPE values_68881
[7];
2992 /* Set up values_68881 array by converting the decimal values
2993 strings_68881 to binary. */
2996 init_68881_table (void)
3000 enum machine_mode mode
;
3003 for (i
= 0; i
< 7; i
++)
3007 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3008 values_68881
[i
] = r
;
3010 inited_68881_table
= 1;
3014 standard_68881_constant_p (rtx x
)
3019 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3020 used at all on those chips. */
3024 if (! inited_68881_table
)
3025 init_68881_table ();
3027 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3029 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3031 for (i
= 0; i
< 6; i
++)
3033 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3034 return (codes_68881
[i
]);
3037 if (GET_MODE (x
) == SFmode
)
3040 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3041 return (codes_68881
[6]);
3043 /* larger powers of ten in the constants ram are not used
3044 because they are not equal to a `double' C constant. */
3048 /* If X is a floating-point constant, return the logarithm of X base 2,
3049 or 0 if X is not a power of 2. */
3052 floating_exact_log2 (rtx x
)
3054 REAL_VALUE_TYPE r
, r1
;
3057 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3059 if (REAL_VALUES_LESS (r
, dconst1
))
3062 exp
= real_exponent (&r
);
3063 real_2expN (&r1
, exp
);
3064 if (REAL_VALUES_EQUAL (r1
, r
))
3070 /* A C compound statement to output to stdio stream STREAM the
3071 assembler syntax for an instruction operand X. X is an RTL
3074 CODE is a value that can be used to specify one of several ways
3075 of printing the operand. It is used when identical operands
3076 must be printed differently depending on the context. CODE
3077 comes from the `%' specification that was used to request
3078 printing of the operand. If the specification was just `%DIGIT'
3079 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3080 is the ASCII code for LTR.
3082 If X is a register, this macro should print the register's name.
3083 The names can be found in an array `reg_names' whose type is
3084 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3086 When the machine description has a specification `%PUNCT' (a `%'
3087 followed by a punctuation character), this macro is called with
3088 a null pointer for X and the punctuation character for CODE.
3090 The m68k specific codes are:
3092 '.' for dot needed in Motorola-style opcode names.
3093 '-' for an operand pushing on the stack:
3094 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3095 '+' for an operand pushing on the stack:
3096 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3097 '@' for a reference to the top word on the stack:
3098 sp@, (sp) or (%sp) depending on the style of syntax.
3099 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3100 but & in SGS syntax).
3101 '!' for the cc register (used in an `and to cc' insn).
3102 '$' for the letter `s' in an op code, but only on the 68040.
3103 '&' for the letter `d' in an op code, but only on the 68040.
3104 '/' for register prefix needed by longlong.h.
3106 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3107 'd' to force memory addressing to be absolute, not relative.
3108 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3109 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3110 or print pair of registers as rx:ry.
3111 'p' print an address with @PLTPC attached, but only if the operand
3112 is not locally-bound. */
3115 print_operand (FILE *file
, rtx op
, int letter
)
3120 fprintf (file
, ".");
3122 else if (letter
== '#')
3123 asm_fprintf (file
, "%I");
3124 else if (letter
== '-')
3125 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3126 else if (letter
== '+')
3127 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3128 else if (letter
== '@')
3129 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3130 else if (letter
== '!')
3131 asm_fprintf (file
, "%Rfpcr");
3132 else if (letter
== '$')
3135 fprintf (file
, "s");
3137 else if (letter
== '&')
3140 fprintf (file
, "d");
3142 else if (letter
== '/')
3143 asm_fprintf (file
, "%R");
3144 else if (letter
== 'p')
3146 output_addr_const (file
, op
);
3147 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3148 fprintf (file
, "@PLTPC");
3150 else if (GET_CODE (op
) == REG
)
3153 /* Print out the second register name of a register pair.
3154 I.e., R (6) => 7. */
3155 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3157 fputs (M68K_REGNAME(REGNO (op
)), file
);
3159 else if (GET_CODE (op
) == MEM
)
3161 output_address (XEXP (op
, 0));
3162 if (letter
== 'd' && ! TARGET_68020
3163 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3164 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3165 && INTVAL (XEXP (op
, 0)) < 0x8000
3166 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3167 fprintf (file
, MOTOROLA
? ".l" : ":l");
3169 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3172 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3173 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3175 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3178 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3179 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3181 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3184 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3185 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3189 /* Use `print_operand_address' instead of `output_addr_const'
3190 to ensure that we print relevant PIC stuff. */
3191 asm_fprintf (file
, "%I");
3193 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3194 print_operand_address (file
, op
);
3196 output_addr_const (file
, op
);
3201 /* A C compound statement to output to stdio stream STREAM the
3202 assembler syntax for an instruction operand that is a memory
3203 reference whose address is ADDR. ADDR is an RTL expression.
3205 Note that this contains a kludge that knows that the only reason
3206 we have an address (plus (label_ref...) (reg...)) when not generating
3207 PIC code is in the insn before a tablejump, and we know that m68k.md
3208 generates a label LInnn: on such an insn.
3210 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3211 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3213 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3214 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3215 we want. This difference can be accommodated by using an assembler
3216 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3217 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3218 macro. See m68k/sgs.h for an example; for versions without the bug.
3219 Some assemblers refuse all the above solutions. The workaround is to
3220 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3223 They also do not like things like "pea 1.w", so we simple leave off
3224 the .w on small constants.
3226 This routine is responsible for distinguishing between -fpic and -fPIC
3227 style relocations in an address. When generating -fpic code the
3228 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3229 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3232 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3233 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3234 #else /* !MOTOROLA */
3235 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3236 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3237 #endif /* !MOTOROLA */
3240 print_operand_address (FILE *file
, rtx addr
)
3242 register rtx reg1
, reg2
, breg
, ireg
;
3245 switch (GET_CODE (addr
))
3248 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3251 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3252 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3255 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3256 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3259 reg1
= reg2
= ireg
= breg
= offset
= 0;
3260 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3262 offset
= XEXP (addr
, 0);
3263 addr
= XEXP (addr
, 1);
3265 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3267 offset
= XEXP (addr
, 1);
3268 addr
= XEXP (addr
, 0);
3270 if (GET_CODE (addr
) != PLUS
)
3274 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3276 reg1
= XEXP (addr
, 0);
3277 addr
= XEXP (addr
, 1);
3279 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3281 reg1
= XEXP (addr
, 1);
3282 addr
= XEXP (addr
, 0);
3284 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3286 reg1
= XEXP (addr
, 0);
3287 addr
= XEXP (addr
, 1);
3289 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3291 reg1
= XEXP (addr
, 1);
3292 addr
= XEXP (addr
, 0);
3294 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3296 reg1
= XEXP (addr
, 0);
3297 addr
= XEXP (addr
, 1);
3299 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3301 reg1
= XEXP (addr
, 1);
3302 addr
= XEXP (addr
, 0);
3304 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3305 || GET_CODE (addr
) == SIGN_EXTEND
)
3313 #if 0 /* for OLD_INDEXING */
3314 else if (GET_CODE (addr
) == PLUS
)
3316 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3318 reg2
= XEXP (addr
, 0);
3319 addr
= XEXP (addr
, 1);
3321 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3323 reg2
= XEXP (addr
, 1);
3324 addr
= XEXP (addr
, 0);
3333 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3334 || GET_CODE (reg1
) == MULT
))
3335 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3340 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3345 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3346 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3349 if (GET_CODE (ireg
) == MULT
)
3351 scale
= INTVAL (XEXP (ireg
, 1));
3352 ireg
= XEXP (ireg
, 0);
3354 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3356 ASM_OUTPUT_CASE_FETCH (file
,
3357 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3358 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3359 fprintf (file
, "w");
3363 ASM_OUTPUT_CASE_FETCH (file
,
3364 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3365 M68K_REGNAME (REGNO (ireg
)));
3366 fprintf (file
, "l");
3369 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3373 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3374 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3376 ASM_OUTPUT_CASE_FETCH (file
,
3377 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3378 M68K_REGNAME (REGNO (breg
)));
3379 fprintf (file
, "l)");
3382 if (ireg
!= 0 || breg
!= 0)
3387 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3393 output_addr_const (file
, addr
);
3394 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3396 fprintf (file
, "@GOT");
3398 fprintf (file
, ".w");
3401 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3405 else /* !MOTOROLA */
3407 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3410 output_addr_const (file
, addr
);
3411 if (breg
== pic_offset_table_rtx
)
3415 fprintf (file
, ":w");
3418 fprintf (file
, ":l");
3427 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3429 scale
= INTVAL (XEXP (ireg
, 1));
3430 ireg
= XEXP (ireg
, 0);
3432 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3433 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3434 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3436 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3437 M68K_REGNAME (REGNO (ireg
)));
3439 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3443 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3444 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3446 ASM_OUTPUT_CASE_FETCH (file
,
3447 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3448 M68K_REGNAME (REGNO (reg1
)));
3449 fprintf (file
, "l)");
3452 /* FALL-THROUGH (is this really what we want?) */
3454 if (GET_CODE (addr
) == CONST_INT
3455 && INTVAL (addr
) < 0x8000
3456 && INTVAL (addr
) >= -0x8000)
3458 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3460 else if (GET_CODE (addr
) == CONST_INT
)
3462 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3464 else if (TARGET_PCREL
)
3467 output_addr_const (file
, addr
);
3469 asm_fprintf (file
, ":w,%Rpc)");
3471 asm_fprintf (file
, ":l,%Rpc)");
3475 /* Special case for SYMBOL_REF if the symbol name ends in
3476 `.<letter>', this can be mistaken as a size suffix. Put
3477 the name in parentheses. */
3478 if (GET_CODE (addr
) == SYMBOL_REF
3479 && strlen (XSTR (addr
, 0)) > 2
3480 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3483 output_addr_const (file
, addr
);
3487 output_addr_const (file
, addr
);
3493 /* Check for cases where a clr insns can be omitted from code using
3494 strict_low_part sets. For example, the second clrl here is not needed:
3495 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3497 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3498 insn we are checking for redundancy. TARGET is the register set by the
3502 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3507 p
= prev_nonnote_insn (first_insn
);
3511 /* If it isn't an insn, then give up. */
3512 if (GET_CODE (p
) != INSN
)
3515 if (reg_set_p (target
, p
))
3517 rtx set
= single_set (p
);
3520 /* If it isn't an easy to recognize insn, then give up. */
3524 dest
= SET_DEST (set
);
3526 /* If this sets the entire target register to zero, then our
3527 first_insn is redundant. */
3528 if (rtx_equal_p (dest
, target
)
3529 && SET_SRC (set
) == const0_rtx
)
3531 else if (GET_CODE (dest
) == STRICT_LOW_PART
3532 && GET_CODE (XEXP (dest
, 0)) == REG
3533 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3534 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3535 <= GET_MODE_SIZE (mode
)))
3536 /* This is a strict low part set which modifies less than
3537 we are using, so it is safe. */
3543 p
= prev_nonnote_insn (p
);
3549 /* Operand predicates for implementing asymmetric pc-relative addressing
3550 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3551 when used as a source operand, but not as a destination operand.
3553 We model this by restricting the meaning of the basic predicates
3554 (general_operand, memory_operand, etc) to forbid the use of this
3555 addressing mode, and then define the following predicates that permit
3556 this addressing mode. These predicates can then be used for the
3557 source operands of the appropriate instructions.
3559 n.b. While it is theoretically possible to change all machine patterns
3560 to use this addressing more where permitted by the architecture,
3561 it has only been implemented for "common" cases: SImode, HImode, and
3562 QImode operands, and only for the principle operations that would
3563 require this addressing mode: data movement and simple integer operations.
3565 In parallel with these new predicates, two new constraint letters
3566 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3567 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3568 In the pcrel case 's' is only valid in combination with 'a' registers.
3569 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3570 of how these constraints are used.
3572 The use of these predicates is strictly optional, though patterns that
3573 don't will cause an extra reload register to be allocated where one
3576 lea (abc:w,%pc),%a0 ; need to reload address
3577 moveq &1,%d1 ; since write to pc-relative space
3578 movel %d1,%a0@ ; is not allowed
3580 lea (abc:w,%pc),%a1 ; no need to reload address here
3581 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3583 For more info, consult tiemann@cygnus.com.
3586 All of the ugliness with predicates and constraints is due to the
3587 simple fact that the m68k does not allow a pc-relative addressing
3588 mode as a destination. gcc does not distinguish between source and
3589 destination addresses. Hence, if we claim that pc-relative address
3590 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3591 end up with invalid code. To get around this problem, we left
3592 pc-relative modes as invalid addresses, and then added special
3593 predicates and constraints to accept them.
3595 A cleaner way to handle this is to modify gcc to distinguish
3596 between source and destination addresses. We can then say that
3597 pc-relative is a valid source address but not a valid destination
3598 address, and hopefully avoid a lot of the predicate and constraint
3599 hackery. Unfortunately, this would be a pretty big change. It would
3600 be a useful change for a number of ports, but there aren't any current
3601 plans to undertake this.
3603 ***************************************************************************/
3607 output_andsi3 (rtx
*operands
)
3610 if (GET_CODE (operands
[2]) == CONST_INT
3611 && (INTVAL (operands
[2]) | 0xffff) == -1
3612 && (DATA_REG_P (operands
[0])
3613 || offsettable_memref_p (operands
[0]))
3614 && !TARGET_COLDFIRE
)
3616 if (GET_CODE (operands
[0]) != REG
)
3617 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3618 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3619 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3621 if (operands
[2] == const0_rtx
)
3623 return "and%.w %2,%0";
3625 if (GET_CODE (operands
[2]) == CONST_INT
3626 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3627 && (DATA_REG_P (operands
[0])
3628 || offsettable_memref_p (operands
[0])))
3630 if (DATA_REG_P (operands
[0]))
3631 operands
[1] = GEN_INT (logval
);
3634 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3635 operands
[1] = GEN_INT (logval
% 8);
3637 /* This does not set condition codes in a standard way. */
3639 return "bclr %1,%0";
3641 return "and%.l %2,%0";
3645 output_iorsi3 (rtx
*operands
)
3647 register int logval
;
3648 if (GET_CODE (operands
[2]) == CONST_INT
3649 && INTVAL (operands
[2]) >> 16 == 0
3650 && (DATA_REG_P (operands
[0])
3651 || offsettable_memref_p (operands
[0]))
3652 && !TARGET_COLDFIRE
)
3654 if (GET_CODE (operands
[0]) != REG
)
3655 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3656 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3658 if (INTVAL (operands
[2]) == 0xffff)
3659 return "mov%.w %2,%0";
3660 return "or%.w %2,%0";
3662 if (GET_CODE (operands
[2]) == CONST_INT
3663 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3664 && (DATA_REG_P (operands
[0])
3665 || offsettable_memref_p (operands
[0])))
3667 if (DATA_REG_P (operands
[0]))
3668 operands
[1] = GEN_INT (logval
);
3671 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3672 operands
[1] = GEN_INT (logval
% 8);
3675 return "bset %1,%0";
3677 return "or%.l %2,%0";
3681 output_xorsi3 (rtx
*operands
)
3683 register int logval
;
3684 if (GET_CODE (operands
[2]) == CONST_INT
3685 && INTVAL (operands
[2]) >> 16 == 0
3686 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3687 && !TARGET_COLDFIRE
)
3689 if (! DATA_REG_P (operands
[0]))
3690 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3691 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3693 if (INTVAL (operands
[2]) == 0xffff)
3695 return "eor%.w %2,%0";
3697 if (GET_CODE (operands
[2]) == CONST_INT
3698 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3699 && (DATA_REG_P (operands
[0])
3700 || offsettable_memref_p (operands
[0])))
3702 if (DATA_REG_P (operands
[0]))
3703 operands
[1] = GEN_INT (logval
);
3706 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3707 operands
[1] = GEN_INT (logval
% 8);
3710 return "bchg %1,%0";
3712 return "eor%.l %2,%0";
3715 /* Return the instruction that should be used for a call to address X,
3716 which is known to be in operand 0. */
3721 if (symbolic_operand (x
, VOIDmode
))
3722 return m68k_symbolic_call
;
3727 #ifdef M68K_TARGET_COFF
3729 /* Output assembly to switch to section NAME with attribute FLAGS. */
3732 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3733 tree decl ATTRIBUTE_UNUSED
)
3737 if (flags
& SECTION_WRITE
)
3742 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3745 #endif /* M68K_TARGET_COFF */
3748 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3749 HOST_WIDE_INT delta
,
3750 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3756 if (delta
> 0 && delta
<= 8)
3757 asm_fprintf (file
, (MOTOROLA
3758 ? "\taddq.l %I%d,4(%Rsp)\n"
3759 : "\taddql %I%d,%Rsp@(4)\n"),
3761 else if (delta
< 0 && delta
>= -8)
3762 asm_fprintf (file
, (MOTOROLA
3763 ? "\tsubq.l %I%d,4(%Rsp)\n"
3764 : "\tsubql %I%d,%Rsp@(4)\n"),
3766 else if (TARGET_COLDFIRE
)
3768 /* ColdFire can't add/sub a constant to memory unless it is in
3769 the range of addq/subq. So load the value into %d0 and
3770 then add it to 4(%sp). */
3771 if (delta
>= -128 && delta
<= 127)
3772 asm_fprintf (file
, (MOTOROLA
3773 ? "\tmoveq.l %I%wd,%Rd0\n"
3774 : "\tmoveql %I%wd,%Rd0\n"),
3777 asm_fprintf (file
, (MOTOROLA
3778 ? "\tmove.l %I%wd,%Rd0\n"
3779 : "\tmovel %I%wd,%Rd0\n"),
3781 asm_fprintf (file
, (MOTOROLA
3782 ? "\tadd.l %Rd0,4(%Rsp)\n"
3783 : "\taddl %Rd0,%Rsp@(4)\n"));
3786 asm_fprintf (file
, (MOTOROLA
3787 ? "\tadd.l %I%wd,4(%Rsp)\n"
3788 : "\taddl %I%wd,%Rsp@(4)\n"),
3791 xops
[0] = DECL_RTL (function
);
3793 gcc_assert (MEM_P (xops
[0])
3794 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
3795 xops
[0] = XEXP (xops
[0], 0);
3797 fmt
= m68k_symbolic_jump
;
3798 if (m68k_symbolic_jump
== NULL
)
3799 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3801 output_asm_insn (fmt
, xops
);
3804 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3807 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3808 int incoming ATTRIBUTE_UNUSED
)
3810 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3813 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3815 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3816 unsigned int new_reg
)
3819 /* Interrupt functions can only use registers that have already been
3820 saved by the prologue, even if they would normally be
3823 if (m68k_interrupt_function_p (current_function_decl
)
3824 && !regs_ever_live
[new_reg
])
3830 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3831 On the 68000, the cpu registers can hold any mode except bytes in address
3832 registers, but the 68881 registers can hold only SFmode or DFmode. */
3834 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3836 if (DATA_REGNO_P (regno
))
3838 /* Data Registers, can hold aggregate if fits in. */
3839 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3842 else if (ADDRESS_REGNO_P (regno
))
3844 /* Address Registers, can't hold bytes, can hold aggregate if
3846 if (GET_MODE_SIZE (mode
) == 1)
3848 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3851 else if (FP_REGNO_P (regno
))
3853 /* FPU registers, hold float or complex float of long double or
3855 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3856 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3857 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3863 /* Return floating point values in a 68881 register. This makes 68881 code
3864 a little bit faster. It also makes -msoft-float code incompatible with
3865 hard-float code, so people have to be careful not to mix the two.
3866 For ColdFire it was decided the ABI incompatibility is undesirable.
3867 If there is need for a hard-float ABI it is probably worth doing it
3868 properly and also passing function arguments in FP registers. */
3870 m68k_libcall_value (enum machine_mode mode
)
3877 return gen_rtx_REG (mode
, 16);
3882 return gen_rtx_REG (mode
, 0);
3886 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3888 enum machine_mode mode
;
3890 mode
= TYPE_MODE (valtype
);
3896 return gen_rtx_REG (mode
, 16);
3902 /* If the function returns a pointer, push that into %a0 */
3903 if (POINTER_TYPE_P (valtype
))
3904 return gen_rtx_REG (mode
, 8);
3906 return gen_rtx_REG (mode
, 0);