1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static rtx
find_addr_reg (rtx
);
107 static const char *singlemove_string (rtx
*);
108 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
109 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
110 #ifdef M68K_TARGET_COFF
111 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
112 #endif /* M68K_TARGET_COFF */
113 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
114 HOST_WIDE_INT
, tree
);
115 static rtx
m68k_struct_value_rtx (tree
, int);
116 static bool m68k_interrupt_function_p (tree func
);
117 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
118 tree args
, int flags
,
120 static void m68k_compute_frame_layout (void);
121 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
122 static int const_int_cost (rtx
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Specify the identification number of the library being built */
127 const char *m68k_library_id_string
;
129 /* Nonzero if the last compare/test insn had FP operands. The
130 sCC expanders peek at this to determine what to do for the
131 68060, which has no fsCC instructions. */
132 int m68k_last_compare_had_fp_operands
;
134 /* Initialize the GCC target structure. */
136 #if INT_OP_GROUP == INT_OP_DOT_WORD
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
141 #if INT_OP_GROUP == INT_OP_NO_DOT
142 #undef TARGET_ASM_BYTE_OP
143 #define TARGET_ASM_BYTE_OP "\tbyte\t"
144 #undef TARGET_ASM_ALIGNED_HI_OP
145 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
146 #undef TARGET_ASM_ALIGNED_SI_OP
147 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
150 #if INT_OP_GROUP == INT_OP_DC
151 #undef TARGET_ASM_BYTE_OP
152 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
155 #undef TARGET_ASM_ALIGNED_SI_OP
156 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
159 #undef TARGET_ASM_UNALIGNED_HI_OP
160 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
161 #undef TARGET_ASM_UNALIGNED_SI_OP
162 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
164 #undef TARGET_ASM_FUNCTION_PROLOGUE
165 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
166 #undef TARGET_ASM_FUNCTION_EPILOGUE
167 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
169 #undef TARGET_ASM_OUTPUT_MI_THUNK
170 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
171 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
172 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
174 #undef TARGET_ASM_FILE_START_APP_OFF
175 #define TARGET_ASM_FILE_START_APP_OFF true
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS m68k_rtx_costs
180 #undef TARGET_ATTRIBUTE_TABLE
181 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
183 #undef TARGET_PROMOTE_PROTOTYPES
184 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
186 #undef TARGET_STRUCT_VALUE_RTX
187 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
189 static const struct attribute_spec m68k_attribute_table
[] =
191 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
192 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
193 { NULL
, 0, 0, false, false, false, NULL
}
196 struct gcc_target targetm
= TARGET_INITIALIZER
;
198 /* Sometimes certain combinations of command options do not make
199 sense on a particular target machine. You can define a macro
200 `OVERRIDE_OPTIONS' to take account of this. This macro, if
201 defined, is executed once just after all the command options have
204 Don't use this macro to turn on various extra optimizations for
205 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
208 override_options (void)
210 /* Library identification */
211 if (m68k_library_id_string
)
215 if (! TARGET_ID_SHARED_LIBRARY
)
216 error ("-mshared-library-id= specified without -mid-shared-library");
217 id
= atoi (m68k_library_id_string
);
218 if (id
< 0 || id
> MAX_LIBRARY_ID
)
219 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
221 /* From now on, m68k_library_id_string will contain the library offset. */
222 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
225 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
227 m68k_library_id_string
= "_current_shared_library_a5_offset_";
229 /* Sanity check to ensure that msep-data and mid-sahred-library are not
230 * both specified together. Doing so simply doesn't make sense.
232 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
233 error ("cannot specify both -msep-data and -mid-shared-library");
235 /* If we're generating code for a separate A5 relative data segment,
236 * we've got to enable -fPIC as well. This might be relaxable to
237 * -fpic but it hasn't been tested properly.
239 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
242 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
244 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
245 error("-fPIC is not currently supported on the 68000 or 68010\n");
247 /* ??? A historic way of turning on pic, or is this intended to
248 be an embedded thing that doesn't have the same name binding
249 significance that it does on hosted ELF systems? */
250 if (TARGET_PCREL
&& flag_pic
== 0)
253 /* Turn off function cse if we are doing PIC. We always want function call
254 to be done as `bsr foo@PLTPC', so it will force the assembler to create
255 the PLT entry for `foo'. Doing function cse will cause the address of
256 `foo' to be loaded into a register, which is exactly what we want to
257 avoid when we are doing PIC on svr4 m68k. */
259 flag_no_function_cse
= 1;
261 SUBTARGET_OVERRIDE_OPTIONS
;
264 /* Return nonzero if FUNC is an interrupt function as specified by the
265 "interrupt_handler" attribute. */
267 m68k_interrupt_function_p(tree func
)
271 if (TREE_CODE (func
) != FUNCTION_DECL
)
274 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
275 return (a
!= NULL_TREE
);
278 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
279 struct attribute_spec.handler. */
281 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
282 tree args ATTRIBUTE_UNUSED
,
283 int flags ATTRIBUTE_UNUSED
,
286 if (TREE_CODE (*node
) != FUNCTION_DECL
)
288 warning ("%qs attribute only applies to functions",
289 IDENTIFIER_POINTER (name
));
290 *no_add_attrs
= true;
297 m68k_compute_frame_layout (void)
300 unsigned int mask
, rmask
;
301 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
303 /* Only compute the frame once per function.
304 Don't cache information until reload has been completed. */
305 if (current_frame
.funcdef_no
== current_function_funcdef_no
309 current_frame
.size
= (get_frame_size () + 3) & -4;
311 mask
= rmask
= saved
= 0;
312 for (regno
= 0; regno
< 16; regno
++)
313 if (m68k_save_reg (regno
, interrupt_handler
))
316 rmask
|= 1 << (15 - regno
);
319 current_frame
.offset
= saved
* 4;
320 current_frame
.reg_no
= saved
;
321 current_frame
.reg_mask
= mask
;
322 current_frame
.reg_rev_mask
= rmask
;
324 current_frame
.foffset
= 0;
325 mask
= rmask
= saved
= 0;
326 if (TARGET_68881
/* || TARGET_CFV4E */)
328 for (regno
= 16; regno
< 24; regno
++)
329 if (m68k_save_reg (regno
, interrupt_handler
))
331 mask
|= 1 << (regno
- 16);
332 rmask
|= 1 << (23 - regno
);
335 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
336 current_frame
.offset
+= current_frame
.foffset
;
338 current_frame
.fpu_no
= saved
;
339 current_frame
.fpu_mask
= mask
;
340 current_frame
.fpu_rev_mask
= rmask
;
342 /* Remember what function this frame refers to. */
343 current_frame
.funcdef_no
= current_function_funcdef_no
;
347 m68k_initial_elimination_offset (int from
, int to
)
349 /* FIXME: The correct offset to compute here would appear to be
350 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
351 but for some obscure reason, this must be 0 to get correct code. */
352 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
355 m68k_compute_frame_layout ();
357 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
358 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
359 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
360 return current_frame
.offset
+ current_frame
.size
;
365 /* Refer to the array `regs_ever_live' to determine which registers
366 to save; `regs_ever_live[I]' is nonzero if register number I
367 is ever used in the function. This function is responsible for
368 knowing which registers should not be saved even if used.
369 Return true if we need to save REGNO. */
372 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
374 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
376 if (current_function_uses_pic_offset_table
)
378 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
382 if (current_function_calls_eh_return
)
387 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
388 if (test
== INVALID_REGNUM
)
395 /* Fixed regs we never touch. */
396 if (fixed_regs
[regno
])
399 /* The frame pointer (if it is such) is handled specially. */
400 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
403 /* Interrupt handlers must also save call_used_regs
404 if they are live or when calling nested functions. */
405 if (interrupt_handler
)
407 if (regs_ever_live
[regno
])
410 if (!current_function_is_leaf
&& call_used_regs
[regno
])
414 /* Never need to save registers that aren't touched. */
415 if (!regs_ever_live
[regno
])
418 /* Otherwise save everything that isn't call-clobbered. */
419 return !call_used_regs
[regno
];
422 /* This function generates the assembly code for function entry.
423 STREAM is a stdio stream to output the code to.
424 SIZE is an int: how many units of temporary storage to allocate. */
427 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
429 HOST_WIDE_INT fsize_with_regs
;
430 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
432 m68k_compute_frame_layout();
434 /* If the stack limit is a symbol, we can check it here,
435 before actually allocating the space. */
436 if (current_function_limit_stack
437 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
438 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
439 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
441 /* On ColdFire add register save into initial stack frame setup, if possible. */
442 fsize_with_regs
= current_frame
.size
;
443 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
444 fsize_with_regs
+= current_frame
.reg_no
* 4;
446 if (frame_pointer_needed
)
448 if (current_frame
.size
== 0 && TARGET_68040
)
449 /* on the 68040, pea + move is faster than link.w 0 */
450 fprintf (stream
, MOTOROLA
?
451 "\tpea (%s)\n\tmove.l %s,%s\n" :
452 "\tpea %s@\n\tmovel %s,%s\n",
453 M68K_REGNAME(FRAME_POINTER_REGNUM
),
454 M68K_REGNAME(STACK_POINTER_REGNUM
),
455 M68K_REGNAME(FRAME_POINTER_REGNUM
));
456 else if (fsize_with_regs
< 0x8000)
457 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
458 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
459 else if (TARGET_68020
)
460 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
461 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
463 /* Adding negative number is faster on the 68040. */
464 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
465 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
466 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
468 if (dwarf2out_do_frame ())
471 l
= (char *) dwarf2out_cfi_label ();
473 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
474 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
475 cfa_offset
+= current_frame
.size
;
478 else if (fsize_with_regs
) /* !frame_pointer_needed */
480 if (fsize_with_regs
< 0x8000)
482 if (fsize_with_regs
<= 8)
484 if (!TARGET_COLDFIRE
)
485 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
488 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
491 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
492 /* On the CPU32 it is faster to use two subqw instructions to
493 subtract a small integer (8 < N <= 16) to a register. */
495 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
496 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
497 fsize_with_regs
- 8);
498 else if (TARGET_68040
)
499 /* Adding negative number is faster on the 68040. */
500 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
503 asm_fprintf (stream
, MOTOROLA
?
504 "\tlea (%wd,%Rsp),%Rsp\n" :
505 "\tlea %Rsp@(%wd),%Rsp\n",
508 else /* fsize_with_regs >= 0x8000 */
509 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
511 if (dwarf2out_do_frame ())
513 cfa_offset
+= current_frame
.size
+ 4;
514 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
516 } /* !frame_pointer_needed */
518 if (current_frame
.fpu_mask
)
520 asm_fprintf (stream
, MOTOROLA
?
521 "\tfmovm %I0x%x,-(%Rsp)\n" :
522 "\tfmovem %I0x%x,%Rsp@-\n",
523 current_frame
.fpu_mask
);
525 if (dwarf2out_do_frame ())
527 char *l
= (char *) dwarf2out_cfi_label ();
530 cfa_offset
+= current_frame
.fpu_no
* 12;
531 if (! frame_pointer_needed
)
532 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
533 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
534 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
535 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
539 /* If the stack limit is not a symbol, check it here.
540 This has the disadvantage that it may be too late... */
541 if (current_function_limit_stack
)
543 if (REG_P (stack_limit_rtx
))
544 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
545 M68K_REGNAME(REGNO (stack_limit_rtx
)));
546 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
547 warning ("stack limit expression is not supported");
550 if (current_frame
.reg_no
<= 2)
552 /* Store each separately in the same order moveml uses.
553 Using two movel instructions instead of a single moveml
554 is about 15% faster for the 68020 and 68030 at no expense
559 for (i
= 0; i
< 16; i
++)
560 if (current_frame
.reg_rev_mask
& (1 << i
))
562 asm_fprintf (stream
, MOTOROLA
?
563 "\t%Omove.l %s,-(%Rsp)\n" :
564 "\tmovel %s,%Rsp@-\n",
565 M68K_REGNAME(15 - i
));
566 if (dwarf2out_do_frame ())
568 char *l
= (char *) dwarf2out_cfi_label ();
571 if (! frame_pointer_needed
)
572 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
573 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
577 else if (current_frame
.reg_rev_mask
)
580 /* The ColdFire does not support the predecrement form of the
581 MOVEM instruction, so we must adjust the stack pointer and
582 then use the plain address register indirect mode.
583 The required register save space was combined earlier with
584 the fsize_with_regs amount. */
586 asm_fprintf (stream
, MOTOROLA
?
587 "\tmovm.l %I0x%x,(%Rsp)\n" :
588 "\tmoveml %I0x%x,%Rsp@\n",
589 current_frame
.reg_mask
);
591 asm_fprintf (stream
, MOTOROLA
?
592 "\tmovm.l %I0x%x,-(%Rsp)\n" :
593 "\tmoveml %I0x%x,%Rsp@-\n",
594 current_frame
.reg_rev_mask
);
595 if (dwarf2out_do_frame ())
597 char *l
= (char *) dwarf2out_cfi_label ();
600 cfa_offset
+= current_frame
.reg_no
* 4;
601 if (! frame_pointer_needed
)
602 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
603 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
604 if (current_frame
.reg_mask
& (1 << regno
))
605 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
608 if (!TARGET_SEP_DATA
&& flag_pic
&&
609 (current_function_uses_pic_offset_table
||
610 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
612 if (TARGET_ID_SHARED_LIBRARY
)
614 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
615 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
616 m68k_library_id_string
,
617 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
622 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
623 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
626 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
627 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
628 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
629 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
630 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
636 /* Return true if this function's epilogue can be output as RTL. */
639 use_return_insn (void)
641 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
644 /* We can output the epilogue as RTL only if no registers need to be
646 m68k_compute_frame_layout();
647 return current_frame
.reg_no
? false : true;
650 /* This function generates the assembly code for function exit,
651 on machines that need it.
653 The function epilogue should not depend on the current stack pointer!
654 It should use the frame pointer only, if there is a frame pointer.
655 This is mandatory because of alloca; we also take advantage of it to
656 omit stack adjustments before returning. */
659 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
661 HOST_WIDE_INT fsize
, fsize_with_regs
;
663 bool restore_from_sp
= false;
664 rtx insn
= get_last_insn ();
666 m68k_compute_frame_layout();
668 /* If the last insn was a BARRIER, we don't have to write any code. */
669 if (GET_CODE (insn
) == NOTE
)
670 insn
= prev_nonnote_insn (insn
);
671 if (insn
&& GET_CODE (insn
) == BARRIER
)
673 /* Output just a no-op so that debuggers don't get confused
674 about which function the pc is in at this address. */
675 fprintf (stream
, "\tnop\n");
679 #ifdef FUNCTION_EXTRA_EPILOGUE
680 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
683 fsize
= current_frame
.size
;
685 /* FIXME : leaf_function_p below is too strong.
686 What we really need to know there is if there could be pending
687 stack adjustment needed at that point. */
688 restore_from_sp
= ! frame_pointer_needed
689 || (! current_function_calls_alloca
&& leaf_function_p ());
691 /* fsize_with_regs is the size we need to adjust the sp when
692 popping the frame. */
693 fsize_with_regs
= fsize
;
695 /* Because the ColdFire doesn't support moveml with
696 complex address modes, we must adjust the stack manually
697 after restoring registers. When the frame pointer isn't used,
698 we can merge movem adjustment into frame unlinking
699 made immediately after it. */
700 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
701 fsize_with_regs
+= current_frame
.reg_no
* 4;
703 if (current_frame
.offset
+ fsize
>= 0x8000
705 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
707 /* Because the ColdFire doesn't support moveml with
708 complex address modes we make an extra correction here. */
710 fsize
+= current_frame
.offset
;
712 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
713 fsize
= 0, big
= true;
715 if (current_frame
.reg_no
<= 2)
717 /* Restore each separately in the same order moveml does.
718 Using two movel instructions instead of a single moveml
719 is about 15% faster for the 68020 and 68030 at no expense
723 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
725 for (i
= 0; i
< 16; i
++)
726 if (current_frame
.reg_mask
& (1 << i
))
731 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
733 M68K_REGNAME(FRAME_POINTER_REGNUM
),
736 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
737 M68K_REGNAME(FRAME_POINTER_REGNUM
),
741 else if (restore_from_sp
)
742 asm_fprintf (stream
, MOTOROLA
?
743 "\t%Omove.l (%Rsp)+,%s\n" :
744 "\tmovel %Rsp@+,%s\n",
749 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
751 M68K_REGNAME(FRAME_POINTER_REGNUM
),
754 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
755 M68K_REGNAME(FRAME_POINTER_REGNUM
),
762 else if (current_frame
.reg_mask
)
764 /* The ColdFire requires special handling due to its limited moveml insn. */
769 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
770 M68K_REGNAME(FRAME_POINTER_REGNUM
));
771 asm_fprintf (stream
, MOTOROLA
?
772 "\tmovm.l (%Ra1),%I0x%x\n" :
773 "\tmoveml %Ra1@,%I0x%x\n",
774 current_frame
.reg_mask
);
776 else if (restore_from_sp
)
777 asm_fprintf (stream
, MOTOROLA
?
778 "\tmovm.l (%Rsp),%I0x%x\n" :
779 "\tmoveml %Rsp@,%I0x%x\n",
780 current_frame
.reg_mask
);
784 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
785 current_frame
.offset
+ fsize
,
786 M68K_REGNAME(FRAME_POINTER_REGNUM
),
787 current_frame
.reg_mask
);
789 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
790 M68K_REGNAME(FRAME_POINTER_REGNUM
),
791 current_frame
.offset
+ fsize
,
792 current_frame
.reg_mask
);
795 else /* !TARGET_COLDFIRE */
800 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
801 current_frame
.offset
+ fsize
,
802 M68K_REGNAME(FRAME_POINTER_REGNUM
),
803 current_frame
.reg_mask
);
805 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
806 M68K_REGNAME(FRAME_POINTER_REGNUM
),
807 current_frame
.offset
+ fsize
,
808 current_frame
.reg_mask
);
810 else if (restore_from_sp
)
812 asm_fprintf (stream
, MOTOROLA
?
813 "\tmovm.l (%Rsp)+,%I0x%x\n" :
814 "\tmoveml %Rsp@+,%I0x%x\n",
815 current_frame
.reg_mask
);
820 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
821 current_frame
.offset
+ fsize
,
822 M68K_REGNAME(FRAME_POINTER_REGNUM
),
823 current_frame
.reg_mask
);
825 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
826 M68K_REGNAME(FRAME_POINTER_REGNUM
),
827 current_frame
.offset
+ fsize
,
828 current_frame
.reg_mask
);
832 if (current_frame
.fpu_rev_mask
)
837 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
838 current_frame
.foffset
+ fsize
,
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.fpu_rev_mask
);
842 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
843 M68K_REGNAME(FRAME_POINTER_REGNUM
),
844 current_frame
.foffset
+ fsize
,
845 current_frame
.fpu_rev_mask
);
847 else if (restore_from_sp
)
850 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
851 current_frame
.fpu_rev_mask
);
853 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
854 current_frame
.fpu_rev_mask
);
859 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
860 current_frame
.foffset
+ fsize
,
861 M68K_REGNAME(FRAME_POINTER_REGNUM
),
862 current_frame
.fpu_rev_mask
);
864 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
865 M68K_REGNAME(FRAME_POINTER_REGNUM
),
866 current_frame
.foffset
+ fsize
,
867 current_frame
.fpu_rev_mask
);
870 if (frame_pointer_needed
)
871 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
872 else if (fsize_with_regs
)
874 if (fsize_with_regs
<= 8)
876 if (!TARGET_COLDFIRE
)
877 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
880 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
883 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
885 /* On the CPU32 it is faster to use two addqw instructions to
886 add a small integer (8 < N <= 16) to a register. */
887 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
888 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
889 fsize_with_regs
- 8);
891 else if (fsize_with_regs
< 0x8000)
894 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
897 asm_fprintf (stream
, MOTOROLA
?
898 "\tlea (%wd,%Rsp),%Rsp\n" :
899 "\tlea %Rsp@(%wd),%Rsp\n",
903 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
905 if (current_function_calls_eh_return
)
906 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
907 if (m68k_interrupt_function_p (current_function_decl
))
908 fprintf (stream
, "\trte\n");
909 else if (current_function_pops_args
)
910 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
912 fprintf (stream
, "\trts\n");
915 /* Return true if X is a valid comparison operator for the dbcc
918 Note it rejects floating point comparison operators.
919 (In the future we could use Fdbcc).
921 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
924 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
926 switch (GET_CODE (x
))
928 case EQ
: case NE
: case GTU
: case LTU
:
932 /* Reject some when CC_NO_OVERFLOW is set. This may be over
934 case GT
: case LT
: case GE
: case LE
:
935 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
941 /* Return nonzero if flags are currently in the 68881 flag register. */
943 flags_in_68881 (void)
945 /* We could add support for these in the future */
946 return cc_status
.flags
& CC_IN_68881
;
949 /* Output a BSR instruction suitable for PIC code. */
951 m68k_output_pic_call(rtx dest
)
955 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
957 /* We output a BSR instruction if we're using -fpic or we're building for
958 * a target that supports long branches. If we're building -fPIC on the
959 * 68000, 68010 or ColdFire we generate one of two sequences:
960 * a shorter one that uses a GOT entry or a longer one that doesn't.
961 * We'll use the -Os command-line flag to decide which to generate.
962 * Both sequences take the same time to execute on the ColdFire.
964 else if (TARGET_PCREL
)
966 else if ((flag_pic
== 1) || TARGET_68020
)
968 out
= "bsr.l %0@PLTPC";
970 out
= "bsr %0@PLTPC";
972 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
973 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
975 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
977 output_asm_insn(out
, &dest
);
980 /* Output a dbCC; jCC sequence. Note we do not handle the
981 floating point version of this sequence (Fdbcc). We also
982 do not handle alternative conditions when CC_NO_OVERFLOW is
983 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
984 kick those out before we get here. */
987 output_dbcc_and_branch (rtx
*operands
)
989 switch (GET_CODE (operands
[3]))
992 output_asm_insn (MOTOROLA
?
993 "dbeq %0,%l1\n\tjbeq %l2" :
994 "dbeq %0,%l1\n\tjeq %l2",
999 output_asm_insn (MOTOROLA
?
1000 "dbne %0,%l1\n\tjbne %l2" :
1001 "dbne %0,%l1\n\tjne %l2",
1006 output_asm_insn (MOTOROLA
?
1007 "dbgt %0,%l1\n\tjbgt %l2" :
1008 "dbgt %0,%l1\n\tjgt %l2",
1013 output_asm_insn (MOTOROLA
?
1014 "dbhi %0,%l1\n\tjbhi %l2" :
1015 "dbhi %0,%l1\n\tjhi %l2",
1020 output_asm_insn (MOTOROLA
?
1021 "dblt %0,%l1\n\tjblt %l2" :
1022 "dblt %0,%l1\n\tjlt %l2",
1027 output_asm_insn (MOTOROLA
?
1028 "dbcs %0,%l1\n\tjbcs %l2" :
1029 "dbcs %0,%l1\n\tjcs %l2",
1034 output_asm_insn (MOTOROLA
?
1035 "dbge %0,%l1\n\tjbge %l2" :
1036 "dbge %0,%l1\n\tjge %l2",
1041 output_asm_insn (MOTOROLA
?
1042 "dbcc %0,%l1\n\tjbcc %l2" :
1043 "dbcc %0,%l1\n\tjcc %l2",
1048 output_asm_insn (MOTOROLA
?
1049 "dble %0,%l1\n\tjble %l2" :
1050 "dble %0,%l1\n\tjle %l2",
1055 output_asm_insn (MOTOROLA
?
1056 "dbls %0,%l1\n\tjbls %l2" :
1057 "dbls %0,%l1\n\tjls %l2",
1065 /* If the decrement is to be done in SImode, then we have
1066 to compensate for the fact that dbcc decrements in HImode. */
1067 switch (GET_MODE (operands
[0]))
1070 output_asm_insn (MOTOROLA
?
1071 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1072 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1085 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1088 enum rtx_code op_code
= GET_CODE (op
);
1090 /* This does not produce a useful cc. */
1093 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1094 below. Swap the operands and change the op if these requirements
1095 are not fulfilled. */
1096 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1100 operand1
= operand2
;
1102 op_code
= swap_condition (op_code
);
1104 loperands
[0] = operand1
;
1105 if (GET_CODE (operand1
) == REG
)
1106 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1108 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1109 if (operand2
!= const0_rtx
)
1111 loperands
[2] = operand2
;
1112 if (GET_CODE (operand2
) == REG
)
1113 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1115 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1117 loperands
[4] = gen_label_rtx ();
1118 if (operand2
!= const0_rtx
)
1120 output_asm_insn (MOTOROLA
?
1121 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1122 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1127 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1128 output_asm_insn ("tst%.l %0", loperands
);
1131 output_asm_insn ("cmp%.w #0,%0", loperands
);
1134 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1136 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1137 output_asm_insn ("tst%.l %1", loperands
);
1139 output_asm_insn ("cmp%.w #0,%1", loperands
);
1142 loperands
[5] = dest
;
1147 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1148 CODE_LABEL_NUMBER (loperands
[4]));
1149 output_asm_insn ("seq %5", loperands
);
1153 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1154 CODE_LABEL_NUMBER (loperands
[4]));
1155 output_asm_insn ("sne %5", loperands
);
1159 loperands
[6] = gen_label_rtx ();
1160 output_asm_insn (MOTOROLA
?
1161 "shi %5\n\tjbra %l6" :
1162 "shi %5\n\tjra %l6",
1164 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1165 CODE_LABEL_NUMBER (loperands
[4]));
1166 output_asm_insn ("sgt %5", loperands
);
1167 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1168 CODE_LABEL_NUMBER (loperands
[6]));
1172 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1173 CODE_LABEL_NUMBER (loperands
[4]));
1174 output_asm_insn ("shi %5", loperands
);
1178 loperands
[6] = gen_label_rtx ();
1179 output_asm_insn (MOTOROLA
?
1180 "scs %5\n\tjbra %l6" :
1181 "scs %5\n\tjra %l6",
1183 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1184 CODE_LABEL_NUMBER (loperands
[4]));
1185 output_asm_insn ("slt %5", loperands
);
1186 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1187 CODE_LABEL_NUMBER (loperands
[6]));
1191 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1192 CODE_LABEL_NUMBER (loperands
[4]));
1193 output_asm_insn ("scs %5", loperands
);
1197 loperands
[6] = gen_label_rtx ();
1198 output_asm_insn (MOTOROLA
?
1199 "scc %5\n\tjbra %l6" :
1200 "scc %5\n\tjra %l6",
1202 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1203 CODE_LABEL_NUMBER (loperands
[4]));
1204 output_asm_insn ("sge %5", loperands
);
1205 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1206 CODE_LABEL_NUMBER (loperands
[6]));
1210 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1211 CODE_LABEL_NUMBER (loperands
[4]));
1212 output_asm_insn ("scc %5", loperands
);
1216 loperands
[6] = gen_label_rtx ();
1217 output_asm_insn (MOTOROLA
?
1218 "sls %5\n\tjbra %l6" :
1219 "sls %5\n\tjra %l6",
1221 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1222 CODE_LABEL_NUMBER (loperands
[4]));
1223 output_asm_insn ("sle %5", loperands
);
1224 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1225 CODE_LABEL_NUMBER (loperands
[6]));
1229 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1230 CODE_LABEL_NUMBER (loperands
[4]));
1231 output_asm_insn ("sls %5", loperands
);
1241 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1243 operands
[0] = countop
;
1244 operands
[1] = dataop
;
1246 if (GET_CODE (countop
) == CONST_INT
)
1248 register int count
= INTVAL (countop
);
1249 /* If COUNT is bigger than size of storage unit in use,
1250 advance to the containing unit of same size. */
1251 if (count
> signpos
)
1253 int offset
= (count
& ~signpos
) / 8;
1254 count
= count
& signpos
;
1255 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1257 if (count
== signpos
)
1258 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1260 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1262 /* These three statements used to use next_insns_test_no...
1263 but it appears that this should do the same job. */
1265 && next_insn_tests_no_inequality (insn
))
1268 && next_insn_tests_no_inequality (insn
))
1271 && next_insn_tests_no_inequality (insn
))
1274 cc_status
.flags
= CC_NOT_NEGATIVE
;
1276 return "btst %0,%1";
1279 /* Legitimize PIC addresses. If the address is already
1280 position-independent, we return ORIG. Newly generated
1281 position-independent addresses go to REG. If we need more
1282 than one register, we lose.
1284 An address is legitimized by making an indirect reference
1285 through the Global Offset Table with the name of the symbol
1288 The assembler and linker are responsible for placing the
1289 address of the symbol in the GOT. The function prologue
1290 is responsible for initializing a5 to the starting address
1293 The assembler is also responsible for translating a symbol name
1294 into a constant displacement from the start of the GOT.
1296 A quick example may make things a little clearer:
1298 When not generating PIC code to store the value 12345 into _foo
1299 we would generate the following code:
1303 When generating PIC two transformations are made. First, the compiler
1304 loads the address of foo into a register. So the first transformation makes:
1309 The code in movsi will intercept the lea instruction and call this
1310 routine which will transform the instructions into:
1312 movel a5@(_foo:w), a0
1316 That (in a nutshell) is how *all* symbol and label references are
1320 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1325 /* First handle a simple SYMBOL_REF or LABEL_REF */
1326 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1331 pic_ref
= gen_rtx_MEM (Pmode
,
1332 gen_rtx_PLUS (Pmode
,
1333 pic_offset_table_rtx
, orig
));
1334 current_function_uses_pic_offset_table
= 1;
1335 MEM_READONLY_P (pic_ref
) = 1;
1336 emit_move_insn (reg
, pic_ref
);
1339 else if (GET_CODE (orig
) == CONST
)
1343 /* Make sure this has not already been legitimized. */
1344 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1345 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1351 /* legitimize both operands of the PLUS */
1352 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1354 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1355 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1356 base
== reg
? 0 : reg
);
1360 if (GET_CODE (orig
) == CONST_INT
)
1361 return plus_constant (base
, INTVAL (orig
));
1362 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1363 /* Likewise, should we set special REG_NOTEs here? */
1369 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1371 static CONST_METHOD
const_method (rtx
);
1373 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1376 const_method (rtx constant
)
1381 i
= INTVAL (constant
);
1385 /* The ColdFire doesn't have byte or word operations. */
1386 /* FIXME: This may not be useful for the m68060 either. */
1387 if (!TARGET_COLDFIRE
)
1389 /* if -256 < N < 256 but N is not in range for a moveq
1390 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1391 if (USE_MOVQ (i
^ 0xff))
1393 /* Likewise, try with not.w */
1394 if (USE_MOVQ (i
^ 0xffff))
1396 /* This is the only value where neg.w is useful */
1401 /* Try also with swap. */
1403 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1408 /* Try using MVZ/MVS with an immediate value to load constants. */
1409 if (i
>= 0 && i
<= 65535)
1411 if (i
>= -32768 && i
<= 32767)
1415 /* Otherwise, use move.l */
1420 const_int_cost (rtx constant
)
1422 switch (const_method (constant
))
1425 /* Constants between -128 and 127 are cheap due to moveq */
1433 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1443 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1448 /* Constant zero is super cheap due to clr instruction. */
1449 if (x
== const0_rtx
)
1452 *total
= const_int_cost (x
);
1462 /* Make 0.0 cheaper than other floating constants to
1463 encourage creating tstsf and tstdf insns. */
1464 if (outer_code
== COMPARE
1465 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1471 /* These are vaguely right for a 68020. */
1472 /* The costs for long multiply have been adjusted to work properly
1473 in synth_mult on the 68020, relative to an average of the time
1474 for add and the time for shift, taking away a little more because
1475 sometimes move insns are needed. */
1476 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1477 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 : TARGET_COLDFIRE ? 10 : 13)
1478 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1479 (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
1480 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1483 /* An lea costs about three times as much as a simple add. */
1484 if (GET_MODE (x
) == SImode
1485 && GET_CODE (XEXP (x
, 1)) == REG
1486 && GET_CODE (XEXP (x
, 0)) == MULT
1487 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1488 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1489 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1490 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1491 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1493 /* lea an@(dx:l:i),am */
1494 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1504 *total
= COSTS_N_INSNS(1);
1507 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1509 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1511 if (INTVAL (XEXP (x
, 1)) < 16)
1512 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1514 /* We're using clrw + swap for these cases. */
1515 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1518 *total
= COSTS_N_INSNS (10); /* worst case */
1521 /* A shift by a big integer takes an extra instruction. */
1522 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1523 && (INTVAL (XEXP (x
, 1)) == 16))
1525 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1528 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1529 && !(INTVAL (XEXP (x
, 1)) > 0
1530 && INTVAL (XEXP (x
, 1)) <= 8))
1532 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1538 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1539 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1540 && GET_MODE (x
) == SImode
)
1541 *total
= COSTS_N_INSNS (MULW_COST
);
1542 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1543 *total
= COSTS_N_INSNS (MULW_COST
);
1545 *total
= COSTS_N_INSNS (MULL_COST
);
1552 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1553 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1554 else if (TARGET_CF_HWDIV
)
1555 *total
= COSTS_N_INSNS (18);
1557 *total
= COSTS_N_INSNS (43); /* div.l */
1566 output_move_const_into_data_reg (rtx
*operands
)
1570 i
= INTVAL (operands
[1]);
1571 switch (const_method (operands
[1]))
1574 return "mvsw %1,%0";
1576 return "mvzw %1,%0";
1578 return "moveq %1,%0";
1581 operands
[1] = GEN_INT (i
^ 0xff);
1582 return "moveq %1,%0\n\tnot%.b %0";
1585 operands
[1] = GEN_INT (i
^ 0xffff);
1586 return "moveq %1,%0\n\tnot%.w %0";
1589 return "moveq #-128,%0\n\tneg%.w %0";
1594 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1595 return "moveq %1,%0\n\tswap %0";
1598 return "move%.l %1,%0";
1604 /* Return 1 if 'constant' can be represented by
1605 mov3q on a ColdFire V4 core. */
1607 valid_mov3q_const (rtx constant
)
1611 if (TARGET_CFV4
&& GET_CODE (constant
) == CONST_INT
)
1613 i
= INTVAL (constant
);
1614 if ((i
== -1) || (i
>= 1 && i
<= 7))
1622 output_move_simode_const (rtx
*operands
)
1624 if (operands
[1] == const0_rtx
1625 && (DATA_REG_P (operands
[0])
1626 || GET_CODE (operands
[0]) == MEM
)
1627 /* clr insns on 68000 read before writing.
1628 This isn't so on the 68010, but we have no TARGET_68010. */
1629 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1630 || !(GET_CODE (operands
[0]) == MEM
1631 && MEM_VOLATILE_P (operands
[0]))))
1633 else if ((GET_MODE (operands
[0]) == SImode
)
1634 && valid_mov3q_const (operands
[1]))
1635 return "mov3q%.l %1,%0";
1636 else if (operands
[1] == const0_rtx
1637 && ADDRESS_REG_P (operands
[0]))
1638 return "sub%.l %0,%0";
1639 else if (DATA_REG_P (operands
[0]))
1640 return output_move_const_into_data_reg (operands
);
1641 else if (ADDRESS_REG_P (operands
[0])
1642 && INTVAL (operands
[1]) < 0x8000
1643 && INTVAL (operands
[1]) >= -0x8000)
1645 if (valid_mov3q_const (operands
[1]))
1646 return "mov3q%.l %1,%0";
1647 return "move%.w %1,%0";
1649 else if (GET_CODE (operands
[0]) == MEM
1650 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1651 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1652 && INTVAL (operands
[1]) < 0x8000
1653 && INTVAL (operands
[1]) >= -0x8000)
1655 if (valid_mov3q_const (operands
[1]))
1656 return "mov3q%.l %1,%-";
1659 return "move%.l %1,%0";
1663 output_move_simode (rtx
*operands
)
1665 if (GET_CODE (operands
[1]) == CONST_INT
)
1666 return output_move_simode_const (operands
);
1667 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1668 || GET_CODE (operands
[1]) == CONST
)
1669 && push_operand (operands
[0], SImode
))
1671 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1672 || GET_CODE (operands
[1]) == CONST
)
1673 && ADDRESS_REG_P (operands
[0]))
1674 return "lea %a1,%0";
1675 return "move%.l %1,%0";
1679 output_move_himode (rtx
*operands
)
1681 if (GET_CODE (operands
[1]) == CONST_INT
)
1683 if (operands
[1] == const0_rtx
1684 && (DATA_REG_P (operands
[0])
1685 || GET_CODE (operands
[0]) == MEM
)
1686 /* clr insns on 68000 read before writing.
1687 This isn't so on the 68010, but we have no TARGET_68010. */
1688 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1689 || !(GET_CODE (operands
[0]) == MEM
1690 && MEM_VOLATILE_P (operands
[0]))))
1692 else if (operands
[1] == const0_rtx
1693 && ADDRESS_REG_P (operands
[0]))
1694 return "sub%.l %0,%0";
1695 else if (DATA_REG_P (operands
[0])
1696 && INTVAL (operands
[1]) < 128
1697 && INTVAL (operands
[1]) >= -128)
1699 return "moveq %1,%0";
1701 else if (INTVAL (operands
[1]) < 0x8000
1702 && INTVAL (operands
[1]) >= -0x8000)
1703 return "move%.w %1,%0";
1705 else if (CONSTANT_P (operands
[1]))
1706 return "move%.l %1,%0";
1707 /* Recognize the insn before a tablejump, one that refers
1708 to a table of offsets. Such an insn will need to refer
1709 to a label on the insn. So output one. Use the label-number
1710 of the table of offsets to generate this label. This code,
1711 and similar code below, assumes that there will be at most one
1712 reference to each table. */
1713 if (GET_CODE (operands
[1]) == MEM
1714 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1715 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1716 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1718 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1720 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1721 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1723 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1724 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1726 return "move%.w %1,%0";
1730 output_move_qimode (rtx
*operands
)
1732 /* 68k family always modifies the stack pointer by at least 2, even for
1733 byte pushes. The 5200 (ColdFire) does not do this. */
1734 if (GET_CODE (operands
[0]) == MEM
1735 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1736 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1737 && ! ADDRESS_REG_P (operands
[1])
1738 && ! TARGET_COLDFIRE
)
1739 /* generated by pushqi1 pattern now */
1742 /* clr and st insns on 68000 read before writing.
1743 This isn't so on the 68010, but we have no TARGET_68010. */
1744 if (!ADDRESS_REG_P (operands
[0])
1745 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1746 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1748 if (operands
[1] == const0_rtx
)
1750 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1751 && GET_CODE (operands
[1]) == CONST_INT
1752 && (INTVAL (operands
[1]) & 255) == 255)
1758 if (GET_CODE (operands
[1]) == CONST_INT
1759 && DATA_REG_P (operands
[0])
1760 && INTVAL (operands
[1]) < 128
1761 && INTVAL (operands
[1]) >= -128)
1763 return "moveq %1,%0";
1765 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1766 return "sub%.l %0,%0";
1767 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1768 return "move%.l %1,%0";
1769 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1770 from address registers. */
1771 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1772 return "move%.w %1,%0";
1773 return "move%.b %1,%0";
1777 output_move_stricthi (rtx
*operands
)
1779 if (operands
[1] == const0_rtx
1780 /* clr insns on 68000 read before writing.
1781 This isn't so on the 68010, but we have no TARGET_68010. */
1782 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1783 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1785 return "move%.w %1,%0";
1789 output_move_strictqi (rtx
*operands
)
1791 if (operands
[1] == const0_rtx
1792 /* clr insns on 68000 read before writing.
1793 This isn't so on the 68010, but we have no TARGET_68010. */
1794 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1795 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1797 return "move%.b %1,%0";
1800 /* Return the best assembler insn template
1801 for moving operands[1] into operands[0] as a fullword. */
1804 singlemove_string (rtx
*operands
)
1806 if (GET_CODE (operands
[1]) == CONST_INT
)
1807 return output_move_simode_const (operands
);
1808 return "move%.l %1,%0";
1812 /* Output assembler code to perform a doubleword move insn
1813 with operands OPERANDS. */
1816 output_move_double (rtx
*operands
)
1820 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1825 rtx addreg0
= 0, addreg1
= 0;
1826 int dest_overlapped_low
= 0;
1827 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1832 /* First classify both operands. */
1834 if (REG_P (operands
[0]))
1836 else if (offsettable_memref_p (operands
[0]))
1838 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1840 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1842 else if (GET_CODE (operands
[0]) == MEM
)
1847 if (REG_P (operands
[1]))
1849 else if (CONSTANT_P (operands
[1]))
1851 else if (offsettable_memref_p (operands
[1]))
1853 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1855 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1857 else if (GET_CODE (operands
[1]) == MEM
)
1862 /* Check for the cases that the operand constraints are not
1863 supposed to allow to happen. Abort if we get one,
1864 because generating code for these cases is painful. */
1866 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1869 /* If one operand is decrementing and one is incrementing
1870 decrement the former register explicitly
1871 and change that operand into ordinary indexing. */
1873 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1875 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1877 output_asm_insn ("sub%.l #12,%0", operands
);
1879 output_asm_insn ("subq%.l #8,%0", operands
);
1880 if (GET_MODE (operands
[1]) == XFmode
)
1881 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1882 else if (GET_MODE (operands
[0]) == DFmode
)
1883 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1885 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1888 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1890 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1892 output_asm_insn ("sub%.l #12,%1", operands
);
1894 output_asm_insn ("subq%.l #8,%1", operands
);
1895 if (GET_MODE (operands
[1]) == XFmode
)
1896 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1897 else if (GET_MODE (operands
[1]) == DFmode
)
1898 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1900 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1904 /* If an operand is an unoffsettable memory ref, find a register
1905 we can increment temporarily to make it refer to the second word. */
1907 if (optype0
== MEMOP
)
1908 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1910 if (optype1
== MEMOP
)
1911 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1913 /* Ok, we can do one word at a time.
1914 Normally we do the low-numbered word first,
1915 but if either operand is autodecrementing then we
1916 do the high-numbered word first.
1918 In either case, set up in LATEHALF the operands to use
1919 for the high-numbered word and in some cases alter the
1920 operands in OPERANDS to be suitable for the low-numbered word. */
1924 if (optype0
== REGOP
)
1926 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1927 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1929 else if (optype0
== OFFSOP
)
1931 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
1932 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
1936 middlehalf
[0] = operands
[0];
1937 latehalf
[0] = operands
[0];
1940 if (optype1
== REGOP
)
1942 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1943 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1945 else if (optype1
== OFFSOP
)
1947 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
1948 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
1950 else if (optype1
== CNSTOP
)
1952 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1957 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1958 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1959 operands
[1] = GEN_INT (l
[0]);
1960 middlehalf
[1] = GEN_INT (l
[1]);
1961 latehalf
[1] = GEN_INT (l
[2]);
1963 else if (CONSTANT_P (operands
[1]))
1965 /* actually, no non-CONST_DOUBLE constant should ever
1968 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1969 latehalf
[1] = constm1_rtx
;
1971 latehalf
[1] = const0_rtx
;
1976 middlehalf
[1] = operands
[1];
1977 latehalf
[1] = operands
[1];
1981 /* size is not 12: */
1983 if (optype0
== REGOP
)
1984 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1985 else if (optype0
== OFFSOP
)
1986 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
1988 latehalf
[0] = operands
[0];
1990 if (optype1
== REGOP
)
1991 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1992 else if (optype1
== OFFSOP
)
1993 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
1994 else if (optype1
== CNSTOP
)
1995 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1997 latehalf
[1] = operands
[1];
2000 /* If insn is effectively movd N(sp),-(sp) then we will do the
2001 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2002 for the low word as well, to compensate for the first decrement of sp. */
2003 if (optype0
== PUSHOP
2004 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2005 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2006 operands
[1] = middlehalf
[1] = latehalf
[1];
2008 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2009 if the upper part of reg N does not appear in the MEM, arrange to
2010 emit the move late-half first. Otherwise, compute the MEM address
2011 into the upper part of N and use that as a pointer to the memory
2013 if (optype0
== REGOP
2014 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2016 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2018 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2019 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2021 /* If both halves of dest are used in the src memory address,
2022 compute the address into latehalf of dest.
2023 Note that this can't happen if the dest is two data regs. */
2025 xops
[0] = latehalf
[0];
2026 xops
[1] = XEXP (operands
[1], 0);
2027 output_asm_insn ("lea %a1,%0", xops
);
2028 if (GET_MODE (operands
[1]) == XFmode
)
2030 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2031 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2032 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2036 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2037 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2041 && reg_overlap_mentioned_p (middlehalf
[0],
2042 XEXP (operands
[1], 0)))
2044 /* Check for two regs used by both source and dest.
2045 Note that this can't happen if the dest is all data regs.
2046 It can happen if the dest is d6, d7, a0.
2047 But in that case, latehalf is an addr reg, so
2048 the code at compadr does ok. */
2050 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2051 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2054 /* JRV says this can't happen: */
2055 if (addreg0
|| addreg1
)
2058 /* Only the middle reg conflicts; simply put it last. */
2059 output_asm_insn (singlemove_string (operands
), operands
);
2060 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2061 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2064 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2065 /* If the low half of dest is mentioned in the source memory
2066 address, the arrange to emit the move late half first. */
2067 dest_overlapped_low
= 1;
2070 /* If one or both operands autodecrementing,
2071 do the two words, high-numbered first. */
2073 /* Likewise, the first move would clobber the source of the second one,
2074 do them in the other order. This happens only for registers;
2075 such overlap can't happen in memory unless the user explicitly
2076 sets it up, and that is an undefined circumstance. */
2078 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2079 || (optype0
== REGOP
&& optype1
== REGOP
2080 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2081 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2082 || dest_overlapped_low
)
2084 /* Make any unoffsettable addresses point at high-numbered word. */
2088 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2090 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2095 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2097 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2101 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2103 /* Undo the adds we just did. */
2105 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2107 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2111 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2113 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2115 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2118 /* Do low-numbered word. */
2119 return singlemove_string (operands
);
2122 /* Normal case: do the two words, low-numbered first. */
2124 output_asm_insn (singlemove_string (operands
), operands
);
2126 /* Do the middle one of the three words for long double */
2130 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2132 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2134 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2137 /* Make any unoffsettable addresses point at high-numbered word. */
2139 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2141 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2144 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2146 /* Undo the adds we just did. */
2150 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2152 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2157 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2159 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2165 /* Return a REG that occurs in ADDR with coefficient 1.
2166 ADDR can be effectively incremented by incrementing REG. */
2169 find_addr_reg (rtx addr
)
2171 while (GET_CODE (addr
) == PLUS
)
2173 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2174 addr
= XEXP (addr
, 0);
2175 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2176 addr
= XEXP (addr
, 1);
2177 else if (CONSTANT_P (XEXP (addr
, 0)))
2178 addr
= XEXP (addr
, 1);
2179 else if (CONSTANT_P (XEXP (addr
, 1)))
2180 addr
= XEXP (addr
, 0);
2184 if (GET_CODE (addr
) == REG
)
2189 /* Output assembler code to perform a 32-bit 3-operand add. */
2192 output_addsi3 (rtx
*operands
)
2194 if (! operands_match_p (operands
[0], operands
[1]))
2196 if (!ADDRESS_REG_P (operands
[1]))
2198 rtx tmp
= operands
[1];
2200 operands
[1] = operands
[2];
2204 /* These insns can result from reloads to access
2205 stack slots over 64k from the frame pointer. */
2206 if (GET_CODE (operands
[2]) == CONST_INT
2207 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2208 return "move%.l %2,%0\n\tadd%.l %1,%0";
2209 if (GET_CODE (operands
[2]) == REG
)
2210 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2211 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2213 if (GET_CODE (operands
[2]) == CONST_INT
)
2215 if (INTVAL (operands
[2]) > 0
2216 && INTVAL (operands
[2]) <= 8)
2217 return "addq%.l %2,%0";
2218 if (INTVAL (operands
[2]) < 0
2219 && INTVAL (operands
[2]) >= -8)
2221 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2222 return "subq%.l %2,%0";
2224 /* On the CPU32 it is faster to use two addql instructions to
2225 add a small integer (8 < N <= 16) to a register.
2226 Likewise for subql. */
2227 if (TARGET_CPU32
&& REG_P (operands
[0]))
2229 if (INTVAL (operands
[2]) > 8
2230 && INTVAL (operands
[2]) <= 16)
2232 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2233 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2235 if (INTVAL (operands
[2]) < -8
2236 && INTVAL (operands
[2]) >= -16)
2238 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2239 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2242 if (ADDRESS_REG_P (operands
[0])
2243 && INTVAL (operands
[2]) >= -0x8000
2244 && INTVAL (operands
[2]) < 0x8000)
2247 return "add%.w %2,%0";
2249 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2252 return "add%.l %2,%0";
2255 /* Store in cc_status the expressions that the condition codes will
2256 describe after execution of an instruction whose pattern is EXP.
2257 Do not alter them if the instruction would not alter the cc's. */
2259 /* On the 68000, all the insns to store in an address register fail to
2260 set the cc's. However, in some cases these instructions can make it
2261 possibly invalid to use the saved cc's. In those cases we clear out
2262 some or all of the saved cc's so they won't be used. */
2265 notice_update_cc (rtx exp
, rtx insn
)
2267 if (GET_CODE (exp
) == SET
)
2269 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2273 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2275 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2276 cc_status
.value1
= 0;
2277 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2278 cc_status
.value2
= 0;
2280 else if (!FP_REG_P (SET_DEST (exp
))
2281 && SET_DEST (exp
) != cc0_rtx
2282 && (FP_REG_P (SET_SRC (exp
))
2283 || GET_CODE (SET_SRC (exp
)) == FIX
2284 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2285 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2289 /* A pair of move insns doesn't produce a useful overall cc. */
2290 else if (!FP_REG_P (SET_DEST (exp
))
2291 && !FP_REG_P (SET_SRC (exp
))
2292 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2293 && (GET_CODE (SET_SRC (exp
)) == REG
2294 || GET_CODE (SET_SRC (exp
)) == MEM
2295 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2299 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2303 else if (XEXP (exp
, 0) != pc_rtx
)
2305 cc_status
.flags
= 0;
2306 cc_status
.value1
= XEXP (exp
, 0);
2307 cc_status
.value2
= XEXP (exp
, 1);
2310 else if (GET_CODE (exp
) == PARALLEL
2311 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2313 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2315 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2317 cc_status
.flags
= 0;
2318 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2319 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2324 if (cc_status
.value2
!= 0
2325 && ADDRESS_REG_P (cc_status
.value2
)
2326 && GET_MODE (cc_status
.value2
) == QImode
)
2328 if (cc_status
.value2
!= 0)
2329 switch (GET_CODE (cc_status
.value2
))
2331 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2332 case ROTATE
: case ROTATERT
:
2333 /* These instructions always clear the overflow bit, and set
2334 the carry to the bit shifted out. */
2335 /* ??? We don't currently have a way to signal carry not valid,
2336 nor do we check for it in the branch insns. */
2340 case PLUS
: case MINUS
: case MULT
:
2341 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2342 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2343 cc_status
.flags
|= CC_NO_OVERFLOW
;
2346 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2347 ends with a move insn moving r2 in r2's mode.
2348 Thus, the cc's are set for r2.
2349 This can set N bit spuriously. */
2350 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2355 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2357 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2358 cc_status
.value2
= 0;
2359 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2360 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2361 cc_status
.flags
= CC_IN_68881
;
2365 output_move_const_double (rtx
*operands
)
2367 int code
= standard_68881_constant_p (operands
[1]);
2371 static char buf
[40];
2373 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2376 return "fmove%.d %1,%0";
2380 output_move_const_single (rtx
*operands
)
2382 int code
= standard_68881_constant_p (operands
[1]);
2386 static char buf
[40];
2388 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2391 return "fmove%.s %f1,%0";
2394 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2395 from the "fmovecr" instruction.
2396 The value, anded with 0xff, gives the code to use in fmovecr
2397 to get the desired constant. */
2399 /* This code has been fixed for cross-compilation. */
2401 static int inited_68881_table
= 0;
2403 static const char *const strings_68881
[7] = {
2413 static const int codes_68881
[7] = {
2423 REAL_VALUE_TYPE values_68881
[7];
2425 /* Set up values_68881 array by converting the decimal values
2426 strings_68881 to binary. */
2429 init_68881_table (void)
2433 enum machine_mode mode
;
2436 for (i
= 0; i
< 7; i
++)
2440 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2441 values_68881
[i
] = r
;
2443 inited_68881_table
= 1;
2447 standard_68881_constant_p (rtx x
)
2452 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2453 used at all on those chips. */
2454 if (TARGET_68040
|| TARGET_68060
)
2457 if (! inited_68881_table
)
2458 init_68881_table ();
2460 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2462 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2464 for (i
= 0; i
< 6; i
++)
2466 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2467 return (codes_68881
[i
]);
2470 if (GET_MODE (x
) == SFmode
)
2473 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2474 return (codes_68881
[6]);
2476 /* larger powers of ten in the constants ram are not used
2477 because they are not equal to a `double' C constant. */
2481 /* If X is a floating-point constant, return the logarithm of X base 2,
2482 or 0 if X is not a power of 2. */
2485 floating_exact_log2 (rtx x
)
2487 REAL_VALUE_TYPE r
, r1
;
2490 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2492 if (REAL_VALUES_LESS (r
, dconst1
))
2495 exp
= real_exponent (&r
);
2496 real_2expN (&r1
, exp
);
2497 if (REAL_VALUES_EQUAL (r1
, r
))
2503 /* A C compound statement to output to stdio stream STREAM the
2504 assembler syntax for an instruction operand X. X is an RTL
2507 CODE is a value that can be used to specify one of several ways
2508 of printing the operand. It is used when identical operands
2509 must be printed differently depending on the context. CODE
2510 comes from the `%' specification that was used to request
2511 printing of the operand. If the specification was just `%DIGIT'
2512 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2513 is the ASCII code for LTR.
2515 If X is a register, this macro should print the register's name.
2516 The names can be found in an array `reg_names' whose type is
2517 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2519 When the machine description has a specification `%PUNCT' (a `%'
2520 followed by a punctuation character), this macro is called with
2521 a null pointer for X and the punctuation character for CODE.
2523 The m68k specific codes are:
2525 '.' for dot needed in Motorola-style opcode names.
2526 '-' for an operand pushing on the stack:
2527 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2528 '+' for an operand pushing on the stack:
2529 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2530 '@' for a reference to the top word on the stack:
2531 sp@, (sp) or (%sp) depending on the style of syntax.
2532 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2533 but & in SGS syntax).
2534 '!' for the cc register (used in an `and to cc' insn).
2535 '$' for the letter `s' in an op code, but only on the 68040.
2536 '&' for the letter `d' in an op code, but only on the 68040.
2537 '/' for register prefix needed by longlong.h.
2539 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2540 'd' to force memory addressing to be absolute, not relative.
2541 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2542 'o' for operands to go directly to output_operand_address (bypassing
2543 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2544 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2545 or print pair of registers as rx:ry.
2550 print_operand (FILE *file
, rtx op
, int letter
)
2555 fprintf (file
, ".");
2557 else if (letter
== '#')
2558 asm_fprintf (file
, "%I");
2559 else if (letter
== '-')
2560 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2561 else if (letter
== '+')
2562 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2563 else if (letter
== '@')
2564 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2565 else if (letter
== '!')
2566 asm_fprintf (file
, "%Rfpcr");
2567 else if (letter
== '$')
2569 if (TARGET_68040_ONLY
)
2570 fprintf (file
, "s");
2572 else if (letter
== '&')
2574 if (TARGET_68040_ONLY
)
2575 fprintf (file
, "d");
2577 else if (letter
== '/')
2578 asm_fprintf (file
, "%R");
2579 else if (letter
== 'o')
2581 /* This is only for direct addresses with TARGET_PCREL */
2582 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2585 output_addr_const (file
, XEXP (op
, 0));
2587 else if (GET_CODE (op
) == REG
)
2590 /* Print out the second register name of a register pair.
2591 I.e., R (6) => 7. */
2592 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2594 fputs (M68K_REGNAME(REGNO (op
)), file
);
2596 else if (GET_CODE (op
) == MEM
)
2598 output_address (XEXP (op
, 0));
2599 if (letter
== 'd' && ! TARGET_68020
2600 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2601 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2602 && INTVAL (XEXP (op
, 0)) < 0x8000
2603 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2604 fprintf (file
, MOTOROLA
? ".l" : ":l");
2606 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2609 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2610 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2612 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2615 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2616 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2618 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2621 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2622 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2626 /* Use `print_operand_address' instead of `output_addr_const'
2627 to ensure that we print relevant PIC stuff. */
2628 asm_fprintf (file
, "%I");
2630 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2631 print_operand_address (file
, op
);
2633 output_addr_const (file
, op
);
2638 /* A C compound statement to output to stdio stream STREAM the
2639 assembler syntax for an instruction operand that is a memory
2640 reference whose address is ADDR. ADDR is an RTL expression.
2642 Note that this contains a kludge that knows that the only reason
2643 we have an address (plus (label_ref...) (reg...)) when not generating
2644 PIC code is in the insn before a tablejump, and we know that m68k.md
2645 generates a label LInnn: on such an insn.
2647 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2648 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2650 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2651 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2652 we want. This difference can be accommodated by using an assembler
2653 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2654 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2655 macro. See m68k/sgs.h for an example; for versions without the bug.
2656 Some assemblers refuse all the above solutions. The workaround is to
2657 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2660 They also do not like things like "pea 1.w", so we simple leave off
2661 the .w on small constants.
2663 This routine is responsible for distinguishing between -fpic and -fPIC
2664 style relocations in an address. When generating -fpic code the
2665 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
2666 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
2669 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2670 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2671 #else /* !MOTOROLA */
2672 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2673 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2674 #endif /* !MOTOROLA */
2677 print_operand_address (FILE *file
, rtx addr
)
2679 register rtx reg1
, reg2
, breg
, ireg
;
2682 switch (GET_CODE (addr
))
2685 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2688 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2689 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2692 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2693 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2696 reg1
= reg2
= ireg
= breg
= offset
= 0;
2697 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2699 offset
= XEXP (addr
, 0);
2700 addr
= XEXP (addr
, 1);
2702 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2704 offset
= XEXP (addr
, 1);
2705 addr
= XEXP (addr
, 0);
2707 if (GET_CODE (addr
) != PLUS
)
2711 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2713 reg1
= XEXP (addr
, 0);
2714 addr
= XEXP (addr
, 1);
2716 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2718 reg1
= XEXP (addr
, 1);
2719 addr
= XEXP (addr
, 0);
2721 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2723 reg1
= XEXP (addr
, 0);
2724 addr
= XEXP (addr
, 1);
2726 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2728 reg1
= XEXP (addr
, 1);
2729 addr
= XEXP (addr
, 0);
2731 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2733 reg1
= XEXP (addr
, 0);
2734 addr
= XEXP (addr
, 1);
2736 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2738 reg1
= XEXP (addr
, 1);
2739 addr
= XEXP (addr
, 0);
2741 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2742 || GET_CODE (addr
) == SIGN_EXTEND
)
2754 #if 0 /* for OLD_INDEXING */
2755 else if (GET_CODE (addr
) == PLUS
)
2757 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2759 reg2
= XEXP (addr
, 0);
2760 addr
= XEXP (addr
, 1);
2762 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2764 reg2
= XEXP (addr
, 1);
2765 addr
= XEXP (addr
, 0);
2777 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2778 || GET_CODE (reg1
) == MULT
))
2779 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2784 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2789 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2790 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2793 if (GET_CODE (ireg
) == MULT
)
2795 scale
= INTVAL (XEXP (ireg
, 1));
2796 ireg
= XEXP (ireg
, 0);
2798 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2800 ASM_OUTPUT_CASE_FETCH (file
,
2801 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2802 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2803 fprintf (file
, "w");
2807 ASM_OUTPUT_CASE_FETCH (file
,
2808 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2809 M68K_REGNAME(REGNO (ireg
)));
2810 fprintf (file
, "l");
2813 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2817 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2818 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2820 ASM_OUTPUT_CASE_FETCH (file
,
2821 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2822 M68K_REGNAME(REGNO (breg
)));
2823 fprintf (file
, "l)");
2826 if (ireg
!= 0 || breg
!= 0)
2833 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2841 output_addr_const (file
, addr
);
2842 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2844 fprintf (file
, "@GOT");
2846 fprintf (file
, ".w");
2849 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2853 else /* !MOTOROLA */
2855 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2858 output_addr_const (file
, addr
);
2859 if (breg
== pic_offset_table_rtx
)
2863 fprintf (file
, ":w"); break;
2865 fprintf (file
, ":l"); break;
2873 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2875 scale
= INTVAL (XEXP (ireg
, 1));
2876 ireg
= XEXP (ireg
, 0);
2878 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2879 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2880 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2882 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2883 M68K_REGNAME(REGNO (ireg
)));
2885 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2889 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2890 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2892 ASM_OUTPUT_CASE_FETCH (file
,
2893 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2894 M68K_REGNAME(REGNO (reg1
)));
2895 fprintf (file
, "l)");
2898 /* FALL-THROUGH (is this really what we want?) */
2900 if (GET_CODE (addr
) == CONST_INT
2901 && INTVAL (addr
) < 0x8000
2902 && INTVAL (addr
) >= -0x8000)
2904 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2906 else if (GET_CODE (addr
) == CONST_INT
)
2908 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2910 else if (TARGET_PCREL
)
2913 output_addr_const (file
, addr
);
2915 asm_fprintf (file
, ":w,%Rpc)");
2917 asm_fprintf (file
, ":l,%Rpc)");
2921 /* Special case for SYMBOL_REF if the symbol name ends in
2922 `.<letter>', this can be mistaken as a size suffix. Put
2923 the name in parentheses. */
2924 if (GET_CODE (addr
) == SYMBOL_REF
2925 && strlen (XSTR (addr
, 0)) > 2
2926 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
2929 output_addr_const (file
, addr
);
2933 output_addr_const (file
, addr
);
2939 /* Check for cases where a clr insns can be omitted from code using
2940 strict_low_part sets. For example, the second clrl here is not needed:
2941 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2943 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2944 insn we are checking for redundancy. TARGET is the register set by the
2948 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
2953 p
= prev_nonnote_insn (first_insn
);
2957 /* If it isn't an insn, then give up. */
2958 if (GET_CODE (p
) != INSN
)
2961 if (reg_set_p (target
, p
))
2963 rtx set
= single_set (p
);
2966 /* If it isn't an easy to recognize insn, then give up. */
2970 dest
= SET_DEST (set
);
2972 /* If this sets the entire target register to zero, then our
2973 first_insn is redundant. */
2974 if (rtx_equal_p (dest
, target
)
2975 && SET_SRC (set
) == const0_rtx
)
2977 else if (GET_CODE (dest
) == STRICT_LOW_PART
2978 && GET_CODE (XEXP (dest
, 0)) == REG
2979 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2980 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2981 <= GET_MODE_SIZE (mode
)))
2982 /* This is a strict low part set which modifies less than
2983 we are using, so it is safe. */
2989 p
= prev_nonnote_insn (p
);
2995 /* Operand predicates for implementing asymmetric pc-relative addressing
2996 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
2997 when used as a source operand, but not as a destination operand.
2999 We model this by restricting the meaning of the basic predicates
3000 (general_operand, memory_operand, etc) to forbid the use of this
3001 addressing mode, and then define the following predicates that permit
3002 this addressing mode. These predicates can then be used for the
3003 source operands of the appropriate instructions.
3005 n.b. While it is theoretically possible to change all machine patterns
3006 to use this addressing more where permitted by the architecture,
3007 it has only been implemented for "common" cases: SImode, HImode, and
3008 QImode operands, and only for the principle operations that would
3009 require this addressing mode: data movement and simple integer operations.
3011 In parallel with these new predicates, two new constraint letters
3012 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3013 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3014 In the pcrel case 's' is only valid in combination with 'a' registers.
3015 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3016 of how these constraints are used.
3018 The use of these predicates is strictly optional, though patterns that
3019 don't will cause an extra reload register to be allocated where one
3022 lea (abc:w,%pc),%a0 ; need to reload address
3023 moveq &1,%d1 ; since write to pc-relative space
3024 movel %d1,%a0@ ; is not allowed
3026 lea (abc:w,%pc),%a1 ; no need to reload address here
3027 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3029 For more info, consult tiemann@cygnus.com.
3032 All of the ugliness with predicates and constraints is due to the
3033 simple fact that the m68k does not allow a pc-relative addressing
3034 mode as a destination. gcc does not distinguish between source and
3035 destination addresses. Hence, if we claim that pc-relative address
3036 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3037 end up with invalid code. To get around this problem, we left
3038 pc-relative modes as invalid addresses, and then added special
3039 predicates and constraints to accept them.
3041 A cleaner way to handle this is to modify gcc to distinguish
3042 between source and destination addresses. We can then say that
3043 pc-relative is a valid source address but not a valid destination
3044 address, and hopefully avoid a lot of the predicate and constraint
3045 hackery. Unfortunately, this would be a pretty big change. It would
3046 be a useful change for a number of ports, but there aren't any current
3047 plans to undertake this.
3049 ***************************************************************************/
3053 output_andsi3 (rtx
*operands
)
3056 if (GET_CODE (operands
[2]) == CONST_INT
3057 && (INTVAL (operands
[2]) | 0xffff) == -1
3058 && (DATA_REG_P (operands
[0])
3059 || offsettable_memref_p (operands
[0]))
3060 && !TARGET_COLDFIRE
)
3062 if (GET_CODE (operands
[0]) != REG
)
3063 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3064 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3065 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3067 if (operands
[2] == const0_rtx
)
3069 return "and%.w %2,%0";
3071 if (GET_CODE (operands
[2]) == CONST_INT
3072 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3073 && (DATA_REG_P (operands
[0])
3074 || offsettable_memref_p (operands
[0])))
3076 if (DATA_REG_P (operands
[0]))
3078 operands
[1] = GEN_INT (logval
);
3082 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3083 operands
[1] = GEN_INT (logval
% 8);
3085 /* This does not set condition codes in a standard way. */
3087 return "bclr %1,%0";
3089 return "and%.l %2,%0";
3093 output_iorsi3 (rtx
*operands
)
3095 register int logval
;
3096 if (GET_CODE (operands
[2]) == CONST_INT
3097 && INTVAL (operands
[2]) >> 16 == 0
3098 && (DATA_REG_P (operands
[0])
3099 || offsettable_memref_p (operands
[0]))
3100 && !TARGET_COLDFIRE
)
3102 if (GET_CODE (operands
[0]) != REG
)
3103 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3104 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3106 if (INTVAL (operands
[2]) == 0xffff)
3107 return "mov%.w %2,%0";
3108 return "or%.w %2,%0";
3110 if (GET_CODE (operands
[2]) == CONST_INT
3111 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3112 && (DATA_REG_P (operands
[0])
3113 || offsettable_memref_p (operands
[0])))
3115 if (DATA_REG_P (operands
[0]))
3116 operands
[1] = GEN_INT (logval
);
3119 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3120 operands
[1] = GEN_INT (logval
% 8);
3123 return "bset %1,%0";
3125 return "or%.l %2,%0";
3129 output_xorsi3 (rtx
*operands
)
3131 register int logval
;
3132 if (GET_CODE (operands
[2]) == CONST_INT
3133 && INTVAL (operands
[2]) >> 16 == 0
3134 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3135 && !TARGET_COLDFIRE
)
3137 if (! DATA_REG_P (operands
[0]))
3138 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3139 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3141 if (INTVAL (operands
[2]) == 0xffff)
3143 return "eor%.w %2,%0";
3145 if (GET_CODE (operands
[2]) == CONST_INT
3146 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3147 && (DATA_REG_P (operands
[0])
3148 || offsettable_memref_p (operands
[0])))
3150 if (DATA_REG_P (operands
[0]))
3151 operands
[1] = GEN_INT (logval
);
3154 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3155 operands
[1] = GEN_INT (logval
% 8);
3158 return "bchg %1,%0";
3160 return "eor%.l %2,%0";
3163 #ifdef M68K_TARGET_COFF
3165 /* Output assembly to switch to section NAME with attribute FLAGS. */
3168 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3169 tree decl ATTRIBUTE_UNUSED
)
3173 if (flags
& SECTION_WRITE
)
3178 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3181 #endif /* M68K_TARGET_COFF */
3184 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3185 HOST_WIDE_INT delta
,
3186 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3192 if (delta
> 0 && delta
<= 8)
3193 asm_fprintf (file
, MOTOROLA
?
3194 "\taddq.l %I%d,4(%Rsp)\n" :
3195 "\taddql %I%d,%Rsp@(4)\n",
3197 else if (delta
< 0 && delta
>= -8)
3198 asm_fprintf (file
, MOTOROLA
?
3199 "\tsubq.l %I%d,4(%Rsp)\n" :
3200 "\tsubql %I%d,%Rsp@(4)\n",
3202 else if (TARGET_COLDFIRE
)
3204 /* ColdFire can't add/sub a constant to memory unless it is in
3205 the range of addq/subq. So load the value into %d0 and
3206 then add it to 4(%sp). */
3207 if (delta
>= -128 && delta
<= 127)
3208 asm_fprintf (file
, MOTOROLA
?
3209 "\tmoveq.l %I%wd,%Rd0\n" :
3210 "\tmoveql %I%wd,%Rd0\n", delta
);
3212 asm_fprintf (file
, MOTOROLA
?
3213 "\tmove.l %I%wd,%Rd0\n" :
3214 "\tmovel %I%wd,%Rd0\n", delta
);
3215 asm_fprintf (file
, MOTOROLA
?
3216 "\tadd.l %Rd0,4(%Rsp)\n" :
3217 "\taddl %Rd0,%Rsp@(4)\n");
3220 asm_fprintf (file
, MOTOROLA
?
3221 "\tadd.l %I%wd,4(%Rsp)\n" :
3222 "\taddl %I%wd,%Rsp@(4)\n",
3225 xops
[0] = DECL_RTL (function
);
3227 /* Logic taken from call patterns in m68k.md. */
3232 else if ((flag_pic
== 1) || TARGET_68020
)
3235 #if defined(USE_GAS)
3236 fmt
= "bra.l %0@PLTPC";
3238 fmt
= "bra %0@PLTPC";
3240 else /* !MOTOROLA */
3247 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3248 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3250 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3254 #if MOTOROLA && !defined (USE_GAS)
3261 output_asm_insn (fmt
, xops
);
3264 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3267 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3268 int incoming ATTRIBUTE_UNUSED
)
3270 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3273 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3275 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3276 unsigned int new_reg
)
3279 /* Interrupt functions can only use registers that have already been
3280 saved by the prologue, even if they would normally be
3283 if (m68k_interrupt_function_p (current_function_decl
)
3284 && !regs_ever_live
[new_reg
])