1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* These bits are controlled by all CPU selection options. Many options
205 also control MASK_68881, but some (notably -m68020) leave it alone. */
207 #define MASK_ALL_CPU_BITS \
208 (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
209 | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_BITFIELD)
211 /* Implement TARGET_HANDLE_OPTION. */
214 m68k_handle_option (size_t code
, const char *arg
, int value
)
219 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
220 target_flags
|= MASK_5200
;
224 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
225 target_flags
|= MASK_5200
| MASK_CF_HWDIV
;
229 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
230 target_flags
|= MASK_528x
| MASK_CF_HWDIV
;
234 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
235 target_flags
|= MASK_CFV3
| MASK_CF_HWDIV
;
239 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
240 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
;
245 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
250 target_flags
&= ~MASK_ALL_CPU_BITS
;
251 target_flags
|= MASK_68020
| MASK_BITFIELD
;
255 target_flags
&= ~MASK_ALL_CPU_BITS
;
256 target_flags
|= MASK_BITFIELD
| MASK_68881
| MASK_68020
| MASK_68040
;
260 target_flags
&= ~MASK_ALL_CPU_BITS
;
261 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68020
262 | MASK_68040
| MASK_68060
);
266 target_flags
&= ~MASK_ALL_CPU_BITS
;
267 target_flags
|= MASK_68020
| MASK_68030
| MASK_BITFIELD
;
271 target_flags
&= ~MASK_ALL_CPU_BITS
;
272 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
273 | MASK_68040_ONLY
| MASK_68040
);
277 target_flags
&= ~MASK_ALL_CPU_BITS
;
278 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
279 | MASK_68040_ONLY
| MASK_68060
);
283 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
288 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
289 target_flags
|= MASK_68020
;
292 case OPT_mshared_library_id_
:
293 if (value
> MAX_LIBRARY_ID
)
294 error ("-mshared-library-id=%s is not between 0 and %d",
295 arg
, MAX_LIBRARY_ID
);
297 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
305 /* Sometimes certain combinations of command options do not make
306 sense on a particular target machine. You can define a macro
307 `OVERRIDE_OPTIONS' to take account of this. This macro, if
308 defined, is executed once just after all the command options have
311 Don't use this macro to turn on various extra optimizations for
312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
315 override_options (void)
317 /* Sanity check to ensure that msep-data and mid-sahred-library are not
318 * both specified together. Doing so simply doesn't make sense.
320 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
321 error ("cannot specify both -msep-data and -mid-shared-library");
323 /* If we're generating code for a separate A5 relative data segment,
324 * we've got to enable -fPIC as well. This might be relaxable to
325 * -fpic but it hasn't been tested properly.
327 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
330 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
332 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
333 error("-fPIC is not currently supported on the 68000 or 68010\n");
335 /* ??? A historic way of turning on pic, or is this intended to
336 be an embedded thing that doesn't have the same name binding
337 significance that it does on hosted ELF systems? */
338 if (TARGET_PCREL
&& flag_pic
== 0)
341 /* Turn off function cse if we are doing PIC. We always want function call
342 to be done as `bsr foo@PLTPC', so it will force the assembler to create
343 the PLT entry for `foo'. Doing function cse will cause the address of
344 `foo' to be loaded into a register, which is exactly what we want to
345 avoid when we are doing PIC on svr4 m68k. */
347 flag_no_function_cse
= 1;
349 SUBTARGET_OVERRIDE_OPTIONS
;
352 /* Return nonzero if FUNC is an interrupt function as specified by the
353 "interrupt_handler" attribute. */
355 m68k_interrupt_function_p(tree func
)
359 if (TREE_CODE (func
) != FUNCTION_DECL
)
362 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
363 return (a
!= NULL_TREE
);
366 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
367 struct attribute_spec.handler. */
369 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
370 tree args ATTRIBUTE_UNUSED
,
371 int flags ATTRIBUTE_UNUSED
,
374 if (TREE_CODE (*node
) != FUNCTION_DECL
)
376 warning ("%qs attribute only applies to functions",
377 IDENTIFIER_POINTER (name
));
378 *no_add_attrs
= true;
385 m68k_compute_frame_layout (void)
388 unsigned int mask
, rmask
;
389 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
391 /* Only compute the frame once per function.
392 Don't cache information until reload has been completed. */
393 if (current_frame
.funcdef_no
== current_function_funcdef_no
397 current_frame
.size
= (get_frame_size () + 3) & -4;
399 mask
= rmask
= saved
= 0;
400 for (regno
= 0; regno
< 16; regno
++)
401 if (m68k_save_reg (regno
, interrupt_handler
))
404 rmask
|= 1 << (15 - regno
);
407 current_frame
.offset
= saved
* 4;
408 current_frame
.reg_no
= saved
;
409 current_frame
.reg_mask
= mask
;
410 current_frame
.reg_rev_mask
= rmask
;
412 current_frame
.foffset
= 0;
413 mask
= rmask
= saved
= 0;
414 if (TARGET_68881
/* || TARGET_CFV4E */)
416 for (regno
= 16; regno
< 24; regno
++)
417 if (m68k_save_reg (regno
, interrupt_handler
))
419 mask
|= 1 << (regno
- 16);
420 rmask
|= 1 << (23 - regno
);
423 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
424 current_frame
.offset
+= current_frame
.foffset
;
426 current_frame
.fpu_no
= saved
;
427 current_frame
.fpu_mask
= mask
;
428 current_frame
.fpu_rev_mask
= rmask
;
430 /* Remember what function this frame refers to. */
431 current_frame
.funcdef_no
= current_function_funcdef_no
;
435 m68k_initial_elimination_offset (int from
, int to
)
437 /* FIXME: The correct offset to compute here would appear to be
438 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
439 but for some obscure reason, this must be 0 to get correct code. */
440 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
443 m68k_compute_frame_layout ();
445 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
446 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
447 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
448 return current_frame
.offset
+ current_frame
.size
;
453 /* Refer to the array `regs_ever_live' to determine which registers
454 to save; `regs_ever_live[I]' is nonzero if register number I
455 is ever used in the function. This function is responsible for
456 knowing which registers should not be saved even if used.
457 Return true if we need to save REGNO. */
460 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
462 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
464 if (current_function_uses_pic_offset_table
)
466 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
470 if (current_function_calls_eh_return
)
475 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
476 if (test
== INVALID_REGNUM
)
483 /* Fixed regs we never touch. */
484 if (fixed_regs
[regno
])
487 /* The frame pointer (if it is such) is handled specially. */
488 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
491 /* Interrupt handlers must also save call_used_regs
492 if they are live or when calling nested functions. */
493 if (interrupt_handler
)
495 if (regs_ever_live
[regno
])
498 if (!current_function_is_leaf
&& call_used_regs
[regno
])
502 /* Never need to save registers that aren't touched. */
503 if (!regs_ever_live
[regno
])
506 /* Otherwise save everything that isn't call-clobbered. */
507 return !call_used_regs
[regno
];
510 /* This function generates the assembly code for function entry.
511 STREAM is a stdio stream to output the code to.
512 SIZE is an int: how many units of temporary storage to allocate. */
515 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
517 HOST_WIDE_INT fsize_with_regs
;
518 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
520 m68k_compute_frame_layout();
522 /* If the stack limit is a symbol, we can check it here,
523 before actually allocating the space. */
524 if (current_function_limit_stack
525 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
526 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
527 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
529 /* On ColdFire add register save into initial stack frame setup, if possible. */
530 fsize_with_regs
= current_frame
.size
;
531 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
532 fsize_with_regs
+= current_frame
.reg_no
* 4;
534 if (frame_pointer_needed
)
536 if (current_frame
.size
== 0 && TARGET_68040
)
537 /* on the 68040, pea + move is faster than link.w 0 */
538 fprintf (stream
, MOTOROLA
?
539 "\tpea (%s)\n\tmove.l %s,%s\n" :
540 "\tpea %s@\n\tmovel %s,%s\n",
541 M68K_REGNAME(FRAME_POINTER_REGNUM
),
542 M68K_REGNAME(STACK_POINTER_REGNUM
),
543 M68K_REGNAME(FRAME_POINTER_REGNUM
));
544 else if (fsize_with_regs
< 0x8000)
545 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
546 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
547 else if (TARGET_68020
)
548 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
549 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
551 /* Adding negative number is faster on the 68040. */
552 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
553 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
554 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
556 if (dwarf2out_do_frame ())
559 l
= (char *) dwarf2out_cfi_label ();
561 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
562 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
563 cfa_offset
+= current_frame
.size
;
566 else if (fsize_with_regs
) /* !frame_pointer_needed */
568 if (fsize_with_regs
< 0x8000)
570 if (fsize_with_regs
<= 8)
572 if (!TARGET_COLDFIRE
)
573 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
576 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
579 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
580 /* On the CPU32 it is faster to use two subqw instructions to
581 subtract a small integer (8 < N <= 16) to a register. */
583 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
584 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
585 fsize_with_regs
- 8);
586 else if (TARGET_68040
)
587 /* Adding negative number is faster on the 68040. */
588 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
591 asm_fprintf (stream
, MOTOROLA
?
592 "\tlea (%wd,%Rsp),%Rsp\n" :
593 "\tlea %Rsp@(%wd),%Rsp\n",
596 else /* fsize_with_regs >= 0x8000 */
597 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
599 if (dwarf2out_do_frame ())
601 cfa_offset
+= current_frame
.size
+ 4;
602 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
604 } /* !frame_pointer_needed */
606 if (current_frame
.fpu_mask
)
608 asm_fprintf (stream
, MOTOROLA
?
609 "\tfmovm %I0x%x,-(%Rsp)\n" :
610 "\tfmovem %I0x%x,%Rsp@-\n",
611 current_frame
.fpu_mask
);
613 if (dwarf2out_do_frame ())
615 char *l
= (char *) dwarf2out_cfi_label ();
618 cfa_offset
+= current_frame
.fpu_no
* 12;
619 if (! frame_pointer_needed
)
620 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
621 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
622 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
623 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
627 /* If the stack limit is not a symbol, check it here.
628 This has the disadvantage that it may be too late... */
629 if (current_function_limit_stack
)
631 if (REG_P (stack_limit_rtx
))
632 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
633 M68K_REGNAME(REGNO (stack_limit_rtx
)));
634 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
635 warning ("stack limit expression is not supported");
638 if (current_frame
.reg_no
<= 2)
640 /* Store each separately in the same order moveml uses.
641 Using two movel instructions instead of a single moveml
642 is about 15% faster for the 68020 and 68030 at no expense
647 for (i
= 0; i
< 16; i
++)
648 if (current_frame
.reg_rev_mask
& (1 << i
))
650 asm_fprintf (stream
, MOTOROLA
?
651 "\t%Omove.l %s,-(%Rsp)\n" :
652 "\tmovel %s,%Rsp@-\n",
653 M68K_REGNAME(15 - i
));
654 if (dwarf2out_do_frame ())
656 char *l
= (char *) dwarf2out_cfi_label ();
659 if (! frame_pointer_needed
)
660 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
661 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
665 else if (current_frame
.reg_rev_mask
)
668 /* The ColdFire does not support the predecrement form of the
669 MOVEM instruction, so we must adjust the stack pointer and
670 then use the plain address register indirect mode.
671 The required register save space was combined earlier with
672 the fsize_with_regs amount. */
674 asm_fprintf (stream
, MOTOROLA
?
675 "\tmovm.l %I0x%x,(%Rsp)\n" :
676 "\tmoveml %I0x%x,%Rsp@\n",
677 current_frame
.reg_mask
);
679 asm_fprintf (stream
, MOTOROLA
?
680 "\tmovm.l %I0x%x,-(%Rsp)\n" :
681 "\tmoveml %I0x%x,%Rsp@-\n",
682 current_frame
.reg_rev_mask
);
683 if (dwarf2out_do_frame ())
685 char *l
= (char *) dwarf2out_cfi_label ();
688 cfa_offset
+= current_frame
.reg_no
* 4;
689 if (! frame_pointer_needed
)
690 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
691 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
692 if (current_frame
.reg_mask
& (1 << regno
))
693 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
696 if (!TARGET_SEP_DATA
&& flag_pic
&&
697 (current_function_uses_pic_offset_table
||
698 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
700 if (TARGET_ID_SHARED_LIBRARY
)
702 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
703 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
704 m68k_library_id_string
,
705 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
710 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
711 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
714 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
715 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
716 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
717 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
718 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
724 /* Return true if this function's epilogue can be output as RTL. */
727 use_return_insn (void)
729 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
732 /* We can output the epilogue as RTL only if no registers need to be
734 m68k_compute_frame_layout();
735 return current_frame
.reg_no
? false : true;
738 /* This function generates the assembly code for function exit,
739 on machines that need it.
741 The function epilogue should not depend on the current stack pointer!
742 It should use the frame pointer only, if there is a frame pointer.
743 This is mandatory because of alloca; we also take advantage of it to
744 omit stack adjustments before returning. */
747 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
749 HOST_WIDE_INT fsize
, fsize_with_regs
;
751 bool restore_from_sp
= false;
752 rtx insn
= get_last_insn ();
754 m68k_compute_frame_layout();
756 /* If the last insn was a BARRIER, we don't have to write any code. */
757 if (GET_CODE (insn
) == NOTE
)
758 insn
= prev_nonnote_insn (insn
);
759 if (insn
&& GET_CODE (insn
) == BARRIER
)
761 /* Output just a no-op so that debuggers don't get confused
762 about which function the pc is in at this address. */
763 fprintf (stream
, "\tnop\n");
767 #ifdef FUNCTION_EXTRA_EPILOGUE
768 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
771 fsize
= current_frame
.size
;
773 /* FIXME : leaf_function_p below is too strong.
774 What we really need to know there is if there could be pending
775 stack adjustment needed at that point. */
776 restore_from_sp
= ! frame_pointer_needed
777 || (! current_function_calls_alloca
&& leaf_function_p ());
779 /* fsize_with_regs is the size we need to adjust the sp when
780 popping the frame. */
781 fsize_with_regs
= fsize
;
783 /* Because the ColdFire doesn't support moveml with
784 complex address modes, we must adjust the stack manually
785 after restoring registers. When the frame pointer isn't used,
786 we can merge movem adjustment into frame unlinking
787 made immediately after it. */
788 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
789 fsize_with_regs
+= current_frame
.reg_no
* 4;
791 if (current_frame
.offset
+ fsize
>= 0x8000
793 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
795 /* Because the ColdFire doesn't support moveml with
796 complex address modes we make an extra correction here. */
798 fsize
+= current_frame
.offset
;
800 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
801 fsize
= 0, big
= true;
803 if (current_frame
.reg_no
<= 2)
805 /* Restore each separately in the same order moveml does.
806 Using two movel instructions instead of a single moveml
807 is about 15% faster for the 68020 and 68030 at no expense
811 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
813 for (i
= 0; i
< 16; i
++)
814 if (current_frame
.reg_mask
& (1 << i
))
819 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
821 M68K_REGNAME(FRAME_POINTER_REGNUM
),
824 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
825 M68K_REGNAME(FRAME_POINTER_REGNUM
),
829 else if (restore_from_sp
)
830 asm_fprintf (stream
, MOTOROLA
?
831 "\t%Omove.l (%Rsp)+,%s\n" :
832 "\tmovel %Rsp@+,%s\n",
837 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
842 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
843 M68K_REGNAME(FRAME_POINTER_REGNUM
),
850 else if (current_frame
.reg_mask
)
852 /* The ColdFire requires special handling due to its limited moveml insn. */
857 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
858 M68K_REGNAME(FRAME_POINTER_REGNUM
));
859 asm_fprintf (stream
, MOTOROLA
?
860 "\tmovm.l (%Ra1),%I0x%x\n" :
861 "\tmoveml %Ra1@,%I0x%x\n",
862 current_frame
.reg_mask
);
864 else if (restore_from_sp
)
865 asm_fprintf (stream
, MOTOROLA
?
866 "\tmovm.l (%Rsp),%I0x%x\n" :
867 "\tmoveml %Rsp@,%I0x%x\n",
868 current_frame
.reg_mask
);
872 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
873 current_frame
.offset
+ fsize
,
874 M68K_REGNAME(FRAME_POINTER_REGNUM
),
875 current_frame
.reg_mask
);
877 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
878 M68K_REGNAME(FRAME_POINTER_REGNUM
),
879 current_frame
.offset
+ fsize
,
880 current_frame
.reg_mask
);
883 else /* !TARGET_COLDFIRE */
888 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
889 current_frame
.offset
+ fsize
,
890 M68K_REGNAME(FRAME_POINTER_REGNUM
),
891 current_frame
.reg_mask
);
893 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
894 M68K_REGNAME(FRAME_POINTER_REGNUM
),
895 current_frame
.offset
+ fsize
,
896 current_frame
.reg_mask
);
898 else if (restore_from_sp
)
900 asm_fprintf (stream
, MOTOROLA
?
901 "\tmovm.l (%Rsp)+,%I0x%x\n" :
902 "\tmoveml %Rsp@+,%I0x%x\n",
903 current_frame
.reg_mask
);
908 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
909 current_frame
.offset
+ fsize
,
910 M68K_REGNAME(FRAME_POINTER_REGNUM
),
911 current_frame
.reg_mask
);
913 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
914 M68K_REGNAME(FRAME_POINTER_REGNUM
),
915 current_frame
.offset
+ fsize
,
916 current_frame
.reg_mask
);
920 if (current_frame
.fpu_rev_mask
)
925 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
926 current_frame
.foffset
+ fsize
,
927 M68K_REGNAME(FRAME_POINTER_REGNUM
),
928 current_frame
.fpu_rev_mask
);
930 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
931 M68K_REGNAME(FRAME_POINTER_REGNUM
),
932 current_frame
.foffset
+ fsize
,
933 current_frame
.fpu_rev_mask
);
935 else if (restore_from_sp
)
938 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
939 current_frame
.fpu_rev_mask
);
941 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
942 current_frame
.fpu_rev_mask
);
947 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
948 current_frame
.foffset
+ fsize
,
949 M68K_REGNAME(FRAME_POINTER_REGNUM
),
950 current_frame
.fpu_rev_mask
);
952 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
953 M68K_REGNAME(FRAME_POINTER_REGNUM
),
954 current_frame
.foffset
+ fsize
,
955 current_frame
.fpu_rev_mask
);
958 if (frame_pointer_needed
)
959 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
960 else if (fsize_with_regs
)
962 if (fsize_with_regs
<= 8)
964 if (!TARGET_COLDFIRE
)
965 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
968 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
971 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
973 /* On the CPU32 it is faster to use two addqw instructions to
974 add a small integer (8 < N <= 16) to a register. */
975 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
976 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
977 fsize_with_regs
- 8);
979 else if (fsize_with_regs
< 0x8000)
982 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
985 asm_fprintf (stream
, MOTOROLA
?
986 "\tlea (%wd,%Rsp),%Rsp\n" :
987 "\tlea %Rsp@(%wd),%Rsp\n",
991 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
993 if (current_function_calls_eh_return
)
994 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
995 if (m68k_interrupt_function_p (current_function_decl
))
996 fprintf (stream
, "\trte\n");
997 else if (current_function_pops_args
)
998 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1000 fprintf (stream
, "\trts\n");
1003 /* Return true if X is a valid comparison operator for the dbcc
1006 Note it rejects floating point comparison operators.
1007 (In the future we could use Fdbcc).
1009 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1012 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1014 switch (GET_CODE (x
))
1016 case EQ
: case NE
: case GTU
: case LTU
:
1020 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1022 case GT
: case LT
: case GE
: case LE
:
1023 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1029 /* Return nonzero if flags are currently in the 68881 flag register. */
1031 flags_in_68881 (void)
1033 /* We could add support for these in the future */
1034 return cc_status
.flags
& CC_IN_68881
;
1037 /* Output a BSR instruction suitable for PIC code. */
1039 m68k_output_pic_call(rtx dest
)
1043 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1045 /* We output a BSR instruction if we're using -fpic or we're building for
1046 * a target that supports long branches. If we're building -fPIC on the
1047 * 68000, 68010 or ColdFire we generate one of two sequences:
1048 * a shorter one that uses a GOT entry or a longer one that doesn't.
1049 * We'll use the -Os command-line flag to decide which to generate.
1050 * Both sequences take the same time to execute on the ColdFire.
1052 else if (TARGET_PCREL
)
1054 else if ((flag_pic
== 1) || TARGET_68020
)
1055 #if defined(USE_GAS)
1056 out
= "bsr.l %0@PLTPC";
1058 out
= "bsr %0@PLTPC";
1060 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1061 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1063 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1065 output_asm_insn(out
, &dest
);
1068 /* Output a dbCC; jCC sequence. Note we do not handle the
1069 floating point version of this sequence (Fdbcc). We also
1070 do not handle alternative conditions when CC_NO_OVERFLOW is
1071 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1072 kick those out before we get here. */
1075 output_dbcc_and_branch (rtx
*operands
)
1077 switch (GET_CODE (operands
[3]))
1080 output_asm_insn (MOTOROLA
?
1081 "dbeq %0,%l1\n\tjbeq %l2" :
1082 "dbeq %0,%l1\n\tjeq %l2",
1087 output_asm_insn (MOTOROLA
?
1088 "dbne %0,%l1\n\tjbne %l2" :
1089 "dbne %0,%l1\n\tjne %l2",
1094 output_asm_insn (MOTOROLA
?
1095 "dbgt %0,%l1\n\tjbgt %l2" :
1096 "dbgt %0,%l1\n\tjgt %l2",
1101 output_asm_insn (MOTOROLA
?
1102 "dbhi %0,%l1\n\tjbhi %l2" :
1103 "dbhi %0,%l1\n\tjhi %l2",
1108 output_asm_insn (MOTOROLA
?
1109 "dblt %0,%l1\n\tjblt %l2" :
1110 "dblt %0,%l1\n\tjlt %l2",
1115 output_asm_insn (MOTOROLA
?
1116 "dbcs %0,%l1\n\tjbcs %l2" :
1117 "dbcs %0,%l1\n\tjcs %l2",
1122 output_asm_insn (MOTOROLA
?
1123 "dbge %0,%l1\n\tjbge %l2" :
1124 "dbge %0,%l1\n\tjge %l2",
1129 output_asm_insn (MOTOROLA
?
1130 "dbcc %0,%l1\n\tjbcc %l2" :
1131 "dbcc %0,%l1\n\tjcc %l2",
1136 output_asm_insn (MOTOROLA
?
1137 "dble %0,%l1\n\tjble %l2" :
1138 "dble %0,%l1\n\tjle %l2",
1143 output_asm_insn (MOTOROLA
?
1144 "dbls %0,%l1\n\tjbls %l2" :
1145 "dbls %0,%l1\n\tjls %l2",
1153 /* If the decrement is to be done in SImode, then we have
1154 to compensate for the fact that dbcc decrements in HImode. */
1155 switch (GET_MODE (operands
[0]))
1158 output_asm_insn (MOTOROLA
?
1159 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1160 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1173 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1176 enum rtx_code op_code
= GET_CODE (op
);
1178 /* This does not produce a useful cc. */
1181 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1182 below. Swap the operands and change the op if these requirements
1183 are not fulfilled. */
1184 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1188 operand1
= operand2
;
1190 op_code
= swap_condition (op_code
);
1192 loperands
[0] = operand1
;
1193 if (GET_CODE (operand1
) == REG
)
1194 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1196 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1197 if (operand2
!= const0_rtx
)
1199 loperands
[2] = operand2
;
1200 if (GET_CODE (operand2
) == REG
)
1201 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1203 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1205 loperands
[4] = gen_label_rtx ();
1206 if (operand2
!= const0_rtx
)
1208 output_asm_insn (MOTOROLA
?
1209 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1210 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1215 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1216 output_asm_insn ("tst%.l %0", loperands
);
1219 output_asm_insn ("cmp%.w #0,%0", loperands
);
1222 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1224 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1225 output_asm_insn ("tst%.l %1", loperands
);
1227 output_asm_insn ("cmp%.w #0,%1", loperands
);
1230 loperands
[5] = dest
;
1235 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1236 CODE_LABEL_NUMBER (loperands
[4]));
1237 output_asm_insn ("seq %5", loperands
);
1241 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1242 CODE_LABEL_NUMBER (loperands
[4]));
1243 output_asm_insn ("sne %5", loperands
);
1247 loperands
[6] = gen_label_rtx ();
1248 output_asm_insn (MOTOROLA
?
1249 "shi %5\n\tjbra %l6" :
1250 "shi %5\n\tjra %l6",
1252 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1253 CODE_LABEL_NUMBER (loperands
[4]));
1254 output_asm_insn ("sgt %5", loperands
);
1255 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1256 CODE_LABEL_NUMBER (loperands
[6]));
1260 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1261 CODE_LABEL_NUMBER (loperands
[4]));
1262 output_asm_insn ("shi %5", loperands
);
1266 loperands
[6] = gen_label_rtx ();
1267 output_asm_insn (MOTOROLA
?
1268 "scs %5\n\tjbra %l6" :
1269 "scs %5\n\tjra %l6",
1271 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1272 CODE_LABEL_NUMBER (loperands
[4]));
1273 output_asm_insn ("slt %5", loperands
);
1274 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1275 CODE_LABEL_NUMBER (loperands
[6]));
1279 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1280 CODE_LABEL_NUMBER (loperands
[4]));
1281 output_asm_insn ("scs %5", loperands
);
1285 loperands
[6] = gen_label_rtx ();
1286 output_asm_insn (MOTOROLA
?
1287 "scc %5\n\tjbra %l6" :
1288 "scc %5\n\tjra %l6",
1290 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1291 CODE_LABEL_NUMBER (loperands
[4]));
1292 output_asm_insn ("sge %5", loperands
);
1293 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1294 CODE_LABEL_NUMBER (loperands
[6]));
1298 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1299 CODE_LABEL_NUMBER (loperands
[4]));
1300 output_asm_insn ("scc %5", loperands
);
1304 loperands
[6] = gen_label_rtx ();
1305 output_asm_insn (MOTOROLA
?
1306 "sls %5\n\tjbra %l6" :
1307 "sls %5\n\tjra %l6",
1309 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1310 CODE_LABEL_NUMBER (loperands
[4]));
1311 output_asm_insn ("sle %5", loperands
);
1312 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1313 CODE_LABEL_NUMBER (loperands
[6]));
1317 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1318 CODE_LABEL_NUMBER (loperands
[4]));
1319 output_asm_insn ("sls %5", loperands
);
1329 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1331 operands
[0] = countop
;
1332 operands
[1] = dataop
;
1334 if (GET_CODE (countop
) == CONST_INT
)
1336 register int count
= INTVAL (countop
);
1337 /* If COUNT is bigger than size of storage unit in use,
1338 advance to the containing unit of same size. */
1339 if (count
> signpos
)
1341 int offset
= (count
& ~signpos
) / 8;
1342 count
= count
& signpos
;
1343 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1345 if (count
== signpos
)
1346 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1348 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1350 /* These three statements used to use next_insns_test_no...
1351 but it appears that this should do the same job. */
1353 && next_insn_tests_no_inequality (insn
))
1356 && next_insn_tests_no_inequality (insn
))
1359 && next_insn_tests_no_inequality (insn
))
1362 cc_status
.flags
= CC_NOT_NEGATIVE
;
1364 return "btst %0,%1";
1367 /* Legitimize PIC addresses. If the address is already
1368 position-independent, we return ORIG. Newly generated
1369 position-independent addresses go to REG. If we need more
1370 than one register, we lose.
1372 An address is legitimized by making an indirect reference
1373 through the Global Offset Table with the name of the symbol
1376 The assembler and linker are responsible for placing the
1377 address of the symbol in the GOT. The function prologue
1378 is responsible for initializing a5 to the starting address
1381 The assembler is also responsible for translating a symbol name
1382 into a constant displacement from the start of the GOT.
1384 A quick example may make things a little clearer:
1386 When not generating PIC code to store the value 12345 into _foo
1387 we would generate the following code:
1391 When generating PIC two transformations are made. First, the compiler
1392 loads the address of foo into a register. So the first transformation makes:
1397 The code in movsi will intercept the lea instruction and call this
1398 routine which will transform the instructions into:
1400 movel a5@(_foo:w), a0
1404 That (in a nutshell) is how *all* symbol and label references are
1408 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1413 /* First handle a simple SYMBOL_REF or LABEL_REF */
1414 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1419 pic_ref
= gen_rtx_MEM (Pmode
,
1420 gen_rtx_PLUS (Pmode
,
1421 pic_offset_table_rtx
, orig
));
1422 current_function_uses_pic_offset_table
= 1;
1423 MEM_READONLY_P (pic_ref
) = 1;
1424 emit_move_insn (reg
, pic_ref
);
1427 else if (GET_CODE (orig
) == CONST
)
1431 /* Make sure this has not already been legitimized. */
1432 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1433 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1439 /* legitimize both operands of the PLUS */
1440 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1442 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1443 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1444 base
== reg
? 0 : reg
);
1448 if (GET_CODE (orig
) == CONST_INT
)
1449 return plus_constant (base
, INTVAL (orig
));
1450 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1451 /* Likewise, should we set special REG_NOTEs here? */
1457 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1459 static CONST_METHOD
const_method (rtx
);
1461 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1464 const_method (rtx constant
)
1469 i
= INTVAL (constant
);
1473 /* The ColdFire doesn't have byte or word operations. */
1474 /* FIXME: This may not be useful for the m68060 either. */
1475 if (!TARGET_COLDFIRE
)
1477 /* if -256 < N < 256 but N is not in range for a moveq
1478 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1479 if (USE_MOVQ (i
^ 0xff))
1481 /* Likewise, try with not.w */
1482 if (USE_MOVQ (i
^ 0xffff))
1484 /* This is the only value where neg.w is useful */
1489 /* Try also with swap. */
1491 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1496 /* Try using MVZ/MVS with an immediate value to load constants. */
1497 if (i
>= 0 && i
<= 65535)
1499 if (i
>= -32768 && i
<= 32767)
1503 /* Otherwise, use move.l */
1508 const_int_cost (rtx constant
)
1510 switch (const_method (constant
))
1513 /* Constants between -128 and 127 are cheap due to moveq */
1521 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1531 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1536 /* Constant zero is super cheap due to clr instruction. */
1537 if (x
== const0_rtx
)
1540 *total
= const_int_cost (x
);
1550 /* Make 0.0 cheaper than other floating constants to
1551 encourage creating tstsf and tstdf insns. */
1552 if (outer_code
== COMPARE
1553 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1559 /* These are vaguely right for a 68020. */
1560 /* The costs for long multiply have been adjusted to work properly
1561 in synth_mult on the 68020, relative to an average of the time
1562 for add and the time for shift, taking away a little more because
1563 sometimes move insns are needed. */
1564 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1565 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 : TARGET_COLDFIRE ? 10 : 13)
1566 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1567 (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
1568 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1571 /* An lea costs about three times as much as a simple add. */
1572 if (GET_MODE (x
) == SImode
1573 && GET_CODE (XEXP (x
, 1)) == REG
1574 && GET_CODE (XEXP (x
, 0)) == MULT
1575 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1576 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1577 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1578 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1579 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1581 /* lea an@(dx:l:i),am */
1582 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1592 *total
= COSTS_N_INSNS(1);
1595 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1597 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1599 if (INTVAL (XEXP (x
, 1)) < 16)
1600 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1602 /* We're using clrw + swap for these cases. */
1603 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1606 *total
= COSTS_N_INSNS (10); /* worst case */
1609 /* A shift by a big integer takes an extra instruction. */
1610 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1611 && (INTVAL (XEXP (x
, 1)) == 16))
1613 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1616 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1617 && !(INTVAL (XEXP (x
, 1)) > 0
1618 && INTVAL (XEXP (x
, 1)) <= 8))
1620 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1626 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1627 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1628 && GET_MODE (x
) == SImode
)
1629 *total
= COSTS_N_INSNS (MULW_COST
);
1630 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1631 *total
= COSTS_N_INSNS (MULW_COST
);
1633 *total
= COSTS_N_INSNS (MULL_COST
);
1640 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1641 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1642 else if (TARGET_CF_HWDIV
)
1643 *total
= COSTS_N_INSNS (18);
1645 *total
= COSTS_N_INSNS (43); /* div.l */
1654 output_move_const_into_data_reg (rtx
*operands
)
1658 i
= INTVAL (operands
[1]);
1659 switch (const_method (operands
[1]))
1662 return "mvsw %1,%0";
1664 return "mvzw %1,%0";
1666 return "moveq %1,%0";
1669 operands
[1] = GEN_INT (i
^ 0xff);
1670 return "moveq %1,%0\n\tnot%.b %0";
1673 operands
[1] = GEN_INT (i
^ 0xffff);
1674 return "moveq %1,%0\n\tnot%.w %0";
1677 return "moveq #-128,%0\n\tneg%.w %0";
1682 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1683 return "moveq %1,%0\n\tswap %0";
1686 return "move%.l %1,%0";
1692 /* Return 1 if 'constant' can be represented by
1693 mov3q on a ColdFire V4 core. */
1695 valid_mov3q_const (rtx constant
)
1699 if (TARGET_CFV4
&& GET_CODE (constant
) == CONST_INT
)
1701 i
= INTVAL (constant
);
1702 if ((i
== -1) || (i
>= 1 && i
<= 7))
1710 output_move_simode_const (rtx
*operands
)
1712 if (operands
[1] == const0_rtx
1713 && (DATA_REG_P (operands
[0])
1714 || GET_CODE (operands
[0]) == MEM
)
1715 /* clr insns on 68000 read before writing.
1716 This isn't so on the 68010, but we have no TARGET_68010. */
1717 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1718 || !(GET_CODE (operands
[0]) == MEM
1719 && MEM_VOLATILE_P (operands
[0]))))
1721 else if ((GET_MODE (operands
[0]) == SImode
)
1722 && valid_mov3q_const (operands
[1]))
1723 return "mov3q%.l %1,%0";
1724 else if (operands
[1] == const0_rtx
1725 && ADDRESS_REG_P (operands
[0]))
1726 return "sub%.l %0,%0";
1727 else if (DATA_REG_P (operands
[0]))
1728 return output_move_const_into_data_reg (operands
);
1729 else if (ADDRESS_REG_P (operands
[0])
1730 && INTVAL (operands
[1]) < 0x8000
1731 && INTVAL (operands
[1]) >= -0x8000)
1733 if (valid_mov3q_const (operands
[1]))
1734 return "mov3q%.l %1,%0";
1735 return "move%.w %1,%0";
1737 else if (GET_CODE (operands
[0]) == MEM
1738 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1739 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1740 && INTVAL (operands
[1]) < 0x8000
1741 && INTVAL (operands
[1]) >= -0x8000)
1743 if (valid_mov3q_const (operands
[1]))
1744 return "mov3q%.l %1,%-";
1747 return "move%.l %1,%0";
1751 output_move_simode (rtx
*operands
)
1753 if (GET_CODE (operands
[1]) == CONST_INT
)
1754 return output_move_simode_const (operands
);
1755 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1756 || GET_CODE (operands
[1]) == CONST
)
1757 && push_operand (operands
[0], SImode
))
1759 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1760 || GET_CODE (operands
[1]) == CONST
)
1761 && ADDRESS_REG_P (operands
[0]))
1762 return "lea %a1,%0";
1763 return "move%.l %1,%0";
1767 output_move_himode (rtx
*operands
)
1769 if (GET_CODE (operands
[1]) == CONST_INT
)
1771 if (operands
[1] == const0_rtx
1772 && (DATA_REG_P (operands
[0])
1773 || GET_CODE (operands
[0]) == MEM
)
1774 /* clr insns on 68000 read before writing.
1775 This isn't so on the 68010, but we have no TARGET_68010. */
1776 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1777 || !(GET_CODE (operands
[0]) == MEM
1778 && MEM_VOLATILE_P (operands
[0]))))
1780 else if (operands
[1] == const0_rtx
1781 && ADDRESS_REG_P (operands
[0]))
1782 return "sub%.l %0,%0";
1783 else if (DATA_REG_P (operands
[0])
1784 && INTVAL (operands
[1]) < 128
1785 && INTVAL (operands
[1]) >= -128)
1787 return "moveq %1,%0";
1789 else if (INTVAL (operands
[1]) < 0x8000
1790 && INTVAL (operands
[1]) >= -0x8000)
1791 return "move%.w %1,%0";
1793 else if (CONSTANT_P (operands
[1]))
1794 return "move%.l %1,%0";
1795 /* Recognize the insn before a tablejump, one that refers
1796 to a table of offsets. Such an insn will need to refer
1797 to a label on the insn. So output one. Use the label-number
1798 of the table of offsets to generate this label. This code,
1799 and similar code below, assumes that there will be at most one
1800 reference to each table. */
1801 if (GET_CODE (operands
[1]) == MEM
1802 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1803 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1804 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1806 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1808 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1809 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1811 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1812 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1814 return "move%.w %1,%0";
1818 output_move_qimode (rtx
*operands
)
1820 /* 68k family always modifies the stack pointer by at least 2, even for
1821 byte pushes. The 5200 (ColdFire) does not do this. */
1822 if (GET_CODE (operands
[0]) == MEM
1823 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1824 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1825 && ! ADDRESS_REG_P (operands
[1])
1826 && ! TARGET_COLDFIRE
)
1827 /* generated by pushqi1 pattern now */
1830 /* clr and st insns on 68000 read before writing.
1831 This isn't so on the 68010, but we have no TARGET_68010. */
1832 if (!ADDRESS_REG_P (operands
[0])
1833 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1834 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1836 if (operands
[1] == const0_rtx
)
1838 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1839 && GET_CODE (operands
[1]) == CONST_INT
1840 && (INTVAL (operands
[1]) & 255) == 255)
1846 if (GET_CODE (operands
[1]) == CONST_INT
1847 && DATA_REG_P (operands
[0])
1848 && INTVAL (operands
[1]) < 128
1849 && INTVAL (operands
[1]) >= -128)
1851 return "moveq %1,%0";
1853 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1854 return "sub%.l %0,%0";
1855 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1856 return "move%.l %1,%0";
1857 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1858 from address registers. */
1859 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1860 return "move%.w %1,%0";
1861 return "move%.b %1,%0";
1865 output_move_stricthi (rtx
*operands
)
1867 if (operands
[1] == const0_rtx
1868 /* clr insns on 68000 read before writing.
1869 This isn't so on the 68010, but we have no TARGET_68010. */
1870 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1871 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1873 return "move%.w %1,%0";
1877 output_move_strictqi (rtx
*operands
)
1879 if (operands
[1] == const0_rtx
1880 /* clr insns on 68000 read before writing.
1881 This isn't so on the 68010, but we have no TARGET_68010. */
1882 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1883 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1885 return "move%.b %1,%0";
1888 /* Return the best assembler insn template
1889 for moving operands[1] into operands[0] as a fullword. */
1892 singlemove_string (rtx
*operands
)
1894 if (GET_CODE (operands
[1]) == CONST_INT
)
1895 return output_move_simode_const (operands
);
1896 return "move%.l %1,%0";
1900 /* Output assembler code to perform a doubleword move insn
1901 with operands OPERANDS. */
1904 output_move_double (rtx
*operands
)
1908 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1913 rtx addreg0
= 0, addreg1
= 0;
1914 int dest_overlapped_low
= 0;
1915 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1920 /* First classify both operands. */
1922 if (REG_P (operands
[0]))
1924 else if (offsettable_memref_p (operands
[0]))
1926 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1928 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1930 else if (GET_CODE (operands
[0]) == MEM
)
1935 if (REG_P (operands
[1]))
1937 else if (CONSTANT_P (operands
[1]))
1939 else if (offsettable_memref_p (operands
[1]))
1941 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1943 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1945 else if (GET_CODE (operands
[1]) == MEM
)
1950 /* Check for the cases that the operand constraints are not
1951 supposed to allow to happen. Abort if we get one,
1952 because generating code for these cases is painful. */
1954 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1957 /* If one operand is decrementing and one is incrementing
1958 decrement the former register explicitly
1959 and change that operand into ordinary indexing. */
1961 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1963 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1965 output_asm_insn ("sub%.l #12,%0", operands
);
1967 output_asm_insn ("subq%.l #8,%0", operands
);
1968 if (GET_MODE (operands
[1]) == XFmode
)
1969 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1970 else if (GET_MODE (operands
[0]) == DFmode
)
1971 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1973 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1976 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1978 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1980 output_asm_insn ("sub%.l #12,%1", operands
);
1982 output_asm_insn ("subq%.l #8,%1", operands
);
1983 if (GET_MODE (operands
[1]) == XFmode
)
1984 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1985 else if (GET_MODE (operands
[1]) == DFmode
)
1986 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1988 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1992 /* If an operand is an unoffsettable memory ref, find a register
1993 we can increment temporarily to make it refer to the second word. */
1995 if (optype0
== MEMOP
)
1996 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1998 if (optype1
== MEMOP
)
1999 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2001 /* Ok, we can do one word at a time.
2002 Normally we do the low-numbered word first,
2003 but if either operand is autodecrementing then we
2004 do the high-numbered word first.
2006 In either case, set up in LATEHALF the operands to use
2007 for the high-numbered word and in some cases alter the
2008 operands in OPERANDS to be suitable for the low-numbered word. */
2012 if (optype0
== REGOP
)
2014 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2015 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2017 else if (optype0
== OFFSOP
)
2019 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2020 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2024 middlehalf
[0] = operands
[0];
2025 latehalf
[0] = operands
[0];
2028 if (optype1
== REGOP
)
2030 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2031 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2033 else if (optype1
== OFFSOP
)
2035 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2036 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2038 else if (optype1
== CNSTOP
)
2040 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2045 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2046 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2047 operands
[1] = GEN_INT (l
[0]);
2048 middlehalf
[1] = GEN_INT (l
[1]);
2049 latehalf
[1] = GEN_INT (l
[2]);
2051 else if (CONSTANT_P (operands
[1]))
2053 /* actually, no non-CONST_DOUBLE constant should ever
2056 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2057 latehalf
[1] = constm1_rtx
;
2059 latehalf
[1] = const0_rtx
;
2064 middlehalf
[1] = operands
[1];
2065 latehalf
[1] = operands
[1];
2069 /* size is not 12: */
2071 if (optype0
== REGOP
)
2072 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2073 else if (optype0
== OFFSOP
)
2074 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2076 latehalf
[0] = operands
[0];
2078 if (optype1
== REGOP
)
2079 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2080 else if (optype1
== OFFSOP
)
2081 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2082 else if (optype1
== CNSTOP
)
2083 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2085 latehalf
[1] = operands
[1];
2088 /* If insn is effectively movd N(sp),-(sp) then we will do the
2089 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2090 for the low word as well, to compensate for the first decrement of sp. */
2091 if (optype0
== PUSHOP
2092 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2093 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2094 operands
[1] = middlehalf
[1] = latehalf
[1];
2096 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2097 if the upper part of reg N does not appear in the MEM, arrange to
2098 emit the move late-half first. Otherwise, compute the MEM address
2099 into the upper part of N and use that as a pointer to the memory
2101 if (optype0
== REGOP
2102 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2104 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2106 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2107 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2109 /* If both halves of dest are used in the src memory address,
2110 compute the address into latehalf of dest.
2111 Note that this can't happen if the dest is two data regs. */
2113 xops
[0] = latehalf
[0];
2114 xops
[1] = XEXP (operands
[1], 0);
2115 output_asm_insn ("lea %a1,%0", xops
);
2116 if (GET_MODE (operands
[1]) == XFmode
)
2118 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2119 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2120 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2124 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2125 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2129 && reg_overlap_mentioned_p (middlehalf
[0],
2130 XEXP (operands
[1], 0)))
2132 /* Check for two regs used by both source and dest.
2133 Note that this can't happen if the dest is all data regs.
2134 It can happen if the dest is d6, d7, a0.
2135 But in that case, latehalf is an addr reg, so
2136 the code at compadr does ok. */
2138 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2139 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2142 /* JRV says this can't happen: */
2143 if (addreg0
|| addreg1
)
2146 /* Only the middle reg conflicts; simply put it last. */
2147 output_asm_insn (singlemove_string (operands
), operands
);
2148 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2149 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2152 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2153 /* If the low half of dest is mentioned in the source memory
2154 address, the arrange to emit the move late half first. */
2155 dest_overlapped_low
= 1;
2158 /* If one or both operands autodecrementing,
2159 do the two words, high-numbered first. */
2161 /* Likewise, the first move would clobber the source of the second one,
2162 do them in the other order. This happens only for registers;
2163 such overlap can't happen in memory unless the user explicitly
2164 sets it up, and that is an undefined circumstance. */
2166 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2167 || (optype0
== REGOP
&& optype1
== REGOP
2168 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2169 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2170 || dest_overlapped_low
)
2172 /* Make any unoffsettable addresses point at high-numbered word. */
2176 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2178 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2183 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2185 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2189 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2191 /* Undo the adds we just did. */
2193 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2195 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2199 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2201 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2203 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2206 /* Do low-numbered word. */
2207 return singlemove_string (operands
);
2210 /* Normal case: do the two words, low-numbered first. */
2212 output_asm_insn (singlemove_string (operands
), operands
);
2214 /* Do the middle one of the three words for long double */
2218 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2220 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2222 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2225 /* Make any unoffsettable addresses point at high-numbered word. */
2227 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2229 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2232 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2234 /* Undo the adds we just did. */
2238 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2240 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2245 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2247 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2253 /* Return a REG that occurs in ADDR with coefficient 1.
2254 ADDR can be effectively incremented by incrementing REG. */
2257 find_addr_reg (rtx addr
)
2259 while (GET_CODE (addr
) == PLUS
)
2261 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2262 addr
= XEXP (addr
, 0);
2263 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2264 addr
= XEXP (addr
, 1);
2265 else if (CONSTANT_P (XEXP (addr
, 0)))
2266 addr
= XEXP (addr
, 1);
2267 else if (CONSTANT_P (XEXP (addr
, 1)))
2268 addr
= XEXP (addr
, 0);
2272 if (GET_CODE (addr
) == REG
)
2277 /* Output assembler code to perform a 32-bit 3-operand add. */
2280 output_addsi3 (rtx
*operands
)
2282 if (! operands_match_p (operands
[0], operands
[1]))
2284 if (!ADDRESS_REG_P (operands
[1]))
2286 rtx tmp
= operands
[1];
2288 operands
[1] = operands
[2];
2292 /* These insns can result from reloads to access
2293 stack slots over 64k from the frame pointer. */
2294 if (GET_CODE (operands
[2]) == CONST_INT
2295 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2296 return "move%.l %2,%0\n\tadd%.l %1,%0";
2297 if (GET_CODE (operands
[2]) == REG
)
2298 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2299 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2301 if (GET_CODE (operands
[2]) == CONST_INT
)
2303 if (INTVAL (operands
[2]) > 0
2304 && INTVAL (operands
[2]) <= 8)
2305 return "addq%.l %2,%0";
2306 if (INTVAL (operands
[2]) < 0
2307 && INTVAL (operands
[2]) >= -8)
2309 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2310 return "subq%.l %2,%0";
2312 /* On the CPU32 it is faster to use two addql instructions to
2313 add a small integer (8 < N <= 16) to a register.
2314 Likewise for subql. */
2315 if (TARGET_CPU32
&& REG_P (operands
[0]))
2317 if (INTVAL (operands
[2]) > 8
2318 && INTVAL (operands
[2]) <= 16)
2320 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2321 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2323 if (INTVAL (operands
[2]) < -8
2324 && INTVAL (operands
[2]) >= -16)
2326 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2327 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2330 if (ADDRESS_REG_P (operands
[0])
2331 && INTVAL (operands
[2]) >= -0x8000
2332 && INTVAL (operands
[2]) < 0x8000)
2335 return "add%.w %2,%0";
2337 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2340 return "add%.l %2,%0";
2343 /* Store in cc_status the expressions that the condition codes will
2344 describe after execution of an instruction whose pattern is EXP.
2345 Do not alter them if the instruction would not alter the cc's. */
2347 /* On the 68000, all the insns to store in an address register fail to
2348 set the cc's. However, in some cases these instructions can make it
2349 possibly invalid to use the saved cc's. In those cases we clear out
2350 some or all of the saved cc's so they won't be used. */
2353 notice_update_cc (rtx exp
, rtx insn
)
2355 if (GET_CODE (exp
) == SET
)
2357 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2361 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2363 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2364 cc_status
.value1
= 0;
2365 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2366 cc_status
.value2
= 0;
2368 else if (!FP_REG_P (SET_DEST (exp
))
2369 && SET_DEST (exp
) != cc0_rtx
2370 && (FP_REG_P (SET_SRC (exp
))
2371 || GET_CODE (SET_SRC (exp
)) == FIX
2372 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2373 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2377 /* A pair of move insns doesn't produce a useful overall cc. */
2378 else if (!FP_REG_P (SET_DEST (exp
))
2379 && !FP_REG_P (SET_SRC (exp
))
2380 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2381 && (GET_CODE (SET_SRC (exp
)) == REG
2382 || GET_CODE (SET_SRC (exp
)) == MEM
2383 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2387 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2391 else if (XEXP (exp
, 0) != pc_rtx
)
2393 cc_status
.flags
= 0;
2394 cc_status
.value1
= XEXP (exp
, 0);
2395 cc_status
.value2
= XEXP (exp
, 1);
2398 else if (GET_CODE (exp
) == PARALLEL
2399 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2401 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2403 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2405 cc_status
.flags
= 0;
2406 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2407 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2412 if (cc_status
.value2
!= 0
2413 && ADDRESS_REG_P (cc_status
.value2
)
2414 && GET_MODE (cc_status
.value2
) == QImode
)
2416 if (cc_status
.value2
!= 0)
2417 switch (GET_CODE (cc_status
.value2
))
2419 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2420 case ROTATE
: case ROTATERT
:
2421 /* These instructions always clear the overflow bit, and set
2422 the carry to the bit shifted out. */
2423 /* ??? We don't currently have a way to signal carry not valid,
2424 nor do we check for it in the branch insns. */
2428 case PLUS
: case MINUS
: case MULT
:
2429 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2430 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2431 cc_status
.flags
|= CC_NO_OVERFLOW
;
2434 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2435 ends with a move insn moving r2 in r2's mode.
2436 Thus, the cc's are set for r2.
2437 This can set N bit spuriously. */
2438 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2443 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2445 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2446 cc_status
.value2
= 0;
2447 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2448 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2449 cc_status
.flags
= CC_IN_68881
;
2453 output_move_const_double (rtx
*operands
)
2455 int code
= standard_68881_constant_p (operands
[1]);
2459 static char buf
[40];
2461 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2464 return "fmove%.d %1,%0";
2468 output_move_const_single (rtx
*operands
)
2470 int code
= standard_68881_constant_p (operands
[1]);
2474 static char buf
[40];
2476 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2479 return "fmove%.s %f1,%0";
2482 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2483 from the "fmovecr" instruction.
2484 The value, anded with 0xff, gives the code to use in fmovecr
2485 to get the desired constant. */
2487 /* This code has been fixed for cross-compilation. */
2489 static int inited_68881_table
= 0;
2491 static const char *const strings_68881
[7] = {
2501 static const int codes_68881
[7] = {
2511 REAL_VALUE_TYPE values_68881
[7];
2513 /* Set up values_68881 array by converting the decimal values
2514 strings_68881 to binary. */
2517 init_68881_table (void)
2521 enum machine_mode mode
;
2524 for (i
= 0; i
< 7; i
++)
2528 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2529 values_68881
[i
] = r
;
2531 inited_68881_table
= 1;
2535 standard_68881_constant_p (rtx x
)
2540 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2541 used at all on those chips. */
2542 if (TARGET_68040
|| TARGET_68060
)
2545 if (! inited_68881_table
)
2546 init_68881_table ();
2548 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2550 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2552 for (i
= 0; i
< 6; i
++)
2554 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2555 return (codes_68881
[i
]);
2558 if (GET_MODE (x
) == SFmode
)
2561 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2562 return (codes_68881
[6]);
2564 /* larger powers of ten in the constants ram are not used
2565 because they are not equal to a `double' C constant. */
2569 /* If X is a floating-point constant, return the logarithm of X base 2,
2570 or 0 if X is not a power of 2. */
2573 floating_exact_log2 (rtx x
)
2575 REAL_VALUE_TYPE r
, r1
;
2578 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2580 if (REAL_VALUES_LESS (r
, dconst1
))
2583 exp
= real_exponent (&r
);
2584 real_2expN (&r1
, exp
);
2585 if (REAL_VALUES_EQUAL (r1
, r
))
2591 /* A C compound statement to output to stdio stream STREAM the
2592 assembler syntax for an instruction operand X. X is an RTL
2595 CODE is a value that can be used to specify one of several ways
2596 of printing the operand. It is used when identical operands
2597 must be printed differently depending on the context. CODE
2598 comes from the `%' specification that was used to request
2599 printing of the operand. If the specification was just `%DIGIT'
2600 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2601 is the ASCII code for LTR.
2603 If X is a register, this macro should print the register's name.
2604 The names can be found in an array `reg_names' whose type is
2605 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2607 When the machine description has a specification `%PUNCT' (a `%'
2608 followed by a punctuation character), this macro is called with
2609 a null pointer for X and the punctuation character for CODE.
2611 The m68k specific codes are:
2613 '.' for dot needed in Motorola-style opcode names.
2614 '-' for an operand pushing on the stack:
2615 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2616 '+' for an operand pushing on the stack:
2617 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2618 '@' for a reference to the top word on the stack:
2619 sp@, (sp) or (%sp) depending on the style of syntax.
2620 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2621 but & in SGS syntax).
2622 '!' for the cc register (used in an `and to cc' insn).
2623 '$' for the letter `s' in an op code, but only on the 68040.
2624 '&' for the letter `d' in an op code, but only on the 68040.
2625 '/' for register prefix needed by longlong.h.
2627 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2628 'd' to force memory addressing to be absolute, not relative.
2629 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2630 'o' for operands to go directly to output_operand_address (bypassing
2631 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2632 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2633 or print pair of registers as rx:ry.
2638 print_operand (FILE *file
, rtx op
, int letter
)
2643 fprintf (file
, ".");
2645 else if (letter
== '#')
2646 asm_fprintf (file
, "%I");
2647 else if (letter
== '-')
2648 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2649 else if (letter
== '+')
2650 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2651 else if (letter
== '@')
2652 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2653 else if (letter
== '!')
2654 asm_fprintf (file
, "%Rfpcr");
2655 else if (letter
== '$')
2657 if (TARGET_68040_ONLY
)
2658 fprintf (file
, "s");
2660 else if (letter
== '&')
2662 if (TARGET_68040_ONLY
)
2663 fprintf (file
, "d");
2665 else if (letter
== '/')
2666 asm_fprintf (file
, "%R");
2667 else if (letter
== 'o')
2669 /* This is only for direct addresses with TARGET_PCREL */
2670 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2673 output_addr_const (file
, XEXP (op
, 0));
2675 else if (GET_CODE (op
) == REG
)
2678 /* Print out the second register name of a register pair.
2679 I.e., R (6) => 7. */
2680 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2682 fputs (M68K_REGNAME(REGNO (op
)), file
);
2684 else if (GET_CODE (op
) == MEM
)
2686 output_address (XEXP (op
, 0));
2687 if (letter
== 'd' && ! TARGET_68020
2688 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2689 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2690 && INTVAL (XEXP (op
, 0)) < 0x8000
2691 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2692 fprintf (file
, MOTOROLA
? ".l" : ":l");
2694 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2697 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2698 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2700 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2703 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2704 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2706 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2709 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2710 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2714 /* Use `print_operand_address' instead of `output_addr_const'
2715 to ensure that we print relevant PIC stuff. */
2716 asm_fprintf (file
, "%I");
2718 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2719 print_operand_address (file
, op
);
2721 output_addr_const (file
, op
);
2726 /* A C compound statement to output to stdio stream STREAM the
2727 assembler syntax for an instruction operand that is a memory
2728 reference whose address is ADDR. ADDR is an RTL expression.
2730 Note that this contains a kludge that knows that the only reason
2731 we have an address (plus (label_ref...) (reg...)) when not generating
2732 PIC code is in the insn before a tablejump, and we know that m68k.md
2733 generates a label LInnn: on such an insn.
2735 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2736 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2738 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2739 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2740 we want. This difference can be accommodated by using an assembler
2741 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2742 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2743 macro. See m68k/sgs.h for an example; for versions without the bug.
2744 Some assemblers refuse all the above solutions. The workaround is to
2745 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2748 They also do not like things like "pea 1.w", so we simple leave off
2749 the .w on small constants.
2751 This routine is responsible for distinguishing between -fpic and -fPIC
2752 style relocations in an address. When generating -fpic code the
2753 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
2754 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
2757 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2758 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2759 #else /* !MOTOROLA */
2760 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2761 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2762 #endif /* !MOTOROLA */
2765 print_operand_address (FILE *file
, rtx addr
)
2767 register rtx reg1
, reg2
, breg
, ireg
;
2770 switch (GET_CODE (addr
))
2773 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2776 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2777 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2780 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2781 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2784 reg1
= reg2
= ireg
= breg
= offset
= 0;
2785 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2787 offset
= XEXP (addr
, 0);
2788 addr
= XEXP (addr
, 1);
2790 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2792 offset
= XEXP (addr
, 1);
2793 addr
= XEXP (addr
, 0);
2795 if (GET_CODE (addr
) != PLUS
)
2799 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2801 reg1
= XEXP (addr
, 0);
2802 addr
= XEXP (addr
, 1);
2804 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2806 reg1
= XEXP (addr
, 1);
2807 addr
= XEXP (addr
, 0);
2809 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2811 reg1
= XEXP (addr
, 0);
2812 addr
= XEXP (addr
, 1);
2814 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2816 reg1
= XEXP (addr
, 1);
2817 addr
= XEXP (addr
, 0);
2819 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2821 reg1
= XEXP (addr
, 0);
2822 addr
= XEXP (addr
, 1);
2824 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2826 reg1
= XEXP (addr
, 1);
2827 addr
= XEXP (addr
, 0);
2829 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2830 || GET_CODE (addr
) == SIGN_EXTEND
)
2842 #if 0 /* for OLD_INDEXING */
2843 else if (GET_CODE (addr
) == PLUS
)
2845 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2847 reg2
= XEXP (addr
, 0);
2848 addr
= XEXP (addr
, 1);
2850 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2852 reg2
= XEXP (addr
, 1);
2853 addr
= XEXP (addr
, 0);
2865 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2866 || GET_CODE (reg1
) == MULT
))
2867 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2872 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2877 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2878 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2881 if (GET_CODE (ireg
) == MULT
)
2883 scale
= INTVAL (XEXP (ireg
, 1));
2884 ireg
= XEXP (ireg
, 0);
2886 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2888 ASM_OUTPUT_CASE_FETCH (file
,
2889 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2890 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2891 fprintf (file
, "w");
2895 ASM_OUTPUT_CASE_FETCH (file
,
2896 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2897 M68K_REGNAME(REGNO (ireg
)));
2898 fprintf (file
, "l");
2901 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2905 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2906 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2908 ASM_OUTPUT_CASE_FETCH (file
,
2909 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2910 M68K_REGNAME(REGNO (breg
)));
2911 fprintf (file
, "l)");
2914 if (ireg
!= 0 || breg
!= 0)
2921 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2929 output_addr_const (file
, addr
);
2930 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2932 fprintf (file
, "@GOT");
2934 fprintf (file
, ".w");
2937 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2941 else /* !MOTOROLA */
2943 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2946 output_addr_const (file
, addr
);
2947 if (breg
== pic_offset_table_rtx
)
2951 fprintf (file
, ":w"); break;
2953 fprintf (file
, ":l"); break;
2961 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2963 scale
= INTVAL (XEXP (ireg
, 1));
2964 ireg
= XEXP (ireg
, 0);
2966 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2967 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2968 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2970 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2971 M68K_REGNAME(REGNO (ireg
)));
2973 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2977 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2978 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2980 ASM_OUTPUT_CASE_FETCH (file
,
2981 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2982 M68K_REGNAME(REGNO (reg1
)));
2983 fprintf (file
, "l)");
2986 /* FALL-THROUGH (is this really what we want?) */
2988 if (GET_CODE (addr
) == CONST_INT
2989 && INTVAL (addr
) < 0x8000
2990 && INTVAL (addr
) >= -0x8000)
2992 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2994 else if (GET_CODE (addr
) == CONST_INT
)
2996 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2998 else if (TARGET_PCREL
)
3001 output_addr_const (file
, addr
);
3003 asm_fprintf (file
, ":w,%Rpc)");
3005 asm_fprintf (file
, ":l,%Rpc)");
3009 /* Special case for SYMBOL_REF if the symbol name ends in
3010 `.<letter>', this can be mistaken as a size suffix. Put
3011 the name in parentheses. */
3012 if (GET_CODE (addr
) == SYMBOL_REF
3013 && strlen (XSTR (addr
, 0)) > 2
3014 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3017 output_addr_const (file
, addr
);
3021 output_addr_const (file
, addr
);
3027 /* Check for cases where a clr insns can be omitted from code using
3028 strict_low_part sets. For example, the second clrl here is not needed:
3029 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3031 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3032 insn we are checking for redundancy. TARGET is the register set by the
3036 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3041 p
= prev_nonnote_insn (first_insn
);
3045 /* If it isn't an insn, then give up. */
3046 if (GET_CODE (p
) != INSN
)
3049 if (reg_set_p (target
, p
))
3051 rtx set
= single_set (p
);
3054 /* If it isn't an easy to recognize insn, then give up. */
3058 dest
= SET_DEST (set
);
3060 /* If this sets the entire target register to zero, then our
3061 first_insn is redundant. */
3062 if (rtx_equal_p (dest
, target
)
3063 && SET_SRC (set
) == const0_rtx
)
3065 else if (GET_CODE (dest
) == STRICT_LOW_PART
3066 && GET_CODE (XEXP (dest
, 0)) == REG
3067 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3068 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3069 <= GET_MODE_SIZE (mode
)))
3070 /* This is a strict low part set which modifies less than
3071 we are using, so it is safe. */
3077 p
= prev_nonnote_insn (p
);
3083 /* Operand predicates for implementing asymmetric pc-relative addressing
3084 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3085 when used as a source operand, but not as a destination operand.
3087 We model this by restricting the meaning of the basic predicates
3088 (general_operand, memory_operand, etc) to forbid the use of this
3089 addressing mode, and then define the following predicates that permit
3090 this addressing mode. These predicates can then be used for the
3091 source operands of the appropriate instructions.
3093 n.b. While it is theoretically possible to change all machine patterns
3094 to use this addressing more where permitted by the architecture,
3095 it has only been implemented for "common" cases: SImode, HImode, and
3096 QImode operands, and only for the principle operations that would
3097 require this addressing mode: data movement and simple integer operations.
3099 In parallel with these new predicates, two new constraint letters
3100 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3101 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3102 In the pcrel case 's' is only valid in combination with 'a' registers.
3103 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3104 of how these constraints are used.
3106 The use of these predicates is strictly optional, though patterns that
3107 don't will cause an extra reload register to be allocated where one
3110 lea (abc:w,%pc),%a0 ; need to reload address
3111 moveq &1,%d1 ; since write to pc-relative space
3112 movel %d1,%a0@ ; is not allowed
3114 lea (abc:w,%pc),%a1 ; no need to reload address here
3115 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3117 For more info, consult tiemann@cygnus.com.
3120 All of the ugliness with predicates and constraints is due to the
3121 simple fact that the m68k does not allow a pc-relative addressing
3122 mode as a destination. gcc does not distinguish between source and
3123 destination addresses. Hence, if we claim that pc-relative address
3124 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3125 end up with invalid code. To get around this problem, we left
3126 pc-relative modes as invalid addresses, and then added special
3127 predicates and constraints to accept them.
3129 A cleaner way to handle this is to modify gcc to distinguish
3130 between source and destination addresses. We can then say that
3131 pc-relative is a valid source address but not a valid destination
3132 address, and hopefully avoid a lot of the predicate and constraint
3133 hackery. Unfortunately, this would be a pretty big change. It would
3134 be a useful change for a number of ports, but there aren't any current
3135 plans to undertake this.
3137 ***************************************************************************/
3141 output_andsi3 (rtx
*operands
)
3144 if (GET_CODE (operands
[2]) == CONST_INT
3145 && (INTVAL (operands
[2]) | 0xffff) == -1
3146 && (DATA_REG_P (operands
[0])
3147 || offsettable_memref_p (operands
[0]))
3148 && !TARGET_COLDFIRE
)
3150 if (GET_CODE (operands
[0]) != REG
)
3151 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3152 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3153 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3155 if (operands
[2] == const0_rtx
)
3157 return "and%.w %2,%0";
3159 if (GET_CODE (operands
[2]) == CONST_INT
3160 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3161 && (DATA_REG_P (operands
[0])
3162 || offsettable_memref_p (operands
[0])))
3164 if (DATA_REG_P (operands
[0]))
3166 operands
[1] = GEN_INT (logval
);
3170 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3171 operands
[1] = GEN_INT (logval
% 8);
3173 /* This does not set condition codes in a standard way. */
3175 return "bclr %1,%0";
3177 return "and%.l %2,%0";
3181 output_iorsi3 (rtx
*operands
)
3183 register int logval
;
3184 if (GET_CODE (operands
[2]) == CONST_INT
3185 && INTVAL (operands
[2]) >> 16 == 0
3186 && (DATA_REG_P (operands
[0])
3187 || offsettable_memref_p (operands
[0]))
3188 && !TARGET_COLDFIRE
)
3190 if (GET_CODE (operands
[0]) != REG
)
3191 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3192 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3194 if (INTVAL (operands
[2]) == 0xffff)
3195 return "mov%.w %2,%0";
3196 return "or%.w %2,%0";
3198 if (GET_CODE (operands
[2]) == CONST_INT
3199 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3200 && (DATA_REG_P (operands
[0])
3201 || offsettable_memref_p (operands
[0])))
3203 if (DATA_REG_P (operands
[0]))
3204 operands
[1] = GEN_INT (logval
);
3207 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3208 operands
[1] = GEN_INT (logval
% 8);
3211 return "bset %1,%0";
3213 return "or%.l %2,%0";
3217 output_xorsi3 (rtx
*operands
)
3219 register int logval
;
3220 if (GET_CODE (operands
[2]) == CONST_INT
3221 && INTVAL (operands
[2]) >> 16 == 0
3222 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3223 && !TARGET_COLDFIRE
)
3225 if (! DATA_REG_P (operands
[0]))
3226 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3227 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3229 if (INTVAL (operands
[2]) == 0xffff)
3231 return "eor%.w %2,%0";
3233 if (GET_CODE (operands
[2]) == CONST_INT
3234 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3235 && (DATA_REG_P (operands
[0])
3236 || offsettable_memref_p (operands
[0])))
3238 if (DATA_REG_P (operands
[0]))
3239 operands
[1] = GEN_INT (logval
);
3242 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3243 operands
[1] = GEN_INT (logval
% 8);
3246 return "bchg %1,%0";
3248 return "eor%.l %2,%0";
3251 #ifdef M68K_TARGET_COFF
3253 /* Output assembly to switch to section NAME with attribute FLAGS. */
3256 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3257 tree decl ATTRIBUTE_UNUSED
)
3261 if (flags
& SECTION_WRITE
)
3266 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3269 #endif /* M68K_TARGET_COFF */
3272 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3273 HOST_WIDE_INT delta
,
3274 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3280 if (delta
> 0 && delta
<= 8)
3281 asm_fprintf (file
, MOTOROLA
?
3282 "\taddq.l %I%d,4(%Rsp)\n" :
3283 "\taddql %I%d,%Rsp@(4)\n",
3285 else if (delta
< 0 && delta
>= -8)
3286 asm_fprintf (file
, MOTOROLA
?
3287 "\tsubq.l %I%d,4(%Rsp)\n" :
3288 "\tsubql %I%d,%Rsp@(4)\n",
3290 else if (TARGET_COLDFIRE
)
3292 /* ColdFire can't add/sub a constant to memory unless it is in
3293 the range of addq/subq. So load the value into %d0 and
3294 then add it to 4(%sp). */
3295 if (delta
>= -128 && delta
<= 127)
3296 asm_fprintf (file
, MOTOROLA
?
3297 "\tmoveq.l %I%wd,%Rd0\n" :
3298 "\tmoveql %I%wd,%Rd0\n", delta
);
3300 asm_fprintf (file
, MOTOROLA
?
3301 "\tmove.l %I%wd,%Rd0\n" :
3302 "\tmovel %I%wd,%Rd0\n", delta
);
3303 asm_fprintf (file
, MOTOROLA
?
3304 "\tadd.l %Rd0,4(%Rsp)\n" :
3305 "\taddl %Rd0,%Rsp@(4)\n");
3308 asm_fprintf (file
, MOTOROLA
?
3309 "\tadd.l %I%wd,4(%Rsp)\n" :
3310 "\taddl %I%wd,%Rsp@(4)\n",
3313 xops
[0] = DECL_RTL (function
);
3315 /* Logic taken from call patterns in m68k.md. */
3320 else if ((flag_pic
== 1) || TARGET_68020
)
3323 #if defined(USE_GAS)
3324 fmt
= "bra.l %0@PLTPC";
3326 fmt
= "bra %0@PLTPC";
3328 else /* !MOTOROLA */
3335 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3336 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3338 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3342 #if MOTOROLA && !defined (USE_GAS)
3349 output_asm_insn (fmt
, xops
);
3352 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3355 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3356 int incoming ATTRIBUTE_UNUSED
)
3358 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3361 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3363 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3364 unsigned int new_reg
)
3367 /* Interrupt functions can only use registers that have already been
3368 saved by the prologue, even if they would normally be
3371 if (m68k_interrupt_function_p (current_function_decl
)
3372 && !regs_ever_live
[new_reg
])