1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static rtx
find_addr_reg (rtx
);
107 static const char *singlemove_string (rtx
*);
108 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
109 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
110 #ifdef M68K_TARGET_COFF
111 static void m68k_coff_asm_named_section (const char *, unsigned int);
112 #endif /* M68K_TARGET_COFF */
113 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
114 HOST_WIDE_INT
, tree
);
115 static rtx
m68k_struct_value_rtx (tree
, int);
116 static bool m68k_interrupt_function_p (tree func
);
117 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
118 tree args
, int flags
,
120 static void m68k_compute_frame_layout (void);
121 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
122 static int const_int_cost (rtx
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Specify the identification number of the library being built */
127 const char *m68k_library_id_string
;
129 /* Nonzero if the last compare/test insn had FP operands. The
130 sCC expanders peek at this to determine what to do for the
131 68060, which has no fsCC instructions. */
132 int m68k_last_compare_had_fp_operands
;
134 /* Initialize the GCC target structure. */
136 #if INT_OP_GROUP == INT_OP_DOT_WORD
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
141 #if INT_OP_GROUP == INT_OP_NO_DOT
142 #undef TARGET_ASM_BYTE_OP
143 #define TARGET_ASM_BYTE_OP "\tbyte\t"
144 #undef TARGET_ASM_ALIGNED_HI_OP
145 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
146 #undef TARGET_ASM_ALIGNED_SI_OP
147 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
150 #if INT_OP_GROUP == INT_OP_DC
151 #undef TARGET_ASM_BYTE_OP
152 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
155 #undef TARGET_ASM_ALIGNED_SI_OP
156 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
159 #undef TARGET_ASM_UNALIGNED_HI_OP
160 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
161 #undef TARGET_ASM_UNALIGNED_SI_OP
162 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
164 #undef TARGET_ASM_FUNCTION_PROLOGUE
165 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
166 #undef TARGET_ASM_FUNCTION_EPILOGUE
167 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
169 #undef TARGET_ASM_OUTPUT_MI_THUNK
170 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
171 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
172 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
174 #undef TARGET_ASM_FILE_START_APP_OFF
175 #define TARGET_ASM_FILE_START_APP_OFF true
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS m68k_rtx_costs
180 #undef TARGET_ATTRIBUTE_TABLE
181 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
183 #undef TARGET_PROMOTE_PROTOTYPES
184 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
186 #undef TARGET_STRUCT_VALUE_RTX
187 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
189 static const struct attribute_spec m68k_attribute_table
[] =
191 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
192 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
193 { NULL
, 0, 0, false, false, false, NULL
}
196 struct gcc_target targetm
= TARGET_INITIALIZER
;
198 /* Sometimes certain combinations of command options do not make
199 sense on a particular target machine. You can define a macro
200 `OVERRIDE_OPTIONS' to take account of this. This macro, if
201 defined, is executed once just after all the command options have
204 Don't use this macro to turn on various extra optimizations for
205 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
208 override_options (void)
210 /* Library identification */
211 if (m68k_library_id_string
)
215 if (! TARGET_ID_SHARED_LIBRARY
)
216 error ("-mshared-library-id= specified without -mid-shared-library");
217 id
= atoi (m68k_library_id_string
);
218 if (id
< 0 || id
> MAX_LIBRARY_ID
)
219 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
221 /* From now on, m68k_library_id_string will contain the library offset. */
222 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
225 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
227 m68k_library_id_string
= "_current_shared_library_a5_offset_";
229 /* Sanity check to ensure that msep-data and mid-sahred-library are not
230 * both specified together. Doing so simply doesn't make sense.
232 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
233 error ("cannot specify both -msep-data and -mid-shared-library");
235 /* If we're generating code for a separate A5 relative data segment,
236 * we've got to enable -fPIC as well. This might be relaxable to
237 * -fpic but it hasn't been tested properly.
239 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
242 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
244 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
245 error("-fPIC is not currently supported on the 68000 or 68010\n");
247 /* ??? A historic way of turning on pic, or is this intended to
248 be an embedded thing that doesn't have the same name binding
249 significance that it does on hosted ELF systems? */
250 if (TARGET_PCREL
&& flag_pic
== 0)
253 /* Turn off function cse if we are doing PIC. We always want function call
254 to be done as `bsr foo@PLTPC', so it will force the assembler to create
255 the PLT entry for `foo'. Doing function cse will cause the address of
256 `foo' to be loaded into a register, which is exactly what we want to
257 avoid when we are doing PIC on svr4 m68k. */
259 flag_no_function_cse
= 1;
261 SUBTARGET_OVERRIDE_OPTIONS
;
264 /* Return nonzero if FUNC is an interrupt function as specified by the
265 "interrupt_handler" attribute. */
267 m68k_interrupt_function_p(tree func
)
271 if (TREE_CODE (func
) != FUNCTION_DECL
)
274 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
275 return (a
!= NULL_TREE
);
278 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
279 struct attribute_spec.handler. */
281 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
282 tree args ATTRIBUTE_UNUSED
,
283 int flags ATTRIBUTE_UNUSED
,
286 if (TREE_CODE (*node
) != FUNCTION_DECL
)
288 warning ("`%s' attribute only applies to functions",
289 IDENTIFIER_POINTER (name
));
290 *no_add_attrs
= true;
297 m68k_compute_frame_layout (void)
300 unsigned int mask
, rmask
;
301 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
303 /* Only compute the frame once per function.
304 Don't cache information until reload has been completed. */
305 if (current_frame
.funcdef_no
== current_function_funcdef_no
309 current_frame
.size
= (get_frame_size () + 3) & -4;
311 mask
= rmask
= saved
= 0;
312 for (regno
= 0; regno
< 16; regno
++)
313 if (m68k_save_reg (regno
, interrupt_handler
))
316 rmask
|= 1 << (15 - regno
);
319 current_frame
.offset
= saved
* 4;
320 current_frame
.reg_no
= saved
;
321 current_frame
.reg_mask
= mask
;
322 current_frame
.reg_rev_mask
= rmask
;
324 current_frame
.foffset
= 0;
325 mask
= rmask
= saved
= 0;
326 if (TARGET_68881
/* || TARGET_CFV4E */)
328 for (regno
= 16; regno
< 24; regno
++)
329 if (m68k_save_reg (regno
, interrupt_handler
))
331 mask
|= 1 << (regno
- 16);
332 rmask
|= 1 << (23 - regno
);
335 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
336 current_frame
.offset
+= current_frame
.foffset
;
338 current_frame
.fpu_no
= saved
;
339 current_frame
.fpu_mask
= mask
;
340 current_frame
.fpu_rev_mask
= rmask
;
342 /* Remember what function this frame refers to. */
343 current_frame
.funcdef_no
= current_function_funcdef_no
;
347 m68k_initial_elimination_offset (int from
, int to
)
349 /* FIXME: The correct offset to compute here would appear to be
350 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
351 but for some obscure reason, this must be 0 to get correct code. */
352 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
355 m68k_compute_frame_layout ();
357 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
358 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
359 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
360 return current_frame
.offset
+ current_frame
.size
;
365 /* Refer to the array `regs_ever_live' to determine which registers
366 to save; `regs_ever_live[I]' is nonzero if register number I
367 is ever used in the function. This function is responsible for
368 knowing which registers should not be saved even if used.
369 Return true if we need to save REGNO. */
372 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
374 if (flag_pic
&& current_function_uses_pic_offset_table
375 && regno
== PIC_OFFSET_TABLE_REGNUM
)
378 if (current_function_calls_eh_return
)
383 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
384 if (test
== INVALID_REGNUM
)
391 /* Fixed regs we never touch. */
392 if (fixed_regs
[regno
])
395 /* The frame pointer (if it is such) is handled specially. */
396 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
399 /* Interrupt handlers must also save call_used_regs
400 if they are live or when calling nested functions. */
401 if (interrupt_handler
)
403 if (regs_ever_live
[regno
])
406 if (!current_function_is_leaf
&& call_used_regs
[regno
])
410 /* Never need to save registers that aren't touched. */
411 if (!regs_ever_live
[regno
])
414 /* Otherwise save everything that isn't call-clobbered. */
415 return !call_used_regs
[regno
];
418 /* This function generates the assembly code for function entry.
419 STREAM is a stdio stream to output the code to.
420 SIZE is an int: how many units of temporary storage to allocate. */
423 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
425 HOST_WIDE_INT fsize_with_regs
;
426 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
428 m68k_compute_frame_layout();
430 /* If the stack limit is a symbol, we can check it here,
431 before actually allocating the space. */
432 if (current_function_limit_stack
433 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
434 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
435 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
437 /* On ColdFire add register save into initial stack frame setup, if possible. */
438 fsize_with_regs
= current_frame
.size
;
439 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
440 fsize_with_regs
+= current_frame
.reg_no
* 4;
442 if (frame_pointer_needed
)
444 if (current_frame
.size
== 0 && TARGET_68040
)
445 /* on the 68040, pea + move is faster than link.w 0 */
446 fprintf (stream
, MOTOROLA
?
447 "\tpea (%s)\n\tmove.l %s,%s\n" :
448 "\tpea %s@\n\tmovel %s,%s\n",
449 M68K_REGNAME(FRAME_POINTER_REGNUM
),
450 M68K_REGNAME(STACK_POINTER_REGNUM
),
451 M68K_REGNAME(FRAME_POINTER_REGNUM
));
452 else if (fsize_with_regs
< 0x8000)
453 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
454 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
455 else if (TARGET_68020
)
456 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
457 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
459 /* Adding negative number is faster on the 68040. */
460 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
461 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
462 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
464 if (dwarf2out_do_frame ())
467 l
= (char *) dwarf2out_cfi_label ();
469 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
470 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
471 cfa_offset
+= current_frame
.size
;
474 else if (fsize_with_regs
) /* !frame_pointer_needed */
476 if (fsize_with_regs
< 0x8000)
478 if (fsize_with_regs
<= 8)
480 if (!TARGET_COLDFIRE
)
481 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
484 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
487 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
488 /* On the CPU32 it is faster to use two subqw instructions to
489 subtract a small integer (8 < N <= 16) to a register. */
491 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
492 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
493 fsize_with_regs
- 8);
494 else if (TARGET_68040
)
495 /* Adding negative number is faster on the 68040. */
496 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
499 asm_fprintf (stream
, MOTOROLA
?
500 "\tlea (%wd,%Rsp),%Rsp\n" :
501 "\tlea %Rsp@(%wd),%Rsp\n",
504 else /* fsize_with_regs >= 0x8000 */
505 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
507 if (dwarf2out_do_frame ())
509 cfa_offset
+= current_frame
.size
+ 4;
510 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
512 } /* !frame_pointer_needed */
514 if (current_frame
.fpu_mask
)
516 asm_fprintf (stream
, MOTOROLA
?
517 "\tfmovm %I0x%x,-(%Rsp)\n" :
518 "\tfmovem %I0x%x,%Rsp@-\n",
519 current_frame
.fpu_mask
);
521 if (dwarf2out_do_frame ())
523 char *l
= (char *) dwarf2out_cfi_label ();
526 cfa_offset
+= current_frame
.fpu_no
* 12;
527 if (! frame_pointer_needed
)
528 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
529 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
530 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
531 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
535 /* If the stack limit is not a symbol, check it here.
536 This has the disadvantage that it may be too late... */
537 if (current_function_limit_stack
)
539 if (REG_P (stack_limit_rtx
))
540 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
541 M68K_REGNAME(REGNO (stack_limit_rtx
)));
542 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
543 warning ("stack limit expression is not supported");
546 if (current_frame
.reg_no
<= 2)
548 /* Store each separately in the same order moveml uses.
549 Using two movel instructions instead of a single moveml
550 is about 15% faster for the 68020 and 68030 at no expense
555 for (i
= 0; i
< 16; i
++)
556 if (current_frame
.reg_rev_mask
& (1 << i
))
558 asm_fprintf (stream
, MOTOROLA
?
559 "\t%Omove.l %s,-(%Rsp)\n" :
560 "\tmovel %s,%Rsp@-\n",
561 M68K_REGNAME(15 - i
));
562 if (dwarf2out_do_frame ())
564 char *l
= (char *) dwarf2out_cfi_label ();
567 if (! frame_pointer_needed
)
568 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
569 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
573 else if (current_frame
.reg_rev_mask
)
576 /* The ColdFire does not support the predecrement form of the
577 MOVEM instruction, so we must adjust the stack pointer and
578 then use the plain address register indirect mode.
579 The required register save space was combined earlier with
580 the fsize_with_regs amount. */
582 asm_fprintf (stream
, MOTOROLA
?
583 "\tmovm.l %I0x%x,(%Rsp)\n" :
584 "\tmoveml %I0x%x,%Rsp@\n",
585 current_frame
.reg_mask
);
587 asm_fprintf (stream
, MOTOROLA
?
588 "\tmovm.l %I0x%x,-(%Rsp)\n" :
589 "\tmoveml %I0x%x,%Rsp@-\n",
590 current_frame
.reg_rev_mask
);
591 if (dwarf2out_do_frame ())
593 char *l
= (char *) dwarf2out_cfi_label ();
596 cfa_offset
+= current_frame
.reg_no
* 4;
597 if (! frame_pointer_needed
)
598 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
599 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
600 if (current_frame
.reg_mask
& (1 << regno
))
601 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
604 if (!TARGET_SEP_DATA
&& flag_pic
&&
605 (current_function_uses_pic_offset_table
||
606 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
608 if (TARGET_ID_SHARED_LIBRARY
)
610 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
611 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
612 m68k_library_id_string
,
613 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
618 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
619 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
622 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
623 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
624 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
625 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
626 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
632 /* Return true if this function's epilogue can be output as RTL. */
635 use_return_insn (void)
637 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
640 /* We can output the epilogue as RTL only if no registers need to be
642 m68k_compute_frame_layout();
643 return current_frame
.reg_no
? false : true;
646 /* This function generates the assembly code for function exit,
647 on machines that need it.
649 The function epilogue should not depend on the current stack pointer!
650 It should use the frame pointer only, if there is a frame pointer.
651 This is mandatory because of alloca; we also take advantage of it to
652 omit stack adjustments before returning. */
655 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
657 HOST_WIDE_INT fsize
, fsize_with_regs
;
659 bool restore_from_sp
= false;
660 rtx insn
= get_last_insn ();
662 m68k_compute_frame_layout();
664 /* If the last insn was a BARRIER, we don't have to write any code. */
665 if (GET_CODE (insn
) == NOTE
)
666 insn
= prev_nonnote_insn (insn
);
667 if (insn
&& GET_CODE (insn
) == BARRIER
)
669 /* Output just a no-op so that debuggers don't get confused
670 about which function the pc is in at this address. */
671 fprintf (stream
, "\tnop\n");
675 #ifdef FUNCTION_EXTRA_EPILOGUE
676 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
679 fsize
= current_frame
.size
;
681 /* FIXME : leaf_function_p below is too strong.
682 What we really need to know there is if there could be pending
683 stack adjustment needed at that point. */
684 restore_from_sp
= ! frame_pointer_needed
685 || (! current_function_calls_alloca
&& leaf_function_p ());
687 /* fsize_with_regs is the size we need to adjust the sp when
688 popping the frame. */
689 fsize_with_regs
= fsize
;
691 /* Because the ColdFire doesn't support moveml with
692 complex address modes, we must adjust the stack manually
693 after restoring registers. When the frame pointer isn't used,
694 we can merge movem adjustment into frame unlinking
695 made immediately after it. */
696 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
697 fsize_with_regs
+= current_frame
.reg_no
* 4;
699 if (current_frame
.offset
+ fsize
>= 0x8000
701 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
703 /* Because the ColdFire doesn't support moveml with
704 complex address modes we make an extra correction here. */
706 fsize
+= current_frame
.offset
;
708 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
709 fsize
= 0, big
= true;
711 if (current_frame
.reg_no
<= 2)
713 /* Restore each separately in the same order moveml does.
714 Using two movel instructions instead of a single moveml
715 is about 15% faster for the 68020 and 68030 at no expense
719 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
721 for (i
= 0; i
< 16; i
++)
722 if (current_frame
.reg_mask
& (1 << i
))
727 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
729 M68K_REGNAME(FRAME_POINTER_REGNUM
),
732 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
733 M68K_REGNAME(FRAME_POINTER_REGNUM
),
737 else if (restore_from_sp
)
738 asm_fprintf (stream
, MOTOROLA
?
739 "\t%Omove.l (%Rsp)+,%s\n" :
740 "\tmovel %Rsp@+,%s\n",
745 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
747 M68K_REGNAME(FRAME_POINTER_REGNUM
),
750 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
751 M68K_REGNAME(FRAME_POINTER_REGNUM
),
758 else if (current_frame
.reg_mask
)
760 /* The ColdFire requires special handling due to its limited moveml insn. */
765 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
766 M68K_REGNAME(FRAME_POINTER_REGNUM
));
767 asm_fprintf (stream
, MOTOROLA
?
768 "\tmovm.l (%Ra1),%I0x%x\n" :
769 "\tmoveml %Ra1@,%I0x%x\n",
770 current_frame
.reg_mask
);
772 else if (restore_from_sp
)
773 asm_fprintf (stream
, MOTOROLA
?
774 "\tmovm.l (%Rsp),%I0x%x\n" :
775 "\tmoveml %Rsp@,%I0x%x\n",
776 current_frame
.reg_mask
);
780 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
781 current_frame
.offset
+ fsize
,
782 M68K_REGNAME(FRAME_POINTER_REGNUM
),
783 current_frame
.reg_mask
);
785 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
786 M68K_REGNAME(FRAME_POINTER_REGNUM
),
787 current_frame
.offset
+ fsize
,
788 current_frame
.reg_mask
);
791 else /* !TARGET_COLDFIRE */
796 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
797 current_frame
.offset
+ fsize
,
798 M68K_REGNAME(FRAME_POINTER_REGNUM
),
799 current_frame
.reg_mask
);
801 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
802 M68K_REGNAME(FRAME_POINTER_REGNUM
),
803 current_frame
.offset
+ fsize
,
804 current_frame
.reg_mask
);
806 else if (restore_from_sp
)
808 asm_fprintf (stream
, MOTOROLA
?
809 "\tmovm.l (%Rsp)+,%I0x%x\n" :
810 "\tmoveml %Rsp@+,%I0x%x\n",
811 current_frame
.reg_mask
);
816 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
817 current_frame
.offset
+ fsize
,
818 M68K_REGNAME(FRAME_POINTER_REGNUM
),
819 current_frame
.reg_mask
);
821 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
822 M68K_REGNAME(FRAME_POINTER_REGNUM
),
823 current_frame
.offset
+ fsize
,
824 current_frame
.reg_mask
);
828 if (current_frame
.fpu_rev_mask
)
833 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
834 current_frame
.foffset
+ fsize
,
835 M68K_REGNAME(FRAME_POINTER_REGNUM
),
836 current_frame
.fpu_rev_mask
);
838 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.foffset
+ fsize
,
841 current_frame
.fpu_rev_mask
);
843 else if (restore_from_sp
)
846 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
847 current_frame
.fpu_rev_mask
);
849 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
850 current_frame
.fpu_rev_mask
);
855 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
856 current_frame
.foffset
+ fsize
,
857 M68K_REGNAME(FRAME_POINTER_REGNUM
),
858 current_frame
.fpu_rev_mask
);
860 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
861 M68K_REGNAME(FRAME_POINTER_REGNUM
),
862 current_frame
.foffset
+ fsize
,
863 current_frame
.fpu_rev_mask
);
866 if (frame_pointer_needed
)
867 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
868 else if (fsize_with_regs
)
870 if (fsize_with_regs
<= 8)
872 if (!TARGET_COLDFIRE
)
873 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
876 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
879 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
881 /* On the CPU32 it is faster to use two addqw instructions to
882 add a small integer (8 < N <= 16) to a register. */
883 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
884 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
885 fsize_with_regs
- 8);
887 else if (fsize_with_regs
< 0x8000)
890 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
893 asm_fprintf (stream
, MOTOROLA
?
894 "\tlea (%wd,%Rsp),%Rsp\n" :
895 "\tlea %Rsp@(%wd),%Rsp\n",
899 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
901 if (current_function_calls_eh_return
)
902 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
903 if (m68k_interrupt_function_p (current_function_decl
))
904 fprintf (stream
, "\trte\n");
905 else if (current_function_pops_args
)
906 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
908 fprintf (stream
, "\trts\n");
911 /* Similar to general_operand, but exclude stack_pointer_rtx. */
914 not_sp_operand (rtx op
, enum machine_mode mode
)
916 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
919 /* Return true if X is a valid comparison operator for the dbcc
922 Note it rejects floating point comparison operators.
923 (In the future we could use Fdbcc).
925 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
928 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
930 switch (GET_CODE (x
))
932 case EQ
: case NE
: case GTU
: case LTU
:
936 /* Reject some when CC_NO_OVERFLOW is set. This may be over
938 case GT
: case LT
: case GE
: case LE
:
939 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
945 /* Return nonzero if flags are currently in the 68881 flag register. */
947 flags_in_68881 (void)
949 /* We could add support for these in the future */
950 return cc_status
.flags
& CC_IN_68881
;
953 /* Output a BSR instruction suitable for PIC code. */
955 m68k_output_pic_call(rtx dest
)
959 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
961 /* We output a BSR instruction if we're using -fpic or we're building for
962 * a target that supports long branches. If we're building -fPIC on the
963 * 68000, 68010 or ColdFire we generate one of two sequences:
964 * a shorter one that uses a GOT entry or a longer one that doesn't.
965 * We'll use the -Os command-line flag to decide which to generate.
966 * Both sequences take the same time to execute on the ColdFire.
968 else if (TARGET_PCREL
)
970 else if ((flag_pic
== 1) || TARGET_68020
)
972 out
= "bsr.l %0@PLTPC";
974 out
= "bsr %0@PLTPC";
976 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
977 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
979 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
981 output_asm_insn(out
, &dest
);
984 /* Output a dbCC; jCC sequence. Note we do not handle the
985 floating point version of this sequence (Fdbcc). We also
986 do not handle alternative conditions when CC_NO_OVERFLOW is
987 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
988 kick those out before we get here. */
991 output_dbcc_and_branch (rtx
*operands
)
993 switch (GET_CODE (operands
[3]))
996 output_asm_insn (MOTOROLA
?
997 "dbeq %0,%l1\n\tjbeq %l2" :
998 "dbeq %0,%l1\n\tjeq %l2",
1003 output_asm_insn (MOTOROLA
?
1004 "dbne %0,%l1\n\tjbne %l2" :
1005 "dbne %0,%l1\n\tjne %l2",
1010 output_asm_insn (MOTOROLA
?
1011 "dbgt %0,%l1\n\tjbgt %l2" :
1012 "dbgt %0,%l1\n\tjgt %l2",
1017 output_asm_insn (MOTOROLA
?
1018 "dbhi %0,%l1\n\tjbhi %l2" :
1019 "dbhi %0,%l1\n\tjhi %l2",
1024 output_asm_insn (MOTOROLA
?
1025 "dblt %0,%l1\n\tjblt %l2" :
1026 "dblt %0,%l1\n\tjlt %l2",
1031 output_asm_insn (MOTOROLA
?
1032 "dbcs %0,%l1\n\tjbcs %l2" :
1033 "dbcs %0,%l1\n\tjcs %l2",
1038 output_asm_insn (MOTOROLA
?
1039 "dbge %0,%l1\n\tjbge %l2" :
1040 "dbge %0,%l1\n\tjge %l2",
1045 output_asm_insn (MOTOROLA
?
1046 "dbcc %0,%l1\n\tjbcc %l2" :
1047 "dbcc %0,%l1\n\tjcc %l2",
1052 output_asm_insn (MOTOROLA
?
1053 "dble %0,%l1\n\tjble %l2" :
1054 "dble %0,%l1\n\tjle %l2",
1059 output_asm_insn (MOTOROLA
?
1060 "dbls %0,%l1\n\tjbls %l2" :
1061 "dbls %0,%l1\n\tjls %l2",
1069 /* If the decrement is to be done in SImode, then we have
1070 to compensate for the fact that dbcc decrements in HImode. */
1071 switch (GET_MODE (operands
[0]))
1074 output_asm_insn (MOTOROLA
?
1075 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1076 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1089 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1092 enum rtx_code op_code
= GET_CODE (op
);
1094 /* This does not produce a useful cc. */
1097 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1098 below. Swap the operands and change the op if these requirements
1099 are not fulfilled. */
1100 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1104 operand1
= operand2
;
1106 op_code
= swap_condition (op_code
);
1108 loperands
[0] = operand1
;
1109 if (GET_CODE (operand1
) == REG
)
1110 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1112 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1113 if (operand2
!= const0_rtx
)
1115 loperands
[2] = operand2
;
1116 if (GET_CODE (operand2
) == REG
)
1117 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1119 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1121 loperands
[4] = gen_label_rtx();
1122 if (operand2
!= const0_rtx
)
1124 output_asm_insn (MOTOROLA
?
1125 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1126 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1131 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1132 output_asm_insn ("tst%.l %0", loperands
);
1135 output_asm_insn ("cmp%.w #0,%0", loperands
);
1138 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1140 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1141 output_asm_insn ("tst%.l %1", loperands
);
1143 output_asm_insn ("cmp%.w #0,%1", loperands
);
1146 loperands
[5] = dest
;
1151 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1152 CODE_LABEL_NUMBER (loperands
[4]));
1153 output_asm_insn ("seq %5", loperands
);
1157 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1158 CODE_LABEL_NUMBER (loperands
[4]));
1159 output_asm_insn ("sne %5", loperands
);
1163 loperands
[6] = gen_label_rtx();
1164 output_asm_insn (MOTOROLA
?
1165 "shi %5\n\tjbra %l6" :
1166 "shi %5\n\tjra %l6",
1168 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1169 CODE_LABEL_NUMBER (loperands
[4]));
1170 output_asm_insn ("sgt %5", loperands
);
1171 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1172 CODE_LABEL_NUMBER (loperands
[6]));
1176 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1177 CODE_LABEL_NUMBER (loperands
[4]));
1178 output_asm_insn ("shi %5", loperands
);
1182 loperands
[6] = gen_label_rtx();
1183 output_asm_insn (MOTOROLA
?
1184 "scs %5\n\tjbra %l6" :
1185 "scs %5\n\tjra %l6",
1187 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1188 CODE_LABEL_NUMBER (loperands
[4]));
1189 output_asm_insn ("slt %5", loperands
);
1190 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1191 CODE_LABEL_NUMBER (loperands
[6]));
1195 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1196 CODE_LABEL_NUMBER (loperands
[4]));
1197 output_asm_insn ("scs %5", loperands
);
1201 loperands
[6] = gen_label_rtx();
1202 output_asm_insn (MOTOROLA
?
1203 "scc %5\n\tjbra %l6" :
1204 "scc %5\n\tjra %l6",
1206 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1207 CODE_LABEL_NUMBER (loperands
[4]));
1208 output_asm_insn ("sge %5", loperands
);
1209 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1210 CODE_LABEL_NUMBER (loperands
[6]));
1214 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1215 CODE_LABEL_NUMBER (loperands
[4]));
1216 output_asm_insn ("scc %5", loperands
);
1220 loperands
[6] = gen_label_rtx();
1221 output_asm_insn (MOTOROLA
?
1222 "sls %5\n\tjbra %l6" :
1223 "sls %5\n\tjra %l6",
1225 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1226 CODE_LABEL_NUMBER (loperands
[4]));
1227 output_asm_insn ("sle %5", loperands
);
1228 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1229 CODE_LABEL_NUMBER (loperands
[6]));
1233 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1234 CODE_LABEL_NUMBER (loperands
[4]));
1235 output_asm_insn ("sls %5", loperands
);
1245 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1247 operands
[0] = countop
;
1248 operands
[1] = dataop
;
1250 if (GET_CODE (countop
) == CONST_INT
)
1252 register int count
= INTVAL (countop
);
1253 /* If COUNT is bigger than size of storage unit in use,
1254 advance to the containing unit of same size. */
1255 if (count
> signpos
)
1257 int offset
= (count
& ~signpos
) / 8;
1258 count
= count
& signpos
;
1259 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1261 if (count
== signpos
)
1262 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1264 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1266 /* These three statements used to use next_insns_test_no...
1267 but it appears that this should do the same job. */
1269 && next_insn_tests_no_inequality (insn
))
1272 && next_insn_tests_no_inequality (insn
))
1275 && next_insn_tests_no_inequality (insn
))
1278 cc_status
.flags
= CC_NOT_NEGATIVE
;
1280 return "btst %0,%1";
1283 /* Returns true if OP is either a symbol reference or a sum of a symbol
1284 reference and a constant. */
1287 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1289 switch (GET_CODE (op
))
1297 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1298 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1299 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1301 #if 0 /* Deleted, with corresponding change in m68k.h,
1302 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1304 return GET_MODE (op
) == mode
;
1312 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1315 extend_operator(rtx x
, enum machine_mode mode
)
1317 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1319 switch (GET_CODE(x
))
1330 /* Legitimize PIC addresses. If the address is already
1331 position-independent, we return ORIG. Newly generated
1332 position-independent addresses go to REG. If we need more
1333 than one register, we lose.
1335 An address is legitimized by making an indirect reference
1336 through the Global Offset Table with the name of the symbol
1339 The assembler and linker are responsible for placing the
1340 address of the symbol in the GOT. The function prologue
1341 is responsible for initializing a5 to the starting address
1344 The assembler is also responsible for translating a symbol name
1345 into a constant displacement from the start of the GOT.
1347 A quick example may make things a little clearer:
1349 When not generating PIC code to store the value 12345 into _foo
1350 we would generate the following code:
1354 When generating PIC two transformations are made. First, the compiler
1355 loads the address of foo into a register. So the first transformation makes:
1360 The code in movsi will intercept the lea instruction and call this
1361 routine which will transform the instructions into:
1363 movel a5@(_foo:w), a0
1367 That (in a nutshell) is how *all* symbol and label references are
1371 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1376 /* First handle a simple SYMBOL_REF or LABEL_REF */
1377 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1382 pic_ref
= gen_rtx_MEM (Pmode
,
1383 gen_rtx_PLUS (Pmode
,
1384 pic_offset_table_rtx
, orig
));
1385 current_function_uses_pic_offset_table
= 1;
1386 RTX_UNCHANGING_P (pic_ref
) = 1;
1387 emit_move_insn (reg
, pic_ref
);
1390 else if (GET_CODE (orig
) == CONST
)
1394 /* Make sure this has not already been legitimized. */
1395 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1396 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1402 /* legitimize both operands of the PLUS */
1403 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1405 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1406 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1407 base
== reg
? 0 : reg
);
1411 if (GET_CODE (orig
) == CONST_INT
)
1412 return plus_constant (base
, INTVAL (orig
));
1413 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1414 /* Likewise, should we set special REG_NOTEs here? */
1420 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1422 static CONST_METHOD
const_method (rtx
);
1424 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1427 const_method (rtx constant
)
1432 i
= INTVAL (constant
);
1436 /* The ColdFire doesn't have byte or word operations. */
1437 /* FIXME: This may not be useful for the m68060 either. */
1438 if (!TARGET_COLDFIRE
)
1440 /* if -256 < N < 256 but N is not in range for a moveq
1441 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1442 if (USE_MOVQ (i
^ 0xff))
1444 /* Likewise, try with not.w */
1445 if (USE_MOVQ (i
^ 0xffff))
1447 /* This is the only value where neg.w is useful */
1450 /* Try also with swap */
1452 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1458 /* Try using MVZ/MVS with an immediate value to load constants. */
1459 if (i
>= 0 && i
<= 65535)
1461 if (i
>= -32768 && i
<= 32767)
1465 /* Otherwise, use move.l */
1470 const_int_cost (rtx constant
)
1472 switch (const_method (constant
))
1475 /* Constants between -128 and 127 are cheap due to moveq */
1483 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1493 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1498 /* Constant zero is super cheap due to clr instruction. */
1499 if (x
== const0_rtx
)
1502 *total
= const_int_cost (x
);
1512 /* Make 0.0 cheaper than other floating constants to
1513 encourage creating tstsf and tstdf insns. */
1514 if (outer_code
== COMPARE
1515 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1521 /* These are vaguely right for a 68020. */
1522 /* The costs for long multiply have been adjusted to work properly
1523 in synth_mult on the 68020, relative to an average of the time
1524 for add and the time for shift, taking away a little more because
1525 sometimes move insns are needed. */
1526 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1527 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1528 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1529 TARGET_CFV3 ? 2 : 5)
1530 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1533 /* An lea costs about three times as much as a simple add. */
1534 if (GET_MODE (x
) == SImode
1535 && GET_CODE (XEXP (x
, 1)) == REG
1536 && GET_CODE (XEXP (x
, 0)) == MULT
1537 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1538 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1539 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1540 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1541 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1543 /* lea an@(dx:l:i),am */
1544 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1554 *total
= COSTS_N_INSNS(1);
1557 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1559 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1561 if (INTVAL (XEXP (x
, 1)) < 16)
1562 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1564 /* We're using clrw + swap for these cases. */
1565 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1568 *total
= COSTS_N_INSNS (10); /* worst case */
1571 /* A shift by a big integer takes an extra instruction. */
1572 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1573 && (INTVAL (XEXP (x
, 1)) == 16))
1575 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1578 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1579 && !(INTVAL (XEXP (x
, 1)) > 0
1580 && INTVAL (XEXP (x
, 1)) <= 8))
1582 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1588 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1589 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1590 && GET_MODE (x
) == SImode
)
1591 *total
= COSTS_N_INSNS (MULW_COST
);
1592 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1593 *total
= COSTS_N_INSNS (MULW_COST
);
1595 *total
= COSTS_N_INSNS (MULL_COST
);
1602 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1603 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1604 else if (TARGET_CF_HWDIV
)
1605 *total
= COSTS_N_INSNS (18);
1607 *total
= COSTS_N_INSNS (43); /* div.l */
1616 output_move_const_into_data_reg (rtx
*operands
)
1620 i
= INTVAL (operands
[1]);
1621 switch (const_method (operands
[1]))
1624 return "mvsw %1,%0";
1626 return "mvzw %1,%0";
1628 return "moveq %1,%0";
1631 operands
[1] = GEN_INT (i
^ 0xff);
1632 return "moveq %1,%0\n\tnot%.b %0";
1635 operands
[1] = GEN_INT (i
^ 0xffff);
1636 return "moveq %1,%0\n\tnot%.w %0";
1639 return "moveq #-128,%0\n\tneg%.w %0";
1644 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1645 return "moveq %1,%0\n\tswap %0";
1648 return "move%.l %1,%0";
1655 output_move_simode_const (rtx
*operands
)
1657 if (operands
[1] == const0_rtx
1658 && (DATA_REG_P (operands
[0])
1659 || GET_CODE (operands
[0]) == MEM
)
1660 /* clr insns on 68000 read before writing.
1661 This isn't so on the 68010, but we have no TARGET_68010. */
1662 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1663 || !(GET_CODE (operands
[0]) == MEM
1664 && MEM_VOLATILE_P (operands
[0]))))
1666 else if (operands
[1] == const0_rtx
1667 && ADDRESS_REG_P (operands
[0]))
1668 return "sub%.l %0,%0";
1669 else if (DATA_REG_P (operands
[0]))
1670 return output_move_const_into_data_reg (operands
);
1671 else if (ADDRESS_REG_P (operands
[0])
1672 && INTVAL (operands
[1]) < 0x8000
1673 && INTVAL (operands
[1]) >= -0x8000)
1674 return "move%.w %1,%0";
1675 else if (GET_CODE (operands
[0]) == MEM
1676 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1677 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1678 && INTVAL (operands
[1]) < 0x8000
1679 && INTVAL (operands
[1]) >= -0x8000)
1681 return "move%.l %1,%0";
1685 output_move_simode (rtx
*operands
)
1687 if (GET_CODE (operands
[1]) == CONST_INT
)
1688 return output_move_simode_const (operands
);
1689 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1690 || GET_CODE (operands
[1]) == CONST
)
1691 && push_operand (operands
[0], SImode
))
1693 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1694 || GET_CODE (operands
[1]) == CONST
)
1695 && ADDRESS_REG_P (operands
[0]))
1696 return "lea %a1,%0";
1697 return "move%.l %1,%0";
1701 output_move_himode (rtx
*operands
)
1703 if (GET_CODE (operands
[1]) == CONST_INT
)
1705 if (operands
[1] == const0_rtx
1706 && (DATA_REG_P (operands
[0])
1707 || GET_CODE (operands
[0]) == MEM
)
1708 /* clr insns on 68000 read before writing.
1709 This isn't so on the 68010, but we have no TARGET_68010. */
1710 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1711 || !(GET_CODE (operands
[0]) == MEM
1712 && MEM_VOLATILE_P (operands
[0]))))
1714 else if (operands
[1] == const0_rtx
1715 && ADDRESS_REG_P (operands
[0]))
1716 return "sub%.l %0,%0";
1717 else if (DATA_REG_P (operands
[0])
1718 && INTVAL (operands
[1]) < 128
1719 && INTVAL (operands
[1]) >= -128)
1721 return "moveq %1,%0";
1723 else if (INTVAL (operands
[1]) < 0x8000
1724 && INTVAL (operands
[1]) >= -0x8000)
1725 return "move%.w %1,%0";
1727 else if (CONSTANT_P (operands
[1]))
1728 return "move%.l %1,%0";
1729 /* Recognize the insn before a tablejump, one that refers
1730 to a table of offsets. Such an insn will need to refer
1731 to a label on the insn. So output one. Use the label-number
1732 of the table of offsets to generate this label. This code,
1733 and similar code below, assumes that there will be at most one
1734 reference to each table. */
1735 if (GET_CODE (operands
[1]) == MEM
1736 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1737 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1738 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1740 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1742 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1743 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1746 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1748 return "move%.w %1,%0";
1752 output_move_qimode (rtx
*operands
)
1756 /* This is probably useless, since it loses for pushing a struct
1757 of several bytes a byte at a time. */
1758 /* 68k family always modifies the stack pointer by at least 2, even for
1759 byte pushes. The 5200 (ColdFire) does not do this. */
1760 if (GET_CODE (operands
[0]) == MEM
1761 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1762 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1763 && ! ADDRESS_REG_P (operands
[1])
1764 && ! TARGET_COLDFIRE
)
1766 xoperands
[1] = operands
[1];
1768 = gen_rtx_MEM (QImode
,
1769 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1770 /* Just pushing a byte puts it in the high byte of the halfword. */
1771 /* We must put it in the low-order, high-numbered byte. */
1772 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1774 xoperands
[3] = stack_pointer_rtx
;
1775 output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands
);
1778 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1782 /* clr and st insns on 68000 read before writing.
1783 This isn't so on the 68010, but we have no TARGET_68010. */
1784 if (!ADDRESS_REG_P (operands
[0])
1785 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1786 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1788 if (operands
[1] == const0_rtx
)
1790 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1791 && GET_CODE (operands
[1]) == CONST_INT
1792 && (INTVAL (operands
[1]) & 255) == 255)
1798 if (GET_CODE (operands
[1]) == CONST_INT
1799 && DATA_REG_P (operands
[0])
1800 && INTVAL (operands
[1]) < 128
1801 && INTVAL (operands
[1]) >= -128)
1803 return "moveq %1,%0";
1805 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1806 return "sub%.l %0,%0";
1807 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1808 return "move%.l %1,%0";
1809 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1810 from address registers. */
1811 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1812 return "move%.w %1,%0";
1813 return "move%.b %1,%0";
1817 output_move_stricthi (rtx
*operands
)
1819 if (operands
[1] == const0_rtx
1820 /* clr insns on 68000 read before writing.
1821 This isn't so on the 68010, but we have no TARGET_68010. */
1822 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1823 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1825 return "move%.w %1,%0";
1829 output_move_strictqi (rtx
*operands
)
1831 if (operands
[1] == const0_rtx
1832 /* clr insns on 68000 read before writing.
1833 This isn't so on the 68010, but we have no TARGET_68010. */
1834 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1835 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1837 return "move%.b %1,%0";
1840 /* Return the best assembler insn template
1841 for moving operands[1] into operands[0] as a fullword. */
1844 singlemove_string (rtx
*operands
)
1846 if (GET_CODE (operands
[1]) == CONST_INT
)
1847 return output_move_simode_const (operands
);
1848 return "move%.l %1,%0";
1852 /* Output assembler code to perform a doubleword move insn
1853 with operands OPERANDS. */
1856 output_move_double (rtx
*operands
)
1860 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1865 rtx addreg0
= 0, addreg1
= 0;
1866 int dest_overlapped_low
= 0;
1867 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1872 /* First classify both operands. */
1874 if (REG_P (operands
[0]))
1876 else if (offsettable_memref_p (operands
[0]))
1878 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1880 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1882 else if (GET_CODE (operands
[0]) == MEM
)
1887 if (REG_P (operands
[1]))
1889 else if (CONSTANT_P (operands
[1]))
1891 else if (offsettable_memref_p (operands
[1]))
1893 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1895 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1897 else if (GET_CODE (operands
[1]) == MEM
)
1902 /* Check for the cases that the operand constraints are not
1903 supposed to allow to happen. Abort if we get one,
1904 because generating code for these cases is painful. */
1906 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1909 /* If one operand is decrementing and one is incrementing
1910 decrement the former register explicitly
1911 and change that operand into ordinary indexing. */
1913 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1915 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1917 output_asm_insn ("sub%.l #12,%0", operands
);
1919 output_asm_insn ("subq%.l #8,%0", operands
);
1920 if (GET_MODE (operands
[1]) == XFmode
)
1921 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1922 else if (GET_MODE (operands
[0]) == DFmode
)
1923 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1925 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1928 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1930 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1932 output_asm_insn ("sub%.l #12,%1", operands
);
1934 output_asm_insn ("subq%.l #8,%1", operands
);
1935 if (GET_MODE (operands
[1]) == XFmode
)
1936 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1937 else if (GET_MODE (operands
[1]) == DFmode
)
1938 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1940 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1944 /* If an operand is an unoffsettable memory ref, find a register
1945 we can increment temporarily to make it refer to the second word. */
1947 if (optype0
== MEMOP
)
1948 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1950 if (optype1
== MEMOP
)
1951 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1953 /* Ok, we can do one word at a time.
1954 Normally we do the low-numbered word first,
1955 but if either operand is autodecrementing then we
1956 do the high-numbered word first.
1958 In either case, set up in LATEHALF the operands to use
1959 for the high-numbered word and in some cases alter the
1960 operands in OPERANDS to be suitable for the low-numbered word. */
1964 if (optype0
== REGOP
)
1966 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1967 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1969 else if (optype0
== OFFSOP
)
1971 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
1972 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
1976 middlehalf
[0] = operands
[0];
1977 latehalf
[0] = operands
[0];
1980 if (optype1
== REGOP
)
1982 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1983 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1985 else if (optype1
== OFFSOP
)
1987 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
1988 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
1990 else if (optype1
== CNSTOP
)
1992 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1997 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1998 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1999 operands
[1] = GEN_INT (l
[0]);
2000 middlehalf
[1] = GEN_INT (l
[1]);
2001 latehalf
[1] = GEN_INT (l
[2]);
2003 else if (CONSTANT_P (operands
[1]))
2005 /* actually, no non-CONST_DOUBLE constant should ever
2008 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2009 latehalf
[1] = constm1_rtx
;
2011 latehalf
[1] = const0_rtx
;
2016 middlehalf
[1] = operands
[1];
2017 latehalf
[1] = operands
[1];
2021 /* size is not 12: */
2023 if (optype0
== REGOP
)
2024 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2025 else if (optype0
== OFFSOP
)
2026 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2028 latehalf
[0] = operands
[0];
2030 if (optype1
== REGOP
)
2031 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2032 else if (optype1
== OFFSOP
)
2033 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2034 else if (optype1
== CNSTOP
)
2035 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2037 latehalf
[1] = operands
[1];
2040 /* If insn is effectively movd N(sp),-(sp) then we will do the
2041 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2042 for the low word as well, to compensate for the first decrement of sp. */
2043 if (optype0
== PUSHOP
2044 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2045 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2046 operands
[1] = middlehalf
[1] = latehalf
[1];
2048 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2049 if the upper part of reg N does not appear in the MEM, arrange to
2050 emit the move late-half first. Otherwise, compute the MEM address
2051 into the upper part of N and use that as a pointer to the memory
2053 if (optype0
== REGOP
2054 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2056 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2058 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2059 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2061 /* If both halves of dest are used in the src memory address,
2062 compute the address into latehalf of dest.
2063 Note that this can't happen if the dest is two data regs. */
2065 xops
[0] = latehalf
[0];
2066 xops
[1] = XEXP (operands
[1], 0);
2067 output_asm_insn ("lea %a1,%0", xops
);
2068 if (GET_MODE (operands
[1]) == XFmode
)
2070 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2071 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2072 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2076 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2077 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2081 && reg_overlap_mentioned_p (middlehalf
[0],
2082 XEXP (operands
[1], 0)))
2084 /* Check for two regs used by both source and dest.
2085 Note that this can't happen if the dest is all data regs.
2086 It can happen if the dest is d6, d7, a0.
2087 But in that case, latehalf is an addr reg, so
2088 the code at compadr does ok. */
2090 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2091 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2094 /* JRV says this can't happen: */
2095 if (addreg0
|| addreg1
)
2098 /* Only the middle reg conflicts; simply put it last. */
2099 output_asm_insn (singlemove_string (operands
), operands
);
2100 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2101 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2104 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2105 /* If the low half of dest is mentioned in the source memory
2106 address, the arrange to emit the move late half first. */
2107 dest_overlapped_low
= 1;
2110 /* If one or both operands autodecrementing,
2111 do the two words, high-numbered first. */
2113 /* Likewise, the first move would clobber the source of the second one,
2114 do them in the other order. This happens only for registers;
2115 such overlap can't happen in memory unless the user explicitly
2116 sets it up, and that is an undefined circumstance. */
2118 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2119 || (optype0
== REGOP
&& optype1
== REGOP
2120 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2121 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2122 || dest_overlapped_low
)
2124 /* Make any unoffsettable addresses point at high-numbered word. */
2128 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2130 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2135 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2137 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2141 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2143 /* Undo the adds we just did. */
2145 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2147 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2151 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2153 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2155 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2158 /* Do low-numbered word. */
2159 return singlemove_string (operands
);
2162 /* Normal case: do the two words, low-numbered first. */
2164 output_asm_insn (singlemove_string (operands
), operands
);
2166 /* Do the middle one of the three words for long double */
2170 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2172 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2174 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2177 /* Make any unoffsettable addresses point at high-numbered word. */
2179 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2181 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2184 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2186 /* Undo the adds we just did. */
2190 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2192 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2197 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2199 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2205 /* Return a REG that occurs in ADDR with coefficient 1.
2206 ADDR can be effectively incremented by incrementing REG. */
2209 find_addr_reg (rtx addr
)
2211 while (GET_CODE (addr
) == PLUS
)
2213 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2214 addr
= XEXP (addr
, 0);
2215 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2216 addr
= XEXP (addr
, 1);
2217 else if (CONSTANT_P (XEXP (addr
, 0)))
2218 addr
= XEXP (addr
, 1);
2219 else if (CONSTANT_P (XEXP (addr
, 1)))
2220 addr
= XEXP (addr
, 0);
2224 if (GET_CODE (addr
) == REG
)
2229 /* Output assembler code to perform a 32-bit 3-operand add. */
2232 output_addsi3 (rtx
*operands
)
2234 if (! operands_match_p (operands
[0], operands
[1]))
2236 if (!ADDRESS_REG_P (operands
[1]))
2238 rtx tmp
= operands
[1];
2240 operands
[1] = operands
[2];
2244 /* These insns can result from reloads to access
2245 stack slots over 64k from the frame pointer. */
2246 if (GET_CODE (operands
[2]) == CONST_INT
2247 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2248 return "move%.l %2,%0\n\tadd%.l %1,%0";
2249 if (GET_CODE (operands
[2]) == REG
)
2250 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2251 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2253 if (GET_CODE (operands
[2]) == CONST_INT
)
2255 if (INTVAL (operands
[2]) > 0
2256 && INTVAL (operands
[2]) <= 8)
2257 return "addq%.l %2,%0";
2258 if (INTVAL (operands
[2]) < 0
2259 && INTVAL (operands
[2]) >= -8)
2261 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2262 return "subq%.l %2,%0";
2264 /* On the CPU32 it is faster to use two addql instructions to
2265 add a small integer (8 < N <= 16) to a register.
2266 Likewise for subql. */
2267 if (TARGET_CPU32
&& REG_P (operands
[0]))
2269 if (INTVAL (operands
[2]) > 8
2270 && INTVAL (operands
[2]) <= 16)
2272 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2273 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2275 if (INTVAL (operands
[2]) < -8
2276 && INTVAL (operands
[2]) >= -16)
2278 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2279 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2282 if (ADDRESS_REG_P (operands
[0])
2283 && INTVAL (operands
[2]) >= -0x8000
2284 && INTVAL (operands
[2]) < 0x8000)
2287 return "add%.w %2,%0";
2289 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2292 return "add%.l %2,%0";
2295 /* Store in cc_status the expressions that the condition codes will
2296 describe after execution of an instruction whose pattern is EXP.
2297 Do not alter them if the instruction would not alter the cc's. */
2299 /* On the 68000, all the insns to store in an address register fail to
2300 set the cc's. However, in some cases these instructions can make it
2301 possibly invalid to use the saved cc's. In those cases we clear out
2302 some or all of the saved cc's so they won't be used. */
2305 notice_update_cc (rtx exp
, rtx insn
)
2307 if (GET_CODE (exp
) == SET
)
2309 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2313 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2315 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2316 cc_status
.value1
= 0;
2317 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2318 cc_status
.value2
= 0;
2320 else if (!FP_REG_P (SET_DEST (exp
))
2321 && SET_DEST (exp
) != cc0_rtx
2322 && (FP_REG_P (SET_SRC (exp
))
2323 || GET_CODE (SET_SRC (exp
)) == FIX
2324 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2325 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2329 /* A pair of move insns doesn't produce a useful overall cc. */
2330 else if (!FP_REG_P (SET_DEST (exp
))
2331 && !FP_REG_P (SET_SRC (exp
))
2332 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2333 && (GET_CODE (SET_SRC (exp
)) == REG
2334 || GET_CODE (SET_SRC (exp
)) == MEM
2335 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2339 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2343 else if (XEXP (exp
, 0) != pc_rtx
)
2345 cc_status
.flags
= 0;
2346 cc_status
.value1
= XEXP (exp
, 0);
2347 cc_status
.value2
= XEXP (exp
, 1);
2350 else if (GET_CODE (exp
) == PARALLEL
2351 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2353 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2355 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2357 cc_status
.flags
= 0;
2358 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2359 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2364 if (cc_status
.value2
!= 0
2365 && ADDRESS_REG_P (cc_status
.value2
)
2366 && GET_MODE (cc_status
.value2
) == QImode
)
2368 if (cc_status
.value2
!= 0)
2369 switch (GET_CODE (cc_status
.value2
))
2371 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2372 case ROTATE
: case ROTATERT
:
2373 /* These instructions always clear the overflow bit, and set
2374 the carry to the bit shifted out. */
2375 /* ??? We don't currently have a way to signal carry not valid,
2376 nor do we check for it in the branch insns. */
2380 case PLUS
: case MINUS
: case MULT
:
2381 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2382 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2383 cc_status
.flags
|= CC_NO_OVERFLOW
;
2386 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2387 ends with a move insn moving r2 in r2's mode.
2388 Thus, the cc's are set for r2.
2389 This can set N bit spuriously. */
2390 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2395 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2397 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2398 cc_status
.value2
= 0;
2399 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2400 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2401 cc_status
.flags
= CC_IN_68881
;
2405 output_move_const_double (rtx
*operands
)
2407 int code
= standard_68881_constant_p (operands
[1]);
2411 static char buf
[40];
2413 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2416 return "fmove%.d %1,%0";
2420 output_move_const_single (rtx
*operands
)
2422 int code
= standard_68881_constant_p (operands
[1]);
2426 static char buf
[40];
2428 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2431 return "fmove%.s %f1,%0";
2434 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2435 from the "fmovecr" instruction.
2436 The value, anded with 0xff, gives the code to use in fmovecr
2437 to get the desired constant. */
2439 /* This code has been fixed for cross-compilation. */
2441 static int inited_68881_table
= 0;
2443 static const char *const strings_68881
[7] = {
2453 static const int codes_68881
[7] = {
2463 REAL_VALUE_TYPE values_68881
[7];
2465 /* Set up values_68881 array by converting the decimal values
2466 strings_68881 to binary. */
2469 init_68881_table (void)
2473 enum machine_mode mode
;
2476 for (i
= 0; i
< 7; i
++)
2480 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2481 values_68881
[i
] = r
;
2483 inited_68881_table
= 1;
2487 standard_68881_constant_p (rtx x
)
2492 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2493 used at all on those chips. */
2494 if (TARGET_68040
|| TARGET_68060
)
2497 if (! inited_68881_table
)
2498 init_68881_table ();
2500 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2502 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2504 for (i
= 0; i
< 6; i
++)
2506 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2507 return (codes_68881
[i
]);
2510 if (GET_MODE (x
) == SFmode
)
2513 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2514 return (codes_68881
[6]);
2516 /* larger powers of ten in the constants ram are not used
2517 because they are not equal to a `double' C constant. */
2521 /* If X is a floating-point constant, return the logarithm of X base 2,
2522 or 0 if X is not a power of 2. */
2525 floating_exact_log2 (rtx x
)
2527 REAL_VALUE_TYPE r
, r1
;
2530 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2532 if (REAL_VALUES_LESS (r
, dconst1
))
2535 exp
= real_exponent (&r
);
2536 real_2expN (&r1
, exp
);
2537 if (REAL_VALUES_EQUAL (r1
, r
))
2543 /* A C compound statement to output to stdio stream STREAM the
2544 assembler syntax for an instruction operand X. X is an RTL
2547 CODE is a value that can be used to specify one of several ways
2548 of printing the operand. It is used when identical operands
2549 must be printed differently depending on the context. CODE
2550 comes from the `%' specification that was used to request
2551 printing of the operand. If the specification was just `%DIGIT'
2552 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2553 is the ASCII code for LTR.
2555 If X is a register, this macro should print the register's name.
2556 The names can be found in an array `reg_names' whose type is
2557 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2559 When the machine description has a specification `%PUNCT' (a `%'
2560 followed by a punctuation character), this macro is called with
2561 a null pointer for X and the punctuation character for CODE.
2563 The m68k specific codes are:
2565 '.' for dot needed in Motorola-style opcode names.
2566 '-' for an operand pushing on the stack:
2567 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2568 '+' for an operand pushing on the stack:
2569 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2570 '@' for a reference to the top word on the stack:
2571 sp@, (sp) or (%sp) depending on the style of syntax.
2572 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2573 but & in SGS syntax).
2574 '!' for the cc register (used in an `and to cc' insn).
2575 '$' for the letter `s' in an op code, but only on the 68040.
2576 '&' for the letter `d' in an op code, but only on the 68040.
2577 '/' for register prefix needed by longlong.h.
2579 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2580 'd' to force memory addressing to be absolute, not relative.
2581 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2582 'o' for operands to go directly to output_operand_address (bypassing
2583 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2584 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2585 or print pair of registers as rx:ry.
2590 print_operand (FILE *file
, rtx op
, int letter
)
2595 fprintf (file
, ".");
2597 else if (letter
== '#')
2598 asm_fprintf (file
, "%I");
2599 else if (letter
== '-')
2600 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2601 else if (letter
== '+')
2602 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2603 else if (letter
== '@')
2604 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2605 else if (letter
== '!')
2606 asm_fprintf (file
, "%Rfpcr");
2607 else if (letter
== '$')
2609 if (TARGET_68040_ONLY
)
2610 fprintf (file
, "s");
2612 else if (letter
== '&')
2614 if (TARGET_68040_ONLY
)
2615 fprintf (file
, "d");
2617 else if (letter
== '/')
2618 asm_fprintf (file
, "%R");
2619 else if (letter
== 'o')
2621 /* This is only for direct addresses with TARGET_PCREL */
2622 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2625 output_addr_const (file
, XEXP (op
, 0));
2627 else if (GET_CODE (op
) == REG
)
2630 /* Print out the second register name of a register pair.
2631 I.e., R (6) => 7. */
2632 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2634 fputs (M68K_REGNAME(REGNO (op
)), file
);
2636 else if (GET_CODE (op
) == MEM
)
2638 output_address (XEXP (op
, 0));
2639 if (letter
== 'd' && ! TARGET_68020
2640 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2641 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2642 && INTVAL (XEXP (op
, 0)) < 0x8000
2643 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2644 fprintf (file
, MOTOROLA
? ".l" : ":l");
2646 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2649 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2650 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2652 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2655 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2656 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2658 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2661 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2662 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2666 /* Use `print_operand_address' instead of `output_addr_const'
2667 to ensure that we print relevant PIC stuff. */
2668 asm_fprintf (file
, "%I");
2670 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2671 print_operand_address (file
, op
);
2673 output_addr_const (file
, op
);
2678 /* A C compound statement to output to stdio stream STREAM the
2679 assembler syntax for an instruction operand that is a memory
2680 reference whose address is ADDR. ADDR is an RTL expression.
2682 Note that this contains a kludge that knows that the only reason
2683 we have an address (plus (label_ref...) (reg...)) when not generating
2684 PIC code is in the insn before a tablejump, and we know that m68k.md
2685 generates a label LInnn: on such an insn.
2687 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2688 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2690 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2691 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2692 we want. This difference can be accommodated by using an assembler
2693 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2694 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2695 macro. See m68k/sgs.h for an example; for versions without the bug.
2696 Some assemblers refuse all the above solutions. The workaround is to
2697 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2700 They also do not like things like "pea 1.w", so we simple leave off
2701 the .w on small constants.
2703 This routine is responsible for distinguishing between -fpic and -fPIC
2704 style relocations in an address. When generating -fpic code the
2705 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2706 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2709 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2710 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2711 #else /* !MOTOROLA */
2712 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2713 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2714 #endif /* !MOTOROLA */
2717 print_operand_address (FILE *file
, rtx addr
)
2719 register rtx reg1
, reg2
, breg
, ireg
;
2722 switch (GET_CODE (addr
))
2725 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2728 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2729 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2732 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2733 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2736 reg1
= reg2
= ireg
= breg
= offset
= 0;
2737 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2739 offset
= XEXP (addr
, 0);
2740 addr
= XEXP (addr
, 1);
2742 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2744 offset
= XEXP (addr
, 1);
2745 addr
= XEXP (addr
, 0);
2747 if (GET_CODE (addr
) != PLUS
)
2751 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2753 reg1
= XEXP (addr
, 0);
2754 addr
= XEXP (addr
, 1);
2756 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2758 reg1
= XEXP (addr
, 1);
2759 addr
= XEXP (addr
, 0);
2761 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2763 reg1
= XEXP (addr
, 0);
2764 addr
= XEXP (addr
, 1);
2766 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2768 reg1
= XEXP (addr
, 1);
2769 addr
= XEXP (addr
, 0);
2771 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2773 reg1
= XEXP (addr
, 0);
2774 addr
= XEXP (addr
, 1);
2776 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2778 reg1
= XEXP (addr
, 1);
2779 addr
= XEXP (addr
, 0);
2781 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2782 || GET_CODE (addr
) == SIGN_EXTEND
)
2794 #if 0 /* for OLD_INDEXING */
2795 else if (GET_CODE (addr
) == PLUS
)
2797 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2799 reg2
= XEXP (addr
, 0);
2800 addr
= XEXP (addr
, 1);
2802 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2804 reg2
= XEXP (addr
, 1);
2805 addr
= XEXP (addr
, 0);
2817 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2818 || GET_CODE (reg1
) == MULT
))
2819 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2824 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2829 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2830 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2833 if (GET_CODE (ireg
) == MULT
)
2835 scale
= INTVAL (XEXP (ireg
, 1));
2836 ireg
= XEXP (ireg
, 0);
2838 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2840 ASM_OUTPUT_CASE_FETCH (file
,
2841 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2842 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2843 fprintf (file
, "w");
2847 ASM_OUTPUT_CASE_FETCH (file
,
2848 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2849 M68K_REGNAME(REGNO (ireg
)));
2850 fprintf (file
, "l");
2853 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2857 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2858 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2860 ASM_OUTPUT_CASE_FETCH (file
,
2861 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2862 M68K_REGNAME(REGNO (breg
)));
2863 fprintf (file
, "l)");
2866 if (ireg
!= 0 || breg
!= 0)
2873 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2881 output_addr_const (file
, addr
);
2882 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2884 fprintf (file
, "@GOT");
2886 fprintf (file
, ".w");
2889 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2893 else /* !MOTOROLA */
2895 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2898 output_addr_const (file
, addr
);
2899 if (breg
== pic_offset_table_rtx
)
2903 fprintf (file
, ":w"); break;
2905 fprintf (file
, ":l"); break;
2913 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2915 scale
= INTVAL (XEXP (ireg
, 1));
2916 ireg
= XEXP (ireg
, 0);
2918 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2919 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2920 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2922 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2923 M68K_REGNAME(REGNO (ireg
)));
2925 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2929 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2930 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2932 ASM_OUTPUT_CASE_FETCH (file
,
2933 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2934 M68K_REGNAME(REGNO (reg1
)));
2935 fprintf (file
, "l)");
2938 /* FALL-THROUGH (is this really what we want?) */
2940 if (GET_CODE (addr
) == CONST_INT
2941 && INTVAL (addr
) < 0x8000
2942 && INTVAL (addr
) >= -0x8000)
2944 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2946 else if (GET_CODE (addr
) == CONST_INT
)
2948 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2950 else if (TARGET_PCREL
)
2953 output_addr_const (file
, addr
);
2955 asm_fprintf (file
, ":w,%Rpc)");
2957 asm_fprintf (file
, ":l,%Rpc)");
2961 /* Special case for SYMBOL_REF if the symbol name ends in
2962 `.<letter>', this can be mistaken as a size suffix. Put
2963 the name in parentheses. */
2964 if (GET_CODE (addr
) == SYMBOL_REF
2965 && strlen (XSTR (addr
, 0)) > 2
2966 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
2969 output_addr_const (file
, addr
);
2973 output_addr_const (file
, addr
);
2979 /* Check for cases where a clr insns can be omitted from code using
2980 strict_low_part sets. For example, the second clrl here is not needed:
2981 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2983 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2984 insn we are checking for redundancy. TARGET is the register set by the
2988 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
2993 p
= prev_nonnote_insn (first_insn
);
2997 /* If it isn't an insn, then give up. */
2998 if (GET_CODE (p
) != INSN
)
3001 if (reg_set_p (target
, p
))
3003 rtx set
= single_set (p
);
3006 /* If it isn't an easy to recognize insn, then give up. */
3010 dest
= SET_DEST (set
);
3012 /* If this sets the entire target register to zero, then our
3013 first_insn is redundant. */
3014 if (rtx_equal_p (dest
, target
)
3015 && SET_SRC (set
) == const0_rtx
)
3017 else if (GET_CODE (dest
) == STRICT_LOW_PART
3018 && GET_CODE (XEXP (dest
, 0)) == REG
3019 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3020 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3021 <= GET_MODE_SIZE (mode
)))
3022 /* This is a strict low part set which modifies less than
3023 we are using, so it is safe. */
3029 p
= prev_nonnote_insn (p
);
3035 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3036 range carefully since this predicate is used in DImode contexts. Also, we
3037 need some extra crud to make it work when hosted on 64-bit machines. */
3040 const_uint32_operand (rtx op
, enum machine_mode mode
)
3042 /* It doesn't make sense to ask this question with a mode that is
3043 not larger than 32 bits. */
3044 if (GET_MODE_BITSIZE (mode
) <= 32)
3047 #if HOST_BITS_PER_WIDE_INT > 32
3048 /* All allowed constants will fit a CONST_INT. */
3049 return (GET_CODE (op
) == CONST_INT
3050 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3052 return (GET_CODE (op
) == CONST_INT
3053 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3057 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3058 to check the range carefully since this predicate is used in DImode
3062 const_sint32_operand (rtx op
, enum machine_mode mode
)
3064 /* It doesn't make sense to ask this question with a mode that is
3065 not larger than 32 bits. */
3066 if (GET_MODE_BITSIZE (mode
) <= 32)
3069 /* All allowed constants will fit a CONST_INT. */
3070 return (GET_CODE (op
) == CONST_INT
3071 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3074 /* Operand predicates for implementing asymmetric pc-relative addressing
3075 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3076 when used as a source operand, but not as a destination operand.
3078 We model this by restricting the meaning of the basic predicates
3079 (general_operand, memory_operand, etc) to forbid the use of this
3080 addressing mode, and then define the following predicates that permit
3081 this addressing mode. These predicates can then be used for the
3082 source operands of the appropriate instructions.
3084 n.b. While it is theoretically possible to change all machine patterns
3085 to use this addressing more where permitted by the architecture,
3086 it has only been implemented for "common" cases: SImode, HImode, and
3087 QImode operands, and only for the principle operations that would
3088 require this addressing mode: data movement and simple integer operations.
3090 In parallel with these new predicates, two new constraint letters
3091 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3092 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3093 In the pcrel case 's' is only valid in combination with 'a' registers.
3094 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3095 of how these constraints are used.
3097 The use of these predicates is strictly optional, though patterns that
3098 don't will cause an extra reload register to be allocated where one
3101 lea (abc:w,%pc),%a0 ; need to reload address
3102 moveq &1,%d1 ; since write to pc-relative space
3103 movel %d1,%a0@ ; is not allowed
3105 lea (abc:w,%pc),%a1 ; no need to reload address here
3106 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3108 For more info, consult tiemann@cygnus.com.
3111 All of the ugliness with predicates and constraints is due to the
3112 simple fact that the m68k does not allow a pc-relative addressing
3113 mode as a destination. gcc does not distinguish between source and
3114 destination addresses. Hence, if we claim that pc-relative address
3115 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3116 end up with invalid code. To get around this problem, we left
3117 pc-relative modes as invalid addresses, and then added special
3118 predicates and constraints to accept them.
3120 A cleaner way to handle this is to modify gcc to distinguish
3121 between source and destination addresses. We can then say that
3122 pc-relative is a valid source address but not a valid destination
3123 address, and hopefully avoid a lot of the predicate and constraint
3124 hackery. Unfortunately, this would be a pretty big change. It would
3125 be a useful change for a number of ports, but there aren't any current
3126 plans to undertake this.
3128 ***************************************************************************/
3131 /* Special case of a general operand that's used as a source operand.
3132 Use this to permit reads from PC-relative memory when -mpcrel
3136 general_src_operand (rtx op
, enum machine_mode mode
)
3139 && GET_CODE (op
) == MEM
3140 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3141 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3142 || GET_CODE (XEXP (op
, 0)) == CONST
))
3144 return general_operand (op
, mode
);
3147 /* Special case of a nonimmediate operand that's used as a source.
3148 Use this to permit reads from PC-relative memory when -mpcrel
3152 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3154 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3155 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3156 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3157 || GET_CODE (XEXP (op
, 0)) == CONST
))
3159 return nonimmediate_operand (op
, mode
);
3162 /* Special case of a memory operand that's used as a source.
3163 Use this to permit reads from PC-relative memory when -mpcrel
3167 memory_src_operand (rtx op
, enum machine_mode mode
)
3169 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3170 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3171 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3172 || GET_CODE (XEXP (op
, 0)) == CONST
))
3174 return memory_operand (op
, mode
);
3177 /* Predicate that accepts only a pc-relative address. This is needed
3178 because pc-relative addresses don't satisfy the predicate
3179 "general_src_operand". */
3182 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3184 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3185 || GET_CODE (op
) == CONST
);
3189 output_andsi3 (rtx
*operands
)
3192 if (GET_CODE (operands
[2]) == CONST_INT
3193 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3194 && (DATA_REG_P (operands
[0])
3195 || offsettable_memref_p (operands
[0]))
3196 && !TARGET_COLDFIRE
)
3198 if (GET_CODE (operands
[0]) != REG
)
3199 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3200 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3201 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3203 if (operands
[2] == const0_rtx
)
3205 return "and%.w %2,%0";
3207 if (GET_CODE (operands
[2]) == CONST_INT
3208 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3209 && (DATA_REG_P (operands
[0])
3210 || offsettable_memref_p (operands
[0])))
3212 if (DATA_REG_P (operands
[0]))
3214 operands
[1] = GEN_INT (logval
);
3218 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3219 operands
[1] = GEN_INT (logval
% 8);
3221 /* This does not set condition codes in a standard way. */
3223 return "bclr %1,%0";
3225 return "and%.l %2,%0";
3229 output_iorsi3 (rtx
*operands
)
3231 register int logval
;
3232 if (GET_CODE (operands
[2]) == CONST_INT
3233 && INTVAL (operands
[2]) >> 16 == 0
3234 && (DATA_REG_P (operands
[0])
3235 || offsettable_memref_p (operands
[0]))
3236 && !TARGET_COLDFIRE
)
3238 if (GET_CODE (operands
[0]) != REG
)
3239 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3240 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3242 if (INTVAL (operands
[2]) == 0xffff)
3243 return "mov%.w %2,%0";
3244 return "or%.w %2,%0";
3246 if (GET_CODE (operands
[2]) == CONST_INT
3247 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3248 && (DATA_REG_P (operands
[0])
3249 || offsettable_memref_p (operands
[0])))
3251 if (DATA_REG_P (operands
[0]))
3252 operands
[1] = GEN_INT (logval
);
3255 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3256 operands
[1] = GEN_INT (logval
% 8);
3259 return "bset %1,%0";
3261 return "or%.l %2,%0";
3265 output_xorsi3 (rtx
*operands
)
3267 register int logval
;
3268 if (GET_CODE (operands
[2]) == CONST_INT
3269 && INTVAL (operands
[2]) >> 16 == 0
3270 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3271 && !TARGET_COLDFIRE
)
3273 if (! DATA_REG_P (operands
[0]))
3274 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3275 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3277 if (INTVAL (operands
[2]) == 0xffff)
3279 return "eor%.w %2,%0";
3281 if (GET_CODE (operands
[2]) == CONST_INT
3282 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3283 && (DATA_REG_P (operands
[0])
3284 || offsettable_memref_p (operands
[0])))
3286 if (DATA_REG_P (operands
[0]))
3287 operands
[1] = GEN_INT (logval
);
3290 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3291 operands
[1] = GEN_INT (logval
% 8);
3294 return "bchg %1,%0";
3296 return "eor%.l %2,%0";
3299 #ifdef M68K_TARGET_COFF
3301 /* Output assembly to switch to section NAME with attribute FLAGS. */
3304 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3308 if (flags
& SECTION_WRITE
)
3313 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3316 #endif /* M68K_TARGET_COFF */
3319 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3320 HOST_WIDE_INT delta
,
3321 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3327 if (delta
> 0 && delta
<= 8)
3328 asm_fprintf (file
, MOTOROLA
?
3329 "\taddq.l %I%d,4(%Rsp)\n" :
3330 "\taddql %I%d,%Rsp@(4)\n",
3332 else if (delta
< 0 && delta
>= -8)
3333 asm_fprintf (file
, MOTOROLA
?
3334 "\tsubq.l %I%d,4(%Rsp)\n" :
3335 "\tsubql %I%d,%Rsp@(4)\n",
3337 else if (TARGET_COLDFIRE
)
3339 /* ColdFire can't add/sub a constant to memory unless it is in
3340 the range of addq/subq. So load the value into %d0 and
3341 then add it to 4(%sp). */
3342 if (delta
>= -128 && delta
<= 127)
3343 asm_fprintf (file
, MOTOROLA
?
3344 "\tmoveq.l %I%wd,%Rd0\n" :
3345 "\tmoveql %I%wd,%Rd0\n", delta
);
3347 asm_fprintf (file
, MOTOROLA
?
3348 "\tmove.l %I%wd,%Rd0\n" :
3349 "\tmovel %I%wd,%Rd0\n", delta
);
3350 asm_fprintf (file
, MOTOROLA
?
3351 "\tadd.l %Rd0,4(%Rsp)\n" :
3352 "\taddl %Rd0,%Rsp@(4)\n");
3355 asm_fprintf (file
, MOTOROLA
?
3356 "\tadd.l %I%wd,4(%Rsp)\n" :
3357 "\taddl %I%wd,%Rsp@(4)\n",
3360 xops
[0] = DECL_RTL (function
);
3362 /* Logic taken from call patterns in m68k.md. */
3367 else if ((flag_pic
== 1) || TARGET_68020
)
3370 #if defined(USE_GAS)
3371 fmt
= "bra.l %0@PLTPC";
3373 fmt
= "bra %0@PLTPC";
3375 else /* !MOTOROLA */
3382 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3383 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3385 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3389 #if MOTOROLA && !defined (USE_GAS)
3396 output_asm_insn (fmt
, xops
);
3399 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3402 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3403 int incoming ATTRIBUTE_UNUSED
)
3405 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);