1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* Structure describing stack frame layout. */
49 /* Stack pointer to frame pointer offset. */
52 /* Offset of FPU registers. */
53 HOST_WIDE_INT foffset
;
55 /* Frame size in bytes (rounded up). */
58 /* Data and address register. */
60 unsigned int reg_mask
;
61 unsigned int reg_rev_mask
;
65 unsigned int fpu_mask
;
66 unsigned int fpu_rev_mask
;
68 /* Offsets relative to ARG_POINTER. */
69 HOST_WIDE_INT frame_pointer_offset
;
70 HOST_WIDE_INT stack_pointer_offset
;
72 /* Function which the above information refers to. */
76 /* Current frame information calculated by m68k_compute_frame_layout(). */
77 static struct m68k_frame current_frame
;
79 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
80 if SGS_SWITCH_TABLE. */
81 int switch_table_difference_label_flag
;
83 static rtx
find_addr_reg (rtx
);
84 static const char *singlemove_string (rtx
*);
85 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
86 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
87 #ifdef M68K_TARGET_COFF
88 static void m68k_coff_asm_named_section (const char *, unsigned int);
89 #endif /* M68K_TARGET_COFF */
91 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
92 static void m68k_hp320_file_start (void);
94 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
96 static bool m68k_interrupt_function_p (tree func
);
97 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
100 static void m68k_compute_frame_layout (void);
101 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
102 static int const_int_cost (rtx
);
103 static bool m68k_rtx_costs (rtx
, int, int, int *);
106 /* Alignment to use for loops and jumps */
107 /* Specify power of two alignment used for loops. */
108 const char *m68k_align_loops_string
;
109 /* Specify power of two alignment used for non-loop jumps. */
110 const char *m68k_align_jumps_string
;
111 /* Specify power of two alignment used for functions. */
112 const char *m68k_align_funcs_string
;
113 /* Specify the identification number of the library being built */
114 const char *m68k_library_id_string
;
116 /* Specify power of two alignment used for loops. */
117 int m68k_align_loops
;
118 /* Specify power of two alignment used for non-loop jumps. */
119 int m68k_align_jumps
;
120 /* Specify power of two alignment used for functions. */
121 int m68k_align_funcs
;
123 /* Nonzero if the last compare/test insn had FP operands. The
124 sCC expanders peek at this to determine what to do for the
125 68060, which has no fsCC instructions. */
126 int m68k_last_compare_had_fp_operands
;
128 /* Initialize the GCC target structure. */
130 #if INT_OP_GROUP == INT_OP_DOT_WORD
131 #undef TARGET_ASM_ALIGNED_HI_OP
132 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
135 #if INT_OP_GROUP == INT_OP_NO_DOT
136 #undef TARGET_ASM_BYTE_OP
137 #define TARGET_ASM_BYTE_OP "\tbyte\t"
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
140 #undef TARGET_ASM_ALIGNED_SI_OP
141 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
144 #if INT_OP_GROUP == INT_OP_DC
145 #undef TARGET_ASM_BYTE_OP
146 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
147 #undef TARGET_ASM_ALIGNED_HI_OP
148 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
149 #undef TARGET_ASM_ALIGNED_SI_OP
150 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
153 #undef TARGET_ASM_UNALIGNED_HI_OP
154 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
155 #undef TARGET_ASM_UNALIGNED_SI_OP
156 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
158 #undef TARGET_ASM_FUNCTION_PROLOGUE
159 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
160 #undef TARGET_ASM_FUNCTION_EPILOGUE
161 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
163 #undef TARGET_ASM_INTERNAL_LABEL
164 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
167 #undef TARGET_ASM_OUTPUT_MI_THUNK
168 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
169 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
170 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
172 #undef TARGET_ASM_FILE_START_APP_OFF
173 #define TARGET_ASM_FILE_START_APP_OFF true
175 #undef TARGET_RTX_COSTS
176 #define TARGET_RTX_COSTS m68k_rtx_costs
178 #undef TARGET_ATTRIBUTE_TABLE
179 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
181 static const struct attribute_spec m68k_attribute_table
[] =
183 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
184 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
185 { NULL
, 0, 0, false, false, false, NULL
}
188 struct gcc_target targetm
= TARGET_INITIALIZER
;
190 /* Sometimes certain combinations of command options do not make
191 sense on a particular target machine. You can define a macro
192 `OVERRIDE_OPTIONS' to take account of this. This macro, if
193 defined, is executed once just after all the command options have
196 Don't use this macro to turn on various extra optimizations for
197 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
200 override_options (void)
207 /* Validate -malign-loops= value, or provide default */
208 m68k_align_loops
= def_align
;
209 if (m68k_align_loops_string
)
211 i
= atoi (m68k_align_loops_string
);
212 if (i
< 1 || i
> MAX_CODE_ALIGN
)
213 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
215 m68k_align_loops
= i
;
218 /* Library identification */
219 if (m68k_library_id_string
)
223 if (! TARGET_ID_SHARED_LIBRARY
)
224 error ("-mshared-library-id= specified without -mid-shared-library");
225 id
= atoi (m68k_library_id_string
);
226 if (id
< 0 || id
> MAX_LIBRARY_ID
)
227 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
229 /* From now on, m68k_library_id_string will contain the library offset. */
230 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
233 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
235 m68k_library_id_string
= "_current_shared_library_a5_offset_";
237 /* Sanity check to ensure that msep-data and mid-sahred-library are not
238 * both specified together. Doing so simply doesn't make sense.
240 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
241 error ("cannot specify both -msep-data and -mid-shared-library");
243 /* If we're generating code for a separate A5 relative data segment,
244 * we've got to enable -fPIC as well. This might be relaxable to
245 * -fpic but it hasn't been tested properly.
247 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
250 /* Validate -malign-jumps= value, or provide default */
251 m68k_align_jumps
= def_align
;
252 if (m68k_align_jumps_string
)
254 i
= atoi (m68k_align_jumps_string
);
255 if (i
< 1 || i
> MAX_CODE_ALIGN
)
256 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
258 m68k_align_jumps
= i
;
261 /* Validate -malign-functions= value, or provide default */
262 m68k_align_funcs
= def_align
;
263 if (m68k_align_funcs_string
)
265 i
= atoi (m68k_align_funcs_string
);
266 if (i
< 1 || i
> MAX_CODE_ALIGN
)
267 error ("-malign-functions=%d is not between 1 and %d",
270 m68k_align_funcs
= i
;
273 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
275 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
276 error("-fPIC is not currently supported on the 68000 or 68010\n");
278 /* ??? A historic way of turning on pic, or is this intended to
279 be an embedded thing that doesn't have the same name binding
280 significance that it does on hosted ELF systems? */
281 if (TARGET_PCREL
&& flag_pic
== 0)
284 /* Turn off function cse if we are doing PIC. We always want function call
285 to be done as `bsr foo@PLTPC', so it will force the assembler to create
286 the PLT entry for `foo'. Doing function cse will cause the address of
287 `foo' to be loaded into a register, which is exactly what we want to
288 avoid when we are doing PIC on svr4 m68k. */
290 flag_no_function_cse
= 1;
292 SUBTARGET_OVERRIDE_OPTIONS
;
295 /* Return nonzero if FUNC is an interrupt function as specified by the
296 "interrupt_handler" attribute. */
298 m68k_interrupt_function_p(tree func
)
302 if (TREE_CODE (func
) != FUNCTION_DECL
)
305 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
306 return (a
!= NULL_TREE
);
309 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
310 struct attribute_spec.handler. */
312 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
313 tree args ATTRIBUTE_UNUSED
,
314 int flags ATTRIBUTE_UNUSED
,
317 if (TREE_CODE (*node
) != FUNCTION_DECL
)
319 warning ("`%s' attribute only applies to functions",
320 IDENTIFIER_POINTER (name
));
321 *no_add_attrs
= true;
328 m68k_compute_frame_layout (void)
331 unsigned int mask
, rmask
;
332 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
334 /* Only compute the frame once per function.
335 Don't cache information until reload has been completed. */
336 if (current_frame
.funcdef_no
== current_function_funcdef_no
340 current_frame
.size
= (get_frame_size () + 3) & -4;
342 mask
= rmask
= saved
= 0;
343 for (regno
= 0; regno
< 16; regno
++)
344 if (m68k_save_reg (regno
, interrupt_handler
))
347 rmask
|= 1 << (15 - regno
);
350 current_frame
.offset
= saved
* 4;
351 current_frame
.reg_no
= saved
;
352 current_frame
.reg_mask
= mask
;
353 current_frame
.reg_rev_mask
= rmask
;
355 current_frame
.foffset
= 0;
356 mask
= rmask
= saved
= 0;
357 if (TARGET_68881
/* || TARGET_CFV4E */)
359 for (regno
= 16; regno
< 24; regno
++)
360 if (m68k_save_reg (regno
, interrupt_handler
))
362 mask
|= 1 << (regno
- 16);
363 rmask
|= 1 << (23 - regno
);
366 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
367 current_frame
.offset
+= current_frame
.foffset
;
369 current_frame
.fpu_no
= saved
;
370 current_frame
.fpu_mask
= mask
;
371 current_frame
.fpu_rev_mask
= rmask
;
373 /* Remember what function this frame refers to. */
374 current_frame
.funcdef_no
= current_function_funcdef_no
;
378 m68k_initial_elimination_offset (int from
, int to
)
380 /* FIXME: The correct offset to compute here would appear to be
381 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
382 but for some obscure reason, this must be 0 to get correct code. */
383 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
386 m68k_compute_frame_layout ();
388 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
389 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
390 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
391 return current_frame
.offset
+ current_frame
.size
;
396 /* Refer to the array `regs_ever_live' to determine which registers
397 to save; `regs_ever_live[I]' is nonzero if register number I
398 is ever used in the function. This function is responsible for
399 knowing which registers should not be saved even if used.
400 Return true if we need to save REGNO. */
403 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
405 if (flag_pic
&& current_function_uses_pic_offset_table
406 && regno
== PIC_OFFSET_TABLE_REGNUM
)
409 if (current_function_calls_eh_return
)
414 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
415 if (test
== INVALID_REGNUM
)
422 /* Fixed regs we never touch. */
423 if (fixed_regs
[regno
])
426 /* The frame pointer (if it is such) is handled specially. */
427 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
430 /* Interrupt handlers must also save call_used_regs
431 if they are live or when calling nested functions. */
432 if (interrupt_handler
)
434 if (regs_ever_live
[regno
])
437 if (!current_function_is_leaf
&& call_used_regs
[regno
])
441 /* Never need to save registers that aren't touched. */
442 if (!regs_ever_live
[regno
])
445 /* Otherwise save everything that isn't call-clobbered. */
446 return !call_used_regs
[regno
];
449 /* This function generates the assembly code for function entry.
450 STREAM is a stdio stream to output the code to.
451 SIZE is an int: how many units of temporary storage to allocate. */
454 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
456 HOST_WIDE_INT fsize_with_regs
;
457 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
459 m68k_compute_frame_layout();
461 /* If the stack limit is a symbol, we can check it here,
462 before actually allocating the space. */
463 if (current_function_limit_stack
464 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
466 #if defined (MOTOROLA)
467 asm_fprintf (stream
, "\tcmp.l %I%s+%wd,%Rsp\n\ttrapcs\n",
468 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
470 asm_fprintf (stream
, "\tcmpl %I%s+%wd,%Rsp\n\ttrapcs\n",
471 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
475 /* On ColdFire add register save into initial stack frame setup, if possible. */
476 fsize_with_regs
= current_frame
.size
;
477 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
478 fsize_with_regs
+= current_frame
.reg_no
* 4;
480 if (frame_pointer_needed
)
482 if (current_frame
.size
== 0 && TARGET_68040
)
484 /* on the 68040, pea + move is faster than link.w 0 */
486 fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
487 reg_names
[FRAME_POINTER_REGNUM
],
488 reg_names
[STACK_POINTER_REGNUM
],
489 reg_names
[FRAME_POINTER_REGNUM
]);
491 fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
492 reg_names
[FRAME_POINTER_REGNUM
],
493 reg_names
[STACK_POINTER_REGNUM
],
494 reg_names
[FRAME_POINTER_REGNUM
]);
497 else if (fsize_with_regs
< 0x8000)
500 asm_fprintf (stream
, "\tlink.w %s,%I%wd\n",
501 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
503 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
504 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
507 else if (TARGET_68020
)
510 asm_fprintf (stream
, "\tlink.l %s,%I%wd\n",
511 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
513 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
514 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
519 /* Adding negative number is faster on the 68040. */
521 asm_fprintf (stream
, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
522 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
524 asm_fprintf (stream
, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
525 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
528 if (dwarf2out_do_frame ())
531 l
= (char *) dwarf2out_cfi_label ();
533 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
534 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
535 cfa_offset
+= current_frame
.size
;
538 else if (fsize_with_regs
) /* !frame_pointer_needed */
540 if (fsize_with_regs
< 0x8000)
542 if (fsize_with_regs
<= 8)
544 if (!TARGET_COLDFIRE
)
547 asm_fprintf (stream
, "\tsubq.w %I%wd,%Rsp\n", fsize_with_regs
);
549 asm_fprintf (stream
, "\tsubqw %I%wd,%Rsp\n", fsize_with_regs
);
555 asm_fprintf (stream
, "\tsubq.l %I%wd,%Rsp\n", fsize_with_regs
);
557 asm_fprintf (stream
, "\tsubql %I%wd,%Rsp\n", fsize_with_regs
);
561 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
563 /* On the CPU32 it is faster to use two subqw instructions to
564 subtract a small integer (8 < N <= 16) to a register. */
567 "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
568 fsize_with_regs
- 8);
570 asm_fprintf (stream
, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
571 fsize_with_regs
- 8);
574 else if (TARGET_68040
)
576 /* Adding negative number is faster on the 68040. */
578 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", -fsize_with_regs
);
580 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", -fsize_with_regs
);
586 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", -fsize_with_regs
);
588 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", -fsize_with_regs
);
592 else /* fsize_with_regs >= 0x8000 */
595 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", -fsize_with_regs
);
597 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", -fsize_with_regs
);
600 if (dwarf2out_do_frame ())
602 cfa_offset
+= current_frame
.size
+ 4;
603 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
605 } /* !frame_pointer_needed */
607 if (current_frame
.fpu_mask
)
610 asm_fprintf (stream
, "\tfmovm %I0x%x,-(%Rsp)\n", current_frame
.fpu_mask
);
612 asm_fprintf (stream
, "\tfmovem %I0x%x,%Rsp@-\n", current_frame
.fpu_mask
);
614 if (dwarf2out_do_frame ())
616 char *l
= (char *) dwarf2out_cfi_label ();
619 cfa_offset
+= current_frame
.fpu_no
* 12;
620 if (! frame_pointer_needed
)
621 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
622 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
623 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
624 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
628 /* If the stack limit is not a symbol, check it here.
629 This has the disadvantage that it may be too late... */
630 if (current_function_limit_stack
)
632 if (REG_P (stack_limit_rtx
))
634 #if defined (MOTOROLA)
635 asm_fprintf (stream
, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
636 reg_names
[REGNO (stack_limit_rtx
)]);
638 asm_fprintf (stream
, "\tcmpl %s,%Rsp\n\ttrapcs\n",
639 reg_names
[REGNO (stack_limit_rtx
)]);
642 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
643 warning ("stack limit expression is not supported");
646 if (current_frame
.reg_no
<= 2)
648 /* Store each separately in the same order moveml uses.
649 Using two movel instructions instead of a single moveml
650 is about 15% faster for the 68020 and 68030 at no expense
655 for (i
= 0; i
< 16; i
++)
656 if (current_frame
.reg_rev_mask
& (1 << i
))
660 "\t%Omove.l %s,-(%Rsp)\n",
662 "\tmovel %s,%Rsp@-\n",
665 if (dwarf2out_do_frame ())
667 char *l
= (char *) dwarf2out_cfi_label ();
670 if (! frame_pointer_needed
)
671 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
672 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
676 else if (current_frame
.reg_rev_mask
)
680 /* The ColdFire does not support the predecrement form of the
681 MOVEM instruction, so we must adjust the stack pointer and
682 then use the plain address register indirect mode.
683 The required register save space was combined earlier with
684 the fsize_with_regs amount. */
687 asm_fprintf (stream
, "\tmovm.l %I0x%x,(%Rsp)\n", current_frame
.reg_mask
);
689 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@\n", current_frame
.reg_mask
);
695 asm_fprintf (stream
, "\tmovm.l %I0x%x,-(%Rsp)\n", current_frame
.reg_rev_mask
);
697 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@-\n", current_frame
.reg_rev_mask
);
700 if (dwarf2out_do_frame ())
702 char *l
= (char *) dwarf2out_cfi_label ();
705 cfa_offset
+= current_frame
.reg_no
* 4;
706 if (! frame_pointer_needed
)
707 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
708 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
709 if (current_frame
.reg_mask
& (1 << regno
))
710 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
713 if (!TARGET_SEP_DATA
&& flag_pic
&&
714 (current_function_uses_pic_offset_table
||
715 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
717 if (TARGET_ID_SHARED_LIBRARY
)
719 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
720 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
721 m68k_library_id_string
,
722 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
727 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
728 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
730 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
731 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
732 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
733 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
734 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
740 /* Return true if this function's epilogue can be output as RTL. */
743 use_return_insn (void)
745 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
748 /* We can output the epilogue as RTL only if no registers need to be
750 m68k_compute_frame_layout();
751 return current_frame
.reg_no
? false : true;
754 /* This function generates the assembly code for function exit,
755 on machines that need it.
757 The function epilogue should not depend on the current stack pointer!
758 It should use the frame pointer only, if there is a frame pointer.
759 This is mandatory because of alloca; we also take advantage of it to
760 omit stack adjustments before returning. */
763 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
765 HOST_WIDE_INT fsize
, fsize_with_regs
;
767 bool restore_from_sp
= false;
768 rtx insn
= get_last_insn ();
770 m68k_compute_frame_layout();
772 /* If the last insn was a BARRIER, we don't have to write any code. */
773 if (GET_CODE (insn
) == NOTE
)
774 insn
= prev_nonnote_insn (insn
);
775 if (insn
&& GET_CODE (insn
) == BARRIER
)
777 /* Output just a no-op so that debuggers don't get confused
778 about which function the pc is in at this address. */
779 fprintf (stream
, "\tnop\n");
783 #ifdef FUNCTION_EXTRA_EPILOGUE
784 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
787 fsize
= current_frame
.size
;
789 /* FIXME : leaf_function_p below is too strong.
790 What we really need to know there is if there could be pending
791 stack adjustment needed at that point. */
792 restore_from_sp
= ! frame_pointer_needed
793 || (! current_function_calls_alloca
&& leaf_function_p ());
795 /* fsize_with_regs is the size we need to adjust the sp when
796 popping the frame. */
797 fsize_with_regs
= fsize
;
799 /* Because the ColdFire doesn't support moveml with
800 complex address modes, we must adjust the stack manually
801 after restoring registers. When the frame pointer isn't used,
802 we can merge movem adjustment into frame unlinking
803 made immediately after it. */
804 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
805 fsize_with_regs
+= current_frame
.reg_no
* 4;
807 if (current_frame
.offset
+ fsize
>= 0x8000
809 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
811 /* Because the ColdFire doesn't support moveml with
812 complex address modes we make an extra correction here. */
816 asm_fprintf (stream
, "\t%Omove.l %I%d,%Ra1\n",
817 -fsize
- current_frame
.offset
);
819 asm_fprintf (stream
, "\tmovel %I%d,%Ra1\n",
820 -fsize
- current_frame
.offset
);
826 asm_fprintf (stream
, "\t%Omove.l %I%wd,%Ra1\n", -fsize
);
828 asm_fprintf (stream
, "\tmovel %I%wd,%Ra1\n", -fsize
);
832 fsize
= 0, big
= true;
834 if (current_frame
.reg_no
<= 2)
836 /* Restore each separately in the same order moveml does.
837 Using two movel instructions instead of a single moveml
838 is about 15% faster for the 68020 and 68030 at no expense
842 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
844 for (i
= 0; i
< 16; i
++)
845 if (current_frame
.reg_mask
& (1 << i
))
850 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
852 reg_names
[FRAME_POINTER_REGNUM
],
855 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
856 reg_names
[FRAME_POINTER_REGNUM
],
861 else if (restore_from_sp
)
864 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
867 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
874 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
876 reg_names
[FRAME_POINTER_REGNUM
],
879 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
880 reg_names
[FRAME_POINTER_REGNUM
],
888 else if (current_frame
.reg_mask
)
890 /* The ColdFire requires special handling due to its limited moveml insn. */
896 asm_fprintf (stream
, "\tadd.l %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
897 asm_fprintf (stream
, "\tmovm.l (%Ra1),%I0x%x\n", current_frame
.reg_mask
);
899 asm_fprintf (stream
, "\taddl %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
900 asm_fprintf (stream
, "\tmoveml %Ra1@,%I0x%x\n", current_frame
.reg_mask
);
903 else if (restore_from_sp
)
906 asm_fprintf (stream
, "\tmovm.l (%Rsp),%I0x%x\n", current_frame
.reg_mask
);
908 asm_fprintf (stream
, "\tmoveml %Rsp@,%I0x%x\n", current_frame
.reg_mask
);
914 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
915 current_frame
.offset
+ fsize
,
916 reg_names
[FRAME_POINTER_REGNUM
],
917 current_frame
.reg_mask
);
919 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
920 reg_names
[FRAME_POINTER_REGNUM
],
921 current_frame
.offset
+ fsize
,
922 current_frame
.reg_mask
);
926 else /* !TARGET_COLDFIRE */
931 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
932 current_frame
.offset
+ fsize
,
933 reg_names
[FRAME_POINTER_REGNUM
],
934 current_frame
.reg_mask
);
936 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
937 reg_names
[FRAME_POINTER_REGNUM
],
938 current_frame
.offset
+ fsize
,
939 current_frame
.reg_mask
);
942 else if (restore_from_sp
)
945 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%I0x%x\n",
946 current_frame
.reg_mask
);
948 asm_fprintf (stream
, "\tmoveml %Rsp@+,%I0x%x\n",
949 current_frame
.reg_mask
);
955 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
956 current_frame
.offset
+ fsize
,
957 reg_names
[FRAME_POINTER_REGNUM
],
958 current_frame
.reg_mask
);
960 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
961 reg_names
[FRAME_POINTER_REGNUM
],
962 current_frame
.offset
+ fsize
,
963 current_frame
.reg_mask
);
968 if (current_frame
.fpu_rev_mask
)
973 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
974 current_frame
.foffset
+ fsize
,
975 reg_names
[FRAME_POINTER_REGNUM
],
976 current_frame
.fpu_rev_mask
);
978 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
979 reg_names
[FRAME_POINTER_REGNUM
],
980 current_frame
.foffset
+ fsize
,
981 current_frame
.fpu_rev_mask
);
984 else if (restore_from_sp
)
987 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
988 current_frame
.fpu_rev_mask
);
990 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
991 current_frame
.fpu_rev_mask
);
997 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
998 current_frame
.foffset
+ fsize
,
999 reg_names
[FRAME_POINTER_REGNUM
],
1000 current_frame
.fpu_rev_mask
);
1002 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1003 reg_names
[FRAME_POINTER_REGNUM
],
1004 current_frame
.foffset
+ fsize
,
1005 current_frame
.fpu_rev_mask
);
1009 if (frame_pointer_needed
)
1010 fprintf (stream
, "\tunlk %s\n",
1011 reg_names
[FRAME_POINTER_REGNUM
]);
1012 else if (fsize_with_regs
)
1014 if (fsize_with_regs
<= 8)
1016 if (!TARGET_COLDFIRE
)
1019 asm_fprintf (stream
, "\taddq.w %I%wd,%Rsp\n", fsize_with_regs
);
1021 asm_fprintf (stream
, "\taddqw %I%wd,%Rsp\n", fsize_with_regs
);
1024 else /* TARGET_COLDFIRE */
1027 asm_fprintf (stream
, "\taddq.l %I%wd,%Rsp\n", fsize_with_regs
);
1029 asm_fprintf (stream
, "\taddql %I%wd,%Rsp\n", fsize_with_regs
);
1033 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
1035 /* On the CPU32 it is faster to use two addqw instructions to
1036 add a small integer (8 < N <= 16) to a register. */
1038 asm_fprintf (stream
, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
1039 fsize_with_regs
- 8);
1041 asm_fprintf (stream
, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
1042 fsize_with_regs
- 8);
1045 else if (fsize_with_regs
< 0x8000)
1050 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", fsize_with_regs
);
1052 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", fsize_with_regs
);
1058 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", fsize_with_regs
);
1060 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", fsize_with_regs
);
1067 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", fsize_with_regs
);
1069 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", fsize_with_regs
);
1073 if (current_function_calls_eh_return
)
1076 asm_fprintf (stream
, "\tadd.l %Ra0,%Rsp\n");
1078 asm_fprintf (stream
, "\taddl %Ra0,%Rsp\n");
1081 if (m68k_interrupt_function_p (current_function_decl
))
1082 fprintf (stream
, "\trte\n");
1083 else if (current_function_pops_args
)
1084 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1086 fprintf (stream
, "\trts\n");
1089 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1092 not_sp_operand (rtx op
, enum machine_mode mode
)
1094 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
1097 /* Return true if X is a valid comparison operator for the dbcc
1100 Note it rejects floating point comparison operators.
1101 (In the future we could use Fdbcc).
1103 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1106 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1108 switch (GET_CODE (x
))
1110 case EQ
: case NE
: case GTU
: case LTU
:
1114 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1116 case GT
: case LT
: case GE
: case LE
:
1117 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1123 /* Return nonzero if flags are currently in the 68881 flag register. */
1125 flags_in_68881 (void)
1127 /* We could add support for these in the future */
1128 return cc_status
.flags
& CC_IN_68881
;
1131 /* Output a BSR instruction suitable for PIC code. */
1133 m68k_output_pic_call(rtx dest
)
1137 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1139 /* We output a BSR instruction if we're using -fpic or we're building for
1140 * a target that supports long branches. If we're building -fPIC on the
1141 * 68000, 68010 or ColdFire we generate one of two sequences:
1142 * a shorter one that uses a GOT entry or a longer one that doesn't.
1143 * We'll use the -Os command-line flag to decide which to generate.
1144 * Both sequences take the same time to execute on the ColdFire.
1146 else if (TARGET_PCREL
)
1148 else if ((flag_pic
== 1) || TARGET_68020
)
1151 #elif defined(USE_GAS)
1152 out
= "bsr.l %0@PLTPC";
1154 out
= "bsr %0@PLTPC";
1156 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1157 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1159 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1161 output_asm_insn(out
, &dest
);
1164 /* Output a dbCC; jCC sequence. Note we do not handle the
1165 floating point version of this sequence (Fdbcc). We also
1166 do not handle alternative conditions when CC_NO_OVERFLOW is
1167 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1168 kick those out before we get here. */
1171 output_dbcc_and_branch (rtx
*operands
)
1173 switch (GET_CODE (operands
[3]))
1177 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
1179 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1185 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
1187 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1193 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
1195 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1201 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
1203 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1209 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
1211 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1217 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
1219 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1225 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
1227 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1233 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
1235 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1241 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
1243 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1249 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
1251 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1259 /* If the decrement is to be done in SImode, then we have
1260 to compensate for the fact that dbcc decrements in HImode. */
1261 switch (GET_MODE (operands
[0]))
1265 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
1267 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1280 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1283 enum rtx_code op_code
= GET_CODE (op
);
1285 /* This does not produce a useful cc. */
1288 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1289 below. Swap the operands and change the op if these requirements
1290 are not fulfilled. */
1291 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1295 operand1
= operand2
;
1297 op_code
= swap_condition (op_code
);
1299 loperands
[0] = operand1
;
1300 if (GET_CODE (operand1
) == REG
)
1301 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1303 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1304 if (operand2
!= const0_rtx
)
1306 loperands
[2] = operand2
;
1307 if (GET_CODE (operand2
) == REG
)
1308 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1310 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1312 loperands
[4] = gen_label_rtx();
1313 if (operand2
!= const0_rtx
)
1316 #ifdef SGS_CMP_ORDER
1317 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1319 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1322 #ifdef SGS_CMP_ORDER
1323 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1325 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1331 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1332 output_asm_insn ("tst%.l %0", loperands
);
1335 #ifdef SGS_CMP_ORDER
1336 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1338 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1343 output_asm_insn ("jbne %l4", loperands
);
1345 output_asm_insn ("jne %l4", loperands
);
1348 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1349 output_asm_insn ("tst%.l %1", loperands
);
1352 #ifdef SGS_CMP_ORDER
1353 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1355 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1360 loperands
[5] = dest
;
1365 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1366 CODE_LABEL_NUMBER (loperands
[4]));
1367 output_asm_insn ("seq %5", loperands
);
1371 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1372 CODE_LABEL_NUMBER (loperands
[4]));
1373 output_asm_insn ("sne %5", loperands
);
1377 loperands
[6] = gen_label_rtx();
1379 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1381 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1383 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1384 CODE_LABEL_NUMBER (loperands
[4]));
1385 output_asm_insn ("sgt %5", loperands
);
1386 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1387 CODE_LABEL_NUMBER (loperands
[6]));
1391 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1392 CODE_LABEL_NUMBER (loperands
[4]));
1393 output_asm_insn ("shi %5", loperands
);
1397 loperands
[6] = gen_label_rtx();
1399 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1401 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1403 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1404 CODE_LABEL_NUMBER (loperands
[4]));
1405 output_asm_insn ("slt %5", loperands
);
1406 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1407 CODE_LABEL_NUMBER (loperands
[6]));
1411 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1412 CODE_LABEL_NUMBER (loperands
[4]));
1413 output_asm_insn ("scs %5", loperands
);
1417 loperands
[6] = gen_label_rtx();
1419 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1421 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1423 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1424 CODE_LABEL_NUMBER (loperands
[4]));
1425 output_asm_insn ("sge %5", loperands
);
1426 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1427 CODE_LABEL_NUMBER (loperands
[6]));
1431 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1432 CODE_LABEL_NUMBER (loperands
[4]));
1433 output_asm_insn ("scc %5", loperands
);
1437 loperands
[6] = gen_label_rtx();
1439 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1441 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1443 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1444 CODE_LABEL_NUMBER (loperands
[4]));
1445 output_asm_insn ("sle %5", loperands
);
1446 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1447 CODE_LABEL_NUMBER (loperands
[6]));
1451 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1452 CODE_LABEL_NUMBER (loperands
[4]));
1453 output_asm_insn ("sls %5", loperands
);
1463 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1465 operands
[0] = countop
;
1466 operands
[1] = dataop
;
1468 if (GET_CODE (countop
) == CONST_INT
)
1470 register int count
= INTVAL (countop
);
1471 /* If COUNT is bigger than size of storage unit in use,
1472 advance to the containing unit of same size. */
1473 if (count
> signpos
)
1475 int offset
= (count
& ~signpos
) / 8;
1476 count
= count
& signpos
;
1477 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1479 if (count
== signpos
)
1480 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1482 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1484 /* These three statements used to use next_insns_test_no...
1485 but it appears that this should do the same job. */
1487 && next_insn_tests_no_inequality (insn
))
1490 && next_insn_tests_no_inequality (insn
))
1493 && next_insn_tests_no_inequality (insn
))
1496 cc_status
.flags
= CC_NOT_NEGATIVE
;
1498 return "btst %0,%1";
1501 /* Returns true if OP is either a symbol reference or a sum of a symbol
1502 reference and a constant. */
1505 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1507 switch (GET_CODE (op
))
1515 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1516 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1517 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1519 #if 0 /* Deleted, with corresponding change in m68k.h,
1520 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1522 return GET_MODE (op
) == mode
;
1530 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1533 extend_operator(rtx x
, enum machine_mode mode
)
1535 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1537 switch (GET_CODE(x
))
1548 /* Legitimize PIC addresses. If the address is already
1549 position-independent, we return ORIG. Newly generated
1550 position-independent addresses go to REG. If we need more
1551 than one register, we lose.
1553 An address is legitimized by making an indirect reference
1554 through the Global Offset Table with the name of the symbol
1557 The assembler and linker are responsible for placing the
1558 address of the symbol in the GOT. The function prologue
1559 is responsible for initializing a5 to the starting address
1562 The assembler is also responsible for translating a symbol name
1563 into a constant displacement from the start of the GOT.
1565 A quick example may make things a little clearer:
1567 When not generating PIC code to store the value 12345 into _foo
1568 we would generate the following code:
1572 When generating PIC two transformations are made. First, the compiler
1573 loads the address of foo into a register. So the first transformation makes:
1578 The code in movsi will intercept the lea instruction and call this
1579 routine which will transform the instructions into:
1581 movel a5@(_foo:w), a0
1585 That (in a nutshell) is how *all* symbol and label references are
1589 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1594 /* First handle a simple SYMBOL_REF or LABEL_REF */
1595 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1600 pic_ref
= gen_rtx_MEM (Pmode
,
1601 gen_rtx_PLUS (Pmode
,
1602 pic_offset_table_rtx
, orig
));
1603 current_function_uses_pic_offset_table
= 1;
1604 RTX_UNCHANGING_P (pic_ref
) = 1;
1605 emit_move_insn (reg
, pic_ref
);
1608 else if (GET_CODE (orig
) == CONST
)
1612 /* Make sure this has not already been legitimized. */
1613 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1614 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1620 /* legitimize both operands of the PLUS */
1621 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1623 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1624 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1625 base
== reg
? 0 : reg
);
1629 if (GET_CODE (orig
) == CONST_INT
)
1630 return plus_constant (base
, INTVAL (orig
));
1631 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1632 /* Likewise, should we set special REG_NOTEs here? */
1638 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1640 static CONST_METHOD
const_method (rtx
);
1642 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1645 const_method (rtx constant
)
1650 i
= INTVAL (constant
);
1654 /* The ColdFire doesn't have byte or word operations. */
1655 /* FIXME: This may not be useful for the m68060 either. */
1656 if (!TARGET_COLDFIRE
)
1658 /* if -256 < N < 256 but N is not in range for a moveq
1659 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1660 if (USE_MOVQ (i
^ 0xff))
1662 /* Likewise, try with not.w */
1663 if (USE_MOVQ (i
^ 0xffff))
1665 /* This is the only value where neg.w is useful */
1668 /* Try also with swap */
1670 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1673 /* Otherwise, use move.l */
1678 const_int_cost (rtx constant
)
1680 switch (const_method (constant
))
1683 /* Constants between -128 and 127 are cheap due to moveq */
1689 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1699 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1704 /* Constant zero is super cheap due to clr instruction. */
1705 if (x
== const0_rtx
)
1708 *total
= const_int_cost (x
);
1718 /* Make 0.0 cheaper than other floating constants to
1719 encourage creating tstsf and tstdf insns. */
1720 if (outer_code
== COMPARE
1721 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1727 /* These are vaguely right for a 68020. */
1728 /* The costs for long multiply have been adjusted to work properly
1729 in synth_mult on the 68020, relative to an average of the time
1730 for add and the time for shift, taking away a little more because
1731 sometimes move insns are needed. */
1732 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1733 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1734 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1735 TARGET_CFV3 ? 2 : 5)
1736 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1739 /* An lea costs about three times as much as a simple add. */
1740 if (GET_MODE (x
) == SImode
1741 && GET_CODE (XEXP (x
, 1)) == REG
1742 && GET_CODE (XEXP (x
, 0)) == MULT
1743 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1744 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1745 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1746 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1747 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1749 /* lea an@(dx:l:i),am */
1750 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1760 *total
= COSTS_N_INSNS(1);
1763 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1765 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1767 if (INTVAL (XEXP (x
, 1)) < 16)
1768 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1770 /* We're using clrw + swap for these cases. */
1771 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1774 *total
= COSTS_N_INSNS (10); /* worst case */
1777 /* A shift by a big integer takes an extra instruction. */
1778 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1779 && (INTVAL (XEXP (x
, 1)) == 16))
1781 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1784 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1785 && !(INTVAL (XEXP (x
, 1)) > 0
1786 && INTVAL (XEXP (x
, 1)) <= 8))
1788 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1794 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1795 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1796 && GET_MODE (x
) == SImode
)
1797 *total
= COSTS_N_INSNS (MULW_COST
);
1798 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1799 *total
= COSTS_N_INSNS (MULW_COST
);
1801 *total
= COSTS_N_INSNS (MULL_COST
);
1808 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1809 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1810 else if (TARGET_CF_HWDIV
)
1811 *total
= COSTS_N_INSNS (18);
1813 *total
= COSTS_N_INSNS (43); /* div.l */
1822 output_move_const_into_data_reg (rtx
*operands
)
1826 i
= INTVAL (operands
[1]);
1827 switch (const_method (operands
[1]))
1830 return "moveq %1,%0";
1832 operands
[1] = GEN_INT (i
^ 0xff);
1833 return "moveq %1,%0\n\tnot%.b %0";
1835 operands
[1] = GEN_INT (i
^ 0xffff);
1836 return "moveq %1,%0\n\tnot%.w %0";
1838 return "moveq %#-128,%0\n\tneg%.w %0";
1843 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1844 return "moveq %1,%0\n\tswap %0";
1847 return "move%.l %1,%0";
1854 output_move_simode_const (rtx
*operands
)
1856 if (operands
[1] == const0_rtx
1857 && (DATA_REG_P (operands
[0])
1858 || GET_CODE (operands
[0]) == MEM
)
1859 /* clr insns on 68000 read before writing.
1860 This isn't so on the 68010, but we have no TARGET_68010. */
1861 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1862 || !(GET_CODE (operands
[0]) == MEM
1863 && MEM_VOLATILE_P (operands
[0]))))
1865 else if (operands
[1] == const0_rtx
1866 && ADDRESS_REG_P (operands
[0]))
1867 return "sub%.l %0,%0";
1868 else if (DATA_REG_P (operands
[0]))
1869 return output_move_const_into_data_reg (operands
);
1870 else if (ADDRESS_REG_P (operands
[0])
1871 && INTVAL (operands
[1]) < 0x8000
1872 && INTVAL (operands
[1]) >= -0x8000)
1873 return "move%.w %1,%0";
1874 else if (GET_CODE (operands
[0]) == MEM
1875 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1876 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1877 && INTVAL (operands
[1]) < 0x8000
1878 && INTVAL (operands
[1]) >= -0x8000)
1880 return "move%.l %1,%0";
1884 output_move_simode (rtx
*operands
)
1886 if (GET_CODE (operands
[1]) == CONST_INT
)
1887 return output_move_simode_const (operands
);
1888 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1889 || GET_CODE (operands
[1]) == CONST
)
1890 && push_operand (operands
[0], SImode
))
1892 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1893 || GET_CODE (operands
[1]) == CONST
)
1894 && ADDRESS_REG_P (operands
[0]))
1895 return "lea %a1,%0";
1896 return "move%.l %1,%0";
1900 output_move_himode (rtx
*operands
)
1902 if (GET_CODE (operands
[1]) == CONST_INT
)
1904 if (operands
[1] == const0_rtx
1905 && (DATA_REG_P (operands
[0])
1906 || GET_CODE (operands
[0]) == MEM
)
1907 /* clr insns on 68000 read before writing.
1908 This isn't so on the 68010, but we have no TARGET_68010. */
1909 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1910 || !(GET_CODE (operands
[0]) == MEM
1911 && MEM_VOLATILE_P (operands
[0]))))
1913 else if (operands
[1] == const0_rtx
1914 && ADDRESS_REG_P (operands
[0]))
1915 return "sub%.l %0,%0";
1916 else if (DATA_REG_P (operands
[0])
1917 && INTVAL (operands
[1]) < 128
1918 && INTVAL (operands
[1]) >= -128)
1920 return "moveq %1,%0";
1922 else if (INTVAL (operands
[1]) < 0x8000
1923 && INTVAL (operands
[1]) >= -0x8000)
1924 return "move%.w %1,%0";
1926 else if (CONSTANT_P (operands
[1]))
1927 return "move%.l %1,%0";
1928 /* Recognize the insn before a tablejump, one that refers
1929 to a table of offsets. Such an insn will need to refer
1930 to a label on the insn. So output one. Use the label-number
1931 of the table of offsets to generate this label. This code,
1932 and similar code below, assumes that there will be at most one
1933 reference to each table. */
1934 if (GET_CODE (operands
[1]) == MEM
1935 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1936 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1937 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1939 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1940 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1942 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1943 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1945 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1946 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1947 #endif /* not SGS */
1948 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1949 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1950 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1951 #ifdef SGS_SWITCH_TABLES
1952 /* Set flag saying we need to define the symbol
1953 LD%n (with value L%n-LI%n) at the end of the switch table. */
1954 switch_table_difference_label_flag
= 1;
1955 #endif /* SGS_SWITCH_TABLES */
1956 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1958 return "move%.w %1,%0";
1962 output_move_qimode (rtx
*operands
)
1966 /* This is probably useless, since it loses for pushing a struct
1967 of several bytes a byte at a time. */
1968 /* 68k family always modifies the stack pointer by at least 2, even for
1969 byte pushes. The 5200 (ColdFire) does not do this. */
1970 if (GET_CODE (operands
[0]) == MEM
1971 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1972 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1973 && ! ADDRESS_REG_P (operands
[1])
1974 && ! TARGET_COLDFIRE
)
1976 xoperands
[1] = operands
[1];
1978 = gen_rtx_MEM (QImode
,
1979 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1980 /* Just pushing a byte puts it in the high byte of the halfword. */
1981 /* We must put it in the low-order, high-numbered byte. */
1982 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1984 xoperands
[3] = stack_pointer_rtx
;
1985 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1988 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1992 /* clr and st insns on 68000 read before writing.
1993 This isn't so on the 68010, but we have no TARGET_68010. */
1994 if (!ADDRESS_REG_P (operands
[0])
1995 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1996 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1998 if (operands
[1] == const0_rtx
)
2000 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2001 && GET_CODE (operands
[1]) == CONST_INT
2002 && (INTVAL (operands
[1]) & 255) == 255)
2008 if (GET_CODE (operands
[1]) == CONST_INT
2009 && DATA_REG_P (operands
[0])
2010 && INTVAL (operands
[1]) < 128
2011 && INTVAL (operands
[1]) >= -128)
2013 return "moveq %1,%0";
2015 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2016 return "sub%.l %0,%0";
2017 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2018 return "move%.l %1,%0";
2019 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2020 from address registers. */
2021 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2022 return "move%.w %1,%0";
2023 return "move%.b %1,%0";
2027 output_move_stricthi (rtx
*operands
)
2029 if (operands
[1] == const0_rtx
2030 /* clr insns on 68000 read before writing.
2031 This isn't so on the 68010, but we have no TARGET_68010. */
2032 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2033 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2035 return "move%.w %1,%0";
2039 output_move_strictqi (rtx
*operands
)
2041 if (operands
[1] == const0_rtx
2042 /* clr insns on 68000 read before writing.
2043 This isn't so on the 68010, but we have no TARGET_68010. */
2044 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2045 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2047 return "move%.b %1,%0";
2050 /* Return the best assembler insn template
2051 for moving operands[1] into operands[0] as a fullword. */
2054 singlemove_string (rtx
*operands
)
2056 if (GET_CODE (operands
[1]) == CONST_INT
)
2057 return output_move_simode_const (operands
);
2058 return "move%.l %1,%0";
2062 /* Output assembler code to perform a doubleword move insn
2063 with operands OPERANDS. */
2066 output_move_double (rtx
*operands
)
2070 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2075 rtx addreg0
= 0, addreg1
= 0;
2076 int dest_overlapped_low
= 0;
2077 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2082 /* First classify both operands. */
2084 if (REG_P (operands
[0]))
2086 else if (offsettable_memref_p (operands
[0]))
2088 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2090 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2092 else if (GET_CODE (operands
[0]) == MEM
)
2097 if (REG_P (operands
[1]))
2099 else if (CONSTANT_P (operands
[1]))
2101 else if (offsettable_memref_p (operands
[1]))
2103 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2105 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2107 else if (GET_CODE (operands
[1]) == MEM
)
2112 /* Check for the cases that the operand constraints are not
2113 supposed to allow to happen. Abort if we get one,
2114 because generating code for these cases is painful. */
2116 if (optype0
== RNDOP
|| optype1
== RNDOP
)
2119 /* If one operand is decrementing and one is incrementing
2120 decrement the former register explicitly
2121 and change that operand into ordinary indexing. */
2123 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2125 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2127 output_asm_insn ("sub%.l %#12,%0", operands
);
2129 output_asm_insn ("subq%.l %#8,%0", operands
);
2130 if (GET_MODE (operands
[1]) == XFmode
)
2131 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2132 else if (GET_MODE (operands
[0]) == DFmode
)
2133 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2135 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2138 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2140 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2142 output_asm_insn ("sub%.l %#12,%1", operands
);
2144 output_asm_insn ("subq%.l %#8,%1", operands
);
2145 if (GET_MODE (operands
[1]) == XFmode
)
2146 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2147 else if (GET_MODE (operands
[1]) == DFmode
)
2148 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2150 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2154 /* If an operand is an unoffsettable memory ref, find a register
2155 we can increment temporarily to make it refer to the second word. */
2157 if (optype0
== MEMOP
)
2158 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2160 if (optype1
== MEMOP
)
2161 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2163 /* Ok, we can do one word at a time.
2164 Normally we do the low-numbered word first,
2165 but if either operand is autodecrementing then we
2166 do the high-numbered word first.
2168 In either case, set up in LATEHALF the operands to use
2169 for the high-numbered word and in some cases alter the
2170 operands in OPERANDS to be suitable for the low-numbered word. */
2174 if (optype0
== REGOP
)
2176 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2177 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2179 else if (optype0
== OFFSOP
)
2181 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2182 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2186 middlehalf
[0] = operands
[0];
2187 latehalf
[0] = operands
[0];
2190 if (optype1
== REGOP
)
2192 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2193 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2195 else if (optype1
== OFFSOP
)
2197 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2198 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2200 else if (optype1
== CNSTOP
)
2202 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2207 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2208 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2209 operands
[1] = GEN_INT (l
[0]);
2210 middlehalf
[1] = GEN_INT (l
[1]);
2211 latehalf
[1] = GEN_INT (l
[2]);
2213 else if (CONSTANT_P (operands
[1]))
2215 /* actually, no non-CONST_DOUBLE constant should ever
2218 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2219 latehalf
[1] = constm1_rtx
;
2221 latehalf
[1] = const0_rtx
;
2226 middlehalf
[1] = operands
[1];
2227 latehalf
[1] = operands
[1];
2231 /* size is not 12: */
2233 if (optype0
== REGOP
)
2234 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2235 else if (optype0
== OFFSOP
)
2236 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2238 latehalf
[0] = operands
[0];
2240 if (optype1
== REGOP
)
2241 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2242 else if (optype1
== OFFSOP
)
2243 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2244 else if (optype1
== CNSTOP
)
2245 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2247 latehalf
[1] = operands
[1];
2250 /* If insn is effectively movd N(sp),-(sp) then we will do the
2251 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2252 for the low word as well, to compensate for the first decrement of sp. */
2253 if (optype0
== PUSHOP
2254 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2255 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2256 operands
[1] = middlehalf
[1] = latehalf
[1];
2258 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2259 if the upper part of reg N does not appear in the MEM, arrange to
2260 emit the move late-half first. Otherwise, compute the MEM address
2261 into the upper part of N and use that as a pointer to the memory
2263 if (optype0
== REGOP
2264 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2266 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2268 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2269 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2271 /* If both halves of dest are used in the src memory address,
2272 compute the address into latehalf of dest.
2273 Note that this can't happen if the dest is two data regs. */
2275 xops
[0] = latehalf
[0];
2276 xops
[1] = XEXP (operands
[1], 0);
2277 output_asm_insn ("lea %a1,%0", xops
);
2278 if (GET_MODE (operands
[1]) == XFmode
)
2280 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2281 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2282 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2286 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2287 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2291 && reg_overlap_mentioned_p (middlehalf
[0],
2292 XEXP (operands
[1], 0)))
2294 /* Check for two regs used by both source and dest.
2295 Note that this can't happen if the dest is all data regs.
2296 It can happen if the dest is d6, d7, a0.
2297 But in that case, latehalf is an addr reg, so
2298 the code at compadr does ok. */
2300 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2301 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2304 /* JRV says this can't happen: */
2305 if (addreg0
|| addreg1
)
2308 /* Only the middle reg conflicts; simply put it last. */
2309 output_asm_insn (singlemove_string (operands
), operands
);
2310 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2311 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2314 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2315 /* If the low half of dest is mentioned in the source memory
2316 address, the arrange to emit the move late half first. */
2317 dest_overlapped_low
= 1;
2320 /* If one or both operands autodecrementing,
2321 do the two words, high-numbered first. */
2323 /* Likewise, the first move would clobber the source of the second one,
2324 do them in the other order. This happens only for registers;
2325 such overlap can't happen in memory unless the user explicitly
2326 sets it up, and that is an undefined circumstance. */
2328 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2329 || (optype0
== REGOP
&& optype1
== REGOP
2330 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2331 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2332 || dest_overlapped_low
)
2334 /* Make any unoffsettable addresses point at high-numbered word. */
2338 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2340 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2345 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2347 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2351 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2353 /* Undo the adds we just did. */
2355 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2357 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2361 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2363 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2365 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2368 /* Do low-numbered word. */
2369 return singlemove_string (operands
);
2372 /* Normal case: do the two words, low-numbered first. */
2374 output_asm_insn (singlemove_string (operands
), operands
);
2376 /* Do the middle one of the three words for long double */
2380 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2382 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2384 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2387 /* Make any unoffsettable addresses point at high-numbered word. */
2389 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2391 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2394 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2396 /* Undo the adds we just did. */
2400 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2402 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2407 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2409 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2415 /* Return a REG that occurs in ADDR with coefficient 1.
2416 ADDR can be effectively incremented by incrementing REG. */
2419 find_addr_reg (rtx addr
)
2421 while (GET_CODE (addr
) == PLUS
)
2423 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2424 addr
= XEXP (addr
, 0);
2425 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2426 addr
= XEXP (addr
, 1);
2427 else if (CONSTANT_P (XEXP (addr
, 0)))
2428 addr
= XEXP (addr
, 1);
2429 else if (CONSTANT_P (XEXP (addr
, 1)))
2430 addr
= XEXP (addr
, 0);
2434 if (GET_CODE (addr
) == REG
)
2439 /* Output assembler code to perform a 32-bit 3-operand add. */
2442 output_addsi3 (rtx
*operands
)
2444 if (! operands_match_p (operands
[0], operands
[1]))
2446 if (!ADDRESS_REG_P (operands
[1]))
2448 rtx tmp
= operands
[1];
2450 operands
[1] = operands
[2];
2454 /* These insns can result from reloads to access
2455 stack slots over 64k from the frame pointer. */
2456 if (GET_CODE (operands
[2]) == CONST_INT
2457 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2458 return "move%.l %2,%0\n\tadd%.l %1,%0";
2460 if (GET_CODE (operands
[2]) == REG
)
2461 return "lea 0(%1,%2.l),%0";
2463 return "lea %c2(%1),%0";
2464 #elif defined(MOTOROLA)
2465 if (GET_CODE (operands
[2]) == REG
)
2466 return "lea (%1,%2.l),%0";
2468 return "lea (%c2,%1),%0";
2469 #else /* not MOTOROLA (MIT syntax) */
2470 if (GET_CODE (operands
[2]) == REG
)
2471 return "lea %1@(0,%2:l),%0";
2473 return "lea %1@(%c2),%0";
2474 #endif /* not MOTOROLA */
2476 if (GET_CODE (operands
[2]) == CONST_INT
)
2478 if (INTVAL (operands
[2]) > 0
2479 && INTVAL (operands
[2]) <= 8)
2480 return "addq%.l %2,%0";
2481 if (INTVAL (operands
[2]) < 0
2482 && INTVAL (operands
[2]) >= -8)
2484 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2485 return "subq%.l %2,%0";
2487 /* On the CPU32 it is faster to use two addql instructions to
2488 add a small integer (8 < N <= 16) to a register.
2489 Likewise for subql. */
2490 if (TARGET_CPU32
&& REG_P (operands
[0]))
2492 if (INTVAL (operands
[2]) > 8
2493 && INTVAL (operands
[2]) <= 16)
2495 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2496 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2498 if (INTVAL (operands
[2]) < -8
2499 && INTVAL (operands
[2]) >= -16)
2501 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2502 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2505 if (ADDRESS_REG_P (operands
[0])
2506 && INTVAL (operands
[2]) >= -0x8000
2507 && INTVAL (operands
[2]) < 0x8000)
2510 return "add%.w %2,%0";
2513 return "lea (%c2,%0),%0";
2515 return "lea %0@(%c2),%0";
2519 return "add%.l %2,%0";
2522 /* Store in cc_status the expressions that the condition codes will
2523 describe after execution of an instruction whose pattern is EXP.
2524 Do not alter them if the instruction would not alter the cc's. */
2526 /* On the 68000, all the insns to store in an address register fail to
2527 set the cc's. However, in some cases these instructions can make it
2528 possibly invalid to use the saved cc's. In those cases we clear out
2529 some or all of the saved cc's so they won't be used. */
2532 notice_update_cc (rtx exp
, rtx insn
)
2534 if (GET_CODE (exp
) == SET
)
2536 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2540 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2542 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2543 cc_status
.value1
= 0;
2544 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2545 cc_status
.value2
= 0;
2547 else if (!FP_REG_P (SET_DEST (exp
))
2548 && SET_DEST (exp
) != cc0_rtx
2549 && (FP_REG_P (SET_SRC (exp
))
2550 || GET_CODE (SET_SRC (exp
)) == FIX
2551 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2552 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2556 /* A pair of move insns doesn't produce a useful overall cc. */
2557 else if (!FP_REG_P (SET_DEST (exp
))
2558 && !FP_REG_P (SET_SRC (exp
))
2559 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2560 && (GET_CODE (SET_SRC (exp
)) == REG
2561 || GET_CODE (SET_SRC (exp
)) == MEM
2562 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2566 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2570 else if (XEXP (exp
, 0) != pc_rtx
)
2572 cc_status
.flags
= 0;
2573 cc_status
.value1
= XEXP (exp
, 0);
2574 cc_status
.value2
= XEXP (exp
, 1);
2577 else if (GET_CODE (exp
) == PARALLEL
2578 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2580 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2582 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2584 cc_status
.flags
= 0;
2585 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2586 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2591 if (cc_status
.value2
!= 0
2592 && ADDRESS_REG_P (cc_status
.value2
)
2593 && GET_MODE (cc_status
.value2
) == QImode
)
2595 if (cc_status
.value2
!= 0)
2596 switch (GET_CODE (cc_status
.value2
))
2598 case PLUS
: case MINUS
: case MULT
:
2599 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2600 #if 0 /* These instructions always clear the overflow bit */
2601 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2602 case ROTATE
: case ROTATERT
:
2604 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2605 cc_status
.flags
|= CC_NO_OVERFLOW
;
2608 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2609 ends with a move insn moving r2 in r2's mode.
2610 Thus, the cc's are set for r2.
2611 This can set N bit spuriously. */
2612 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2617 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2619 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2620 cc_status
.value2
= 0;
2621 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2622 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2623 cc_status
.flags
= CC_IN_68881
;
2627 output_move_const_double (rtx
*operands
)
2629 int code
= standard_68881_constant_p (operands
[1]);
2633 static char buf
[40];
2635 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2638 return "fmove%.d %1,%0";
2642 output_move_const_single (rtx
*operands
)
2644 int code
= standard_68881_constant_p (operands
[1]);
2648 static char buf
[40];
2650 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2653 return "fmove%.s %f1,%0";
2656 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2657 from the "fmovecr" instruction.
2658 The value, anded with 0xff, gives the code to use in fmovecr
2659 to get the desired constant. */
2661 /* This code has been fixed for cross-compilation. */
2663 static int inited_68881_table
= 0;
2665 static const char *const strings_68881
[7] = {
2675 static const int codes_68881
[7] = {
2685 REAL_VALUE_TYPE values_68881
[7];
2687 /* Set up values_68881 array by converting the decimal values
2688 strings_68881 to binary. */
2691 init_68881_table (void)
2695 enum machine_mode mode
;
2698 for (i
= 0; i
< 7; i
++)
2702 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2703 values_68881
[i
] = r
;
2705 inited_68881_table
= 1;
2709 standard_68881_constant_p (rtx x
)
2714 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2715 used at all on those chips. */
2716 if (TARGET_68040
|| TARGET_68060
)
2719 if (! inited_68881_table
)
2720 init_68881_table ();
2722 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2724 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2726 for (i
= 0; i
< 6; i
++)
2728 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2729 return (codes_68881
[i
]);
2732 if (GET_MODE (x
) == SFmode
)
2735 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2736 return (codes_68881
[6]);
2738 /* larger powers of ten in the constants ram are not used
2739 because they are not equal to a `double' C constant. */
2743 /* If X is a floating-point constant, return the logarithm of X base 2,
2744 or 0 if X is not a power of 2. */
2747 floating_exact_log2 (rtx x
)
2749 REAL_VALUE_TYPE r
, r1
;
2752 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2754 if (REAL_VALUES_LESS (r
, dconst1
))
2757 exp
= real_exponent (&r
);
2758 real_2expN (&r1
, exp
);
2759 if (REAL_VALUES_EQUAL (r1
, r
))
2765 /* A C compound statement to output to stdio stream STREAM the
2766 assembler syntax for an instruction operand X. X is an RTL
2769 CODE is a value that can be used to specify one of several ways
2770 of printing the operand. It is used when identical operands
2771 must be printed differently depending on the context. CODE
2772 comes from the `%' specification that was used to request
2773 printing of the operand. If the specification was just `%DIGIT'
2774 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2775 is the ASCII code for LTR.
2777 If X is a register, this macro should print the register's name.
2778 The names can be found in an array `reg_names' whose type is
2779 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2781 When the machine description has a specification `%PUNCT' (a `%'
2782 followed by a punctuation character), this macro is called with
2783 a null pointer for X and the punctuation character for CODE.
2785 The m68k specific codes are:
2787 '.' for dot needed in Motorola-style opcode names.
2788 '-' for an operand pushing on the stack:
2789 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2790 '+' for an operand pushing on the stack:
2791 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2792 '@' for a reference to the top word on the stack:
2793 sp@, (sp) or (%sp) depending on the style of syntax.
2794 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2795 but & in SGS syntax).
2796 '!' for the cc register (used in an `and to cc' insn).
2797 '$' for the letter `s' in an op code, but only on the 68040.
2798 '&' for the letter `d' in an op code, but only on the 68040.
2799 '/' for register prefix needed by longlong.h.
2801 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2802 'd' to force memory addressing to be absolute, not relative.
2803 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2804 'o' for operands to go directly to output_operand_address (bypassing
2805 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2806 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2807 or print pair of registers as rx:ry.
2812 print_operand (FILE *file
, rtx op
, int letter
)
2816 #if defined (MOTOROLA)
2817 fprintf (file
, ".");
2820 else if (letter
== '#')
2822 asm_fprintf (file
, "%I");
2824 else if (letter
== '-')
2827 asm_fprintf (file
, "-(%Rsp)");
2829 asm_fprintf (file
, "%Rsp@-");
2832 else if (letter
== '+')
2835 asm_fprintf (file
, "(%Rsp)+");
2837 asm_fprintf (file
, "%Rsp@+");
2840 else if (letter
== '@')
2843 asm_fprintf (file
, "(%Rsp)");
2845 asm_fprintf (file
, "%Rsp@");
2848 else if (letter
== '!')
2850 asm_fprintf (file
, "%Rfpcr");
2852 else if (letter
== '$')
2854 if (TARGET_68040_ONLY
)
2856 fprintf (file
, "s");
2859 else if (letter
== '&')
2861 if (TARGET_68040_ONLY
)
2863 fprintf (file
, "d");
2866 else if (letter
== '/')
2868 asm_fprintf (file
, "%R");
2870 else if (letter
== 'o')
2872 /* This is only for direct addresses with TARGET_PCREL */
2873 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2876 output_addr_const (file
, XEXP (op
, 0));
2878 else if (GET_CODE (op
) == REG
)
2881 /* Print out the second register name of a register pair.
2882 I.e., R (6) => 7. */
2883 fputs (reg_names
[REGNO (op
) + 1], file
);
2885 fputs (reg_names
[REGNO (op
)], file
);
2887 else if (GET_CODE (op
) == MEM
)
2889 output_address (XEXP (op
, 0));
2890 if (letter
== 'd' && ! TARGET_68020
2891 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2892 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2893 && INTVAL (XEXP (op
, 0)) < 0x8000
2894 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2897 fprintf (file
, ".l");
2899 fprintf (file
, ":l");
2903 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2906 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2907 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2909 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2912 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2913 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2915 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2918 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2919 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2923 /* Use `print_operand_address' instead of `output_addr_const'
2924 to ensure that we print relevant PIC stuff. */
2925 asm_fprintf (file
, "%I");
2927 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2928 print_operand_address (file
, op
);
2930 output_addr_const (file
, op
);
2935 /* A C compound statement to output to stdio stream STREAM the
2936 assembler syntax for an instruction operand that is a memory
2937 reference whose address is ADDR. ADDR is an RTL expression.
2939 Note that this contains a kludge that knows that the only reason
2940 we have an address (plus (label_ref...) (reg...)) when not generating
2941 PIC code is in the insn before a tablejump, and we know that m68k.md
2942 generates a label LInnn: on such an insn.
2944 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2945 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2947 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2948 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2949 we want. This difference can be accommodated by using an assembler
2950 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2951 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2952 macro. See m68k/sgs.h for an example; for versions without the bug.
2953 Some assemblers refuse all the above solutions. The workaround is to
2954 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2957 They also do not like things like "pea 1.w", so we simple leave off
2958 the .w on small constants.
2960 This routine is responsible for distinguishing between -fpic and -fPIC
2961 style relocations in an address. When generating -fpic code the
2962 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2963 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2965 #ifndef ASM_OUTPUT_CASE_FETCH
2968 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2969 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2971 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2972 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2975 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2976 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2978 #endif /* ASM_OUTPUT_CASE_FETCH */
2981 print_operand_address (FILE *file
, rtx addr
)
2983 register rtx reg1
, reg2
, breg
, ireg
;
2986 switch (GET_CODE (addr
))
2990 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2992 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2997 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2999 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
3004 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
3006 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
3010 reg1
= reg2
= ireg
= breg
= offset
= 0;
3011 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3013 offset
= XEXP (addr
, 0);
3014 addr
= XEXP (addr
, 1);
3016 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3018 offset
= XEXP (addr
, 1);
3019 addr
= XEXP (addr
, 0);
3021 if (GET_CODE (addr
) != PLUS
)
3025 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3027 reg1
= XEXP (addr
, 0);
3028 addr
= XEXP (addr
, 1);
3030 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3032 reg1
= XEXP (addr
, 1);
3033 addr
= XEXP (addr
, 0);
3035 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3037 reg1
= XEXP (addr
, 0);
3038 addr
= XEXP (addr
, 1);
3040 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3042 reg1
= XEXP (addr
, 1);
3043 addr
= XEXP (addr
, 0);
3045 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3047 reg1
= XEXP (addr
, 0);
3048 addr
= XEXP (addr
, 1);
3050 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3052 reg1
= XEXP (addr
, 1);
3053 addr
= XEXP (addr
, 0);
3055 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3056 || GET_CODE (addr
) == SIGN_EXTEND
)
3068 #if 0 /* for OLD_INDEXING */
3069 else if (GET_CODE (addr
) == PLUS
)
3071 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3073 reg2
= XEXP (addr
, 0);
3074 addr
= XEXP (addr
, 1);
3076 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3078 reg2
= XEXP (addr
, 1);
3079 addr
= XEXP (addr
, 0);
3091 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3092 || GET_CODE (reg1
) == MULT
))
3093 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3098 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3103 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3104 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3107 if (GET_CODE (ireg
) == MULT
)
3109 scale
= INTVAL (XEXP (ireg
, 1));
3110 ireg
= XEXP (ireg
, 0);
3112 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3114 ASM_OUTPUT_CASE_FETCH (file
,
3115 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3116 reg_names
[REGNO (XEXP (ireg
, 0))]);
3117 fprintf (file
, "w");
3121 ASM_OUTPUT_CASE_FETCH (file
,
3122 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3123 reg_names
[REGNO (ireg
)]);
3124 fprintf (file
, "l");
3129 fprintf (file
, "*%d", scale
);
3131 fprintf (file
, ":%d", scale
);
3137 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3138 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3140 ASM_OUTPUT_CASE_FETCH (file
,
3141 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3142 reg_names
[REGNO (breg
)]);
3143 fprintf (file
, "l)");
3146 if (ireg
!= 0 || breg
!= 0)
3153 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3160 output_addr_const (file
, addr
);
3161 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3163 fprintf (file
, "@GOT");
3165 fprintf (file
, ".w");
3168 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3174 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3177 output_addr_const (file
, addr
);
3178 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3179 fprintf (file
, ":w");
3180 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3181 fprintf (file
, ":l");
3183 if (addr
!= 0 && ireg
!= 0)
3188 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3190 scale
= INTVAL (XEXP (ireg
, 1));
3191 ireg
= XEXP (ireg
, 0);
3193 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3196 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3198 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3204 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3206 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3212 fprintf (file
, "*%d", scale
);
3214 fprintf (file
, ":%d", scale
);
3220 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3221 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3223 ASM_OUTPUT_CASE_FETCH (file
,
3224 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3225 reg_names
[REGNO (reg1
)]);
3226 fprintf (file
, "l)");
3229 /* FALL-THROUGH (is this really what we want?) */
3231 if (GET_CODE (addr
) == CONST_INT
3232 && INTVAL (addr
) < 0x8000
3233 && INTVAL (addr
) >= -0x8000)
3237 /* Many SGS assemblers croak on size specifiers for constants. */
3238 fprintf (file
, "%d", (int) INTVAL (addr
));
3240 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3243 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3246 else if (GET_CODE (addr
) == CONST_INT
)
3248 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3250 else if (TARGET_PCREL
)
3253 output_addr_const (file
, addr
);
3255 asm_fprintf (file
, ":w,%Rpc)");
3257 asm_fprintf (file
, ":l,%Rpc)");
3261 /* Special case for SYMBOL_REF if the symbol name ends in
3262 `.<letter>', this can be mistaken as a size suffix. Put
3263 the name in parentheses. */
3264 if (GET_CODE (addr
) == SYMBOL_REF
3265 && strlen (XSTR (addr
, 0)) > 2
3266 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3269 output_addr_const (file
, addr
);
3273 output_addr_const (file
, addr
);
3279 /* Check for cases where a clr insns can be omitted from code using
3280 strict_low_part sets. For example, the second clrl here is not needed:
3281 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3283 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3284 insn we are checking for redundancy. TARGET is the register set by the
3288 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3293 p
= prev_nonnote_insn (first_insn
);
3297 /* If it isn't an insn, then give up. */
3298 if (GET_CODE (p
) != INSN
)
3301 if (reg_set_p (target
, p
))
3303 rtx set
= single_set (p
);
3306 /* If it isn't an easy to recognize insn, then give up. */
3310 dest
= SET_DEST (set
);
3312 /* If this sets the entire target register to zero, then our
3313 first_insn is redundant. */
3314 if (rtx_equal_p (dest
, target
)
3315 && SET_SRC (set
) == const0_rtx
)
3317 else if (GET_CODE (dest
) == STRICT_LOW_PART
3318 && GET_CODE (XEXP (dest
, 0)) == REG
3319 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3320 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3321 <= GET_MODE_SIZE (mode
)))
3322 /* This is a strict low part set which modifies less than
3323 we are using, so it is safe. */
3329 p
= prev_nonnote_insn (p
);
3336 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3337 range carefully since this predicate is used in DImode contexts. Also, we
3338 need some extra crud to make it work when hosted on 64-bit machines. */
3341 const_uint32_operand (rtx op
, enum machine_mode mode
)
3343 /* It doesn't make sense to ask this question with a mode that is
3344 not larger than 32 bits. */
3345 if (GET_MODE_BITSIZE (mode
) <= 32)
3348 #if HOST_BITS_PER_WIDE_INT > 32
3349 /* All allowed constants will fit a CONST_INT. */
3350 return (GET_CODE (op
) == CONST_INT
3351 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3353 return (GET_CODE (op
) == CONST_INT
3354 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3358 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3359 to check the range carefully since this predicate is used in DImode
3363 const_sint32_operand (rtx op
, enum machine_mode mode
)
3365 /* It doesn't make sense to ask this question with a mode that is
3366 not larger than 32 bits. */
3367 if (GET_MODE_BITSIZE (mode
) <= 32)
3370 /* All allowed constants will fit a CONST_INT. */
3371 return (GET_CODE (op
) == CONST_INT
3372 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3375 /* Operand predicates for implementing asymmetric pc-relative addressing
3376 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3377 when used as a source operand, but not as a destination operand.
3379 We model this by restricting the meaning of the basic predicates
3380 (general_operand, memory_operand, etc) to forbid the use of this
3381 addressing mode, and then define the following predicates that permit
3382 this addressing mode. These predicates can then be used for the
3383 source operands of the appropriate instructions.
3385 n.b. While it is theoretically possible to change all machine patterns
3386 to use this addressing more where permitted by the architecture,
3387 it has only been implemented for "common" cases: SImode, HImode, and
3388 QImode operands, and only for the principle operations that would
3389 require this addressing mode: data movement and simple integer operations.
3391 In parallel with these new predicates, two new constraint letters
3392 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3393 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3394 In the pcrel case 's' is only valid in combination with 'a' registers.
3395 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3396 of how these constraints are used.
3398 The use of these predicates is strictly optional, though patterns that
3399 don't will cause an extra reload register to be allocated where one
3402 lea (abc:w,%pc),%a0 ; need to reload address
3403 moveq &1,%d1 ; since write to pc-relative space
3404 movel %d1,%a0@ ; is not allowed
3406 lea (abc:w,%pc),%a1 ; no need to reload address here
3407 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3409 For more info, consult tiemann@cygnus.com.
3412 All of the ugliness with predicates and constraints is due to the
3413 simple fact that the m68k does not allow a pc-relative addressing
3414 mode as a destination. gcc does not distinguish between source and
3415 destination addresses. Hence, if we claim that pc-relative address
3416 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3417 end up with invalid code. To get around this problem, we left
3418 pc-relative modes as invalid addresses, and then added special
3419 predicates and constraints to accept them.
3421 A cleaner way to handle this is to modify gcc to distinguish
3422 between source and destination addresses. We can then say that
3423 pc-relative is a valid source address but not a valid destination
3424 address, and hopefully avoid a lot of the predicate and constraint
3425 hackery. Unfortunately, this would be a pretty big change. It would
3426 be a useful change for a number of ports, but there aren't any current
3427 plans to undertake this.
3429 ***************************************************************************/
3432 /* Special case of a general operand that's used as a source operand.
3433 Use this to permit reads from PC-relative memory when -mpcrel
3437 general_src_operand (rtx op
, enum machine_mode mode
)
3440 && GET_CODE (op
) == MEM
3441 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3442 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3443 || GET_CODE (XEXP (op
, 0)) == CONST
))
3445 return general_operand (op
, mode
);
3448 /* Special case of a nonimmediate operand that's used as a source.
3449 Use this to permit reads from PC-relative memory when -mpcrel
3453 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3455 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3456 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3457 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3458 || GET_CODE (XEXP (op
, 0)) == CONST
))
3460 return nonimmediate_operand (op
, mode
);
3463 /* Special case of a memory operand that's used as a source.
3464 Use this to permit reads from PC-relative memory when -mpcrel
3468 memory_src_operand (rtx op
, enum machine_mode mode
)
3470 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3471 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3472 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3473 || GET_CODE (XEXP (op
, 0)) == CONST
))
3475 return memory_operand (op
, mode
);
3478 /* Predicate that accepts only a pc-relative address. This is needed
3479 because pc-relative addresses don't satisfy the predicate
3480 "general_src_operand". */
3483 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3485 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3486 || GET_CODE (op
) == CONST
);
3490 output_andsi3 (rtx
*operands
)
3493 if (GET_CODE (operands
[2]) == CONST_INT
3494 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3495 && (DATA_REG_P (operands
[0])
3496 || offsettable_memref_p (operands
[0]))
3497 && !TARGET_COLDFIRE
)
3499 if (GET_CODE (operands
[0]) != REG
)
3500 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3501 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3502 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3504 if (operands
[2] == const0_rtx
)
3506 return "and%.w %2,%0";
3508 if (GET_CODE (operands
[2]) == CONST_INT
3509 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3510 && (DATA_REG_P (operands
[0])
3511 || offsettable_memref_p (operands
[0])))
3513 if (DATA_REG_P (operands
[0]))
3515 operands
[1] = GEN_INT (logval
);
3519 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3520 operands
[1] = GEN_INT (logval
% 8);
3522 /* This does not set condition codes in a standard way. */
3524 return "bclr %1,%0";
3526 return "and%.l %2,%0";
3530 output_iorsi3 (rtx
*operands
)
3532 register int logval
;
3533 if (GET_CODE (operands
[2]) == CONST_INT
3534 && INTVAL (operands
[2]) >> 16 == 0
3535 && (DATA_REG_P (operands
[0])
3536 || offsettable_memref_p (operands
[0]))
3537 && !TARGET_COLDFIRE
)
3539 if (GET_CODE (operands
[0]) != REG
)
3540 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3541 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3543 if (INTVAL (operands
[2]) == 0xffff)
3544 return "mov%.w %2,%0";
3545 return "or%.w %2,%0";
3547 if (GET_CODE (operands
[2]) == CONST_INT
3548 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3549 && (DATA_REG_P (operands
[0])
3550 || offsettable_memref_p (operands
[0])))
3552 if (DATA_REG_P (operands
[0]))
3553 operands
[1] = GEN_INT (logval
);
3556 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3557 operands
[1] = GEN_INT (logval
% 8);
3560 return "bset %1,%0";
3562 return "or%.l %2,%0";
3566 output_xorsi3 (rtx
*operands
)
3568 register int logval
;
3569 if (GET_CODE (operands
[2]) == CONST_INT
3570 && INTVAL (operands
[2]) >> 16 == 0
3571 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3572 && !TARGET_COLDFIRE
)
3574 if (! DATA_REG_P (operands
[0]))
3575 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3576 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3578 if (INTVAL (operands
[2]) == 0xffff)
3580 return "eor%.w %2,%0";
3582 if (GET_CODE (operands
[2]) == CONST_INT
3583 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3584 && (DATA_REG_P (operands
[0])
3585 || offsettable_memref_p (operands
[0])))
3587 if (DATA_REG_P (operands
[0]))
3588 operands
[1] = GEN_INT (logval
);
3591 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3592 operands
[1] = GEN_INT (logval
% 8);
3595 return "bchg %1,%0";
3597 return "eor%.l %2,%0";
3600 #ifdef M68K_TARGET_COFF
3602 /* Output assembly to switch to section NAME with attribute FLAGS. */
3605 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3609 if (flags
& SECTION_WRITE
)
3614 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3617 #endif /* M68K_TARGET_COFF */
3621 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3622 unsigned long labelno
)
3624 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3625 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3627 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3631 m68k_hp320_file_start (void)
3633 /* version 1: 68010.
3634 2: 68020 without FPU.
3635 3: 68020 with FPU. */
3636 fprintf (asm_out_file
, "\tversion %d\n",
3637 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3642 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3643 HOST_WIDE_INT delta
,
3644 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3650 if (delta
> 0 && delta
<= 8)
3652 asm_fprintf (file
, "\taddq.l %I%d,4(%Rsp)\n", (int) delta
);
3654 asm_fprintf (file
, "\taddql %I%d,%Rsp@(4)\n", (int) delta
);
3656 else if (delta
< 0 && delta
>= -8)
3658 asm_fprintf (file
, "\tsubq.l %I%d,4(%Rsp)\n", (int) -delta
);
3660 asm_fprintf (file
, "\tsubql %I%d,%Rsp@(4)\n", (int) -delta
);
3664 asm_fprintf (file
, "\tadd.l %I%wd,4(%Rsp)\n", delta
);
3666 asm_fprintf (file
, "\taddl %I%wd,%Rsp@(4)\n", delta
);
3669 xops
[0] = DECL_RTL (function
);
3671 /* Logic taken from call patterns in m68k.md. */
3676 else if ((flag_pic
== 1) || TARGET_68020
)
3683 fmt
= "bra.l %0@PLTPC";
3685 fmt
= "bra %0@PLTPC";
3696 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3697 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3699 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3703 #if defined (MOTOROLA) && !defined (USE_GAS)
3710 output_asm_insn (fmt
, xops
);