1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
38 /* Needed for use_return_insn. */
41 #ifdef SUPPORT_SUN_FPA
43 /* Index into this array by (register number >> 3) to find the
44 smallest class which contains that register. */
45 enum reg_class regno_reg_class
[]
46 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
47 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
49 #endif /* defined SUPPORT_SUN_FPA */
51 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
52 if SGS_SWITCH_TABLE. */
53 int switch_table_difference_label_flag
;
55 static rtx
find_addr_reg ();
56 rtx
legitimize_pic_address ();
57 void print_operand_address ();
60 /* Alignment to use for loops and jumps */
61 /* Specify power of two alignment used for loops. */
62 const char *m68k_align_loops_string
;
63 /* Specify power of two alignment used for non-loop jumps. */
64 const char *m68k_align_jumps_string
;
65 /* Specify power of two alignment used for functions. */
66 const char *m68k_align_funcs_string
;
68 /* Specify power of two alignment used for loops. */
70 /* Specify power of two alignment used for non-loop jumps. */
72 /* Specify power of two alignment used for functions. */
75 /* Nonzero if the last compare/test insn had FP operands. The
76 sCC expanders peek at this to determine what to do for the
77 68060, which has no fsCC instructions. */
78 int m68k_last_compare_had_fp_operands
;
80 /* Sometimes certain combinations of command options do not make
81 sense on a particular target machine. You can define a macro
82 `OVERRIDE_OPTIONS' to take account of this. This macro, if
83 defined, is executed once just after all the command options have
86 Don't use this macro to turn on various extra optimizations for
87 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
96 /* Validate -malign-loops= value, or provide default */
97 if (m68k_align_loops_string
)
99 m68k_align_loops
= atoi (m68k_align_loops_string
);
100 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
101 fatal ("-malign-loops=%d is not between 1 and %d",
102 m68k_align_loops
, MAX_CODE_ALIGN
);
105 m68k_align_loops
= def_align
;
107 /* Validate -malign-jumps= value, or provide default */
108 if (m68k_align_jumps_string
)
110 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
111 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
112 fatal ("-malign-jumps=%d is not between 1 and %d",
113 m68k_align_jumps
, MAX_CODE_ALIGN
);
116 m68k_align_jumps
= def_align
;
118 /* Validate -malign-functions= value, or provide default */
119 if (m68k_align_funcs_string
)
121 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
122 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
123 fatal ("-malign-functions=%d is not between 1 and %d",
124 m68k_align_funcs
, MAX_CODE_ALIGN
);
127 m68k_align_funcs
= def_align
;
130 /* This function generates the assembly code for function entry.
131 STREAM is a stdio stream to output the code to.
132 SIZE is an int: how many units of temporary storage to allocate.
133 Refer to the array `regs_ever_live' to determine which registers
134 to save; `regs_ever_live[I]' is nonzero if register number I
135 is ever used in the function. This function is responsible for
136 knowing which registers should not be saved even if used. */
139 /* Note that the order of the bit mask for fmovem is the opposite
140 of the order for movem! */
144 output_function_prologue (stream
, size
)
149 register int mask
= 0;
150 int num_saved_regs
= 0;
151 extern char call_used_regs
[];
152 int fsize
= (size
+ 3) & -4;
153 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
156 if (frame_pointer_needed
)
158 if (fsize
== 0 && TARGET_68040
)
160 /* on the 68040, pea + move is faster than link.w 0 */
162 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
163 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
164 reg_names
[FRAME_POINTER_REGNUM
]);
166 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
167 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
168 reg_names
[FRAME_POINTER_REGNUM
]);
171 else if (fsize
< 0x8000)
174 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
175 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
177 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
178 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
181 else if (TARGET_68020
)
184 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
185 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
187 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
188 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
193 /* Adding negative number is faster on the 68040. */
195 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
196 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
198 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
199 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 if (dwarf2out_do_frame ())
205 l
= (char *) dwarf2out_cfi_label ();
206 cfa_store_offset
+= 4;
207 cfa_offset
= cfa_store_offset
;
208 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
209 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
210 cfa_store_offset
+= fsize
;
215 if (fsize
+ 4 < 0x8000)
222 /* asm_fprintf() cannot handle %. */
224 asm_fprintf (stream
, "\tsubq.w %0I%d,%Rsp\n", fsize
+ 4);
226 asm_fprintf (stream
, "\tsubqw %0I%d,%Rsp\n", fsize
+ 4);
231 /* asm_fprintf() cannot handle %. */
233 asm_fprintf (stream
, "\tsubq.l %0I%d,%Rsp\n", fsize
+ 4);
235 asm_fprintf (stream
, "\tsubql %0I%d,%Rsp\n", fsize
+ 4);
239 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
241 /* On the CPU32 it is faster to use two subqw instructions to
242 subtract a small integer (8 < N <= 16) to a register. */
243 /* asm_fprintf() cannot handle %. */
245 asm_fprintf (stream
, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
248 asm_fprintf (stream
, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
253 #endif /* not NO_ADDSUB_Q */
256 /* Adding negative number is faster on the 68040. */
257 /* asm_fprintf() cannot handle %. */
259 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
261 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
267 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
269 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
275 /* asm_fprintf() cannot handle %. */
277 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
279 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
282 if (dwarf2out_do_frame ())
284 cfa_store_offset
+= fsize
;
285 cfa_offset
= cfa_store_offset
;
286 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
289 #ifdef SUPPORT_SUN_FPA
290 for (regno
= 24; regno
< 56; regno
++)
291 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
294 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
297 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
300 if (dwarf2out_do_frame ())
302 char *l
= dwarf2out_cfi_label ();
304 cfa_store_offset
+= 8;
305 if (! frame_pointer_needed
)
307 cfa_offset
= cfa_store_offset
;
308 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
310 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
316 for (regno
= 16; regno
< 24; regno
++)
317 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
319 mask
|= 1 << (regno
- 16);
322 if ((mask
& 0xff) != 0)
325 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
327 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
329 if (dwarf2out_do_frame ())
331 char *l
= (char *) dwarf2out_cfi_label ();
334 cfa_store_offset
+= num_saved_regs
* 12;
335 if (! frame_pointer_needed
)
337 cfa_offset
= cfa_store_offset
;
338 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
340 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
341 if (mask
& (1 << (regno
- 16)))
342 dwarf2out_reg_save (l
, regno
,
343 -cfa_store_offset
+ n_regs
++ * 12);
349 for (regno
= 0; regno
< 16; regno
++)
350 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
352 mask
|= 1 << (15 - regno
);
355 if (frame_pointer_needed
)
357 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
360 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
362 mask
|= 1 << (15 - PIC_OFFSET_TABLE_REGNUM
);
369 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
371 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
374 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
378 if (num_saved_regs
<= 2)
380 /* Store each separately in the same order moveml uses.
381 Using two movel instructions instead of a single moveml
382 is about 15% faster for the 68020 and 68030 at no expense
387 /* Undo the work from above. */
388 for (i
= 0; i
< 16; i
++)
393 "\t%Omove.l %s,-(%Rsp)\n",
395 "\tmovel %s,%Rsp@-\n",
398 if (dwarf2out_do_frame ())
400 char *l
= (char *) dwarf2out_cfi_label ();
402 cfa_store_offset
+= 4;
403 if (! frame_pointer_needed
)
405 cfa_offset
= cfa_store_offset
;
406 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
408 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
416 /* The coldfire does not support the predecrement form of the
417 movml instruction, so we must adjust the stack pointer and
418 then use the plain address register indirect mode. We also
419 have to invert the register save mask to use the new mode.
421 FIXME: if num_saved_regs was calculated earlier, we could
422 combine the stack pointer adjustment with any adjustment
423 done when the initial stack frame is created. This would
424 save an instruction */
429 for (i
= 0; i
< 16; i
++)
431 newmask
|= (1 << (15-i
));
434 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
435 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
437 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
438 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
444 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
446 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
449 if (dwarf2out_do_frame ())
451 char *l
= (char *) dwarf2out_cfi_label ();
454 cfa_store_offset
+= num_saved_regs
* 4;
455 if (! frame_pointer_needed
)
457 cfa_offset
= cfa_store_offset
;
458 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
460 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
461 if (mask
& (1 << (15 - regno
)))
462 dwarf2out_reg_save (l
, regno
,
463 -cfa_store_offset
+ n_regs
++ * 4);
466 if (flag_pic
&& current_function_uses_pic_offset_table
)
469 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
470 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
472 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
473 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
474 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
475 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
476 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
481 /* Return true if this function's epilogue can be output as RTL. */
488 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
491 /* Copied from output_function_epilogue (). We should probably create a
492 separate layout routine to perform the common work. */
494 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
495 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
501 /* This function generates the assembly code for function exit,
502 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
504 The function epilogue should not depend on the current stack pointer!
505 It should use the frame pointer only, if there is a frame pointer.
506 This is mandatory because of alloca; we also take advantage of it to
507 omit stack adjustments before returning. */
510 output_function_epilogue (stream
, size
)
515 register int mask
, fmask
;
517 int offset
, foffset
, fpoffset
;
518 extern char call_used_regs
[];
519 int fsize
= (size
+ 3) & -4;
521 rtx insn
= get_last_insn ();
522 int restore_from_sp
= 0;
524 /* If the last insn was a BARRIER, we don't have to write any code. */
525 if (GET_CODE (insn
) == NOTE
)
526 insn
= prev_nonnote_insn (insn
);
527 if (insn
&& GET_CODE (insn
) == BARRIER
)
529 /* Output just a no-op so that debuggers don't get confused
530 about which function the pc is in at this address. */
531 asm_fprintf (stream
, "\tnop\n");
535 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
536 if (profile_block_flag
== 2)
538 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
542 #ifdef FUNCTION_EXTRA_EPILOGUE
543 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
545 nregs
= 0; fmask
= 0; fpoffset
= 0;
546 #ifdef SUPPORT_SUN_FPA
547 for (regno
= 24 ; regno
< 56 ; regno
++)
548 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
550 fpoffset
= nregs
* 8;
555 for (regno
= 16; regno
< 24; regno
++)
556 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
559 fmask
|= 1 << (23 - regno
);
562 foffset
= fpoffset
+ nregs
* 12;
564 if (frame_pointer_needed
)
565 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
566 for (regno
= 0; regno
< 16; regno
++)
567 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
572 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
575 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
577 offset
= foffset
+ nregs
* 4;
578 /* FIXME : leaf_function_p below is too strong.
579 What we really need to know there is if there could be pending
580 stack adjustment needed at that point. */
581 restore_from_sp
= ! frame_pointer_needed
582 || (! current_function_calls_alloca
&& leaf_function_p ());
583 if (offset
+ fsize
>= 0x8000
585 && (mask
|| fmask
|| fpoffset
))
588 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
590 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
594 if (TARGET_5200
|| nregs
<= 2)
596 /* Restore each separately in the same order moveml does.
597 Using two movel instructions instead of a single moveml
598 is about 15% faster for the 68020 and 68030 at no expense
603 /* Undo the work from above. */
604 for (i
= 0; i
< 16; i
++)
610 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
612 reg_names
[FRAME_POINTER_REGNUM
],
615 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
616 reg_names
[FRAME_POINTER_REGNUM
],
617 offset
+ fsize
, reg_names
[i
]);
620 else if (restore_from_sp
)
623 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
626 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
633 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
635 reg_names
[FRAME_POINTER_REGNUM
],
638 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
639 reg_names
[FRAME_POINTER_REGNUM
],
640 offset
+ fsize
, reg_names
[i
]);
651 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
653 reg_names
[FRAME_POINTER_REGNUM
],
656 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
657 reg_names
[FRAME_POINTER_REGNUM
],
658 offset
+ fsize
, mask
);
661 else if (restore_from_sp
)
664 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
666 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
672 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
674 reg_names
[FRAME_POINTER_REGNUM
],
677 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
678 reg_names
[FRAME_POINTER_REGNUM
],
679 offset
+ fsize
, mask
);
688 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
690 reg_names
[FRAME_POINTER_REGNUM
],
693 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
694 reg_names
[FRAME_POINTER_REGNUM
],
695 foffset
+ fsize
, fmask
);
698 else if (restore_from_sp
)
701 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
703 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
709 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
711 reg_names
[FRAME_POINTER_REGNUM
],
714 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
715 reg_names
[FRAME_POINTER_REGNUM
],
716 foffset
+ fsize
, fmask
);
721 for (regno
= 55; regno
>= 24; regno
--)
722 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
727 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
729 reg_names
[FRAME_POINTER_REGNUM
],
732 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
733 reg_names
[FRAME_POINTER_REGNUM
],
734 fpoffset
+ fsize
, reg_names
[regno
]);
737 else if (restore_from_sp
)
740 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
743 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
750 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
752 reg_names
[FRAME_POINTER_REGNUM
],
755 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
756 reg_names
[FRAME_POINTER_REGNUM
],
757 fpoffset
+ fsize
, reg_names
[regno
]);
762 if (frame_pointer_needed
)
763 fprintf (stream
, "\tunlk %s\n",
764 reg_names
[FRAME_POINTER_REGNUM
]);
773 asm_fprintf (stream
, "\taddq.w %0I%d,%Rsp\n", fsize
+ 4);
775 asm_fprintf (stream
, "\taddqw %0I%d,%Rsp\n", fsize
+ 4);
781 asm_fprintf (stream
, "\taddq.l %0I%d,%Rsp\n", fsize
+ 4);
783 asm_fprintf (stream
, "\taddql %0I%d,%Rsp\n", fsize
+ 4);
787 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
789 /* On the CPU32 it is faster to use two addqw instructions to
790 add a small integer (8 < N <= 16) to a register. */
791 /* asm_fprintf() cannot handle %. */
793 asm_fprintf (stream
, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
796 asm_fprintf (stream
, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
801 #endif /* not NO_ADDSUB_Q */
802 if (fsize
+ 4 < 0x8000)
806 /* asm_fprintf() cannot handle %. */
808 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
810 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
816 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
818 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
824 /* asm_fprintf() cannot handle %. */
826 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
828 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
832 if (current_function_pops_args
)
833 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
835 fprintf (stream
, "\trts\n");
838 /* Similar to general_operand, but exclude stack_pointer_rtx. */
841 not_sp_operand (op
, mode
)
843 enum machine_mode mode
;
845 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
848 /* Return TRUE if X is a valid comparison operator for the dbcc
851 Note it rejects floating point comparison operators.
852 (In the future we could use Fdbcc).
854 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
857 valid_dbcc_comparison_p (x
, mode
)
859 enum machine_mode mode ATTRIBUTE_UNUSED
;
861 switch (GET_CODE (x
))
863 case EQ
: case NE
: case GTU
: case LTU
:
867 /* Reject some when CC_NO_OVERFLOW is set. This may be over
869 case GT
: case LT
: case GE
: case LE
:
870 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
876 /* Return non-zero if flags are currently in the 68881 flag register. */
880 /* We could add support for these in the future */
881 return cc_status
.flags
& CC_IN_68881
;
884 /* Output a dbCC; jCC sequence. Note we do not handle the
885 floating point version of this sequence (Fdbcc). We also
886 do not handle alternative conditions when CC_NO_OVERFLOW is
887 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
888 kick those out before we get here. */
891 output_dbcc_and_branch (operands
)
894 switch (GET_CODE (operands
[3]))
898 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
900 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
906 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
908 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
914 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
916 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
922 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
924 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
930 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
932 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
938 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
940 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
946 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
948 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
954 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
956 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
962 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
964 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
970 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
972 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
980 /* If the decrement is to be done in SImode, then we have
981 to compensate for the fact that dbcc decrements in HImode. */
982 switch (GET_MODE (operands
[0]))
986 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
988 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1001 output_scc_di(op
, operand1
, operand2
, dest
)
1008 enum rtx_code op_code
= GET_CODE (op
);
1010 /* This does not produce a usefull cc. */
1013 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1014 below. Swap the operands and change the op if these requirements
1015 are not fulfilled. */
1016 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1020 operand1
= operand2
;
1022 op_code
= swap_condition (op_code
);
1024 loperands
[0] = operand1
;
1025 if (GET_CODE (operand1
) == REG
)
1026 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1028 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1029 if (operand2
!= const0_rtx
)
1031 loperands
[2] = operand2
;
1032 if (GET_CODE (operand2
) == REG
)
1033 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1035 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1037 loperands
[4] = gen_label_rtx();
1038 if (operand2
!= const0_rtx
)
1041 #ifdef SGS_CMP_ORDER
1042 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1044 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1047 #ifdef SGS_CMP_ORDER
1048 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1050 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1056 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1057 output_asm_insn ("tst%.l %0", loperands
);
1060 #ifdef SGS_CMP_ORDER
1061 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1063 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1068 output_asm_insn ("jbne %l4", loperands
);
1070 output_asm_insn ("jne %l4", loperands
);
1073 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1074 output_asm_insn ("tst%.l %1", loperands
);
1077 #ifdef SGS_CMP_ORDER
1078 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1080 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1085 loperands
[5] = dest
;
1090 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1091 CODE_LABEL_NUMBER (loperands
[4]));
1092 output_asm_insn ("seq %5", loperands
);
1096 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1097 CODE_LABEL_NUMBER (loperands
[4]));
1098 output_asm_insn ("sne %5", loperands
);
1102 loperands
[6] = gen_label_rtx();
1104 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1106 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1108 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1109 CODE_LABEL_NUMBER (loperands
[4]));
1110 output_asm_insn ("sgt %5", loperands
);
1111 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1112 CODE_LABEL_NUMBER (loperands
[6]));
1116 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1117 CODE_LABEL_NUMBER (loperands
[4]));
1118 output_asm_insn ("shi %5", loperands
);
1122 loperands
[6] = gen_label_rtx();
1124 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1126 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1128 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1129 CODE_LABEL_NUMBER (loperands
[4]));
1130 output_asm_insn ("slt %5", loperands
);
1131 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1132 CODE_LABEL_NUMBER (loperands
[6]));
1136 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1137 CODE_LABEL_NUMBER (loperands
[4]));
1138 output_asm_insn ("scs %5", loperands
);
1142 loperands
[6] = gen_label_rtx();
1144 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1146 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1148 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1149 CODE_LABEL_NUMBER (loperands
[4]));
1150 output_asm_insn ("sge %5", loperands
);
1151 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1152 CODE_LABEL_NUMBER (loperands
[6]));
1156 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1157 CODE_LABEL_NUMBER (loperands
[4]));
1158 output_asm_insn ("scc %5", loperands
);
1162 loperands
[6] = gen_label_rtx();
1164 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1166 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1168 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1169 CODE_LABEL_NUMBER (loperands
[4]));
1170 output_asm_insn ("sle %5", loperands
);
1171 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1172 CODE_LABEL_NUMBER (loperands
[6]));
1176 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1177 CODE_LABEL_NUMBER (loperands
[4]));
1178 output_asm_insn ("sls %5", loperands
);
1188 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1190 rtx countop
, dataop
;
1194 operands
[0] = countop
;
1195 operands
[1] = dataop
;
1197 if (GET_CODE (countop
) == CONST_INT
)
1199 register int count
= INTVAL (countop
);
1200 /* If COUNT is bigger than size of storage unit in use,
1201 advance to the containing unit of same size. */
1202 if (count
> signpos
)
1204 int offset
= (count
& ~signpos
) / 8;
1205 count
= count
& signpos
;
1206 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1208 if (count
== signpos
)
1209 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1211 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1213 /* These three statements used to use next_insns_test_no...
1214 but it appears that this should do the same job. */
1216 && next_insn_tests_no_inequality (insn
))
1219 && next_insn_tests_no_inequality (insn
))
1222 && next_insn_tests_no_inequality (insn
))
1225 cc_status
.flags
= CC_NOT_NEGATIVE
;
1227 return "btst %0,%1";
1230 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1231 reference and a constant. */
1234 symbolic_operand (op
, mode
)
1236 enum machine_mode mode ATTRIBUTE_UNUSED
;
1238 switch (GET_CODE (op
))
1246 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1247 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1248 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1250 #if 0 /* Deleted, with corresponding change in m68k.h,
1251 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1253 return GET_MODE (op
) == mode
;
1261 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1264 extend_operator(x
, mode
)
1266 enum machine_mode mode
;
1268 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1270 switch (GET_CODE(x
))
1281 /* Legitimize PIC addresses. If the address is already
1282 position-independent, we return ORIG. Newly generated
1283 position-independent addresses go to REG. If we need more
1284 than one register, we lose.
1286 An address is legitimized by making an indirect reference
1287 through the Global Offset Table with the name of the symbol
1290 The assembler and linker are responsible for placing the
1291 address of the symbol in the GOT. The function prologue
1292 is responsible for initializing a5 to the starting address
1295 The assembler is also responsible for translating a symbol name
1296 into a constant displacement from the start of the GOT.
1298 A quick example may make things a little clearer:
1300 When not generating PIC code to store the value 12345 into _foo
1301 we would generate the following code:
1305 When generating PIC two transformations are made. First, the compiler
1306 loads the address of foo into a register. So the first transformation makes:
1311 The code in movsi will intercept the lea instruction and call this
1312 routine which will transform the instructions into:
1314 movel a5@(_foo:w), a0
1318 That (in a nutshell) is how *all* symbol and label references are
1322 legitimize_pic_address (orig
, mode
, reg
)
1324 enum machine_mode mode ATTRIBUTE_UNUSED
;
1328 /* First handle a simple SYMBOL_REF or LABEL_REF */
1329 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1334 pic_ref
= gen_rtx_MEM (Pmode
,
1335 gen_rtx_PLUS (Pmode
,
1336 pic_offset_table_rtx
, orig
));
1337 current_function_uses_pic_offset_table
= 1;
1338 if (reload_in_progress
)
1339 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1340 RTX_UNCHANGING_P (pic_ref
) = 1;
1341 emit_move_insn (reg
, pic_ref
);
1344 else if (GET_CODE (orig
) == CONST
)
1348 /* Make sure this is CONST has not already been legitimized */
1349 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1350 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1356 /* legitimize both operands of the PLUS */
1357 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1359 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1360 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1361 base
== reg
? 0 : reg
);
1365 if (GET_CODE (orig
) == CONST_INT
)
1366 return plus_constant_for_output (base
, INTVAL (orig
));
1367 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1368 /* Likewise, should we set special REG_NOTEs here? */
1374 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1376 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1379 const_method (constant
)
1385 i
= INTVAL (constant
);
1389 /* The Coldfire doesn't have byte or word operations. */
1390 /* FIXME: This may not be useful for the m68060 either */
1393 /* if -256 < N < 256 but N is not in range for a moveq
1394 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1395 if (USE_MOVQ (i
^ 0xff))
1397 /* Likewise, try with not.w */
1398 if (USE_MOVQ (i
^ 0xffff))
1400 /* This is the only value where neg.w is useful */
1403 /* Try also with swap */
1405 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1408 /* Otherwise, use move.l */
1413 const_int_cost (constant
)
1416 switch (const_method (constant
))
1419 /* Constants between -128 and 127 are cheap due to moveq */
1425 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1435 output_move_const_into_data_reg (operands
)
1440 i
= INTVAL (operands
[1]);
1441 switch (const_method (operands
[1]))
1444 #if defined (MOTOROLA) && !defined (CRDS)
1445 return "moveq%.l %1,%0";
1447 return "moveq %1,%0";
1450 operands
[1] = GEN_INT (i
^ 0xff);
1451 #if defined (MOTOROLA) && !defined (CRDS)
1452 return "moveq%.l %1,%0\n\tnot%.b %0";
1454 return "moveq %1,%0\n\tnot%.b %0";
1457 operands
[1] = GEN_INT (i
^ 0xffff);
1458 #if defined (MOTOROLA) && !defined (CRDS)
1459 return "moveq%.l %1,%0\n\tnot%.w %0";
1461 return "moveq %1,%0\n\tnot%.w %0";
1464 #if defined (MOTOROLA) && !defined (CRDS)
1465 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1467 return "moveq %#-128,%0\n\tneg%.w %0";
1473 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1474 #if defined (MOTOROLA) && !defined (CRDS)
1475 return "moveq%.l %1,%0\n\tswap %0";
1477 return "moveq %1,%0\n\tswap %0";
1481 return "move%.l %1,%0";
1488 output_move_simode_const (operands
)
1491 if (operands
[1] == const0_rtx
1492 && (DATA_REG_P (operands
[0])
1493 || GET_CODE (operands
[0]) == MEM
)
1494 /* clr insns on 68000 read before writing.
1495 This isn't so on the 68010, but we have no TARGET_68010. */
1496 && ((TARGET_68020
|| TARGET_5200
)
1497 || !(GET_CODE (operands
[0]) == MEM
1498 && MEM_VOLATILE_P (operands
[0]))))
1500 else if (operands
[1] == const0_rtx
1501 && ADDRESS_REG_P (operands
[0]))
1502 return "sub%.l %0,%0";
1503 else if (DATA_REG_P (operands
[0]))
1504 return output_move_const_into_data_reg (operands
);
1505 else if (ADDRESS_REG_P (operands
[0])
1506 && INTVAL (operands
[1]) < 0x8000
1507 && INTVAL (operands
[1]) >= -0x8000)
1508 return "move%.w %1,%0";
1509 else if (GET_CODE (operands
[0]) == MEM
1510 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1511 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1512 && INTVAL (operands
[1]) < 0x8000
1513 && INTVAL (operands
[1]) >= -0x8000)
1515 return "move%.l %1,%0";
1519 output_move_simode (operands
)
1522 if (GET_CODE (operands
[1]) == CONST_INT
)
1523 return output_move_simode_const (operands
);
1524 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1525 || GET_CODE (operands
[1]) == CONST
)
1526 && push_operand (operands
[0], SImode
))
1528 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1529 || GET_CODE (operands
[1]) == CONST
)
1530 && ADDRESS_REG_P (operands
[0]))
1531 return "lea %a1,%0";
1532 return "move%.l %1,%0";
1536 output_move_himode (operands
)
1539 if (GET_CODE (operands
[1]) == CONST_INT
)
1541 if (operands
[1] == const0_rtx
1542 && (DATA_REG_P (operands
[0])
1543 || GET_CODE (operands
[0]) == MEM
)
1544 /* clr insns on 68000 read before writing.
1545 This isn't so on the 68010, but we have no TARGET_68010. */
1546 && ((TARGET_68020
|| TARGET_5200
)
1547 || !(GET_CODE (operands
[0]) == MEM
1548 && MEM_VOLATILE_P (operands
[0]))))
1550 else if (operands
[1] == const0_rtx
1551 && ADDRESS_REG_P (operands
[0]))
1552 return "sub%.l %0,%0";
1553 else if (DATA_REG_P (operands
[0])
1554 && INTVAL (operands
[1]) < 128
1555 && INTVAL (operands
[1]) >= -128)
1557 #if defined(MOTOROLA) && !defined(CRDS)
1558 return "moveq%.l %1,%0";
1560 return "moveq %1,%0";
1563 else if (INTVAL (operands
[1]) < 0x8000
1564 && INTVAL (operands
[1]) >= -0x8000)
1565 return "move%.w %1,%0";
1567 else if (CONSTANT_P (operands
[1]))
1568 return "move%.l %1,%0";
1570 /* Recognize the insn before a tablejump, one that refers
1571 to a table of offsets. Such an insn will need to refer
1572 to a label on the insn. So output one. Use the label-number
1573 of the table of offsets to generate this label. This code,
1574 and similar code below, assumes that there will be at most one
1575 reference to each table. */
1576 if (GET_CODE (operands
[1]) == MEM
1577 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1578 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1579 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1581 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1582 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1584 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1585 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1587 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1588 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1589 #endif /* not SGS */
1590 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1591 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1592 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1593 #ifdef SGS_SWITCH_TABLES
1594 /* Set flag saying we need to define the symbol
1595 LD%n (with value L%n-LI%n) at the end of the switch table. */
1596 switch_table_difference_label_flag
= 1;
1597 #endif /* SGS_SWITCH_TABLES */
1598 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1600 #endif /* SGS_NO_LI */
1601 return "move%.w %1,%0";
1605 output_move_qimode (operands
)
1610 /* This is probably useless, since it loses for pushing a struct
1611 of several bytes a byte at a time. */
1612 /* 68k family always modifies the stack pointer by at least 2, even for
1613 byte pushes. The 5200 (coldfire) does not do this. */
1614 if (GET_CODE (operands
[0]) == MEM
1615 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1616 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1617 && ! ADDRESS_REG_P (operands
[1])
1620 xoperands
[1] = operands
[1];
1622 = gen_rtx_MEM (QImode
,
1623 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1624 /* Just pushing a byte puts it in the high byte of the halfword. */
1625 /* We must put it in the low-order, high-numbered byte. */
1626 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1628 xoperands
[3] = stack_pointer_rtx
;
1630 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1632 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1636 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1640 /* clr and st insns on 68000 read before writing.
1641 This isn't so on the 68010, but we have no TARGET_68010. */
1642 if (!ADDRESS_REG_P (operands
[0])
1643 && ((TARGET_68020
|| TARGET_5200
)
1644 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1646 if (operands
[1] == const0_rtx
)
1648 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1649 && GET_CODE (operands
[1]) == CONST_INT
1650 && (INTVAL (operands
[1]) & 255) == 255)
1656 if (GET_CODE (operands
[1]) == CONST_INT
1657 && DATA_REG_P (operands
[0])
1658 && INTVAL (operands
[1]) < 128
1659 && INTVAL (operands
[1]) >= -128)
1661 #if defined(MOTOROLA) && !defined(CRDS)
1662 return "moveq%.l %1,%0";
1664 return "moveq %1,%0";
1667 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1668 return "sub%.l %0,%0";
1669 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1670 return "move%.l %1,%0";
1671 /* 68k family (including the 5200 coldfire) does not support byte moves to
1672 from address registers. */
1673 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1674 return "move%.w %1,%0";
1675 return "move%.b %1,%0";
1679 output_move_stricthi (operands
)
1682 if (operands
[1] == const0_rtx
1683 /* clr insns on 68000 read before writing.
1684 This isn't so on the 68010, but we have no TARGET_68010. */
1685 && ((TARGET_68020
|| TARGET_5200
)
1686 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1688 return "move%.w %1,%0";
1692 output_move_strictqi (operands
)
1695 if (operands
[1] == const0_rtx
1696 /* clr insns on 68000 read before writing.
1697 This isn't so on the 68010, but we have no TARGET_68010. */
1698 && ((TARGET_68020
|| TARGET_5200
)
1699 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1701 return "move%.b %1,%0";
1704 /* Return the best assembler insn template
1705 for moving operands[1] into operands[0] as a fullword. */
1708 singlemove_string (operands
)
1711 #ifdef SUPPORT_SUN_FPA
1712 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1713 return "fpmoves %1,%0";
1715 if (GET_CODE (operands
[1]) == CONST_INT
)
1716 return output_move_simode_const (operands
);
1717 return "move%.l %1,%0";
1721 /* Output assembler code to perform a doubleword move insn
1722 with operands OPERANDS. */
1725 output_move_double (operands
)
1730 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1735 rtx addreg0
= 0, addreg1
= 0;
1736 int dest_overlapped_low
= 0;
1737 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1742 /* First classify both operands. */
1744 if (REG_P (operands
[0]))
1746 else if (offsettable_memref_p (operands
[0]))
1748 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1750 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1752 else if (GET_CODE (operands
[0]) == MEM
)
1757 if (REG_P (operands
[1]))
1759 else if (CONSTANT_P (operands
[1]))
1761 else if (offsettable_memref_p (operands
[1]))
1763 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1765 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1767 else if (GET_CODE (operands
[1]) == MEM
)
1772 /* Check for the cases that the operand constraints are not
1773 supposed to allow to happen. Abort if we get one,
1774 because generating code for these cases is painful. */
1776 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1779 /* If one operand is decrementing and one is incrementing
1780 decrement the former register explicitly
1781 and change that operand into ordinary indexing. */
1783 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1785 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1787 output_asm_insn ("sub%.l %#12,%0", operands
);
1789 output_asm_insn ("subq%.l %#8,%0", operands
);
1790 if (GET_MODE (operands
[1]) == XFmode
)
1791 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1792 else if (GET_MODE (operands
[0]) == DFmode
)
1793 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1795 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1798 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1800 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1802 output_asm_insn ("sub%.l %#12,%1", operands
);
1804 output_asm_insn ("subq%.l %#8,%1", operands
);
1805 if (GET_MODE (operands
[1]) == XFmode
)
1806 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1807 else if (GET_MODE (operands
[1]) == DFmode
)
1808 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1810 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1814 /* If an operand is an unoffsettable memory ref, find a register
1815 we can increment temporarily to make it refer to the second word. */
1817 if (optype0
== MEMOP
)
1818 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1820 if (optype1
== MEMOP
)
1821 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1823 /* Ok, we can do one word at a time.
1824 Normally we do the low-numbered word first,
1825 but if either operand is autodecrementing then we
1826 do the high-numbered word first.
1828 In either case, set up in LATEHALF the operands to use
1829 for the high-numbered word and in some cases alter the
1830 operands in OPERANDS to be suitable for the low-numbered word. */
1834 if (optype0
== REGOP
)
1836 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1837 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1839 else if (optype0
== OFFSOP
)
1841 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1842 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1846 middlehalf
[0] = operands
[0];
1847 latehalf
[0] = operands
[0];
1850 if (optype1
== REGOP
)
1852 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1853 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1855 else if (optype1
== OFFSOP
)
1857 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1858 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1860 else if (optype1
== CNSTOP
)
1862 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1867 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1868 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1869 operands
[1] = GEN_INT (l
[0]);
1870 middlehalf
[1] = GEN_INT (l
[1]);
1871 latehalf
[1] = GEN_INT (l
[2]);
1873 else if (CONSTANT_P (operands
[1]))
1875 /* actually, no non-CONST_DOUBLE constant should ever
1878 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1879 latehalf
[1] = constm1_rtx
;
1881 latehalf
[1] = const0_rtx
;
1886 middlehalf
[1] = operands
[1];
1887 latehalf
[1] = operands
[1];
1891 /* size is not 12: */
1893 if (optype0
== REGOP
)
1894 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1895 else if (optype0
== OFFSOP
)
1896 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1898 latehalf
[0] = operands
[0];
1900 if (optype1
== REGOP
)
1901 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1902 else if (optype1
== OFFSOP
)
1903 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1904 else if (optype1
== CNSTOP
)
1905 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1907 latehalf
[1] = operands
[1];
1910 /* If insn is effectively movd N(sp),-(sp) then we will do the
1911 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1912 for the low word as well, to compensate for the first decrement of sp. */
1913 if (optype0
== PUSHOP
1914 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1915 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1916 operands
[1] = middlehalf
[1] = latehalf
[1];
1918 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1919 if the upper part of reg N does not appear in the MEM, arrange to
1920 emit the move late-half first. Otherwise, compute the MEM address
1921 into the upper part of N and use that as a pointer to the memory
1923 if (optype0
== REGOP
1924 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1926 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1928 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1929 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1931 /* If both halves of dest are used in the src memory address,
1932 compute the address into latehalf of dest.
1933 Note that this can't happen if the dest is two data regs. */
1935 xops
[0] = latehalf
[0];
1936 xops
[1] = XEXP (operands
[1], 0);
1937 output_asm_insn ("lea %a1,%0", xops
);
1938 if( GET_MODE (operands
[1]) == XFmode
)
1940 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1941 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1942 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1946 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1947 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1951 && reg_overlap_mentioned_p (middlehalf
[0],
1952 XEXP (operands
[1], 0)))
1954 /* Check for two regs used by both source and dest.
1955 Note that this can't happen if the dest is all data regs.
1956 It can happen if the dest is d6, d7, a0.
1957 But in that case, latehalf is an addr reg, so
1958 the code at compadr does ok. */
1960 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1961 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1964 /* JRV says this can't happen: */
1965 if (addreg0
|| addreg1
)
1968 /* Only the middle reg conflicts; simply put it last. */
1969 output_asm_insn (singlemove_string (operands
), operands
);
1970 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1971 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1974 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1975 /* If the low half of dest is mentioned in the source memory
1976 address, the arrange to emit the move late half first. */
1977 dest_overlapped_low
= 1;
1980 /* If one or both operands autodecrementing,
1981 do the two words, high-numbered first. */
1983 /* Likewise, the first move would clobber the source of the second one,
1984 do them in the other order. This happens only for registers;
1985 such overlap can't happen in memory unless the user explicitly
1986 sets it up, and that is an undefined circumstance. */
1988 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1989 || (optype0
== REGOP
&& optype1
== REGOP
1990 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1991 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1992 || dest_overlapped_low
)
1994 /* Make any unoffsettable addresses point at high-numbered word. */
1998 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2000 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2005 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2007 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2011 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2013 /* Undo the adds we just did. */
2015 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2017 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2021 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2023 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2025 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2028 /* Do low-numbered word. */
2029 return singlemove_string (operands
);
2032 /* Normal case: do the two words, low-numbered first. */
2034 output_asm_insn (singlemove_string (operands
), operands
);
2036 /* Do the middle one of the three words for long double */
2040 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2042 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2044 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2047 /* Make any unoffsettable addresses point at high-numbered word. */
2049 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2051 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2054 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2056 /* Undo the adds we just did. */
2060 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2062 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2067 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2069 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2075 /* Return a REG that occurs in ADDR with coefficient 1.
2076 ADDR can be effectively incremented by incrementing REG. */
2079 find_addr_reg (addr
)
2082 while (GET_CODE (addr
) == PLUS
)
2084 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2085 addr
= XEXP (addr
, 0);
2086 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2087 addr
= XEXP (addr
, 1);
2088 else if (CONSTANT_P (XEXP (addr
, 0)))
2089 addr
= XEXP (addr
, 1);
2090 else if (CONSTANT_P (XEXP (addr
, 1)))
2091 addr
= XEXP (addr
, 0);
2095 if (GET_CODE (addr
) == REG
)
2100 /* Output assembler code to perform a 32 bit 3 operand add. */
2103 output_addsi3 (operands
)
2106 if (! operands_match_p (operands
[0], operands
[1]))
2108 if (!ADDRESS_REG_P (operands
[1]))
2110 rtx tmp
= operands
[1];
2112 operands
[1] = operands
[2];
2116 /* These insns can result from reloads to access
2117 stack slots over 64k from the frame pointer. */
2118 if (GET_CODE (operands
[2]) == CONST_INT
2119 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2120 return "move%.l %2,%0\n\tadd%.l %1,%0";
2122 if (GET_CODE (operands
[2]) == REG
)
2123 return "lea 0(%1,%2.l),%0";
2125 return "lea %c2(%1),%0";
2128 if (GET_CODE (operands
[2]) == REG
)
2129 return "lea (%1,%2.l),%0";
2131 return "lea (%c2,%1),%0";
2132 #else /* not MOTOROLA (MIT syntax) */
2133 if (GET_CODE (operands
[2]) == REG
)
2134 return "lea %1@(0,%2:l),%0";
2136 return "lea %1@(%c2),%0";
2137 #endif /* not MOTOROLA */
2138 #endif /* not SGS */
2140 if (GET_CODE (operands
[2]) == CONST_INT
)
2143 if (INTVAL (operands
[2]) > 0
2144 && INTVAL (operands
[2]) <= 8)
2145 return "addq%.l %2,%0";
2146 if (INTVAL (operands
[2]) < 0
2147 && INTVAL (operands
[2]) >= -8)
2149 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2150 return "subq%.l %2,%0";
2152 /* On the CPU32 it is faster to use two addql instructions to
2153 add a small integer (8 < N <= 16) to a register.
2154 Likewise for subql. */
2155 if (TARGET_CPU32
&& REG_P (operands
[0]))
2157 if (INTVAL (operands
[2]) > 8
2158 && INTVAL (operands
[2]) <= 16)
2160 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2161 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2163 if (INTVAL (operands
[2]) < -8
2164 && INTVAL (operands
[2]) >= -16)
2166 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2167 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2171 if (ADDRESS_REG_P (operands
[0])
2172 && INTVAL (operands
[2]) >= -0x8000
2173 && INTVAL (operands
[2]) < 0x8000)
2176 return "add%.w %2,%0";
2179 return "lea (%c2,%0),%0";
2181 return "lea %0@(%c2),%0";
2185 return "add%.l %2,%0";
2188 /* Store in cc_status the expressions that the condition codes will
2189 describe after execution of an instruction whose pattern is EXP.
2190 Do not alter them if the instruction would not alter the cc's. */
2192 /* On the 68000, all the insns to store in an address register fail to
2193 set the cc's. However, in some cases these instructions can make it
2194 possibly invalid to use the saved cc's. In those cases we clear out
2195 some or all of the saved cc's so they won't be used. */
2198 notice_update_cc (exp
, insn
)
2202 /* If the cc is being set from the fpa and the expression is not an
2203 explicit floating point test instruction (which has code to deal with
2204 this), reinit the CC. */
2205 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2206 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2207 && !(GET_CODE (exp
) == PARALLEL
2208 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2209 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2213 else if (GET_CODE (exp
) == SET
)
2215 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2219 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2221 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2222 cc_status
.value1
= 0;
2223 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2224 cc_status
.value2
= 0;
2226 else if (!FP_REG_P (SET_DEST (exp
))
2227 && SET_DEST (exp
) != cc0_rtx
2228 && (FP_REG_P (SET_SRC (exp
))
2229 || GET_CODE (SET_SRC (exp
)) == FIX
2230 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2231 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2235 /* A pair of move insns doesn't produce a useful overall cc. */
2236 else if (!FP_REG_P (SET_DEST (exp
))
2237 && !FP_REG_P (SET_SRC (exp
))
2238 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2239 && (GET_CODE (SET_SRC (exp
)) == REG
2240 || GET_CODE (SET_SRC (exp
)) == MEM
2241 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2245 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2249 else if (XEXP (exp
, 0) != pc_rtx
)
2251 cc_status
.flags
= 0;
2252 cc_status
.value1
= XEXP (exp
, 0);
2253 cc_status
.value2
= XEXP (exp
, 1);
2256 else if (GET_CODE (exp
) == PARALLEL
2257 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2259 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2261 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2263 cc_status
.flags
= 0;
2264 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2265 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2270 if (cc_status
.value2
!= 0
2271 && ADDRESS_REG_P (cc_status
.value2
)
2272 && GET_MODE (cc_status
.value2
) == QImode
)
2274 if (cc_status
.value2
!= 0
2275 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2276 switch (GET_CODE (cc_status
.value2
))
2278 case PLUS
: case MINUS
: case MULT
:
2279 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2280 #if 0 /* These instructions always clear the overflow bit */
2281 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2282 case ROTATE
: case ROTATERT
:
2284 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2285 cc_status
.flags
|= CC_NO_OVERFLOW
;
2288 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2289 ends with a move insn moving r2 in r2's mode.
2290 Thus, the cc's are set for r2.
2291 This can set N bit spuriously. */
2292 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2297 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2299 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2300 cc_status
.value2
= 0;
2301 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2302 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2303 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2304 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2305 cc_status
.flags
= CC_IN_68881
;
2309 output_move_const_double (operands
)
2312 #ifdef SUPPORT_SUN_FPA
2313 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2315 int code
= standard_sun_fpa_constant_p (operands
[1]);
2319 static char buf
[40];
2321 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2324 return "fpmove%.d %1,%0";
2329 int code
= standard_68881_constant_p (operands
[1]);
2333 static char buf
[40];
2335 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2338 return "fmove%.d %1,%0";
2343 output_move_const_single (operands
)
2346 #ifdef SUPPORT_SUN_FPA
2349 int code
= standard_sun_fpa_constant_p (operands
[1]);
2353 static char buf
[40];
2355 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2358 return "fpmove%.s %1,%0";
2361 #endif /* defined SUPPORT_SUN_FPA */
2363 int code
= standard_68881_constant_p (operands
[1]);
2367 static char buf
[40];
2369 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2372 return "fmove%.s %f1,%0";
2376 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2377 from the "fmovecr" instruction.
2378 The value, anded with 0xff, gives the code to use in fmovecr
2379 to get the desired constant. */
2381 /* This code has been fixed for cross-compilation. */
2383 static int inited_68881_table
= 0;
2385 char *strings_68881
[7] = {
2395 int codes_68881
[7] = {
2405 REAL_VALUE_TYPE values_68881
[7];
2407 /* Set up values_68881 array by converting the decimal values
2408 strings_68881 to binary. */
2415 enum machine_mode mode
;
2418 for (i
= 0; i
< 7; i
++)
2422 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2423 values_68881
[i
] = r
;
2425 inited_68881_table
= 1;
2429 standard_68881_constant_p (x
)
2435 #ifdef NO_ASM_FMOVECR
2439 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2440 used at all on those chips. */
2441 if (TARGET_68040
|| TARGET_68060
)
2444 #ifndef REAL_ARITHMETIC
2445 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2446 if (! flag_pretend_float
)
2451 if (! inited_68881_table
)
2452 init_68881_table ();
2454 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2456 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2458 for (i
= 0; i
< 6; i
++)
2460 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2461 return (codes_68881
[i
]);
2464 if (GET_MODE (x
) == SFmode
)
2467 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2468 return (codes_68881
[6]);
2470 /* larger powers of ten in the constants ram are not used
2471 because they are not equal to a `double' C constant. */
2475 /* If X is a floating-point constant, return the logarithm of X base 2,
2476 or 0 if X is not a power of 2. */
2479 floating_exact_log2 (x
)
2482 REAL_VALUE_TYPE r
, r1
;
2485 #ifndef REAL_ARITHMETIC
2486 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2487 if (! flag_pretend_float
)
2492 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2494 if (REAL_VALUES_LESS (r
, dconst0
))
2499 while (REAL_VALUES_LESS (r1
, r
))
2501 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2502 if (REAL_VALUES_EQUAL (r1
, r
))
2509 #ifdef SUPPORT_SUN_FPA
2510 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2511 from the Sun FPA's constant RAM.
2512 The value returned, anded with 0x1ff, gives the code to use in fpmove
2513 to get the desired constant. */
2515 static int inited_FPA_table
= 0;
2517 char *strings_FPA
[38] = {
2518 /* small rationals */
2531 /* Decimal equivalents of double precision values */
2532 "2.718281828459045091", /* D_E */
2533 "6.283185307179586477", /* 2 pi */
2534 "3.141592653589793116", /* D_PI */
2535 "1.570796326794896619", /* pi/2 */
2536 "1.414213562373095145", /* D_SQRT2 */
2537 "0.7071067811865475244", /* 1/sqrt(2) */
2538 "-1.570796326794896619", /* -pi/2 */
2539 "1.442695040888963387", /* D_LOG2ofE */
2540 "3.321928024887362182", /* D_LOG2of10 */
2541 "0.6931471805599452862", /* D_LOGEof2 */
2542 "2.302585092994045901", /* D_LOGEof10 */
2543 "0.3010299956639811980", /* D_LOG10of2 */
2544 "0.4342944819032518167", /* D_LOG10ofE */
2545 /* Decimal equivalents of single precision values */
2546 "2.718281745910644531", /* S_E */
2547 "6.283185307179586477", /* 2 pi */
2548 "3.141592741012573242", /* S_PI */
2549 "1.570796326794896619", /* pi/2 */
2550 "1.414213538169860840", /* S_SQRT2 */
2551 "0.7071067811865475244", /* 1/sqrt(2) */
2552 "-1.570796326794896619", /* -pi/2 */
2553 "1.442695021629333496", /* S_LOG2ofE */
2554 "3.321928024291992188", /* S_LOG2of10 */
2555 "0.6931471824645996094", /* S_LOGEof2 */
2556 "2.302585124969482442", /* S_LOGEof10 */
2557 "0.3010300099849700928", /* S_LOG10of2 */
2558 "0.4342944920063018799", /* S_LOG10ofE */
2562 int codes_FPA
[38] = {
2563 /* small rationals */
2576 /* double precision */
2590 /* single precision */
2606 REAL_VALUE_TYPE values_FPA
[38];
2608 /* This code has been fixed for cross-compilation. */
2613 enum machine_mode mode
;
2618 for (i
= 0; i
< 38; i
++)
2622 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2625 inited_FPA_table
= 1;
2630 standard_sun_fpa_constant_p (x
)
2636 #ifndef REAL_ARITHMETIC
2637 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2638 if (! flag_pretend_float
)
2643 if (! inited_FPA_table
)
2646 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2648 for (i
=0; i
<12; i
++)
2650 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2651 return (codes_FPA
[i
]);
2654 if (GET_MODE (x
) == SFmode
)
2656 for (i
=25; i
<38; i
++)
2658 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2659 return (codes_FPA
[i
]);
2664 for (i
=12; i
<25; i
++)
2666 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2667 return (codes_FPA
[i
]);
2672 #endif /* define SUPPORT_SUN_FPA */
2674 /* A C compound statement to output to stdio stream STREAM the
2675 assembler syntax for an instruction operand X. X is an RTL
2678 CODE is a value that can be used to specify one of several ways
2679 of printing the operand. It is used when identical operands
2680 must be printed differently depending on the context. CODE
2681 comes from the `%' specification that was used to request
2682 printing of the operand. If the specification was just `%DIGIT'
2683 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2684 is the ASCII code for LTR.
2686 If X is a register, this macro should print the register's name.
2687 The names can be found in an array `reg_names' whose type is
2688 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2690 When the machine description has a specification `%PUNCT' (a `%'
2691 followed by a punctuation character), this macro is called with
2692 a null pointer for X and the punctuation character for CODE.
2694 The m68k specific codes are:
2696 '.' for dot needed in Motorola-style opcode names.
2697 '-' for an operand pushing on the stack:
2698 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2699 '+' for an operand pushing on the stack:
2700 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2701 '@' for a reference to the top word on the stack:
2702 sp@, (sp) or (%sp) depending on the style of syntax.
2703 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2704 but & in SGS syntax, $ in CRDS/UNOS syntax).
2705 '!' for the cc register (used in an `and to cc' insn).
2706 '$' for the letter `s' in an op code, but only on the 68040.
2707 '&' for the letter `d' in an op code, but only on the 68040.
2708 '/' for register prefix needed by longlong.h.
2710 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2711 'd' to force memory addressing to be absolute, not relative.
2712 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2713 'o' for operands to go directly to output_operand_address (bypassing
2714 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2715 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2716 than directly). Second part of 'y' below.
2717 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2718 or print pair of registers as rx:ry.
2719 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2720 CONST_DOUBLE's as SunFPA constant RAM registers if
2721 possible, so it should not be used except for the SunFPA.
2726 print_operand (file
, op
, letter
)
2727 FILE *file
; /* file to write to */
2728 rtx op
; /* operand to print */
2729 int letter
; /* %<letter> or 0 */
2731 #ifdef SUPPORT_SUN_FPA
2737 #if defined (MOTOROLA) && !defined (CRDS)
2738 asm_fprintf (file
, ".");
2741 else if (letter
== '#')
2743 asm_fprintf (file
, "%0I");
2745 else if (letter
== '-')
2748 asm_fprintf (file
, "-(%Rsp)");
2750 asm_fprintf (file
, "%Rsp@-");
2753 else if (letter
== '+')
2756 asm_fprintf (file
, "(%Rsp)+");
2758 asm_fprintf (file
, "%Rsp@+");
2761 else if (letter
== '@')
2764 asm_fprintf (file
, "(%Rsp)");
2766 asm_fprintf (file
, "%Rsp@");
2769 else if (letter
== '!')
2771 asm_fprintf (file
, "%Rfpcr");
2773 else if (letter
== '$')
2775 if (TARGET_68040_ONLY
)
2777 fprintf (file
, "s");
2780 else if (letter
== '&')
2782 if (TARGET_68040_ONLY
)
2784 fprintf (file
, "d");
2787 else if (letter
== '/')
2789 asm_fprintf (file
, "%R");
2791 else if (letter
== 'o')
2793 /* This is only for direct addresses with TARGET_PCREL */
2794 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2797 output_addr_const (file
, XEXP (op
, 0));
2799 else if (GET_CODE (op
) == REG
)
2801 #ifdef SUPPORT_SUN_FPA
2803 && (letter
== 'y' || letter
== 'x')
2804 && GET_MODE (op
) == DFmode
)
2806 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2807 reg_names
[REGNO (op
)+1]);
2813 /* Print out the second register name of a register pair.
2814 I.e., R (6) => 7. */
2815 fputs (reg_names
[REGNO (op
) + 1], file
);
2817 fputs (reg_names
[REGNO (op
)], file
);
2820 else if (GET_CODE (op
) == MEM
)
2822 output_address (XEXP (op
, 0));
2823 if (letter
== 'd' && ! TARGET_68020
2824 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2825 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2826 && INTVAL (XEXP (op
, 0)) < 0x8000
2827 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2830 fprintf (file
, ".l");
2832 fprintf (file
, ":l");
2836 #ifdef SUPPORT_SUN_FPA
2837 else if ((letter
== 'y' || letter
== 'w')
2838 && GET_CODE (op
) == CONST_DOUBLE
2839 && (i
= standard_sun_fpa_constant_p (op
)))
2841 fprintf (file
, "%%%d", i
& 0x1ff);
2844 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2847 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2848 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2850 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2853 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2854 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2856 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2859 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2860 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2864 /* Use `print_operand_address' instead of `output_addr_const'
2865 to ensure that we print relevant PIC stuff. */
2866 asm_fprintf (file
, "%0I");
2868 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2869 print_operand_address (file
, op
);
2871 output_addr_const (file
, op
);
2876 /* A C compound statement to output to stdio stream STREAM the
2877 assembler syntax for an instruction operand that is a memory
2878 reference whose address is ADDR. ADDR is an RTL expression.
2880 Note that this contains a kludge that knows that the only reason
2881 we have an address (plus (label_ref...) (reg...)) when not generating
2882 PIC code is in the insn before a tablejump, and we know that m68k.md
2883 generates a label LInnn: on such an insn.
2885 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2886 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2888 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2889 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2890 we want. This difference can be accommodated by using an assembler
2891 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2892 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2893 macro. See m68k/sgs.h for an example; for versions without the bug.
2894 Some assemblers refuse all the above solutions. The workaround is to
2895 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2898 They also do not like things like "pea 1.w", so we simple leave off
2899 the .w on small constants.
2901 This routine is responsible for distinguishing between -fpic and -fPIC
2902 style relocations in an address. When generating -fpic code the
2903 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2904 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2906 #ifndef ASM_OUTPUT_CASE_FETCH
2909 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2910 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2912 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2913 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2916 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2917 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2919 #endif /* ASM_OUTPUT_CASE_FETCH */
2922 print_operand_address (file
, addr
)
2926 register rtx reg1
, reg2
, breg
, ireg
;
2929 switch (GET_CODE (addr
))
2933 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2935 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2940 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2942 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2947 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2949 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2953 reg1
= reg2
= ireg
= breg
= offset
= 0;
2954 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2956 offset
= XEXP (addr
, 0);
2957 addr
= XEXP (addr
, 1);
2959 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2961 offset
= XEXP (addr
, 1);
2962 addr
= XEXP (addr
, 0);
2964 if (GET_CODE (addr
) != PLUS
)
2968 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2970 reg1
= XEXP (addr
, 0);
2971 addr
= XEXP (addr
, 1);
2973 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2975 reg1
= XEXP (addr
, 1);
2976 addr
= XEXP (addr
, 0);
2978 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2980 reg1
= XEXP (addr
, 0);
2981 addr
= XEXP (addr
, 1);
2983 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2985 reg1
= XEXP (addr
, 1);
2986 addr
= XEXP (addr
, 0);
2988 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2990 reg1
= XEXP (addr
, 0);
2991 addr
= XEXP (addr
, 1);
2993 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2995 reg1
= XEXP (addr
, 1);
2996 addr
= XEXP (addr
, 0);
2998 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2999 || GET_CODE (addr
) == SIGN_EXTEND
)
3011 #if 0 /* for OLD_INDEXING */
3012 else if (GET_CODE (addr
) == PLUS
)
3014 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3016 reg2
= XEXP (addr
, 0);
3017 addr
= XEXP (addr
, 1);
3019 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3021 reg2
= XEXP (addr
, 1);
3022 addr
= XEXP (addr
, 0);
3034 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3035 || GET_CODE (reg1
) == MULT
))
3036 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3041 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3046 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3047 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3050 if (GET_CODE (ireg
) == MULT
)
3052 scale
= INTVAL (XEXP (ireg
, 1));
3053 ireg
= XEXP (ireg
, 0);
3055 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3057 ASM_OUTPUT_CASE_FETCH (file
,
3058 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3059 reg_names
[REGNO (XEXP (ireg
, 0))]);
3060 fprintf (file
, "w");
3064 ASM_OUTPUT_CASE_FETCH (file
,
3065 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3066 reg_names
[REGNO (ireg
)]);
3067 fprintf (file
, "l");
3072 fprintf (file
, "*%d", scale
);
3074 fprintf (file
, ":%d", scale
);
3080 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3081 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3083 ASM_OUTPUT_CASE_FETCH (file
,
3084 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3085 reg_names
[REGNO (breg
)]);
3086 fprintf (file
, "l)");
3089 if (ireg
!= 0 || breg
!= 0)
3096 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3103 output_addr_const (file
, addr
);
3104 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3106 fprintf (file
, "@GOT");
3108 fprintf (file
, ".w");
3111 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3117 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3120 output_addr_const (file
, addr
);
3121 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3122 fprintf (file
, ":w");
3123 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3124 fprintf (file
, ":l");
3126 if (addr
!= 0 && ireg
!= 0)
3131 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3133 scale
= INTVAL (XEXP (ireg
, 1));
3134 ireg
= XEXP (ireg
, 0);
3136 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3139 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3141 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3147 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3149 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3155 fprintf (file
, "*%d", scale
);
3157 fprintf (file
, ":%d", scale
);
3163 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3164 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3166 ASM_OUTPUT_CASE_FETCH (file
,
3167 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3168 reg_names
[REGNO (reg1
)]);
3169 fprintf (file
, "l)");
3172 /* FALL-THROUGH (is this really what we want?) */
3174 if (GET_CODE (addr
) == CONST_INT
3175 && INTVAL (addr
) < 0x8000
3176 && INTVAL (addr
) >= -0x8000)
3180 /* Many SGS assemblers croak on size specifiers for constants. */
3181 fprintf (file
, "%d", INTVAL (addr
));
3183 fprintf (file
, "%d.w", INTVAL (addr
));
3186 fprintf (file
, "%d:w", INTVAL (addr
));
3189 else if (GET_CODE (addr
) == CONST_INT
)
3192 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
3199 else if (TARGET_PCREL
)
3202 output_addr_const (file
, addr
);
3204 asm_fprintf (file
, ":w,%Rpc)");
3206 asm_fprintf (file
, ":l,%Rpc)");
3210 /* Special case for SYMBOL_REF if the symbol name ends in
3211 `.<letter>', this can be mistaken as a size suffix. Put
3212 the name in parentheses. */
3213 if (GET_CODE (addr
) == SYMBOL_REF
3214 && strlen (XSTR (addr
, 0)) > 2
3215 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3218 output_addr_const (file
, addr
);
3222 output_addr_const (file
, addr
);
3228 /* Check for cases where a clr insns can be omitted from code using
3229 strict_low_part sets. For example, the second clrl here is not needed:
3230 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3232 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3233 insn we are checking for redundancy. TARGET is the register set by the
3237 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3238 enum machine_mode mode
;
3244 p
= prev_nonnote_insn (first_insn
);
3248 /* If it isn't an insn, then give up. */
3249 if (GET_CODE (p
) != INSN
)
3252 if (reg_set_p (target
, p
))
3254 rtx set
= single_set (p
);
3257 /* If it isn't an easy to recognize insn, then give up. */
3261 dest
= SET_DEST (set
);
3263 /* If this sets the entire target register to zero, then our
3264 first_insn is redundant. */
3265 if (rtx_equal_p (dest
, target
)
3266 && SET_SRC (set
) == const0_rtx
)
3268 else if (GET_CODE (dest
) == STRICT_LOW_PART
3269 && GET_CODE (XEXP (dest
, 0)) == REG
3270 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3271 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3272 <= GET_MODE_SIZE (mode
)))
3273 /* This is a strict low part set which modifies less than
3274 we are using, so it is safe. */
3280 p
= prev_nonnote_insn (p
);
3287 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3288 range carefully since this predicate is used in DImode contexts. Also, we
3289 need some extra crud to make it work when hosted on 64-bit machines. */
3292 const_uint32_operand (op
, mode
)
3294 enum machine_mode mode ATTRIBUTE_UNUSED
;
3296 #if HOST_BITS_PER_WIDE_INT > 32
3297 /* All allowed constants will fit a CONST_INT. */
3298 return (GET_CODE (op
) == CONST_INT
3299 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3301 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3302 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3306 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3307 to check the range carefully since this predicate is used in DImode
3311 const_sint32_operand (op
, mode
)
3313 enum machine_mode mode ATTRIBUTE_UNUSED
;
3315 /* All allowed constants will fit a CONST_INT. */
3316 return (GET_CODE (op
) == CONST_INT
3317 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3320 /* Operand predicates for implementing asymmetric pc-relative addressing
3321 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3322 when used as a source operand, but not as a destintation operand.
3324 We model this by restricting the meaning of the basic predicates
3325 (general_operand, memory_operand, etc) to forbid the use of this
3326 addressing mode, and then define the following predicates that permit
3327 this addressing mode. These predicates can then be used for the
3328 source operands of the appropriate instructions.
3330 n.b. While it is theoretically possible to change all machine patterns
3331 to use this addressing more where permitted by the architecture,
3332 it has only been implemented for "common" cases: SImode, HImode, and
3333 QImode operands, and only for the principle operations that would
3334 require this addressing mode: data movement and simple integer operations.
3336 In parallel with these new predicates, two new constraint letters
3337 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3338 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3339 In the pcrel case 's' is only valid in combination with 'a' registers.
3340 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3341 of how these constraints are used.
3343 The use of these predicates is strictly optional, though patterns that
3344 don't will cause an extra reload register to be allocated where one
3347 lea (abc:w,%pc),%a0 ; need to reload address
3348 moveq &1,%d1 ; since write to pc-relative space
3349 movel %d1,%a0@ ; is not allowed
3351 lea (abc:w,%pc),%a1 ; no need to reload address here
3352 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3354 For more info, consult tiemann@cygnus.com.
3357 All of the ugliness with predicates and constraints is due to the
3358 simple fact that the m68k does not allow a pc-relative addressing
3359 mode as a destination. gcc does not distinguish between source and
3360 destination addresses. Hence, if we claim that pc-relative address
3361 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3362 end up with invalid code. To get around this problem, we left
3363 pc-relative modes as invalid addresses, and then added special
3364 predicates and constraints to accept them.
3366 A cleaner way to handle this is to modify gcc to distinguish
3367 between source and destination addresses. We can then say that
3368 pc-relative is a valid source address but not a valid destination
3369 address, and hopefully avoid a lot of the predicate and constraint
3370 hackery. Unfortunately, this would be a pretty big change. It would
3371 be a useful change for a number of ports, but there aren't any current
3372 plans to undertake this.
3374 ***************************************************************************/
3377 /* Special case of a general operand that's used as a source operand.
3378 Use this to permit reads from PC-relative memory when -mpcrel
3382 general_src_operand (op
, mode
)
3384 enum machine_mode mode
;
3387 && GET_CODE (op
) == MEM
3388 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3389 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3390 || GET_CODE (XEXP (op
, 0)) == CONST
))
3392 return general_operand (op
, mode
);
3395 /* Special case of a nonimmediate operand that's used as a source.
3396 Use this to permit reads from PC-relative memory when -mpcrel
3400 nonimmediate_src_operand (op
, mode
)
3402 enum machine_mode mode
;
3404 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3405 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3406 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3407 || GET_CODE (XEXP (op
, 0)) == CONST
))
3409 return nonimmediate_operand (op
, mode
);
3412 /* Special case of a memory operand that's used as a source.
3413 Use this to permit reads from PC-relative memory when -mpcrel
3417 memory_src_operand (op
, mode
)
3419 enum machine_mode mode
;
3421 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3422 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3423 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3424 || GET_CODE (XEXP (op
, 0)) == CONST
))
3426 return memory_operand (op
, mode
);
3429 /* Predicate that accepts only a pc-relative address. This is needed
3430 because pc-relative addresses don't satisfy the predicate
3431 "general_src_operand". */
3434 pcrel_address (op
, mode
)
3436 enum machine_mode mode
;
3438 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3439 || GET_CODE (op
) == CONST
);
3443 output_andsi3 (operands
)
3447 if (GET_CODE (operands
[2]) == CONST_INT
3448 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3449 && (DATA_REG_P (operands
[0])
3450 || offsettable_memref_p (operands
[0]))
3453 if (GET_CODE (operands
[0]) != REG
)
3454 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3455 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3456 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3458 if (operands
[2] == const0_rtx
)
3460 return "and%.w %2,%0";
3462 if (GET_CODE (operands
[2]) == CONST_INT
3463 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3464 && (DATA_REG_P (operands
[0])
3465 || offsettable_memref_p (operands
[0])))
3467 if (DATA_REG_P (operands
[0]))
3469 operands
[1] = GEN_INT (logval
);
3473 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3474 operands
[1] = GEN_INT (logval
% 8);
3476 /* This does not set condition codes in a standard way. */
3478 return "bclr %1,%0";
3480 return "and%.l %2,%0";
3484 output_iorsi3 (operands
)
3487 register int logval
;
3488 if (GET_CODE (operands
[2]) == CONST_INT
3489 && INTVAL (operands
[2]) >> 16 == 0
3490 && (DATA_REG_P (operands
[0])
3491 || offsettable_memref_p (operands
[0]))
3494 if (GET_CODE (operands
[0]) != REG
)
3495 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3496 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3498 if (INTVAL (operands
[2]) == 0xffff)
3499 return "mov%.w %2,%0";
3500 return "or%.w %2,%0";
3502 if (GET_CODE (operands
[2]) == CONST_INT
3503 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3504 && (DATA_REG_P (operands
[0])
3505 || offsettable_memref_p (operands
[0])))
3507 if (DATA_REG_P (operands
[0]))
3509 operands
[1] = GEN_INT (logval
);
3513 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3514 operands
[1] = GEN_INT (logval
% 8);
3517 return "bset %1,%0";
3519 return "or%.l %2,%0";
3523 output_xorsi3 (operands
)
3526 register int logval
;
3527 if (GET_CODE (operands
[2]) == CONST_INT
3528 && INTVAL (operands
[2]) >> 16 == 0
3529 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3532 if (! DATA_REG_P (operands
[0]))
3533 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3534 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3536 if (INTVAL (operands
[2]) == 0xffff)
3538 return "eor%.w %2,%0";
3540 if (GET_CODE (operands
[2]) == CONST_INT
3541 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3542 && (DATA_REG_P (operands
[0])
3543 || offsettable_memref_p (operands
[0])))
3545 if (DATA_REG_P (operands
[0]))
3547 operands
[1] = GEN_INT (logval
);
3551 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3552 operands
[1] = GEN_INT (logval
% 8);
3555 return "bchg %1,%0";
3557 return "eor%.l %2,%0";