1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* The minimum number of integer registers that we want to save with the
74 movem instruction. Using two movel instructions instead of a single
75 moveml is about 15% faster for the 68020 and 68030 at no expense in
77 #define MIN_MOVEM_REGS 3
79 /* The minimum number of floating point registers that we want to save
80 with the fmovem instruction. */
81 #define MIN_FMOVEM_REGS 1
83 /* Structure describing stack frame layout. */
86 /* Stack pointer to frame pointer offset. */
89 /* Offset of FPU registers. */
90 HOST_WIDE_INT foffset
;
92 /* Frame size in bytes (rounded up). */
95 /* Data and address register. */
97 unsigned int reg_mask
;
101 unsigned int fpu_mask
;
103 /* Offsets relative to ARG_POINTER. */
104 HOST_WIDE_INT frame_pointer_offset
;
105 HOST_WIDE_INT stack_pointer_offset
;
107 /* Function which the above information refers to. */
111 /* Current frame information calculated by m68k_compute_frame_layout(). */
112 static struct m68k_frame current_frame
;
114 /* Structure describing an m68k address.
116 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
117 with null fields evaluating to 0. Here:
119 - BASE satisfies m68k_legitimate_base_reg_p
120 - INDEX satisfies m68k_legitimate_index_reg_p
121 - OFFSET satisfies m68k_legitimate_constant_address_p
123 INDEX is either HImode or SImode. The other fields are SImode.
125 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
126 the address is (BASE)+. */
127 struct m68k_address
{
135 static bool m68k_handle_option (size_t, const char *, int);
136 static rtx
find_addr_reg (rtx
);
137 static const char *singlemove_string (rtx
*);
138 #ifdef M68K_TARGET_COFF
139 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
140 #endif /* M68K_TARGET_COFF */
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_rtx_costs (rtx
, int, int, int *);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands
;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_DEFAULT_TARGET_FLAGS
200 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
201 #undef TARGET_HANDLE_OPTION
202 #define TARGET_HANDLE_OPTION m68k_handle_option
204 #undef TARGET_RTX_COSTS
205 #define TARGET_RTX_COSTS m68k_rtx_costs
207 #undef TARGET_ATTRIBUTE_TABLE
208 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
210 #undef TARGET_PROMOTE_PROTOTYPES
211 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
213 #undef TARGET_STRUCT_VALUE_RTX
214 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
216 #undef TARGET_CANNOT_FORCE_CONST_MEM
217 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
219 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
220 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
222 static const struct attribute_spec m68k_attribute_table
[] =
224 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
225 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
226 { NULL
, 0, 0, false, false, false, NULL
}
229 struct gcc_target targetm
= TARGET_INITIALIZER
;
231 /* Base flags for 68k ISAs. */
232 #define FL_FOR_isa_00 FL_ISA_68000
233 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
234 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
235 generated 68881 code for 68020 and 68030 targets unless explicitly told
237 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
238 | FL_BITFIELD | FL_68881)
239 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
240 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
242 /* Base flags for ColdFire ISAs. */
243 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
244 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
245 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
246 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
247 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
251 /* Traditional 68000 instruction sets. */
257 /* ColdFire instruction set variants. */
265 /* Information about one of the -march, -mcpu or -mtune arguments. */
266 struct m68k_target_selection
268 /* The argument being described. */
271 /* For -mcpu, this is the device selected by the option.
272 For -mtune and -march, it is a representative device
273 for the microarchitecture or ISA respectively. */
274 enum target_device device
;
276 /* The M68K_DEVICE fields associated with DEVICE. See the comment
277 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
279 enum uarch_type microarch
;
284 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
285 static const struct m68k_target_selection all_devices
[] =
287 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
288 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
289 #include "m68k-devices.def"
291 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
294 /* A list of all ISAs, mapping each one to a representative device.
295 Used for -march selection. */
296 static const struct m68k_target_selection all_isas
[] =
298 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
299 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
300 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
301 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
302 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
303 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
304 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
305 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
307 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
309 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
310 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
313 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
316 /* A list of all microarchitectures, mapping each one to a representative
317 device. Used for -mtune selection. */
318 static const struct m68k_target_selection all_microarchs
[] =
320 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
321 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
322 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
323 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
324 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
325 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
326 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
327 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
328 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
329 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
330 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
332 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
333 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
337 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
340 /* The entries associated with the -mcpu, -march and -mtune settings,
341 or null for options that have not been used. */
342 const struct m68k_target_selection
*m68k_cpu_entry
;
343 const struct m68k_target_selection
*m68k_arch_entry
;
344 const struct m68k_target_selection
*m68k_tune_entry
;
346 /* Which CPU we are generating code for. */
347 enum target_device m68k_cpu
;
349 /* Which microarchitecture to tune for. */
350 enum uarch_type m68k_tune
;
352 /* Which FPU to use. */
353 enum fpu_type m68k_fpu
;
355 /* The set of FL_* flags that apply to the target processor. */
356 unsigned int m68k_cpu_flags
;
358 /* Asm templates for calling or jumping to an arbitrary symbolic address,
359 or NULL if such calls or jumps are not supported. The address is held
361 const char *m68k_symbolic_call
;
362 const char *m68k_symbolic_jump
;
364 /* See whether TABLE has an entry with name NAME. Return true and
365 store the entry in *ENTRY if so, otherwise return false and
366 leave *ENTRY alone. */
369 m68k_find_selection (const struct m68k_target_selection
**entry
,
370 const struct m68k_target_selection
*table
,
375 for (i
= 0; table
[i
].name
; i
++)
376 if (strcmp (table
[i
].name
, name
) == 0)
384 /* Implement TARGET_HANDLE_OPTION. */
387 m68k_handle_option (size_t code
, const char *arg
, int value
)
392 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
395 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
398 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
401 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
404 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
407 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
410 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
420 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
423 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
427 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
430 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
432 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
435 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
437 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
440 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
443 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
446 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
449 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
453 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
455 case OPT_mshared_library_id_
:
456 if (value
> MAX_LIBRARY_ID
)
457 error ("-mshared-library-id=%s is not between 0 and %d",
458 arg
, MAX_LIBRARY_ID
);
460 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
468 /* Sometimes certain combinations of command options do not make
469 sense on a particular target machine. You can define a macro
470 `OVERRIDE_OPTIONS' to take account of this. This macro, if
471 defined, is executed once just after all the command options have
474 Don't use this macro to turn on various extra optimizations for
475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
478 override_options (void)
480 const struct m68k_target_selection
*entry
;
481 unsigned long target_mask
;
489 -march=ARCH should generate code that runs any processor
490 implementing architecture ARCH. -mcpu=CPU should override -march
491 and should generate code that runs on processor CPU, making free
492 use of any instructions that CPU understands. -mtune=UARCH applies
493 on top of -mcpu or -march and optimizes the code for UARCH. It does
494 not change the target architecture. */
497 /* Complain if the -march setting is for a different microarchitecture,
498 or includes flags that the -mcpu setting doesn't. */
500 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
501 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
502 warning (0, "-mcpu=%s conflicts with -march=%s",
503 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
505 entry
= m68k_cpu_entry
;
508 entry
= m68k_arch_entry
;
511 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
513 m68k_cpu_flags
= entry
->flags
;
515 /* Use the architecture setting to derive default values for
518 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
519 target_mask
|= MASK_BITFIELD
;
520 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
521 target_mask
|= MASK_CF_HWDIV
;
522 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
523 target_mask
|= MASK_HARD_FLOAT
;
524 target_flags
|= target_mask
& ~target_flags_explicit
;
526 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
527 m68k_cpu
= entry
->device
;
529 m68k_tune
= m68k_tune_entry
->microarch
;
530 #ifdef M68K_DEFAULT_TUNE
531 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
532 m68k_tune
= M68K_DEFAULT_TUNE
;
535 m68k_tune
= entry
->microarch
;
537 /* Set the type of FPU. */
538 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
539 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
542 if (TARGET_COLDFIRE_FPU
)
544 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
545 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
548 /* Sanity check to ensure that msep-data and mid-sahred-library are not
549 * both specified together. Doing so simply doesn't make sense.
551 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
552 error ("cannot specify both -msep-data and -mid-shared-library");
554 /* If we're generating code for a separate A5 relative data segment,
555 * we've got to enable -fPIC as well. This might be relaxable to
556 * -fpic but it hasn't been tested properly.
558 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
561 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
562 error if the target does not support them. */
563 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
564 error ("-mpcrel -fPIC is not currently supported on selected cpu");
566 /* ??? A historic way of turning on pic, or is this intended to
567 be an embedded thing that doesn't have the same name binding
568 significance that it does on hosted ELF systems? */
569 if (TARGET_PCREL
&& flag_pic
== 0)
574 #if MOTOROLA && !defined (USE_GAS)
575 m68k_symbolic_call
= "jsr %a0";
576 m68k_symbolic_jump
= "jmp %a0";
578 m68k_symbolic_call
= "jbsr %a0";
579 m68k_symbolic_jump
= "jra %a0";
582 else if (TARGET_ID_SHARED_LIBRARY
)
583 /* All addresses must be loaded from the GOT. */
585 else if (TARGET_68020
|| TARGET_ISAB
)
589 m68k_symbolic_call
= "bsr.l %c0";
590 m68k_symbolic_jump
= "bra.l %c0";
595 m68k_symbolic_call
= "bsr.l %p0";
596 m68k_symbolic_jump
= "bra.l %p0";
598 m68k_symbolic_call
= "bsr %p0";
599 m68k_symbolic_jump
= "bra %p0";
602 /* Turn off function cse if we are doing PIC. We always want
603 function call to be done as `bsr foo@PLTPC'. */
604 /* ??? It's traditional to do this for -mpcrel too, but it isn't
605 clear how intentional that is. */
606 flag_no_function_cse
= 1;
609 SUBTARGET_OVERRIDE_OPTIONS
;
612 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
613 given argument and NAME is the argument passed to -mcpu. Return NULL
614 if -mcpu was not passed. */
617 m68k_cpp_cpu_ident (const char *prefix
)
621 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
624 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
625 given argument and NAME is the name of the representative device for
626 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
629 m68k_cpp_cpu_family (const char *prefix
)
633 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
636 /* Return nonzero if FUNC is an interrupt function as specified by the
637 "interrupt_handler" attribute. */
639 m68k_interrupt_function_p (tree func
)
643 if (TREE_CODE (func
) != FUNCTION_DECL
)
646 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
647 return (a
!= NULL_TREE
);
650 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
651 struct attribute_spec.handler. */
653 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
654 tree args ATTRIBUTE_UNUSED
,
655 int flags ATTRIBUTE_UNUSED
,
658 if (TREE_CODE (*node
) != FUNCTION_DECL
)
660 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
661 IDENTIFIER_POINTER (name
));
662 *no_add_attrs
= true;
669 m68k_compute_frame_layout (void)
673 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
675 /* Only compute the frame once per function.
676 Don't cache information until reload has been completed. */
677 if (current_frame
.funcdef_no
== current_function_funcdef_no
681 current_frame
.size
= (get_frame_size () + 3) & -4;
684 for (regno
= 0; regno
< 16; regno
++)
685 if (m68k_save_reg (regno
, interrupt_handler
))
687 mask
|= 1 << (regno
- D0_REG
);
690 current_frame
.offset
= saved
* 4;
691 current_frame
.reg_no
= saved
;
692 current_frame
.reg_mask
= mask
;
694 current_frame
.foffset
= 0;
696 if (TARGET_HARD_FLOAT
)
698 for (regno
= 16; regno
< 24; regno
++)
699 if (m68k_save_reg (regno
, interrupt_handler
))
701 mask
|= 1 << (regno
- FP0_REG
);
704 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
705 current_frame
.offset
+= current_frame
.foffset
;
707 current_frame
.fpu_no
= saved
;
708 current_frame
.fpu_mask
= mask
;
710 /* Remember what function this frame refers to. */
711 current_frame
.funcdef_no
= current_function_funcdef_no
;
715 m68k_initial_elimination_offset (int from
, int to
)
718 /* The arg pointer points 8 bytes before the start of the arguments,
719 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
720 frame pointer in most frames. */
721 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
722 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
723 return argptr_offset
;
725 m68k_compute_frame_layout ();
727 gcc_assert (to
== STACK_POINTER_REGNUM
);
730 case ARG_POINTER_REGNUM
:
731 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
732 case FRAME_POINTER_REGNUM
:
733 return current_frame
.offset
+ current_frame
.size
;
739 /* Refer to the array `regs_ever_live' to determine which registers
740 to save; `regs_ever_live[I]' is nonzero if register number I
741 is ever used in the function. This function is responsible for
742 knowing which registers should not be saved even if used.
743 Return true if we need to save REGNO. */
746 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
748 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
750 if (current_function_uses_pic_offset_table
)
752 /* Reload may introduce constant pool references into a function
753 that thitherto didn't need a PIC register. Note that the test
754 above will not catch that case because we will only set
755 current_function_uses_pic_offset_table when emitting
756 the address reloads. */
757 if (current_function_uses_const_pool
)
761 if (current_function_calls_eh_return
)
766 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
767 if (test
== INVALID_REGNUM
)
774 /* Fixed regs we never touch. */
775 if (fixed_regs
[regno
])
778 /* The frame pointer (if it is such) is handled specially. */
779 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
782 /* Interrupt handlers must also save call_used_regs
783 if they are live or when calling nested functions. */
784 if (interrupt_handler
)
786 if (regs_ever_live
[regno
])
789 if (!current_function_is_leaf
&& call_used_regs
[regno
])
793 /* Never need to save registers that aren't touched. */
794 if (!regs_ever_live
[regno
])
797 /* Otherwise save everything that isn't call-clobbered. */
798 return !call_used_regs
[regno
];
801 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
802 the lowest memory address. COUNT is the number of registers to be
803 moved, with register REGNO + I being moved if bit I of MASK is set.
804 STORE_P specifies the direction of the move and ADJUST_STACK_P says
805 whether or not this is pre-decrement (if STORE_P) or post-increment
806 (if !STORE_P) operation. */
809 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
810 unsigned int count
, unsigned int regno
,
811 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
814 rtx body
, addr
, src
, operands
[2];
815 enum machine_mode mode
;
817 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
818 mode
= reg_raw_mode
[regno
];
823 src
= plus_constant (base
, (count
824 * GET_MODE_SIZE (mode
)
825 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
826 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
829 for (; mask
!= 0; mask
>>= 1, regno
++)
832 addr
= plus_constant (base
, offset
);
833 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
834 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
835 XVECEXP (body
, 0, i
++)
836 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
837 offset
+= GET_MODE_SIZE (mode
);
839 gcc_assert (i
== XVECLEN (body
, 0));
841 return emit_insn (body
);
844 /* Make INSN a frame-related instruction. */
847 m68k_set_frame_related (rtx insn
)
852 RTX_FRAME_RELATED_P (insn
) = 1;
853 body
= PATTERN (insn
);
854 if (GET_CODE (body
) == PARALLEL
)
855 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
856 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
859 /* Emit RTL for the "prologue" define_expand. */
862 m68k_expand_prologue (void)
864 HOST_WIDE_INT fsize_with_regs
;
865 rtx limit
, src
, dest
, insn
;
867 m68k_compute_frame_layout ();
869 /* If the stack limit is a symbol, we can check it here,
870 before actually allocating the space. */
871 if (current_function_limit_stack
872 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
874 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
875 if (!LEGITIMATE_CONSTANT_P (limit
))
877 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
878 limit
= gen_rtx_REG (Pmode
, D0_REG
);
880 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
881 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
882 cc0_rtx
, const0_rtx
),
886 fsize_with_regs
= current_frame
.size
;
889 /* ColdFire's move multiple instructions do not allow pre-decrement
890 addressing. Add the size of movem saves to the initial stack
891 allocation instead. */
892 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
893 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
894 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
895 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
898 if (frame_pointer_needed
)
900 if (fsize_with_regs
== 0 && TUNE_68040
)
902 /* On the 68040, two separate moves are faster than link.w 0. */
903 dest
= gen_frame_mem (Pmode
,
904 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
905 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
906 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
909 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
910 m68k_set_frame_related
911 (emit_insn (gen_link (frame_pointer_rtx
,
912 GEN_INT (-4 - fsize_with_regs
))));
915 m68k_set_frame_related
916 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
917 m68k_set_frame_related
918 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
920 GEN_INT (-fsize_with_regs
))));
923 else if (fsize_with_regs
!= 0)
924 m68k_set_frame_related
925 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
927 GEN_INT (-fsize_with_regs
))));
929 if (current_frame
.fpu_mask
)
931 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
933 m68k_set_frame_related
934 (m68k_emit_movem (stack_pointer_rtx
,
935 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
936 current_frame
.fpu_no
, FP0_REG
,
937 current_frame
.fpu_mask
, true, true));
942 /* If we're using moveml to save the integer registers,
943 the stack pointer will point to the bottom of the moveml
944 save area. Find the stack offset of the first FP register. */
945 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
948 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
949 m68k_set_frame_related
950 (m68k_emit_movem (stack_pointer_rtx
, offset
,
951 current_frame
.fpu_no
, FP0_REG
,
952 current_frame
.fpu_mask
, true, false));
956 /* If the stack limit is not a symbol, check it here.
957 This has the disadvantage that it may be too late... */
958 if (current_function_limit_stack
)
960 if (REG_P (stack_limit_rtx
))
962 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
963 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
964 cc0_rtx
, const0_rtx
),
967 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
968 warning (0, "stack limit expression is not supported");
971 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
973 /* Store each register separately in the same order moveml does. */
976 for (i
= 16; i
-- > 0; )
977 if (current_frame
.reg_mask
& (1 << i
))
979 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
980 dest
= gen_frame_mem (SImode
,
981 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
982 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
988 /* The required register save space has already been allocated.
989 The first register should be stored at (%sp). */
990 m68k_set_frame_related
991 (m68k_emit_movem (stack_pointer_rtx
, 0,
992 current_frame
.reg_no
, D0_REG
,
993 current_frame
.reg_mask
, true, false));
995 m68k_set_frame_related
996 (m68k_emit_movem (stack_pointer_rtx
,
997 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
998 current_frame
.reg_no
, D0_REG
,
999 current_frame
.reg_mask
, true, true));
1004 && current_function_uses_pic_offset_table
)
1006 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1007 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
1013 /* Return true if a simple (return) instruction is sufficient for this
1014 instruction (i.e. if no epilogue is needed). */
1017 m68k_use_return_insn (void)
1019 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1022 m68k_compute_frame_layout ();
1023 return current_frame
.offset
== 0;
1026 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1027 SIBCALL_P says which.
1029 The function epilogue should not depend on the current stack pointer!
1030 It should use the frame pointer only, if there is a frame pointer.
1031 This is mandatory because of alloca; we also take advantage of it to
1032 omit stack adjustments before returning. */
1035 m68k_expand_epilogue (bool sibcall_p
)
1037 HOST_WIDE_INT fsize
, fsize_with_regs
;
1038 bool big
, restore_from_sp
;
1040 m68k_compute_frame_layout ();
1042 fsize
= current_frame
.size
;
1044 restore_from_sp
= false;
1046 /* FIXME : current_function_is_leaf below is too strong.
1047 What we really need to know there is if there could be pending
1048 stack adjustment needed at that point. */
1049 restore_from_sp
= (!frame_pointer_needed
1050 || (!current_function_calls_alloca
1051 && current_function_is_leaf
));
1053 /* fsize_with_regs is the size we need to adjust the sp when
1054 popping the frame. */
1055 fsize_with_regs
= fsize
;
1056 if (TARGET_COLDFIRE
&& restore_from_sp
)
1058 /* ColdFire's move multiple instructions do not allow post-increment
1059 addressing. Add the size of movem loads to the final deallocation
1061 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1062 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1063 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1064 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1067 if (current_frame
.offset
+ fsize
>= 0x8000
1069 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1072 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1073 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1075 /* ColdFire's move multiple instructions do not support the
1076 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1077 stack-based restore. */
1078 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1079 GEN_INT (-(current_frame
.offset
+ fsize
)));
1080 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1081 gen_rtx_REG (Pmode
, A1_REG
),
1082 frame_pointer_rtx
));
1083 restore_from_sp
= true;
1087 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1093 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1095 /* Restore each register separately in the same order moveml does. */
1097 HOST_WIDE_INT offset
;
1099 offset
= current_frame
.offset
+ fsize
;
1100 for (i
= 0; i
< 16; i
++)
1101 if (current_frame
.reg_mask
& (1 << i
))
1107 /* Generate the address -OFFSET(%fp,%a1.l). */
1108 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1109 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1110 addr
= plus_constant (addr
, -offset
);
1112 else if (restore_from_sp
)
1113 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1115 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1116 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1117 gen_frame_mem (SImode
, addr
));
1118 offset
-= GET_MODE_SIZE (SImode
);
1121 else if (current_frame
.reg_mask
)
1124 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1125 gen_rtx_REG (Pmode
, A1_REG
),
1127 -(current_frame
.offset
+ fsize
),
1128 current_frame
.reg_no
, D0_REG
,
1129 current_frame
.reg_mask
, false, false);
1130 else if (restore_from_sp
)
1131 m68k_emit_movem (stack_pointer_rtx
, 0,
1132 current_frame
.reg_no
, D0_REG
,
1133 current_frame
.reg_mask
, false,
1136 m68k_emit_movem (frame_pointer_rtx
,
1137 -(current_frame
.offset
+ fsize
),
1138 current_frame
.reg_no
, D0_REG
,
1139 current_frame
.reg_mask
, false, false);
1142 if (current_frame
.fpu_no
> 0)
1145 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1146 gen_rtx_REG (Pmode
, A1_REG
),
1148 -(current_frame
.foffset
+ fsize
),
1149 current_frame
.fpu_no
, FP0_REG
,
1150 current_frame
.fpu_mask
, false, false);
1151 else if (restore_from_sp
)
1153 if (TARGET_COLDFIRE
)
1157 /* If we used moveml to restore the integer registers, the
1158 stack pointer will still point to the bottom of the moveml
1159 save area. Find the stack offset of the first FP
1161 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1164 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1165 m68k_emit_movem (stack_pointer_rtx
, offset
,
1166 current_frame
.fpu_no
, FP0_REG
,
1167 current_frame
.fpu_mask
, false, false);
1170 m68k_emit_movem (stack_pointer_rtx
, 0,
1171 current_frame
.fpu_no
, FP0_REG
,
1172 current_frame
.fpu_mask
, false, true);
1175 m68k_emit_movem (frame_pointer_rtx
,
1176 -(current_frame
.foffset
+ fsize
),
1177 current_frame
.fpu_no
, FP0_REG
,
1178 current_frame
.fpu_mask
, false, false);
1181 if (frame_pointer_needed
)
1182 emit_insn (gen_unlink (frame_pointer_rtx
));
1183 else if (fsize_with_regs
)
1184 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1186 GEN_INT (fsize_with_regs
)));
1188 if (current_function_calls_eh_return
)
1189 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1191 EH_RETURN_STACKADJ_RTX
));
1194 emit_insn (gen_rtx_RETURN (VOIDmode
));
1197 /* Return true if X is a valid comparison operator for the dbcc
1200 Note it rejects floating point comparison operators.
1201 (In the future we could use Fdbcc).
1203 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1206 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1208 switch (GET_CODE (x
))
1210 case EQ
: case NE
: case GTU
: case LTU
:
1214 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1216 case GT
: case LT
: case GE
: case LE
:
1217 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1223 /* Return nonzero if flags are currently in the 68881 flag register. */
1225 flags_in_68881 (void)
1227 /* We could add support for these in the future */
1228 return cc_status
.flags
& CC_IN_68881
;
1231 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls
1232 for nested functions because we use the static chain register for
1236 m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED
, tree exp
)
1238 return TREE_OPERAND (exp
, 2) == NULL
;
1241 /* Convert X to a legitimate function call memory reference and return the
1245 m68k_legitimize_call_address (rtx x
)
1247 gcc_assert (MEM_P (x
));
1248 if (call_operand (XEXP (x
, 0), VOIDmode
))
1250 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1253 /* Likewise for sibling calls. */
1256 m68k_legitimize_sibcall_address (rtx x
)
1258 gcc_assert (MEM_P (x
));
1259 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1262 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1263 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1266 /* Output a dbCC; jCC sequence. Note we do not handle the
1267 floating point version of this sequence (Fdbcc). We also
1268 do not handle alternative conditions when CC_NO_OVERFLOW is
1269 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1270 kick those out before we get here. */
1273 output_dbcc_and_branch (rtx
*operands
)
1275 switch (GET_CODE (operands
[3]))
1278 output_asm_insn (MOTOROLA
1279 ? "dbeq %0,%l1\n\tjbeq %l2"
1280 : "dbeq %0,%l1\n\tjeq %l2",
1285 output_asm_insn (MOTOROLA
1286 ? "dbne %0,%l1\n\tjbne %l2"
1287 : "dbne %0,%l1\n\tjne %l2",
1292 output_asm_insn (MOTOROLA
1293 ? "dbgt %0,%l1\n\tjbgt %l2"
1294 : "dbgt %0,%l1\n\tjgt %l2",
1299 output_asm_insn (MOTOROLA
1300 ? "dbhi %0,%l1\n\tjbhi %l2"
1301 : "dbhi %0,%l1\n\tjhi %l2",
1306 output_asm_insn (MOTOROLA
1307 ? "dblt %0,%l1\n\tjblt %l2"
1308 : "dblt %0,%l1\n\tjlt %l2",
1313 output_asm_insn (MOTOROLA
1314 ? "dbcs %0,%l1\n\tjbcs %l2"
1315 : "dbcs %0,%l1\n\tjcs %l2",
1320 output_asm_insn (MOTOROLA
1321 ? "dbge %0,%l1\n\tjbge %l2"
1322 : "dbge %0,%l1\n\tjge %l2",
1327 output_asm_insn (MOTOROLA
1328 ? "dbcc %0,%l1\n\tjbcc %l2"
1329 : "dbcc %0,%l1\n\tjcc %l2",
1334 output_asm_insn (MOTOROLA
1335 ? "dble %0,%l1\n\tjble %l2"
1336 : "dble %0,%l1\n\tjle %l2",
1341 output_asm_insn (MOTOROLA
1342 ? "dbls %0,%l1\n\tjbls %l2"
1343 : "dbls %0,%l1\n\tjls %l2",
1351 /* If the decrement is to be done in SImode, then we have
1352 to compensate for the fact that dbcc decrements in HImode. */
1353 switch (GET_MODE (operands
[0]))
1356 output_asm_insn (MOTOROLA
1357 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1358 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1371 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1374 enum rtx_code op_code
= GET_CODE (op
);
1376 /* This does not produce a useful cc. */
1379 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1380 below. Swap the operands and change the op if these requirements
1381 are not fulfilled. */
1382 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1386 operand1
= operand2
;
1388 op_code
= swap_condition (op_code
);
1390 loperands
[0] = operand1
;
1391 if (GET_CODE (operand1
) == REG
)
1392 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1394 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1395 if (operand2
!= const0_rtx
)
1397 loperands
[2] = operand2
;
1398 if (GET_CODE (operand2
) == REG
)
1399 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1401 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1403 loperands
[4] = gen_label_rtx ();
1404 if (operand2
!= const0_rtx
)
1406 output_asm_insn (MOTOROLA
1407 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1408 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1413 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1414 output_asm_insn ("tst%.l %0", loperands
);
1416 output_asm_insn ("cmp%.w #0,%0", loperands
);
1418 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1420 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1421 output_asm_insn ("tst%.l %1", loperands
);
1423 output_asm_insn ("cmp%.w #0,%1", loperands
);
1426 loperands
[5] = dest
;
1431 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1432 CODE_LABEL_NUMBER (loperands
[4]));
1433 output_asm_insn ("seq %5", loperands
);
1437 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1438 CODE_LABEL_NUMBER (loperands
[4]));
1439 output_asm_insn ("sne %5", loperands
);
1443 loperands
[6] = gen_label_rtx ();
1444 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1446 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1447 CODE_LABEL_NUMBER (loperands
[4]));
1448 output_asm_insn ("sgt %5", loperands
);
1449 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1450 CODE_LABEL_NUMBER (loperands
[6]));
1454 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1455 CODE_LABEL_NUMBER (loperands
[4]));
1456 output_asm_insn ("shi %5", loperands
);
1460 loperands
[6] = gen_label_rtx ();
1461 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1463 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1464 CODE_LABEL_NUMBER (loperands
[4]));
1465 output_asm_insn ("slt %5", loperands
);
1466 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1467 CODE_LABEL_NUMBER (loperands
[6]));
1471 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1472 CODE_LABEL_NUMBER (loperands
[4]));
1473 output_asm_insn ("scs %5", loperands
);
1477 loperands
[6] = gen_label_rtx ();
1478 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1480 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1481 CODE_LABEL_NUMBER (loperands
[4]));
1482 output_asm_insn ("sge %5", loperands
);
1483 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1484 CODE_LABEL_NUMBER (loperands
[6]));
1488 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1489 CODE_LABEL_NUMBER (loperands
[4]));
1490 output_asm_insn ("scc %5", loperands
);
1494 loperands
[6] = gen_label_rtx ();
1495 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1497 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1498 CODE_LABEL_NUMBER (loperands
[4]));
1499 output_asm_insn ("sle %5", loperands
);
1500 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1501 CODE_LABEL_NUMBER (loperands
[6]));
1505 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1506 CODE_LABEL_NUMBER (loperands
[4]));
1507 output_asm_insn ("sls %5", loperands
);
1517 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1519 operands
[0] = countop
;
1520 operands
[1] = dataop
;
1522 if (GET_CODE (countop
) == CONST_INT
)
1524 register int count
= INTVAL (countop
);
1525 /* If COUNT is bigger than size of storage unit in use,
1526 advance to the containing unit of same size. */
1527 if (count
> signpos
)
1529 int offset
= (count
& ~signpos
) / 8;
1530 count
= count
& signpos
;
1531 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1533 if (count
== signpos
)
1534 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1536 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1538 /* These three statements used to use next_insns_test_no...
1539 but it appears that this should do the same job. */
1541 && next_insn_tests_no_inequality (insn
))
1544 && next_insn_tests_no_inequality (insn
))
1547 && next_insn_tests_no_inequality (insn
))
1550 cc_status
.flags
= CC_NOT_NEGATIVE
;
1552 return "btst %0,%1";
1555 /* Return true if X is a legitimate base register. STRICT_P says
1556 whether we need strict checking. */
1559 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1561 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1562 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1567 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1568 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1571 /* Return true if X is a legitimate index register. STRICT_P says
1572 whether we need strict checking. */
1575 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1577 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1582 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1583 : !FP_REGNO_P (REGNO (x
))));
1586 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1587 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1588 ADDRESS if so. STRICT_P says whether we need strict checking. */
1591 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1595 /* Check for a scale factor. */
1597 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1598 && GET_CODE (x
) == MULT
1599 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1600 && (INTVAL (XEXP (x
, 1)) == 2
1601 || INTVAL (XEXP (x
, 1)) == 4
1602 || (INTVAL (XEXP (x
, 1)) == 8
1603 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1605 scale
= INTVAL (XEXP (x
, 1));
1609 /* Check for a word extension. */
1610 if (!TARGET_COLDFIRE
1611 && GET_CODE (x
) == SIGN_EXTEND
1612 && GET_MODE (XEXP (x
, 0)) == HImode
)
1615 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1617 address
->scale
= scale
;
1625 /* Return true if X is an illegitimate symbolic constant. */
1628 m68k_illegitimate_symbolic_constant_p (rtx x
)
1632 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1634 split_const (x
, &base
, &offset
);
1635 if (GET_CODE (base
) == SYMBOL_REF
1636 && !offset_within_block_p (base
, INTVAL (offset
)))
1642 /* Return true if X is a legitimate constant address that can reach
1643 bytes in the range [X, X + REACH). STRICT_P says whether we need
1647 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1651 if (!CONSTANT_ADDRESS_P (x
))
1655 && !(strict_p
&& TARGET_PCREL
)
1656 && symbolic_operand (x
, VOIDmode
))
1659 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1661 split_const (x
, &base
, &offset
);
1662 if (GET_CODE (base
) == SYMBOL_REF
1663 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1670 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1671 labels will become jump tables. */
1674 m68k_jump_table_ref_p (rtx x
)
1676 if (GET_CODE (x
) != LABEL_REF
)
1680 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1683 x
= next_nonnote_insn (x
);
1684 return x
&& JUMP_TABLE_DATA_P (x
);
1687 /* Return true if X is a legitimate address for values of mode MODE.
1688 STRICT_P says whether strict checking is needed. If the address
1689 is valid, describe its components in *ADDRESS. */
1692 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1693 bool strict_p
, struct m68k_address
*address
)
1697 memset (address
, 0, sizeof (*address
));
1699 if (mode
== BLKmode
)
1702 reach
= GET_MODE_SIZE (mode
);
1704 /* Check for (An) (mode 2). */
1705 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1711 /* Check for -(An) and (An)+ (modes 3 and 4). */
1712 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1713 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1715 address
->code
= GET_CODE (x
);
1716 address
->base
= XEXP (x
, 0);
1720 /* Check for (d16,An) (mode 5). */
1721 if (GET_CODE (x
) == PLUS
1722 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1723 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1724 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1726 address
->base
= XEXP (x
, 0);
1727 address
->offset
= XEXP (x
, 1);
1731 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1732 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1735 && GET_CODE (x
) == PLUS
1736 && XEXP (x
, 0) == pic_offset_table_rtx
1737 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1738 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1740 address
->base
= XEXP (x
, 0);
1741 address
->offset
= XEXP (x
, 1);
1745 /* The ColdFire FPU only accepts addressing modes 2-5. */
1746 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1749 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1750 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1751 All these modes are variations of mode 7. */
1752 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1754 address
->offset
= x
;
1758 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1761 ??? do_tablejump creates these addresses before placing the target
1762 label, so we have to assume that unplaced labels are jump table
1763 references. It seems unlikely that we would ever generate indexed
1764 accesses to unplaced labels in other cases. */
1765 if (GET_CODE (x
) == PLUS
1766 && m68k_jump_table_ref_p (XEXP (x
, 1))
1767 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1769 address
->offset
= XEXP (x
, 1);
1773 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1774 (bd,An,Xn.SIZE*SCALE) addresses. */
1778 /* Check for a nonzero base displacement. */
1779 if (GET_CODE (x
) == PLUS
1780 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1782 address
->offset
= XEXP (x
, 1);
1786 /* Check for a suppressed index register. */
1787 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1793 /* Check for a suppressed base register. Do not allow this case
1794 for non-symbolic offsets as it effectively gives gcc freedom
1795 to treat data registers as base registers, which can generate
1798 && symbolic_operand (address
->offset
, VOIDmode
)
1799 && m68k_decompose_index (x
, strict_p
, address
))
1804 /* Check for a nonzero base displacement. */
1805 if (GET_CODE (x
) == PLUS
1806 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1807 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1809 address
->offset
= XEXP (x
, 1);
1814 /* We now expect the sum of a base and an index. */
1815 if (GET_CODE (x
) == PLUS
)
1817 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1818 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1820 address
->base
= XEXP (x
, 0);
1824 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1825 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1827 address
->base
= XEXP (x
, 1);
1834 /* Return true if X is a legitimate address for values of mode MODE.
1835 STRICT_P says whether strict checking is needed. */
1838 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1840 struct m68k_address address
;
1842 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1845 /* Return true if X is a memory, describing its address in ADDRESS if so.
1846 Apply strict checking if called during or after reload. */
1849 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1852 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1853 reload_in_progress
|| reload_completed
,
1857 /* Return true if X matches the 'Q' constraint. It must be a memory
1858 with a base address and no constant offset or index. */
1861 m68k_matches_q_p (rtx x
)
1863 struct m68k_address address
;
1865 return (m68k_legitimate_mem_p (x
, &address
)
1866 && address
.code
== UNKNOWN
1872 /* Return true if X matches the 'U' constraint. It must be a base address
1873 with a constant offset and no index. */
1876 m68k_matches_u_p (rtx x
)
1878 struct m68k_address address
;
1880 return (m68k_legitimate_mem_p (x
, &address
)
1881 && address
.code
== UNKNOWN
1887 /* Legitimize PIC addresses. If the address is already
1888 position-independent, we return ORIG. Newly generated
1889 position-independent addresses go to REG. If we need more
1890 than one register, we lose.
1892 An address is legitimized by making an indirect reference
1893 through the Global Offset Table with the name of the symbol
1896 The assembler and linker are responsible for placing the
1897 address of the symbol in the GOT. The function prologue
1898 is responsible for initializing a5 to the starting address
1901 The assembler is also responsible for translating a symbol name
1902 into a constant displacement from the start of the GOT.
1904 A quick example may make things a little clearer:
1906 When not generating PIC code to store the value 12345 into _foo
1907 we would generate the following code:
1911 When generating PIC two transformations are made. First, the compiler
1912 loads the address of foo into a register. So the first transformation makes:
1917 The code in movsi will intercept the lea instruction and call this
1918 routine which will transform the instructions into:
1920 movel a5@(_foo:w), a0
1924 That (in a nutshell) is how *all* symbol and label references are
1928 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1933 /* First handle a simple SYMBOL_REF or LABEL_REF */
1934 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1938 pic_ref
= gen_rtx_MEM (Pmode
,
1939 gen_rtx_PLUS (Pmode
,
1940 pic_offset_table_rtx
, orig
));
1941 current_function_uses_pic_offset_table
= 1;
1942 MEM_READONLY_P (pic_ref
) = 1;
1943 emit_move_insn (reg
, pic_ref
);
1946 else if (GET_CODE (orig
) == CONST
)
1950 /* Make sure this has not already been legitimized. */
1951 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1952 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1957 /* legitimize both operands of the PLUS */
1958 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1960 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1961 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1962 base
== reg
? 0 : reg
);
1964 if (GET_CODE (orig
) == CONST_INT
)
1965 return plus_constant (base
, INTVAL (orig
));
1966 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1967 /* Likewise, should we set special REG_NOTEs here? */
1973 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1975 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1977 /* Return the type of move that should be used for integer I. */
1980 const_method (HOST_WIDE_INT i
)
1987 /* The ColdFire doesn't have byte or word operations. */
1988 /* FIXME: This may not be useful for the m68060 either. */
1989 if (!TARGET_COLDFIRE
)
1991 /* if -256 < N < 256 but N is not in range for a moveq
1992 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1993 if (USE_MOVQ (i
^ 0xff))
1995 /* Likewise, try with not.w */
1996 if (USE_MOVQ (i
^ 0xffff))
1998 /* This is the only value where neg.w is useful */
2003 /* Try also with swap. */
2005 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2010 /* Try using MVZ/MVS with an immediate value to load constants. */
2011 if (i
>= 0 && i
<= 65535)
2013 if (i
>= -32768 && i
<= 32767)
2017 /* Otherwise, use move.l */
2021 /* Return the cost of moving constant I into a data register. */
2024 const_int_cost (HOST_WIDE_INT i
)
2026 switch (const_method (i
))
2029 /* Constants between -128 and 127 are cheap due to moveq. */
2037 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2047 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2052 /* Constant zero is super cheap due to clr instruction. */
2053 if (x
== const0_rtx
)
2056 *total
= const_int_cost (INTVAL (x
));
2066 /* Make 0.0 cheaper than other floating constants to
2067 encourage creating tstsf and tstdf insns. */
2068 if (outer_code
== COMPARE
2069 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2075 /* These are vaguely right for a 68020. */
2076 /* The costs for long multiply have been adjusted to work properly
2077 in synth_mult on the 68020, relative to an average of the time
2078 for add and the time for shift, taking away a little more because
2079 sometimes move insns are needed. */
2080 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2086 : TARGET_COLDFIRE ? 3 : 13)
2091 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2092 : TARGET_COLDFIRE ? 2 : 8)
2095 (TARGET_CF_HWDIV ? 11 \
2096 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2099 /* An lea costs about three times as much as a simple add. */
2100 if (GET_MODE (x
) == SImode
2101 && GET_CODE (XEXP (x
, 1)) == REG
2102 && GET_CODE (XEXP (x
, 0)) == MULT
2103 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2104 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2105 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2106 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2107 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2109 /* lea an@(dx:l:i),am */
2110 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2120 *total
= COSTS_N_INSNS(1);
2125 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2127 if (INTVAL (XEXP (x
, 1)) < 16)
2128 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2130 /* We're using clrw + swap for these cases. */
2131 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2134 *total
= COSTS_N_INSNS (10); /* Worst case. */
2137 /* A shift by a big integer takes an extra instruction. */
2138 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2139 && (INTVAL (XEXP (x
, 1)) == 16))
2141 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2144 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2145 && !(INTVAL (XEXP (x
, 1)) > 0
2146 && INTVAL (XEXP (x
, 1)) <= 8))
2148 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2154 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2155 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2156 && GET_MODE (x
) == SImode
)
2157 *total
= COSTS_N_INSNS (MULW_COST
);
2158 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2159 *total
= COSTS_N_INSNS (MULW_COST
);
2161 *total
= COSTS_N_INSNS (MULL_COST
);
2168 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2169 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2170 else if (TARGET_CF_HWDIV
)
2171 *total
= COSTS_N_INSNS (18);
2173 *total
= COSTS_N_INSNS (43); /* div.l */
2181 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2185 output_move_const_into_data_reg (rtx
*operands
)
2189 i
= INTVAL (operands
[1]);
2190 switch (const_method (i
))
2193 return "mvzw %1,%0";
2195 return "mvsw %1,%0";
2197 return "moveq %1,%0";
2200 operands
[1] = GEN_INT (i
^ 0xff);
2201 return "moveq %1,%0\n\tnot%.b %0";
2204 operands
[1] = GEN_INT (i
^ 0xffff);
2205 return "moveq %1,%0\n\tnot%.w %0";
2208 return "moveq #-128,%0\n\tneg%.w %0";
2213 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2214 return "moveq %1,%0\n\tswap %0";
2217 return "move%.l %1,%0";
2223 /* Return true if I can be handled by ISA B's mov3q instruction. */
2226 valid_mov3q_const (HOST_WIDE_INT i
)
2228 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2231 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2232 I is the value of OPERANDS[1]. */
2235 output_move_simode_const (rtx
*operands
)
2241 src
= INTVAL (operands
[1]);
2243 && (DATA_REG_P (dest
) || MEM_P (dest
))
2244 /* clr insns on 68000 read before writing. */
2245 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2246 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2248 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2249 return "mov3q%.l %1,%0";
2250 else if (src
== 0 && ADDRESS_REG_P (dest
))
2251 return "sub%.l %0,%0";
2252 else if (DATA_REG_P (dest
))
2253 return output_move_const_into_data_reg (operands
);
2254 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2256 if (valid_mov3q_const (src
))
2257 return "mov3q%.l %1,%0";
2258 return "move%.w %1,%0";
2260 else if (MEM_P (dest
)
2261 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2262 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2263 && IN_RANGE (src
, -0x8000, 0x7fff))
2265 if (valid_mov3q_const (src
))
2266 return "mov3q%.l %1,%-";
2269 return "move%.l %1,%0";
2273 output_move_simode (rtx
*operands
)
2275 if (GET_CODE (operands
[1]) == CONST_INT
)
2276 return output_move_simode_const (operands
);
2277 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2278 || GET_CODE (operands
[1]) == CONST
)
2279 && push_operand (operands
[0], SImode
))
2281 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2282 || GET_CODE (operands
[1]) == CONST
)
2283 && ADDRESS_REG_P (operands
[0]))
2284 return "lea %a1,%0";
2285 return "move%.l %1,%0";
2289 output_move_himode (rtx
*operands
)
2291 if (GET_CODE (operands
[1]) == CONST_INT
)
2293 if (operands
[1] == const0_rtx
2294 && (DATA_REG_P (operands
[0])
2295 || GET_CODE (operands
[0]) == MEM
)
2296 /* clr insns on 68000 read before writing. */
2297 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2298 || !(GET_CODE (operands
[0]) == MEM
2299 && MEM_VOLATILE_P (operands
[0]))))
2301 else if (operands
[1] == const0_rtx
2302 && ADDRESS_REG_P (operands
[0]))
2303 return "sub%.l %0,%0";
2304 else if (DATA_REG_P (operands
[0])
2305 && INTVAL (operands
[1]) < 128
2306 && INTVAL (operands
[1]) >= -128)
2307 return "moveq %1,%0";
2308 else if (INTVAL (operands
[1]) < 0x8000
2309 && INTVAL (operands
[1]) >= -0x8000)
2310 return "move%.w %1,%0";
2312 else if (CONSTANT_P (operands
[1]))
2313 return "move%.l %1,%0";
2314 /* Recognize the insn before a tablejump, one that refers
2315 to a table of offsets. Such an insn will need to refer
2316 to a label on the insn. So output one. Use the label-number
2317 of the table of offsets to generate this label. This code,
2318 and similar code below, assumes that there will be at most one
2319 reference to each table. */
2320 if (GET_CODE (operands
[1]) == MEM
2321 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2322 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2323 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2325 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2327 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2328 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2330 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2331 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2333 return "move%.w %1,%0";
2337 output_move_qimode (rtx
*operands
)
2339 /* 68k family always modifies the stack pointer by at least 2, even for
2340 byte pushes. The 5200 (ColdFire) does not do this. */
2342 /* This case is generated by pushqi1 pattern now. */
2343 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2344 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2345 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2346 && ! ADDRESS_REG_P (operands
[1])
2347 && ! TARGET_COLDFIRE
));
2349 /* clr and st insns on 68000 read before writing. */
2350 if (!ADDRESS_REG_P (operands
[0])
2351 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2352 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2354 if (operands
[1] == const0_rtx
)
2356 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2357 && GET_CODE (operands
[1]) == CONST_INT
2358 && (INTVAL (operands
[1]) & 255) == 255)
2364 if (GET_CODE (operands
[1]) == CONST_INT
2365 && DATA_REG_P (operands
[0])
2366 && INTVAL (operands
[1]) < 128
2367 && INTVAL (operands
[1]) >= -128)
2368 return "moveq %1,%0";
2369 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2370 return "sub%.l %0,%0";
2371 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2372 return "move%.l %1,%0";
2373 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2374 from address registers. */
2375 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2376 return "move%.w %1,%0";
2377 return "move%.b %1,%0";
2381 output_move_stricthi (rtx
*operands
)
2383 if (operands
[1] == const0_rtx
2384 /* clr insns on 68000 read before writing. */
2385 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2386 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2388 return "move%.w %1,%0";
2392 output_move_strictqi (rtx
*operands
)
2394 if (operands
[1] == const0_rtx
2395 /* clr insns on 68000 read before writing. */
2396 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2397 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2399 return "move%.b %1,%0";
2402 /* Return the best assembler insn template
2403 for moving operands[1] into operands[0] as a fullword. */
2406 singlemove_string (rtx
*operands
)
2408 if (GET_CODE (operands
[1]) == CONST_INT
)
2409 return output_move_simode_const (operands
);
2410 return "move%.l %1,%0";
2414 /* Output assembler code to perform a doubleword move insn
2415 with operands OPERANDS. */
2418 output_move_double (rtx
*operands
)
2422 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2427 rtx addreg0
= 0, addreg1
= 0;
2428 int dest_overlapped_low
= 0;
2429 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2434 /* First classify both operands. */
2436 if (REG_P (operands
[0]))
2438 else if (offsettable_memref_p (operands
[0]))
2440 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2442 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2444 else if (GET_CODE (operands
[0]) == MEM
)
2449 if (REG_P (operands
[1]))
2451 else if (CONSTANT_P (operands
[1]))
2453 else if (offsettable_memref_p (operands
[1]))
2455 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2457 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2459 else if (GET_CODE (operands
[1]) == MEM
)
2464 /* Check for the cases that the operand constraints are not supposed
2465 to allow to happen. Generating code for these cases is
2467 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2469 /* If one operand is decrementing and one is incrementing
2470 decrement the former register explicitly
2471 and change that operand into ordinary indexing. */
2473 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2475 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2477 output_asm_insn ("sub%.l #12,%0", operands
);
2479 output_asm_insn ("subq%.l #8,%0", operands
);
2480 if (GET_MODE (operands
[1]) == XFmode
)
2481 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2482 else if (GET_MODE (operands
[0]) == DFmode
)
2483 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2485 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2488 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2490 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2492 output_asm_insn ("sub%.l #12,%1", operands
);
2494 output_asm_insn ("subq%.l #8,%1", operands
);
2495 if (GET_MODE (operands
[1]) == XFmode
)
2496 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2497 else if (GET_MODE (operands
[1]) == DFmode
)
2498 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2500 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2504 /* If an operand is an unoffsettable memory ref, find a register
2505 we can increment temporarily to make it refer to the second word. */
2507 if (optype0
== MEMOP
)
2508 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2510 if (optype1
== MEMOP
)
2511 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2513 /* Ok, we can do one word at a time.
2514 Normally we do the low-numbered word first,
2515 but if either operand is autodecrementing then we
2516 do the high-numbered word first.
2518 In either case, set up in LATEHALF the operands to use
2519 for the high-numbered word and in some cases alter the
2520 operands in OPERANDS to be suitable for the low-numbered word. */
2524 if (optype0
== REGOP
)
2526 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2527 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2529 else if (optype0
== OFFSOP
)
2531 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2532 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2536 middlehalf
[0] = operands
[0];
2537 latehalf
[0] = operands
[0];
2540 if (optype1
== REGOP
)
2542 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2543 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2545 else if (optype1
== OFFSOP
)
2547 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2548 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2550 else if (optype1
== CNSTOP
)
2552 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2557 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2558 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2559 operands
[1] = GEN_INT (l
[0]);
2560 middlehalf
[1] = GEN_INT (l
[1]);
2561 latehalf
[1] = GEN_INT (l
[2]);
2565 /* No non-CONST_DOUBLE constant should ever appear
2567 gcc_assert (!CONSTANT_P (operands
[1]));
2572 middlehalf
[1] = operands
[1];
2573 latehalf
[1] = operands
[1];
2577 /* size is not 12: */
2579 if (optype0
== REGOP
)
2580 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2581 else if (optype0
== OFFSOP
)
2582 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2584 latehalf
[0] = operands
[0];
2586 if (optype1
== REGOP
)
2587 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2588 else if (optype1
== OFFSOP
)
2589 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2590 else if (optype1
== CNSTOP
)
2591 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2593 latehalf
[1] = operands
[1];
2596 /* If insn is effectively movd N(sp),-(sp) then we will do the
2597 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2598 for the low word as well, to compensate for the first decrement of sp. */
2599 if (optype0
== PUSHOP
2600 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2601 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2602 operands
[1] = middlehalf
[1] = latehalf
[1];
2604 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2605 if the upper part of reg N does not appear in the MEM, arrange to
2606 emit the move late-half first. Otherwise, compute the MEM address
2607 into the upper part of N and use that as a pointer to the memory
2609 if (optype0
== REGOP
2610 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2612 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2614 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2615 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2617 /* If both halves of dest are used in the src memory address,
2618 compute the address into latehalf of dest.
2619 Note that this can't happen if the dest is two data regs. */
2621 xops
[0] = latehalf
[0];
2622 xops
[1] = XEXP (operands
[1], 0);
2623 output_asm_insn ("lea %a1,%0", xops
);
2624 if (GET_MODE (operands
[1]) == XFmode
)
2626 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2627 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2628 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2632 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2633 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2637 && reg_overlap_mentioned_p (middlehalf
[0],
2638 XEXP (operands
[1], 0)))
2640 /* Check for two regs used by both source and dest.
2641 Note that this can't happen if the dest is all data regs.
2642 It can happen if the dest is d6, d7, a0.
2643 But in that case, latehalf is an addr reg, so
2644 the code at compadr does ok. */
2646 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2647 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2650 /* JRV says this can't happen: */
2651 gcc_assert (!addreg0
&& !addreg1
);
2653 /* Only the middle reg conflicts; simply put it last. */
2654 output_asm_insn (singlemove_string (operands
), operands
);
2655 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2656 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2659 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2660 /* If the low half of dest is mentioned in the source memory
2661 address, the arrange to emit the move late half first. */
2662 dest_overlapped_low
= 1;
2665 /* If one or both operands autodecrementing,
2666 do the two words, high-numbered first. */
2668 /* Likewise, the first move would clobber the source of the second one,
2669 do them in the other order. This happens only for registers;
2670 such overlap can't happen in memory unless the user explicitly
2671 sets it up, and that is an undefined circumstance. */
2673 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2674 || (optype0
== REGOP
&& optype1
== REGOP
2675 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2676 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2677 || dest_overlapped_low
)
2679 /* Make any unoffsettable addresses point at high-numbered word. */
2683 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2685 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2690 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2692 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2696 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2698 /* Undo the adds we just did. */
2700 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2702 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2706 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2708 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2710 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2713 /* Do low-numbered word. */
2714 return singlemove_string (operands
);
2717 /* Normal case: do the two words, low-numbered first. */
2719 output_asm_insn (singlemove_string (operands
), operands
);
2721 /* Do the middle one of the three words for long double */
2725 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2727 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2729 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2732 /* Make any unoffsettable addresses point at high-numbered word. */
2734 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2736 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2739 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2741 /* Undo the adds we just did. */
2745 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2747 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2752 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2754 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2761 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2762 new rtx with the correct mode. */
2765 force_mode (enum machine_mode mode
, rtx orig
)
2767 if (mode
== GET_MODE (orig
))
2770 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2773 return gen_rtx_REG (mode
, REGNO (orig
));
2777 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2779 return reg_renumber
&& FP_REG_P (op
);
2782 /* Emit insns to move operands[1] into operands[0].
2784 Return 1 if we have written out everything that needs to be done to
2785 do the move. Otherwise, return 0 and the caller will emit the move
2788 Note SCRATCH_REG may not be in the proper mode depending on how it
2789 will be used. This routine is responsible for creating a new copy
2790 of SCRATCH_REG in the proper mode. */
2793 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2795 register rtx operand0
= operands
[0];
2796 register rtx operand1
= operands
[1];
2800 && reload_in_progress
&& GET_CODE (operand0
) == REG
2801 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2802 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2803 else if (scratch_reg
2804 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2805 && GET_CODE (SUBREG_REG (operand0
)) == REG
2806 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2808 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2809 the code which tracks sets/uses for delete_output_reload. */
2810 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2811 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2812 SUBREG_BYTE (operand0
));
2813 operand0
= alter_subreg (&temp
);
2817 && reload_in_progress
&& GET_CODE (operand1
) == REG
2818 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2819 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2820 else if (scratch_reg
2821 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2822 && GET_CODE (SUBREG_REG (operand1
)) == REG
2823 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2825 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2826 the code which tracks sets/uses for delete_output_reload. */
2827 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2828 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2829 SUBREG_BYTE (operand1
));
2830 operand1
= alter_subreg (&temp
);
2833 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2834 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2835 != XEXP (operand0
, 0)))
2836 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2837 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2838 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2839 != XEXP (operand1
, 0)))
2840 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2842 /* Handle secondary reloads for loads/stores of FP registers where
2843 the address is symbolic by using the scratch register */
2844 if (fp_reg_operand (operand0
, mode
)
2845 && ((GET_CODE (operand1
) == MEM
2846 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2847 || ((GET_CODE (operand1
) == SUBREG
2848 && GET_CODE (XEXP (operand1
, 0)) == MEM
2849 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2852 if (GET_CODE (operand1
) == SUBREG
)
2853 operand1
= XEXP (operand1
, 0);
2855 /* SCRATCH_REG will hold an address. We want
2856 it in SImode regardless of what mode it was originally given
2858 scratch_reg
= force_mode (SImode
, scratch_reg
);
2860 /* D might not fit in 14 bits either; for such cases load D into
2862 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2864 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2865 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2867 XEXP (XEXP (operand1
, 0), 0),
2871 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2872 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2873 gen_rtx_MEM (mode
, scratch_reg
)));
2876 else if (fp_reg_operand (operand1
, mode
)
2877 && ((GET_CODE (operand0
) == MEM
2878 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2879 || ((GET_CODE (operand0
) == SUBREG
)
2880 && GET_CODE (XEXP (operand0
, 0)) == MEM
2881 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2884 if (GET_CODE (operand0
) == SUBREG
)
2885 operand0
= XEXP (operand0
, 0);
2887 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2888 it in SIMODE regardless of what mode it was originally given
2890 scratch_reg
= force_mode (SImode
, scratch_reg
);
2892 /* D might not fit in 14 bits either; for such cases load D into
2894 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2896 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2897 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2900 XEXP (XEXP (operand0
, 0),
2905 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2906 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2910 /* Handle secondary reloads for loads of FP registers from constant
2911 expressions by forcing the constant into memory.
2913 use scratch_reg to hold the address of the memory location.
2915 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2916 NO_REGS when presented with a const_int and an register class
2917 containing only FP registers. Doing so unfortunately creates
2918 more problems than it solves. Fix this for 2.5. */
2919 else if (fp_reg_operand (operand0
, mode
)
2920 && CONSTANT_P (operand1
)
2925 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2926 it in SIMODE regardless of what mode it was originally given
2928 scratch_reg
= force_mode (SImode
, scratch_reg
);
2930 /* Force the constant into memory and put the address of the
2931 memory location into scratch_reg. */
2932 xoperands
[0] = scratch_reg
;
2933 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2934 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2936 /* Now load the destination register. */
2937 emit_insn (gen_rtx_SET (mode
, operand0
,
2938 gen_rtx_MEM (mode
, scratch_reg
)));
2942 /* Now have insn-emit do whatever it normally does. */
2946 /* Split one or more DImode RTL references into pairs of SImode
2947 references. The RTL can be REG, offsettable MEM, integer constant, or
2948 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2949 split and "num" is its length. lo_half and hi_half are output arrays
2950 that parallel "operands". */
2953 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2957 rtx op
= operands
[num
];
2959 /* simplify_subreg refuses to split volatile memory addresses,
2960 but we still have to handle it. */
2961 if (GET_CODE (op
) == MEM
)
2963 lo_half
[num
] = adjust_address (op
, SImode
, 4);
2964 hi_half
[num
] = adjust_address (op
, SImode
, 0);
2968 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2969 GET_MODE (op
) == VOIDmode
2970 ? DImode
: GET_MODE (op
), 4);
2971 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2972 GET_MODE (op
) == VOIDmode
2973 ? DImode
: GET_MODE (op
), 0);
2978 /* Split X into a base and a constant offset, storing them in *BASE
2979 and *OFFSET respectively. */
2982 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
2985 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2987 *offset
+= INTVAL (XEXP (x
, 1));
2993 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
2994 instruction. STORE_P says whether the move is a load or store.
2996 If the instruction uses post-increment or pre-decrement addressing,
2997 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
2998 adjustment. This adjustment will be made by the first element of
2999 PARALLEL, with the loads or stores starting at element 1. If the
3000 instruction does not use post-increment or pre-decrement addressing,
3001 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3002 start at element 0. */
3005 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3006 HOST_WIDE_INT automod_offset
, bool store_p
)
3008 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3009 HOST_WIDE_INT offset
, mem_offset
;
3011 enum reg_class rclass
;
3013 len
= XVECLEN (pattern
, 0);
3014 first
= (automod_base
!= NULL
);
3018 /* Stores must be pre-decrement and loads must be post-increment. */
3019 if (store_p
!= (automod_offset
< 0))
3022 /* Work out the base and offset for lowest memory location. */
3023 base
= automod_base
;
3024 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3028 /* Allow any valid base and offset in the first access. */
3035 for (i
= first
; i
< len
; i
++)
3037 /* We need a plain SET. */
3038 set
= XVECEXP (pattern
, 0, i
);
3039 if (GET_CODE (set
) != SET
)
3042 /* Check that we have a memory location... */
3043 mem
= XEXP (set
, !store_p
);
3044 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3047 /* ...with the right address. */
3050 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3051 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3052 There are no mode restrictions for 680x0 besides the
3053 automodification rules enforced above. */
3055 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3060 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3061 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3065 /* Check that we have a register of the required mode and class. */
3066 reg
= XEXP (set
, store_p
);
3068 || !HARD_REGISTER_P (reg
)
3069 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3074 /* The register must belong to RCLASS and have a higher number
3075 than the register in the previous SET. */
3076 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3077 || REGNO (last_reg
) >= REGNO (reg
))
3082 /* Work out which register class we need. */
3083 if (INT_REGNO_P (REGNO (reg
)))
3084 rclass
= GENERAL_REGS
;
3085 else if (FP_REGNO_P (REGNO (reg
)))
3092 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3095 /* If we have an automodification, check whether the final offset is OK. */
3096 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3099 /* Reject unprofitable cases. */
3100 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3106 /* Return the assembly code template for a movem or fmovem instruction
3107 whose pattern is given by PATTERN. Store the template's operands
3110 If the instruction uses post-increment or pre-decrement addressing,
3111 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3112 is true if this is a store instruction. */
3115 m68k_output_movem (rtx
*operands
, rtx pattern
,
3116 HOST_WIDE_INT automod_offset
, bool store_p
)
3121 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3123 first
= (automod_offset
!= 0);
3124 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3126 /* When using movem with pre-decrement addressing, register X + D0_REG
3127 is controlled by bit 15 - X. For all other addressing modes,
3128 register X + D0_REG is controlled by bit X. Confusingly, the
3129 register mask for fmovem is in the opposite order to that for
3133 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3134 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3135 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3136 if (automod_offset
< 0)
3138 if (FP_REGNO_P (regno
))
3139 mask
|= 1 << (regno
- FP0_REG
);
3141 mask
|= 1 << (15 - (regno
- D0_REG
));
3145 if (FP_REGNO_P (regno
))
3146 mask
|= 1 << (7 - (regno
- FP0_REG
));
3148 mask
|= 1 << (regno
- D0_REG
);
3153 if (automod_offset
== 0)
3154 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3155 else if (automod_offset
< 0)
3156 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3158 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3159 operands
[1] = GEN_INT (mask
);
3160 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3163 return MOTOROLA
? "fmovm %1,%a0" : "fmovem %1,%a0";
3165 return MOTOROLA
? "fmovm %a0,%1" : "fmovem %a0,%1";
3170 return MOTOROLA
? "movm.l %1,%a0" : "moveml %1,%a0";
3172 return MOTOROLA
? "movm.l %a0,%1" : "moveml %a0,%1";
3176 /* Return a REG that occurs in ADDR with coefficient 1.
3177 ADDR can be effectively incremented by incrementing REG. */
3180 find_addr_reg (rtx addr
)
3182 while (GET_CODE (addr
) == PLUS
)
3184 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3185 addr
= XEXP (addr
, 0);
3186 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3187 addr
= XEXP (addr
, 1);
3188 else if (CONSTANT_P (XEXP (addr
, 0)))
3189 addr
= XEXP (addr
, 1);
3190 else if (CONSTANT_P (XEXP (addr
, 1)))
3191 addr
= XEXP (addr
, 0);
3195 gcc_assert (GET_CODE (addr
) == REG
);
3199 /* Output assembler code to perform a 32-bit 3-operand add. */
3202 output_addsi3 (rtx
*operands
)
3204 if (! operands_match_p (operands
[0], operands
[1]))
3206 if (!ADDRESS_REG_P (operands
[1]))
3208 rtx tmp
= operands
[1];
3210 operands
[1] = operands
[2];
3214 /* These insns can result from reloads to access
3215 stack slots over 64k from the frame pointer. */
3216 if (GET_CODE (operands
[2]) == CONST_INT
3217 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3218 return "move%.l %2,%0\n\tadd%.l %1,%0";
3219 if (GET_CODE (operands
[2]) == REG
)
3220 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3221 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3223 if (GET_CODE (operands
[2]) == CONST_INT
)
3225 if (INTVAL (operands
[2]) > 0
3226 && INTVAL (operands
[2]) <= 8)
3227 return "addq%.l %2,%0";
3228 if (INTVAL (operands
[2]) < 0
3229 && INTVAL (operands
[2]) >= -8)
3231 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3232 return "subq%.l %2,%0";
3234 /* On the CPU32 it is faster to use two addql instructions to
3235 add a small integer (8 < N <= 16) to a register.
3236 Likewise for subql. */
3237 if (TUNE_CPU32
&& REG_P (operands
[0]))
3239 if (INTVAL (operands
[2]) > 8
3240 && INTVAL (operands
[2]) <= 16)
3242 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3243 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3245 if (INTVAL (operands
[2]) < -8
3246 && INTVAL (operands
[2]) >= -16)
3248 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3249 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3252 if (ADDRESS_REG_P (operands
[0])
3253 && INTVAL (operands
[2]) >= -0x8000
3254 && INTVAL (operands
[2]) < 0x8000)
3257 return "add%.w %2,%0";
3259 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3262 return "add%.l %2,%0";
3265 /* Store in cc_status the expressions that the condition codes will
3266 describe after execution of an instruction whose pattern is EXP.
3267 Do not alter them if the instruction would not alter the cc's. */
3269 /* On the 68000, all the insns to store in an address register fail to
3270 set the cc's. However, in some cases these instructions can make it
3271 possibly invalid to use the saved cc's. In those cases we clear out
3272 some or all of the saved cc's so they won't be used. */
3275 notice_update_cc (rtx exp
, rtx insn
)
3277 if (GET_CODE (exp
) == SET
)
3279 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3281 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3283 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3284 cc_status
.value1
= 0;
3285 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3286 cc_status
.value2
= 0;
3288 /* fmoves to memory or data registers do not set the condition
3289 codes. Normal moves _do_ set the condition codes, but not in
3290 a way that is appropriate for comparison with 0, because -0.0
3291 would be treated as a negative nonzero number. Note that it
3292 isn't appropriate to conditionalize this restriction on
3293 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3294 we care about the difference between -0.0 and +0.0. */
3295 else if (!FP_REG_P (SET_DEST (exp
))
3296 && SET_DEST (exp
) != cc0_rtx
3297 && (FP_REG_P (SET_SRC (exp
))
3298 || GET_CODE (SET_SRC (exp
)) == FIX
3299 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3301 /* A pair of move insns doesn't produce a useful overall cc. */
3302 else if (!FP_REG_P (SET_DEST (exp
))
3303 && !FP_REG_P (SET_SRC (exp
))
3304 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3305 && (GET_CODE (SET_SRC (exp
)) == REG
3306 || GET_CODE (SET_SRC (exp
)) == MEM
3307 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3309 else if (SET_DEST (exp
) != pc_rtx
)
3311 cc_status
.flags
= 0;
3312 cc_status
.value1
= SET_DEST (exp
);
3313 cc_status
.value2
= SET_SRC (exp
);
3316 else if (GET_CODE (exp
) == PARALLEL
3317 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3319 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3320 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3322 if (ADDRESS_REG_P (dest
))
3324 else if (dest
!= pc_rtx
)
3326 cc_status
.flags
= 0;
3327 cc_status
.value1
= dest
;
3328 cc_status
.value2
= src
;
3333 if (cc_status
.value2
!= 0
3334 && ADDRESS_REG_P (cc_status
.value2
)
3335 && GET_MODE (cc_status
.value2
) == QImode
)
3337 if (cc_status
.value2
!= 0)
3338 switch (GET_CODE (cc_status
.value2
))
3340 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3341 case ROTATE
: case ROTATERT
:
3342 /* These instructions always clear the overflow bit, and set
3343 the carry to the bit shifted out. */
3344 /* ??? We don't currently have a way to signal carry not valid,
3345 nor do we check for it in the branch insns. */
3349 case PLUS
: case MINUS
: case MULT
:
3350 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3351 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3352 cc_status
.flags
|= CC_NO_OVERFLOW
;
3355 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3356 ends with a move insn moving r2 in r2's mode.
3357 Thus, the cc's are set for r2.
3358 This can set N bit spuriously. */
3359 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3364 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3366 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3367 cc_status
.value2
= 0;
3368 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3369 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3370 cc_status
.flags
= CC_IN_68881
;
3374 output_move_const_double (rtx
*operands
)
3376 int code
= standard_68881_constant_p (operands
[1]);
3380 static char buf
[40];
3382 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3385 return "fmove%.d %1,%0";
3389 output_move_const_single (rtx
*operands
)
3391 int code
= standard_68881_constant_p (operands
[1]);
3395 static char buf
[40];
3397 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3400 return "fmove%.s %f1,%0";
3403 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3404 from the "fmovecr" instruction.
3405 The value, anded with 0xff, gives the code to use in fmovecr
3406 to get the desired constant. */
3408 /* This code has been fixed for cross-compilation. */
3410 static int inited_68881_table
= 0;
3412 static const char *const strings_68881
[7] = {
3422 static const int codes_68881
[7] = {
3432 REAL_VALUE_TYPE values_68881
[7];
3434 /* Set up values_68881 array by converting the decimal values
3435 strings_68881 to binary. */
3438 init_68881_table (void)
3442 enum machine_mode mode
;
3445 for (i
= 0; i
< 7; i
++)
3449 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3450 values_68881
[i
] = r
;
3452 inited_68881_table
= 1;
3456 standard_68881_constant_p (rtx x
)
3461 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3462 used at all on those chips. */
3466 if (! inited_68881_table
)
3467 init_68881_table ();
3469 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3471 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3473 for (i
= 0; i
< 6; i
++)
3475 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3476 return (codes_68881
[i
]);
3479 if (GET_MODE (x
) == SFmode
)
3482 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3483 return (codes_68881
[6]);
3485 /* larger powers of ten in the constants ram are not used
3486 because they are not equal to a `double' C constant. */
3490 /* If X is a floating-point constant, return the logarithm of X base 2,
3491 or 0 if X is not a power of 2. */
3494 floating_exact_log2 (rtx x
)
3496 REAL_VALUE_TYPE r
, r1
;
3499 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3501 if (REAL_VALUES_LESS (r
, dconst1
))
3504 exp
= real_exponent (&r
);
3505 real_2expN (&r1
, exp
);
3506 if (REAL_VALUES_EQUAL (r1
, r
))
3512 /* A C compound statement to output to stdio stream STREAM the
3513 assembler syntax for an instruction operand X. X is an RTL
3516 CODE is a value that can be used to specify one of several ways
3517 of printing the operand. It is used when identical operands
3518 must be printed differently depending on the context. CODE
3519 comes from the `%' specification that was used to request
3520 printing of the operand. If the specification was just `%DIGIT'
3521 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3522 is the ASCII code for LTR.
3524 If X is a register, this macro should print the register's name.
3525 The names can be found in an array `reg_names' whose type is
3526 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3528 When the machine description has a specification `%PUNCT' (a `%'
3529 followed by a punctuation character), this macro is called with
3530 a null pointer for X and the punctuation character for CODE.
3532 The m68k specific codes are:
3534 '.' for dot needed in Motorola-style opcode names.
3535 '-' for an operand pushing on the stack:
3536 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3537 '+' for an operand pushing on the stack:
3538 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3539 '@' for a reference to the top word on the stack:
3540 sp@, (sp) or (%sp) depending on the style of syntax.
3541 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3542 but & in SGS syntax).
3543 '!' for the cc register (used in an `and to cc' insn).
3544 '$' for the letter `s' in an op code, but only on the 68040.
3545 '&' for the letter `d' in an op code, but only on the 68040.
3546 '/' for register prefix needed by longlong.h.
3547 '?' for m68k_library_id_string
3549 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3550 'd' to force memory addressing to be absolute, not relative.
3551 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3552 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3553 or print pair of registers as rx:ry.
3554 'p' print an address with @PLTPC attached, but only if the operand
3555 is not locally-bound. */
3558 print_operand (FILE *file
, rtx op
, int letter
)
3563 fprintf (file
, ".");
3565 else if (letter
== '#')
3566 asm_fprintf (file
, "%I");
3567 else if (letter
== '-')
3568 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3569 else if (letter
== '+')
3570 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3571 else if (letter
== '@')
3572 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3573 else if (letter
== '!')
3574 asm_fprintf (file
, "%Rfpcr");
3575 else if (letter
== '$')
3578 fprintf (file
, "s");
3580 else if (letter
== '&')
3583 fprintf (file
, "d");
3585 else if (letter
== '/')
3586 asm_fprintf (file
, "%R");
3587 else if (letter
== '?')
3588 asm_fprintf (file
, m68k_library_id_string
);
3589 else if (letter
== 'p')
3591 output_addr_const (file
, op
);
3592 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3593 fprintf (file
, "@PLTPC");
3595 else if (GET_CODE (op
) == REG
)
3598 /* Print out the second register name of a register pair.
3599 I.e., R (6) => 7. */
3600 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3602 fputs (M68K_REGNAME(REGNO (op
)), file
);
3604 else if (GET_CODE (op
) == MEM
)
3606 output_address (XEXP (op
, 0));
3607 if (letter
== 'd' && ! TARGET_68020
3608 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3609 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3610 && INTVAL (XEXP (op
, 0)) < 0x8000
3611 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3612 fprintf (file
, MOTOROLA
? ".l" : ":l");
3614 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3617 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3618 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3620 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3623 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3624 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3626 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3629 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3630 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3634 /* Use `print_operand_address' instead of `output_addr_const'
3635 to ensure that we print relevant PIC stuff. */
3636 asm_fprintf (file
, "%I");
3638 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3639 print_operand_address (file
, op
);
3641 output_addr_const (file
, op
);
3646 /* A C compound statement to output to stdio stream STREAM the
3647 assembler syntax for an instruction operand that is a memory
3648 reference whose address is ADDR. ADDR is an RTL expression.
3650 Note that this contains a kludge that knows that the only reason
3651 we have an address (plus (label_ref...) (reg...)) when not generating
3652 PIC code is in the insn before a tablejump, and we know that m68k.md
3653 generates a label LInnn: on such an insn.
3655 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3656 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3658 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3659 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3660 we want. This difference can be accommodated by using an assembler
3661 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3662 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3663 macro. See m68k/sgs.h for an example; for versions without the bug.
3664 Some assemblers refuse all the above solutions. The workaround is to
3665 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3668 They also do not like things like "pea 1.w", so we simple leave off
3669 the .w on small constants.
3671 This routine is responsible for distinguishing between -fpic and -fPIC
3672 style relocations in an address. When generating -fpic code the
3673 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3674 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3677 print_operand_address (FILE *file
, rtx addr
)
3679 struct m68k_address address
;
3681 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3684 if (address
.code
== PRE_DEC
)
3685 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3686 M68K_REGNAME (REGNO (address
.base
)));
3687 else if (address
.code
== POST_INC
)
3688 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3689 M68K_REGNAME (REGNO (address
.base
)));
3690 else if (!address
.base
&& !address
.index
)
3692 /* A constant address. */
3693 gcc_assert (address
.offset
== addr
);
3694 if (GET_CODE (addr
) == CONST_INT
)
3696 /* (xxx).w or (xxx).l. */
3697 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3698 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3700 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3702 else if (TARGET_PCREL
)
3704 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3706 output_addr_const (file
, addr
);
3707 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3711 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3712 name ends in `.<letter>', as the last 2 characters can be
3713 mistaken as a size suffix. Put the name in parentheses. */
3714 if (GET_CODE (addr
) == SYMBOL_REF
3715 && strlen (XSTR (addr
, 0)) > 2
3716 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3719 output_addr_const (file
, addr
);
3723 output_addr_const (file
, addr
);
3730 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3731 label being acceesed, otherwise it is -1. */
3732 labelno
= (address
.offset
3734 && GET_CODE (address
.offset
) == LABEL_REF
3735 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3739 /* Print the "offset(base" component. */
3741 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3746 output_addr_const (file
, address
.offset
);
3747 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3749 fprintf (file
, "@GOT");
3750 if (flag_pic
== 1 && TARGET_68020
)
3751 fprintf (file
, ".w");
3756 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3758 /* Print the ",index" component, if any. */
3763 fprintf (file
, "%s.%c",
3764 M68K_REGNAME (REGNO (address
.index
)),
3765 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3766 if (address
.scale
!= 1)
3767 fprintf (file
, "*%d", address
.scale
);
3771 else /* !MOTOROLA */
3773 if (!address
.offset
&& !address
.index
)
3774 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3777 /* Print the "base@(offset" component. */
3779 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3783 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3784 fprintf (file
, "@(");
3787 output_addr_const (file
, address
.offset
);
3788 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3792 fprintf (file
, ":w"); break;
3794 fprintf (file
, ":l"); break;
3800 /* Print the ",index" component, if any. */
3803 fprintf (file
, ",%s:%c",
3804 M68K_REGNAME (REGNO (address
.index
)),
3805 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3806 if (address
.scale
!= 1)
3807 fprintf (file
, ":%d", address
.scale
);
3815 /* Check for cases where a clr insns can be omitted from code using
3816 strict_low_part sets. For example, the second clrl here is not needed:
3817 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3819 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3820 insn we are checking for redundancy. TARGET is the register set by the
3824 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3829 p
= prev_nonnote_insn (first_insn
);
3833 /* If it isn't an insn, then give up. */
3834 if (GET_CODE (p
) != INSN
)
3837 if (reg_set_p (target
, p
))
3839 rtx set
= single_set (p
);
3842 /* If it isn't an easy to recognize insn, then give up. */
3846 dest
= SET_DEST (set
);
3848 /* If this sets the entire target register to zero, then our
3849 first_insn is redundant. */
3850 if (rtx_equal_p (dest
, target
)
3851 && SET_SRC (set
) == const0_rtx
)
3853 else if (GET_CODE (dest
) == STRICT_LOW_PART
3854 && GET_CODE (XEXP (dest
, 0)) == REG
3855 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3856 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3857 <= GET_MODE_SIZE (mode
)))
3858 /* This is a strict low part set which modifies less than
3859 we are using, so it is safe. */
3865 p
= prev_nonnote_insn (p
);
3871 /* Operand predicates for implementing asymmetric pc-relative addressing
3872 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3873 when used as a source operand, but not as a destination operand.
3875 We model this by restricting the meaning of the basic predicates
3876 (general_operand, memory_operand, etc) to forbid the use of this
3877 addressing mode, and then define the following predicates that permit
3878 this addressing mode. These predicates can then be used for the
3879 source operands of the appropriate instructions.
3881 n.b. While it is theoretically possible to change all machine patterns
3882 to use this addressing more where permitted by the architecture,
3883 it has only been implemented for "common" cases: SImode, HImode, and
3884 QImode operands, and only for the principle operations that would
3885 require this addressing mode: data movement and simple integer operations.
3887 In parallel with these new predicates, two new constraint letters
3888 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3889 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3890 In the pcrel case 's' is only valid in combination with 'a' registers.
3891 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3892 of how these constraints are used.
3894 The use of these predicates is strictly optional, though patterns that
3895 don't will cause an extra reload register to be allocated where one
3898 lea (abc:w,%pc),%a0 ; need to reload address
3899 moveq &1,%d1 ; since write to pc-relative space
3900 movel %d1,%a0@ ; is not allowed
3902 lea (abc:w,%pc),%a1 ; no need to reload address here
3903 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3905 For more info, consult tiemann@cygnus.com.
3908 All of the ugliness with predicates and constraints is due to the
3909 simple fact that the m68k does not allow a pc-relative addressing
3910 mode as a destination. gcc does not distinguish between source and
3911 destination addresses. Hence, if we claim that pc-relative address
3912 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3913 end up with invalid code. To get around this problem, we left
3914 pc-relative modes as invalid addresses, and then added special
3915 predicates and constraints to accept them.
3917 A cleaner way to handle this is to modify gcc to distinguish
3918 between source and destination addresses. We can then say that
3919 pc-relative is a valid source address but not a valid destination
3920 address, and hopefully avoid a lot of the predicate and constraint
3921 hackery. Unfortunately, this would be a pretty big change. It would
3922 be a useful change for a number of ports, but there aren't any current
3923 plans to undertake this.
3925 ***************************************************************************/
3929 output_andsi3 (rtx
*operands
)
3932 if (GET_CODE (operands
[2]) == CONST_INT
3933 && (INTVAL (operands
[2]) | 0xffff) == -1
3934 && (DATA_REG_P (operands
[0])
3935 || offsettable_memref_p (operands
[0]))
3936 && !TARGET_COLDFIRE
)
3938 if (GET_CODE (operands
[0]) != REG
)
3939 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3940 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3941 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3943 if (operands
[2] == const0_rtx
)
3945 return "and%.w %2,%0";
3947 if (GET_CODE (operands
[2]) == CONST_INT
3948 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3949 && (DATA_REG_P (operands
[0])
3950 || offsettable_memref_p (operands
[0])))
3952 if (DATA_REG_P (operands
[0]))
3953 operands
[1] = GEN_INT (logval
);
3956 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3957 operands
[1] = GEN_INT (logval
% 8);
3959 /* This does not set condition codes in a standard way. */
3961 return "bclr %1,%0";
3963 return "and%.l %2,%0";
3967 output_iorsi3 (rtx
*operands
)
3969 register int logval
;
3970 if (GET_CODE (operands
[2]) == CONST_INT
3971 && INTVAL (operands
[2]) >> 16 == 0
3972 && (DATA_REG_P (operands
[0])
3973 || offsettable_memref_p (operands
[0]))
3974 && !TARGET_COLDFIRE
)
3976 if (GET_CODE (operands
[0]) != REG
)
3977 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3978 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3980 if (INTVAL (operands
[2]) == 0xffff)
3981 return "mov%.w %2,%0";
3982 return "or%.w %2,%0";
3984 if (GET_CODE (operands
[2]) == CONST_INT
3985 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3986 && (DATA_REG_P (operands
[0])
3987 || offsettable_memref_p (operands
[0])))
3989 if (DATA_REG_P (operands
[0]))
3990 operands
[1] = GEN_INT (logval
);
3993 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3994 operands
[1] = GEN_INT (logval
% 8);
3997 return "bset %1,%0";
3999 return "or%.l %2,%0";
4003 output_xorsi3 (rtx
*operands
)
4005 register int logval
;
4006 if (GET_CODE (operands
[2]) == CONST_INT
4007 && INTVAL (operands
[2]) >> 16 == 0
4008 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4009 && !TARGET_COLDFIRE
)
4011 if (! DATA_REG_P (operands
[0]))
4012 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4013 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4015 if (INTVAL (operands
[2]) == 0xffff)
4017 return "eor%.w %2,%0";
4019 if (GET_CODE (operands
[2]) == CONST_INT
4020 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4021 && (DATA_REG_P (operands
[0])
4022 || offsettable_memref_p (operands
[0])))
4024 if (DATA_REG_P (operands
[0]))
4025 operands
[1] = GEN_INT (logval
);
4028 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4029 operands
[1] = GEN_INT (logval
% 8);
4032 return "bchg %1,%0";
4034 return "eor%.l %2,%0";
4037 /* Return the instruction that should be used for a call to address X,
4038 which is known to be in operand 0. */
4043 if (symbolic_operand (x
, VOIDmode
))
4044 return m68k_symbolic_call
;
4049 /* Likewise sibling calls. */
4052 output_sibcall (rtx x
)
4054 if (symbolic_operand (x
, VOIDmode
))
4055 return m68k_symbolic_jump
;
4060 #ifdef M68K_TARGET_COFF
4062 /* Output assembly to switch to section NAME with attribute FLAGS. */
4065 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4066 tree decl ATTRIBUTE_UNUSED
)
4070 if (flags
& SECTION_WRITE
)
4075 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4078 #endif /* M68K_TARGET_COFF */
4081 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4082 HOST_WIDE_INT delta
,
4083 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
4089 if (delta
> 0 && delta
<= 8)
4090 asm_fprintf (file
, (MOTOROLA
4091 ? "\taddq.l %I%d,4(%Rsp)\n"
4092 : "\taddql %I%d,%Rsp@(4)\n"),
4094 else if (delta
< 0 && delta
>= -8)
4095 asm_fprintf (file
, (MOTOROLA
4096 ? "\tsubq.l %I%d,4(%Rsp)\n"
4097 : "\tsubql %I%d,%Rsp@(4)\n"),
4099 else if (TARGET_COLDFIRE
)
4101 /* ColdFire can't add/sub a constant to memory unless it is in
4102 the range of addq/subq. So load the value into %d0 and
4103 then add it to 4(%sp). */
4104 if (delta
>= -128 && delta
<= 127)
4105 asm_fprintf (file
, (MOTOROLA
4106 ? "\tmoveq.l %I%wd,%Rd0\n"
4107 : "\tmoveql %I%wd,%Rd0\n"),
4110 asm_fprintf (file
, (MOTOROLA
4111 ? "\tmove.l %I%wd,%Rd0\n"
4112 : "\tmovel %I%wd,%Rd0\n"),
4114 asm_fprintf (file
, (MOTOROLA
4115 ? "\tadd.l %Rd0,4(%Rsp)\n"
4116 : "\taddl %Rd0,%Rsp@(4)\n"));
4119 asm_fprintf (file
, (MOTOROLA
4120 ? "\tadd.l %I%wd,4(%Rsp)\n"
4121 : "\taddl %I%wd,%Rsp@(4)\n"),
4124 xops
[0] = DECL_RTL (function
);
4126 gcc_assert (MEM_P (xops
[0])
4127 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
4128 xops
[0] = XEXP (xops
[0], 0);
4130 fmt
= m68k_symbolic_jump
;
4131 if (m68k_symbolic_jump
== NULL
)
4132 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
4134 output_asm_insn (fmt
, xops
);
4137 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4140 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4141 int incoming ATTRIBUTE_UNUSED
)
4143 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4146 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4148 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4149 unsigned int new_reg
)
4152 /* Interrupt functions can only use registers that have already been
4153 saved by the prologue, even if they would normally be
4156 if (m68k_interrupt_function_p (current_function_decl
)
4157 && !regs_ever_live
[new_reg
])
4163 /* Value is true if hard register REGNO can hold a value of machine-mode
4164 MODE. On the 68000, we let the cpu registers can hold any mode, but
4165 restrict the 68881 registers to floating-point modes. */
4168 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4170 if (DATA_REGNO_P (regno
))
4172 /* Data Registers, can hold aggregate if fits in. */
4173 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4176 else if (ADDRESS_REGNO_P (regno
))
4178 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4181 else if (FP_REGNO_P (regno
))
4183 /* FPU registers, hold float or complex float of long double or
4185 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4186 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4187 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4193 /* Implement SECONDARY_RELOAD_CLASS. */
4196 m68k_secondary_reload_class (enum reg_class rclass
,
4197 enum machine_mode mode
, rtx x
)
4201 regno
= true_regnum (x
);
4203 /* If one operand of a movqi is an address register, the other
4204 operand must be a general register or constant. Other types
4205 of operand must be reloaded through a data register. */
4206 if (GET_MODE_SIZE (mode
) == 1
4207 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
4208 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
4211 /* PC-relative addresses must be loaded into an address register first. */
4213 && !reg_class_subset_p (rclass
, ADDR_REGS
)
4214 && symbolic_operand (x
, VOIDmode
))
4220 /* Implement PREFERRED_RELOAD_CLASS. */
4223 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
4225 enum reg_class secondary_class
;
4227 /* If RCLASS might need a secondary reload, try restricting it to
4228 a class that doesn't. */
4229 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
4230 if (secondary_class
!= NO_REGS
4231 && reg_class_subset_p (secondary_class
, rclass
))
4232 return secondary_class
;
4234 /* Prefer to use moveq for in-range constants. */
4235 if (GET_CODE (x
) == CONST_INT
4236 && reg_class_subset_p (DATA_REGS
, rclass
)
4237 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
4240 /* ??? Do we really need this now? */
4241 if (GET_CODE (x
) == CONST_DOUBLE
4242 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4244 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
4253 /* Return floating point values in a 68881 register. This makes 68881 code
4254 a little bit faster. It also makes -msoft-float code incompatible with
4255 hard-float code, so people have to be careful not to mix the two.
4256 For ColdFire it was decided the ABI incompatibility is undesirable.
4257 If there is need for a hard-float ABI it is probably worth doing it
4258 properly and also passing function arguments in FP registers. */
4260 m68k_libcall_value (enum machine_mode mode
)
4267 return gen_rtx_REG (mode
, 16);
4272 return gen_rtx_REG (mode
, 0);
4276 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4278 enum machine_mode mode
;
4280 mode
= TYPE_MODE (valtype
);
4286 return gen_rtx_REG (mode
, 16);
4292 /* If the function returns a pointer, push that into %a0. */
4293 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4294 /* For compatibility with the large body of existing code which
4295 does not always properly declare external functions returning
4296 pointer types, the m68k/SVR4 convention is to copy the value
4297 returned for pointer functions from a0 to d0 in the function
4298 epilogue, so that callers that have neglected to properly
4299 declare the callee can still find the correct return value in
4301 return gen_rtx_PARALLEL
4304 gen_rtx_EXPR_LIST (VOIDmode
,
4305 gen_rtx_REG (mode
, A0_REG
),
4307 gen_rtx_EXPR_LIST (VOIDmode
,
4308 gen_rtx_REG (mode
, D0_REG
),
4310 else if (POINTER_TYPE_P (valtype
))
4311 return gen_rtx_REG (mode
, A0_REG
);
4313 return gen_rtx_REG (mode
, D0_REG
);