1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
57 function at any time during the compilation process. In the future
58 we should try and eliminate the USE if we can easily determine that
59 all PIC references were deleted from the current function. That would
60 save an address register */
65 if (flag_pic
&& current_function_uses_pic_offset_table
)
67 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
68 emit_insn_after (insn
, get_insns ());
74 /* This function generates the assembly code for function entry.
75 STREAM is a stdio stream to output the code to.
76 SIZE is an int: how many units of temporary storage to allocate.
77 Refer to the array `regs_ever_live' to determine which registers
78 to save; `regs_ever_live[I]' is nonzero if register number I
79 is ever used in the function. This function is responsible for
80 knowing which registers should not be saved even if used. */
83 /* Note that the order of the bit mask for fmovem is the opposite
84 of the order for movem! */
88 output_function_prologue (stream
, size
)
93 register int mask
= 0;
94 int num_saved_regs
= 0;
95 extern char call_used_regs
[];
96 int fsize
= (size
+ 3) & -4;
99 if (frame_pointer_needed
)
101 if (fsize
== 0 && TARGET_68040
)
103 /* on the 68040, pea + move is faster than link.w 0 */
105 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
106 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
107 reg_names
[FRAME_POINTER_REGNUM
]);
109 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
110 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
111 reg_names
[FRAME_POINTER_REGNUM
]);
114 else if (fsize
< 0x8000)
117 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
118 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
120 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
121 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
124 else if (TARGET_68020
)
127 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
128 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
130 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
131 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
136 /* Adding negative number is faster on the 68040. */
138 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
139 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
141 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
142 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
148 /* Adding negative number is faster on the 68040. */
149 if (fsize
+ 4 < 0x8000)
151 /* asm_fprintf() cannot handle %. */
153 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
155 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
160 /* asm_fprintf() cannot handle %. */
162 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
164 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
168 #ifdef SUPPORT_SUN_FPA
169 for (regno
= 24; regno
< 56; regno
++)
170 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
173 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
176 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
181 for (regno
= 16; regno
< 24; regno
++)
182 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
183 mask
|= 1 << (regno
- 16);
184 if ((mask
& 0xff) != 0)
187 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
189 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
193 for (regno
= 0; regno
< 16; regno
++)
194 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
196 mask
|= 1 << (15 - regno
);
199 if (frame_pointer_needed
)
201 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
206 fprintf (stream
, "\ttstl sp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
209 if (num_saved_regs
<= 2)
211 /* Store each separately in the same order moveml uses.
212 Using two movel instructions instead of a single moveml
213 is about 15% faster for the 68020 and 68030 at no expense
218 /* Undo the work from above. */
219 for (i
= 0; i
< 16; i
++)
223 "\t%Omove.l %s,-(%Rsp)\n",
225 "\tmovel %s,%Rsp@-\n",
232 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
234 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
237 if (flag_pic
&& current_function_uses_pic_offset_table
)
240 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
241 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
243 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
244 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
245 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
246 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
247 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
252 /* Return true if this function's epilogue can be output as RTL. */
259 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
262 /* Copied from output_function_epilogue (). We should probably create a
263 separate layout routine to perform the common work. */
265 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
266 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
272 /* This function generates the assembly code for function exit,
273 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
275 The function epilogue should not depend on the current stack pointer!
276 It should use the frame pointer only, if there is a frame pointer.
277 This is mandatory because of alloca; we also take advantage of it to
278 omit stack adjustments before returning. */
281 output_function_epilogue (stream
, size
)
286 register int mask
, fmask
;
288 int offset
, foffset
, fpoffset
;
289 extern char call_used_regs
[];
290 int fsize
= (size
+ 3) & -4;
292 rtx insn
= get_last_insn ();
293 int restore_from_sp
= 0;
295 /* If the last insn was a BARRIER, we don't have to write any code. */
296 if (GET_CODE (insn
) == NOTE
)
297 insn
= prev_nonnote_insn (insn
);
298 if (insn
&& GET_CODE (insn
) == BARRIER
)
300 /* Output just a no-op so that debuggers don't get confused
301 about which function the pc is in at this address. */
302 asm_fprintf (stream
, "\tnop\n");
306 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
307 if (profile_block_flag
== 2)
309 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
313 #ifdef FUNCTION_EXTRA_EPILOGUE
314 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
316 nregs
= 0; fmask
= 0; fpoffset
= 0;
317 #ifdef SUPPORT_SUN_FPA
318 for (regno
= 24 ; regno
< 56 ; regno
++)
319 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
321 fpoffset
= nregs
* 8;
324 for (regno
= 16; regno
< 24; regno
++)
325 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
328 fmask
|= 1 << (23 - regno
);
330 foffset
= fpoffset
+ nregs
* 12;
332 if (frame_pointer_needed
)
333 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
334 for (regno
= 0; regno
< 16; regno
++)
335 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
340 offset
= foffset
+ nregs
* 4;
341 restore_from_sp
= ! frame_pointer_needed
342 || (! current_function_calls_alloca
&& leaf_function_p ());
343 if (offset
+ fsize
>= 0x8000
345 && (mask
|| fmask
|| fpoffset
))
348 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
350 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
356 /* Restore each separately in the same order moveml does.
357 Using two movel instructions instead of a single moveml
358 is about 15% faster for the 68020 and 68030 at no expense
363 /* Undo the work from above. */
364 for (i
= 0; i
< 16; i
++)
370 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
372 reg_names
[FRAME_POINTER_REGNUM
],
375 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
376 reg_names
[FRAME_POINTER_REGNUM
],
377 offset
+ fsize
, reg_names
[i
]);
380 else if (restore_from_sp
)
383 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
386 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
393 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
395 reg_names
[FRAME_POINTER_REGNUM
],
398 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
399 reg_names
[FRAME_POINTER_REGNUM
],
400 offset
+ fsize
, reg_names
[i
]);
411 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
413 reg_names
[FRAME_POINTER_REGNUM
],
416 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
417 reg_names
[FRAME_POINTER_REGNUM
],
418 offset
+ fsize
, mask
);
421 else if (restore_from_sp
)
424 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
426 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
432 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
434 reg_names
[FRAME_POINTER_REGNUM
],
437 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
438 reg_names
[FRAME_POINTER_REGNUM
],
439 offset
+ fsize
, mask
);
448 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
450 reg_names
[FRAME_POINTER_REGNUM
],
453 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
454 reg_names
[FRAME_POINTER_REGNUM
],
455 foffset
+ fsize
, fmask
);
458 else if (restore_from_sp
)
461 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
463 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
469 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
471 reg_names
[FRAME_POINTER_REGNUM
],
474 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
475 reg_names
[FRAME_POINTER_REGNUM
],
476 foffset
+ fsize
, fmask
);
481 for (regno
= 55; regno
>= 24; regno
--)
482 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
487 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
489 reg_names
[FRAME_POINTER_REGNUM
],
492 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
493 reg_names
[FRAME_POINTER_REGNUM
],
494 fpoffset
+ fsize
, reg_names
[regno
]);
497 else if (restore_from_sp
)
500 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
503 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
510 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
512 reg_names
[FRAME_POINTER_REGNUM
],
515 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
516 reg_names
[FRAME_POINTER_REGNUM
],
517 fpoffset
+ fsize
, reg_names
[regno
]);
522 if (frame_pointer_needed
)
523 fprintf (stream
, "\tunlk %s\n",
524 reg_names
[FRAME_POINTER_REGNUM
]);
527 if (fsize
+ 4 < 0x8000)
529 /* asm_fprintf() cannot handle %. */
531 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
533 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
538 /* asm_fprintf() cannot handle %. */
540 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
542 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
546 if (current_function_pops_args
)
547 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
549 fprintf (stream
, "\trts\n");
552 /* Similar to general_operand, but exclude stack_pointer_rtx. */
555 not_sp_operand (op
, mode
)
557 enum machine_mode mode
;
559 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
562 /* Return TRUE if X is a valid comparison operator for the dbcc
565 Note it rejects floating point comparison operators.
566 (In the future we could use Fdbcc).
568 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
571 valid_dbcc_comparison_p (x
, mode
)
573 enum machine_mode mode
;
575 switch (GET_CODE (x
))
577 case EQ
: case NE
: case GTU
: case LTU
:
581 /* Reject some when CC_NO_OVERFLOW is set. This may be over
583 case GT
: case LT
: case GE
: case LE
:
584 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
590 /* Return non-zero if flags are currently in the 68881 flag register. */
594 /* We could add support for these in the future */
595 return cc_status
.flags
& CC_IN_68881
;
598 /* Output a dbCC; jCC sequence. Note we do not handle the
599 floating point version of this sequence (Fdbcc). We also
600 do not handle alternative conditions when CC_NO_OVERFLOW is
601 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
602 kick those out before we get here. */
604 output_dbcc_and_branch (operands
)
607 switch (GET_CODE (operands
[3]))
611 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
613 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
619 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
621 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
627 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
629 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
635 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
637 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
643 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
645 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
651 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
653 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
659 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
661 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
667 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
669 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
675 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
677 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
683 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
685 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
693 /* If the decrement is to be done in SImode, then we have
694 to compensate for the fact that dbcc decrements in HImode. */
695 switch (GET_MODE (operands
[0]))
699 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
701 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
714 output_scc_di(op
, operand1
, operand2
, dest
)
721 enum rtx_code op_code
= GET_CODE (op
);
723 /* The m68k cmp.l instruction requires operand1 to be a reg as used
724 below. Swap the operands and change the op if these requirements
725 are not fulfilled. */
726 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
732 op_code
= swap_condition (op_code
);
734 loperands
[0] = operand1
;
735 if (GET_CODE (operand1
) == REG
)
736 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
738 loperands
[1] = adj_offsettable_operand (operand1
, 4);
739 if (operand2
!= const0_rtx
)
741 loperands
[2] = operand2
;
742 if (GET_CODE (operand2
) == REG
)
743 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
745 loperands
[3] = adj_offsettable_operand (operand2
, 4);
747 loperands
[4] = gen_label_rtx();
748 if (operand2
!= const0_rtx
)
751 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
753 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
757 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
759 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
764 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
766 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
773 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
774 CODE_LABEL_NUMBER (loperands
[4]));
775 output_asm_insn ("seq %5", loperands
);
779 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
780 CODE_LABEL_NUMBER (loperands
[4]));
781 output_asm_insn ("sne %5", loperands
);
785 loperands
[6] = gen_label_rtx();
787 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
789 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
791 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
792 CODE_LABEL_NUMBER (loperands
[4]));
793 output_asm_insn ("sgt %5", loperands
);
794 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
795 CODE_LABEL_NUMBER (loperands
[6]));
799 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
800 CODE_LABEL_NUMBER (loperands
[4]));
801 output_asm_insn ("shi %5", loperands
);
805 loperands
[6] = gen_label_rtx();
807 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
809 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
811 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
812 CODE_LABEL_NUMBER (loperands
[4]));
813 output_asm_insn ("slt %5", loperands
);
814 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
815 CODE_LABEL_NUMBER (loperands
[6]));
819 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
820 CODE_LABEL_NUMBER (loperands
[4]));
821 output_asm_insn ("scs %5", loperands
);
825 loperands
[6] = gen_label_rtx();
827 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
829 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
831 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
832 CODE_LABEL_NUMBER (loperands
[4]));
833 output_asm_insn ("sge %5", loperands
);
834 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
835 CODE_LABEL_NUMBER (loperands
[6]));
839 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
840 CODE_LABEL_NUMBER (loperands
[4]));
841 output_asm_insn ("scc %5", loperands
);
845 loperands
[6] = gen_label_rtx();
847 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
849 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
851 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
852 CODE_LABEL_NUMBER (loperands
[4]));
853 output_asm_insn ("sle %5", loperands
);
854 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
855 CODE_LABEL_NUMBER (loperands
[6]));
859 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
860 CODE_LABEL_NUMBER (loperands
[4]));
861 output_asm_insn ("sls %5", loperands
);
871 output_btst (operands
, countop
, dataop
, insn
, signpos
)
877 operands
[0] = countop
;
878 operands
[1] = dataop
;
880 if (GET_CODE (countop
) == CONST_INT
)
882 register int count
= INTVAL (countop
);
883 /* If COUNT is bigger than size of storage unit in use,
884 advance to the containing unit of same size. */
887 int offset
= (count
& ~signpos
) / 8;
888 count
= count
& signpos
;
889 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
891 if (count
== signpos
)
892 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
894 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
896 /* These three statements used to use next_insns_test_no...
897 but it appears that this should do the same job. */
899 && next_insn_tests_no_inequality (insn
))
902 && next_insn_tests_no_inequality (insn
))
905 && next_insn_tests_no_inequality (insn
))
908 cc_status
.flags
= CC_NOT_NEGATIVE
;
913 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
914 reference and a constant. */
917 symbolic_operand (op
, mode
)
919 enum machine_mode mode
;
921 switch (GET_CODE (op
))
929 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
930 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
931 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
933 #if 0 /* Deleted, with corresponding change in m68k.h,
934 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
936 return GET_MODE (op
) == mode
;
944 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
947 extend_operator(x
, mode
)
949 enum machine_mode mode
;
951 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
964 /* Legitimize PIC addresses. If the address is already
965 position-independent, we return ORIG. Newly generated
966 position-independent addresses go to REG. If we need more
967 than one register, we lose.
969 An address is legitimized by making an indirect reference
970 through the Global Offset Table with the name of the symbol
973 The assembler and linker are responsible for placing the
974 address of the symbol in the GOT. The function prologue
975 is responsible for initializing a5 to the starting address
978 The assembler is also responsible for translating a symbol name
979 into a constant displacement from the start of the GOT.
981 A quick example may make things a little clearer:
983 When not generating PIC code to store the value 12345 into _foo
984 we would generate the following code:
988 When generating PIC two transformations are made. First, the compiler
989 loads the address of foo into a register. So the first transformation makes:
994 The code in movsi will intercept the lea instruction and call this
995 routine which will transform the instructions into:
997 movel a5@(_foo:w), a0
1001 That (in a nutshell) is how *all* symbol and label references are
1005 legitimize_pic_address (orig
, mode
, reg
)
1007 enum machine_mode mode
;
1011 /* First handle a simple SYMBOL_REF or LABEL_REF */
1012 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1017 pic_ref
= gen_rtx (MEM
, Pmode
,
1018 gen_rtx (PLUS
, Pmode
,
1019 pic_offset_table_rtx
, orig
));
1020 current_function_uses_pic_offset_table
= 1;
1021 RTX_UNCHANGING_P (pic_ref
) = 1;
1022 emit_move_insn (reg
, pic_ref
);
1025 else if (GET_CODE (orig
) == CONST
)
1029 /* Make sure this is CONST has not already been legitimized */
1030 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1031 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1037 /* legitimize both operands of the PLUS */
1038 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1040 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1041 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1042 base
== reg
? 0 : reg
);
1046 if (GET_CODE (orig
) == CONST_INT
)
1047 return plus_constant_for_output (base
, INTVAL (orig
));
1048 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1049 /* Likewise, should we set special REG_NOTEs here? */
1055 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1057 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1060 const_method (constant
)
1066 i
= INTVAL (constant
);
1069 /* if -256 < N < 256 but N is not in range for a moveq
1070 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1071 if (USE_MOVQ (i
^ 0xff))
1073 /* Likewise, try with not.w */
1074 if (USE_MOVQ (i
^ 0xffff))
1076 /* This is the only value where neg.w is useful */
1079 /* Try also with swap */
1081 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1083 /* Otherwise, use move.l */
1087 const_int_cost (constant
)
1090 switch (const_method (constant
))
1093 /* Constants between -128 and 127 are cheap due to moveq */
1099 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1109 output_move_const_into_data_reg (operands
)
1114 i
= INTVAL (operands
[1]);
1115 switch (const_method (operands
[1]))
1118 #if defined (MOTOROLA) && !defined (CRDS)
1119 return "moveq%.l %1,%0";
1121 return "moveq %1,%0";
1124 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1125 #if defined (MOTOROLA) && !defined (CRDS)
1126 return "moveq%.l %1,%0\n\tnot%.b %0";
1128 return "moveq %1,%0\n\tnot%.b %0";
1131 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1132 #if defined (MOTOROLA) && !defined (CRDS)
1133 return "moveq%.l %1,%0\n\tnot%.w %0";
1135 return "moveq %1,%0\n\tnot%.w %0";
1138 #if defined (MOTOROLA) && !defined (CRDS)
1139 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1141 return "moveq %#-128,%0\n\tneg%.w %0";
1147 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1148 #if defined (MOTOROLA) && !defined (CRDS)
1149 return "moveq%.l %1,%0\n\tswap %0";
1151 return "moveq %1,%0\n\tswap %0";
1155 return "move%.l %1,%0";
1161 /* Return the best assembler insn template
1162 for moving operands[1] into operands[0] as a fullword. */
1165 singlemove_string (operands
)
1168 #ifdef SUPPORT_SUN_FPA
1169 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1170 return "fpmoves %1,%0";
1172 if (DATA_REG_P (operands
[0])
1173 && GET_CODE (operands
[1]) == CONST_INT
)
1174 return output_move_const_into_data_reg (operands
);
1175 if (operands
[1] != const0_rtx
)
1176 return "move%.l %1,%0";
1177 if (! ADDRESS_REG_P (operands
[0]))
1179 return "sub%.l %0,%0";
1183 /* Output assembler code to perform a doubleword move insn
1184 with operands OPERANDS. */
1187 output_move_double (operands
)
1192 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1197 rtx addreg0
= 0, addreg1
= 0;
1198 int dest_overlapped_low
= 0;
1199 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1204 /* First classify both operands. */
1206 if (REG_P (operands
[0]))
1208 else if (offsettable_memref_p (operands
[0]))
1210 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1212 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1214 else if (GET_CODE (operands
[0]) == MEM
)
1219 if (REG_P (operands
[1]))
1221 else if (CONSTANT_P (operands
[1]))
1223 else if (offsettable_memref_p (operands
[1]))
1225 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1227 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1229 else if (GET_CODE (operands
[1]) == MEM
)
1234 /* Check for the cases that the operand constraints are not
1235 supposed to allow to happen. Abort if we get one,
1236 because generating code for these cases is painful. */
1238 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1241 /* If one operand is decrementing and one is incrementing
1242 decrement the former register explicitly
1243 and change that operand into ordinary indexing. */
1245 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1247 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1249 output_asm_insn ("sub%.l %#12,%0", operands
);
1251 output_asm_insn ("subq%.l %#8,%0", operands
);
1252 if (GET_MODE (operands
[1]) == XFmode
)
1253 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1254 else if (GET_MODE (operands
[0]) == DFmode
)
1255 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1257 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1260 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1262 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1264 output_asm_insn ("sub%.l %#12,%1", operands
);
1266 output_asm_insn ("subq%.l %#8,%1", operands
);
1267 if (GET_MODE (operands
[1]) == XFmode
)
1268 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1269 else if (GET_MODE (operands
[1]) == DFmode
)
1270 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1272 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1276 /* If an operand is an unoffsettable memory ref, find a register
1277 we can increment temporarily to make it refer to the second word. */
1279 if (optype0
== MEMOP
)
1280 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1282 if (optype1
== MEMOP
)
1283 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1285 /* Ok, we can do one word at a time.
1286 Normally we do the low-numbered word first,
1287 but if either operand is autodecrementing then we
1288 do the high-numbered word first.
1290 In either case, set up in LATEHALF the operands to use
1291 for the high-numbered word and in some cases alter the
1292 operands in OPERANDS to be suitable for the low-numbered word. */
1296 if (optype0
== REGOP
)
1298 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1299 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1301 else if (optype0
== OFFSOP
)
1303 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1304 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1308 middlehalf
[0] = operands
[0];
1309 latehalf
[0] = operands
[0];
1312 if (optype1
== REGOP
)
1314 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1315 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1317 else if (optype1
== OFFSOP
)
1319 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1320 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1322 else if (optype1
== CNSTOP
)
1324 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1329 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1330 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1331 operands
[1] = GEN_INT (l
[0]);
1332 middlehalf
[1] = GEN_INT (l
[1]);
1333 latehalf
[1] = GEN_INT (l
[2]);
1335 else if (CONSTANT_P (operands
[1]))
1337 /* actually, no non-CONST_DOUBLE constant should ever
1340 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1341 latehalf
[1] = constm1_rtx
;
1343 latehalf
[1] = const0_rtx
;
1348 middlehalf
[1] = operands
[1];
1349 latehalf
[1] = operands
[1];
1353 /* size is not 12: */
1355 if (optype0
== REGOP
)
1356 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1357 else if (optype0
== OFFSOP
)
1358 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1360 latehalf
[0] = operands
[0];
1362 if (optype1
== REGOP
)
1363 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1364 else if (optype1
== OFFSOP
)
1365 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1366 else if (optype1
== CNSTOP
)
1367 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1369 latehalf
[1] = operands
[1];
1372 /* If insn is effectively movd N(sp),-(sp) then we will do the
1373 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1374 for the low word as well, to compensate for the first decrement of sp. */
1375 if (optype0
== PUSHOP
1376 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1377 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1378 operands
[1] = middlehalf
[1] = latehalf
[1];
1380 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1381 if the upper part of reg N does not appear in the MEM, arrange to
1382 emit the move late-half first. Otherwise, compute the MEM address
1383 into the upper part of N and use that as a pointer to the memory
1385 if (optype0
== REGOP
1386 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1388 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1390 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1391 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1393 /* If both halves of dest are used in the src memory address,
1394 compute the address into latehalf of dest.
1395 Note that this can't happen if the dest is two data regs. */
1397 xops
[0] = latehalf
[0];
1398 xops
[1] = XEXP (operands
[1], 0);
1399 output_asm_insn ("lea %a1,%0", xops
);
1400 if( GET_MODE (operands
[1]) == XFmode
)
1402 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1403 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1404 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1408 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1409 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1413 && reg_overlap_mentioned_p (middlehalf
[0],
1414 XEXP (operands
[1], 0)))
1416 /* Check for two regs used by both source and dest.
1417 Note that this can't happen if the dest is all data regs.
1418 It can happen if the dest is d6, d7, a0.
1419 But in that case, latehalf is an addr reg, so
1420 the code at compadr does ok. */
1422 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1423 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1426 /* JRV says this can't happen: */
1427 if (addreg0
|| addreg1
)
1430 /* Only the middle reg conflicts; simply put it last. */
1431 output_asm_insn (singlemove_string (operands
), operands
);
1432 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1433 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1436 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1437 /* If the low half of dest is mentioned in the source memory
1438 address, the arrange to emit the move late half first. */
1439 dest_overlapped_low
= 1;
1442 /* If one or both operands autodecrementing,
1443 do the two words, high-numbered first. */
1445 /* Likewise, the first move would clobber the source of the second one,
1446 do them in the other order. This happens only for registers;
1447 such overlap can't happen in memory unless the user explicitly
1448 sets it up, and that is an undefined circumstance. */
1450 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1451 || (optype0
== REGOP
&& optype1
== REGOP
1452 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1453 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1454 || dest_overlapped_low
)
1456 /* Make any unoffsettable addresses point at high-numbered word. */
1460 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1462 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1467 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1469 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1473 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1475 /* Undo the adds we just did. */
1477 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1479 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1483 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1485 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1487 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1490 /* Do low-numbered word. */
1491 return singlemove_string (operands
);
1494 /* Normal case: do the two words, low-numbered first. */
1496 output_asm_insn (singlemove_string (operands
), operands
);
1498 /* Do the middle one of the three words for long double */
1502 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1504 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1506 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1509 /* Make any unoffsettable addresses point at high-numbered word. */
1511 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1513 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1516 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1518 /* Undo the adds we just did. */
1522 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1524 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1529 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1531 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1537 /* Return a REG that occurs in ADDR with coefficient 1.
1538 ADDR can be effectively incremented by incrementing REG. */
1541 find_addr_reg (addr
)
1544 while (GET_CODE (addr
) == PLUS
)
1546 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1547 addr
= XEXP (addr
, 0);
1548 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1549 addr
= XEXP (addr
, 1);
1550 else if (CONSTANT_P (XEXP (addr
, 0)))
1551 addr
= XEXP (addr
, 1);
1552 else if (CONSTANT_P (XEXP (addr
, 1)))
1553 addr
= XEXP (addr
, 0);
1557 if (GET_CODE (addr
) == REG
)
1562 /* Store in cc_status the expressions that the condition codes will
1563 describe after execution of an instruction whose pattern is EXP.
1564 Do not alter them if the instruction would not alter the cc's. */
1566 /* On the 68000, all the insns to store in an address register fail to
1567 set the cc's. However, in some cases these instructions can make it
1568 possibly invalid to use the saved cc's. In those cases we clear out
1569 some or all of the saved cc's so they won't be used. */
1571 notice_update_cc (exp
, insn
)
1575 /* If the cc is being set from the fpa and the expression is not an
1576 explicit floating point test instruction (which has code to deal with
1577 this), reinit the CC. */
1578 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1579 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1580 && !(GET_CODE (exp
) == PARALLEL
1581 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1582 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1586 else if (GET_CODE (exp
) == SET
)
1588 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1592 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1594 if (cc_status
.value1
1595 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1596 cc_status
.value1
= 0;
1597 if (cc_status
.value2
1598 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1599 cc_status
.value2
= 0;
1601 else if (!FP_REG_P (SET_DEST (exp
))
1602 && SET_DEST (exp
) != cc0_rtx
1603 && (FP_REG_P (SET_SRC (exp
))
1604 || GET_CODE (SET_SRC (exp
)) == FIX
1605 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1606 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1610 /* A pair of move insns doesn't produce a useful overall cc. */
1611 else if (!FP_REG_P (SET_DEST (exp
))
1612 && !FP_REG_P (SET_SRC (exp
))
1613 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1614 && (GET_CODE (SET_SRC (exp
)) == REG
1615 || GET_CODE (SET_SRC (exp
)) == MEM
1616 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1620 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1624 else if (XEXP (exp
, 0) != pc_rtx
)
1626 cc_status
.flags
= 0;
1627 cc_status
.value1
= XEXP (exp
, 0);
1628 cc_status
.value2
= XEXP (exp
, 1);
1631 else if (GET_CODE (exp
) == PARALLEL
1632 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1634 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1636 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1638 cc_status
.flags
= 0;
1639 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1640 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1645 if (cc_status
.value2
!= 0
1646 && ADDRESS_REG_P (cc_status
.value2
)
1647 && GET_MODE (cc_status
.value2
) == QImode
)
1649 if (cc_status
.value2
!= 0
1650 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1651 switch (GET_CODE (cc_status
.value2
))
1653 case PLUS
: case MINUS
: case MULT
:
1654 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1655 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1656 case ROTATE
: case ROTATERT
:
1657 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1658 cc_status
.flags
|= CC_NO_OVERFLOW
;
1661 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1662 ends with a move insn moving r2 in r2's mode.
1663 Thus, the cc's are set for r2.
1664 This can set N bit spuriously. */
1665 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1667 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1669 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1670 cc_status
.value2
= 0;
1671 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1672 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1673 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1674 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1675 cc_status
.flags
= CC_IN_68881
;
1679 output_move_const_double (operands
)
1682 #ifdef SUPPORT_SUN_FPA
1683 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1685 int code
= standard_sun_fpa_constant_p (operands
[1]);
1689 static char buf
[40];
1691 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1694 return "fpmove%.d %1,%0";
1699 int code
= standard_68881_constant_p (operands
[1]);
1703 static char buf
[40];
1705 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1708 return "fmove%.d %1,%0";
1713 output_move_const_single (operands
)
1716 #ifdef SUPPORT_SUN_FPA
1719 int code
= standard_sun_fpa_constant_p (operands
[1]);
1723 static char buf
[40];
1725 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1728 return "fpmove%.s %1,%0";
1731 #endif /* defined SUPPORT_SUN_FPA */
1733 int code
= standard_68881_constant_p (operands
[1]);
1737 static char buf
[40];
1739 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1742 return "fmove%.s %f1,%0";
1746 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1747 from the "fmovecr" instruction.
1748 The value, anded with 0xff, gives the code to use in fmovecr
1749 to get the desired constant. */
1751 /* This code has been fixed for cross-compilation. */
1753 static int inited_68881_table
= 0;
1755 char *strings_68881
[7] = {
1765 int codes_68881
[7] = {
1775 REAL_VALUE_TYPE values_68881
[7];
1777 /* Set up values_68881 array by converting the decimal values
1778 strings_68881 to binary. */
1785 enum machine_mode mode
;
1788 for (i
= 0; i
< 7; i
++)
1792 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
1793 values_68881
[i
] = r
;
1795 inited_68881_table
= 1;
1799 standard_68881_constant_p (x
)
1804 enum machine_mode mode
;
1806 #ifdef NO_ASM_FMOVECR
1810 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
1814 #ifndef REAL_ARITHMETIC
1815 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1816 if (! flag_pretend_float
)
1821 if (! inited_68881_table
)
1822 init_68881_table ();
1824 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1826 for (i
= 0; i
< 6; i
++)
1828 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
1829 return (codes_68881
[i
]);
1832 if (GET_MODE (x
) == SFmode
)
1835 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
1836 return (codes_68881
[6]);
1838 /* larger powers of ten in the constants ram are not used
1839 because they are not equal to a `double' C constant. */
1843 /* If X is a floating-point constant, return the logarithm of X base 2,
1844 or 0 if X is not a power of 2. */
1847 floating_exact_log2 (x
)
1850 REAL_VALUE_TYPE r
, r1
;
1853 #ifndef REAL_ARITHMETIC
1854 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1855 if (! flag_pretend_float
)
1860 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1862 if (REAL_VALUES_LESS (r
, dconst0
))
1867 while (REAL_VALUES_LESS (r1
, r
))
1869 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
1870 if (REAL_VALUES_EQUAL (r1
, r
))
1877 #ifdef SUPPORT_SUN_FPA
1878 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1879 from the Sun FPA's constant RAM.
1880 The value returned, anded with 0x1ff, gives the code to use in fpmove
1881 to get the desired constant. */
1883 static int inited_FPA_table
= 0;
1885 char *strings_FPA
[38] = {
1886 /* small rationals */
1899 /* Decimal equivalents of double precision values */
1900 "2.718281828459045091", /* D_E */
1901 "6.283185307179586477", /* 2 pi */
1902 "3.141592653589793116", /* D_PI */
1903 "1.570796326794896619", /* pi/2 */
1904 "1.414213562373095145", /* D_SQRT2 */
1905 "0.7071067811865475244", /* 1/sqrt(2) */
1906 "-1.570796326794896619", /* -pi/2 */
1907 "1.442695040888963387", /* D_LOG2ofE */
1908 "3.321928024887362182", /* D_LOG2of10 */
1909 "0.6931471805599452862", /* D_LOGEof2 */
1910 "2.302585092994045901", /* D_LOGEof10 */
1911 "0.3010299956639811980", /* D_LOG10of2 */
1912 "0.4342944819032518167", /* D_LOG10ofE */
1913 /* Decimal equivalents of single precision values */
1914 "2.718281745910644531", /* S_E */
1915 "6.283185307179586477", /* 2 pi */
1916 "3.141592741012573242", /* S_PI */
1917 "1.570796326794896619", /* pi/2 */
1918 "1.414213538169860840", /* S_SQRT2 */
1919 "0.7071067811865475244", /* 1/sqrt(2) */
1920 "-1.570796326794896619", /* -pi/2 */
1921 "1.442695021629333496", /* S_LOG2ofE */
1922 "3.321928024291992188", /* S_LOG2of10 */
1923 "0.6931471824645996094", /* S_LOGEof2 */
1924 "2.302585124969482442", /* S_LOGEof10 */
1925 "0.3010300099849700928", /* S_LOG10of2 */
1926 "0.4342944920063018799", /* S_LOG10ofE */
1930 int codes_FPA
[38] = {
1931 /* small rationals */
1944 /* double precision */
1958 /* single precision */
1974 REAL_VALUE_TYPE values_FPA
[38];
1976 /* This code has been fixed for cross-compilation. */
1981 enum machine_mode mode
;
1986 for (i
= 0; i
< 38; i
++)
1990 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
1993 inited_FPA_table
= 1;
1998 standard_sun_fpa_constant_p (x
)
2004 #ifndef REAL_ARITHMETIC
2005 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2006 if (! flag_pretend_float
)
2011 if (! inited_FPA_table
)
2014 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2016 for (i
=0; i
<12; i
++)
2018 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2019 return (codes_FPA
[i
]);
2022 if (GET_MODE (x
) == SFmode
)
2024 for (i
=25; i
<38; i
++)
2026 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2027 return (codes_FPA
[i
]);
2032 for (i
=12; i
<25; i
++)
2034 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2035 return (codes_FPA
[i
]);
2040 #endif /* define SUPPORT_SUN_FPA */
2042 /* A C compound statement to output to stdio stream STREAM the
2043 assembler syntax for an instruction operand X. X is an RTL
2046 CODE is a value that can be used to specify one of several ways
2047 of printing the operand. It is used when identical operands
2048 must be printed differently depending on the context. CODE
2049 comes from the `%' specification that was used to request
2050 printing of the operand. If the specification was just `%DIGIT'
2051 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2052 is the ASCII code for LTR.
2054 If X is a register, this macro should print the register's name.
2055 The names can be found in an array `reg_names' whose type is
2056 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2058 When the machine description has a specification `%PUNCT' (a `%'
2059 followed by a punctuation character), this macro is called with
2060 a null pointer for X and the punctuation character for CODE.
2062 The m68k specific codes are:
2064 '.' for dot needed in Motorola-style opcode names.
2065 '-' for an operand pushing on the stack:
2066 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2067 '+' for an operand pushing on the stack:
2068 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2069 '@' for a reference to the top word on the stack:
2070 sp@, (sp) or (%sp) depending on the style of syntax.
2071 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2072 but & in SGS syntax).
2073 '!' for the cc register (used in an `and to cc' insn).
2074 '$' for the letter `s' in an op code, but only on the 68040.
2075 '&' for the letter `d' in an op code, but only on the 68040.
2076 '/' for register prefix needed by longlong.h.
2078 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2079 'd' to force memory addressing to be absolute, not relative.
2080 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2081 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2082 than directly). Second part of 'y' below.
2083 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2084 or print pair of registers as rx:ry.
2085 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2086 CONST_DOUBLE's as SunFPA constant RAM registers if
2087 possible, so it should not be used except for the SunFPA.
2092 print_operand (file
, op
, letter
)
2093 FILE *file
; /* file to write to */
2094 rtx op
; /* operand to print */
2095 int letter
; /* %<letter> or 0 */
2102 asm_fprintf (file
, ".");
2105 else if (letter
== '#')
2107 asm_fprintf (file
, "%0I");
2109 else if (letter
== '-')
2112 asm_fprintf (file
, "-(%Rsp)");
2114 asm_fprintf (file
, "%Rsp@-");
2117 else if (letter
== '+')
2120 asm_fprintf (file
, "(%Rsp)+");
2122 asm_fprintf (file
, "%Rsp@+");
2125 else if (letter
== '@')
2128 asm_fprintf (file
, "(%Rsp)");
2130 asm_fprintf (file
, "%Rsp@");
2133 else if (letter
== '!')
2135 asm_fprintf (file
, "%Rfpcr");
2137 else if (letter
== '$')
2139 if (TARGET_68040_ONLY
)
2141 fprintf (file
, "s");
2144 else if (letter
== '&')
2146 if (TARGET_68040_ONLY
)
2148 fprintf (file
, "d");
2151 else if (letter
== '/')
2153 asm_fprintf (file
, "%R");
2155 else if (GET_CODE (op
) == REG
)
2157 #ifdef SUPPORT_SUN_FPA
2159 && (letter
== 'y' || letter
== 'x')
2160 && GET_MODE (op
) == DFmode
)
2162 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2163 reg_names
[REGNO (op
)+1]);
2169 /* Print out the second register name of a register pair.
2170 I.e., R (6) => 7. */
2171 fputs (reg_names
[REGNO (op
) + 1], file
);
2173 fputs (reg_names
[REGNO (op
)], file
);
2176 else if (GET_CODE (op
) == MEM
)
2178 output_address (XEXP (op
, 0));
2179 if (letter
== 'd' && ! TARGET_68020
2180 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2181 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2182 && INTVAL (XEXP (op
, 0)) < 0x8000
2183 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2186 fprintf (file
, ".l");
2188 fprintf (file
, ":l");
2192 #ifdef SUPPORT_SUN_FPA
2193 else if ((letter
== 'y' || letter
== 'w')
2194 && GET_CODE (op
) == CONST_DOUBLE
2195 && (i
= standard_sun_fpa_constant_p (op
)))
2197 fprintf (file
, "%%%d", i
& 0x1ff);
2200 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2203 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2204 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2206 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2209 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2210 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2212 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2215 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2216 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2220 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2225 /* A C compound statement to output to stdio stream STREAM the
2226 assembler syntax for an instruction operand that is a memory
2227 reference whose address is ADDR. ADDR is an RTL expression.
2229 Note that this contains a kludge that knows that the only reason
2230 we have an address (plus (label_ref...) (reg...)) when not generating
2231 PIC code is in the insn before a tablejump, and we know that m68k.md
2232 generates a label LInnn: on such an insn.
2234 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2235 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2237 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2238 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2239 we want. This difference can be accommodated by using an assembler
2240 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2241 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2242 macro. See m68k/sgs.h for an example; for versions without the bug.
2243 Some assemblers refuse all the above solutions. The workaround is to
2244 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2247 They also do not like things like "pea 1.w", so we simple leave off
2248 the .w on small constants.
2250 This routine is responsible for distinguishing between -fpic and -fPIC
2251 style relocations in an address. When generating -fpic code the
2252 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2253 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2255 #ifndef ASM_OUTPUT_CASE_FETCH
2258 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2259 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2261 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2262 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2265 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2266 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2268 #endif /* ASM_OUTPUT_CASE_FETCH */
2271 print_operand_address (file
, addr
)
2275 register rtx reg1
, reg2
, breg
, ireg
;
2278 switch (GET_CODE (addr
))
2282 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2284 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2289 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2291 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2296 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2298 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2302 reg1
= reg2
= ireg
= breg
= offset
= 0;
2303 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2305 offset
= XEXP (addr
, 0);
2306 addr
= XEXP (addr
, 1);
2308 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2310 offset
= XEXP (addr
, 1);
2311 addr
= XEXP (addr
, 0);
2313 if (GET_CODE (addr
) != PLUS
)
2317 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2319 reg1
= XEXP (addr
, 0);
2320 addr
= XEXP (addr
, 1);
2322 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2324 reg1
= XEXP (addr
, 1);
2325 addr
= XEXP (addr
, 0);
2327 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2329 reg1
= XEXP (addr
, 0);
2330 addr
= XEXP (addr
, 1);
2332 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2334 reg1
= XEXP (addr
, 1);
2335 addr
= XEXP (addr
, 0);
2337 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2339 reg1
= XEXP (addr
, 0);
2340 addr
= XEXP (addr
, 1);
2342 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2344 reg1
= XEXP (addr
, 1);
2345 addr
= XEXP (addr
, 0);
2347 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2348 || GET_CODE (addr
) == SIGN_EXTEND
)
2360 #if 0 /* for OLD_INDEXING */
2361 else if (GET_CODE (addr
) == PLUS
)
2363 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2365 reg2
= XEXP (addr
, 0);
2366 addr
= XEXP (addr
, 1);
2368 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2370 reg2
= XEXP (addr
, 1);
2371 addr
= XEXP (addr
, 0);
2383 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2384 || GET_CODE (reg1
) == MULT
))
2385 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2390 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2395 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2396 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2399 if (GET_CODE (ireg
) == MULT
)
2401 scale
= INTVAL (XEXP (ireg
, 1));
2402 ireg
= XEXP (ireg
, 0);
2404 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2406 ASM_OUTPUT_CASE_FETCH (file
,
2407 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2408 reg_names
[REGNO (XEXP (ireg
, 0))]);
2409 fprintf (file
, "w");
2413 ASM_OUTPUT_CASE_FETCH (file
,
2414 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2415 reg_names
[REGNO (ireg
)]);
2416 fprintf (file
, "l");
2421 fprintf (file
, "*%d", scale
);
2423 fprintf (file
, ":%d", scale
);
2429 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2430 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2432 ASM_OUTPUT_CASE_FETCH (file
,
2433 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2434 reg_names
[REGNO (breg
)]);
2435 fprintf (file
, "l)");
2438 if (ireg
!= 0 || breg
!= 0)
2445 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2452 output_addr_const (file
, addr
);
2453 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2454 fprintf (file
, "@GOT");
2456 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2462 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2465 output_addr_const (file
, addr
);
2466 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2467 fprintf (file
, ":w");
2468 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2469 fprintf (file
, ":l");
2471 if (addr
!= 0 && ireg
!= 0)
2476 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2478 scale
= INTVAL (XEXP (ireg
, 1));
2479 ireg
= XEXP (ireg
, 0);
2481 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2484 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2486 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2492 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2494 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2500 fprintf (file
, "*%d", scale
);
2502 fprintf (file
, ":%d", scale
);
2508 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2509 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2511 ASM_OUTPUT_CASE_FETCH (file
,
2512 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2513 reg_names
[REGNO (reg1
)]);
2514 fprintf (file
, "l)");
2517 /* FALL-THROUGH (is this really what we want? */
2519 if (GET_CODE (addr
) == CONST_INT
2520 && INTVAL (addr
) < 0x8000
2521 && INTVAL (addr
) >= -0x8000)
2525 /* Many SGS assemblers croak on size specifiers for constants. */
2526 fprintf (file
, "%d", INTVAL (addr
));
2528 fprintf (file
, "%d.w", INTVAL (addr
));
2531 fprintf (file
, "%d:w", INTVAL (addr
));
2536 output_addr_const (file
, addr
);
2542 /* Check for cases where a clr insns can be omitted from code using
2543 strict_low_part sets. For example, the second clrl here is not needed:
2544 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2546 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2547 insn we are checking for redundancy. TARGET is the register set by the
2551 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2552 enum machine_mode mode
;
2558 p
= prev_nonnote_insn (first_insn
);
2562 /* If it isn't an insn, then give up. */
2563 if (GET_CODE (p
) != INSN
)
2566 if (reg_set_p (target
, p
))
2568 rtx set
= single_set (p
);
2571 /* If it isn't an easy to recognize insn, then give up. */
2575 dest
= SET_DEST (set
);
2577 /* If this sets the entire target register to zero, then our
2578 first_insn is redundant. */
2579 if (rtx_equal_p (dest
, target
)
2580 && SET_SRC (set
) == const0_rtx
)
2582 else if (GET_CODE (dest
) == STRICT_LOW_PART
2583 && GET_CODE (XEXP (dest
, 0)) == REG
2584 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2585 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2586 <= GET_MODE_SIZE (mode
)))
2587 /* This is a strict low part set which modifies less than
2588 we are using, so it is safe. */
2594 p
= prev_nonnote_insn (p
);
2601 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2602 range carefully since this predicate is used in DImode contexts. Also, we
2603 need some extra crud to make it work when hosted on 64-bit machines. */
2606 const_uint32_operand (op
, mode
)
2608 enum machine_mode mode
;
2610 #if HOST_BITS_PER_WIDE_INT > 32
2611 /* All allowed constants will fit a CONST_INT. */
2612 return (GET_CODE (op
) == CONST_INT
2613 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
2615 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
2616 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
2620 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2621 to check the range carefully since this predicate is used in DImode
2625 const_sint32_operand (op
, mode
)
2627 enum machine_mode mode
;
2629 /* All allowed constants will fit a CONST_INT. */
2630 return (GET_CODE (op
) == CONST_INT
2631 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));