1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Specify the identification number of the library being built */
127 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
129 /* Nonzero if the last compare/test insn had FP operands. The
130 sCC expanders peek at this to determine what to do for the
131 68060, which has no fsCC instructions. */
132 int m68k_last_compare_had_fp_operands
;
134 /* Initialize the GCC target structure. */
136 #if INT_OP_GROUP == INT_OP_DOT_WORD
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
141 #if INT_OP_GROUP == INT_OP_NO_DOT
142 #undef TARGET_ASM_BYTE_OP
143 #define TARGET_ASM_BYTE_OP "\tbyte\t"
144 #undef TARGET_ASM_ALIGNED_HI_OP
145 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
146 #undef TARGET_ASM_ALIGNED_SI_OP
147 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
150 #if INT_OP_GROUP == INT_OP_DC
151 #undef TARGET_ASM_BYTE_OP
152 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
155 #undef TARGET_ASM_ALIGNED_SI_OP
156 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
159 #undef TARGET_ASM_UNALIGNED_HI_OP
160 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
161 #undef TARGET_ASM_UNALIGNED_SI_OP
162 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
164 #undef TARGET_ASM_FUNCTION_PROLOGUE
165 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
166 #undef TARGET_ASM_FUNCTION_EPILOGUE
167 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
169 #undef TARGET_ASM_OUTPUT_MI_THUNK
170 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
171 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
172 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
174 #undef TARGET_ASM_FILE_START_APP_OFF
175 #define TARGET_ASM_FILE_START_APP_OFF true
177 #undef TARGET_DEFAULT_TARGET_FLAGS
178 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
179 #undef TARGET_HANDLE_OPTION
180 #define TARGET_HANDLE_OPTION m68k_handle_option
182 #undef TARGET_RTX_COSTS
183 #define TARGET_RTX_COSTS m68k_rtx_costs
185 #undef TARGET_ATTRIBUTE_TABLE
186 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
188 #undef TARGET_PROMOTE_PROTOTYPES
189 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
191 #undef TARGET_STRUCT_VALUE_RTX
192 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
194 #undef TARGET_CANNOT_FORCE_CONST_MEM
195 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
197 static const struct attribute_spec m68k_attribute_table
[] =
199 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
200 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
201 { NULL
, 0, 0, false, false, false, NULL
}
204 struct gcc_target targetm
= TARGET_INITIALIZER
;
206 /* Base flags for 68k ISAs. */
207 #define FL_FOR_isa_00 FL_ISA_68000
208 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
209 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
210 generated 68881 code for 68020 and 68030 targets unless explicitly told
212 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
213 | FL_BITFIELD | FL_68881)
214 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
215 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
217 /* Base flags for ColdFire ISAs. */
218 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
219 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
220 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
221 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
222 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
226 /* Traditional 68000 instruction sets. */
232 /* ColdFire instruction set variants. */
240 /* Information about one of the -march, -mcpu or -mtune arguments. */
241 struct m68k_target_selection
243 /* The argument being described. */
246 /* For -mcpu, this is the device selected by the option.
247 For -mtune and -march, it is a representative device
248 for the microarchitecture or ISA respectively. */
249 enum target_device device
;
251 /* The M68K_DEVICE fields associated with DEVICE. See the comment
252 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
254 enum uarch_type microarch
;
259 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
260 static const struct m68k_target_selection all_devices
[] =
262 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
263 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
264 #include "m68k-devices.def"
266 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
269 /* A list of all ISAs, mapping each one to a representative device.
270 Used for -march selection. */
271 static const struct m68k_target_selection all_isas
[] =
273 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
274 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
275 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
276 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
277 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
278 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
279 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
280 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
282 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
284 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
285 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
288 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
291 /* A list of all microarchitectures, mapping each one to a representative
292 device. Used for -mtune selection. */
293 static const struct m68k_target_selection all_microarchs
[] =
295 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
296 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
297 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
298 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
299 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
300 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
301 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
302 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
303 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
304 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
305 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
307 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
308 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
312 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
315 /* The entries associated with the -mcpu, -march and -mtune settings,
316 or null for options that have not been used. */
317 const struct m68k_target_selection
*m68k_cpu_entry
;
318 const struct m68k_target_selection
*m68k_arch_entry
;
319 const struct m68k_target_selection
*m68k_tune_entry
;
321 /* Which CPU we are generating code for. */
322 enum target_device m68k_cpu
;
324 /* Which microarchitecture to tune for. */
325 enum uarch_type m68k_tune
;
327 /* Which FPU to use. */
328 enum fpu_type m68k_fpu
;
330 /* The set of FL_* flags that apply to the target processor. */
331 unsigned int m68k_cpu_flags
;
333 /* Asm templates for calling or jumping to an arbitrary symbolic address,
334 or NULL if such calls or jumps are not supported. The address is held
336 const char *m68k_symbolic_call
;
337 const char *m68k_symbolic_jump
;
339 /* See whether TABLE has an entry with name NAME. Return true and
340 store the entry in *ENTRY if so, otherwise return false and
341 leave *ENTRY alone. */
344 m68k_find_selection (const struct m68k_target_selection
**entry
,
345 const struct m68k_target_selection
*table
,
350 for (i
= 0; table
[i
].name
; i
++)
351 if (strcmp (table
[i
].name
, name
) == 0)
359 /* Implement TARGET_HANDLE_OPTION. */
362 m68k_handle_option (size_t code
, const char *arg
, int value
)
367 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
370 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
373 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
376 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
379 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
382 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
385 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
388 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
391 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
395 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
398 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
402 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
405 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
407 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
410 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
412 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
415 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
418 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
421 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
424 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
428 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
430 case OPT_mshared_library_id_
:
431 if (value
> MAX_LIBRARY_ID
)
432 error ("-mshared-library-id=%s is not between 0 and %d",
433 arg
, MAX_LIBRARY_ID
);
435 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
443 /* Sometimes certain combinations of command options do not make
444 sense on a particular target machine. You can define a macro
445 `OVERRIDE_OPTIONS' to take account of this. This macro, if
446 defined, is executed once just after all the command options have
449 Don't use this macro to turn on various extra optimizations for
450 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
453 override_options (void)
455 const struct m68k_target_selection
*entry
;
456 unsigned long target_mask
;
464 -march=ARCH should generate code that runs any processor
465 implementing architecture ARCH. -mcpu=CPU should override -march
466 and should generate code that runs on processor CPU, making free
467 use of any instructions that CPU understands. -mtune=UARCH applies
468 on top of -mcpu or -march and optimizes the code for UARCH. It does
469 not change the target architecture. */
472 /* Complain if the -march setting is for a different microarchitecture,
473 or includes flags that the -mcpu setting doesn't. */
475 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
476 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
477 warning (0, "-mcpu=%s conflicts with -march=%s",
478 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
480 entry
= m68k_cpu_entry
;
483 entry
= m68k_arch_entry
;
486 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
488 m68k_cpu_flags
= entry
->flags
;
490 /* Use the architecture setting to derive default values for
493 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
494 target_mask
|= MASK_BITFIELD
;
495 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
496 target_mask
|= MASK_CF_HWDIV
;
497 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
498 target_mask
|= MASK_HARD_FLOAT
;
499 target_flags
|= target_mask
& ~target_flags_explicit
;
501 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
502 m68k_cpu
= entry
->device
;
504 m68k_tune
= m68k_tune_entry
->microarch
;
505 #ifdef M68K_DEFAULT_TUNE
506 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
507 m68k_tune
= M68K_DEFAULT_TUNE
;
510 m68k_tune
= entry
->microarch
;
512 /* Set the type of FPU. */
513 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
514 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
517 if (TARGET_COLDFIRE_FPU
)
519 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
520 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
523 /* Sanity check to ensure that msep-data and mid-sahred-library are not
524 * both specified together. Doing so simply doesn't make sense.
526 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
527 error ("cannot specify both -msep-data and -mid-shared-library");
529 /* If we're generating code for a separate A5 relative data segment,
530 * we've got to enable -fPIC as well. This might be relaxable to
531 * -fpic but it hasn't been tested properly.
533 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
536 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
537 error if the target does not support them. */
538 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
539 error ("-mpcrel -fPIC is not currently supported on selected cpu");
541 /* ??? A historic way of turning on pic, or is this intended to
542 be an embedded thing that doesn't have the same name binding
543 significance that it does on hosted ELF systems? */
544 if (TARGET_PCREL
&& flag_pic
== 0)
549 #if MOTOROLA && !defined (USE_GAS)
550 m68k_symbolic_call
= "jsr %a0";
551 m68k_symbolic_jump
= "jmp %a0";
553 m68k_symbolic_call
= "jbsr %a0";
554 m68k_symbolic_jump
= "jra %a0";
557 else if (TARGET_ID_SHARED_LIBRARY
)
558 /* All addresses must be loaded from the GOT. */
560 else if (TARGET_68020
|| TARGET_ISAB
)
564 m68k_symbolic_call
= "bsr.l %c0";
565 m68k_symbolic_jump
= "bra.l %c0";
570 m68k_symbolic_call
= "bsr.l %p0";
571 m68k_symbolic_jump
= "bra.l %p0";
573 m68k_symbolic_call
= "bsr %p0";
574 m68k_symbolic_jump
= "bra %p0";
577 /* Turn off function cse if we are doing PIC. We always want
578 function call to be done as `bsr foo@PLTPC'. */
579 /* ??? It's traditional to do this for -mpcrel too, but it isn't
580 clear how intentional that is. */
581 flag_no_function_cse
= 1;
584 SUBTARGET_OVERRIDE_OPTIONS
;
587 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
588 given argument and NAME is the argument passed to -mcpu. Return NULL
589 if -mcpu was not passed. */
592 m68k_cpp_cpu_ident (const char *prefix
)
596 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
599 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
600 given argument and NAME is the name of the representative device for
601 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
604 m68k_cpp_cpu_family (const char *prefix
)
608 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
611 /* Return nonzero if FUNC is an interrupt function as specified by the
612 "interrupt_handler" attribute. */
614 m68k_interrupt_function_p(tree func
)
618 if (TREE_CODE (func
) != FUNCTION_DECL
)
621 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
622 return (a
!= NULL_TREE
);
625 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
626 struct attribute_spec.handler. */
628 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
629 tree args ATTRIBUTE_UNUSED
,
630 int flags ATTRIBUTE_UNUSED
,
633 if (TREE_CODE (*node
) != FUNCTION_DECL
)
635 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
636 IDENTIFIER_POINTER (name
));
637 *no_add_attrs
= true;
644 m68k_compute_frame_layout (void)
647 unsigned int mask
, rmask
;
648 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
650 /* Only compute the frame once per function.
651 Don't cache information until reload has been completed. */
652 if (current_frame
.funcdef_no
== current_function_funcdef_no
656 current_frame
.size
= (get_frame_size () + 3) & -4;
658 mask
= rmask
= saved
= 0;
659 for (regno
= 0; regno
< 16; regno
++)
660 if (m68k_save_reg (regno
, interrupt_handler
))
663 rmask
|= 1 << (15 - regno
);
666 current_frame
.offset
= saved
* 4;
667 current_frame
.reg_no
= saved
;
668 current_frame
.reg_mask
= mask
;
669 current_frame
.reg_rev_mask
= rmask
;
671 current_frame
.foffset
= 0;
672 mask
= rmask
= saved
= 0;
673 if (TARGET_HARD_FLOAT
)
675 for (regno
= 16; regno
< 24; regno
++)
676 if (m68k_save_reg (regno
, interrupt_handler
))
678 mask
|= 1 << (regno
- 16);
679 rmask
|= 1 << (23 - regno
);
682 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
683 current_frame
.offset
+= current_frame
.foffset
;
685 current_frame
.fpu_no
= saved
;
686 current_frame
.fpu_mask
= mask
;
687 current_frame
.fpu_rev_mask
= rmask
;
689 /* Remember what function this frame refers to. */
690 current_frame
.funcdef_no
= current_function_funcdef_no
;
694 m68k_initial_elimination_offset (int from
, int to
)
697 /* The arg pointer points 8 bytes before the start of the arguments,
698 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
699 frame pointer in most frames. */
700 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
701 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
702 return argptr_offset
;
704 m68k_compute_frame_layout ();
706 gcc_assert (to
== STACK_POINTER_REGNUM
);
709 case ARG_POINTER_REGNUM
:
710 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
711 case FRAME_POINTER_REGNUM
:
712 return current_frame
.offset
+ current_frame
.size
;
718 /* Refer to the array `regs_ever_live' to determine which registers
719 to save; `regs_ever_live[I]' is nonzero if register number I
720 is ever used in the function. This function is responsible for
721 knowing which registers should not be saved even if used.
722 Return true if we need to save REGNO. */
725 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
727 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
729 if (current_function_uses_pic_offset_table
)
731 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
735 if (current_function_calls_eh_return
)
740 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
741 if (test
== INVALID_REGNUM
)
748 /* Fixed regs we never touch. */
749 if (fixed_regs
[regno
])
752 /* The frame pointer (if it is such) is handled specially. */
753 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
756 /* Interrupt handlers must also save call_used_regs
757 if they are live or when calling nested functions. */
758 if (interrupt_handler
)
760 if (regs_ever_live
[regno
])
763 if (!current_function_is_leaf
&& call_used_regs
[regno
])
767 /* Never need to save registers that aren't touched. */
768 if (!regs_ever_live
[regno
])
771 /* Otherwise save everything that isn't call-clobbered. */
772 return !call_used_regs
[regno
];
775 /* This function generates the assembly code for function entry.
776 STREAM is a stdio stream to output the code to.
777 SIZE is an int: how many units of temporary storage to allocate. */
780 m68k_output_function_prologue (FILE *stream
,
781 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
783 HOST_WIDE_INT fsize_with_regs
;
784 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
786 m68k_compute_frame_layout();
788 /* If the stack limit is a symbol, we can check it here,
789 before actually allocating the space. */
790 if (current_function_limit_stack
791 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
792 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
793 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
795 /* On ColdFire add register save into initial stack frame setup, if possible. */
796 fsize_with_regs
= current_frame
.size
;
799 if (current_frame
.reg_no
> 2)
800 fsize_with_regs
+= current_frame
.reg_no
* 4;
801 if (current_frame
.fpu_no
)
802 fsize_with_regs
+= current_frame
.fpu_no
* 8;
805 if (frame_pointer_needed
)
807 if (current_frame
.size
== 0 && TUNE_68040
)
808 /* on the 68040, pea + move is faster than link.w 0 */
809 fprintf (stream
, (MOTOROLA
810 ? "\tpea (%s)\n\tmove.l %s,%s\n"
811 : "\tpea %s@\n\tmovel %s,%s\n"),
812 M68K_REGNAME (FRAME_POINTER_REGNUM
),
813 M68K_REGNAME (STACK_POINTER_REGNUM
),
814 M68K_REGNAME (FRAME_POINTER_REGNUM
));
815 else if (fsize_with_regs
< 0x8000)
816 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
817 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
818 else if (TARGET_68020
)
819 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
820 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
822 /* Adding negative number is faster on the 68040. */
824 "\tlink" ASM_DOTW
" %s,%I0\n"
825 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
826 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
828 else if (fsize_with_regs
) /* !frame_pointer_needed */
830 if (fsize_with_regs
< 0x8000)
832 if (fsize_with_regs
<= 8)
834 if (!TARGET_COLDFIRE
)
835 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
838 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
841 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
842 /* On the CPU32 it is faster to use two subqw instructions to
843 subtract a small integer (8 < N <= 16) to a register. */
845 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
846 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
847 fsize_with_regs
- 8);
849 /* Adding negative number is faster on the 68040. */
850 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
853 asm_fprintf (stream
, (MOTOROLA
854 ? "\tlea (%wd,%Rsp),%Rsp\n"
855 : "\tlea %Rsp@(%wd),%Rsp\n"),
858 else /* fsize_with_regs >= 0x8000 */
859 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
861 } /* !frame_pointer_needed */
863 if (dwarf2out_do_frame ())
865 if (frame_pointer_needed
)
868 l
= (char *) dwarf2out_cfi_label ();
870 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
871 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
872 cfa_offset
+= current_frame
.size
;
876 cfa_offset
+= current_frame
.size
;
877 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
881 if (current_frame
.fpu_mask
)
885 asm_fprintf (stream
, (MOTOROLA
886 ? "\tfmovm %I0x%x,-(%Rsp)\n"
887 : "\tfmovem %I0x%x,%Rsp@-\n"),
888 current_frame
.fpu_mask
);
894 /* stack already has registers in it. Find the offset from
895 the bottom of stack to where the FP registers go */
896 if (current_frame
.reg_no
<= 2)
899 offset
= current_frame
.reg_no
* 4;
902 "\tfmovem %I0x%x,%d(%Rsp)\n",
903 current_frame
.fpu_rev_mask
,
907 "\tfmovem %I0x%x,(%Rsp)\n",
908 current_frame
.fpu_rev_mask
);
911 if (dwarf2out_do_frame ())
913 char *l
= (char *) dwarf2out_cfi_label ();
916 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
917 if (! frame_pointer_needed
)
918 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
919 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
920 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
921 dwarf2out_reg_save (l
, regno
, -cfa_offset
922 + n_regs
++ * TARGET_FP_REG_SIZE
);
926 /* If the stack limit is not a symbol, check it here.
927 This has the disadvantage that it may be too late... */
928 if (current_function_limit_stack
)
930 if (REG_P (stack_limit_rtx
))
931 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
932 M68K_REGNAME (REGNO (stack_limit_rtx
)));
933 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
934 warning (0, "stack limit expression is not supported");
937 if (current_frame
.reg_no
<= 2)
939 /* Store each separately in the same order moveml uses.
940 Using two movel instructions instead of a single moveml
941 is about 15% faster for the 68020 and 68030 at no expense
946 for (i
= 0; i
< 16; i
++)
947 if (current_frame
.reg_rev_mask
& (1 << i
))
949 asm_fprintf (stream
, (MOTOROLA
950 ? "\t%Omove.l %s,-(%Rsp)\n"
951 : "\tmovel %s,%Rsp@-\n"),
952 M68K_REGNAME (15 - i
));
953 if (dwarf2out_do_frame ())
955 char *l
= (char *) dwarf2out_cfi_label ();
958 if (! frame_pointer_needed
)
959 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
960 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
964 else if (current_frame
.reg_rev_mask
)
967 /* The ColdFire does not support the predecrement form of the
968 MOVEM instruction, so we must adjust the stack pointer and
969 then use the plain address register indirect mode.
970 The required register save space was combined earlier with
971 the fsize_with_regs amount. */
973 asm_fprintf (stream
, (MOTOROLA
974 ? "\tmovm.l %I0x%x,(%Rsp)\n"
975 : "\tmoveml %I0x%x,%Rsp@\n"),
976 current_frame
.reg_mask
);
978 asm_fprintf (stream
, (MOTOROLA
979 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
980 : "\tmoveml %I0x%x,%Rsp@-\n"),
981 current_frame
.reg_rev_mask
);
982 if (dwarf2out_do_frame ())
984 char *l
= (char *) dwarf2out_cfi_label ();
987 cfa_offset
+= current_frame
.reg_no
* 4;
988 if (! frame_pointer_needed
)
989 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
990 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
991 if (current_frame
.reg_mask
& (1 << regno
))
992 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
995 if (!TARGET_SEP_DATA
&& flag_pic
996 && (current_function_uses_pic_offset_table
997 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
999 if (TARGET_ID_SHARED_LIBRARY
)
1001 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
1002 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1003 m68k_library_id_string
,
1004 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1009 asm_fprintf (stream
,
1010 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
1011 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1014 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
1015 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1016 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
1017 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1018 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1024 /* Return true if a simple (return) instruction is sufficient for this
1025 instruction (i.e. if no epilogue is needed). */
1028 m68k_use_return_insn (void)
1030 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1033 m68k_compute_frame_layout ();
1034 return current_frame
.offset
== 0;
1037 /* This function generates the assembly code for function exit,
1038 on machines that need it.
1040 The function epilogue should not depend on the current stack pointer!
1041 It should use the frame pointer only, if there is a frame pointer.
1042 This is mandatory because of alloca; we also take advantage of it to
1043 omit stack adjustments before returning. */
1046 m68k_output_function_epilogue (FILE *stream
,
1047 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1049 HOST_WIDE_INT fsize
, fsize_with_regs
;
1051 bool restore_from_sp
= false;
1052 rtx insn
= get_last_insn ();
1054 m68k_compute_frame_layout ();
1056 /* If the last insn was a BARRIER, we don't have to write any code. */
1057 if (GET_CODE (insn
) == NOTE
)
1058 insn
= prev_nonnote_insn (insn
);
1059 if (insn
&& GET_CODE (insn
) == BARRIER
)
1062 fsize
= current_frame
.size
;
1064 /* FIXME: leaf_function_p below is too strong.
1065 What we really need to know there is if there could be pending
1066 stack adjustment needed at that point. */
1068 = (! frame_pointer_needed
1069 || (! current_function_calls_alloca
&& leaf_function_p ()));
1071 /* fsize_with_regs is the size we need to adjust the sp when
1072 popping the frame. */
1073 fsize_with_regs
= fsize
;
1075 /* Because the ColdFire doesn't support moveml with
1076 complex address modes, we must adjust the stack manually
1077 after restoring registers. When the frame pointer isn't used,
1078 we can merge movem adjustment into frame unlinking
1079 made immediately after it. */
1080 if (TARGET_COLDFIRE
&& restore_from_sp
)
1082 if (current_frame
.reg_no
> 2)
1083 fsize_with_regs
+= current_frame
.reg_no
* 4;
1084 if (current_frame
.fpu_no
)
1085 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1088 if (current_frame
.offset
+ fsize
>= 0x8000
1089 && ! restore_from_sp
1090 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1092 /* Because the ColdFire doesn't support moveml with
1093 complex address modes we make an extra correction here. */
1094 if (TARGET_COLDFIRE
)
1095 fsize
+= current_frame
.offset
;
1097 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1098 fsize
= 0, big
= true;
1100 if (current_frame
.reg_no
<= 2)
1102 /* Restore each separately in the same order moveml does.
1103 Using two movel instructions instead of a single moveml
1104 is about 15% faster for the 68020 and 68030 at no expense
1108 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1110 for (i
= 0; i
< 16; i
++)
1111 if (current_frame
.reg_mask
& (1 << i
))
1116 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1118 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1121 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1122 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1126 else if (restore_from_sp
)
1127 asm_fprintf (stream
, (MOTOROLA
1128 ? "\t%Omove.l (%Rsp)+,%s\n"
1129 : "\tmovel %Rsp@+,%s\n"),
1134 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1136 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1139 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1140 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1147 else if (current_frame
.reg_mask
)
1149 /* The ColdFire requires special handling due to its limited moveml
1151 if (TARGET_COLDFIRE
)
1155 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1156 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1157 asm_fprintf (stream
, (MOTOROLA
1158 ? "\tmovm.l (%Ra1),%I0x%x\n"
1159 : "\tmoveml %Ra1@,%I0x%x\n"),
1160 current_frame
.reg_mask
);
1162 else if (restore_from_sp
)
1163 asm_fprintf (stream
, (MOTOROLA
1164 ? "\tmovm.l (%Rsp),%I0x%x\n"
1165 : "\tmoveml %Rsp@,%I0x%x\n"),
1166 current_frame
.reg_mask
);
1170 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1171 current_frame
.offset
+ fsize
,
1172 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1173 current_frame
.reg_mask
);
1175 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1176 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1177 current_frame
.offset
+ fsize
,
1178 current_frame
.reg_mask
);
1181 else /* !TARGET_COLDFIRE */
1186 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1187 current_frame
.offset
+ fsize
,
1188 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1189 current_frame
.reg_mask
);
1191 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1192 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1193 current_frame
.offset
+ fsize
,
1194 current_frame
.reg_mask
);
1196 else if (restore_from_sp
)
1198 asm_fprintf (stream
, (MOTOROLA
1199 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1200 : "\tmoveml %Rsp@+,%I0x%x\n"),
1201 current_frame
.reg_mask
);
1206 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1207 current_frame
.offset
+ fsize
,
1208 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1209 current_frame
.reg_mask
);
1211 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1212 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1213 current_frame
.offset
+ fsize
,
1214 current_frame
.reg_mask
);
1218 if (current_frame
.fpu_rev_mask
)
1222 if (TARGET_COLDFIRE
)
1224 if (current_frame
.reg_no
)
1225 asm_fprintf (stream
, MOTOROLA
?
1226 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1227 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1228 current_frame
.reg_no
* 4,
1229 current_frame
.fpu_rev_mask
);
1231 asm_fprintf (stream
, MOTOROLA
?
1232 "\tfmovem.d (%Ra1),%I0x%x\n" :
1233 "\tfmovmd (%Ra1),%I0x%x\n",
1234 current_frame
.fpu_rev_mask
);
1237 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1238 current_frame
.foffset
+ fsize
,
1239 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1240 current_frame
.fpu_rev_mask
);
1242 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1243 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1244 current_frame
.foffset
+ fsize
,
1245 current_frame
.fpu_rev_mask
);
1247 else if (restore_from_sp
)
1249 if (TARGET_COLDFIRE
)
1253 /* Stack already has registers in it. Find the offset from
1254 the bottom of stack to where the FP registers go. */
1255 if (current_frame
.reg_no
<= 2)
1258 offset
= current_frame
.reg_no
* 4;
1260 asm_fprintf (stream
,
1261 "\tfmovem %Rsp@(%d), %I0x%x\n",
1262 offset
, current_frame
.fpu_rev_mask
);
1264 asm_fprintf (stream
,
1265 "\tfmovem %Rsp@, %I0x%x\n",
1266 current_frame
.fpu_rev_mask
);
1269 asm_fprintf (stream
, MOTOROLA
?
1270 "\tfmovm (%Rsp)+,%I0x%x\n" :
1271 "\tfmovem %Rsp@+,%I0x%x\n",
1272 current_frame
.fpu_rev_mask
);
1276 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1277 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1278 current_frame
.foffset
+ fsize
,
1279 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1280 current_frame
.fpu_rev_mask
);
1282 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1283 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1284 current_frame
.foffset
+ fsize
,
1285 current_frame
.fpu_rev_mask
);
1288 if (frame_pointer_needed
)
1289 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1290 else if (fsize_with_regs
)
1292 if (fsize_with_regs
<= 8)
1294 if (!TARGET_COLDFIRE
)
1295 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1298 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1301 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1303 /* On the CPU32 it is faster to use two addqw instructions to
1304 add a small integer (8 < N <= 16) to a register. */
1305 asm_fprintf (stream
,
1306 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1307 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1308 fsize_with_regs
- 8);
1310 else if (fsize_with_regs
< 0x8000)
1313 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1316 asm_fprintf (stream
, (MOTOROLA
1317 ? "\tlea (%wd,%Rsp),%Rsp\n"
1318 : "\tlea %Rsp@(%wd),%Rsp\n"),
1322 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1324 if (current_function_calls_eh_return
)
1325 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1326 if (m68k_interrupt_function_p (current_function_decl
))
1327 fprintf (stream
, "\trte\n");
1328 else if (current_function_pops_args
)
1329 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1331 fprintf (stream
, "\trts\n");
1334 /* Return true if X is a valid comparison operator for the dbcc
1337 Note it rejects floating point comparison operators.
1338 (In the future we could use Fdbcc).
1340 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1343 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1345 switch (GET_CODE (x
))
1347 case EQ
: case NE
: case GTU
: case LTU
:
1351 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1353 case GT
: case LT
: case GE
: case LE
:
1354 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1360 /* Return nonzero if flags are currently in the 68881 flag register. */
1362 flags_in_68881 (void)
1364 /* We could add support for these in the future */
1365 return cc_status
.flags
& CC_IN_68881
;
1368 /* Convert X to a legitimate function call memory reference and return the
1372 m68k_legitimize_call_address (rtx x
)
1374 gcc_assert (MEM_P (x
));
1375 if (call_operand (XEXP (x
, 0), VOIDmode
))
1377 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1380 /* Output a dbCC; jCC sequence. Note we do not handle the
1381 floating point version of this sequence (Fdbcc). We also
1382 do not handle alternative conditions when CC_NO_OVERFLOW is
1383 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1384 kick those out before we get here. */
1387 output_dbcc_and_branch (rtx
*operands
)
1389 switch (GET_CODE (operands
[3]))
1392 output_asm_insn (MOTOROLA
1393 ? "dbeq %0,%l1\n\tjbeq %l2"
1394 : "dbeq %0,%l1\n\tjeq %l2",
1399 output_asm_insn (MOTOROLA
1400 ? "dbne %0,%l1\n\tjbne %l2"
1401 : "dbne %0,%l1\n\tjne %l2",
1406 output_asm_insn (MOTOROLA
1407 ? "dbgt %0,%l1\n\tjbgt %l2"
1408 : "dbgt %0,%l1\n\tjgt %l2",
1413 output_asm_insn (MOTOROLA
1414 ? "dbhi %0,%l1\n\tjbhi %l2"
1415 : "dbhi %0,%l1\n\tjhi %l2",
1420 output_asm_insn (MOTOROLA
1421 ? "dblt %0,%l1\n\tjblt %l2"
1422 : "dblt %0,%l1\n\tjlt %l2",
1427 output_asm_insn (MOTOROLA
1428 ? "dbcs %0,%l1\n\tjbcs %l2"
1429 : "dbcs %0,%l1\n\tjcs %l2",
1434 output_asm_insn (MOTOROLA
1435 ? "dbge %0,%l1\n\tjbge %l2"
1436 : "dbge %0,%l1\n\tjge %l2",
1441 output_asm_insn (MOTOROLA
1442 ? "dbcc %0,%l1\n\tjbcc %l2"
1443 : "dbcc %0,%l1\n\tjcc %l2",
1448 output_asm_insn (MOTOROLA
1449 ? "dble %0,%l1\n\tjble %l2"
1450 : "dble %0,%l1\n\tjle %l2",
1455 output_asm_insn (MOTOROLA
1456 ? "dbls %0,%l1\n\tjbls %l2"
1457 : "dbls %0,%l1\n\tjls %l2",
1465 /* If the decrement is to be done in SImode, then we have
1466 to compensate for the fact that dbcc decrements in HImode. */
1467 switch (GET_MODE (operands
[0]))
1470 output_asm_insn (MOTOROLA
1471 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1472 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1485 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1488 enum rtx_code op_code
= GET_CODE (op
);
1490 /* This does not produce a useful cc. */
1493 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1494 below. Swap the operands and change the op if these requirements
1495 are not fulfilled. */
1496 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1500 operand1
= operand2
;
1502 op_code
= swap_condition (op_code
);
1504 loperands
[0] = operand1
;
1505 if (GET_CODE (operand1
) == REG
)
1506 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1508 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1509 if (operand2
!= const0_rtx
)
1511 loperands
[2] = operand2
;
1512 if (GET_CODE (operand2
) == REG
)
1513 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1515 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1517 loperands
[4] = gen_label_rtx ();
1518 if (operand2
!= const0_rtx
)
1520 output_asm_insn (MOTOROLA
1521 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1522 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1527 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1528 output_asm_insn ("tst%.l %0", loperands
);
1530 output_asm_insn ("cmp%.w #0,%0", loperands
);
1532 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1534 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1535 output_asm_insn ("tst%.l %1", loperands
);
1537 output_asm_insn ("cmp%.w #0,%1", loperands
);
1540 loperands
[5] = dest
;
1545 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1546 CODE_LABEL_NUMBER (loperands
[4]));
1547 output_asm_insn ("seq %5", loperands
);
1551 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1552 CODE_LABEL_NUMBER (loperands
[4]));
1553 output_asm_insn ("sne %5", loperands
);
1557 loperands
[6] = gen_label_rtx ();
1558 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1560 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1561 CODE_LABEL_NUMBER (loperands
[4]));
1562 output_asm_insn ("sgt %5", loperands
);
1563 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1564 CODE_LABEL_NUMBER (loperands
[6]));
1568 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1569 CODE_LABEL_NUMBER (loperands
[4]));
1570 output_asm_insn ("shi %5", loperands
);
1574 loperands
[6] = gen_label_rtx ();
1575 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1577 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1578 CODE_LABEL_NUMBER (loperands
[4]));
1579 output_asm_insn ("slt %5", loperands
);
1580 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1581 CODE_LABEL_NUMBER (loperands
[6]));
1585 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1586 CODE_LABEL_NUMBER (loperands
[4]));
1587 output_asm_insn ("scs %5", loperands
);
1591 loperands
[6] = gen_label_rtx ();
1592 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1594 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1595 CODE_LABEL_NUMBER (loperands
[4]));
1596 output_asm_insn ("sge %5", loperands
);
1597 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1598 CODE_LABEL_NUMBER (loperands
[6]));
1602 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1603 CODE_LABEL_NUMBER (loperands
[4]));
1604 output_asm_insn ("scc %5", loperands
);
1608 loperands
[6] = gen_label_rtx ();
1609 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1611 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1612 CODE_LABEL_NUMBER (loperands
[4]));
1613 output_asm_insn ("sle %5", loperands
);
1614 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1615 CODE_LABEL_NUMBER (loperands
[6]));
1619 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1620 CODE_LABEL_NUMBER (loperands
[4]));
1621 output_asm_insn ("sls %5", loperands
);
1631 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1633 operands
[0] = countop
;
1634 operands
[1] = dataop
;
1636 if (GET_CODE (countop
) == CONST_INT
)
1638 register int count
= INTVAL (countop
);
1639 /* If COUNT is bigger than size of storage unit in use,
1640 advance to the containing unit of same size. */
1641 if (count
> signpos
)
1643 int offset
= (count
& ~signpos
) / 8;
1644 count
= count
& signpos
;
1645 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1647 if (count
== signpos
)
1648 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1650 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1652 /* These three statements used to use next_insns_test_no...
1653 but it appears that this should do the same job. */
1655 && next_insn_tests_no_inequality (insn
))
1658 && next_insn_tests_no_inequality (insn
))
1661 && next_insn_tests_no_inequality (insn
))
1664 cc_status
.flags
= CC_NOT_NEGATIVE
;
1666 return "btst %0,%1";
1669 /* Return true if X is an illegitimate symbolic constant. */
1672 m68k_illegitimate_symbolic_constant_p (rtx x
)
1676 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1678 split_const (x
, &base
, &offset
);
1679 if (GET_CODE (base
) == SYMBOL_REF
1680 && !offset_within_block_p (base
, INTVAL (offset
)))
1686 /* Legitimize PIC addresses. If the address is already
1687 position-independent, we return ORIG. Newly generated
1688 position-independent addresses go to REG. If we need more
1689 than one register, we lose.
1691 An address is legitimized by making an indirect reference
1692 through the Global Offset Table with the name of the symbol
1695 The assembler and linker are responsible for placing the
1696 address of the symbol in the GOT. The function prologue
1697 is responsible for initializing a5 to the starting address
1700 The assembler is also responsible for translating a symbol name
1701 into a constant displacement from the start of the GOT.
1703 A quick example may make things a little clearer:
1705 When not generating PIC code to store the value 12345 into _foo
1706 we would generate the following code:
1710 When generating PIC two transformations are made. First, the compiler
1711 loads the address of foo into a register. So the first transformation makes:
1716 The code in movsi will intercept the lea instruction and call this
1717 routine which will transform the instructions into:
1719 movel a5@(_foo:w), a0
1723 That (in a nutshell) is how *all* symbol and label references are
1727 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1732 /* First handle a simple SYMBOL_REF or LABEL_REF */
1733 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1737 pic_ref
= gen_rtx_MEM (Pmode
,
1738 gen_rtx_PLUS (Pmode
,
1739 pic_offset_table_rtx
, orig
));
1740 current_function_uses_pic_offset_table
= 1;
1741 MEM_READONLY_P (pic_ref
) = 1;
1742 emit_move_insn (reg
, pic_ref
);
1745 else if (GET_CODE (orig
) == CONST
)
1749 /* Make sure this has not already been legitimized. */
1750 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1751 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1756 /* legitimize both operands of the PLUS */
1757 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1759 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1760 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1761 base
== reg
? 0 : reg
);
1763 if (GET_CODE (orig
) == CONST_INT
)
1764 return plus_constant (base
, INTVAL (orig
));
1765 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1766 /* Likewise, should we set special REG_NOTEs here? */
1772 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1774 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1776 /* Return the type of move that should be used for integer I. */
1779 const_method (HOST_WIDE_INT i
)
1786 /* The ColdFire doesn't have byte or word operations. */
1787 /* FIXME: This may not be useful for the m68060 either. */
1788 if (!TARGET_COLDFIRE
)
1790 /* if -256 < N < 256 but N is not in range for a moveq
1791 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1792 if (USE_MOVQ (i
^ 0xff))
1794 /* Likewise, try with not.w */
1795 if (USE_MOVQ (i
^ 0xffff))
1797 /* This is the only value where neg.w is useful */
1802 /* Try also with swap. */
1804 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1809 /* Try using MVZ/MVS with an immediate value to load constants. */
1810 if (i
>= 0 && i
<= 65535)
1812 if (i
>= -32768 && i
<= 32767)
1816 /* Otherwise, use move.l */
1820 /* Return the cost of moving constant I into a data register. */
1823 const_int_cost (HOST_WIDE_INT i
)
1825 switch (const_method (i
))
1828 /* Constants between -128 and 127 are cheap due to moveq. */
1836 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1846 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1851 /* Constant zero is super cheap due to clr instruction. */
1852 if (x
== const0_rtx
)
1855 *total
= const_int_cost (INTVAL (x
));
1865 /* Make 0.0 cheaper than other floating constants to
1866 encourage creating tstsf and tstdf insns. */
1867 if (outer_code
== COMPARE
1868 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1874 /* These are vaguely right for a 68020. */
1875 /* The costs for long multiply have been adjusted to work properly
1876 in synth_mult on the 68020, relative to an average of the time
1877 for add and the time for shift, taking away a little more because
1878 sometimes move insns are needed. */
1879 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1885 : TARGET_COLDFIRE ? 3 : 13)
1890 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1891 : TARGET_COLDFIRE ? 2 : 8)
1894 (TARGET_CF_HWDIV ? 11 \
1895 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1898 /* An lea costs about three times as much as a simple add. */
1899 if (GET_MODE (x
) == SImode
1900 && GET_CODE (XEXP (x
, 1)) == REG
1901 && GET_CODE (XEXP (x
, 0)) == MULT
1902 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1903 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1904 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1905 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1906 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1908 /* lea an@(dx:l:i),am */
1909 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1919 *total
= COSTS_N_INSNS(1);
1924 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1926 if (INTVAL (XEXP (x
, 1)) < 16)
1927 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1929 /* We're using clrw + swap for these cases. */
1930 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1933 *total
= COSTS_N_INSNS (10); /* Worst case. */
1936 /* A shift by a big integer takes an extra instruction. */
1937 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1938 && (INTVAL (XEXP (x
, 1)) == 16))
1940 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1943 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1944 && !(INTVAL (XEXP (x
, 1)) > 0
1945 && INTVAL (XEXP (x
, 1)) <= 8))
1947 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1953 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1954 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1955 && GET_MODE (x
) == SImode
)
1956 *total
= COSTS_N_INSNS (MULW_COST
);
1957 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1958 *total
= COSTS_N_INSNS (MULW_COST
);
1960 *total
= COSTS_N_INSNS (MULL_COST
);
1967 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1968 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1969 else if (TARGET_CF_HWDIV
)
1970 *total
= COSTS_N_INSNS (18);
1972 *total
= COSTS_N_INSNS (43); /* div.l */
1980 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
1984 output_move_const_into_data_reg (rtx
*operands
)
1988 i
= INTVAL (operands
[1]);
1989 switch (const_method (i
))
1992 return "mvzw %1,%0";
1994 return "mvsw %1,%0";
1996 return "moveq %1,%0";
1999 operands
[1] = GEN_INT (i
^ 0xff);
2000 return "moveq %1,%0\n\tnot%.b %0";
2003 operands
[1] = GEN_INT (i
^ 0xffff);
2004 return "moveq %1,%0\n\tnot%.w %0";
2007 return "moveq #-128,%0\n\tneg%.w %0";
2012 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2013 return "moveq %1,%0\n\tswap %0";
2016 return "move%.l %1,%0";
2022 /* Return true if I can be handled by ISA B's mov3q instruction. */
2025 valid_mov3q_const (HOST_WIDE_INT i
)
2027 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2030 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2031 I is the value of OPERANDS[1]. */
2034 output_move_simode_const (rtx
*operands
)
2040 src
= INTVAL (operands
[1]);
2042 && (DATA_REG_P (dest
) || MEM_P (dest
))
2043 /* clr insns on 68000 read before writing. */
2044 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2045 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2047 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2048 return "mov3q%.l %1,%0";
2049 else if (src
== 0 && ADDRESS_REG_P (dest
))
2050 return "sub%.l %0,%0";
2051 else if (DATA_REG_P (dest
))
2052 return output_move_const_into_data_reg (operands
);
2053 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2055 if (valid_mov3q_const (src
))
2056 return "mov3q%.l %1,%0";
2057 return "move%.w %1,%0";
2059 else if (MEM_P (dest
)
2060 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2061 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2062 && IN_RANGE (src
, -0x8000, 0x7fff))
2064 if (valid_mov3q_const (src
))
2065 return "mov3q%.l %1,%-";
2068 return "move%.l %1,%0";
2072 output_move_simode (rtx
*operands
)
2074 if (GET_CODE (operands
[1]) == CONST_INT
)
2075 return output_move_simode_const (operands
);
2076 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2077 || GET_CODE (operands
[1]) == CONST
)
2078 && push_operand (operands
[0], SImode
))
2080 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2081 || GET_CODE (operands
[1]) == CONST
)
2082 && ADDRESS_REG_P (operands
[0]))
2083 return "lea %a1,%0";
2084 return "move%.l %1,%0";
2088 output_move_himode (rtx
*operands
)
2090 if (GET_CODE (operands
[1]) == CONST_INT
)
2092 if (operands
[1] == const0_rtx
2093 && (DATA_REG_P (operands
[0])
2094 || GET_CODE (operands
[0]) == MEM
)
2095 /* clr insns on 68000 read before writing. */
2096 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2097 || !(GET_CODE (operands
[0]) == MEM
2098 && MEM_VOLATILE_P (operands
[0]))))
2100 else if (operands
[1] == const0_rtx
2101 && ADDRESS_REG_P (operands
[0]))
2102 return "sub%.l %0,%0";
2103 else if (DATA_REG_P (operands
[0])
2104 && INTVAL (operands
[1]) < 128
2105 && INTVAL (operands
[1]) >= -128)
2106 return "moveq %1,%0";
2107 else if (INTVAL (operands
[1]) < 0x8000
2108 && INTVAL (operands
[1]) >= -0x8000)
2109 return "move%.w %1,%0";
2111 else if (CONSTANT_P (operands
[1]))
2112 return "move%.l %1,%0";
2113 /* Recognize the insn before a tablejump, one that refers
2114 to a table of offsets. Such an insn will need to refer
2115 to a label on the insn. So output one. Use the label-number
2116 of the table of offsets to generate this label. This code,
2117 and similar code below, assumes that there will be at most one
2118 reference to each table. */
2119 if (GET_CODE (operands
[1]) == MEM
2120 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2121 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2122 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2124 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2126 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2127 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2129 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2130 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2132 return "move%.w %1,%0";
2136 output_move_qimode (rtx
*operands
)
2138 /* 68k family always modifies the stack pointer by at least 2, even for
2139 byte pushes. The 5200 (ColdFire) does not do this. */
2141 /* This case is generated by pushqi1 pattern now. */
2142 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2143 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2144 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2145 && ! ADDRESS_REG_P (operands
[1])
2146 && ! TARGET_COLDFIRE
));
2148 /* clr and st insns on 68000 read before writing. */
2149 if (!ADDRESS_REG_P (operands
[0])
2150 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2151 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2153 if (operands
[1] == const0_rtx
)
2155 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2156 && GET_CODE (operands
[1]) == CONST_INT
2157 && (INTVAL (operands
[1]) & 255) == 255)
2163 if (GET_CODE (operands
[1]) == CONST_INT
2164 && DATA_REG_P (operands
[0])
2165 && INTVAL (operands
[1]) < 128
2166 && INTVAL (operands
[1]) >= -128)
2167 return "moveq %1,%0";
2168 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2169 return "sub%.l %0,%0";
2170 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2171 return "move%.l %1,%0";
2172 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2173 from address registers. */
2174 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2175 return "move%.w %1,%0";
2176 return "move%.b %1,%0";
2180 output_move_stricthi (rtx
*operands
)
2182 if (operands
[1] == const0_rtx
2183 /* clr insns on 68000 read before writing. */
2184 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2185 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2187 return "move%.w %1,%0";
2191 output_move_strictqi (rtx
*operands
)
2193 if (operands
[1] == const0_rtx
2194 /* clr insns on 68000 read before writing. */
2195 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2196 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2198 return "move%.b %1,%0";
2201 /* Return the best assembler insn template
2202 for moving operands[1] into operands[0] as a fullword. */
2205 singlemove_string (rtx
*operands
)
2207 if (GET_CODE (operands
[1]) == CONST_INT
)
2208 return output_move_simode_const (operands
);
2209 return "move%.l %1,%0";
2213 /* Output assembler code to perform a doubleword move insn
2214 with operands OPERANDS. */
2217 output_move_double (rtx
*operands
)
2221 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2226 rtx addreg0
= 0, addreg1
= 0;
2227 int dest_overlapped_low
= 0;
2228 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2233 /* First classify both operands. */
2235 if (REG_P (operands
[0]))
2237 else if (offsettable_memref_p (operands
[0]))
2239 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2241 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2243 else if (GET_CODE (operands
[0]) == MEM
)
2248 if (REG_P (operands
[1]))
2250 else if (CONSTANT_P (operands
[1]))
2252 else if (offsettable_memref_p (operands
[1]))
2254 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2256 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2258 else if (GET_CODE (operands
[1]) == MEM
)
2263 /* Check for the cases that the operand constraints are not supposed
2264 to allow to happen. Generating code for these cases is
2266 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2268 /* If one operand is decrementing and one is incrementing
2269 decrement the former register explicitly
2270 and change that operand into ordinary indexing. */
2272 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2274 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2276 output_asm_insn ("sub%.l #12,%0", operands
);
2278 output_asm_insn ("subq%.l #8,%0", operands
);
2279 if (GET_MODE (operands
[1]) == XFmode
)
2280 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2281 else if (GET_MODE (operands
[0]) == DFmode
)
2282 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2284 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2287 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2289 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2291 output_asm_insn ("sub%.l #12,%1", operands
);
2293 output_asm_insn ("subq%.l #8,%1", operands
);
2294 if (GET_MODE (operands
[1]) == XFmode
)
2295 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2296 else if (GET_MODE (operands
[1]) == DFmode
)
2297 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2299 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2303 /* If an operand is an unoffsettable memory ref, find a register
2304 we can increment temporarily to make it refer to the second word. */
2306 if (optype0
== MEMOP
)
2307 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2309 if (optype1
== MEMOP
)
2310 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2312 /* Ok, we can do one word at a time.
2313 Normally we do the low-numbered word first,
2314 but if either operand is autodecrementing then we
2315 do the high-numbered word first.
2317 In either case, set up in LATEHALF the operands to use
2318 for the high-numbered word and in some cases alter the
2319 operands in OPERANDS to be suitable for the low-numbered word. */
2323 if (optype0
== REGOP
)
2325 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2326 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2328 else if (optype0
== OFFSOP
)
2330 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2331 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2335 middlehalf
[0] = operands
[0];
2336 latehalf
[0] = operands
[0];
2339 if (optype1
== REGOP
)
2341 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2342 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2344 else if (optype1
== OFFSOP
)
2346 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2347 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2349 else if (optype1
== CNSTOP
)
2351 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2356 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2357 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2358 operands
[1] = GEN_INT (l
[0]);
2359 middlehalf
[1] = GEN_INT (l
[1]);
2360 latehalf
[1] = GEN_INT (l
[2]);
2364 /* No non-CONST_DOUBLE constant should ever appear
2366 gcc_assert (!CONSTANT_P (operands
[1]));
2371 middlehalf
[1] = operands
[1];
2372 latehalf
[1] = operands
[1];
2376 /* size is not 12: */
2378 if (optype0
== REGOP
)
2379 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2380 else if (optype0
== OFFSOP
)
2381 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2383 latehalf
[0] = operands
[0];
2385 if (optype1
== REGOP
)
2386 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2387 else if (optype1
== OFFSOP
)
2388 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2389 else if (optype1
== CNSTOP
)
2390 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2392 latehalf
[1] = operands
[1];
2395 /* If insn is effectively movd N(sp),-(sp) then we will do the
2396 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2397 for the low word as well, to compensate for the first decrement of sp. */
2398 if (optype0
== PUSHOP
2399 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2400 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2401 operands
[1] = middlehalf
[1] = latehalf
[1];
2403 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2404 if the upper part of reg N does not appear in the MEM, arrange to
2405 emit the move late-half first. Otherwise, compute the MEM address
2406 into the upper part of N and use that as a pointer to the memory
2408 if (optype0
== REGOP
2409 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2411 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2413 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2414 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2416 /* If both halves of dest are used in the src memory address,
2417 compute the address into latehalf of dest.
2418 Note that this can't happen if the dest is two data regs. */
2420 xops
[0] = latehalf
[0];
2421 xops
[1] = XEXP (operands
[1], 0);
2422 output_asm_insn ("lea %a1,%0", xops
);
2423 if (GET_MODE (operands
[1]) == XFmode
)
2425 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2426 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2427 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2431 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2432 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2436 && reg_overlap_mentioned_p (middlehalf
[0],
2437 XEXP (operands
[1], 0)))
2439 /* Check for two regs used by both source and dest.
2440 Note that this can't happen if the dest is all data regs.
2441 It can happen if the dest is d6, d7, a0.
2442 But in that case, latehalf is an addr reg, so
2443 the code at compadr does ok. */
2445 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2446 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2449 /* JRV says this can't happen: */
2450 gcc_assert (!addreg0
&& !addreg1
);
2452 /* Only the middle reg conflicts; simply put it last. */
2453 output_asm_insn (singlemove_string (operands
), operands
);
2454 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2455 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2458 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2459 /* If the low half of dest is mentioned in the source memory
2460 address, the arrange to emit the move late half first. */
2461 dest_overlapped_low
= 1;
2464 /* If one or both operands autodecrementing,
2465 do the two words, high-numbered first. */
2467 /* Likewise, the first move would clobber the source of the second one,
2468 do them in the other order. This happens only for registers;
2469 such overlap can't happen in memory unless the user explicitly
2470 sets it up, and that is an undefined circumstance. */
2472 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2473 || (optype0
== REGOP
&& optype1
== REGOP
2474 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2475 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2476 || dest_overlapped_low
)
2478 /* Make any unoffsettable addresses point at high-numbered word. */
2482 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2484 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2489 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2491 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2495 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2497 /* Undo the adds we just did. */
2499 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2501 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2505 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2507 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2509 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2512 /* Do low-numbered word. */
2513 return singlemove_string (operands
);
2516 /* Normal case: do the two words, low-numbered first. */
2518 output_asm_insn (singlemove_string (operands
), operands
);
2520 /* Do the middle one of the three words for long double */
2524 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2526 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2528 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2531 /* Make any unoffsettable addresses point at high-numbered word. */
2533 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2535 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2538 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2540 /* Undo the adds we just did. */
2544 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2546 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2551 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2553 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2560 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2561 new rtx with the correct mode. */
2564 force_mode (enum machine_mode mode
, rtx orig
)
2566 if (mode
== GET_MODE (orig
))
2569 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2572 return gen_rtx_REG (mode
, REGNO (orig
));
2576 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2578 return reg_renumber
&& FP_REG_P (op
);
2581 /* Emit insns to move operands[1] into operands[0].
2583 Return 1 if we have written out everything that needs to be done to
2584 do the move. Otherwise, return 0 and the caller will emit the move
2587 Note SCRATCH_REG may not be in the proper mode depending on how it
2588 will be used. This routine is responsible for creating a new copy
2589 of SCRATCH_REG in the proper mode. */
2592 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2594 register rtx operand0
= operands
[0];
2595 register rtx operand1
= operands
[1];
2599 && reload_in_progress
&& GET_CODE (operand0
) == REG
2600 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2601 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2602 else if (scratch_reg
2603 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2604 && GET_CODE (SUBREG_REG (operand0
)) == REG
2605 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2607 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2608 the code which tracks sets/uses for delete_output_reload. */
2609 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2610 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2611 SUBREG_BYTE (operand0
));
2612 operand0
= alter_subreg (&temp
);
2616 && reload_in_progress
&& GET_CODE (operand1
) == REG
2617 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2618 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2619 else if (scratch_reg
2620 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2621 && GET_CODE (SUBREG_REG (operand1
)) == REG
2622 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2624 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2625 the code which tracks sets/uses for delete_output_reload. */
2626 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2627 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2628 SUBREG_BYTE (operand1
));
2629 operand1
= alter_subreg (&temp
);
2632 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2633 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2634 != XEXP (operand0
, 0)))
2635 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2636 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2637 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2638 != XEXP (operand1
, 0)))
2639 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2641 /* Handle secondary reloads for loads/stores of FP registers where
2642 the address is symbolic by using the scratch register */
2643 if (fp_reg_operand (operand0
, mode
)
2644 && ((GET_CODE (operand1
) == MEM
2645 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2646 || ((GET_CODE (operand1
) == SUBREG
2647 && GET_CODE (XEXP (operand1
, 0)) == MEM
2648 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2651 if (GET_CODE (operand1
) == SUBREG
)
2652 operand1
= XEXP (operand1
, 0);
2654 /* SCRATCH_REG will hold an address. We want
2655 it in SImode regardless of what mode it was originally given
2657 scratch_reg
= force_mode (SImode
, scratch_reg
);
2659 /* D might not fit in 14 bits either; for such cases load D into
2661 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2663 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2664 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2666 XEXP (XEXP (operand1
, 0), 0),
2670 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2671 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2672 gen_rtx_MEM (mode
, scratch_reg
)));
2675 else if (fp_reg_operand (operand1
, mode
)
2676 && ((GET_CODE (operand0
) == MEM
2677 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2678 || ((GET_CODE (operand0
) == SUBREG
)
2679 && GET_CODE (XEXP (operand0
, 0)) == MEM
2680 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2683 if (GET_CODE (operand0
) == SUBREG
)
2684 operand0
= XEXP (operand0
, 0);
2686 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2687 it in SIMODE regardless of what mode it was originally given
2689 scratch_reg
= force_mode (SImode
, scratch_reg
);
2691 /* D might not fit in 14 bits either; for such cases load D into
2693 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2695 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2696 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2699 XEXP (XEXP (operand0
, 0),
2704 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2705 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2709 /* Handle secondary reloads for loads of FP registers from constant
2710 expressions by forcing the constant into memory.
2712 use scratch_reg to hold the address of the memory location.
2714 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2715 NO_REGS when presented with a const_int and an register class
2716 containing only FP registers. Doing so unfortunately creates
2717 more problems than it solves. Fix this for 2.5. */
2718 else if (fp_reg_operand (operand0
, mode
)
2719 && CONSTANT_P (operand1
)
2724 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2725 it in SIMODE regardless of what mode it was originally given
2727 scratch_reg
= force_mode (SImode
, scratch_reg
);
2729 /* Force the constant into memory and put the address of the
2730 memory location into scratch_reg. */
2731 xoperands
[0] = scratch_reg
;
2732 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2733 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2735 /* Now load the destination register. */
2736 emit_insn (gen_rtx_SET (mode
, operand0
,
2737 gen_rtx_MEM (mode
, scratch_reg
)));
2741 /* Now have insn-emit do whatever it normally does. */
2745 /* Split one or more DImode RTL references into pairs of SImode
2746 references. The RTL can be REG, offsettable MEM, integer constant, or
2747 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2748 split and "num" is its length. lo_half and hi_half are output arrays
2749 that parallel "operands". */
2752 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2756 rtx op
= operands
[num
];
2758 /* simplify_subreg refuses to split volatile memory addresses,
2759 but we still have to handle it. */
2760 if (GET_CODE (op
) == MEM
)
2762 lo_half
[num
] = adjust_address (op
, SImode
, 4);
2763 hi_half
[num
] = adjust_address (op
, SImode
, 0);
2767 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2768 GET_MODE (op
) == VOIDmode
2769 ? DImode
: GET_MODE (op
), 4);
2770 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2771 GET_MODE (op
) == VOIDmode
2772 ? DImode
: GET_MODE (op
), 0);
2777 /* Return a REG that occurs in ADDR with coefficient 1.
2778 ADDR can be effectively incremented by incrementing REG. */
2781 find_addr_reg (rtx addr
)
2783 while (GET_CODE (addr
) == PLUS
)
2785 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2786 addr
= XEXP (addr
, 0);
2787 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2788 addr
= XEXP (addr
, 1);
2789 else if (CONSTANT_P (XEXP (addr
, 0)))
2790 addr
= XEXP (addr
, 1);
2791 else if (CONSTANT_P (XEXP (addr
, 1)))
2792 addr
= XEXP (addr
, 0);
2796 gcc_assert (GET_CODE (addr
) == REG
);
2800 /* Output assembler code to perform a 32-bit 3-operand add. */
2803 output_addsi3 (rtx
*operands
)
2805 if (! operands_match_p (operands
[0], operands
[1]))
2807 if (!ADDRESS_REG_P (operands
[1]))
2809 rtx tmp
= operands
[1];
2811 operands
[1] = operands
[2];
2815 /* These insns can result from reloads to access
2816 stack slots over 64k from the frame pointer. */
2817 if (GET_CODE (operands
[2]) == CONST_INT
2818 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2819 return "move%.l %2,%0\n\tadd%.l %1,%0";
2820 if (GET_CODE (operands
[2]) == REG
)
2821 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2822 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2824 if (GET_CODE (operands
[2]) == CONST_INT
)
2826 if (INTVAL (operands
[2]) > 0
2827 && INTVAL (operands
[2]) <= 8)
2828 return "addq%.l %2,%0";
2829 if (INTVAL (operands
[2]) < 0
2830 && INTVAL (operands
[2]) >= -8)
2832 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2833 return "subq%.l %2,%0";
2835 /* On the CPU32 it is faster to use two addql instructions to
2836 add a small integer (8 < N <= 16) to a register.
2837 Likewise for subql. */
2838 if (TUNE_CPU32
&& REG_P (operands
[0]))
2840 if (INTVAL (operands
[2]) > 8
2841 && INTVAL (operands
[2]) <= 16)
2843 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2844 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2846 if (INTVAL (operands
[2]) < -8
2847 && INTVAL (operands
[2]) >= -16)
2849 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2850 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2853 if (ADDRESS_REG_P (operands
[0])
2854 && INTVAL (operands
[2]) >= -0x8000
2855 && INTVAL (operands
[2]) < 0x8000)
2858 return "add%.w %2,%0";
2860 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2863 return "add%.l %2,%0";
2866 /* Store in cc_status the expressions that the condition codes will
2867 describe after execution of an instruction whose pattern is EXP.
2868 Do not alter them if the instruction would not alter the cc's. */
2870 /* On the 68000, all the insns to store in an address register fail to
2871 set the cc's. However, in some cases these instructions can make it
2872 possibly invalid to use the saved cc's. In those cases we clear out
2873 some or all of the saved cc's so they won't be used. */
2876 notice_update_cc (rtx exp
, rtx insn
)
2878 if (GET_CODE (exp
) == SET
)
2880 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2882 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2884 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2885 cc_status
.value1
= 0;
2886 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2887 cc_status
.value2
= 0;
2889 /* fmoves to memory or data registers do not set the condition
2890 codes. Normal moves _do_ set the condition codes, but not in
2891 a way that is appropriate for comparison with 0, because -0.0
2892 would be treated as a negative nonzero number. Note that it
2893 isn't appropriate to conditionalize this restriction on
2894 HONOR_SIGNED_ZEROS because that macro merely indicates whether
2895 we care about the difference between -0.0 and +0.0. */
2896 else if (!FP_REG_P (SET_DEST (exp
))
2897 && SET_DEST (exp
) != cc0_rtx
2898 && (FP_REG_P (SET_SRC (exp
))
2899 || GET_CODE (SET_SRC (exp
)) == FIX
2900 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
2902 /* A pair of move insns doesn't produce a useful overall cc. */
2903 else if (!FP_REG_P (SET_DEST (exp
))
2904 && !FP_REG_P (SET_SRC (exp
))
2905 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2906 && (GET_CODE (SET_SRC (exp
)) == REG
2907 || GET_CODE (SET_SRC (exp
)) == MEM
2908 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2910 else if (SET_DEST (exp
) != pc_rtx
)
2912 cc_status
.flags
= 0;
2913 cc_status
.value1
= SET_DEST (exp
);
2914 cc_status
.value2
= SET_SRC (exp
);
2917 else if (GET_CODE (exp
) == PARALLEL
2918 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2920 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2921 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2923 if (ADDRESS_REG_P (dest
))
2925 else if (dest
!= pc_rtx
)
2927 cc_status
.flags
= 0;
2928 cc_status
.value1
= dest
;
2929 cc_status
.value2
= src
;
2934 if (cc_status
.value2
!= 0
2935 && ADDRESS_REG_P (cc_status
.value2
)
2936 && GET_MODE (cc_status
.value2
) == QImode
)
2938 if (cc_status
.value2
!= 0)
2939 switch (GET_CODE (cc_status
.value2
))
2941 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2942 case ROTATE
: case ROTATERT
:
2943 /* These instructions always clear the overflow bit, and set
2944 the carry to the bit shifted out. */
2945 /* ??? We don't currently have a way to signal carry not valid,
2946 nor do we check for it in the branch insns. */
2950 case PLUS
: case MINUS
: case MULT
:
2951 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2952 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2953 cc_status
.flags
|= CC_NO_OVERFLOW
;
2956 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2957 ends with a move insn moving r2 in r2's mode.
2958 Thus, the cc's are set for r2.
2959 This can set N bit spuriously. */
2960 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2965 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2967 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2968 cc_status
.value2
= 0;
2969 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2970 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2971 cc_status
.flags
= CC_IN_68881
;
2975 output_move_const_double (rtx
*operands
)
2977 int code
= standard_68881_constant_p (operands
[1]);
2981 static char buf
[40];
2983 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2986 return "fmove%.d %1,%0";
2990 output_move_const_single (rtx
*operands
)
2992 int code
= standard_68881_constant_p (operands
[1]);
2996 static char buf
[40];
2998 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3001 return "fmove%.s %f1,%0";
3004 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3005 from the "fmovecr" instruction.
3006 The value, anded with 0xff, gives the code to use in fmovecr
3007 to get the desired constant. */
3009 /* This code has been fixed for cross-compilation. */
3011 static int inited_68881_table
= 0;
3013 static const char *const strings_68881
[7] = {
3023 static const int codes_68881
[7] = {
3033 REAL_VALUE_TYPE values_68881
[7];
3035 /* Set up values_68881 array by converting the decimal values
3036 strings_68881 to binary. */
3039 init_68881_table (void)
3043 enum machine_mode mode
;
3046 for (i
= 0; i
< 7; i
++)
3050 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3051 values_68881
[i
] = r
;
3053 inited_68881_table
= 1;
3057 standard_68881_constant_p (rtx x
)
3062 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3063 used at all on those chips. */
3067 if (! inited_68881_table
)
3068 init_68881_table ();
3070 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3072 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3074 for (i
= 0; i
< 6; i
++)
3076 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3077 return (codes_68881
[i
]);
3080 if (GET_MODE (x
) == SFmode
)
3083 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3084 return (codes_68881
[6]);
3086 /* larger powers of ten in the constants ram are not used
3087 because they are not equal to a `double' C constant. */
3091 /* If X is a floating-point constant, return the logarithm of X base 2,
3092 or 0 if X is not a power of 2. */
3095 floating_exact_log2 (rtx x
)
3097 REAL_VALUE_TYPE r
, r1
;
3100 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3102 if (REAL_VALUES_LESS (r
, dconst1
))
3105 exp
= real_exponent (&r
);
3106 real_2expN (&r1
, exp
);
3107 if (REAL_VALUES_EQUAL (r1
, r
))
3113 /* A C compound statement to output to stdio stream STREAM the
3114 assembler syntax for an instruction operand X. X is an RTL
3117 CODE is a value that can be used to specify one of several ways
3118 of printing the operand. It is used when identical operands
3119 must be printed differently depending on the context. CODE
3120 comes from the `%' specification that was used to request
3121 printing of the operand. If the specification was just `%DIGIT'
3122 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3123 is the ASCII code for LTR.
3125 If X is a register, this macro should print the register's name.
3126 The names can be found in an array `reg_names' whose type is
3127 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3129 When the machine description has a specification `%PUNCT' (a `%'
3130 followed by a punctuation character), this macro is called with
3131 a null pointer for X and the punctuation character for CODE.
3133 The m68k specific codes are:
3135 '.' for dot needed in Motorola-style opcode names.
3136 '-' for an operand pushing on the stack:
3137 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3138 '+' for an operand pushing on the stack:
3139 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3140 '@' for a reference to the top word on the stack:
3141 sp@, (sp) or (%sp) depending on the style of syntax.
3142 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3143 but & in SGS syntax).
3144 '!' for the cc register (used in an `and to cc' insn).
3145 '$' for the letter `s' in an op code, but only on the 68040.
3146 '&' for the letter `d' in an op code, but only on the 68040.
3147 '/' for register prefix needed by longlong.h.
3149 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3150 'd' to force memory addressing to be absolute, not relative.
3151 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3152 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3153 or print pair of registers as rx:ry.
3154 'p' print an address with @PLTPC attached, but only if the operand
3155 is not locally-bound. */
3158 print_operand (FILE *file
, rtx op
, int letter
)
3163 fprintf (file
, ".");
3165 else if (letter
== '#')
3166 asm_fprintf (file
, "%I");
3167 else if (letter
== '-')
3168 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3169 else if (letter
== '+')
3170 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3171 else if (letter
== '@')
3172 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3173 else if (letter
== '!')
3174 asm_fprintf (file
, "%Rfpcr");
3175 else if (letter
== '$')
3178 fprintf (file
, "s");
3180 else if (letter
== '&')
3183 fprintf (file
, "d");
3185 else if (letter
== '/')
3186 asm_fprintf (file
, "%R");
3187 else if (letter
== 'p')
3189 output_addr_const (file
, op
);
3190 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3191 fprintf (file
, "@PLTPC");
3193 else if (GET_CODE (op
) == REG
)
3196 /* Print out the second register name of a register pair.
3197 I.e., R (6) => 7. */
3198 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3200 fputs (M68K_REGNAME(REGNO (op
)), file
);
3202 else if (GET_CODE (op
) == MEM
)
3204 output_address (XEXP (op
, 0));
3205 if (letter
== 'd' && ! TARGET_68020
3206 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3207 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3208 && INTVAL (XEXP (op
, 0)) < 0x8000
3209 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3210 fprintf (file
, MOTOROLA
? ".l" : ":l");
3212 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3215 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3216 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3218 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3221 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3222 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3224 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3227 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3228 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3232 /* Use `print_operand_address' instead of `output_addr_const'
3233 to ensure that we print relevant PIC stuff. */
3234 asm_fprintf (file
, "%I");
3236 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3237 print_operand_address (file
, op
);
3239 output_addr_const (file
, op
);
3244 /* A C compound statement to output to stdio stream STREAM the
3245 assembler syntax for an instruction operand that is a memory
3246 reference whose address is ADDR. ADDR is an RTL expression.
3248 Note that this contains a kludge that knows that the only reason
3249 we have an address (plus (label_ref...) (reg...)) when not generating
3250 PIC code is in the insn before a tablejump, and we know that m68k.md
3251 generates a label LInnn: on such an insn.
3253 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3254 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3256 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3257 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3258 we want. This difference can be accommodated by using an assembler
3259 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3260 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3261 macro. See m68k/sgs.h for an example; for versions without the bug.
3262 Some assemblers refuse all the above solutions. The workaround is to
3263 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3266 They also do not like things like "pea 1.w", so we simple leave off
3267 the .w on small constants.
3269 This routine is responsible for distinguishing between -fpic and -fPIC
3270 style relocations in an address. When generating -fpic code the
3271 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3272 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3275 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3276 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3277 #else /* !MOTOROLA */
3278 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3279 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3280 #endif /* !MOTOROLA */
3283 print_operand_address (FILE *file
, rtx addr
)
3285 register rtx reg1
, reg2
, breg
, ireg
;
3288 switch (GET_CODE (addr
))
3291 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3294 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3295 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3298 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3299 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3302 reg1
= reg2
= ireg
= breg
= offset
= 0;
3303 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3305 offset
= XEXP (addr
, 0);
3306 addr
= XEXP (addr
, 1);
3308 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3310 offset
= XEXP (addr
, 1);
3311 addr
= XEXP (addr
, 0);
3313 if (GET_CODE (addr
) != PLUS
)
3317 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3319 reg1
= XEXP (addr
, 0);
3320 addr
= XEXP (addr
, 1);
3322 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3324 reg1
= XEXP (addr
, 1);
3325 addr
= XEXP (addr
, 0);
3327 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3329 reg1
= XEXP (addr
, 0);
3330 addr
= XEXP (addr
, 1);
3332 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3334 reg1
= XEXP (addr
, 1);
3335 addr
= XEXP (addr
, 0);
3337 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3339 reg1
= XEXP (addr
, 0);
3340 addr
= XEXP (addr
, 1);
3342 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3344 reg1
= XEXP (addr
, 1);
3345 addr
= XEXP (addr
, 0);
3347 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3348 || GET_CODE (addr
) == SIGN_EXTEND
)
3356 #if 0 /* for OLD_INDEXING */
3357 else if (GET_CODE (addr
) == PLUS
)
3359 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3361 reg2
= XEXP (addr
, 0);
3362 addr
= XEXP (addr
, 1);
3364 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3366 reg2
= XEXP (addr
, 1);
3367 addr
= XEXP (addr
, 0);
3376 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3377 || GET_CODE (reg1
) == MULT
))
3378 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3383 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3388 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3389 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3392 if (GET_CODE (ireg
) == MULT
)
3394 scale
= INTVAL (XEXP (ireg
, 1));
3395 ireg
= XEXP (ireg
, 0);
3397 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3399 ASM_OUTPUT_CASE_FETCH (file
,
3400 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3401 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3402 fprintf (file
, "w");
3406 ASM_OUTPUT_CASE_FETCH (file
,
3407 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3408 M68K_REGNAME (REGNO (ireg
)));
3409 fprintf (file
, "l");
3412 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3416 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3417 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3419 ASM_OUTPUT_CASE_FETCH (file
,
3420 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3421 M68K_REGNAME (REGNO (breg
)));
3422 fprintf (file
, "l)");
3425 if (ireg
!= 0 || breg
!= 0)
3430 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3436 output_addr_const (file
, addr
);
3437 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3439 fprintf (file
, "@GOT");
3441 fprintf (file
, ".w");
3444 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3448 else /* !MOTOROLA */
3450 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3453 output_addr_const (file
, addr
);
3454 if (breg
== pic_offset_table_rtx
)
3458 fprintf (file
, ":w");
3461 fprintf (file
, ":l");
3470 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3472 scale
= INTVAL (XEXP (ireg
, 1));
3473 ireg
= XEXP (ireg
, 0);
3475 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3476 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3477 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3479 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3480 M68K_REGNAME (REGNO (ireg
)));
3482 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3486 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3487 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3489 ASM_OUTPUT_CASE_FETCH (file
,
3490 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3491 M68K_REGNAME (REGNO (reg1
)));
3492 fprintf (file
, "l)");
3495 /* FALL-THROUGH (is this really what we want?) */
3497 if (GET_CODE (addr
) == CONST_INT
3498 && INTVAL (addr
) < 0x8000
3499 && INTVAL (addr
) >= -0x8000)
3501 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3503 else if (GET_CODE (addr
) == CONST_INT
)
3505 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3507 else if (TARGET_PCREL
)
3510 output_addr_const (file
, addr
);
3512 asm_fprintf (file
, ":w,%Rpc)");
3514 asm_fprintf (file
, ":l,%Rpc)");
3518 /* Special case for SYMBOL_REF if the symbol name ends in
3519 `.<letter>', this can be mistaken as a size suffix. Put
3520 the name in parentheses. */
3521 if (GET_CODE (addr
) == SYMBOL_REF
3522 && strlen (XSTR (addr
, 0)) > 2
3523 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3526 output_addr_const (file
, addr
);
3530 output_addr_const (file
, addr
);
3536 /* Check for cases where a clr insns can be omitted from code using
3537 strict_low_part sets. For example, the second clrl here is not needed:
3538 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3540 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3541 insn we are checking for redundancy. TARGET is the register set by the
3545 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3550 p
= prev_nonnote_insn (first_insn
);
3554 /* If it isn't an insn, then give up. */
3555 if (GET_CODE (p
) != INSN
)
3558 if (reg_set_p (target
, p
))
3560 rtx set
= single_set (p
);
3563 /* If it isn't an easy to recognize insn, then give up. */
3567 dest
= SET_DEST (set
);
3569 /* If this sets the entire target register to zero, then our
3570 first_insn is redundant. */
3571 if (rtx_equal_p (dest
, target
)
3572 && SET_SRC (set
) == const0_rtx
)
3574 else if (GET_CODE (dest
) == STRICT_LOW_PART
3575 && GET_CODE (XEXP (dest
, 0)) == REG
3576 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3577 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3578 <= GET_MODE_SIZE (mode
)))
3579 /* This is a strict low part set which modifies less than
3580 we are using, so it is safe. */
3586 p
= prev_nonnote_insn (p
);
3592 /* Operand predicates for implementing asymmetric pc-relative addressing
3593 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3594 when used as a source operand, but not as a destination operand.
3596 We model this by restricting the meaning of the basic predicates
3597 (general_operand, memory_operand, etc) to forbid the use of this
3598 addressing mode, and then define the following predicates that permit
3599 this addressing mode. These predicates can then be used for the
3600 source operands of the appropriate instructions.
3602 n.b. While it is theoretically possible to change all machine patterns
3603 to use this addressing more where permitted by the architecture,
3604 it has only been implemented for "common" cases: SImode, HImode, and
3605 QImode operands, and only for the principle operations that would
3606 require this addressing mode: data movement and simple integer operations.
3608 In parallel with these new predicates, two new constraint letters
3609 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3610 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3611 In the pcrel case 's' is only valid in combination with 'a' registers.
3612 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3613 of how these constraints are used.
3615 The use of these predicates is strictly optional, though patterns that
3616 don't will cause an extra reload register to be allocated where one
3619 lea (abc:w,%pc),%a0 ; need to reload address
3620 moveq &1,%d1 ; since write to pc-relative space
3621 movel %d1,%a0@ ; is not allowed
3623 lea (abc:w,%pc),%a1 ; no need to reload address here
3624 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3626 For more info, consult tiemann@cygnus.com.
3629 All of the ugliness with predicates and constraints is due to the
3630 simple fact that the m68k does not allow a pc-relative addressing
3631 mode as a destination. gcc does not distinguish between source and
3632 destination addresses. Hence, if we claim that pc-relative address
3633 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3634 end up with invalid code. To get around this problem, we left
3635 pc-relative modes as invalid addresses, and then added special
3636 predicates and constraints to accept them.
3638 A cleaner way to handle this is to modify gcc to distinguish
3639 between source and destination addresses. We can then say that
3640 pc-relative is a valid source address but not a valid destination
3641 address, and hopefully avoid a lot of the predicate and constraint
3642 hackery. Unfortunately, this would be a pretty big change. It would
3643 be a useful change for a number of ports, but there aren't any current
3644 plans to undertake this.
3646 ***************************************************************************/
3650 output_andsi3 (rtx
*operands
)
3653 if (GET_CODE (operands
[2]) == CONST_INT
3654 && (INTVAL (operands
[2]) | 0xffff) == -1
3655 && (DATA_REG_P (operands
[0])
3656 || offsettable_memref_p (operands
[0]))
3657 && !TARGET_COLDFIRE
)
3659 if (GET_CODE (operands
[0]) != REG
)
3660 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3661 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3662 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3664 if (operands
[2] == const0_rtx
)
3666 return "and%.w %2,%0";
3668 if (GET_CODE (operands
[2]) == CONST_INT
3669 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3670 && (DATA_REG_P (operands
[0])
3671 || offsettable_memref_p (operands
[0])))
3673 if (DATA_REG_P (operands
[0]))
3674 operands
[1] = GEN_INT (logval
);
3677 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3678 operands
[1] = GEN_INT (logval
% 8);
3680 /* This does not set condition codes in a standard way. */
3682 return "bclr %1,%0";
3684 return "and%.l %2,%0";
3688 output_iorsi3 (rtx
*operands
)
3690 register int logval
;
3691 if (GET_CODE (operands
[2]) == CONST_INT
3692 && INTVAL (operands
[2]) >> 16 == 0
3693 && (DATA_REG_P (operands
[0])
3694 || offsettable_memref_p (operands
[0]))
3695 && !TARGET_COLDFIRE
)
3697 if (GET_CODE (operands
[0]) != REG
)
3698 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3699 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3701 if (INTVAL (operands
[2]) == 0xffff)
3702 return "mov%.w %2,%0";
3703 return "or%.w %2,%0";
3705 if (GET_CODE (operands
[2]) == CONST_INT
3706 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3707 && (DATA_REG_P (operands
[0])
3708 || offsettable_memref_p (operands
[0])))
3710 if (DATA_REG_P (operands
[0]))
3711 operands
[1] = GEN_INT (logval
);
3714 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3715 operands
[1] = GEN_INT (logval
% 8);
3718 return "bset %1,%0";
3720 return "or%.l %2,%0";
3724 output_xorsi3 (rtx
*operands
)
3726 register int logval
;
3727 if (GET_CODE (operands
[2]) == CONST_INT
3728 && INTVAL (operands
[2]) >> 16 == 0
3729 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3730 && !TARGET_COLDFIRE
)
3732 if (! DATA_REG_P (operands
[0]))
3733 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3734 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3736 if (INTVAL (operands
[2]) == 0xffff)
3738 return "eor%.w %2,%0";
3740 if (GET_CODE (operands
[2]) == CONST_INT
3741 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3742 && (DATA_REG_P (operands
[0])
3743 || offsettable_memref_p (operands
[0])))
3745 if (DATA_REG_P (operands
[0]))
3746 operands
[1] = GEN_INT (logval
);
3749 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3750 operands
[1] = GEN_INT (logval
% 8);
3753 return "bchg %1,%0";
3755 return "eor%.l %2,%0";
3758 /* Return the instruction that should be used for a call to address X,
3759 which is known to be in operand 0. */
3764 if (symbolic_operand (x
, VOIDmode
))
3765 return m68k_symbolic_call
;
3770 #ifdef M68K_TARGET_COFF
3772 /* Output assembly to switch to section NAME with attribute FLAGS. */
3775 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3776 tree decl ATTRIBUTE_UNUSED
)
3780 if (flags
& SECTION_WRITE
)
3785 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3788 #endif /* M68K_TARGET_COFF */
3791 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3792 HOST_WIDE_INT delta
,
3793 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3799 if (delta
> 0 && delta
<= 8)
3800 asm_fprintf (file
, (MOTOROLA
3801 ? "\taddq.l %I%d,4(%Rsp)\n"
3802 : "\taddql %I%d,%Rsp@(4)\n"),
3804 else if (delta
< 0 && delta
>= -8)
3805 asm_fprintf (file
, (MOTOROLA
3806 ? "\tsubq.l %I%d,4(%Rsp)\n"
3807 : "\tsubql %I%d,%Rsp@(4)\n"),
3809 else if (TARGET_COLDFIRE
)
3811 /* ColdFire can't add/sub a constant to memory unless it is in
3812 the range of addq/subq. So load the value into %d0 and
3813 then add it to 4(%sp). */
3814 if (delta
>= -128 && delta
<= 127)
3815 asm_fprintf (file
, (MOTOROLA
3816 ? "\tmoveq.l %I%wd,%Rd0\n"
3817 : "\tmoveql %I%wd,%Rd0\n"),
3820 asm_fprintf (file
, (MOTOROLA
3821 ? "\tmove.l %I%wd,%Rd0\n"
3822 : "\tmovel %I%wd,%Rd0\n"),
3824 asm_fprintf (file
, (MOTOROLA
3825 ? "\tadd.l %Rd0,4(%Rsp)\n"
3826 : "\taddl %Rd0,%Rsp@(4)\n"));
3829 asm_fprintf (file
, (MOTOROLA
3830 ? "\tadd.l %I%wd,4(%Rsp)\n"
3831 : "\taddl %I%wd,%Rsp@(4)\n"),
3834 xops
[0] = DECL_RTL (function
);
3836 gcc_assert (MEM_P (xops
[0])
3837 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
3838 xops
[0] = XEXP (xops
[0], 0);
3840 fmt
= m68k_symbolic_jump
;
3841 if (m68k_symbolic_jump
== NULL
)
3842 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3844 output_asm_insn (fmt
, xops
);
3847 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3850 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3851 int incoming ATTRIBUTE_UNUSED
)
3853 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3856 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3858 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3859 unsigned int new_reg
)
3862 /* Interrupt functions can only use registers that have already been
3863 saved by the prologue, even if they would normally be
3866 if (m68k_interrupt_function_p (current_function_decl
)
3867 && !regs_ever_live
[new_reg
])
3873 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3874 On the 68000, the cpu registers can hold any mode except bytes in address
3875 registers, but the 68881 registers can hold only SFmode or DFmode. */
3877 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3879 if (DATA_REGNO_P (regno
))
3881 /* Data Registers, can hold aggregate if fits in. */
3882 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3885 else if (ADDRESS_REGNO_P (regno
))
3887 /* Address Registers, can't hold bytes, can hold aggregate if
3889 if (GET_MODE_SIZE (mode
) == 1)
3891 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3894 else if (FP_REGNO_P (regno
))
3896 /* FPU registers, hold float or complex float of long double or
3898 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3899 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3900 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3906 /* Return floating point values in a 68881 register. This makes 68881 code
3907 a little bit faster. It also makes -msoft-float code incompatible with
3908 hard-float code, so people have to be careful not to mix the two.
3909 For ColdFire it was decided the ABI incompatibility is undesirable.
3910 If there is need for a hard-float ABI it is probably worth doing it
3911 properly and also passing function arguments in FP registers. */
3913 m68k_libcall_value (enum machine_mode mode
)
3920 return gen_rtx_REG (mode
, 16);
3925 return gen_rtx_REG (mode
, 0);
3929 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3931 enum machine_mode mode
;
3933 mode
= TYPE_MODE (valtype
);
3939 return gen_rtx_REG (mode
, 16);
3945 /* If the function returns a pointer, push that into %a0. */
3946 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
3947 /* For compatibility with the large body of existing code which
3948 does not always properly declare external functions returning
3949 pointer types, the m68k/SVR4 convention is to copy the value
3950 returned for pointer functions from a0 to d0 in the function
3951 epilogue, so that callers that have neglected to properly
3952 declare the callee can still find the correct return value in
3954 return gen_rtx_PARALLEL
3957 gen_rtx_EXPR_LIST (VOIDmode
,
3958 gen_rtx_REG (mode
, A0_REG
),
3960 gen_rtx_EXPR_LIST (VOIDmode
,
3961 gen_rtx_REG (mode
, D0_REG
),
3963 else if (POINTER_TYPE_P (valtype
))
3964 return gen_rtx_REG (mode
, A0_REG
);
3966 return gen_rtx_REG (mode
, D0_REG
);