1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* Base flags for 68k ISAs. */
205 #define FL_FOR_isa_00 FL_ISA_68000
206 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
207 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
208 generated 68881 code for 68020 and 68030 targets unless explicitly told
210 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
211 | FL_BITFIELD | FL_68881)
212 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
213 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
215 /* Base flags for ColdFire ISAs. */
216 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
217 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
218 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
219 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
220 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
224 /* Traditional 68000 instruction sets. */
230 /* ColdFire instruction set variants. */
238 /* Information about one of the -march, -mcpu or -mtune arguments. */
239 struct m68k_target_selection
241 /* The argument being described. */
244 /* For -mcpu, this is the device selected by the option.
245 For -mtune and -march, it is a representative device
246 for the microarchitecture or ISA respectively. */
247 enum target_device device
;
249 /* The M68K_DEVICE fields associated with DEVICE. See the comment
250 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
252 enum uarch_type microarch
;
257 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
258 static const struct m68k_target_selection all_devices
[] =
260 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
261 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
262 #include "m68k-devices.def"
264 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
267 /* A list of all ISAs, mapping each one to a representative device.
268 Used for -march selection. */
269 static const struct m68k_target_selection all_isas
[] =
271 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
272 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
273 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
274 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
275 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
276 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
277 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
278 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
280 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
282 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
283 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
286 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
289 /* A list of all microarchitectures, mapping each one to a representative
290 device. Used for -mtune selection. */
291 static const struct m68k_target_selection all_microarchs
[] =
293 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
294 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
295 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
296 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
297 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
298 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
299 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
300 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
301 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
302 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
303 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
305 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
310 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
313 /* The entries associated with the -mcpu, -march and -mtune settings,
314 or null for options that have not been used. */
315 const struct m68k_target_selection
*m68k_cpu_entry
;
316 const struct m68k_target_selection
*m68k_arch_entry
;
317 const struct m68k_target_selection
*m68k_tune_entry
;
319 /* Which CPU we are generating code for. */
320 enum target_device m68k_cpu
;
322 /* Which microarchitecture to tune for. */
323 enum uarch_type m68k_tune
;
325 /* Which FPU to use. */
326 enum fpu_type m68k_fpu
;
328 /* The set of FL_* flags that apply to the target processor. */
329 unsigned int m68k_cpu_flags
;
331 /* See whether TABLE has an entry with name NAME. Return true and
332 store the entry in *ENTRY if so, otherwise return false and
333 leave *ENTRY alone. */
336 m68k_find_selection (const struct m68k_target_selection
**entry
,
337 const struct m68k_target_selection
*table
,
342 for (i
= 0; table
[i
].name
; i
++)
343 if (strcmp (table
[i
].name
, name
) == 0)
351 /* Implement TARGET_HANDLE_OPTION. */
354 m68k_handle_option (size_t code
, const char *arg
, int value
)
359 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
362 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
365 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
368 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
371 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
374 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
377 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
380 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
383 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
387 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
390 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
394 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
397 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
399 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
402 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
404 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
407 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
410 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
420 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
422 case OPT_mshared_library_id_
:
423 if (value
> MAX_LIBRARY_ID
)
424 error ("-mshared-library-id=%s is not between 0 and %d",
425 arg
, MAX_LIBRARY_ID
);
427 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
435 /* Sometimes certain combinations of command options do not make
436 sense on a particular target machine. You can define a macro
437 `OVERRIDE_OPTIONS' to take account of this. This macro, if
438 defined, is executed once just after all the command options have
441 Don't use this macro to turn on various extra optimizations for
442 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
445 override_options (void)
447 const struct m68k_target_selection
*entry
;
448 unsigned long target_mask
;
456 -march=ARCH should generate code that runs any processor
457 implementing architecture ARCH. -mcpu=CPU should override -march
458 and should generate code that runs on processor CPU, making free
459 use of any instructions that CPU understands. -mtune=UARCH applies
460 on top of -mcpu or -march and optimises the code for UARCH. It does
461 not change the target architecture. */
464 /* Complain if the -march setting is for a different microarchitecture,
465 or includes flags that the -mcpu setting doesn't. */
467 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
468 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
469 warning (0, "-mcpu=%s conflicts with -march=%s",
470 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
472 entry
= m68k_cpu_entry
;
475 entry
= m68k_arch_entry
;
478 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
480 m68k_cpu_flags
= entry
->flags
;
482 /* Use the architecture setting to derive default values for
485 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
486 target_mask
|= MASK_BITFIELD
;
487 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
488 target_mask
|= MASK_CF_HWDIV
;
489 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
490 target_mask
|= MASK_HARD_FLOAT
;
491 target_flags
|= target_mask
& ~target_flags_explicit
;
493 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
494 m68k_cpu
= entry
->device
;
496 m68k_tune
= m68k_tune_entry
->microarch
;
497 #ifdef M68K_DEFAULT_TUNE
498 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
499 m68k_tune
= M68K_DEFAULT_TUNE
;
502 m68k_tune
= entry
->microarch
;
504 /* Set the type of FPU. */
505 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
506 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
509 /* Sanity check to ensure that msep-data and mid-sahred-library are not
510 * both specified together. Doing so simply doesn't make sense.
512 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
513 error ("cannot specify both -msep-data and -mid-shared-library");
515 /* If we're generating code for a separate A5 relative data segment,
516 * we've got to enable -fPIC as well. This might be relaxable to
517 * -fpic but it hasn't been tested properly.
519 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
522 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
523 error if the target does not support them. */
524 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
525 error ("-mpcrel -fPIC is not currently supported on selected cpu");
527 /* ??? A historic way of turning on pic, or is this intended to
528 be an embedded thing that doesn't have the same name binding
529 significance that it does on hosted ELF systems? */
530 if (TARGET_PCREL
&& flag_pic
== 0)
533 /* Turn off function cse if we are doing PIC. We always want function call
534 to be done as `bsr foo@PLTPC', so it will force the assembler to create
535 the PLT entry for `foo'. Doing function cse will cause the address of
536 `foo' to be loaded into a register, which is exactly what we want to
537 avoid when we are doing PIC on svr4 m68k. */
539 flag_no_function_cse
= 1;
541 SUBTARGET_OVERRIDE_OPTIONS
;
544 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
545 given argument and NAME is the argument passed to -mcpu. Return NULL
546 if -mcpu was not passed. */
549 m68k_cpp_cpu_ident (const char *prefix
)
553 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
556 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
557 given argument and NAME is the name of the representative device for
558 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
561 m68k_cpp_cpu_family (const char *prefix
)
565 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
568 /* Return nonzero if FUNC is an interrupt function as specified by the
569 "interrupt_handler" attribute. */
571 m68k_interrupt_function_p(tree func
)
575 if (TREE_CODE (func
) != FUNCTION_DECL
)
578 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
579 return (a
!= NULL_TREE
);
582 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
583 struct attribute_spec.handler. */
585 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
586 tree args ATTRIBUTE_UNUSED
,
587 int flags ATTRIBUTE_UNUSED
,
590 if (TREE_CODE (*node
) != FUNCTION_DECL
)
592 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
593 IDENTIFIER_POINTER (name
));
594 *no_add_attrs
= true;
601 m68k_compute_frame_layout (void)
604 unsigned int mask
, rmask
;
605 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
607 /* Only compute the frame once per function.
608 Don't cache information until reload has been completed. */
609 if (current_frame
.funcdef_no
== current_function_funcdef_no
613 current_frame
.size
= (get_frame_size () + 3) & -4;
615 mask
= rmask
= saved
= 0;
616 for (regno
= 0; regno
< 16; regno
++)
617 if (m68k_save_reg (regno
, interrupt_handler
))
620 rmask
|= 1 << (15 - regno
);
623 current_frame
.offset
= saved
* 4;
624 current_frame
.reg_no
= saved
;
625 current_frame
.reg_mask
= mask
;
626 current_frame
.reg_rev_mask
= rmask
;
628 current_frame
.foffset
= 0;
629 mask
= rmask
= saved
= 0;
630 if (TARGET_HARD_FLOAT
)
632 for (regno
= 16; regno
< 24; regno
++)
633 if (m68k_save_reg (regno
, interrupt_handler
))
635 mask
|= 1 << (regno
- 16);
636 rmask
|= 1 << (23 - regno
);
639 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
640 current_frame
.offset
+= current_frame
.foffset
;
642 current_frame
.fpu_no
= saved
;
643 current_frame
.fpu_mask
= mask
;
644 current_frame
.fpu_rev_mask
= rmask
;
646 /* Remember what function this frame refers to. */
647 current_frame
.funcdef_no
= current_function_funcdef_no
;
651 m68k_initial_elimination_offset (int from
, int to
)
654 /* The arg pointer points 8 bytes before the start of the arguments,
655 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
656 frame pointer in most frames. */
657 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
658 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
659 return argptr_offset
;
661 m68k_compute_frame_layout ();
663 gcc_assert (to
== STACK_POINTER_REGNUM
);
666 case ARG_POINTER_REGNUM
:
667 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
668 case FRAME_POINTER_REGNUM
:
669 return current_frame
.offset
+ current_frame
.size
;
675 /* Refer to the array `regs_ever_live' to determine which registers
676 to save; `regs_ever_live[I]' is nonzero if register number I
677 is ever used in the function. This function is responsible for
678 knowing which registers should not be saved even if used.
679 Return true if we need to save REGNO. */
682 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
684 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
686 if (current_function_uses_pic_offset_table
)
688 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
692 if (current_function_calls_eh_return
)
697 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
698 if (test
== INVALID_REGNUM
)
705 /* Fixed regs we never touch. */
706 if (fixed_regs
[regno
])
709 /* The frame pointer (if it is such) is handled specially. */
710 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
713 /* Interrupt handlers must also save call_used_regs
714 if they are live or when calling nested functions. */
715 if (interrupt_handler
)
717 if (regs_ever_live
[regno
])
720 if (!current_function_is_leaf
&& call_used_regs
[regno
])
724 /* Never need to save registers that aren't touched. */
725 if (!regs_ever_live
[regno
])
728 /* Otherwise save everything that isn't call-clobbered. */
729 return !call_used_regs
[regno
];
732 /* This function generates the assembly code for function entry.
733 STREAM is a stdio stream to output the code to.
734 SIZE is an int: how many units of temporary storage to allocate. */
737 m68k_output_function_prologue (FILE *stream
,
738 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
740 HOST_WIDE_INT fsize_with_regs
;
741 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
743 m68k_compute_frame_layout();
745 /* If the stack limit is a symbol, we can check it here,
746 before actually allocating the space. */
747 if (current_function_limit_stack
748 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
749 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
750 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
752 /* On ColdFire add register save into initial stack frame setup, if possible. */
753 fsize_with_regs
= current_frame
.size
;
756 if (current_frame
.reg_no
> 2)
757 fsize_with_regs
+= current_frame
.reg_no
* 4;
758 if (current_frame
.fpu_no
)
759 fsize_with_regs
+= current_frame
.fpu_no
* 8;
762 if (frame_pointer_needed
)
764 if (current_frame
.size
== 0 && TUNE_68040
)
765 /* on the 68040, pea + move is faster than link.w 0 */
766 fprintf (stream
, (MOTOROLA
767 ? "\tpea (%s)\n\tmove.l %s,%s\n"
768 : "\tpea %s@\n\tmovel %s,%s\n"),
769 M68K_REGNAME (FRAME_POINTER_REGNUM
),
770 M68K_REGNAME (STACK_POINTER_REGNUM
),
771 M68K_REGNAME (FRAME_POINTER_REGNUM
));
772 else if (fsize_with_regs
< 0x8000)
773 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
774 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
775 else if (TARGET_68020
)
776 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
777 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
779 /* Adding negative number is faster on the 68040. */
781 "\tlink" ASM_DOTW
" %s,%I0\n"
782 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
783 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
785 else if (fsize_with_regs
) /* !frame_pointer_needed */
787 if (fsize_with_regs
< 0x8000)
789 if (fsize_with_regs
<= 8)
791 if (!TARGET_COLDFIRE
)
792 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
795 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
798 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
799 /* On the CPU32 it is faster to use two subqw instructions to
800 subtract a small integer (8 < N <= 16) to a register. */
802 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
803 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
804 fsize_with_regs
- 8);
806 /* Adding negative number is faster on the 68040. */
807 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
810 asm_fprintf (stream
, (MOTOROLA
811 ? "\tlea (%wd,%Rsp),%Rsp\n"
812 : "\tlea %Rsp@(%wd),%Rsp\n"),
815 else /* fsize_with_regs >= 0x8000 */
816 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
818 } /* !frame_pointer_needed */
820 if (dwarf2out_do_frame ())
822 if (frame_pointer_needed
)
825 l
= (char *) dwarf2out_cfi_label ();
827 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
828 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
829 cfa_offset
+= current_frame
.size
;
833 cfa_offset
+= current_frame
.size
;
834 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
838 if (current_frame
.fpu_mask
)
842 asm_fprintf (stream
, (MOTOROLA
843 ? "\tfmovm %I0x%x,-(%Rsp)\n"
844 : "\tfmovem %I0x%x,%Rsp@-\n"),
845 current_frame
.fpu_mask
);
851 /* stack already has registers in it. Find the offset from
852 the bottom of stack to where the FP registers go */
853 if (current_frame
.reg_no
<= 2)
856 offset
= current_frame
.reg_no
* 4;
859 "\tfmovem %I0x%x,%d(%Rsp)\n",
860 current_frame
.fpu_rev_mask
,
864 "\tfmovem %I0x%x,(%Rsp)\n",
865 current_frame
.fpu_rev_mask
);
868 if (dwarf2out_do_frame ())
870 char *l
= (char *) dwarf2out_cfi_label ();
873 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
874 if (! frame_pointer_needed
)
875 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
876 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
877 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
878 dwarf2out_reg_save (l
, regno
, -cfa_offset
879 + n_regs
++ * TARGET_FP_REG_SIZE
);
883 /* If the stack limit is not a symbol, check it here.
884 This has the disadvantage that it may be too late... */
885 if (current_function_limit_stack
)
887 if (REG_P (stack_limit_rtx
))
888 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
889 M68K_REGNAME (REGNO (stack_limit_rtx
)));
890 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
891 warning (0, "stack limit expression is not supported");
894 if (current_frame
.reg_no
<= 2)
896 /* Store each separately in the same order moveml uses.
897 Using two movel instructions instead of a single moveml
898 is about 15% faster for the 68020 and 68030 at no expense
903 for (i
= 0; i
< 16; i
++)
904 if (current_frame
.reg_rev_mask
& (1 << i
))
906 asm_fprintf (stream
, (MOTOROLA
907 ? "\t%Omove.l %s,-(%Rsp)\n"
908 : "\tmovel %s,%Rsp@-\n"),
909 M68K_REGNAME (15 - i
));
910 if (dwarf2out_do_frame ())
912 char *l
= (char *) dwarf2out_cfi_label ();
915 if (! frame_pointer_needed
)
916 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
917 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
921 else if (current_frame
.reg_rev_mask
)
924 /* The ColdFire does not support the predecrement form of the
925 MOVEM instruction, so we must adjust the stack pointer and
926 then use the plain address register indirect mode.
927 The required register save space was combined earlier with
928 the fsize_with_regs amount. */
930 asm_fprintf (stream
, (MOTOROLA
931 ? "\tmovm.l %I0x%x,(%Rsp)\n"
932 : "\tmoveml %I0x%x,%Rsp@\n"),
933 current_frame
.reg_mask
);
935 asm_fprintf (stream
, (MOTOROLA
936 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
937 : "\tmoveml %I0x%x,%Rsp@-\n"),
938 current_frame
.reg_rev_mask
);
939 if (dwarf2out_do_frame ())
941 char *l
= (char *) dwarf2out_cfi_label ();
944 cfa_offset
+= current_frame
.reg_no
* 4;
945 if (! frame_pointer_needed
)
946 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
947 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
948 if (current_frame
.reg_mask
& (1 << regno
))
949 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
952 if (!TARGET_SEP_DATA
&& flag_pic
953 && (current_function_uses_pic_offset_table
954 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
956 if (TARGET_ID_SHARED_LIBRARY
)
958 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
959 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
960 m68k_library_id_string
,
961 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
967 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
968 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
971 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
972 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
973 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
974 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
975 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
981 /* Return true if this function's epilogue can be output as RTL. */
984 use_return_insn (void)
986 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
989 /* We can output the epilogue as RTL only if no registers need to be
991 m68k_compute_frame_layout ();
992 return current_frame
.reg_no
? false : true;
995 /* This function generates the assembly code for function exit,
996 on machines that need it.
998 The function epilogue should not depend on the current stack pointer!
999 It should use the frame pointer only, if there is a frame pointer.
1000 This is mandatory because of alloca; we also take advantage of it to
1001 omit stack adjustments before returning. */
1004 m68k_output_function_epilogue (FILE *stream
,
1005 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1007 HOST_WIDE_INT fsize
, fsize_with_regs
;
1009 bool restore_from_sp
= false;
1010 rtx insn
= get_last_insn ();
1012 m68k_compute_frame_layout ();
1014 /* If the last insn was a BARRIER, we don't have to write any code. */
1015 if (GET_CODE (insn
) == NOTE
)
1016 insn
= prev_nonnote_insn (insn
);
1017 if (insn
&& GET_CODE (insn
) == BARRIER
)
1019 /* Output just a no-op so that debuggers don't get confused
1020 about which function the pc is in at this address. */
1021 fprintf (stream
, "\tnop\n");
1025 #ifdef FUNCTION_EXTRA_EPILOGUE
1026 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
1029 fsize
= current_frame
.size
;
1031 /* FIXME: leaf_function_p below is too strong.
1032 What we really need to know there is if there could be pending
1033 stack adjustment needed at that point. */
1035 = (! frame_pointer_needed
1036 || (! current_function_calls_alloca
&& leaf_function_p ()));
1038 /* fsize_with_regs is the size we need to adjust the sp when
1039 popping the frame. */
1040 fsize_with_regs
= fsize
;
1042 /* Because the ColdFire doesn't support moveml with
1043 complex address modes, we must adjust the stack manually
1044 after restoring registers. When the frame pointer isn't used,
1045 we can merge movem adjustment into frame unlinking
1046 made immediately after it. */
1047 if (TARGET_COLDFIRE
&& restore_from_sp
)
1049 if (current_frame
.reg_no
> 2)
1050 fsize_with_regs
+= current_frame
.reg_no
* 4;
1051 if (current_frame
.fpu_no
)
1052 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1055 if (current_frame
.offset
+ fsize
>= 0x8000
1056 && ! restore_from_sp
1057 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1059 /* Because the ColdFire doesn't support moveml with
1060 complex address modes we make an extra correction here. */
1061 if (TARGET_COLDFIRE
)
1062 fsize
+= current_frame
.offset
;
1064 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1065 fsize
= 0, big
= true;
1067 if (current_frame
.reg_no
<= 2)
1069 /* Restore each separately in the same order moveml does.
1070 Using two movel instructions instead of a single moveml
1071 is about 15% faster for the 68020 and 68030 at no expense
1075 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1077 for (i
= 0; i
< 16; i
++)
1078 if (current_frame
.reg_mask
& (1 << i
))
1083 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1085 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1088 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1089 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1093 else if (restore_from_sp
)
1094 asm_fprintf (stream
, (MOTOROLA
1095 ? "\t%Omove.l (%Rsp)+,%s\n"
1096 : "\tmovel %Rsp@+,%s\n"),
1101 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1103 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1106 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1107 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1114 else if (current_frame
.reg_mask
)
1116 /* The ColdFire requires special handling due to its limited moveml
1118 if (TARGET_COLDFIRE
)
1122 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1123 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1124 asm_fprintf (stream
, (MOTOROLA
1125 ? "\tmovm.l (%Ra1),%I0x%x\n"
1126 : "\tmoveml %Ra1@,%I0x%x\n"),
1127 current_frame
.reg_mask
);
1129 else if (restore_from_sp
)
1130 asm_fprintf (stream
, (MOTOROLA
1131 ? "\tmovm.l (%Rsp),%I0x%x\n"
1132 : "\tmoveml %Rsp@,%I0x%x\n"),
1133 current_frame
.reg_mask
);
1137 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1138 current_frame
.offset
+ fsize
,
1139 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1140 current_frame
.reg_mask
);
1142 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1143 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1144 current_frame
.offset
+ fsize
,
1145 current_frame
.reg_mask
);
1148 else /* !TARGET_COLDFIRE */
1153 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1154 current_frame
.offset
+ fsize
,
1155 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1156 current_frame
.reg_mask
);
1158 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1159 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1160 current_frame
.offset
+ fsize
,
1161 current_frame
.reg_mask
);
1163 else if (restore_from_sp
)
1165 asm_fprintf (stream
, (MOTOROLA
1166 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1167 : "\tmoveml %Rsp@+,%I0x%x\n"),
1168 current_frame
.reg_mask
);
1173 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1174 current_frame
.offset
+ fsize
,
1175 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1176 current_frame
.reg_mask
);
1178 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1179 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1180 current_frame
.offset
+ fsize
,
1181 current_frame
.reg_mask
);
1185 if (current_frame
.fpu_rev_mask
)
1189 if (TARGET_COLDFIRE
)
1191 if (current_frame
.reg_no
)
1192 asm_fprintf (stream
, MOTOROLA
?
1193 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1194 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1195 current_frame
.reg_no
* 4,
1196 current_frame
.fpu_rev_mask
);
1198 asm_fprintf (stream
, MOTOROLA
?
1199 "\tfmovem.d (%Ra1),%I0x%x\n" :
1200 "\tfmovmd (%Ra1),%I0x%x\n",
1201 current_frame
.fpu_rev_mask
);
1204 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1205 current_frame
.foffset
+ fsize
,
1206 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1207 current_frame
.fpu_rev_mask
);
1209 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1210 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1211 current_frame
.foffset
+ fsize
,
1212 current_frame
.fpu_rev_mask
);
1214 else if (restore_from_sp
)
1216 if (TARGET_COLDFIRE
)
1220 /* Stack already has registers in it. Find the offset from
1221 the bottom of stack to where the FP registers go. */
1222 if (current_frame
.reg_no
<= 2)
1225 offset
= current_frame
.reg_no
* 4;
1227 asm_fprintf (stream
,
1228 "\tfmovem %Rsp@(%d), %I0x%x\n",
1229 offset
, current_frame
.fpu_rev_mask
);
1231 asm_fprintf (stream
,
1232 "\tfmovem %Rsp@, %I0x%x\n",
1233 current_frame
.fpu_rev_mask
);
1236 asm_fprintf (stream
, MOTOROLA
?
1237 "\tfmovm (%Rsp)+,%I0x%x\n" :
1238 "\tfmovem %Rsp@+,%I0x%x\n",
1239 current_frame
.fpu_rev_mask
);
1243 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1244 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1245 current_frame
.foffset
+ fsize
,
1246 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1247 current_frame
.fpu_rev_mask
);
1249 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1250 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1251 current_frame
.foffset
+ fsize
,
1252 current_frame
.fpu_rev_mask
);
1255 if (frame_pointer_needed
)
1256 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1257 else if (fsize_with_regs
)
1259 if (fsize_with_regs
<= 8)
1261 if (!TARGET_COLDFIRE
)
1262 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1265 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1268 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1270 /* On the CPU32 it is faster to use two addqw instructions to
1271 add a small integer (8 < N <= 16) to a register. */
1272 asm_fprintf (stream
,
1273 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1274 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1275 fsize_with_regs
- 8);
1277 else if (fsize_with_regs
< 0x8000)
1280 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1283 asm_fprintf (stream
, (MOTOROLA
1284 ? "\tlea (%wd,%Rsp),%Rsp\n"
1285 : "\tlea %Rsp@(%wd),%Rsp\n"),
1289 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1291 if (current_function_calls_eh_return
)
1292 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1293 if (m68k_interrupt_function_p (current_function_decl
))
1294 fprintf (stream
, "\trte\n");
1295 else if (current_function_pops_args
)
1296 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1298 fprintf (stream
, "\trts\n");
1301 /* Return true if X is a valid comparison operator for the dbcc
1304 Note it rejects floating point comparison operators.
1305 (In the future we could use Fdbcc).
1307 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1310 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1312 switch (GET_CODE (x
))
1314 case EQ
: case NE
: case GTU
: case LTU
:
1318 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1320 case GT
: case LT
: case GE
: case LE
:
1321 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1327 /* Return nonzero if flags are currently in the 68881 flag register. */
1329 flags_in_68881 (void)
1331 /* We could add support for these in the future */
1332 return cc_status
.flags
& CC_IN_68881
;
1335 /* Output a BSR instruction suitable for PIC code. */
1337 m68k_output_pic_call (rtx dest
)
1341 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1343 /* We output a BSR instruction if we're building for a target that
1344 supports long branches. Otherwise we generate one of two sequences:
1345 a shorter one that uses a GOT entry or a longer one that doesn't.
1346 We'll use the -Os command-line flag to decide which to generate.
1347 Both sequences take the same time to execute on the ColdFire. */
1348 else if (TARGET_PCREL
)
1350 else if (TARGET_68020
)
1351 #if defined(USE_GAS)
1352 out
= "bsr.l %0@PLTPC";
1354 out
= "bsr %0@PLTPC";
1356 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1357 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1359 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1361 output_asm_insn (out
, &dest
);
1364 /* Output a dbCC; jCC sequence. Note we do not handle the
1365 floating point version of this sequence (Fdbcc). We also
1366 do not handle alternative conditions when CC_NO_OVERFLOW is
1367 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1368 kick those out before we get here. */
1371 output_dbcc_and_branch (rtx
*operands
)
1373 switch (GET_CODE (operands
[3]))
1376 output_asm_insn (MOTOROLA
1377 ? "dbeq %0,%l1\n\tjbeq %l2"
1378 : "dbeq %0,%l1\n\tjeq %l2",
1383 output_asm_insn (MOTOROLA
1384 ? "dbne %0,%l1\n\tjbne %l2"
1385 : "dbne %0,%l1\n\tjne %l2",
1390 output_asm_insn (MOTOROLA
1391 ? "dbgt %0,%l1\n\tjbgt %l2"
1392 : "dbgt %0,%l1\n\tjgt %l2",
1397 output_asm_insn (MOTOROLA
1398 ? "dbhi %0,%l1\n\tjbhi %l2"
1399 : "dbhi %0,%l1\n\tjhi %l2",
1404 output_asm_insn (MOTOROLA
1405 ? "dblt %0,%l1\n\tjblt %l2"
1406 : "dblt %0,%l1\n\tjlt %l2",
1411 output_asm_insn (MOTOROLA
1412 ? "dbcs %0,%l1\n\tjbcs %l2"
1413 : "dbcs %0,%l1\n\tjcs %l2",
1418 output_asm_insn (MOTOROLA
1419 ? "dbge %0,%l1\n\tjbge %l2"
1420 : "dbge %0,%l1\n\tjge %l2",
1425 output_asm_insn (MOTOROLA
1426 ? "dbcc %0,%l1\n\tjbcc %l2"
1427 : "dbcc %0,%l1\n\tjcc %l2",
1432 output_asm_insn (MOTOROLA
1433 ? "dble %0,%l1\n\tjble %l2"
1434 : "dble %0,%l1\n\tjle %l2",
1439 output_asm_insn (MOTOROLA
1440 ? "dbls %0,%l1\n\tjbls %l2"
1441 : "dbls %0,%l1\n\tjls %l2",
1449 /* If the decrement is to be done in SImode, then we have
1450 to compensate for the fact that dbcc decrements in HImode. */
1451 switch (GET_MODE (operands
[0]))
1454 output_asm_insn (MOTOROLA
1455 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1456 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1469 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1472 enum rtx_code op_code
= GET_CODE (op
);
1474 /* This does not produce a useful cc. */
1477 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1478 below. Swap the operands and change the op if these requirements
1479 are not fulfilled. */
1480 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1484 operand1
= operand2
;
1486 op_code
= swap_condition (op_code
);
1488 loperands
[0] = operand1
;
1489 if (GET_CODE (operand1
) == REG
)
1490 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1492 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1493 if (operand2
!= const0_rtx
)
1495 loperands
[2] = operand2
;
1496 if (GET_CODE (operand2
) == REG
)
1497 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1499 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1501 loperands
[4] = gen_label_rtx ();
1502 if (operand2
!= const0_rtx
)
1504 output_asm_insn (MOTOROLA
1505 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1506 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1511 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1512 output_asm_insn ("tst%.l %0", loperands
);
1514 output_asm_insn ("cmp%.w #0,%0", loperands
);
1516 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1518 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1519 output_asm_insn ("tst%.l %1", loperands
);
1521 output_asm_insn ("cmp%.w #0,%1", loperands
);
1524 loperands
[5] = dest
;
1529 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1530 CODE_LABEL_NUMBER (loperands
[4]));
1531 output_asm_insn ("seq %5", loperands
);
1535 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1536 CODE_LABEL_NUMBER (loperands
[4]));
1537 output_asm_insn ("sne %5", loperands
);
1541 loperands
[6] = gen_label_rtx ();
1542 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1544 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1545 CODE_LABEL_NUMBER (loperands
[4]));
1546 output_asm_insn ("sgt %5", loperands
);
1547 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1548 CODE_LABEL_NUMBER (loperands
[6]));
1552 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1553 CODE_LABEL_NUMBER (loperands
[4]));
1554 output_asm_insn ("shi %5", loperands
);
1558 loperands
[6] = gen_label_rtx ();
1559 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1561 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1562 CODE_LABEL_NUMBER (loperands
[4]));
1563 output_asm_insn ("slt %5", loperands
);
1564 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1565 CODE_LABEL_NUMBER (loperands
[6]));
1569 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1570 CODE_LABEL_NUMBER (loperands
[4]));
1571 output_asm_insn ("scs %5", loperands
);
1575 loperands
[6] = gen_label_rtx ();
1576 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1578 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1579 CODE_LABEL_NUMBER (loperands
[4]));
1580 output_asm_insn ("sge %5", loperands
);
1581 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1582 CODE_LABEL_NUMBER (loperands
[6]));
1586 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1587 CODE_LABEL_NUMBER (loperands
[4]));
1588 output_asm_insn ("scc %5", loperands
);
1592 loperands
[6] = gen_label_rtx ();
1593 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1595 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1596 CODE_LABEL_NUMBER (loperands
[4]));
1597 output_asm_insn ("sle %5", loperands
);
1598 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1599 CODE_LABEL_NUMBER (loperands
[6]));
1603 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1604 CODE_LABEL_NUMBER (loperands
[4]));
1605 output_asm_insn ("sls %5", loperands
);
1615 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1617 operands
[0] = countop
;
1618 operands
[1] = dataop
;
1620 if (GET_CODE (countop
) == CONST_INT
)
1622 register int count
= INTVAL (countop
);
1623 /* If COUNT is bigger than size of storage unit in use,
1624 advance to the containing unit of same size. */
1625 if (count
> signpos
)
1627 int offset
= (count
& ~signpos
) / 8;
1628 count
= count
& signpos
;
1629 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1631 if (count
== signpos
)
1632 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1634 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1636 /* These three statements used to use next_insns_test_no...
1637 but it appears that this should do the same job. */
1639 && next_insn_tests_no_inequality (insn
))
1642 && next_insn_tests_no_inequality (insn
))
1645 && next_insn_tests_no_inequality (insn
))
1648 cc_status
.flags
= CC_NOT_NEGATIVE
;
1650 return "btst %0,%1";
1653 /* Legitimize PIC addresses. If the address is already
1654 position-independent, we return ORIG. Newly generated
1655 position-independent addresses go to REG. If we need more
1656 than one register, we lose.
1658 An address is legitimized by making an indirect reference
1659 through the Global Offset Table with the name of the symbol
1662 The assembler and linker are responsible for placing the
1663 address of the symbol in the GOT. The function prologue
1664 is responsible for initializing a5 to the starting address
1667 The assembler is also responsible for translating a symbol name
1668 into a constant displacement from the start of the GOT.
1670 A quick example may make things a little clearer:
1672 When not generating PIC code to store the value 12345 into _foo
1673 we would generate the following code:
1677 When generating PIC two transformations are made. First, the compiler
1678 loads the address of foo into a register. So the first transformation makes:
1683 The code in movsi will intercept the lea instruction and call this
1684 routine which will transform the instructions into:
1686 movel a5@(_foo:w), a0
1690 That (in a nutshell) is how *all* symbol and label references are
1694 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1699 /* First handle a simple SYMBOL_REF or LABEL_REF */
1700 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1704 pic_ref
= gen_rtx_MEM (Pmode
,
1705 gen_rtx_PLUS (Pmode
,
1706 pic_offset_table_rtx
, orig
));
1707 current_function_uses_pic_offset_table
= 1;
1708 MEM_READONLY_P (pic_ref
) = 1;
1709 emit_move_insn (reg
, pic_ref
);
1712 else if (GET_CODE (orig
) == CONST
)
1716 /* Make sure this has not already been legitimized. */
1717 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1718 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1723 /* legitimize both operands of the PLUS */
1724 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1726 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1727 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1728 base
== reg
? 0 : reg
);
1730 if (GET_CODE (orig
) == CONST_INT
)
1731 return plus_constant (base
, INTVAL (orig
));
1732 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1733 /* Likewise, should we set special REG_NOTEs here? */
1739 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1741 static CONST_METHOD
const_method (rtx
);
1743 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1746 const_method (rtx constant
)
1751 i
= INTVAL (constant
);
1755 /* The ColdFire doesn't have byte or word operations. */
1756 /* FIXME: This may not be useful for the m68060 either. */
1757 if (!TARGET_COLDFIRE
)
1759 /* if -256 < N < 256 but N is not in range for a moveq
1760 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1761 if (USE_MOVQ (i
^ 0xff))
1763 /* Likewise, try with not.w */
1764 if (USE_MOVQ (i
^ 0xffff))
1766 /* This is the only value where neg.w is useful */
1771 /* Try also with swap. */
1773 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1778 /* Try using MVZ/MVS with an immediate value to load constants. */
1779 if (i
>= 0 && i
<= 65535)
1781 if (i
>= -32768 && i
<= 32767)
1785 /* Otherwise, use move.l */
1790 const_int_cost (rtx constant
)
1792 switch (const_method (constant
))
1795 /* Constants between -128 and 127 are cheap due to moveq. */
1803 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1813 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1818 /* Constant zero is super cheap due to clr instruction. */
1819 if (x
== const0_rtx
)
1822 *total
= const_int_cost (x
);
1832 /* Make 0.0 cheaper than other floating constants to
1833 encourage creating tstsf and tstdf insns. */
1834 if (outer_code
== COMPARE
1835 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1841 /* These are vaguely right for a 68020. */
1842 /* The costs for long multiply have been adjusted to work properly
1843 in synth_mult on the 68020, relative to an average of the time
1844 for add and the time for shift, taking away a little more because
1845 sometimes move insns are needed. */
1846 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1852 : TARGET_COLDFIRE ? 3 : 13)
1857 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1858 : TARGET_COLDFIRE ? 2 : 8)
1861 (TARGET_CF_HWDIV ? 11 \
1862 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1865 /* An lea costs about three times as much as a simple add. */
1866 if (GET_MODE (x
) == SImode
1867 && GET_CODE (XEXP (x
, 1)) == REG
1868 && GET_CODE (XEXP (x
, 0)) == MULT
1869 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1870 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1871 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1872 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1873 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1875 /* lea an@(dx:l:i),am */
1876 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1886 *total
= COSTS_N_INSNS(1);
1891 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1893 if (INTVAL (XEXP (x
, 1)) < 16)
1894 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1896 /* We're using clrw + swap for these cases. */
1897 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1900 *total
= COSTS_N_INSNS (10); /* Worst case. */
1903 /* A shift by a big integer takes an extra instruction. */
1904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1905 && (INTVAL (XEXP (x
, 1)) == 16))
1907 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1910 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1911 && !(INTVAL (XEXP (x
, 1)) > 0
1912 && INTVAL (XEXP (x
, 1)) <= 8))
1914 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1920 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1921 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1922 && GET_MODE (x
) == SImode
)
1923 *total
= COSTS_N_INSNS (MULW_COST
);
1924 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1925 *total
= COSTS_N_INSNS (MULW_COST
);
1927 *total
= COSTS_N_INSNS (MULL_COST
);
1934 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1935 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1936 else if (TARGET_CF_HWDIV
)
1937 *total
= COSTS_N_INSNS (18);
1939 *total
= COSTS_N_INSNS (43); /* div.l */
1948 output_move_const_into_data_reg (rtx
*operands
)
1952 i
= INTVAL (operands
[1]);
1953 switch (const_method (operands
[1]))
1956 return "mvzw %1,%0";
1958 return "mvsw %1,%0";
1960 return "moveq %1,%0";
1963 operands
[1] = GEN_INT (i
^ 0xff);
1964 return "moveq %1,%0\n\tnot%.b %0";
1967 operands
[1] = GEN_INT (i
^ 0xffff);
1968 return "moveq %1,%0\n\tnot%.w %0";
1971 return "moveq #-128,%0\n\tneg%.w %0";
1976 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1977 return "moveq %1,%0\n\tswap %0";
1980 return "move%.l %1,%0";
1986 /* Return 1 if 'constant' can be represented by
1987 mov3q on a ColdFire V4 core. */
1989 valid_mov3q_const (rtx constant
)
1993 if (TARGET_ISAB
&& GET_CODE (constant
) == CONST_INT
)
1995 i
= INTVAL (constant
);
1996 if (i
== -1 || (i
>= 1 && i
<= 7))
2004 output_move_simode_const (rtx
*operands
)
2006 if (operands
[1] == const0_rtx
2007 && (DATA_REG_P (operands
[0])
2008 || GET_CODE (operands
[0]) == MEM
)
2009 /* clr insns on 68000 read before writing. */
2010 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2011 || !(GET_CODE (operands
[0]) == MEM
2012 && MEM_VOLATILE_P (operands
[0]))))
2014 else if ((GET_MODE (operands
[0]) == SImode
)
2015 && valid_mov3q_const (operands
[1]))
2016 return "mov3q%.l %1,%0";
2017 else if (operands
[1] == const0_rtx
2018 && ADDRESS_REG_P (operands
[0]))
2019 return "sub%.l %0,%0";
2020 else if (DATA_REG_P (operands
[0]))
2021 return output_move_const_into_data_reg (operands
);
2022 else if (ADDRESS_REG_P (operands
[0])
2023 && INTVAL (operands
[1]) < 0x8000
2024 && INTVAL (operands
[1]) >= -0x8000)
2026 if (valid_mov3q_const (operands
[1]))
2027 return "mov3q%.l %1,%0";
2028 return "move%.w %1,%0";
2030 else if (GET_CODE (operands
[0]) == MEM
2031 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2032 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2033 && INTVAL (operands
[1]) < 0x8000
2034 && INTVAL (operands
[1]) >= -0x8000)
2036 if (valid_mov3q_const (operands
[1]))
2037 return "mov3q%.l %1,%-";
2040 return "move%.l %1,%0";
2044 output_move_simode (rtx
*operands
)
2046 if (GET_CODE (operands
[1]) == CONST_INT
)
2047 return output_move_simode_const (operands
);
2048 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2049 || GET_CODE (operands
[1]) == CONST
)
2050 && push_operand (operands
[0], SImode
))
2052 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2053 || GET_CODE (operands
[1]) == CONST
)
2054 && ADDRESS_REG_P (operands
[0]))
2055 return "lea %a1,%0";
2056 return "move%.l %1,%0";
2060 output_move_himode (rtx
*operands
)
2062 if (GET_CODE (operands
[1]) == CONST_INT
)
2064 if (operands
[1] == const0_rtx
2065 && (DATA_REG_P (operands
[0])
2066 || GET_CODE (operands
[0]) == MEM
)
2067 /* clr insns on 68000 read before writing. */
2068 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2069 || !(GET_CODE (operands
[0]) == MEM
2070 && MEM_VOLATILE_P (operands
[0]))))
2072 else if (operands
[1] == const0_rtx
2073 && ADDRESS_REG_P (operands
[0]))
2074 return "sub%.l %0,%0";
2075 else if (DATA_REG_P (operands
[0])
2076 && INTVAL (operands
[1]) < 128
2077 && INTVAL (operands
[1]) >= -128)
2078 return "moveq %1,%0";
2079 else if (INTVAL (operands
[1]) < 0x8000
2080 && INTVAL (operands
[1]) >= -0x8000)
2081 return "move%.w %1,%0";
2083 else if (CONSTANT_P (operands
[1]))
2084 return "move%.l %1,%0";
2085 /* Recognize the insn before a tablejump, one that refers
2086 to a table of offsets. Such an insn will need to refer
2087 to a label on the insn. So output one. Use the label-number
2088 of the table of offsets to generate this label. This code,
2089 and similar code below, assumes that there will be at most one
2090 reference to each table. */
2091 if (GET_CODE (operands
[1]) == MEM
2092 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2093 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2094 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2096 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2098 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2099 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2101 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2102 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2104 return "move%.w %1,%0";
2108 output_move_qimode (rtx
*operands
)
2110 /* 68k family always modifies the stack pointer by at least 2, even for
2111 byte pushes. The 5200 (ColdFire) does not do this. */
2113 /* This case is generated by pushqi1 pattern now. */
2114 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2115 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2116 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2117 && ! ADDRESS_REG_P (operands
[1])
2118 && ! TARGET_COLDFIRE
));
2120 /* clr and st insns on 68000 read before writing. */
2121 if (!ADDRESS_REG_P (operands
[0])
2122 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2123 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2125 if (operands
[1] == const0_rtx
)
2127 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2128 && GET_CODE (operands
[1]) == CONST_INT
2129 && (INTVAL (operands
[1]) & 255) == 255)
2135 if (GET_CODE (operands
[1]) == CONST_INT
2136 && DATA_REG_P (operands
[0])
2137 && INTVAL (operands
[1]) < 128
2138 && INTVAL (operands
[1]) >= -128)
2139 return "moveq %1,%0";
2140 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2141 return "sub%.l %0,%0";
2142 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2143 return "move%.l %1,%0";
2144 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2145 from address registers. */
2146 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2147 return "move%.w %1,%0";
2148 return "move%.b %1,%0";
2152 output_move_stricthi (rtx
*operands
)
2154 if (operands
[1] == const0_rtx
2155 /* clr insns on 68000 read before writing. */
2156 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2157 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2159 return "move%.w %1,%0";
2163 output_move_strictqi (rtx
*operands
)
2165 if (operands
[1] == const0_rtx
2166 /* clr insns on 68000 read before writing. */
2167 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2168 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2170 return "move%.b %1,%0";
2173 /* Return the best assembler insn template
2174 for moving operands[1] into operands[0] as a fullword. */
2177 singlemove_string (rtx
*operands
)
2179 if (GET_CODE (operands
[1]) == CONST_INT
)
2180 return output_move_simode_const (operands
);
2181 return "move%.l %1,%0";
2185 /* Output assembler code to perform a doubleword move insn
2186 with operands OPERANDS. */
2189 output_move_double (rtx
*operands
)
2193 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2198 rtx addreg0
= 0, addreg1
= 0;
2199 int dest_overlapped_low
= 0;
2200 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2205 /* First classify both operands. */
2207 if (REG_P (operands
[0]))
2209 else if (offsettable_memref_p (operands
[0]))
2211 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2213 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2215 else if (GET_CODE (operands
[0]) == MEM
)
2220 if (REG_P (operands
[1]))
2222 else if (CONSTANT_P (operands
[1]))
2224 else if (offsettable_memref_p (operands
[1]))
2226 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2228 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2230 else if (GET_CODE (operands
[1]) == MEM
)
2235 /* Check for the cases that the operand constraints are not supposed
2236 to allow to happen. Generating code for these cases is
2238 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2240 /* If one operand is decrementing and one is incrementing
2241 decrement the former register explicitly
2242 and change that operand into ordinary indexing. */
2244 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2246 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2248 output_asm_insn ("sub%.l #12,%0", operands
);
2250 output_asm_insn ("subq%.l #8,%0", operands
);
2251 if (GET_MODE (operands
[1]) == XFmode
)
2252 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2253 else if (GET_MODE (operands
[0]) == DFmode
)
2254 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2256 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2259 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2261 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2263 output_asm_insn ("sub%.l #12,%1", operands
);
2265 output_asm_insn ("subq%.l #8,%1", operands
);
2266 if (GET_MODE (operands
[1]) == XFmode
)
2267 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2268 else if (GET_MODE (operands
[1]) == DFmode
)
2269 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2271 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2275 /* If an operand is an unoffsettable memory ref, find a register
2276 we can increment temporarily to make it refer to the second word. */
2278 if (optype0
== MEMOP
)
2279 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2281 if (optype1
== MEMOP
)
2282 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2284 /* Ok, we can do one word at a time.
2285 Normally we do the low-numbered word first,
2286 but if either operand is autodecrementing then we
2287 do the high-numbered word first.
2289 In either case, set up in LATEHALF the operands to use
2290 for the high-numbered word and in some cases alter the
2291 operands in OPERANDS to be suitable for the low-numbered word. */
2295 if (optype0
== REGOP
)
2297 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2298 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2300 else if (optype0
== OFFSOP
)
2302 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2303 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2307 middlehalf
[0] = operands
[0];
2308 latehalf
[0] = operands
[0];
2311 if (optype1
== REGOP
)
2313 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2314 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2316 else if (optype1
== OFFSOP
)
2318 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2319 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2321 else if (optype1
== CNSTOP
)
2323 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2328 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2329 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2330 operands
[1] = GEN_INT (l
[0]);
2331 middlehalf
[1] = GEN_INT (l
[1]);
2332 latehalf
[1] = GEN_INT (l
[2]);
2336 /* No non-CONST_DOUBLE constant should ever appear
2338 gcc_assert (!CONSTANT_P (operands
[1]));
2343 middlehalf
[1] = operands
[1];
2344 latehalf
[1] = operands
[1];
2348 /* size is not 12: */
2350 if (optype0
== REGOP
)
2351 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2352 else if (optype0
== OFFSOP
)
2353 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2355 latehalf
[0] = operands
[0];
2357 if (optype1
== REGOP
)
2358 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2359 else if (optype1
== OFFSOP
)
2360 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2361 else if (optype1
== CNSTOP
)
2362 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2364 latehalf
[1] = operands
[1];
2367 /* If insn is effectively movd N(sp),-(sp) then we will do the
2368 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2369 for the low word as well, to compensate for the first decrement of sp. */
2370 if (optype0
== PUSHOP
2371 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2372 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2373 operands
[1] = middlehalf
[1] = latehalf
[1];
2375 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2376 if the upper part of reg N does not appear in the MEM, arrange to
2377 emit the move late-half first. Otherwise, compute the MEM address
2378 into the upper part of N and use that as a pointer to the memory
2380 if (optype0
== REGOP
2381 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2383 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2385 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2386 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2388 /* If both halves of dest are used in the src memory address,
2389 compute the address into latehalf of dest.
2390 Note that this can't happen if the dest is two data regs. */
2392 xops
[0] = latehalf
[0];
2393 xops
[1] = XEXP (operands
[1], 0);
2394 output_asm_insn ("lea %a1,%0", xops
);
2395 if (GET_MODE (operands
[1]) == XFmode
)
2397 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2398 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2399 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2403 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2404 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2408 && reg_overlap_mentioned_p (middlehalf
[0],
2409 XEXP (operands
[1], 0)))
2411 /* Check for two regs used by both source and dest.
2412 Note that this can't happen if the dest is all data regs.
2413 It can happen if the dest is d6, d7, a0.
2414 But in that case, latehalf is an addr reg, so
2415 the code at compadr does ok. */
2417 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2418 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2421 /* JRV says this can't happen: */
2422 gcc_assert (!addreg0
&& !addreg1
);
2424 /* Only the middle reg conflicts; simply put it last. */
2425 output_asm_insn (singlemove_string (operands
), operands
);
2426 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2427 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2430 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2431 /* If the low half of dest is mentioned in the source memory
2432 address, the arrange to emit the move late half first. */
2433 dest_overlapped_low
= 1;
2436 /* If one or both operands autodecrementing,
2437 do the two words, high-numbered first. */
2439 /* Likewise, the first move would clobber the source of the second one,
2440 do them in the other order. This happens only for registers;
2441 such overlap can't happen in memory unless the user explicitly
2442 sets it up, and that is an undefined circumstance. */
2444 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2445 || (optype0
== REGOP
&& optype1
== REGOP
2446 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2447 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2448 || dest_overlapped_low
)
2450 /* Make any unoffsettable addresses point at high-numbered word. */
2454 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2456 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2461 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2463 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2467 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2469 /* Undo the adds we just did. */
2471 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2473 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2477 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2479 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2481 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2484 /* Do low-numbered word. */
2485 return singlemove_string (operands
);
2488 /* Normal case: do the two words, low-numbered first. */
2490 output_asm_insn (singlemove_string (operands
), operands
);
2492 /* Do the middle one of the three words for long double */
2496 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2498 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2500 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2503 /* Make any unoffsettable addresses point at high-numbered word. */
2505 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2507 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2510 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2512 /* Undo the adds we just did. */
2516 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2518 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2523 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2525 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2532 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2533 new rtx with the correct mode. */
2536 force_mode (enum machine_mode mode
, rtx orig
)
2538 if (mode
== GET_MODE (orig
))
2541 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2544 return gen_rtx_REG (mode
, REGNO (orig
));
2548 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2550 return reg_renumber
&& FP_REG_P (op
);
2553 /* Emit insns to move operands[1] into operands[0].
2555 Return 1 if we have written out everything that needs to be done to
2556 do the move. Otherwise, return 0 and the caller will emit the move
2559 Note SCRATCH_REG may not be in the proper mode depending on how it
2560 will be used. This routine is responsible for creating a new copy
2561 of SCRATCH_REG in the proper mode. */
2564 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2566 register rtx operand0
= operands
[0];
2567 register rtx operand1
= operands
[1];
2571 && reload_in_progress
&& GET_CODE (operand0
) == REG
2572 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2573 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2574 else if (scratch_reg
2575 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2576 && GET_CODE (SUBREG_REG (operand0
)) == REG
2577 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2579 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2580 the code which tracks sets/uses for delete_output_reload. */
2581 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2582 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2583 SUBREG_BYTE (operand0
));
2584 operand0
= alter_subreg (&temp
);
2588 && reload_in_progress
&& GET_CODE (operand1
) == REG
2589 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2590 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2591 else if (scratch_reg
2592 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2593 && GET_CODE (SUBREG_REG (operand1
)) == REG
2594 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2596 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2597 the code which tracks sets/uses for delete_output_reload. */
2598 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2599 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2600 SUBREG_BYTE (operand1
));
2601 operand1
= alter_subreg (&temp
);
2604 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2605 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2606 != XEXP (operand0
, 0)))
2607 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2608 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2609 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2610 != XEXP (operand1
, 0)))
2611 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2613 /* Handle secondary reloads for loads/stores of FP registers where
2614 the address is symbolic by using the scratch register */
2615 if (fp_reg_operand (operand0
, mode
)
2616 && ((GET_CODE (operand1
) == MEM
2617 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2618 || ((GET_CODE (operand1
) == SUBREG
2619 && GET_CODE (XEXP (operand1
, 0)) == MEM
2620 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2623 if (GET_CODE (operand1
) == SUBREG
)
2624 operand1
= XEXP (operand1
, 0);
2626 /* SCRATCH_REG will hold an address. We want
2627 it in SImode regardless of what mode it was originally given
2629 scratch_reg
= force_mode (SImode
, scratch_reg
);
2631 /* D might not fit in 14 bits either; for such cases load D into
2633 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2635 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2636 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2638 XEXP (XEXP (operand1
, 0), 0),
2642 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2643 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2644 gen_rtx_MEM (mode
, scratch_reg
)));
2647 else if (fp_reg_operand (operand1
, mode
)
2648 && ((GET_CODE (operand0
) == MEM
2649 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2650 || ((GET_CODE (operand0
) == SUBREG
)
2651 && GET_CODE (XEXP (operand0
, 0)) == MEM
2652 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2655 if (GET_CODE (operand0
) == SUBREG
)
2656 operand0
= XEXP (operand0
, 0);
2658 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2659 it in SIMODE regardless of what mode it was originally given
2661 scratch_reg
= force_mode (SImode
, scratch_reg
);
2663 /* D might not fit in 14 bits either; for such cases load D into
2665 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2667 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2668 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2671 XEXP (XEXP (operand0
, 0),
2676 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2677 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2681 /* Handle secondary reloads for loads of FP registers from constant
2682 expressions by forcing the constant into memory.
2684 use scratch_reg to hold the address of the memory location.
2686 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2687 NO_REGS when presented with a const_int and an register class
2688 containing only FP registers. Doing so unfortunately creates
2689 more problems than it solves. Fix this for 2.5. */
2690 else if (fp_reg_operand (operand0
, mode
)
2691 && CONSTANT_P (operand1
)
2696 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2697 it in SIMODE regardless of what mode it was originally given
2699 scratch_reg
= force_mode (SImode
, scratch_reg
);
2701 /* Force the constant into memory and put the address of the
2702 memory location into scratch_reg. */
2703 xoperands
[0] = scratch_reg
;
2704 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2705 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2707 /* Now load the destination register. */
2708 emit_insn (gen_rtx_SET (mode
, operand0
,
2709 gen_rtx_MEM (mode
, scratch_reg
)));
2713 /* Now have insn-emit do whatever it normally does. */
2717 /* Return a REG that occurs in ADDR with coefficient 1.
2718 ADDR can be effectively incremented by incrementing REG. */
2721 find_addr_reg (rtx addr
)
2723 while (GET_CODE (addr
) == PLUS
)
2725 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2726 addr
= XEXP (addr
, 0);
2727 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2728 addr
= XEXP (addr
, 1);
2729 else if (CONSTANT_P (XEXP (addr
, 0)))
2730 addr
= XEXP (addr
, 1);
2731 else if (CONSTANT_P (XEXP (addr
, 1)))
2732 addr
= XEXP (addr
, 0);
2736 gcc_assert (GET_CODE (addr
) == REG
);
2740 /* Output assembler code to perform a 32-bit 3-operand add. */
2743 output_addsi3 (rtx
*operands
)
2745 if (! operands_match_p (operands
[0], operands
[1]))
2747 if (!ADDRESS_REG_P (operands
[1]))
2749 rtx tmp
= operands
[1];
2751 operands
[1] = operands
[2];
2755 /* These insns can result from reloads to access
2756 stack slots over 64k from the frame pointer. */
2757 if (GET_CODE (operands
[2]) == CONST_INT
2758 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2759 return "move%.l %2,%0\n\tadd%.l %1,%0";
2760 if (GET_CODE (operands
[2]) == REG
)
2761 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2762 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2764 if (GET_CODE (operands
[2]) == CONST_INT
)
2766 if (INTVAL (operands
[2]) > 0
2767 && INTVAL (operands
[2]) <= 8)
2768 return "addq%.l %2,%0";
2769 if (INTVAL (operands
[2]) < 0
2770 && INTVAL (operands
[2]) >= -8)
2772 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2773 return "subq%.l %2,%0";
2775 /* On the CPU32 it is faster to use two addql instructions to
2776 add a small integer (8 < N <= 16) to a register.
2777 Likewise for subql. */
2778 if (TUNE_CPU32
&& REG_P (operands
[0]))
2780 if (INTVAL (operands
[2]) > 8
2781 && INTVAL (operands
[2]) <= 16)
2783 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2784 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2786 if (INTVAL (operands
[2]) < -8
2787 && INTVAL (operands
[2]) >= -16)
2789 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2790 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2793 if (ADDRESS_REG_P (operands
[0])
2794 && INTVAL (operands
[2]) >= -0x8000
2795 && INTVAL (operands
[2]) < 0x8000)
2798 return "add%.w %2,%0";
2800 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2803 return "add%.l %2,%0";
2806 /* Store in cc_status the expressions that the condition codes will
2807 describe after execution of an instruction whose pattern is EXP.
2808 Do not alter them if the instruction would not alter the cc's. */
2810 /* On the 68000, all the insns to store in an address register fail to
2811 set the cc's. However, in some cases these instructions can make it
2812 possibly invalid to use the saved cc's. In those cases we clear out
2813 some or all of the saved cc's so they won't be used. */
2816 notice_update_cc (rtx exp
, rtx insn
)
2818 if (GET_CODE (exp
) == SET
)
2820 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2822 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2824 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2825 cc_status
.value1
= 0;
2826 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2827 cc_status
.value2
= 0;
2829 else if (!FP_REG_P (SET_DEST (exp
))
2830 && SET_DEST (exp
) != cc0_rtx
2831 && (FP_REG_P (SET_SRC (exp
))
2832 || GET_CODE (SET_SRC (exp
)) == FIX
2833 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2834 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2836 /* A pair of move insns doesn't produce a useful overall cc. */
2837 else if (!FP_REG_P (SET_DEST (exp
))
2838 && !FP_REG_P (SET_SRC (exp
))
2839 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2840 && (GET_CODE (SET_SRC (exp
)) == REG
2841 || GET_CODE (SET_SRC (exp
)) == MEM
2842 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2844 else if (SET_DEST (exp
) != pc_rtx
)
2846 cc_status
.flags
= 0;
2847 cc_status
.value1
= SET_DEST (exp
);
2848 cc_status
.value2
= SET_SRC (exp
);
2851 else if (GET_CODE (exp
) == PARALLEL
2852 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2854 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2855 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2857 if (ADDRESS_REG_P (dest
))
2859 else if (dest
!= pc_rtx
)
2861 cc_status
.flags
= 0;
2862 cc_status
.value1
= dest
;
2863 cc_status
.value2
= src
;
2868 if (cc_status
.value2
!= 0
2869 && ADDRESS_REG_P (cc_status
.value2
)
2870 && GET_MODE (cc_status
.value2
) == QImode
)
2872 if (cc_status
.value2
!= 0)
2873 switch (GET_CODE (cc_status
.value2
))
2875 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2876 case ROTATE
: case ROTATERT
:
2877 /* These instructions always clear the overflow bit, and set
2878 the carry to the bit shifted out. */
2879 /* ??? We don't currently have a way to signal carry not valid,
2880 nor do we check for it in the branch insns. */
2884 case PLUS
: case MINUS
: case MULT
:
2885 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2886 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2887 cc_status
.flags
|= CC_NO_OVERFLOW
;
2890 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2891 ends with a move insn moving r2 in r2's mode.
2892 Thus, the cc's are set for r2.
2893 This can set N bit spuriously. */
2894 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2899 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2901 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2902 cc_status
.value2
= 0;
2903 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2904 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2905 cc_status
.flags
= CC_IN_68881
;
2909 output_move_const_double (rtx
*operands
)
2911 int code
= standard_68881_constant_p (operands
[1]);
2915 static char buf
[40];
2917 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2920 return "fmove%.d %1,%0";
2924 output_move_const_single (rtx
*operands
)
2926 int code
= standard_68881_constant_p (operands
[1]);
2930 static char buf
[40];
2932 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2935 return "fmove%.s %f1,%0";
2938 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2939 from the "fmovecr" instruction.
2940 The value, anded with 0xff, gives the code to use in fmovecr
2941 to get the desired constant. */
2943 /* This code has been fixed for cross-compilation. */
2945 static int inited_68881_table
= 0;
2947 static const char *const strings_68881
[7] = {
2957 static const int codes_68881
[7] = {
2967 REAL_VALUE_TYPE values_68881
[7];
2969 /* Set up values_68881 array by converting the decimal values
2970 strings_68881 to binary. */
2973 init_68881_table (void)
2977 enum machine_mode mode
;
2980 for (i
= 0; i
< 7; i
++)
2984 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2985 values_68881
[i
] = r
;
2987 inited_68881_table
= 1;
2991 standard_68881_constant_p (rtx x
)
2996 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2997 used at all on those chips. */
3001 if (! inited_68881_table
)
3002 init_68881_table ();
3004 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3006 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3008 for (i
= 0; i
< 6; i
++)
3010 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3011 return (codes_68881
[i
]);
3014 if (GET_MODE (x
) == SFmode
)
3017 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3018 return (codes_68881
[6]);
3020 /* larger powers of ten in the constants ram are not used
3021 because they are not equal to a `double' C constant. */
3025 /* If X is a floating-point constant, return the logarithm of X base 2,
3026 or 0 if X is not a power of 2. */
3029 floating_exact_log2 (rtx x
)
3031 REAL_VALUE_TYPE r
, r1
;
3034 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3036 if (REAL_VALUES_LESS (r
, dconst1
))
3039 exp
= real_exponent (&r
);
3040 real_2expN (&r1
, exp
);
3041 if (REAL_VALUES_EQUAL (r1
, r
))
3047 /* A C compound statement to output to stdio stream STREAM the
3048 assembler syntax for an instruction operand X. X is an RTL
3051 CODE is a value that can be used to specify one of several ways
3052 of printing the operand. It is used when identical operands
3053 must be printed differently depending on the context. CODE
3054 comes from the `%' specification that was used to request
3055 printing of the operand. If the specification was just `%DIGIT'
3056 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3057 is the ASCII code for LTR.
3059 If X is a register, this macro should print the register's name.
3060 The names can be found in an array `reg_names' whose type is
3061 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3063 When the machine description has a specification `%PUNCT' (a `%'
3064 followed by a punctuation character), this macro is called with
3065 a null pointer for X and the punctuation character for CODE.
3067 The m68k specific codes are:
3069 '.' for dot needed in Motorola-style opcode names.
3070 '-' for an operand pushing on the stack:
3071 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3072 '+' for an operand pushing on the stack:
3073 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3074 '@' for a reference to the top word on the stack:
3075 sp@, (sp) or (%sp) depending on the style of syntax.
3076 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3077 but & in SGS syntax).
3078 '!' for the cc register (used in an `and to cc' insn).
3079 '$' for the letter `s' in an op code, but only on the 68040.
3080 '&' for the letter `d' in an op code, but only on the 68040.
3081 '/' for register prefix needed by longlong.h.
3083 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3084 'd' to force memory addressing to be absolute, not relative.
3085 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3086 'o' for operands to go directly to output_operand_address (bypassing
3087 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
3088 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3089 or print pair of registers as rx:ry.
3094 print_operand (FILE *file
, rtx op
, int letter
)
3099 fprintf (file
, ".");
3101 else if (letter
== '#')
3102 asm_fprintf (file
, "%I");
3103 else if (letter
== '-')
3104 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3105 else if (letter
== '+')
3106 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3107 else if (letter
== '@')
3108 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3109 else if (letter
== '!')
3110 asm_fprintf (file
, "%Rfpcr");
3111 else if (letter
== '$')
3114 fprintf (file
, "s");
3116 else if (letter
== '&')
3119 fprintf (file
, "d");
3121 else if (letter
== '/')
3122 asm_fprintf (file
, "%R");
3123 else if (letter
== 'o')
3125 /* This is only for direct addresses with TARGET_PCREL */
3126 gcc_assert (GET_CODE (op
) == MEM
3127 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3129 output_addr_const (file
, XEXP (op
, 0));
3131 else if (GET_CODE (op
) == REG
)
3134 /* Print out the second register name of a register pair.
3135 I.e., R (6) => 7. */
3136 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3138 fputs (M68K_REGNAME(REGNO (op
)), file
);
3140 else if (GET_CODE (op
) == MEM
)
3142 output_address (XEXP (op
, 0));
3143 if (letter
== 'd' && ! TARGET_68020
3144 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3145 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3146 && INTVAL (XEXP (op
, 0)) < 0x8000
3147 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3148 fprintf (file
, MOTOROLA
? ".l" : ":l");
3150 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3153 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3154 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3156 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3159 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3160 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3162 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3165 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3166 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3170 /* Use `print_operand_address' instead of `output_addr_const'
3171 to ensure that we print relevant PIC stuff. */
3172 asm_fprintf (file
, "%I");
3174 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3175 print_operand_address (file
, op
);
3177 output_addr_const (file
, op
);
3182 /* A C compound statement to output to stdio stream STREAM the
3183 assembler syntax for an instruction operand that is a memory
3184 reference whose address is ADDR. ADDR is an RTL expression.
3186 Note that this contains a kludge that knows that the only reason
3187 we have an address (plus (label_ref...) (reg...)) when not generating
3188 PIC code is in the insn before a tablejump, and we know that m68k.md
3189 generates a label LInnn: on such an insn.
3191 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3192 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3194 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3195 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3196 we want. This difference can be accommodated by using an assembler
3197 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3198 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3199 macro. See m68k/sgs.h for an example; for versions without the bug.
3200 Some assemblers refuse all the above solutions. The workaround is to
3201 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3204 They also do not like things like "pea 1.w", so we simple leave off
3205 the .w on small constants.
3207 This routine is responsible for distinguishing between -fpic and -fPIC
3208 style relocations in an address. When generating -fpic code the
3209 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3210 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3213 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3214 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3215 #else /* !MOTOROLA */
3216 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3217 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3218 #endif /* !MOTOROLA */
3221 print_operand_address (FILE *file
, rtx addr
)
3223 register rtx reg1
, reg2
, breg
, ireg
;
3226 switch (GET_CODE (addr
))
3229 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3232 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3233 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3236 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3237 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3240 reg1
= reg2
= ireg
= breg
= offset
= 0;
3241 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3243 offset
= XEXP (addr
, 0);
3244 addr
= XEXP (addr
, 1);
3246 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3248 offset
= XEXP (addr
, 1);
3249 addr
= XEXP (addr
, 0);
3251 if (GET_CODE (addr
) != PLUS
)
3255 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3257 reg1
= XEXP (addr
, 0);
3258 addr
= XEXP (addr
, 1);
3260 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3262 reg1
= XEXP (addr
, 1);
3263 addr
= XEXP (addr
, 0);
3265 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3267 reg1
= XEXP (addr
, 0);
3268 addr
= XEXP (addr
, 1);
3270 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3272 reg1
= XEXP (addr
, 1);
3273 addr
= XEXP (addr
, 0);
3275 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3277 reg1
= XEXP (addr
, 0);
3278 addr
= XEXP (addr
, 1);
3280 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3282 reg1
= XEXP (addr
, 1);
3283 addr
= XEXP (addr
, 0);
3285 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3286 || GET_CODE (addr
) == SIGN_EXTEND
)
3294 #if 0 /* for OLD_INDEXING */
3295 else if (GET_CODE (addr
) == PLUS
)
3297 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3299 reg2
= XEXP (addr
, 0);
3300 addr
= XEXP (addr
, 1);
3302 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3304 reg2
= XEXP (addr
, 1);
3305 addr
= XEXP (addr
, 0);
3314 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3315 || GET_CODE (reg1
) == MULT
))
3316 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3321 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3326 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3327 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3330 if (GET_CODE (ireg
) == MULT
)
3332 scale
= INTVAL (XEXP (ireg
, 1));
3333 ireg
= XEXP (ireg
, 0);
3335 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3337 ASM_OUTPUT_CASE_FETCH (file
,
3338 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3339 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3340 fprintf (file
, "w");
3344 ASM_OUTPUT_CASE_FETCH (file
,
3345 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3346 M68K_REGNAME (REGNO (ireg
)));
3347 fprintf (file
, "l");
3350 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3354 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3355 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3357 ASM_OUTPUT_CASE_FETCH (file
,
3358 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3359 M68K_REGNAME (REGNO (breg
)));
3360 fprintf (file
, "l)");
3363 if (ireg
!= 0 || breg
!= 0)
3368 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3374 output_addr_const (file
, addr
);
3375 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3377 fprintf (file
, "@GOT");
3379 fprintf (file
, ".w");
3382 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3386 else /* !MOTOROLA */
3388 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3391 output_addr_const (file
, addr
);
3392 if (breg
== pic_offset_table_rtx
)
3396 fprintf (file
, ":w");
3399 fprintf (file
, ":l");
3408 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3410 scale
= INTVAL (XEXP (ireg
, 1));
3411 ireg
= XEXP (ireg
, 0);
3413 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3414 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3415 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3417 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3418 M68K_REGNAME (REGNO (ireg
)));
3420 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3424 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3425 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3427 ASM_OUTPUT_CASE_FETCH (file
,
3428 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3429 M68K_REGNAME (REGNO (reg1
)));
3430 fprintf (file
, "l)");
3433 /* FALL-THROUGH (is this really what we want?) */
3435 if (GET_CODE (addr
) == CONST_INT
3436 && INTVAL (addr
) < 0x8000
3437 && INTVAL (addr
) >= -0x8000)
3439 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3441 else if (GET_CODE (addr
) == CONST_INT
)
3443 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3445 else if (TARGET_PCREL
)
3448 output_addr_const (file
, addr
);
3450 asm_fprintf (file
, ":w,%Rpc)");
3452 asm_fprintf (file
, ":l,%Rpc)");
3456 /* Special case for SYMBOL_REF if the symbol name ends in
3457 `.<letter>', this can be mistaken as a size suffix. Put
3458 the name in parentheses. */
3459 if (GET_CODE (addr
) == SYMBOL_REF
3460 && strlen (XSTR (addr
, 0)) > 2
3461 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3464 output_addr_const (file
, addr
);
3468 output_addr_const (file
, addr
);
3474 /* Check for cases where a clr insns can be omitted from code using
3475 strict_low_part sets. For example, the second clrl here is not needed:
3476 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3478 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3479 insn we are checking for redundancy. TARGET is the register set by the
3483 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3488 p
= prev_nonnote_insn (first_insn
);
3492 /* If it isn't an insn, then give up. */
3493 if (GET_CODE (p
) != INSN
)
3496 if (reg_set_p (target
, p
))
3498 rtx set
= single_set (p
);
3501 /* If it isn't an easy to recognize insn, then give up. */
3505 dest
= SET_DEST (set
);
3507 /* If this sets the entire target register to zero, then our
3508 first_insn is redundant. */
3509 if (rtx_equal_p (dest
, target
)
3510 && SET_SRC (set
) == const0_rtx
)
3512 else if (GET_CODE (dest
) == STRICT_LOW_PART
3513 && GET_CODE (XEXP (dest
, 0)) == REG
3514 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3515 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3516 <= GET_MODE_SIZE (mode
)))
3517 /* This is a strict low part set which modifies less than
3518 we are using, so it is safe. */
3524 p
= prev_nonnote_insn (p
);
3530 /* Operand predicates for implementing asymmetric pc-relative addressing
3531 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3532 when used as a source operand, but not as a destination operand.
3534 We model this by restricting the meaning of the basic predicates
3535 (general_operand, memory_operand, etc) to forbid the use of this
3536 addressing mode, and then define the following predicates that permit
3537 this addressing mode. These predicates can then be used for the
3538 source operands of the appropriate instructions.
3540 n.b. While it is theoretically possible to change all machine patterns
3541 to use this addressing more where permitted by the architecture,
3542 it has only been implemented for "common" cases: SImode, HImode, and
3543 QImode operands, and only for the principle operations that would
3544 require this addressing mode: data movement and simple integer operations.
3546 In parallel with these new predicates, two new constraint letters
3547 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3548 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3549 In the pcrel case 's' is only valid in combination with 'a' registers.
3550 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3551 of how these constraints are used.
3553 The use of these predicates is strictly optional, though patterns that
3554 don't will cause an extra reload register to be allocated where one
3557 lea (abc:w,%pc),%a0 ; need to reload address
3558 moveq &1,%d1 ; since write to pc-relative space
3559 movel %d1,%a0@ ; is not allowed
3561 lea (abc:w,%pc),%a1 ; no need to reload address here
3562 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3564 For more info, consult tiemann@cygnus.com.
3567 All of the ugliness with predicates and constraints is due to the
3568 simple fact that the m68k does not allow a pc-relative addressing
3569 mode as a destination. gcc does not distinguish between source and
3570 destination addresses. Hence, if we claim that pc-relative address
3571 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3572 end up with invalid code. To get around this problem, we left
3573 pc-relative modes as invalid addresses, and then added special
3574 predicates and constraints to accept them.
3576 A cleaner way to handle this is to modify gcc to distinguish
3577 between source and destination addresses. We can then say that
3578 pc-relative is a valid source address but not a valid destination
3579 address, and hopefully avoid a lot of the predicate and constraint
3580 hackery. Unfortunately, this would be a pretty big change. It would
3581 be a useful change for a number of ports, but there aren't any current
3582 plans to undertake this.
3584 ***************************************************************************/
3588 output_andsi3 (rtx
*operands
)
3591 if (GET_CODE (operands
[2]) == CONST_INT
3592 && (INTVAL (operands
[2]) | 0xffff) == -1
3593 && (DATA_REG_P (operands
[0])
3594 || offsettable_memref_p (operands
[0]))
3595 && !TARGET_COLDFIRE
)
3597 if (GET_CODE (operands
[0]) != REG
)
3598 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3599 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3600 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3602 if (operands
[2] == const0_rtx
)
3604 return "and%.w %2,%0";
3606 if (GET_CODE (operands
[2]) == CONST_INT
3607 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3608 && (DATA_REG_P (operands
[0])
3609 || offsettable_memref_p (operands
[0])))
3611 if (DATA_REG_P (operands
[0]))
3612 operands
[1] = GEN_INT (logval
);
3615 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3616 operands
[1] = GEN_INT (logval
% 8);
3618 /* This does not set condition codes in a standard way. */
3620 return "bclr %1,%0";
3622 return "and%.l %2,%0";
3626 output_iorsi3 (rtx
*operands
)
3628 register int logval
;
3629 if (GET_CODE (operands
[2]) == CONST_INT
3630 && INTVAL (operands
[2]) >> 16 == 0
3631 && (DATA_REG_P (operands
[0])
3632 || offsettable_memref_p (operands
[0]))
3633 && !TARGET_COLDFIRE
)
3635 if (GET_CODE (operands
[0]) != REG
)
3636 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3637 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3639 if (INTVAL (operands
[2]) == 0xffff)
3640 return "mov%.w %2,%0";
3641 return "or%.w %2,%0";
3643 if (GET_CODE (operands
[2]) == CONST_INT
3644 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3645 && (DATA_REG_P (operands
[0])
3646 || offsettable_memref_p (operands
[0])))
3648 if (DATA_REG_P (operands
[0]))
3649 operands
[1] = GEN_INT (logval
);
3652 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3653 operands
[1] = GEN_INT (logval
% 8);
3656 return "bset %1,%0";
3658 return "or%.l %2,%0";
3662 output_xorsi3 (rtx
*operands
)
3664 register int logval
;
3665 if (GET_CODE (operands
[2]) == CONST_INT
3666 && INTVAL (operands
[2]) >> 16 == 0
3667 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3668 && !TARGET_COLDFIRE
)
3670 if (! DATA_REG_P (operands
[0]))
3671 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3672 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3674 if (INTVAL (operands
[2]) == 0xffff)
3676 return "eor%.w %2,%0";
3678 if (GET_CODE (operands
[2]) == CONST_INT
3679 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3680 && (DATA_REG_P (operands
[0])
3681 || offsettable_memref_p (operands
[0])))
3683 if (DATA_REG_P (operands
[0]))
3684 operands
[1] = GEN_INT (logval
);
3687 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3688 operands
[1] = GEN_INT (logval
% 8);
3691 return "bchg %1,%0";
3693 return "eor%.l %2,%0";
3696 #ifdef M68K_TARGET_COFF
3698 /* Output assembly to switch to section NAME with attribute FLAGS. */
3701 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3702 tree decl ATTRIBUTE_UNUSED
)
3706 if (flags
& SECTION_WRITE
)
3711 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3714 #endif /* M68K_TARGET_COFF */
3717 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3718 HOST_WIDE_INT delta
,
3719 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3725 if (delta
> 0 && delta
<= 8)
3726 asm_fprintf (file
, (MOTOROLA
3727 ? "\taddq.l %I%d,4(%Rsp)\n"
3728 : "\taddql %I%d,%Rsp@(4)\n"),
3730 else if (delta
< 0 && delta
>= -8)
3731 asm_fprintf (file
, (MOTOROLA
3732 ? "\tsubq.l %I%d,4(%Rsp)\n"
3733 : "\tsubql %I%d,%Rsp@(4)\n"),
3735 else if (TARGET_COLDFIRE
)
3737 /* ColdFire can't add/sub a constant to memory unless it is in
3738 the range of addq/subq. So load the value into %d0 and
3739 then add it to 4(%sp). */
3740 if (delta
>= -128 && delta
<= 127)
3741 asm_fprintf (file
, (MOTOROLA
3742 ? "\tmoveq.l %I%wd,%Rd0\n"
3743 : "\tmoveql %I%wd,%Rd0\n"),
3746 asm_fprintf (file
, (MOTOROLA
3747 ? "\tmove.l %I%wd,%Rd0\n"
3748 : "\tmovel %I%wd,%Rd0\n"),
3750 asm_fprintf (file
, (MOTOROLA
3751 ? "\tadd.l %Rd0,4(%Rsp)\n"
3752 : "\taddl %Rd0,%Rsp@(4)\n"));
3755 asm_fprintf (file
, (MOTOROLA
3756 ? "\tadd.l %I%wd,4(%Rsp)\n"
3757 : "\taddl %I%wd,%Rsp@(4)\n"),
3760 xops
[0] = DECL_RTL (function
);
3762 /* Logic taken from call patterns in m68k.md. */
3767 else if (flag_pic
== 1 || TARGET_68020
)
3771 #if defined (USE_GAS)
3772 fmt
= "bra.l %0@PLTPC";
3774 fmt
= "bra %0@PLTPC";
3777 else /* !MOTOROLA */
3786 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3787 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3789 fmt
= "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)";
3793 #if MOTOROLA && !defined (USE_GAS)
3800 output_asm_insn (fmt
, xops
);
3803 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3806 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3807 int incoming ATTRIBUTE_UNUSED
)
3809 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3812 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3814 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3815 unsigned int new_reg
)
3818 /* Interrupt functions can only use registers that have already been
3819 saved by the prologue, even if they would normally be
3822 if (m68k_interrupt_function_p (current_function_decl
)
3823 && !regs_ever_live
[new_reg
])
3829 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3830 On the 68000, the cpu registers can hold any mode except bytes in address
3831 registers, but the 68881 registers can hold only SFmode or DFmode. */
3833 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3835 if (DATA_REGNO_P (regno
))
3837 /* Data Registers, can hold aggregate if fits in. */
3838 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3841 else if (ADDRESS_REGNO_P (regno
))
3843 /* Address Registers, can't hold bytes, can hold aggregate if
3845 if (GET_MODE_SIZE (mode
) == 1)
3847 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3850 else if (FP_REGNO_P (regno
))
3852 /* FPU registers, hold float or complex float of long double or
3854 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3855 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3856 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3862 /* Return floating point values in a 68881 register. This makes 68881 code
3863 a little bit faster. It also makes -msoft-float code incompatible with
3864 hard-float code, so people have to be careful not to mix the two.
3865 For ColdFire it was decided the ABI incompatibility is undesirable.
3866 If there is need for a hard-float ABI it is probably worth doing it
3867 properly and also passing function arguments in FP registers. */
3869 m68k_libcall_value (enum machine_mode mode
)
3876 return gen_rtx_REG (mode
, 16);
3881 return gen_rtx_REG (mode
, 0);
3885 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3887 enum machine_mode mode
;
3889 mode
= TYPE_MODE (valtype
);
3895 return gen_rtx_REG (mode
, 16);
3901 /* If the function returns a pointer, push that into %a0 */
3902 if (POINTER_TYPE_P (valtype
))
3903 return gen_rtx_REG (mode
, 8);
3905 return gen_rtx_REG (mode
, 0);