1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
38 /* Needed for use_return_insn. */
41 #ifdef SUPPORT_SUN_FPA
43 /* Index into this array by (register number >> 3) to find the
44 smallest class which contains that register. */
45 enum reg_class regno_reg_class
[]
46 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
47 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
49 #endif /* defined SUPPORT_SUN_FPA */
51 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
52 if SGS_SWITCH_TABLE. */
53 int switch_table_difference_label_flag
;
55 static rtx
find_addr_reg ();
56 rtx
legitimize_pic_address ();
57 void print_operand_address ();
60 /* Alignment to use for loops and jumps */
61 /* Specify power of two alignment used for loops. */
62 const char *m68k_align_loops_string
;
63 /* Specify power of two alignment used for non-loop jumps. */
64 const char *m68k_align_jumps_string
;
65 /* Specify power of two alignment used for functions. */
66 const char *m68k_align_funcs_string
;
68 /* Specify power of two alignment used for loops. */
70 /* Specify power of two alignment used for non-loop jumps. */
72 /* Specify power of two alignment used for functions. */
75 /* Nonzero if the last compare/test insn had FP operands. The
76 sCC expanders peek at this to determine what to do for the
77 68060, which has no fsCC instructions. */
78 int m68k_last_compare_had_fp_operands
;
80 /* Sometimes certain combinations of command options do not make
81 sense on a particular target machine. You can define a macro
82 `OVERRIDE_OPTIONS' to take account of this. This macro, if
83 defined, is executed once just after all the command options have
86 Don't use this macro to turn on various extra optimizations for
87 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
96 /* Validate -malign-loops= value, or provide default */
97 if (m68k_align_loops_string
)
99 m68k_align_loops
= atoi (m68k_align_loops_string
);
100 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
101 fatal ("-malign-loops=%d is not between 1 and %d",
102 m68k_align_loops
, MAX_CODE_ALIGN
);
105 m68k_align_loops
= def_align
;
107 /* Validate -malign-jumps= value, or provide default */
108 if (m68k_align_jumps_string
)
110 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
111 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
112 fatal ("-malign-jumps=%d is not between 1 and %d",
113 m68k_align_jumps
, MAX_CODE_ALIGN
);
116 m68k_align_jumps
= def_align
;
118 /* Validate -malign-functions= value, or provide default */
119 if (m68k_align_funcs_string
)
121 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
122 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
123 fatal ("-malign-functions=%d is not between 1 and %d",
124 m68k_align_funcs
, MAX_CODE_ALIGN
);
127 m68k_align_funcs
= def_align
;
130 /* This function generates the assembly code for function entry.
131 STREAM is a stdio stream to output the code to.
132 SIZE is an int: how many units of temporary storage to allocate.
133 Refer to the array `regs_ever_live' to determine which registers
134 to save; `regs_ever_live[I]' is nonzero if register number I
135 is ever used in the function. This function is responsible for
136 knowing which registers should not be saved even if used. */
139 /* Note that the order of the bit mask for fmovem is the opposite
140 of the order for movem! */
144 output_function_prologue (stream
, size
)
149 register int mask
= 0;
150 int num_saved_regs
= 0;
151 extern char call_used_regs
[];
152 int fsize
= (size
+ 3) & -4;
153 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
156 if (frame_pointer_needed
)
158 if (fsize
== 0 && TARGET_68040
)
160 /* on the 68040, pea + move is faster than link.w 0 */
162 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
163 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
164 reg_names
[FRAME_POINTER_REGNUM
]);
166 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
167 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
168 reg_names
[FRAME_POINTER_REGNUM
]);
171 else if (fsize
< 0x8000)
174 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
175 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
177 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
178 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
181 else if (TARGET_68020
)
184 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
185 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
187 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
188 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
193 /* Adding negative number is faster on the 68040. */
195 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
196 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
198 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
199 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 if (dwarf2out_do_frame ())
205 l
= (char *) dwarf2out_cfi_label ();
206 cfa_store_offset
+= 4;
207 cfa_offset
= cfa_store_offset
;
208 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
209 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
210 cfa_store_offset
+= fsize
;
215 if (fsize
+ 4 < 0x8000)
222 /* asm_fprintf() cannot handle %. */
224 asm_fprintf (stream
, "\tsubq.w %0I%d,%Rsp\n", fsize
+ 4);
226 asm_fprintf (stream
, "\tsubqw %0I%d,%Rsp\n", fsize
+ 4);
231 /* asm_fprintf() cannot handle %. */
233 asm_fprintf (stream
, "\tsubq.l %0I%d,%Rsp\n", fsize
+ 4);
235 asm_fprintf (stream
, "\tsubql %0I%d,%Rsp\n", fsize
+ 4);
239 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
241 /* On the CPU32 it is faster to use two subqw instructions to
242 subtract a small integer (8 < N <= 16) to a register. */
243 /* asm_fprintf() cannot handle %. */
245 asm_fprintf (stream
, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
248 asm_fprintf (stream
, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
253 #endif /* not NO_ADDSUB_Q */
256 /* Adding negative number is faster on the 68040. */
257 /* asm_fprintf() cannot handle %. */
259 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
261 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
267 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
269 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
275 /* asm_fprintf() cannot handle %. */
277 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
279 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
282 if (dwarf2out_do_frame ())
284 cfa_store_offset
+= fsize
;
285 cfa_offset
= cfa_store_offset
;
286 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
289 #ifdef SUPPORT_SUN_FPA
290 for (regno
= 24; regno
< 56; regno
++)
291 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
294 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
297 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
300 if (dwarf2out_do_frame ())
302 char *l
= dwarf2out_cfi_label ();
304 cfa_store_offset
+= 8;
305 if (! frame_pointer_needed
)
307 cfa_offset
= cfa_store_offset
;
308 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
310 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
316 for (regno
= 16; regno
< 24; regno
++)
317 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
319 mask
|= 1 << (regno
- 16);
322 if ((mask
& 0xff) != 0)
325 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
327 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
329 if (dwarf2out_do_frame ())
331 char *l
= (char *) dwarf2out_cfi_label ();
334 cfa_store_offset
+= num_saved_regs
* 12;
335 if (! frame_pointer_needed
)
337 cfa_offset
= cfa_store_offset
;
338 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
340 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
341 if (mask
& (1 << (regno
- 16)))
342 dwarf2out_reg_save (l
, regno
,
343 -cfa_store_offset
+ n_regs
++ * 12);
349 for (regno
= 0; regno
< 16; regno
++)
350 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
352 mask
|= 1 << (15 - regno
);
355 if (frame_pointer_needed
)
357 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
364 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
366 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
369 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
373 if (num_saved_regs
<= 2)
375 /* Store each separately in the same order moveml uses.
376 Using two movel instructions instead of a single moveml
377 is about 15% faster for the 68020 and 68030 at no expense
382 /* Undo the work from above. */
383 for (i
= 0; i
< 16; i
++)
388 "\t%Omove.l %s,-(%Rsp)\n",
390 "\tmovel %s,%Rsp@-\n",
393 if (dwarf2out_do_frame ())
395 char *l
= (char *) dwarf2out_cfi_label ();
397 cfa_store_offset
+= 4;
398 if (! frame_pointer_needed
)
400 cfa_offset
= cfa_store_offset
;
401 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
403 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
411 /* The coldfire does not support the predecrement form of the
412 movml instruction, so we must adjust the stack pointer and
413 then use the plain address register indirect mode. We also
414 have to invert the register save mask to use the new mode.
416 FIXME: if num_saved_regs was calculated earlier, we could
417 combine the stack pointer adjustment with any adjustment
418 done when the initial stack frame is created. This would
419 save an instruction */
424 for (i
= 0; i
< 16; i
++)
426 newmask
|= (1 << (15-i
));
429 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
430 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
432 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
433 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
439 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
441 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
444 if (dwarf2out_do_frame ())
446 char *l
= (char *) dwarf2out_cfi_label ();
449 cfa_store_offset
+= num_saved_regs
* 4;
450 if (! frame_pointer_needed
)
452 cfa_offset
= cfa_store_offset
;
453 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
455 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
456 if (mask
& (1 << (15 - regno
)))
457 dwarf2out_reg_save (l
, regno
,
458 -cfa_store_offset
+ n_regs
++ * 4);
461 if (flag_pic
&& current_function_uses_pic_offset_table
)
464 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
465 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
467 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
468 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
469 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
470 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
471 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
476 /* Return true if this function's epilogue can be output as RTL. */
483 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
486 /* Copied from output_function_epilogue (). We should probably create a
487 separate layout routine to perform the common work. */
489 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
490 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
496 /* This function generates the assembly code for function exit,
497 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
499 The function epilogue should not depend on the current stack pointer!
500 It should use the frame pointer only, if there is a frame pointer.
501 This is mandatory because of alloca; we also take advantage of it to
502 omit stack adjustments before returning. */
505 output_function_epilogue (stream
, size
)
510 register int mask
, fmask
;
512 int offset
, foffset
, fpoffset
;
513 extern char call_used_regs
[];
514 int fsize
= (size
+ 3) & -4;
516 rtx insn
= get_last_insn ();
517 int restore_from_sp
= 0;
519 /* If the last insn was a BARRIER, we don't have to write any code. */
520 if (GET_CODE (insn
) == NOTE
)
521 insn
= prev_nonnote_insn (insn
);
522 if (insn
&& GET_CODE (insn
) == BARRIER
)
524 /* Output just a no-op so that debuggers don't get confused
525 about which function the pc is in at this address. */
526 asm_fprintf (stream
, "\tnop\n");
530 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
531 if (profile_block_flag
== 2)
533 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
537 #ifdef FUNCTION_EXTRA_EPILOGUE
538 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
540 nregs
= 0; fmask
= 0; fpoffset
= 0;
541 #ifdef SUPPORT_SUN_FPA
542 for (regno
= 24 ; regno
< 56 ; regno
++)
543 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
545 fpoffset
= nregs
* 8;
550 for (regno
= 16; regno
< 24; regno
++)
551 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
554 fmask
|= 1 << (23 - regno
);
557 foffset
= fpoffset
+ nregs
* 12;
559 if (frame_pointer_needed
)
560 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
561 for (regno
= 0; regno
< 16; regno
++)
562 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
567 offset
= foffset
+ nregs
* 4;
568 /* FIXME : leaf_function_p below is too strong.
569 What we really need to know there is if there could be pending
570 stack adjustment needed at that point. */
571 restore_from_sp
= ! frame_pointer_needed
572 || (! current_function_calls_alloca
&& leaf_function_p ());
573 if (offset
+ fsize
>= 0x8000
575 && (mask
|| fmask
|| fpoffset
))
578 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
580 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
584 if (TARGET_5200
|| nregs
<= 2)
586 /* Restore each separately in the same order moveml does.
587 Using two movel instructions instead of a single moveml
588 is about 15% faster for the 68020 and 68030 at no expense
593 /* Undo the work from above. */
594 for (i
= 0; i
< 16; i
++)
600 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
602 reg_names
[FRAME_POINTER_REGNUM
],
605 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
606 reg_names
[FRAME_POINTER_REGNUM
],
607 offset
+ fsize
, reg_names
[i
]);
610 else if (restore_from_sp
)
613 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
616 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
623 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
625 reg_names
[FRAME_POINTER_REGNUM
],
628 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
629 reg_names
[FRAME_POINTER_REGNUM
],
630 offset
+ fsize
, reg_names
[i
]);
641 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
643 reg_names
[FRAME_POINTER_REGNUM
],
646 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
647 reg_names
[FRAME_POINTER_REGNUM
],
648 offset
+ fsize
, mask
);
651 else if (restore_from_sp
)
654 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
656 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
662 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
664 reg_names
[FRAME_POINTER_REGNUM
],
667 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
668 reg_names
[FRAME_POINTER_REGNUM
],
669 offset
+ fsize
, mask
);
678 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
680 reg_names
[FRAME_POINTER_REGNUM
],
683 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
684 reg_names
[FRAME_POINTER_REGNUM
],
685 foffset
+ fsize
, fmask
);
688 else if (restore_from_sp
)
691 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
693 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
699 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
701 reg_names
[FRAME_POINTER_REGNUM
],
704 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
705 reg_names
[FRAME_POINTER_REGNUM
],
706 foffset
+ fsize
, fmask
);
711 for (regno
= 55; regno
>= 24; regno
--)
712 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
717 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
719 reg_names
[FRAME_POINTER_REGNUM
],
722 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
723 reg_names
[FRAME_POINTER_REGNUM
],
724 fpoffset
+ fsize
, reg_names
[regno
]);
727 else if (restore_from_sp
)
730 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
733 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
740 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
742 reg_names
[FRAME_POINTER_REGNUM
],
745 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
746 reg_names
[FRAME_POINTER_REGNUM
],
747 fpoffset
+ fsize
, reg_names
[regno
]);
752 if (frame_pointer_needed
)
753 fprintf (stream
, "\tunlk %s\n",
754 reg_names
[FRAME_POINTER_REGNUM
]);
763 asm_fprintf (stream
, "\taddq.w %0I%d,%Rsp\n", fsize
+ 4);
765 asm_fprintf (stream
, "\taddqw %0I%d,%Rsp\n", fsize
+ 4);
771 asm_fprintf (stream
, "\taddq.l %0I%d,%Rsp\n", fsize
+ 4);
773 asm_fprintf (stream
, "\taddql %0I%d,%Rsp\n", fsize
+ 4);
777 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
779 /* On the CPU32 it is faster to use two addqw instructions to
780 add a small integer (8 < N <= 16) to a register. */
781 /* asm_fprintf() cannot handle %. */
783 asm_fprintf (stream
, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
786 asm_fprintf (stream
, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
791 #endif /* not NO_ADDSUB_Q */
792 if (fsize
+ 4 < 0x8000)
796 /* asm_fprintf() cannot handle %. */
798 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
800 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
806 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
808 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
814 /* asm_fprintf() cannot handle %. */
816 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
818 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
822 if (current_function_pops_args
)
823 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
825 fprintf (stream
, "\trts\n");
828 /* Similar to general_operand, but exclude stack_pointer_rtx. */
831 not_sp_operand (op
, mode
)
833 enum machine_mode mode
;
835 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
838 /* Return TRUE if X is a valid comparison operator for the dbcc
841 Note it rejects floating point comparison operators.
842 (In the future we could use Fdbcc).
844 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
847 valid_dbcc_comparison_p (x
, mode
)
849 enum machine_mode mode ATTRIBUTE_UNUSED
;
851 switch (GET_CODE (x
))
853 case EQ
: case NE
: case GTU
: case LTU
:
857 /* Reject some when CC_NO_OVERFLOW is set. This may be over
859 case GT
: case LT
: case GE
: case LE
:
860 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
866 /* Return non-zero if flags are currently in the 68881 flag register. */
870 /* We could add support for these in the future */
871 return cc_status
.flags
& CC_IN_68881
;
874 /* Output a dbCC; jCC sequence. Note we do not handle the
875 floating point version of this sequence (Fdbcc). We also
876 do not handle alternative conditions when CC_NO_OVERFLOW is
877 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
878 kick those out before we get here. */
881 output_dbcc_and_branch (operands
)
884 switch (GET_CODE (operands
[3]))
888 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
890 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
896 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
898 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
904 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
906 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
912 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
914 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
920 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
922 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
928 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
930 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
936 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
938 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
944 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
946 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
952 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
954 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
960 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
962 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
970 /* If the decrement is to be done in SImode, then we have
971 to compensate for the fact that dbcc decrements in HImode. */
972 switch (GET_MODE (operands
[0]))
976 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
978 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
991 output_scc_di(op
, operand1
, operand2
, dest
)
998 enum rtx_code op_code
= GET_CODE (op
);
1000 /* This does not produce a usefull cc. */
1003 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1004 below. Swap the operands and change the op if these requirements
1005 are not fulfilled. */
1006 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1010 operand1
= operand2
;
1012 op_code
= swap_condition (op_code
);
1014 loperands
[0] = operand1
;
1015 if (GET_CODE (operand1
) == REG
)
1016 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1018 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1019 if (operand2
!= const0_rtx
)
1021 loperands
[2] = operand2
;
1022 if (GET_CODE (operand2
) == REG
)
1023 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1025 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1027 loperands
[4] = gen_label_rtx();
1028 if (operand2
!= const0_rtx
)
1031 #ifdef SGS_CMP_ORDER
1032 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1034 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1037 #ifdef SGS_CMP_ORDER
1038 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1040 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1046 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1047 output_asm_insn ("tst%.l %0", loperands
);
1050 #ifdef SGS_CMP_ORDER
1051 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1053 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1058 output_asm_insn ("jbne %l4", loperands
);
1060 output_asm_insn ("jne %l4", loperands
);
1063 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1064 output_asm_insn ("tst%.l %1", loperands
);
1067 #ifdef SGS_CMP_ORDER
1068 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1070 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1075 loperands
[5] = dest
;
1080 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1081 CODE_LABEL_NUMBER (loperands
[4]));
1082 output_asm_insn ("seq %5", loperands
);
1086 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1087 CODE_LABEL_NUMBER (loperands
[4]));
1088 output_asm_insn ("sne %5", loperands
);
1092 loperands
[6] = gen_label_rtx();
1094 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1096 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1098 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1099 CODE_LABEL_NUMBER (loperands
[4]));
1100 output_asm_insn ("sgt %5", loperands
);
1101 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1102 CODE_LABEL_NUMBER (loperands
[6]));
1106 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1107 CODE_LABEL_NUMBER (loperands
[4]));
1108 output_asm_insn ("shi %5", loperands
);
1112 loperands
[6] = gen_label_rtx();
1114 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1116 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1118 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1119 CODE_LABEL_NUMBER (loperands
[4]));
1120 output_asm_insn ("slt %5", loperands
);
1121 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1122 CODE_LABEL_NUMBER (loperands
[6]));
1126 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1127 CODE_LABEL_NUMBER (loperands
[4]));
1128 output_asm_insn ("scs %5", loperands
);
1132 loperands
[6] = gen_label_rtx();
1134 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1136 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1138 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1139 CODE_LABEL_NUMBER (loperands
[4]));
1140 output_asm_insn ("sge %5", loperands
);
1141 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1142 CODE_LABEL_NUMBER (loperands
[6]));
1146 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1147 CODE_LABEL_NUMBER (loperands
[4]));
1148 output_asm_insn ("scc %5", loperands
);
1152 loperands
[6] = gen_label_rtx();
1154 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1156 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1158 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1159 CODE_LABEL_NUMBER (loperands
[4]));
1160 output_asm_insn ("sle %5", loperands
);
1161 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1162 CODE_LABEL_NUMBER (loperands
[6]));
1166 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1167 CODE_LABEL_NUMBER (loperands
[4]));
1168 output_asm_insn ("sls %5", loperands
);
1178 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1180 rtx countop
, dataop
;
1184 operands
[0] = countop
;
1185 operands
[1] = dataop
;
1187 if (GET_CODE (countop
) == CONST_INT
)
1189 register int count
= INTVAL (countop
);
1190 /* If COUNT is bigger than size of storage unit in use,
1191 advance to the containing unit of same size. */
1192 if (count
> signpos
)
1194 int offset
= (count
& ~signpos
) / 8;
1195 count
= count
& signpos
;
1196 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1198 if (count
== signpos
)
1199 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1201 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1203 /* These three statements used to use next_insns_test_no...
1204 but it appears that this should do the same job. */
1206 && next_insn_tests_no_inequality (insn
))
1209 && next_insn_tests_no_inequality (insn
))
1212 && next_insn_tests_no_inequality (insn
))
1215 cc_status
.flags
= CC_NOT_NEGATIVE
;
1217 return "btst %0,%1";
1220 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1221 reference and a constant. */
1224 symbolic_operand (op
, mode
)
1226 enum machine_mode mode ATTRIBUTE_UNUSED
;
1228 switch (GET_CODE (op
))
1236 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1237 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1238 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1240 #if 0 /* Deleted, with corresponding change in m68k.h,
1241 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1243 return GET_MODE (op
) == mode
;
1251 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1254 extend_operator(x
, mode
)
1256 enum machine_mode mode
;
1258 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1260 switch (GET_CODE(x
))
1271 /* Legitimize PIC addresses. If the address is already
1272 position-independent, we return ORIG. Newly generated
1273 position-independent addresses go to REG. If we need more
1274 than one register, we lose.
1276 An address is legitimized by making an indirect reference
1277 through the Global Offset Table with the name of the symbol
1280 The assembler and linker are responsible for placing the
1281 address of the symbol in the GOT. The function prologue
1282 is responsible for initializing a5 to the starting address
1285 The assembler is also responsible for translating a symbol name
1286 into a constant displacement from the start of the GOT.
1288 A quick example may make things a little clearer:
1290 When not generating PIC code to store the value 12345 into _foo
1291 we would generate the following code:
1295 When generating PIC two transformations are made. First, the compiler
1296 loads the address of foo into a register. So the first transformation makes:
1301 The code in movsi will intercept the lea instruction and call this
1302 routine which will transform the instructions into:
1304 movel a5@(_foo:w), a0
1308 That (in a nutshell) is how *all* symbol and label references are
1312 legitimize_pic_address (orig
, mode
, reg
)
1314 enum machine_mode mode ATTRIBUTE_UNUSED
;
1318 /* First handle a simple SYMBOL_REF or LABEL_REF */
1319 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1324 pic_ref
= gen_rtx_MEM (Pmode
,
1325 gen_rtx_PLUS (Pmode
,
1326 pic_offset_table_rtx
, orig
));
1327 current_function_uses_pic_offset_table
= 1;
1328 if (reload_in_progress
)
1329 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1330 RTX_UNCHANGING_P (pic_ref
) = 1;
1331 emit_move_insn (reg
, pic_ref
);
1334 else if (GET_CODE (orig
) == CONST
)
1338 /* Make sure this is CONST has not already been legitimized */
1339 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1340 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1346 /* legitimize both operands of the PLUS */
1347 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1349 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1350 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1351 base
== reg
? 0 : reg
);
1355 if (GET_CODE (orig
) == CONST_INT
)
1356 return plus_constant_for_output (base
, INTVAL (orig
));
1357 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1358 /* Likewise, should we set special REG_NOTEs here? */
1364 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1366 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1369 const_method (constant
)
1375 i
= INTVAL (constant
);
1379 /* The Coldfire doesn't have byte or word operations. */
1380 /* FIXME: This may not be useful for the m68060 either */
1383 /* if -256 < N < 256 but N is not in range for a moveq
1384 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1385 if (USE_MOVQ (i
^ 0xff))
1387 /* Likewise, try with not.w */
1388 if (USE_MOVQ (i
^ 0xffff))
1390 /* This is the only value where neg.w is useful */
1393 /* Try also with swap */
1395 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1398 /* Otherwise, use move.l */
1403 const_int_cost (constant
)
1406 switch (const_method (constant
))
1409 /* Constants between -128 and 127 are cheap due to moveq */
1415 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1425 output_move_const_into_data_reg (operands
)
1430 i
= INTVAL (operands
[1]);
1431 switch (const_method (operands
[1]))
1434 #if defined (MOTOROLA) && !defined (CRDS)
1435 return "moveq%.l %1,%0";
1437 return "moveq %1,%0";
1440 operands
[1] = GEN_INT (i
^ 0xff);
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %1,%0\n\tnot%.b %0";
1444 return "moveq %1,%0\n\tnot%.b %0";
1447 operands
[1] = GEN_INT (i
^ 0xffff);
1448 #if defined (MOTOROLA) && !defined (CRDS)
1449 return "moveq%.l %1,%0\n\tnot%.w %0";
1451 return "moveq %1,%0\n\tnot%.w %0";
1454 #if defined (MOTOROLA) && !defined (CRDS)
1455 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1457 return "moveq %#-128,%0\n\tneg%.w %0";
1463 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1464 #if defined (MOTOROLA) && !defined (CRDS)
1465 return "moveq%.l %1,%0\n\tswap %0";
1467 return "moveq %1,%0\n\tswap %0";
1471 return "move%.l %1,%0";
1478 output_move_simode_const (operands
)
1481 if (operands
[1] == const0_rtx
1482 && (DATA_REG_P (operands
[0])
1483 || GET_CODE (operands
[0]) == MEM
)
1484 /* clr insns on 68000 read before writing.
1485 This isn't so on the 68010, but we have no TARGET_68010. */
1486 && ((TARGET_68020
|| TARGET_5200
)
1487 || !(GET_CODE (operands
[0]) == MEM
1488 && MEM_VOLATILE_P (operands
[0]))))
1490 else if (operands
[1] == const0_rtx
1491 && ADDRESS_REG_P (operands
[0]))
1492 return "sub%.l %0,%0";
1493 else if (DATA_REG_P (operands
[0]))
1494 return output_move_const_into_data_reg (operands
);
1495 else if (ADDRESS_REG_P (operands
[0])
1496 && INTVAL (operands
[1]) < 0x8000
1497 && INTVAL (operands
[1]) >= -0x8000)
1498 return "move%.w %1,%0";
1499 else if (GET_CODE (operands
[0]) == MEM
1500 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1501 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1502 && INTVAL (operands
[1]) < 0x8000
1503 && INTVAL (operands
[1]) >= -0x8000)
1505 return "move%.l %1,%0";
1509 output_move_simode (operands
)
1512 if (GET_CODE (operands
[1]) == CONST_INT
)
1513 return output_move_simode_const (operands
);
1514 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1515 || GET_CODE (operands
[1]) == CONST
)
1516 && push_operand (operands
[0], SImode
))
1518 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1519 || GET_CODE (operands
[1]) == CONST
)
1520 && ADDRESS_REG_P (operands
[0]))
1521 return "lea %a1,%0";
1522 return "move%.l %1,%0";
1526 output_move_himode (operands
)
1529 if (GET_CODE (operands
[1]) == CONST_INT
)
1531 if (operands
[1] == const0_rtx
1532 && (DATA_REG_P (operands
[0])
1533 || GET_CODE (operands
[0]) == MEM
)
1534 /* clr insns on 68000 read before writing.
1535 This isn't so on the 68010, but we have no TARGET_68010. */
1536 && ((TARGET_68020
|| TARGET_5200
)
1537 || !(GET_CODE (operands
[0]) == MEM
1538 && MEM_VOLATILE_P (operands
[0]))))
1540 else if (operands
[1] == const0_rtx
1541 && ADDRESS_REG_P (operands
[0]))
1542 return "sub%.l %0,%0";
1543 else if (DATA_REG_P (operands
[0])
1544 && INTVAL (operands
[1]) < 128
1545 && INTVAL (operands
[1]) >= -128)
1547 #if defined(MOTOROLA) && !defined(CRDS)
1548 return "moveq%.l %1,%0";
1550 return "moveq %1,%0";
1553 else if (INTVAL (operands
[1]) < 0x8000
1554 && INTVAL (operands
[1]) >= -0x8000)
1555 return "move%.w %1,%0";
1557 else if (CONSTANT_P (operands
[1]))
1558 return "move%.l %1,%0";
1560 /* Recognize the insn before a tablejump, one that refers
1561 to a table of offsets. Such an insn will need to refer
1562 to a label on the insn. So output one. Use the label-number
1563 of the table of offsets to generate this label. This code,
1564 and similar code below, assumes that there will be at most one
1565 reference to each table. */
1566 if (GET_CODE (operands
[1]) == MEM
1567 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1568 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1569 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1571 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1572 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1574 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1575 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1577 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1578 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1579 #endif /* not SGS */
1580 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1581 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1582 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1583 #ifdef SGS_SWITCH_TABLES
1584 /* Set flag saying we need to define the symbol
1585 LD%n (with value L%n-LI%n) at the end of the switch table. */
1586 switch_table_difference_label_flag
= 1;
1587 #endif /* SGS_SWITCH_TABLES */
1588 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1590 #endif /* SGS_NO_LI */
1591 return "move%.w %1,%0";
1595 output_move_qimode (operands
)
1600 /* This is probably useless, since it loses for pushing a struct
1601 of several bytes a byte at a time. */
1602 /* 68k family always modifies the stack pointer by at least 2, even for
1603 byte pushes. The 5200 (coldfire) does not do this. */
1604 if (GET_CODE (operands
[0]) == MEM
1605 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1606 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1607 && ! ADDRESS_REG_P (operands
[1])
1610 xoperands
[1] = operands
[1];
1612 = gen_rtx_MEM (QImode
,
1613 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1614 /* Just pushing a byte puts it in the high byte of the halfword. */
1615 /* We must put it in the low-order, high-numbered byte. */
1616 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1618 xoperands
[3] = stack_pointer_rtx
;
1620 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1622 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1626 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1630 /* clr and st insns on 68000 read before writing.
1631 This isn't so on the 68010, but we have no TARGET_68010. */
1632 if (!ADDRESS_REG_P (operands
[0])
1633 && ((TARGET_68020
|| TARGET_5200
)
1634 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1636 if (operands
[1] == const0_rtx
)
1638 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1639 && GET_CODE (operands
[1]) == CONST_INT
1640 && (INTVAL (operands
[1]) & 255) == 255)
1646 if (GET_CODE (operands
[1]) == CONST_INT
1647 && DATA_REG_P (operands
[0])
1648 && INTVAL (operands
[1]) < 128
1649 && INTVAL (operands
[1]) >= -128)
1651 #if defined(MOTOROLA) && !defined(CRDS)
1652 return "moveq%.l %1,%0";
1654 return "moveq %1,%0";
1657 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1658 return "sub%.l %0,%0";
1659 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1660 return "move%.l %1,%0";
1661 /* 68k family (including the 5200 coldfire) does not support byte moves to
1662 from address registers. */
1663 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1664 return "move%.w %1,%0";
1665 return "move%.b %1,%0";
1669 output_move_stricthi (operands
)
1672 if (operands
[1] == const0_rtx
1673 /* clr insns on 68000 read before writing.
1674 This isn't so on the 68010, but we have no TARGET_68010. */
1675 && ((TARGET_68020
|| TARGET_5200
)
1676 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1678 return "move%.w %1,%0";
1682 output_move_strictqi (operands
)
1685 if (operands
[1] == const0_rtx
1686 /* clr insns on 68000 read before writing.
1687 This isn't so on the 68010, but we have no TARGET_68010. */
1688 && ((TARGET_68020
|| TARGET_5200
)
1689 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1691 return "move%.b %1,%0";
1694 /* Return the best assembler insn template
1695 for moving operands[1] into operands[0] as a fullword. */
1698 singlemove_string (operands
)
1701 #ifdef SUPPORT_SUN_FPA
1702 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1703 return "fpmoves %1,%0";
1705 if (GET_CODE (operands
[1]) == CONST_INT
)
1706 return output_move_simode_const (operands
);
1707 return "move%.l %1,%0";
1711 /* Output assembler code to perform a doubleword move insn
1712 with operands OPERANDS. */
1715 output_move_double (operands
)
1720 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1725 rtx addreg0
= 0, addreg1
= 0;
1726 int dest_overlapped_low
= 0;
1727 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1732 /* First classify both operands. */
1734 if (REG_P (operands
[0]))
1736 else if (offsettable_memref_p (operands
[0]))
1738 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1740 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1742 else if (GET_CODE (operands
[0]) == MEM
)
1747 if (REG_P (operands
[1]))
1749 else if (CONSTANT_P (operands
[1]))
1751 else if (offsettable_memref_p (operands
[1]))
1753 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1755 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1757 else if (GET_CODE (operands
[1]) == MEM
)
1762 /* Check for the cases that the operand constraints are not
1763 supposed to allow to happen. Abort if we get one,
1764 because generating code for these cases is painful. */
1766 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1769 /* If one operand is decrementing and one is incrementing
1770 decrement the former register explicitly
1771 and change that operand into ordinary indexing. */
1773 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1775 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1777 output_asm_insn ("sub%.l %#12,%0", operands
);
1779 output_asm_insn ("subq%.l %#8,%0", operands
);
1780 if (GET_MODE (operands
[1]) == XFmode
)
1781 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1782 else if (GET_MODE (operands
[0]) == DFmode
)
1783 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1785 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1788 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1790 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1792 output_asm_insn ("sub%.l %#12,%1", operands
);
1794 output_asm_insn ("subq%.l %#8,%1", operands
);
1795 if (GET_MODE (operands
[1]) == XFmode
)
1796 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1797 else if (GET_MODE (operands
[1]) == DFmode
)
1798 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1800 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1804 /* If an operand is an unoffsettable memory ref, find a register
1805 we can increment temporarily to make it refer to the second word. */
1807 if (optype0
== MEMOP
)
1808 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1810 if (optype1
== MEMOP
)
1811 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1813 /* Ok, we can do one word at a time.
1814 Normally we do the low-numbered word first,
1815 but if either operand is autodecrementing then we
1816 do the high-numbered word first.
1818 In either case, set up in LATEHALF the operands to use
1819 for the high-numbered word and in some cases alter the
1820 operands in OPERANDS to be suitable for the low-numbered word. */
1824 if (optype0
== REGOP
)
1826 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1827 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1829 else if (optype0
== OFFSOP
)
1831 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1832 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1836 middlehalf
[0] = operands
[0];
1837 latehalf
[0] = operands
[0];
1840 if (optype1
== REGOP
)
1842 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1843 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1845 else if (optype1
== OFFSOP
)
1847 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1848 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1850 else if (optype1
== CNSTOP
)
1852 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1857 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1858 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1859 operands
[1] = GEN_INT (l
[0]);
1860 middlehalf
[1] = GEN_INT (l
[1]);
1861 latehalf
[1] = GEN_INT (l
[2]);
1863 else if (CONSTANT_P (operands
[1]))
1865 /* actually, no non-CONST_DOUBLE constant should ever
1868 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1869 latehalf
[1] = constm1_rtx
;
1871 latehalf
[1] = const0_rtx
;
1876 middlehalf
[1] = operands
[1];
1877 latehalf
[1] = operands
[1];
1881 /* size is not 12: */
1883 if (optype0
== REGOP
)
1884 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1885 else if (optype0
== OFFSOP
)
1886 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1888 latehalf
[0] = operands
[0];
1890 if (optype1
== REGOP
)
1891 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1892 else if (optype1
== OFFSOP
)
1893 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1894 else if (optype1
== CNSTOP
)
1895 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1897 latehalf
[1] = operands
[1];
1900 /* If insn is effectively movd N(sp),-(sp) then we will do the
1901 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1902 for the low word as well, to compensate for the first decrement of sp. */
1903 if (optype0
== PUSHOP
1904 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1905 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1906 operands
[1] = middlehalf
[1] = latehalf
[1];
1908 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1909 if the upper part of reg N does not appear in the MEM, arrange to
1910 emit the move late-half first. Otherwise, compute the MEM address
1911 into the upper part of N and use that as a pointer to the memory
1913 if (optype0
== REGOP
1914 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1916 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1918 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1919 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1921 /* If both halves of dest are used in the src memory address,
1922 compute the address into latehalf of dest.
1923 Note that this can't happen if the dest is two data regs. */
1925 xops
[0] = latehalf
[0];
1926 xops
[1] = XEXP (operands
[1], 0);
1927 output_asm_insn ("lea %a1,%0", xops
);
1928 if( GET_MODE (operands
[1]) == XFmode
)
1930 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1931 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1932 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1936 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1937 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1941 && reg_overlap_mentioned_p (middlehalf
[0],
1942 XEXP (operands
[1], 0)))
1944 /* Check for two regs used by both source and dest.
1945 Note that this can't happen if the dest is all data regs.
1946 It can happen if the dest is d6, d7, a0.
1947 But in that case, latehalf is an addr reg, so
1948 the code at compadr does ok. */
1950 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1951 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1954 /* JRV says this can't happen: */
1955 if (addreg0
|| addreg1
)
1958 /* Only the middle reg conflicts; simply put it last. */
1959 output_asm_insn (singlemove_string (operands
), operands
);
1960 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1961 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1964 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1965 /* If the low half of dest is mentioned in the source memory
1966 address, the arrange to emit the move late half first. */
1967 dest_overlapped_low
= 1;
1970 /* If one or both operands autodecrementing,
1971 do the two words, high-numbered first. */
1973 /* Likewise, the first move would clobber the source of the second one,
1974 do them in the other order. This happens only for registers;
1975 such overlap can't happen in memory unless the user explicitly
1976 sets it up, and that is an undefined circumstance. */
1978 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1979 || (optype0
== REGOP
&& optype1
== REGOP
1980 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1981 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1982 || dest_overlapped_low
)
1984 /* Make any unoffsettable addresses point at high-numbered word. */
1988 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1990 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1995 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1997 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2001 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2003 /* Undo the adds we just did. */
2005 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2007 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2011 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2013 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2015 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2018 /* Do low-numbered word. */
2019 return singlemove_string (operands
);
2022 /* Normal case: do the two words, low-numbered first. */
2024 output_asm_insn (singlemove_string (operands
), operands
);
2026 /* Do the middle one of the three words for long double */
2030 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2032 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2034 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2037 /* Make any unoffsettable addresses point at high-numbered word. */
2039 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2041 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2044 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2046 /* Undo the adds we just did. */
2050 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2052 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2057 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2059 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2065 /* Return a REG that occurs in ADDR with coefficient 1.
2066 ADDR can be effectively incremented by incrementing REG. */
2069 find_addr_reg (addr
)
2072 while (GET_CODE (addr
) == PLUS
)
2074 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2075 addr
= XEXP (addr
, 0);
2076 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2077 addr
= XEXP (addr
, 1);
2078 else if (CONSTANT_P (XEXP (addr
, 0)))
2079 addr
= XEXP (addr
, 1);
2080 else if (CONSTANT_P (XEXP (addr
, 1)))
2081 addr
= XEXP (addr
, 0);
2085 if (GET_CODE (addr
) == REG
)
2090 /* Output assembler code to perform a 32 bit 3 operand add. */
2093 output_addsi3 (operands
)
2096 if (! operands_match_p (operands
[0], operands
[1]))
2098 if (!ADDRESS_REG_P (operands
[1]))
2100 rtx tmp
= operands
[1];
2102 operands
[1] = operands
[2];
2106 /* These insns can result from reloads to access
2107 stack slots over 64k from the frame pointer. */
2108 if (GET_CODE (operands
[2]) == CONST_INT
2109 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2110 return "move%.l %2,%0\n\tadd%.l %1,%0";
2112 if (GET_CODE (operands
[2]) == REG
)
2113 return "lea 0(%1,%2.l),%0";
2115 return "lea %c2(%1),%0";
2118 if (GET_CODE (operands
[2]) == REG
)
2119 return "lea (%1,%2.l),%0";
2121 return "lea (%c2,%1),%0";
2122 #else /* not MOTOROLA (MIT syntax) */
2123 if (GET_CODE (operands
[2]) == REG
)
2124 return "lea %1@(0,%2:l),%0";
2126 return "lea %1@(%c2),%0";
2127 #endif /* not MOTOROLA */
2128 #endif /* not SGS */
2130 if (GET_CODE (operands
[2]) == CONST_INT
)
2133 if (INTVAL (operands
[2]) > 0
2134 && INTVAL (operands
[2]) <= 8)
2135 return "addq%.l %2,%0";
2136 if (INTVAL (operands
[2]) < 0
2137 && INTVAL (operands
[2]) >= -8)
2139 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2140 return "subq%.l %2,%0";
2142 /* On the CPU32 it is faster to use two addql instructions to
2143 add a small integer (8 < N <= 16) to a register.
2144 Likewise for subql. */
2145 if (TARGET_CPU32
&& REG_P (operands
[0]))
2147 if (INTVAL (operands
[2]) > 8
2148 && INTVAL (operands
[2]) <= 16)
2150 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2151 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2153 if (INTVAL (operands
[2]) < -8
2154 && INTVAL (operands
[2]) >= -16)
2156 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2157 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2161 if (ADDRESS_REG_P (operands
[0])
2162 && INTVAL (operands
[2]) >= -0x8000
2163 && INTVAL (operands
[2]) < 0x8000)
2166 return "add%.w %2,%0";
2169 return "lea (%c2,%0),%0";
2171 return "lea %0@(%c2),%0";
2175 return "add%.l %2,%0";
2178 /* Store in cc_status the expressions that the condition codes will
2179 describe after execution of an instruction whose pattern is EXP.
2180 Do not alter them if the instruction would not alter the cc's. */
2182 /* On the 68000, all the insns to store in an address register fail to
2183 set the cc's. However, in some cases these instructions can make it
2184 possibly invalid to use the saved cc's. In those cases we clear out
2185 some or all of the saved cc's so they won't be used. */
2188 notice_update_cc (exp
, insn
)
2192 /* If the cc is being set from the fpa and the expression is not an
2193 explicit floating point test instruction (which has code to deal with
2194 this), reinit the CC. */
2195 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2196 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2197 && !(GET_CODE (exp
) == PARALLEL
2198 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2199 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2203 else if (GET_CODE (exp
) == SET
)
2205 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2209 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2211 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2212 cc_status
.value1
= 0;
2213 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2214 cc_status
.value2
= 0;
2216 else if (!FP_REG_P (SET_DEST (exp
))
2217 && SET_DEST (exp
) != cc0_rtx
2218 && (FP_REG_P (SET_SRC (exp
))
2219 || GET_CODE (SET_SRC (exp
)) == FIX
2220 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2221 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2225 /* A pair of move insns doesn't produce a useful overall cc. */
2226 else if (!FP_REG_P (SET_DEST (exp
))
2227 && !FP_REG_P (SET_SRC (exp
))
2228 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2229 && (GET_CODE (SET_SRC (exp
)) == REG
2230 || GET_CODE (SET_SRC (exp
)) == MEM
2231 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2235 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2239 else if (XEXP (exp
, 0) != pc_rtx
)
2241 cc_status
.flags
= 0;
2242 cc_status
.value1
= XEXP (exp
, 0);
2243 cc_status
.value2
= XEXP (exp
, 1);
2246 else if (GET_CODE (exp
) == PARALLEL
2247 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2249 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2251 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2253 cc_status
.flags
= 0;
2254 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2255 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2260 if (cc_status
.value2
!= 0
2261 && ADDRESS_REG_P (cc_status
.value2
)
2262 && GET_MODE (cc_status
.value2
) == QImode
)
2264 if (cc_status
.value2
!= 0
2265 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2266 switch (GET_CODE (cc_status
.value2
))
2268 case PLUS
: case MINUS
: case MULT
:
2269 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2270 #if 0 /* These instructions always clear the overflow bit */
2271 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2272 case ROTATE
: case ROTATERT
:
2274 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2275 cc_status
.flags
|= CC_NO_OVERFLOW
;
2278 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2279 ends with a move insn moving r2 in r2's mode.
2280 Thus, the cc's are set for r2.
2281 This can set N bit spuriously. */
2282 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2287 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2289 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2290 cc_status
.value2
= 0;
2291 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2292 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2293 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2294 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2295 cc_status
.flags
= CC_IN_68881
;
2299 output_move_const_double (operands
)
2302 #ifdef SUPPORT_SUN_FPA
2303 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2305 int code
= standard_sun_fpa_constant_p (operands
[1]);
2309 static char buf
[40];
2311 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2314 return "fpmove%.d %1,%0";
2319 int code
= standard_68881_constant_p (operands
[1]);
2323 static char buf
[40];
2325 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2328 return "fmove%.d %1,%0";
2333 output_move_const_single (operands
)
2336 #ifdef SUPPORT_SUN_FPA
2339 int code
= standard_sun_fpa_constant_p (operands
[1]);
2343 static char buf
[40];
2345 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2348 return "fpmove%.s %1,%0";
2351 #endif /* defined SUPPORT_SUN_FPA */
2353 int code
= standard_68881_constant_p (operands
[1]);
2357 static char buf
[40];
2359 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2362 return "fmove%.s %f1,%0";
2366 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2367 from the "fmovecr" instruction.
2368 The value, anded with 0xff, gives the code to use in fmovecr
2369 to get the desired constant. */
2371 /* This code has been fixed for cross-compilation. */
2373 static int inited_68881_table
= 0;
2375 char *strings_68881
[7] = {
2385 int codes_68881
[7] = {
2395 REAL_VALUE_TYPE values_68881
[7];
2397 /* Set up values_68881 array by converting the decimal values
2398 strings_68881 to binary. */
2405 enum machine_mode mode
;
2408 for (i
= 0; i
< 7; i
++)
2412 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2413 values_68881
[i
] = r
;
2415 inited_68881_table
= 1;
2419 standard_68881_constant_p (x
)
2425 #ifdef NO_ASM_FMOVECR
2429 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2430 used at all on those chips. */
2431 if (TARGET_68040
|| TARGET_68060
)
2434 #ifndef REAL_ARITHMETIC
2435 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2436 if (! flag_pretend_float
)
2441 if (! inited_68881_table
)
2442 init_68881_table ();
2444 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2446 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2448 for (i
= 0; i
< 6; i
++)
2450 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2451 return (codes_68881
[i
]);
2454 if (GET_MODE (x
) == SFmode
)
2457 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2458 return (codes_68881
[6]);
2460 /* larger powers of ten in the constants ram are not used
2461 because they are not equal to a `double' C constant. */
2465 /* If X is a floating-point constant, return the logarithm of X base 2,
2466 or 0 if X is not a power of 2. */
2469 floating_exact_log2 (x
)
2472 REAL_VALUE_TYPE r
, r1
;
2475 #ifndef REAL_ARITHMETIC
2476 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2477 if (! flag_pretend_float
)
2482 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2484 if (REAL_VALUES_LESS (r
, dconst0
))
2489 while (REAL_VALUES_LESS (r1
, r
))
2491 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2492 if (REAL_VALUES_EQUAL (r1
, r
))
2499 #ifdef SUPPORT_SUN_FPA
2500 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2501 from the Sun FPA's constant RAM.
2502 The value returned, anded with 0x1ff, gives the code to use in fpmove
2503 to get the desired constant. */
2505 static int inited_FPA_table
= 0;
2507 char *strings_FPA
[38] = {
2508 /* small rationals */
2521 /* Decimal equivalents of double precision values */
2522 "2.718281828459045091", /* D_E */
2523 "6.283185307179586477", /* 2 pi */
2524 "3.141592653589793116", /* D_PI */
2525 "1.570796326794896619", /* pi/2 */
2526 "1.414213562373095145", /* D_SQRT2 */
2527 "0.7071067811865475244", /* 1/sqrt(2) */
2528 "-1.570796326794896619", /* -pi/2 */
2529 "1.442695040888963387", /* D_LOG2ofE */
2530 "3.321928024887362182", /* D_LOG2of10 */
2531 "0.6931471805599452862", /* D_LOGEof2 */
2532 "2.302585092994045901", /* D_LOGEof10 */
2533 "0.3010299956639811980", /* D_LOG10of2 */
2534 "0.4342944819032518167", /* D_LOG10ofE */
2535 /* Decimal equivalents of single precision values */
2536 "2.718281745910644531", /* S_E */
2537 "6.283185307179586477", /* 2 pi */
2538 "3.141592741012573242", /* S_PI */
2539 "1.570796326794896619", /* pi/2 */
2540 "1.414213538169860840", /* S_SQRT2 */
2541 "0.7071067811865475244", /* 1/sqrt(2) */
2542 "-1.570796326794896619", /* -pi/2 */
2543 "1.442695021629333496", /* S_LOG2ofE */
2544 "3.321928024291992188", /* S_LOG2of10 */
2545 "0.6931471824645996094", /* S_LOGEof2 */
2546 "2.302585124969482442", /* S_LOGEof10 */
2547 "0.3010300099849700928", /* S_LOG10of2 */
2548 "0.4342944920063018799", /* S_LOG10ofE */
2552 int codes_FPA
[38] = {
2553 /* small rationals */
2566 /* double precision */
2580 /* single precision */
2596 REAL_VALUE_TYPE values_FPA
[38];
2598 /* This code has been fixed for cross-compilation. */
2603 enum machine_mode mode
;
2608 for (i
= 0; i
< 38; i
++)
2612 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2615 inited_FPA_table
= 1;
2620 standard_sun_fpa_constant_p (x
)
2626 #ifndef REAL_ARITHMETIC
2627 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2628 if (! flag_pretend_float
)
2633 if (! inited_FPA_table
)
2636 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2638 for (i
=0; i
<12; i
++)
2640 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2641 return (codes_FPA
[i
]);
2644 if (GET_MODE (x
) == SFmode
)
2646 for (i
=25; i
<38; i
++)
2648 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2649 return (codes_FPA
[i
]);
2654 for (i
=12; i
<25; i
++)
2656 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2657 return (codes_FPA
[i
]);
2662 #endif /* define SUPPORT_SUN_FPA */
2664 /* A C compound statement to output to stdio stream STREAM the
2665 assembler syntax for an instruction operand X. X is an RTL
2668 CODE is a value that can be used to specify one of several ways
2669 of printing the operand. It is used when identical operands
2670 must be printed differently depending on the context. CODE
2671 comes from the `%' specification that was used to request
2672 printing of the operand. If the specification was just `%DIGIT'
2673 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2674 is the ASCII code for LTR.
2676 If X is a register, this macro should print the register's name.
2677 The names can be found in an array `reg_names' whose type is
2678 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2680 When the machine description has a specification `%PUNCT' (a `%'
2681 followed by a punctuation character), this macro is called with
2682 a null pointer for X and the punctuation character for CODE.
2684 The m68k specific codes are:
2686 '.' for dot needed in Motorola-style opcode names.
2687 '-' for an operand pushing on the stack:
2688 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2689 '+' for an operand pushing on the stack:
2690 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2691 '@' for a reference to the top word on the stack:
2692 sp@, (sp) or (%sp) depending on the style of syntax.
2693 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2694 but & in SGS syntax, $ in CRDS/UNOS syntax).
2695 '!' for the cc register (used in an `and to cc' insn).
2696 '$' for the letter `s' in an op code, but only on the 68040.
2697 '&' for the letter `d' in an op code, but only on the 68040.
2698 '/' for register prefix needed by longlong.h.
2700 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2701 'd' to force memory addressing to be absolute, not relative.
2702 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2703 'o' for operands to go directly to output_operand_address (bypassing
2704 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2705 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2706 than directly). Second part of 'y' below.
2707 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2708 or print pair of registers as rx:ry.
2709 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2710 CONST_DOUBLE's as SunFPA constant RAM registers if
2711 possible, so it should not be used except for the SunFPA.
2716 print_operand (file
, op
, letter
)
2717 FILE *file
; /* file to write to */
2718 rtx op
; /* operand to print */
2719 int letter
; /* %<letter> or 0 */
2721 #ifdef SUPPORT_SUN_FPA
2727 #if defined (MOTOROLA) && !defined (CRDS)
2728 asm_fprintf (file
, ".");
2731 else if (letter
== '#')
2733 asm_fprintf (file
, "%0I");
2735 else if (letter
== '-')
2738 asm_fprintf (file
, "-(%Rsp)");
2740 asm_fprintf (file
, "%Rsp@-");
2743 else if (letter
== '+')
2746 asm_fprintf (file
, "(%Rsp)+");
2748 asm_fprintf (file
, "%Rsp@+");
2751 else if (letter
== '@')
2754 asm_fprintf (file
, "(%Rsp)");
2756 asm_fprintf (file
, "%Rsp@");
2759 else if (letter
== '!')
2761 asm_fprintf (file
, "%Rfpcr");
2763 else if (letter
== '$')
2765 if (TARGET_68040_ONLY
)
2767 fprintf (file
, "s");
2770 else if (letter
== '&')
2772 if (TARGET_68040_ONLY
)
2774 fprintf (file
, "d");
2777 else if (letter
== '/')
2779 asm_fprintf (file
, "%R");
2781 else if (letter
== 'o')
2783 /* This is only for direct addresses with TARGET_PCREL */
2784 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2787 output_addr_const (file
, XEXP (op
, 0));
2789 else if (GET_CODE (op
) == REG
)
2791 #ifdef SUPPORT_SUN_FPA
2793 && (letter
== 'y' || letter
== 'x')
2794 && GET_MODE (op
) == DFmode
)
2796 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2797 reg_names
[REGNO (op
)+1]);
2803 /* Print out the second register name of a register pair.
2804 I.e., R (6) => 7. */
2805 fputs (reg_names
[REGNO (op
) + 1], file
);
2807 fputs (reg_names
[REGNO (op
)], file
);
2810 else if (GET_CODE (op
) == MEM
)
2812 output_address (XEXP (op
, 0));
2813 if (letter
== 'd' && ! TARGET_68020
2814 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2815 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2816 && INTVAL (XEXP (op
, 0)) < 0x8000
2817 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2820 fprintf (file
, ".l");
2822 fprintf (file
, ":l");
2826 #ifdef SUPPORT_SUN_FPA
2827 else if ((letter
== 'y' || letter
== 'w')
2828 && GET_CODE (op
) == CONST_DOUBLE
2829 && (i
= standard_sun_fpa_constant_p (op
)))
2831 fprintf (file
, "%%%d", i
& 0x1ff);
2834 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2837 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2838 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2840 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2843 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2844 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2846 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2849 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2850 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2854 /* Use `print_operand_address' instead of `output_addr_const'
2855 to ensure that we print relevant PIC stuff. */
2856 asm_fprintf (file
, "%0I");
2858 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2859 print_operand_address (file
, op
);
2861 output_addr_const (file
, op
);
2866 /* A C compound statement to output to stdio stream STREAM the
2867 assembler syntax for an instruction operand that is a memory
2868 reference whose address is ADDR. ADDR is an RTL expression.
2870 Note that this contains a kludge that knows that the only reason
2871 we have an address (plus (label_ref...) (reg...)) when not generating
2872 PIC code is in the insn before a tablejump, and we know that m68k.md
2873 generates a label LInnn: on such an insn.
2875 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2876 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2878 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2879 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2880 we want. This difference can be accommodated by using an assembler
2881 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2882 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2883 macro. See m68k/sgs.h for an example; for versions without the bug.
2884 Some assemblers refuse all the above solutions. The workaround is to
2885 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2888 They also do not like things like "pea 1.w", so we simple leave off
2889 the .w on small constants.
2891 This routine is responsible for distinguishing between -fpic and -fPIC
2892 style relocations in an address. When generating -fpic code the
2893 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2894 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2896 #ifndef ASM_OUTPUT_CASE_FETCH
2899 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2900 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2902 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2903 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2906 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2907 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2909 #endif /* ASM_OUTPUT_CASE_FETCH */
2912 print_operand_address (file
, addr
)
2916 register rtx reg1
, reg2
, breg
, ireg
;
2919 switch (GET_CODE (addr
))
2923 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2925 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2930 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2932 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2937 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2939 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2943 reg1
= reg2
= ireg
= breg
= offset
= 0;
2944 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2946 offset
= XEXP (addr
, 0);
2947 addr
= XEXP (addr
, 1);
2949 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2951 offset
= XEXP (addr
, 1);
2952 addr
= XEXP (addr
, 0);
2954 if (GET_CODE (addr
) != PLUS
)
2958 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2960 reg1
= XEXP (addr
, 0);
2961 addr
= XEXP (addr
, 1);
2963 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2965 reg1
= XEXP (addr
, 1);
2966 addr
= XEXP (addr
, 0);
2968 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2970 reg1
= XEXP (addr
, 0);
2971 addr
= XEXP (addr
, 1);
2973 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2975 reg1
= XEXP (addr
, 1);
2976 addr
= XEXP (addr
, 0);
2978 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2980 reg1
= XEXP (addr
, 0);
2981 addr
= XEXP (addr
, 1);
2983 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2985 reg1
= XEXP (addr
, 1);
2986 addr
= XEXP (addr
, 0);
2988 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2989 || GET_CODE (addr
) == SIGN_EXTEND
)
3001 #if 0 /* for OLD_INDEXING */
3002 else if (GET_CODE (addr
) == PLUS
)
3004 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3006 reg2
= XEXP (addr
, 0);
3007 addr
= XEXP (addr
, 1);
3009 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3011 reg2
= XEXP (addr
, 1);
3012 addr
= XEXP (addr
, 0);
3024 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3025 || GET_CODE (reg1
) == MULT
))
3026 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3031 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3036 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3037 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3040 if (GET_CODE (ireg
) == MULT
)
3042 scale
= INTVAL (XEXP (ireg
, 1));
3043 ireg
= XEXP (ireg
, 0);
3045 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3047 ASM_OUTPUT_CASE_FETCH (file
,
3048 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3049 reg_names
[REGNO (XEXP (ireg
, 0))]);
3050 fprintf (file
, "w");
3054 ASM_OUTPUT_CASE_FETCH (file
,
3055 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3056 reg_names
[REGNO (ireg
)]);
3057 fprintf (file
, "l");
3062 fprintf (file
, "*%d", scale
);
3064 fprintf (file
, ":%d", scale
);
3070 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3071 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3073 ASM_OUTPUT_CASE_FETCH (file
,
3074 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3075 reg_names
[REGNO (breg
)]);
3076 fprintf (file
, "l)");
3079 if (ireg
!= 0 || breg
!= 0)
3086 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3093 output_addr_const (file
, addr
);
3094 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3096 fprintf (file
, "@GOT");
3098 fprintf (file
, ".w");
3101 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3107 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3110 output_addr_const (file
, addr
);
3111 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3112 fprintf (file
, ":w");
3113 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3114 fprintf (file
, ":l");
3116 if (addr
!= 0 && ireg
!= 0)
3121 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3123 scale
= INTVAL (XEXP (ireg
, 1));
3124 ireg
= XEXP (ireg
, 0);
3126 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3129 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3131 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3137 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3139 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3145 fprintf (file
, "*%d", scale
);
3147 fprintf (file
, ":%d", scale
);
3153 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3154 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3156 ASM_OUTPUT_CASE_FETCH (file
,
3157 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3158 reg_names
[REGNO (reg1
)]);
3159 fprintf (file
, "l)");
3162 /* FALL-THROUGH (is this really what we want?) */
3164 if (GET_CODE (addr
) == CONST_INT
3165 && INTVAL (addr
) < 0x8000
3166 && INTVAL (addr
) >= -0x8000)
3170 /* Many SGS assemblers croak on size specifiers for constants. */
3171 fprintf (file
, "%d", INTVAL (addr
));
3173 fprintf (file
, "%d.w", INTVAL (addr
));
3176 fprintf (file
, "%d:w", INTVAL (addr
));
3179 else if (GET_CODE (addr
) == CONST_INT
)
3182 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
3189 else if (TARGET_PCREL
)
3192 output_addr_const (file
, addr
);
3194 asm_fprintf (file
, ":w,%Rpc)");
3196 asm_fprintf (file
, ":l,%Rpc)");
3200 /* Special case for SYMBOL_REF if the symbol name ends in
3201 `.<letter>', this can be mistaken as a size suffix. Put
3202 the name in parentheses. */
3203 if (GET_CODE (addr
) == SYMBOL_REF
3204 && strlen (XSTR (addr
, 0)) > 2
3205 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3208 output_addr_const (file
, addr
);
3212 output_addr_const (file
, addr
);
3218 /* Check for cases where a clr insns can be omitted from code using
3219 strict_low_part sets. For example, the second clrl here is not needed:
3220 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3222 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3223 insn we are checking for redundancy. TARGET is the register set by the
3227 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3228 enum machine_mode mode
;
3234 p
= prev_nonnote_insn (first_insn
);
3238 /* If it isn't an insn, then give up. */
3239 if (GET_CODE (p
) != INSN
)
3242 if (reg_set_p (target
, p
))
3244 rtx set
= single_set (p
);
3247 /* If it isn't an easy to recognize insn, then give up. */
3251 dest
= SET_DEST (set
);
3253 /* If this sets the entire target register to zero, then our
3254 first_insn is redundant. */
3255 if (rtx_equal_p (dest
, target
)
3256 && SET_SRC (set
) == const0_rtx
)
3258 else if (GET_CODE (dest
) == STRICT_LOW_PART
3259 && GET_CODE (XEXP (dest
, 0)) == REG
3260 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3261 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3262 <= GET_MODE_SIZE (mode
)))
3263 /* This is a strict low part set which modifies less than
3264 we are using, so it is safe. */
3270 p
= prev_nonnote_insn (p
);
3277 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3278 range carefully since this predicate is used in DImode contexts. Also, we
3279 need some extra crud to make it work when hosted on 64-bit machines. */
3282 const_uint32_operand (op
, mode
)
3284 enum machine_mode mode ATTRIBUTE_UNUSED
;
3286 #if HOST_BITS_PER_WIDE_INT > 32
3287 /* All allowed constants will fit a CONST_INT. */
3288 return (GET_CODE (op
) == CONST_INT
3289 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3291 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3292 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3296 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3297 to check the range carefully since this predicate is used in DImode
3301 const_sint32_operand (op
, mode
)
3303 enum machine_mode mode ATTRIBUTE_UNUSED
;
3305 /* All allowed constants will fit a CONST_INT. */
3306 return (GET_CODE (op
) == CONST_INT
3307 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3310 /* Operand predicates for implementing asymmetric pc-relative addressing
3311 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3312 when used as a source operand, but not as a destintation operand.
3314 We model this by restricting the meaning of the basic predicates
3315 (general_operand, memory_operand, etc) to forbid the use of this
3316 addressing mode, and then define the following predicates that permit
3317 this addressing mode. These predicates can then be used for the
3318 source operands of the appropriate instructions.
3320 n.b. While it is theoretically possible to change all machine patterns
3321 to use this addressing more where permitted by the architecture,
3322 it has only been implemented for "common" cases: SImode, HImode, and
3323 QImode operands, and only for the principle operations that would
3324 require this addressing mode: data movement and simple integer operations.
3326 In parallel with these new predicates, two new constraint letters
3327 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3328 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3329 In the pcrel case 's' is only valid in combination with 'a' registers.
3330 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3331 of how these constraints are used.
3333 The use of these predicates is strictly optional, though patterns that
3334 don't will cause an extra reload register to be allocated where one
3337 lea (abc:w,%pc),%a0 ; need to reload address
3338 moveq &1,%d1 ; since write to pc-relative space
3339 movel %d1,%a0@ ; is not allowed
3341 lea (abc:w,%pc),%a1 ; no need to reload address here
3342 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3344 For more info, consult tiemann@cygnus.com.
3347 All of the ugliness with predicates and constraints is due to the
3348 simple fact that the m68k does not allow a pc-relative addressing
3349 mode as a destination. gcc does not distinguish between source and
3350 destination addresses. Hence, if we claim that pc-relative address
3351 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3352 end up with invalid code. To get around this problem, we left
3353 pc-relative modes as invalid addresses, and then added special
3354 predicates and constraints to accept them.
3356 A cleaner way to handle this is to modify gcc to distinguish
3357 between source and destination addresses. We can then say that
3358 pc-relative is a valid source address but not a valid destination
3359 address, and hopefully avoid a lot of the predicate and constraint
3360 hackery. Unfortunately, this would be a pretty big change. It would
3361 be a useful change for a number of ports, but there aren't any current
3362 plans to undertake this.
3364 ***************************************************************************/
3367 /* Special case of a general operand that's used as a source operand.
3368 Use this to permit reads from PC-relative memory when -mpcrel
3372 general_src_operand (op
, mode
)
3374 enum machine_mode mode
;
3377 && GET_CODE (op
) == MEM
3378 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3379 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3380 || GET_CODE (XEXP (op
, 0)) == CONST
))
3382 return general_operand (op
, mode
);
3385 /* Special case of a nonimmediate operand that's used as a source.
3386 Use this to permit reads from PC-relative memory when -mpcrel
3390 nonimmediate_src_operand (op
, mode
)
3392 enum machine_mode mode
;
3394 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3395 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3396 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3397 || GET_CODE (XEXP (op
, 0)) == CONST
))
3399 return nonimmediate_operand (op
, mode
);
3402 /* Special case of a memory operand that's used as a source.
3403 Use this to permit reads from PC-relative memory when -mpcrel
3407 memory_src_operand (op
, mode
)
3409 enum machine_mode mode
;
3411 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3412 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3413 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3414 || GET_CODE (XEXP (op
, 0)) == CONST
))
3416 return memory_operand (op
, mode
);
3419 /* Predicate that accepts only a pc-relative address. This is needed
3420 because pc-relative addresses don't satisfy the predicate
3421 "general_src_operand". */
3424 pcrel_address (op
, mode
)
3426 enum machine_mode mode
;
3428 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3429 || GET_CODE (op
) == CONST
);
3433 output_andsi3 (operands
)
3437 if (GET_CODE (operands
[2]) == CONST_INT
3438 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3439 && (DATA_REG_P (operands
[0])
3440 || offsettable_memref_p (operands
[0]))
3443 if (GET_CODE (operands
[0]) != REG
)
3444 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3445 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3446 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3448 if (operands
[2] == const0_rtx
)
3450 return "and%.w %2,%0";
3452 if (GET_CODE (operands
[2]) == CONST_INT
3453 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3454 && (DATA_REG_P (operands
[0])
3455 || offsettable_memref_p (operands
[0])))
3457 if (DATA_REG_P (operands
[0]))
3459 operands
[1] = GEN_INT (logval
);
3463 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3464 operands
[1] = GEN_INT (logval
% 8);
3466 /* This does not set condition codes in a standard way. */
3468 return "bclr %1,%0";
3470 return "and%.l %2,%0";
3474 output_iorsi3 (operands
)
3477 register int logval
;
3478 if (GET_CODE (operands
[2]) == CONST_INT
3479 && INTVAL (operands
[2]) >> 16 == 0
3480 && (DATA_REG_P (operands
[0])
3481 || offsettable_memref_p (operands
[0]))
3484 if (GET_CODE (operands
[0]) != REG
)
3485 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3486 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3488 if (INTVAL (operands
[2]) == 0xffff)
3489 return "mov%.w %2,%0";
3490 return "or%.w %2,%0";
3492 if (GET_CODE (operands
[2]) == CONST_INT
3493 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3494 && (DATA_REG_P (operands
[0])
3495 || offsettable_memref_p (operands
[0])))
3497 if (DATA_REG_P (operands
[0]))
3499 operands
[1] = GEN_INT (logval
);
3503 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3504 operands
[1] = GEN_INT (logval
% 8);
3507 return "bset %1,%0";
3509 return "or%.l %2,%0";
3513 output_xorsi3 (operands
)
3516 register int logval
;
3517 if (GET_CODE (operands
[2]) == CONST_INT
3518 && INTVAL (operands
[2]) >> 16 == 0
3519 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3522 if (! DATA_REG_P (operands
[0]))
3523 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3524 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3526 if (INTVAL (operands
[2]) == 0xffff)
3528 return "eor%.w %2,%0";
3530 if (GET_CODE (operands
[2]) == CONST_INT
3531 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3532 && (DATA_REG_P (operands
[0])
3533 || offsettable_memref_p (operands
[0])))
3535 if (DATA_REG_P (operands
[0]))
3537 operands
[1] = GEN_INT (logval
);
3541 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3542 operands
[1] = GEN_INT (logval
% 8);
3545 return "bchg %1,%0";
3547 return "eor%.l %2,%0";