1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* Base flags for 68k ISAs. */
205 #define FL_FOR_isa_00 FL_ISA_68000
206 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
207 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
208 generated 68881 code for 68020 and 68030 targets unless explicitly told
210 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
211 | FL_BITFIELD | FL_68881)
212 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
213 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
215 /* Base flags for ColdFire ISAs. */
216 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
217 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
218 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
219 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
220 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
224 /* Traditional 68000 instruction sets. */
230 /* ColdFire instruction set variants. */
238 /* Information about one of the -march, -mcpu or -mtune arguments. */
239 struct m68k_target_selection
241 /* The argument being described. */
244 /* For -mcpu, this is the device selected by the option.
245 For -mtune and -march, it is a representative device
246 for the microarchitecture or ISA respectively. */
247 enum target_device device
;
249 /* The M68K_DEVICE fields associated with DEVICE. See the comment
250 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
252 enum uarch_type microarch
;
257 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
258 static const struct m68k_target_selection all_devices
[] =
260 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
261 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
262 #include "m68k-devices.def"
264 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
267 /* A list of all ISAs, mapping each one to a representative device.
268 Used for -march selection. */
269 static const struct m68k_target_selection all_isas
[] =
271 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
272 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
273 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
274 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
275 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
276 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
277 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
278 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
280 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
282 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
283 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
286 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
289 /* A list of all microarchitectures, mapping each one to a representative
290 device. Used for -mtune selection. */
291 static const struct m68k_target_selection all_microarchs
[] =
293 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
294 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
295 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
296 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
297 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
298 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
299 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
300 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
301 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
302 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
303 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
305 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
310 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
313 /* The entries associated with the -mcpu, -march and -mtune settings,
314 or null for options that have not been used. */
315 const struct m68k_target_selection
*m68k_cpu_entry
;
316 const struct m68k_target_selection
*m68k_arch_entry
;
317 const struct m68k_target_selection
*m68k_tune_entry
;
319 /* Which CPU we are generating code for. */
320 enum target_device m68k_cpu
;
322 /* Which microarchitecture to tune for. */
323 enum uarch_type m68k_tune
;
325 /* Which FPU to use. */
326 enum fpu_type m68k_fpu
;
328 /* The set of FL_* flags that apply to the target processor. */
329 unsigned int m68k_cpu_flags
;
331 /* See whether TABLE has an entry with name NAME. Return true and
332 store the entry in *ENTRY if so, otherwise return false and
333 leave *ENTRY alone. */
336 m68k_find_selection (const struct m68k_target_selection
**entry
,
337 const struct m68k_target_selection
*table
,
342 for (i
= 0; table
[i
].name
; i
++)
343 if (strcmp (table
[i
].name
, name
) == 0)
351 /* Implement TARGET_HANDLE_OPTION. */
354 m68k_handle_option (size_t code
, const char *arg
, int value
)
359 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
362 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
365 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
368 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
371 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
374 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
377 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
380 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
383 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
387 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
390 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
394 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
397 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
399 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
402 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
404 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
407 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
410 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
420 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
422 case OPT_mshared_library_id_
:
423 if (value
> MAX_LIBRARY_ID
)
424 error ("-mshared-library-id=%s is not between 0 and %d",
425 arg
, MAX_LIBRARY_ID
);
427 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
435 /* Sometimes certain combinations of command options do not make
436 sense on a particular target machine. You can define a macro
437 `OVERRIDE_OPTIONS' to take account of this. This macro, if
438 defined, is executed once just after all the command options have
441 Don't use this macro to turn on various extra optimizations for
442 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
445 override_options (void)
447 const struct m68k_target_selection
*entry
;
448 unsigned long target_mask
;
456 -march=ARCH should generate code that runs any processor
457 implementing architecture ARCH. -mcpu=CPU should override -march
458 and should generate code that runs on processor CPU, making free
459 use of any instructions that CPU understands. -mtune=UARCH applies
460 on top of -mcpu or -march and optimises the code for UARCH. It does
461 not change the target architecture. */
464 /* Complain if the -march setting is for a different microarchitecture,
465 or includes flags that the -mcpu setting doesn't. */
467 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
468 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
469 warning (0, "-mcpu=%s conflicts with -march=%s",
470 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
472 entry
= m68k_cpu_entry
;
475 entry
= m68k_arch_entry
;
478 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
480 m68k_cpu_flags
= entry
->flags
;
482 /* Use the architecture setting to derive default values for
485 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
486 target_mask
|= MASK_BITFIELD
;
487 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
488 target_mask
|= MASK_CF_HWDIV
;
489 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
490 target_mask
|= MASK_HARD_FLOAT
;
491 target_flags
|= target_mask
& ~target_flags_explicit
;
493 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
494 m68k_cpu
= entry
->device
;
496 m68k_tune
= m68k_tune_entry
->microarch
;
497 #ifdef M68K_DEFAULT_TUNE
498 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
499 m68k_tune
= M68K_DEFAULT_TUNE
;
502 m68k_tune
= entry
->microarch
;
504 /* Set the type of FPU. */
505 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
506 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
509 /* Sanity check to ensure that msep-data and mid-sahred-library are not
510 * both specified together. Doing so simply doesn't make sense.
512 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
513 error ("cannot specify both -msep-data and -mid-shared-library");
515 /* If we're generating code for a separate A5 relative data segment,
516 * we've got to enable -fPIC as well. This might be relaxable to
517 * -fpic but it hasn't been tested properly.
519 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
522 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
524 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
525 error ("-fPIC is not currently supported on the 68000 or 68010");
527 /* ??? A historic way of turning on pic, or is this intended to
528 be an embedded thing that doesn't have the same name binding
529 significance that it does on hosted ELF systems? */
530 if (TARGET_PCREL
&& flag_pic
== 0)
533 /* Turn off function cse if we are doing PIC. We always want function call
534 to be done as `bsr foo@PLTPC', so it will force the assembler to create
535 the PLT entry for `foo'. Doing function cse will cause the address of
536 `foo' to be loaded into a register, which is exactly what we want to
537 avoid when we are doing PIC on svr4 m68k. */
539 flag_no_function_cse
= 1;
541 SUBTARGET_OVERRIDE_OPTIONS
;
544 /* Return nonzero if FUNC is an interrupt function as specified by the
545 "interrupt_handler" attribute. */
547 m68k_interrupt_function_p(tree func
)
551 if (TREE_CODE (func
) != FUNCTION_DECL
)
554 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
555 return (a
!= NULL_TREE
);
558 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
559 struct attribute_spec.handler. */
561 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
562 tree args ATTRIBUTE_UNUSED
,
563 int flags ATTRIBUTE_UNUSED
,
566 if (TREE_CODE (*node
) != FUNCTION_DECL
)
568 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
569 IDENTIFIER_POINTER (name
));
570 *no_add_attrs
= true;
577 m68k_compute_frame_layout (void)
580 unsigned int mask
, rmask
;
581 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
583 /* Only compute the frame once per function.
584 Don't cache information until reload has been completed. */
585 if (current_frame
.funcdef_no
== current_function_funcdef_no
589 current_frame
.size
= (get_frame_size () + 3) & -4;
591 mask
= rmask
= saved
= 0;
592 for (regno
= 0; regno
< 16; regno
++)
593 if (m68k_save_reg (regno
, interrupt_handler
))
596 rmask
|= 1 << (15 - regno
);
599 current_frame
.offset
= saved
* 4;
600 current_frame
.reg_no
= saved
;
601 current_frame
.reg_mask
= mask
;
602 current_frame
.reg_rev_mask
= rmask
;
604 current_frame
.foffset
= 0;
605 mask
= rmask
= saved
= 0;
606 if (TARGET_HARD_FLOAT
)
608 for (regno
= 16; regno
< 24; regno
++)
609 if (m68k_save_reg (regno
, interrupt_handler
))
611 mask
|= 1 << (regno
- 16);
612 rmask
|= 1 << (23 - regno
);
615 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
616 current_frame
.offset
+= current_frame
.foffset
;
618 current_frame
.fpu_no
= saved
;
619 current_frame
.fpu_mask
= mask
;
620 current_frame
.fpu_rev_mask
= rmask
;
622 /* Remember what function this frame refers to. */
623 current_frame
.funcdef_no
= current_function_funcdef_no
;
627 m68k_initial_elimination_offset (int from
, int to
)
630 /* The arg pointer points 8 bytes before the start of the arguments,
631 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
632 frame pointer in most frames. */
633 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
634 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
635 return argptr_offset
;
637 m68k_compute_frame_layout ();
639 gcc_assert (to
== STACK_POINTER_REGNUM
);
642 case ARG_POINTER_REGNUM
:
643 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
644 case FRAME_POINTER_REGNUM
:
645 return current_frame
.offset
+ current_frame
.size
;
651 /* Refer to the array `regs_ever_live' to determine which registers
652 to save; `regs_ever_live[I]' is nonzero if register number I
653 is ever used in the function. This function is responsible for
654 knowing which registers should not be saved even if used.
655 Return true if we need to save REGNO. */
658 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
660 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
662 if (current_function_uses_pic_offset_table
)
664 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
668 if (current_function_calls_eh_return
)
673 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
674 if (test
== INVALID_REGNUM
)
681 /* Fixed regs we never touch. */
682 if (fixed_regs
[regno
])
685 /* The frame pointer (if it is such) is handled specially. */
686 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
689 /* Interrupt handlers must also save call_used_regs
690 if they are live or when calling nested functions. */
691 if (interrupt_handler
)
693 if (regs_ever_live
[regno
])
696 if (!current_function_is_leaf
&& call_used_regs
[regno
])
700 /* Never need to save registers that aren't touched. */
701 if (!regs_ever_live
[regno
])
704 /* Otherwise save everything that isn't call-clobbered. */
705 return !call_used_regs
[regno
];
708 /* This function generates the assembly code for function entry.
709 STREAM is a stdio stream to output the code to.
710 SIZE is an int: how many units of temporary storage to allocate. */
713 m68k_output_function_prologue (FILE *stream
,
714 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
716 HOST_WIDE_INT fsize_with_regs
;
717 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
719 m68k_compute_frame_layout();
721 /* If the stack limit is a symbol, we can check it here,
722 before actually allocating the space. */
723 if (current_function_limit_stack
724 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
725 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
726 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
728 /* On ColdFire add register save into initial stack frame setup, if possible. */
729 fsize_with_regs
= current_frame
.size
;
732 if (current_frame
.reg_no
> 2)
733 fsize_with_regs
+= current_frame
.reg_no
* 4;
734 if (current_frame
.fpu_no
)
735 fsize_with_regs
+= current_frame
.fpu_no
* 8;
738 if (frame_pointer_needed
)
740 if (current_frame
.size
== 0 && TUNE_68040
)
741 /* on the 68040, pea + move is faster than link.w 0 */
742 fprintf (stream
, (MOTOROLA
743 ? "\tpea (%s)\n\tmove.l %s,%s\n"
744 : "\tpea %s@\n\tmovel %s,%s\n"),
745 M68K_REGNAME (FRAME_POINTER_REGNUM
),
746 M68K_REGNAME (STACK_POINTER_REGNUM
),
747 M68K_REGNAME (FRAME_POINTER_REGNUM
));
748 else if (fsize_with_regs
< 0x8000)
749 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
750 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
751 else if (TARGET_68020
)
752 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
753 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
755 /* Adding negative number is faster on the 68040. */
757 "\tlink" ASM_DOTW
" %s,%I0\n"
758 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
759 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
761 else if (fsize_with_regs
) /* !frame_pointer_needed */
763 if (fsize_with_regs
< 0x8000)
765 if (fsize_with_regs
<= 8)
767 if (!TARGET_COLDFIRE
)
768 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
771 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
774 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
775 /* On the CPU32 it is faster to use two subqw instructions to
776 subtract a small integer (8 < N <= 16) to a register. */
778 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
779 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
780 fsize_with_regs
- 8);
782 /* Adding negative number is faster on the 68040. */
783 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
786 asm_fprintf (stream
, (MOTOROLA
787 ? "\tlea (%wd,%Rsp),%Rsp\n"
788 : "\tlea %Rsp@(%wd),%Rsp\n"),
791 else /* fsize_with_regs >= 0x8000 */
792 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
794 } /* !frame_pointer_needed */
796 if (dwarf2out_do_frame ())
798 if (frame_pointer_needed
)
801 l
= (char *) dwarf2out_cfi_label ();
803 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
804 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
805 cfa_offset
+= current_frame
.size
;
809 cfa_offset
+= current_frame
.size
;
810 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
814 if (current_frame
.fpu_mask
)
818 asm_fprintf (stream
, (MOTOROLA
819 ? "\tfmovm %I0x%x,-(%Rsp)\n"
820 : "\tfmovem %I0x%x,%Rsp@-\n"),
821 current_frame
.fpu_mask
);
827 /* stack already has registers in it. Find the offset from
828 the bottom of stack to where the FP registers go */
829 if (current_frame
.reg_no
<= 2)
832 offset
= current_frame
.reg_no
* 4;
835 "\tfmovem %I0x%x,%d(%Rsp)\n",
836 current_frame
.fpu_rev_mask
,
840 "\tfmovem %I0x%x,(%Rsp)\n",
841 current_frame
.fpu_rev_mask
);
844 if (dwarf2out_do_frame ())
846 char *l
= (char *) dwarf2out_cfi_label ();
849 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
850 if (! frame_pointer_needed
)
851 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
852 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
853 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
854 dwarf2out_reg_save (l
, regno
, -cfa_offset
855 + n_regs
++ * TARGET_FP_REG_SIZE
);
859 /* If the stack limit is not a symbol, check it here.
860 This has the disadvantage that it may be too late... */
861 if (current_function_limit_stack
)
863 if (REG_P (stack_limit_rtx
))
864 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
865 M68K_REGNAME (REGNO (stack_limit_rtx
)));
866 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
867 warning (0, "stack limit expression is not supported");
870 if (current_frame
.reg_no
<= 2)
872 /* Store each separately in the same order moveml uses.
873 Using two movel instructions instead of a single moveml
874 is about 15% faster for the 68020 and 68030 at no expense
879 for (i
= 0; i
< 16; i
++)
880 if (current_frame
.reg_rev_mask
& (1 << i
))
882 asm_fprintf (stream
, (MOTOROLA
883 ? "\t%Omove.l %s,-(%Rsp)\n"
884 : "\tmovel %s,%Rsp@-\n"),
885 M68K_REGNAME (15 - i
));
886 if (dwarf2out_do_frame ())
888 char *l
= (char *) dwarf2out_cfi_label ();
891 if (! frame_pointer_needed
)
892 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
893 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
897 else if (current_frame
.reg_rev_mask
)
900 /* The ColdFire does not support the predecrement form of the
901 MOVEM instruction, so we must adjust the stack pointer and
902 then use the plain address register indirect mode.
903 The required register save space was combined earlier with
904 the fsize_with_regs amount. */
906 asm_fprintf (stream
, (MOTOROLA
907 ? "\tmovm.l %I0x%x,(%Rsp)\n"
908 : "\tmoveml %I0x%x,%Rsp@\n"),
909 current_frame
.reg_mask
);
911 asm_fprintf (stream
, (MOTOROLA
912 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
913 : "\tmoveml %I0x%x,%Rsp@-\n"),
914 current_frame
.reg_rev_mask
);
915 if (dwarf2out_do_frame ())
917 char *l
= (char *) dwarf2out_cfi_label ();
920 cfa_offset
+= current_frame
.reg_no
* 4;
921 if (! frame_pointer_needed
)
922 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
923 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
924 if (current_frame
.reg_mask
& (1 << regno
))
925 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
928 if (!TARGET_SEP_DATA
&& flag_pic
929 && (current_function_uses_pic_offset_table
930 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
932 if (TARGET_ID_SHARED_LIBRARY
)
934 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
935 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
936 m68k_library_id_string
,
937 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
943 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
944 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
947 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
948 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
949 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
950 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
951 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
957 /* Return true if this function's epilogue can be output as RTL. */
960 use_return_insn (void)
962 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
965 /* We can output the epilogue as RTL only if no registers need to be
967 m68k_compute_frame_layout ();
968 return current_frame
.reg_no
? false : true;
971 /* This function generates the assembly code for function exit,
972 on machines that need it.
974 The function epilogue should not depend on the current stack pointer!
975 It should use the frame pointer only, if there is a frame pointer.
976 This is mandatory because of alloca; we also take advantage of it to
977 omit stack adjustments before returning. */
980 m68k_output_function_epilogue (FILE *stream
,
981 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
983 HOST_WIDE_INT fsize
, fsize_with_regs
;
985 bool restore_from_sp
= false;
986 rtx insn
= get_last_insn ();
988 m68k_compute_frame_layout ();
990 /* If the last insn was a BARRIER, we don't have to write any code. */
991 if (GET_CODE (insn
) == NOTE
)
992 insn
= prev_nonnote_insn (insn
);
993 if (insn
&& GET_CODE (insn
) == BARRIER
)
995 /* Output just a no-op so that debuggers don't get confused
996 about which function the pc is in at this address. */
997 fprintf (stream
, "\tnop\n");
1001 #ifdef FUNCTION_EXTRA_EPILOGUE
1002 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
1005 fsize
= current_frame
.size
;
1007 /* FIXME: leaf_function_p below is too strong.
1008 What we really need to know there is if there could be pending
1009 stack adjustment needed at that point. */
1011 = (! frame_pointer_needed
1012 || (! current_function_calls_alloca
&& leaf_function_p ()));
1014 /* fsize_with_regs is the size we need to adjust the sp when
1015 popping the frame. */
1016 fsize_with_regs
= fsize
;
1018 /* Because the ColdFire doesn't support moveml with
1019 complex address modes, we must adjust the stack manually
1020 after restoring registers. When the frame pointer isn't used,
1021 we can merge movem adjustment into frame unlinking
1022 made immediately after it. */
1023 if (TARGET_COLDFIRE
&& restore_from_sp
)
1025 if (current_frame
.reg_no
> 2)
1026 fsize_with_regs
+= current_frame
.reg_no
* 4;
1027 if (current_frame
.fpu_no
)
1028 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1031 if (current_frame
.offset
+ fsize
>= 0x8000
1032 && ! restore_from_sp
1033 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1035 /* Because the ColdFire doesn't support moveml with
1036 complex address modes we make an extra correction here. */
1037 if (TARGET_COLDFIRE
)
1038 fsize
+= current_frame
.offset
;
1040 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1041 fsize
= 0, big
= true;
1043 if (current_frame
.reg_no
<= 2)
1045 /* Restore each separately in the same order moveml does.
1046 Using two movel instructions instead of a single moveml
1047 is about 15% faster for the 68020 and 68030 at no expense
1051 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1053 for (i
= 0; i
< 16; i
++)
1054 if (current_frame
.reg_mask
& (1 << i
))
1059 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1061 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1064 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1065 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1069 else if (restore_from_sp
)
1070 asm_fprintf (stream
, (MOTOROLA
1071 ? "\t%Omove.l (%Rsp)+,%s\n"
1072 : "\tmovel %Rsp@+,%s\n"),
1077 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1079 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1082 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1083 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1090 else if (current_frame
.reg_mask
)
1092 /* The ColdFire requires special handling due to its limited moveml
1094 if (TARGET_COLDFIRE
)
1098 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1099 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1100 asm_fprintf (stream
, (MOTOROLA
1101 ? "\tmovm.l (%Ra1),%I0x%x\n"
1102 : "\tmoveml %Ra1@,%I0x%x\n"),
1103 current_frame
.reg_mask
);
1105 else if (restore_from_sp
)
1106 asm_fprintf (stream
, (MOTOROLA
1107 ? "\tmovm.l (%Rsp),%I0x%x\n"
1108 : "\tmoveml %Rsp@,%I0x%x\n"),
1109 current_frame
.reg_mask
);
1113 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1114 current_frame
.offset
+ fsize
,
1115 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1116 current_frame
.reg_mask
);
1118 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1119 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1120 current_frame
.offset
+ fsize
,
1121 current_frame
.reg_mask
);
1124 else /* !TARGET_COLDFIRE */
1129 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1130 current_frame
.offset
+ fsize
,
1131 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1132 current_frame
.reg_mask
);
1134 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1135 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1136 current_frame
.offset
+ fsize
,
1137 current_frame
.reg_mask
);
1139 else if (restore_from_sp
)
1141 asm_fprintf (stream
, (MOTOROLA
1142 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1143 : "\tmoveml %Rsp@+,%I0x%x\n"),
1144 current_frame
.reg_mask
);
1149 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1150 current_frame
.offset
+ fsize
,
1151 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1152 current_frame
.reg_mask
);
1154 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1155 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1156 current_frame
.offset
+ fsize
,
1157 current_frame
.reg_mask
);
1161 if (current_frame
.fpu_rev_mask
)
1165 if (TARGET_COLDFIRE
)
1167 if (current_frame
.reg_no
)
1168 asm_fprintf (stream
, MOTOROLA
?
1169 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1170 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1171 current_frame
.reg_no
* 4,
1172 current_frame
.fpu_rev_mask
);
1174 asm_fprintf (stream
, MOTOROLA
?
1175 "\tfmovem.d (%Ra1),%I0x%x\n" :
1176 "\tfmovmd (%Ra1),%I0x%x\n",
1177 current_frame
.fpu_rev_mask
);
1180 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1181 current_frame
.foffset
+ fsize
,
1182 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1183 current_frame
.fpu_rev_mask
);
1185 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1186 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1187 current_frame
.foffset
+ fsize
,
1188 current_frame
.fpu_rev_mask
);
1190 else if (restore_from_sp
)
1192 if (TARGET_COLDFIRE
)
1196 /* Stack already has registers in it. Find the offset from
1197 the bottom of stack to where the FP registers go. */
1198 if (current_frame
.reg_no
<= 2)
1201 offset
= current_frame
.reg_no
* 4;
1203 asm_fprintf (stream
,
1204 "\tfmovem %Rsp@(%d), %I0x%x\n",
1205 offset
, current_frame
.fpu_rev_mask
);
1207 asm_fprintf (stream
,
1208 "\tfmovem %Rsp@, %I0x%x\n",
1209 current_frame
.fpu_rev_mask
);
1212 asm_fprintf (stream
, MOTOROLA
?
1213 "\tfmovm (%Rsp)+,%I0x%x\n" :
1214 "\tfmovem %Rsp@+,%I0x%x\n",
1215 current_frame
.fpu_rev_mask
);
1219 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1220 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1221 current_frame
.foffset
+ fsize
,
1222 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1223 current_frame
.fpu_rev_mask
);
1225 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1226 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1227 current_frame
.foffset
+ fsize
,
1228 current_frame
.fpu_rev_mask
);
1231 if (frame_pointer_needed
)
1232 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1233 else if (fsize_with_regs
)
1235 if (fsize_with_regs
<= 8)
1237 if (!TARGET_COLDFIRE
)
1238 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1241 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1244 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1246 /* On the CPU32 it is faster to use two addqw instructions to
1247 add a small integer (8 < N <= 16) to a register. */
1248 asm_fprintf (stream
,
1249 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1250 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1251 fsize_with_regs
- 8);
1253 else if (fsize_with_regs
< 0x8000)
1256 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1259 asm_fprintf (stream
, (MOTOROLA
1260 ? "\tlea (%wd,%Rsp),%Rsp\n"
1261 : "\tlea %Rsp@(%wd),%Rsp\n"),
1265 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1267 if (current_function_calls_eh_return
)
1268 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1269 if (m68k_interrupt_function_p (current_function_decl
))
1270 fprintf (stream
, "\trte\n");
1271 else if (current_function_pops_args
)
1272 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1274 fprintf (stream
, "\trts\n");
1277 /* Return true if X is a valid comparison operator for the dbcc
1280 Note it rejects floating point comparison operators.
1281 (In the future we could use Fdbcc).
1283 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1286 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1288 switch (GET_CODE (x
))
1290 case EQ
: case NE
: case GTU
: case LTU
:
1294 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1296 case GT
: case LT
: case GE
: case LE
:
1297 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1303 /* Return nonzero if flags are currently in the 68881 flag register. */
1305 flags_in_68881 (void)
1307 /* We could add support for these in the future */
1308 return cc_status
.flags
& CC_IN_68881
;
1311 /* Output a BSR instruction suitable for PIC code. */
1313 m68k_output_pic_call (rtx dest
)
1317 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1319 /* We output a BSR instruction if we're building for a target that
1320 supports long branches. Otherwise we generate one of two sequences:
1321 a shorter one that uses a GOT entry or a longer one that doesn't.
1322 We'll use the -Os command-line flag to decide which to generate.
1323 Both sequences take the same time to execute on the ColdFire. */
1324 else if (TARGET_PCREL
)
1326 else if (TARGET_68020
)
1327 #if defined(USE_GAS)
1328 out
= "bsr.l %0@PLTPC";
1330 out
= "bsr %0@PLTPC";
1332 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1333 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1335 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1337 output_asm_insn (out
, &dest
);
1340 /* Output a dbCC; jCC sequence. Note we do not handle the
1341 floating point version of this sequence (Fdbcc). We also
1342 do not handle alternative conditions when CC_NO_OVERFLOW is
1343 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1344 kick those out before we get here. */
1347 output_dbcc_and_branch (rtx
*operands
)
1349 switch (GET_CODE (operands
[3]))
1352 output_asm_insn (MOTOROLA
1353 ? "dbeq %0,%l1\n\tjbeq %l2"
1354 : "dbeq %0,%l1\n\tjeq %l2",
1359 output_asm_insn (MOTOROLA
1360 ? "dbne %0,%l1\n\tjbne %l2"
1361 : "dbne %0,%l1\n\tjne %l2",
1366 output_asm_insn (MOTOROLA
1367 ? "dbgt %0,%l1\n\tjbgt %l2"
1368 : "dbgt %0,%l1\n\tjgt %l2",
1373 output_asm_insn (MOTOROLA
1374 ? "dbhi %0,%l1\n\tjbhi %l2"
1375 : "dbhi %0,%l1\n\tjhi %l2",
1380 output_asm_insn (MOTOROLA
1381 ? "dblt %0,%l1\n\tjblt %l2"
1382 : "dblt %0,%l1\n\tjlt %l2",
1387 output_asm_insn (MOTOROLA
1388 ? "dbcs %0,%l1\n\tjbcs %l2"
1389 : "dbcs %0,%l1\n\tjcs %l2",
1394 output_asm_insn (MOTOROLA
1395 ? "dbge %0,%l1\n\tjbge %l2"
1396 : "dbge %0,%l1\n\tjge %l2",
1401 output_asm_insn (MOTOROLA
1402 ? "dbcc %0,%l1\n\tjbcc %l2"
1403 : "dbcc %0,%l1\n\tjcc %l2",
1408 output_asm_insn (MOTOROLA
1409 ? "dble %0,%l1\n\tjble %l2"
1410 : "dble %0,%l1\n\tjle %l2",
1415 output_asm_insn (MOTOROLA
1416 ? "dbls %0,%l1\n\tjbls %l2"
1417 : "dbls %0,%l1\n\tjls %l2",
1425 /* If the decrement is to be done in SImode, then we have
1426 to compensate for the fact that dbcc decrements in HImode. */
1427 switch (GET_MODE (operands
[0]))
1430 output_asm_insn (MOTOROLA
1431 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1432 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1445 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1448 enum rtx_code op_code
= GET_CODE (op
);
1450 /* This does not produce a useful cc. */
1453 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1454 below. Swap the operands and change the op if these requirements
1455 are not fulfilled. */
1456 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1460 operand1
= operand2
;
1462 op_code
= swap_condition (op_code
);
1464 loperands
[0] = operand1
;
1465 if (GET_CODE (operand1
) == REG
)
1466 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1468 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1469 if (operand2
!= const0_rtx
)
1471 loperands
[2] = operand2
;
1472 if (GET_CODE (operand2
) == REG
)
1473 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1475 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1477 loperands
[4] = gen_label_rtx ();
1478 if (operand2
!= const0_rtx
)
1480 output_asm_insn (MOTOROLA
1481 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1482 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1487 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1488 output_asm_insn ("tst%.l %0", loperands
);
1490 output_asm_insn ("cmp%.w #0,%0", loperands
);
1492 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1494 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1495 output_asm_insn ("tst%.l %1", loperands
);
1497 output_asm_insn ("cmp%.w #0,%1", loperands
);
1500 loperands
[5] = dest
;
1505 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1506 CODE_LABEL_NUMBER (loperands
[4]));
1507 output_asm_insn ("seq %5", loperands
);
1511 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1512 CODE_LABEL_NUMBER (loperands
[4]));
1513 output_asm_insn ("sne %5", loperands
);
1517 loperands
[6] = gen_label_rtx ();
1518 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1520 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1521 CODE_LABEL_NUMBER (loperands
[4]));
1522 output_asm_insn ("sgt %5", loperands
);
1523 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1524 CODE_LABEL_NUMBER (loperands
[6]));
1528 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1529 CODE_LABEL_NUMBER (loperands
[4]));
1530 output_asm_insn ("shi %5", loperands
);
1534 loperands
[6] = gen_label_rtx ();
1535 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1537 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1538 CODE_LABEL_NUMBER (loperands
[4]));
1539 output_asm_insn ("slt %5", loperands
);
1540 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1541 CODE_LABEL_NUMBER (loperands
[6]));
1545 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1546 CODE_LABEL_NUMBER (loperands
[4]));
1547 output_asm_insn ("scs %5", loperands
);
1551 loperands
[6] = gen_label_rtx ();
1552 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1554 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1555 CODE_LABEL_NUMBER (loperands
[4]));
1556 output_asm_insn ("sge %5", loperands
);
1557 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1558 CODE_LABEL_NUMBER (loperands
[6]));
1562 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1563 CODE_LABEL_NUMBER (loperands
[4]));
1564 output_asm_insn ("scc %5", loperands
);
1568 loperands
[6] = gen_label_rtx ();
1569 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1571 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1572 CODE_LABEL_NUMBER (loperands
[4]));
1573 output_asm_insn ("sle %5", loperands
);
1574 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1575 CODE_LABEL_NUMBER (loperands
[6]));
1579 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1580 CODE_LABEL_NUMBER (loperands
[4]));
1581 output_asm_insn ("sls %5", loperands
);
1591 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1593 operands
[0] = countop
;
1594 operands
[1] = dataop
;
1596 if (GET_CODE (countop
) == CONST_INT
)
1598 register int count
= INTVAL (countop
);
1599 /* If COUNT is bigger than size of storage unit in use,
1600 advance to the containing unit of same size. */
1601 if (count
> signpos
)
1603 int offset
= (count
& ~signpos
) / 8;
1604 count
= count
& signpos
;
1605 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1607 if (count
== signpos
)
1608 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1610 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1612 /* These three statements used to use next_insns_test_no...
1613 but it appears that this should do the same job. */
1615 && next_insn_tests_no_inequality (insn
))
1618 && next_insn_tests_no_inequality (insn
))
1621 && next_insn_tests_no_inequality (insn
))
1624 cc_status
.flags
= CC_NOT_NEGATIVE
;
1626 return "btst %0,%1";
1629 /* Legitimize PIC addresses. If the address is already
1630 position-independent, we return ORIG. Newly generated
1631 position-independent addresses go to REG. If we need more
1632 than one register, we lose.
1634 An address is legitimized by making an indirect reference
1635 through the Global Offset Table with the name of the symbol
1638 The assembler and linker are responsible for placing the
1639 address of the symbol in the GOT. The function prologue
1640 is responsible for initializing a5 to the starting address
1643 The assembler is also responsible for translating a symbol name
1644 into a constant displacement from the start of the GOT.
1646 A quick example may make things a little clearer:
1648 When not generating PIC code to store the value 12345 into _foo
1649 we would generate the following code:
1653 When generating PIC two transformations are made. First, the compiler
1654 loads the address of foo into a register. So the first transformation makes:
1659 The code in movsi will intercept the lea instruction and call this
1660 routine which will transform the instructions into:
1662 movel a5@(_foo:w), a0
1666 That (in a nutshell) is how *all* symbol and label references are
1670 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1675 /* First handle a simple SYMBOL_REF or LABEL_REF */
1676 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1680 pic_ref
= gen_rtx_MEM (Pmode
,
1681 gen_rtx_PLUS (Pmode
,
1682 pic_offset_table_rtx
, orig
));
1683 current_function_uses_pic_offset_table
= 1;
1684 MEM_READONLY_P (pic_ref
) = 1;
1685 emit_move_insn (reg
, pic_ref
);
1688 else if (GET_CODE (orig
) == CONST
)
1692 /* Make sure this has not already been legitimized. */
1693 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1694 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1699 /* legitimize both operands of the PLUS */
1700 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1702 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1703 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1704 base
== reg
? 0 : reg
);
1706 if (GET_CODE (orig
) == CONST_INT
)
1707 return plus_constant (base
, INTVAL (orig
));
1708 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1709 /* Likewise, should we set special REG_NOTEs here? */
1715 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1717 static CONST_METHOD
const_method (rtx
);
1719 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1722 const_method (rtx constant
)
1727 i
= INTVAL (constant
);
1731 /* The ColdFire doesn't have byte or word operations. */
1732 /* FIXME: This may not be useful for the m68060 either. */
1733 if (!TARGET_COLDFIRE
)
1735 /* if -256 < N < 256 but N is not in range for a moveq
1736 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1737 if (USE_MOVQ (i
^ 0xff))
1739 /* Likewise, try with not.w */
1740 if (USE_MOVQ (i
^ 0xffff))
1742 /* This is the only value where neg.w is useful */
1747 /* Try also with swap. */
1749 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1754 /* Try using MVZ/MVS with an immediate value to load constants. */
1755 if (i
>= 0 && i
<= 65535)
1757 if (i
>= -32768 && i
<= 32767)
1761 /* Otherwise, use move.l */
1766 const_int_cost (rtx constant
)
1768 switch (const_method (constant
))
1771 /* Constants between -128 and 127 are cheap due to moveq. */
1779 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1789 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1794 /* Constant zero is super cheap due to clr instruction. */
1795 if (x
== const0_rtx
)
1798 *total
= const_int_cost (x
);
1808 /* Make 0.0 cheaper than other floating constants to
1809 encourage creating tstsf and tstdf insns. */
1810 if (outer_code
== COMPARE
1811 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1817 /* These are vaguely right for a 68020. */
1818 /* The costs for long multiply have been adjusted to work properly
1819 in synth_mult on the 68020, relative to an average of the time
1820 for add and the time for shift, taking away a little more because
1821 sometimes move insns are needed. */
1822 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1828 : TARGET_COLDFIRE ? 3 : 13)
1833 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1834 : TARGET_COLDFIRE ? 2 : 8)
1837 (TARGET_CF_HWDIV ? 11 \
1838 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1841 /* An lea costs about three times as much as a simple add. */
1842 if (GET_MODE (x
) == SImode
1843 && GET_CODE (XEXP (x
, 1)) == REG
1844 && GET_CODE (XEXP (x
, 0)) == MULT
1845 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1846 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1847 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1848 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1849 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1851 /* lea an@(dx:l:i),am */
1852 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1862 *total
= COSTS_N_INSNS(1);
1867 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1869 if (INTVAL (XEXP (x
, 1)) < 16)
1870 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1872 /* We're using clrw + swap for these cases. */
1873 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1876 *total
= COSTS_N_INSNS (10); /* Worst case. */
1879 /* A shift by a big integer takes an extra instruction. */
1880 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1881 && (INTVAL (XEXP (x
, 1)) == 16))
1883 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1886 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1887 && !(INTVAL (XEXP (x
, 1)) > 0
1888 && INTVAL (XEXP (x
, 1)) <= 8))
1890 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1896 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1897 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1898 && GET_MODE (x
) == SImode
)
1899 *total
= COSTS_N_INSNS (MULW_COST
);
1900 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1901 *total
= COSTS_N_INSNS (MULW_COST
);
1903 *total
= COSTS_N_INSNS (MULL_COST
);
1910 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1911 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1912 else if (TARGET_CF_HWDIV
)
1913 *total
= COSTS_N_INSNS (18);
1915 *total
= COSTS_N_INSNS (43); /* div.l */
1924 output_move_const_into_data_reg (rtx
*operands
)
1928 i
= INTVAL (operands
[1]);
1929 switch (const_method (operands
[1]))
1932 return "mvzw %1,%0";
1934 return "mvsw %1,%0";
1936 return "moveq %1,%0";
1939 operands
[1] = GEN_INT (i
^ 0xff);
1940 return "moveq %1,%0\n\tnot%.b %0";
1943 operands
[1] = GEN_INT (i
^ 0xffff);
1944 return "moveq %1,%0\n\tnot%.w %0";
1947 return "moveq #-128,%0\n\tneg%.w %0";
1952 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1953 return "moveq %1,%0\n\tswap %0";
1956 return "move%.l %1,%0";
1962 /* Return 1 if 'constant' can be represented by
1963 mov3q on a ColdFire V4 core. */
1965 valid_mov3q_const (rtx constant
)
1969 if (TARGET_ISAB
&& GET_CODE (constant
) == CONST_INT
)
1971 i
= INTVAL (constant
);
1972 if (i
== -1 || (i
>= 1 && i
<= 7))
1980 output_move_simode_const (rtx
*operands
)
1982 if (operands
[1] == const0_rtx
1983 && (DATA_REG_P (operands
[0])
1984 || GET_CODE (operands
[0]) == MEM
)
1985 /* clr insns on 68000 read before writing. */
1986 && ((TARGET_68010
|| TARGET_COLDFIRE
)
1987 || !(GET_CODE (operands
[0]) == MEM
1988 && MEM_VOLATILE_P (operands
[0]))))
1990 else if ((GET_MODE (operands
[0]) == SImode
)
1991 && valid_mov3q_const (operands
[1]))
1992 return "mov3q%.l %1,%0";
1993 else if (operands
[1] == const0_rtx
1994 && ADDRESS_REG_P (operands
[0]))
1995 return "sub%.l %0,%0";
1996 else if (DATA_REG_P (operands
[0]))
1997 return output_move_const_into_data_reg (operands
);
1998 else if (ADDRESS_REG_P (operands
[0])
1999 && INTVAL (operands
[1]) < 0x8000
2000 && INTVAL (operands
[1]) >= -0x8000)
2002 if (valid_mov3q_const (operands
[1]))
2003 return "mov3q%.l %1,%0";
2004 return "move%.w %1,%0";
2006 else if (GET_CODE (operands
[0]) == MEM
2007 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2008 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2009 && INTVAL (operands
[1]) < 0x8000
2010 && INTVAL (operands
[1]) >= -0x8000)
2012 if (valid_mov3q_const (operands
[1]))
2013 return "mov3q%.l %1,%-";
2016 return "move%.l %1,%0";
2020 output_move_simode (rtx
*operands
)
2022 if (GET_CODE (operands
[1]) == CONST_INT
)
2023 return output_move_simode_const (operands
);
2024 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2025 || GET_CODE (operands
[1]) == CONST
)
2026 && push_operand (operands
[0], SImode
))
2028 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2029 || GET_CODE (operands
[1]) == CONST
)
2030 && ADDRESS_REG_P (operands
[0]))
2031 return "lea %a1,%0";
2032 return "move%.l %1,%0";
2036 output_move_himode (rtx
*operands
)
2038 if (GET_CODE (operands
[1]) == CONST_INT
)
2040 if (operands
[1] == const0_rtx
2041 && (DATA_REG_P (operands
[0])
2042 || GET_CODE (operands
[0]) == MEM
)
2043 /* clr insns on 68000 read before writing. */
2044 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2045 || !(GET_CODE (operands
[0]) == MEM
2046 && MEM_VOLATILE_P (operands
[0]))))
2048 else if (operands
[1] == const0_rtx
2049 && ADDRESS_REG_P (operands
[0]))
2050 return "sub%.l %0,%0";
2051 else if (DATA_REG_P (operands
[0])
2052 && INTVAL (operands
[1]) < 128
2053 && INTVAL (operands
[1]) >= -128)
2054 return "moveq %1,%0";
2055 else if (INTVAL (operands
[1]) < 0x8000
2056 && INTVAL (operands
[1]) >= -0x8000)
2057 return "move%.w %1,%0";
2059 else if (CONSTANT_P (operands
[1]))
2060 return "move%.l %1,%0";
2061 /* Recognize the insn before a tablejump, one that refers
2062 to a table of offsets. Such an insn will need to refer
2063 to a label on the insn. So output one. Use the label-number
2064 of the table of offsets to generate this label. This code,
2065 and similar code below, assumes that there will be at most one
2066 reference to each table. */
2067 if (GET_CODE (operands
[1]) == MEM
2068 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2069 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2070 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2072 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2074 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2075 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2077 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2078 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2080 return "move%.w %1,%0";
2084 output_move_qimode (rtx
*operands
)
2086 /* 68k family always modifies the stack pointer by at least 2, even for
2087 byte pushes. The 5200 (ColdFire) does not do this. */
2089 /* This case is generated by pushqi1 pattern now. */
2090 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2091 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2092 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2093 && ! ADDRESS_REG_P (operands
[1])
2094 && ! TARGET_COLDFIRE
));
2096 /* clr and st insns on 68000 read before writing. */
2097 if (!ADDRESS_REG_P (operands
[0])
2098 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2099 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2101 if (operands
[1] == const0_rtx
)
2103 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2104 && GET_CODE (operands
[1]) == CONST_INT
2105 && (INTVAL (operands
[1]) & 255) == 255)
2111 if (GET_CODE (operands
[1]) == CONST_INT
2112 && DATA_REG_P (operands
[0])
2113 && INTVAL (operands
[1]) < 128
2114 && INTVAL (operands
[1]) >= -128)
2115 return "moveq %1,%0";
2116 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2117 return "sub%.l %0,%0";
2118 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2119 return "move%.l %1,%0";
2120 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2121 from address registers. */
2122 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2123 return "move%.w %1,%0";
2124 return "move%.b %1,%0";
2128 output_move_stricthi (rtx
*operands
)
2130 if (operands
[1] == const0_rtx
2131 /* clr insns on 68000 read before writing. */
2132 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2133 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2135 return "move%.w %1,%0";
2139 output_move_strictqi (rtx
*operands
)
2141 if (operands
[1] == const0_rtx
2142 /* clr insns on 68000 read before writing. */
2143 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2144 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2146 return "move%.b %1,%0";
2149 /* Return the best assembler insn template
2150 for moving operands[1] into operands[0] as a fullword. */
2153 singlemove_string (rtx
*operands
)
2155 if (GET_CODE (operands
[1]) == CONST_INT
)
2156 return output_move_simode_const (operands
);
2157 return "move%.l %1,%0";
2161 /* Output assembler code to perform a doubleword move insn
2162 with operands OPERANDS. */
2165 output_move_double (rtx
*operands
)
2169 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2174 rtx addreg0
= 0, addreg1
= 0;
2175 int dest_overlapped_low
= 0;
2176 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2181 /* First classify both operands. */
2183 if (REG_P (operands
[0]))
2185 else if (offsettable_memref_p (operands
[0]))
2187 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2189 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2191 else if (GET_CODE (operands
[0]) == MEM
)
2196 if (REG_P (operands
[1]))
2198 else if (CONSTANT_P (operands
[1]))
2200 else if (offsettable_memref_p (operands
[1]))
2202 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2204 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2206 else if (GET_CODE (operands
[1]) == MEM
)
2211 /* Check for the cases that the operand constraints are not supposed
2212 to allow to happen. Generating code for these cases is
2214 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2216 /* If one operand is decrementing and one is incrementing
2217 decrement the former register explicitly
2218 and change that operand into ordinary indexing. */
2220 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2222 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2224 output_asm_insn ("sub%.l #12,%0", operands
);
2226 output_asm_insn ("subq%.l #8,%0", operands
);
2227 if (GET_MODE (operands
[1]) == XFmode
)
2228 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2229 else if (GET_MODE (operands
[0]) == DFmode
)
2230 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2232 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2235 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2237 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2239 output_asm_insn ("sub%.l #12,%1", operands
);
2241 output_asm_insn ("subq%.l #8,%1", operands
);
2242 if (GET_MODE (operands
[1]) == XFmode
)
2243 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2244 else if (GET_MODE (operands
[1]) == DFmode
)
2245 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2247 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2251 /* If an operand is an unoffsettable memory ref, find a register
2252 we can increment temporarily to make it refer to the second word. */
2254 if (optype0
== MEMOP
)
2255 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2257 if (optype1
== MEMOP
)
2258 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2260 /* Ok, we can do one word at a time.
2261 Normally we do the low-numbered word first,
2262 but if either operand is autodecrementing then we
2263 do the high-numbered word first.
2265 In either case, set up in LATEHALF the operands to use
2266 for the high-numbered word and in some cases alter the
2267 operands in OPERANDS to be suitable for the low-numbered word. */
2271 if (optype0
== REGOP
)
2273 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2274 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2276 else if (optype0
== OFFSOP
)
2278 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2279 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2283 middlehalf
[0] = operands
[0];
2284 latehalf
[0] = operands
[0];
2287 if (optype1
== REGOP
)
2289 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2290 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2292 else if (optype1
== OFFSOP
)
2294 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2295 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2297 else if (optype1
== CNSTOP
)
2299 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2304 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2305 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2306 operands
[1] = GEN_INT (l
[0]);
2307 middlehalf
[1] = GEN_INT (l
[1]);
2308 latehalf
[1] = GEN_INT (l
[2]);
2312 /* No non-CONST_DOUBLE constant should ever appear
2314 gcc_assert (!CONSTANT_P (operands
[1]));
2319 middlehalf
[1] = operands
[1];
2320 latehalf
[1] = operands
[1];
2324 /* size is not 12: */
2326 if (optype0
== REGOP
)
2327 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2328 else if (optype0
== OFFSOP
)
2329 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2331 latehalf
[0] = operands
[0];
2333 if (optype1
== REGOP
)
2334 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2335 else if (optype1
== OFFSOP
)
2336 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2337 else if (optype1
== CNSTOP
)
2338 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2340 latehalf
[1] = operands
[1];
2343 /* If insn is effectively movd N(sp),-(sp) then we will do the
2344 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2345 for the low word as well, to compensate for the first decrement of sp. */
2346 if (optype0
== PUSHOP
2347 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2348 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2349 operands
[1] = middlehalf
[1] = latehalf
[1];
2351 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2352 if the upper part of reg N does not appear in the MEM, arrange to
2353 emit the move late-half first. Otherwise, compute the MEM address
2354 into the upper part of N and use that as a pointer to the memory
2356 if (optype0
== REGOP
2357 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2359 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2361 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2362 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2364 /* If both halves of dest are used in the src memory address,
2365 compute the address into latehalf of dest.
2366 Note that this can't happen if the dest is two data regs. */
2368 xops
[0] = latehalf
[0];
2369 xops
[1] = XEXP (operands
[1], 0);
2370 output_asm_insn ("lea %a1,%0", xops
);
2371 if (GET_MODE (operands
[1]) == XFmode
)
2373 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2374 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2375 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2379 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2380 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2384 && reg_overlap_mentioned_p (middlehalf
[0],
2385 XEXP (operands
[1], 0)))
2387 /* Check for two regs used by both source and dest.
2388 Note that this can't happen if the dest is all data regs.
2389 It can happen if the dest is d6, d7, a0.
2390 But in that case, latehalf is an addr reg, so
2391 the code at compadr does ok. */
2393 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2394 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2397 /* JRV says this can't happen: */
2398 gcc_assert (!addreg0
&& !addreg1
);
2400 /* Only the middle reg conflicts; simply put it last. */
2401 output_asm_insn (singlemove_string (operands
), operands
);
2402 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2403 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2406 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2407 /* If the low half of dest is mentioned in the source memory
2408 address, the arrange to emit the move late half first. */
2409 dest_overlapped_low
= 1;
2412 /* If one or both operands autodecrementing,
2413 do the two words, high-numbered first. */
2415 /* Likewise, the first move would clobber the source of the second one,
2416 do them in the other order. This happens only for registers;
2417 such overlap can't happen in memory unless the user explicitly
2418 sets it up, and that is an undefined circumstance. */
2420 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2421 || (optype0
== REGOP
&& optype1
== REGOP
2422 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2423 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2424 || dest_overlapped_low
)
2426 /* Make any unoffsettable addresses point at high-numbered word. */
2430 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2432 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2437 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2439 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2443 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2445 /* Undo the adds we just did. */
2447 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2449 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2453 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2455 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2457 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2460 /* Do low-numbered word. */
2461 return singlemove_string (operands
);
2464 /* Normal case: do the two words, low-numbered first. */
2466 output_asm_insn (singlemove_string (operands
), operands
);
2468 /* Do the middle one of the three words for long double */
2472 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2474 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2476 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2479 /* Make any unoffsettable addresses point at high-numbered word. */
2481 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2483 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2486 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2488 /* Undo the adds we just did. */
2492 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2494 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2499 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2501 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2508 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2509 new rtx with the correct mode. */
2512 force_mode (enum machine_mode mode
, rtx orig
)
2514 if (mode
== GET_MODE (orig
))
2517 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2520 return gen_rtx_REG (mode
, REGNO (orig
));
2524 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2526 return reg_renumber
&& FP_REG_P (op
);
2529 /* Emit insns to move operands[1] into operands[0].
2531 Return 1 if we have written out everything that needs to be done to
2532 do the move. Otherwise, return 0 and the caller will emit the move
2535 Note SCRATCH_REG may not be in the proper mode depending on how it
2536 will be used. This routine is responsible for creating a new copy
2537 of SCRATCH_REG in the proper mode. */
2540 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2542 register rtx operand0
= operands
[0];
2543 register rtx operand1
= operands
[1];
2547 && reload_in_progress
&& GET_CODE (operand0
) == REG
2548 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2549 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2550 else if (scratch_reg
2551 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2552 && GET_CODE (SUBREG_REG (operand0
)) == REG
2553 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2555 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2556 the code which tracks sets/uses for delete_output_reload. */
2557 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2558 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2559 SUBREG_BYTE (operand0
));
2560 operand0
= alter_subreg (&temp
);
2564 && reload_in_progress
&& GET_CODE (operand1
) == REG
2565 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2566 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2567 else if (scratch_reg
2568 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2569 && GET_CODE (SUBREG_REG (operand1
)) == REG
2570 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2572 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2573 the code which tracks sets/uses for delete_output_reload. */
2574 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2575 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2576 SUBREG_BYTE (operand1
));
2577 operand1
= alter_subreg (&temp
);
2580 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2581 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2582 != XEXP (operand0
, 0)))
2583 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2584 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2585 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2586 != XEXP (operand1
, 0)))
2587 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2589 /* Handle secondary reloads for loads/stores of FP registers where
2590 the address is symbolic by using the scratch register */
2591 if (fp_reg_operand (operand0
, mode
)
2592 && ((GET_CODE (operand1
) == MEM
2593 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2594 || ((GET_CODE (operand1
) == SUBREG
2595 && GET_CODE (XEXP (operand1
, 0)) == MEM
2596 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2599 if (GET_CODE (operand1
) == SUBREG
)
2600 operand1
= XEXP (operand1
, 0);
2602 /* SCRATCH_REG will hold an address. We want
2603 it in SImode regardless of what mode it was originally given
2605 scratch_reg
= force_mode (SImode
, scratch_reg
);
2607 /* D might not fit in 14 bits either; for such cases load D into
2609 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2611 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2612 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2614 XEXP (XEXP (operand1
, 0), 0),
2618 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2619 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2620 gen_rtx_MEM (mode
, scratch_reg
)));
2623 else if (fp_reg_operand (operand1
, mode
)
2624 && ((GET_CODE (operand0
) == MEM
2625 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2626 || ((GET_CODE (operand0
) == SUBREG
)
2627 && GET_CODE (XEXP (operand0
, 0)) == MEM
2628 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2631 if (GET_CODE (operand0
) == SUBREG
)
2632 operand0
= XEXP (operand0
, 0);
2634 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2635 it in SIMODE regardless of what mode it was originally given
2637 scratch_reg
= force_mode (SImode
, scratch_reg
);
2639 /* D might not fit in 14 bits either; for such cases load D into
2641 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2643 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2644 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2647 XEXP (XEXP (operand0
, 0),
2652 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2653 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2657 /* Handle secondary reloads for loads of FP registers from constant
2658 expressions by forcing the constant into memory.
2660 use scratch_reg to hold the address of the memory location.
2662 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2663 NO_REGS when presented with a const_int and an register class
2664 containing only FP registers. Doing so unfortunately creates
2665 more problems than it solves. Fix this for 2.5. */
2666 else if (fp_reg_operand (operand0
, mode
)
2667 && CONSTANT_P (operand1
)
2672 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2673 it in SIMODE regardless of what mode it was originally given
2675 scratch_reg
= force_mode (SImode
, scratch_reg
);
2677 /* Force the constant into memory and put the address of the
2678 memory location into scratch_reg. */
2679 xoperands
[0] = scratch_reg
;
2680 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2681 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2683 /* Now load the destination register. */
2684 emit_insn (gen_rtx_SET (mode
, operand0
,
2685 gen_rtx_MEM (mode
, scratch_reg
)));
2689 /* Now have insn-emit do whatever it normally does. */
2693 /* Return a REG that occurs in ADDR with coefficient 1.
2694 ADDR can be effectively incremented by incrementing REG. */
2697 find_addr_reg (rtx addr
)
2699 while (GET_CODE (addr
) == PLUS
)
2701 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2702 addr
= XEXP (addr
, 0);
2703 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2704 addr
= XEXP (addr
, 1);
2705 else if (CONSTANT_P (XEXP (addr
, 0)))
2706 addr
= XEXP (addr
, 1);
2707 else if (CONSTANT_P (XEXP (addr
, 1)))
2708 addr
= XEXP (addr
, 0);
2712 gcc_assert (GET_CODE (addr
) == REG
);
2716 /* Output assembler code to perform a 32-bit 3-operand add. */
2719 output_addsi3 (rtx
*operands
)
2721 if (! operands_match_p (operands
[0], operands
[1]))
2723 if (!ADDRESS_REG_P (operands
[1]))
2725 rtx tmp
= operands
[1];
2727 operands
[1] = operands
[2];
2731 /* These insns can result from reloads to access
2732 stack slots over 64k from the frame pointer. */
2733 if (GET_CODE (operands
[2]) == CONST_INT
2734 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2735 return "move%.l %2,%0\n\tadd%.l %1,%0";
2736 if (GET_CODE (operands
[2]) == REG
)
2737 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2738 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2740 if (GET_CODE (operands
[2]) == CONST_INT
)
2742 if (INTVAL (operands
[2]) > 0
2743 && INTVAL (operands
[2]) <= 8)
2744 return "addq%.l %2,%0";
2745 if (INTVAL (operands
[2]) < 0
2746 && INTVAL (operands
[2]) >= -8)
2748 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2749 return "subq%.l %2,%0";
2751 /* On the CPU32 it is faster to use two addql instructions to
2752 add a small integer (8 < N <= 16) to a register.
2753 Likewise for subql. */
2754 if (TUNE_CPU32
&& REG_P (operands
[0]))
2756 if (INTVAL (operands
[2]) > 8
2757 && INTVAL (operands
[2]) <= 16)
2759 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2760 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2762 if (INTVAL (operands
[2]) < -8
2763 && INTVAL (operands
[2]) >= -16)
2765 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2766 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2769 if (ADDRESS_REG_P (operands
[0])
2770 && INTVAL (operands
[2]) >= -0x8000
2771 && INTVAL (operands
[2]) < 0x8000)
2774 return "add%.w %2,%0";
2776 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2779 return "add%.l %2,%0";
2782 /* Store in cc_status the expressions that the condition codes will
2783 describe after execution of an instruction whose pattern is EXP.
2784 Do not alter them if the instruction would not alter the cc's. */
2786 /* On the 68000, all the insns to store in an address register fail to
2787 set the cc's. However, in some cases these instructions can make it
2788 possibly invalid to use the saved cc's. In those cases we clear out
2789 some or all of the saved cc's so they won't be used. */
2792 notice_update_cc (rtx exp
, rtx insn
)
2794 if (GET_CODE (exp
) == SET
)
2796 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2798 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2800 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2801 cc_status
.value1
= 0;
2802 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2803 cc_status
.value2
= 0;
2805 else if (!FP_REG_P (SET_DEST (exp
))
2806 && SET_DEST (exp
) != cc0_rtx
2807 && (FP_REG_P (SET_SRC (exp
))
2808 || GET_CODE (SET_SRC (exp
)) == FIX
2809 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2810 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2812 /* A pair of move insns doesn't produce a useful overall cc. */
2813 else if (!FP_REG_P (SET_DEST (exp
))
2814 && !FP_REG_P (SET_SRC (exp
))
2815 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2816 && (GET_CODE (SET_SRC (exp
)) == REG
2817 || GET_CODE (SET_SRC (exp
)) == MEM
2818 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2820 else if (SET_DEST (exp
) != pc_rtx
)
2822 cc_status
.flags
= 0;
2823 cc_status
.value1
= SET_DEST (exp
);
2824 cc_status
.value2
= SET_SRC (exp
);
2827 else if (GET_CODE (exp
) == PARALLEL
2828 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2830 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2831 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2833 if (ADDRESS_REG_P (dest
))
2835 else if (dest
!= pc_rtx
)
2837 cc_status
.flags
= 0;
2838 cc_status
.value1
= dest
;
2839 cc_status
.value2
= src
;
2844 if (cc_status
.value2
!= 0
2845 && ADDRESS_REG_P (cc_status
.value2
)
2846 && GET_MODE (cc_status
.value2
) == QImode
)
2848 if (cc_status
.value2
!= 0)
2849 switch (GET_CODE (cc_status
.value2
))
2851 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2852 case ROTATE
: case ROTATERT
:
2853 /* These instructions always clear the overflow bit, and set
2854 the carry to the bit shifted out. */
2855 /* ??? We don't currently have a way to signal carry not valid,
2856 nor do we check for it in the branch insns. */
2860 case PLUS
: case MINUS
: case MULT
:
2861 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2862 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2863 cc_status
.flags
|= CC_NO_OVERFLOW
;
2866 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2867 ends with a move insn moving r2 in r2's mode.
2868 Thus, the cc's are set for r2.
2869 This can set N bit spuriously. */
2870 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2875 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2877 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2878 cc_status
.value2
= 0;
2879 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2880 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2881 cc_status
.flags
= CC_IN_68881
;
2885 output_move_const_double (rtx
*operands
)
2887 int code
= standard_68881_constant_p (operands
[1]);
2891 static char buf
[40];
2893 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2896 return "fmove%.d %1,%0";
2900 output_move_const_single (rtx
*operands
)
2902 int code
= standard_68881_constant_p (operands
[1]);
2906 static char buf
[40];
2908 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2911 return "fmove%.s %f1,%0";
2914 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2915 from the "fmovecr" instruction.
2916 The value, anded with 0xff, gives the code to use in fmovecr
2917 to get the desired constant. */
2919 /* This code has been fixed for cross-compilation. */
2921 static int inited_68881_table
= 0;
2923 static const char *const strings_68881
[7] = {
2933 static const int codes_68881
[7] = {
2943 REAL_VALUE_TYPE values_68881
[7];
2945 /* Set up values_68881 array by converting the decimal values
2946 strings_68881 to binary. */
2949 init_68881_table (void)
2953 enum machine_mode mode
;
2956 for (i
= 0; i
< 7; i
++)
2960 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2961 values_68881
[i
] = r
;
2963 inited_68881_table
= 1;
2967 standard_68881_constant_p (rtx x
)
2972 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2973 used at all on those chips. */
2977 if (! inited_68881_table
)
2978 init_68881_table ();
2980 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2982 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2984 for (i
= 0; i
< 6; i
++)
2986 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2987 return (codes_68881
[i
]);
2990 if (GET_MODE (x
) == SFmode
)
2993 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2994 return (codes_68881
[6]);
2996 /* larger powers of ten in the constants ram are not used
2997 because they are not equal to a `double' C constant. */
3001 /* If X is a floating-point constant, return the logarithm of X base 2,
3002 or 0 if X is not a power of 2. */
3005 floating_exact_log2 (rtx x
)
3007 REAL_VALUE_TYPE r
, r1
;
3010 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3012 if (REAL_VALUES_LESS (r
, dconst1
))
3015 exp
= real_exponent (&r
);
3016 real_2expN (&r1
, exp
);
3017 if (REAL_VALUES_EQUAL (r1
, r
))
3023 /* A C compound statement to output to stdio stream STREAM the
3024 assembler syntax for an instruction operand X. X is an RTL
3027 CODE is a value that can be used to specify one of several ways
3028 of printing the operand. It is used when identical operands
3029 must be printed differently depending on the context. CODE
3030 comes from the `%' specification that was used to request
3031 printing of the operand. If the specification was just `%DIGIT'
3032 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3033 is the ASCII code for LTR.
3035 If X is a register, this macro should print the register's name.
3036 The names can be found in an array `reg_names' whose type is
3037 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3039 When the machine description has a specification `%PUNCT' (a `%'
3040 followed by a punctuation character), this macro is called with
3041 a null pointer for X and the punctuation character for CODE.
3043 The m68k specific codes are:
3045 '.' for dot needed in Motorola-style opcode names.
3046 '-' for an operand pushing on the stack:
3047 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3048 '+' for an operand pushing on the stack:
3049 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3050 '@' for a reference to the top word on the stack:
3051 sp@, (sp) or (%sp) depending on the style of syntax.
3052 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3053 but & in SGS syntax).
3054 '!' for the cc register (used in an `and to cc' insn).
3055 '$' for the letter `s' in an op code, but only on the 68040.
3056 '&' for the letter `d' in an op code, but only on the 68040.
3057 '/' for register prefix needed by longlong.h.
3059 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3060 'd' to force memory addressing to be absolute, not relative.
3061 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3062 'o' for operands to go directly to output_operand_address (bypassing
3063 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
3064 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3065 or print pair of registers as rx:ry.
3070 print_operand (FILE *file
, rtx op
, int letter
)
3075 fprintf (file
, ".");
3077 else if (letter
== '#')
3078 asm_fprintf (file
, "%I");
3079 else if (letter
== '-')
3080 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3081 else if (letter
== '+')
3082 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3083 else if (letter
== '@')
3084 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3085 else if (letter
== '!')
3086 asm_fprintf (file
, "%Rfpcr");
3087 else if (letter
== '$')
3089 if (TARGET_68040_ONLY
)
3090 fprintf (file
, "s");
3092 else if (letter
== '&')
3094 if (TARGET_68040_ONLY
)
3095 fprintf (file
, "d");
3097 else if (letter
== '/')
3098 asm_fprintf (file
, "%R");
3099 else if (letter
== 'o')
3101 /* This is only for direct addresses with TARGET_PCREL */
3102 gcc_assert (GET_CODE (op
) == MEM
3103 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3105 output_addr_const (file
, XEXP (op
, 0));
3107 else if (GET_CODE (op
) == REG
)
3110 /* Print out the second register name of a register pair.
3111 I.e., R (6) => 7. */
3112 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3114 fputs (M68K_REGNAME(REGNO (op
)), file
);
3116 else if (GET_CODE (op
) == MEM
)
3118 output_address (XEXP (op
, 0));
3119 if (letter
== 'd' && ! TARGET_68020
3120 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3121 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3122 && INTVAL (XEXP (op
, 0)) < 0x8000
3123 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3124 fprintf (file
, MOTOROLA
? ".l" : ":l");
3126 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3129 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3130 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3132 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3135 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3136 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3138 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3141 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3142 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3146 /* Use `print_operand_address' instead of `output_addr_const'
3147 to ensure that we print relevant PIC stuff. */
3148 asm_fprintf (file
, "%I");
3150 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3151 print_operand_address (file
, op
);
3153 output_addr_const (file
, op
);
3158 /* A C compound statement to output to stdio stream STREAM the
3159 assembler syntax for an instruction operand that is a memory
3160 reference whose address is ADDR. ADDR is an RTL expression.
3162 Note that this contains a kludge that knows that the only reason
3163 we have an address (plus (label_ref...) (reg...)) when not generating
3164 PIC code is in the insn before a tablejump, and we know that m68k.md
3165 generates a label LInnn: on such an insn.
3167 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3168 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3170 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3171 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3172 we want. This difference can be accommodated by using an assembler
3173 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3174 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3175 macro. See m68k/sgs.h for an example; for versions without the bug.
3176 Some assemblers refuse all the above solutions. The workaround is to
3177 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3180 They also do not like things like "pea 1.w", so we simple leave off
3181 the .w on small constants.
3183 This routine is responsible for distinguishing between -fpic and -fPIC
3184 style relocations in an address. When generating -fpic code the
3185 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3186 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3189 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3190 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3191 #else /* !MOTOROLA */
3192 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3193 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3194 #endif /* !MOTOROLA */
3197 print_operand_address (FILE *file
, rtx addr
)
3199 register rtx reg1
, reg2
, breg
, ireg
;
3202 switch (GET_CODE (addr
))
3205 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3208 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3209 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3212 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3213 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3216 reg1
= reg2
= ireg
= breg
= offset
= 0;
3217 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3219 offset
= XEXP (addr
, 0);
3220 addr
= XEXP (addr
, 1);
3222 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3224 offset
= XEXP (addr
, 1);
3225 addr
= XEXP (addr
, 0);
3227 if (GET_CODE (addr
) != PLUS
)
3231 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3233 reg1
= XEXP (addr
, 0);
3234 addr
= XEXP (addr
, 1);
3236 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3238 reg1
= XEXP (addr
, 1);
3239 addr
= XEXP (addr
, 0);
3241 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3243 reg1
= XEXP (addr
, 0);
3244 addr
= XEXP (addr
, 1);
3246 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3248 reg1
= XEXP (addr
, 1);
3249 addr
= XEXP (addr
, 0);
3251 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3253 reg1
= XEXP (addr
, 0);
3254 addr
= XEXP (addr
, 1);
3256 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3258 reg1
= XEXP (addr
, 1);
3259 addr
= XEXP (addr
, 0);
3261 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3262 || GET_CODE (addr
) == SIGN_EXTEND
)
3270 #if 0 /* for OLD_INDEXING */
3271 else if (GET_CODE (addr
) == PLUS
)
3273 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3275 reg2
= XEXP (addr
, 0);
3276 addr
= XEXP (addr
, 1);
3278 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3280 reg2
= XEXP (addr
, 1);
3281 addr
= XEXP (addr
, 0);
3290 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3291 || GET_CODE (reg1
) == MULT
))
3292 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3297 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3302 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3303 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3306 if (GET_CODE (ireg
) == MULT
)
3308 scale
= INTVAL (XEXP (ireg
, 1));
3309 ireg
= XEXP (ireg
, 0);
3311 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3313 ASM_OUTPUT_CASE_FETCH (file
,
3314 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3315 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3316 fprintf (file
, "w");
3320 ASM_OUTPUT_CASE_FETCH (file
,
3321 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3322 M68K_REGNAME (REGNO (ireg
)));
3323 fprintf (file
, "l");
3326 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3330 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3331 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3333 ASM_OUTPUT_CASE_FETCH (file
,
3334 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3335 M68K_REGNAME (REGNO (breg
)));
3336 fprintf (file
, "l)");
3339 if (ireg
!= 0 || breg
!= 0)
3344 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3350 output_addr_const (file
, addr
);
3351 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3353 fprintf (file
, "@GOT");
3355 fprintf (file
, ".w");
3358 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3362 else /* !MOTOROLA */
3364 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3367 output_addr_const (file
, addr
);
3368 if (breg
== pic_offset_table_rtx
)
3372 fprintf (file
, ":w");
3375 fprintf (file
, ":l");
3384 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3386 scale
= INTVAL (XEXP (ireg
, 1));
3387 ireg
= XEXP (ireg
, 0);
3389 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3390 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3391 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3393 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3394 M68K_REGNAME (REGNO (ireg
)));
3396 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3400 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3401 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3403 ASM_OUTPUT_CASE_FETCH (file
,
3404 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3405 M68K_REGNAME (REGNO (reg1
)));
3406 fprintf (file
, "l)");
3409 /* FALL-THROUGH (is this really what we want?) */
3411 if (GET_CODE (addr
) == CONST_INT
3412 && INTVAL (addr
) < 0x8000
3413 && INTVAL (addr
) >= -0x8000)
3415 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3417 else if (GET_CODE (addr
) == CONST_INT
)
3419 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3421 else if (TARGET_PCREL
)
3424 output_addr_const (file
, addr
);
3426 asm_fprintf (file
, ":w,%Rpc)");
3428 asm_fprintf (file
, ":l,%Rpc)");
3432 /* Special case for SYMBOL_REF if the symbol name ends in
3433 `.<letter>', this can be mistaken as a size suffix. Put
3434 the name in parentheses. */
3435 if (GET_CODE (addr
) == SYMBOL_REF
3436 && strlen (XSTR (addr
, 0)) > 2
3437 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3440 output_addr_const (file
, addr
);
3444 output_addr_const (file
, addr
);
3450 /* Check for cases where a clr insns can be omitted from code using
3451 strict_low_part sets. For example, the second clrl here is not needed:
3452 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3454 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3455 insn we are checking for redundancy. TARGET is the register set by the
3459 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3464 p
= prev_nonnote_insn (first_insn
);
3468 /* If it isn't an insn, then give up. */
3469 if (GET_CODE (p
) != INSN
)
3472 if (reg_set_p (target
, p
))
3474 rtx set
= single_set (p
);
3477 /* If it isn't an easy to recognize insn, then give up. */
3481 dest
= SET_DEST (set
);
3483 /* If this sets the entire target register to zero, then our
3484 first_insn is redundant. */
3485 if (rtx_equal_p (dest
, target
)
3486 && SET_SRC (set
) == const0_rtx
)
3488 else if (GET_CODE (dest
) == STRICT_LOW_PART
3489 && GET_CODE (XEXP (dest
, 0)) == REG
3490 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3491 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3492 <= GET_MODE_SIZE (mode
)))
3493 /* This is a strict low part set which modifies less than
3494 we are using, so it is safe. */
3500 p
= prev_nonnote_insn (p
);
3506 /* Operand predicates for implementing asymmetric pc-relative addressing
3507 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3508 when used as a source operand, but not as a destination operand.
3510 We model this by restricting the meaning of the basic predicates
3511 (general_operand, memory_operand, etc) to forbid the use of this
3512 addressing mode, and then define the following predicates that permit
3513 this addressing mode. These predicates can then be used for the
3514 source operands of the appropriate instructions.
3516 n.b. While it is theoretically possible to change all machine patterns
3517 to use this addressing more where permitted by the architecture,
3518 it has only been implemented for "common" cases: SImode, HImode, and
3519 QImode operands, and only for the principle operations that would
3520 require this addressing mode: data movement and simple integer operations.
3522 In parallel with these new predicates, two new constraint letters
3523 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3524 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3525 In the pcrel case 's' is only valid in combination with 'a' registers.
3526 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3527 of how these constraints are used.
3529 The use of these predicates is strictly optional, though patterns that
3530 don't will cause an extra reload register to be allocated where one
3533 lea (abc:w,%pc),%a0 ; need to reload address
3534 moveq &1,%d1 ; since write to pc-relative space
3535 movel %d1,%a0@ ; is not allowed
3537 lea (abc:w,%pc),%a1 ; no need to reload address here
3538 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3540 For more info, consult tiemann@cygnus.com.
3543 All of the ugliness with predicates and constraints is due to the
3544 simple fact that the m68k does not allow a pc-relative addressing
3545 mode as a destination. gcc does not distinguish between source and
3546 destination addresses. Hence, if we claim that pc-relative address
3547 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3548 end up with invalid code. To get around this problem, we left
3549 pc-relative modes as invalid addresses, and then added special
3550 predicates and constraints to accept them.
3552 A cleaner way to handle this is to modify gcc to distinguish
3553 between source and destination addresses. We can then say that
3554 pc-relative is a valid source address but not a valid destination
3555 address, and hopefully avoid a lot of the predicate and constraint
3556 hackery. Unfortunately, this would be a pretty big change. It would
3557 be a useful change for a number of ports, but there aren't any current
3558 plans to undertake this.
3560 ***************************************************************************/
3564 output_andsi3 (rtx
*operands
)
3567 if (GET_CODE (operands
[2]) == CONST_INT
3568 && (INTVAL (operands
[2]) | 0xffff) == -1
3569 && (DATA_REG_P (operands
[0])
3570 || offsettable_memref_p (operands
[0]))
3571 && !TARGET_COLDFIRE
)
3573 if (GET_CODE (operands
[0]) != REG
)
3574 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3575 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3576 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3578 if (operands
[2] == const0_rtx
)
3580 return "and%.w %2,%0";
3582 if (GET_CODE (operands
[2]) == CONST_INT
3583 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3584 && (DATA_REG_P (operands
[0])
3585 || offsettable_memref_p (operands
[0])))
3587 if (DATA_REG_P (operands
[0]))
3588 operands
[1] = GEN_INT (logval
);
3591 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3592 operands
[1] = GEN_INT (logval
% 8);
3594 /* This does not set condition codes in a standard way. */
3596 return "bclr %1,%0";
3598 return "and%.l %2,%0";
3602 output_iorsi3 (rtx
*operands
)
3604 register int logval
;
3605 if (GET_CODE (operands
[2]) == CONST_INT
3606 && INTVAL (operands
[2]) >> 16 == 0
3607 && (DATA_REG_P (operands
[0])
3608 || offsettable_memref_p (operands
[0]))
3609 && !TARGET_COLDFIRE
)
3611 if (GET_CODE (operands
[0]) != REG
)
3612 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3613 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3615 if (INTVAL (operands
[2]) == 0xffff)
3616 return "mov%.w %2,%0";
3617 return "or%.w %2,%0";
3619 if (GET_CODE (operands
[2]) == CONST_INT
3620 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3621 && (DATA_REG_P (operands
[0])
3622 || offsettable_memref_p (operands
[0])))
3624 if (DATA_REG_P (operands
[0]))
3625 operands
[1] = GEN_INT (logval
);
3628 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3629 operands
[1] = GEN_INT (logval
% 8);
3632 return "bset %1,%0";
3634 return "or%.l %2,%0";
3638 output_xorsi3 (rtx
*operands
)
3640 register int logval
;
3641 if (GET_CODE (operands
[2]) == CONST_INT
3642 && INTVAL (operands
[2]) >> 16 == 0
3643 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3644 && !TARGET_COLDFIRE
)
3646 if (! DATA_REG_P (operands
[0]))
3647 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3648 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3650 if (INTVAL (operands
[2]) == 0xffff)
3652 return "eor%.w %2,%0";
3654 if (GET_CODE (operands
[2]) == CONST_INT
3655 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3656 && (DATA_REG_P (operands
[0])
3657 || offsettable_memref_p (operands
[0])))
3659 if (DATA_REG_P (operands
[0]))
3660 operands
[1] = GEN_INT (logval
);
3663 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3664 operands
[1] = GEN_INT (logval
% 8);
3667 return "bchg %1,%0";
3669 return "eor%.l %2,%0";
3672 #ifdef M68K_TARGET_COFF
3674 /* Output assembly to switch to section NAME with attribute FLAGS. */
3677 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3678 tree decl ATTRIBUTE_UNUSED
)
3682 if (flags
& SECTION_WRITE
)
3687 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3690 #endif /* M68K_TARGET_COFF */
3693 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3694 HOST_WIDE_INT delta
,
3695 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3701 if (delta
> 0 && delta
<= 8)
3702 asm_fprintf (file
, (MOTOROLA
3703 ? "\taddq.l %I%d,4(%Rsp)\n"
3704 : "\taddql %I%d,%Rsp@(4)\n"),
3706 else if (delta
< 0 && delta
>= -8)
3707 asm_fprintf (file
, (MOTOROLA
3708 ? "\tsubq.l %I%d,4(%Rsp)\n"
3709 : "\tsubql %I%d,%Rsp@(4)\n"),
3711 else if (TARGET_COLDFIRE
)
3713 /* ColdFire can't add/sub a constant to memory unless it is in
3714 the range of addq/subq. So load the value into %d0 and
3715 then add it to 4(%sp). */
3716 if (delta
>= -128 && delta
<= 127)
3717 asm_fprintf (file
, (MOTOROLA
3718 ? "\tmoveq.l %I%wd,%Rd0\n"
3719 : "\tmoveql %I%wd,%Rd0\n"),
3722 asm_fprintf (file
, (MOTOROLA
3723 ? "\tmove.l %I%wd,%Rd0\n"
3724 : "\tmovel %I%wd,%Rd0\n"),
3726 asm_fprintf (file
, (MOTOROLA
3727 ? "\tadd.l %Rd0,4(%Rsp)\n"
3728 : "\taddl %Rd0,%Rsp@(4)\n"));
3731 asm_fprintf (file
, (MOTOROLA
3732 ? "\tadd.l %I%wd,4(%Rsp)\n"
3733 : "\taddl %I%wd,%Rsp@(4)\n"),
3736 xops
[0] = DECL_RTL (function
);
3738 /* Logic taken from call patterns in m68k.md. */
3743 else if (flag_pic
== 1 || TARGET_68020
)
3747 #if defined (USE_GAS)
3748 fmt
= "bra.l %0@PLTPC";
3750 fmt
= "bra %0@PLTPC";
3753 else /* !MOTOROLA */
3762 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3763 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3765 fmt
= "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)";
3769 #if MOTOROLA && !defined (USE_GAS)
3776 output_asm_insn (fmt
, xops
);
3779 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3782 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3783 int incoming ATTRIBUTE_UNUSED
)
3785 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3788 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3790 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3791 unsigned int new_reg
)
3794 /* Interrupt functions can only use registers that have already been
3795 saved by the prologue, even if they would normally be
3798 if (m68k_interrupt_function_p (current_function_decl
)
3799 && !regs_ever_live
[new_reg
])
3805 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3806 On the 68000, the cpu registers can hold any mode except bytes in address
3807 registers, but the 68881 registers can hold only SFmode or DFmode. */
3809 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3813 /* Data Registers, can hold aggregate if fits in. */
3814 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3817 else if (regno
< 16)
3819 /* Address Registers, can't hold bytes, can hold aggregate if
3821 if (GET_MODE_SIZE (mode
) == 1)
3823 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3826 else if (regno
< 24)
3828 /* FPU registers, hold float or complex float of long double or
3830 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3831 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3832 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3838 /* Return floating point values in a 68881 register. This makes 68881 code
3839 a little bit faster. It also makes -msoft-float code incompatible with
3840 hard-float code, so people have to be careful not to mix the two.
3841 For ColdFire it was decided the ABI incompatibility is undesirable.
3842 If there is need for a hard-float ABI it is probably worth doing it
3843 properly and also passing function arguments in FP registers. */
3845 m68k_libcall_value (enum machine_mode mode
)
3852 return gen_rtx_REG (mode
, 16);
3857 return gen_rtx_REG (mode
, 0);
3861 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3863 enum machine_mode mode
;
3865 mode
= TYPE_MODE (valtype
);
3871 return gen_rtx_REG (mode
, 16);
3877 /* If the function returns a pointer, push that into %a0 */
3878 if (POINTER_TYPE_P (valtype
))
3879 return gen_rtx_REG (mode
, 8);
3881 return gen_rtx_REG (mode
, 0);