1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* Structure describing stack frame layout. */
49 /* Stack pointer to frame pointer offset. */
52 /* Offset of FPU registers. */
53 HOST_WIDE_INT foffset
;
55 /* Frame size in bytes (rounded up). */
58 /* Data and address register. */
60 unsigned int reg_mask
;
61 unsigned int reg_rev_mask
;
65 unsigned int fpu_mask
;
66 unsigned int fpu_rev_mask
;
68 /* Offsets relative to ARG_POINTER. */
69 HOST_WIDE_INT frame_pointer_offset
;
70 HOST_WIDE_INT stack_pointer_offset
;
72 /* Function which the above information refers to. */
76 /* Current frame information calculated by m68k_compute_frame_layout(). */
77 static struct m68k_frame current_frame
;
79 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
80 if SGS_SWITCH_TABLE. */
81 int switch_table_difference_label_flag
;
83 static rtx
find_addr_reg (rtx
);
84 static const char *singlemove_string (rtx
*);
85 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
86 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
87 #ifdef M68K_TARGET_COFF
88 static void m68k_coff_asm_named_section (const char *, unsigned int);
89 #endif /* M68K_TARGET_COFF */
91 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
92 static void m68k_hp320_file_start (void);
94 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
96 static bool m68k_interrupt_function_p (tree func
);
97 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
100 static void m68k_compute_frame_layout (void);
101 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
102 static int const_int_cost (rtx
);
103 static bool m68k_rtx_costs (rtx
, int, int, int *);
106 /* Alignment to use for loops and jumps */
107 /* Specify power of two alignment used for loops. */
108 const char *m68k_align_loops_string
;
109 /* Specify power of two alignment used for non-loop jumps. */
110 const char *m68k_align_jumps_string
;
111 /* Specify power of two alignment used for functions. */
112 const char *m68k_align_funcs_string
;
113 /* Specify the identification number of the library being built */
114 const char *m68k_library_id_string
;
116 /* Specify power of two alignment used for loops. */
117 int m68k_align_loops
;
118 /* Specify power of two alignment used for non-loop jumps. */
119 int m68k_align_jumps
;
120 /* Specify power of two alignment used for functions. */
121 int m68k_align_funcs
;
123 /* Nonzero if the last compare/test insn had FP operands. The
124 sCC expanders peek at this to determine what to do for the
125 68060, which has no fsCC instructions. */
126 int m68k_last_compare_had_fp_operands
;
128 /* Initialize the GCC target structure. */
130 #if INT_OP_GROUP == INT_OP_DOT_WORD
131 #undef TARGET_ASM_ALIGNED_HI_OP
132 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
135 #if INT_OP_GROUP == INT_OP_NO_DOT
136 #undef TARGET_ASM_BYTE_OP
137 #define TARGET_ASM_BYTE_OP "\tbyte\t"
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
140 #undef TARGET_ASM_ALIGNED_SI_OP
141 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
144 #if INT_OP_GROUP == INT_OP_DC
145 #undef TARGET_ASM_BYTE_OP
146 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
147 #undef TARGET_ASM_ALIGNED_HI_OP
148 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
149 #undef TARGET_ASM_ALIGNED_SI_OP
150 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
153 #undef TARGET_ASM_UNALIGNED_HI_OP
154 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
155 #undef TARGET_ASM_UNALIGNED_SI_OP
156 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
158 #undef TARGET_ASM_FUNCTION_PROLOGUE
159 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
160 #undef TARGET_ASM_FUNCTION_EPILOGUE
161 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
163 #undef TARGET_ASM_INTERNAL_LABEL
164 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
167 #undef TARGET_ASM_OUTPUT_MI_THUNK
168 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
169 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
170 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
172 #undef TARGET_ASM_FILE_START_APP_OFF
173 #define TARGET_ASM_FILE_START_APP_OFF true
175 #undef TARGET_RTX_COSTS
176 #define TARGET_RTX_COSTS m68k_rtx_costs
178 #undef TARGET_ATTRIBUTE_TABLE
179 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
181 static const struct attribute_spec m68k_attribute_table
[] =
183 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
184 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
185 { NULL
, 0, 0, false, false, false, NULL
}
188 struct gcc_target targetm
= TARGET_INITIALIZER
;
190 /* Sometimes certain combinations of command options do not make
191 sense on a particular target machine. You can define a macro
192 `OVERRIDE_OPTIONS' to take account of this. This macro, if
193 defined, is executed once just after all the command options have
196 Don't use this macro to turn on various extra optimizations for
197 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
200 override_options (void)
207 /* Validate -malign-loops= value, or provide default */
208 m68k_align_loops
= def_align
;
209 if (m68k_align_loops_string
)
211 i
= atoi (m68k_align_loops_string
);
212 if (i
< 1 || i
> MAX_CODE_ALIGN
)
213 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
215 m68k_align_loops
= i
;
218 /* Library identification */
219 if (m68k_library_id_string
)
223 if (! TARGET_ID_SHARED_LIBRARY
)
224 error ("-mshared-library-id= specified without -mid-shared-library");
225 id
= atoi (m68k_library_id_string
);
226 if (id
< 0 || id
> MAX_LIBRARY_ID
)
227 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
229 /* From now on, m68k_library_id_string will contain the library offset. */
230 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
233 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
235 m68k_library_id_string
= "_current_shared_library_a5_offset_";
237 /* Sanity check to ensure that msep-data and mid-sahred-library are not
238 * both specified together. Doing so simply doesn't make sense.
240 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
241 error ("cannot specify both -msep-data and -mid-shared-library");
243 /* If we're generating code for a separate A5 relative data segment,
244 * we've got to enable -fPIC as well. This might be relaxable to
245 * -fpic but it hasn't been tested properly.
247 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
250 /* Validate -malign-jumps= value, or provide default */
251 m68k_align_jumps
= def_align
;
252 if (m68k_align_jumps_string
)
254 i
= atoi (m68k_align_jumps_string
);
255 if (i
< 1 || i
> MAX_CODE_ALIGN
)
256 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
258 m68k_align_jumps
= i
;
261 /* Validate -malign-functions= value, or provide default */
262 m68k_align_funcs
= def_align
;
263 if (m68k_align_funcs_string
)
265 i
= atoi (m68k_align_funcs_string
);
266 if (i
< 1 || i
> MAX_CODE_ALIGN
)
267 error ("-malign-functions=%d is not between 1 and %d",
270 m68k_align_funcs
= i
;
273 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
275 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
276 error("-fPIC is not currently supported on the 68000 or 68010\n");
278 /* ??? A historic way of turning on pic, or is this intended to
279 be an embedded thing that doesn't have the same name binding
280 significance that it does on hosted ELF systems? */
281 if (TARGET_PCREL
&& flag_pic
== 0)
284 /* Turn off function cse if we are doing PIC. We always want function call
285 to be done as `bsr foo@PLTPC', so it will force the assembler to create
286 the PLT entry for `foo'. Doing function cse will cause the address of
287 `foo' to be loaded into a register, which is exactly what we want to
288 avoid when we are doing PIC on svr4 m68k. */
290 flag_no_function_cse
= 1;
292 SUBTARGET_OVERRIDE_OPTIONS
;
295 /* Return nonzero if FUNC is an interrupt function as specified by the
296 "interrupt_handler" attribute. */
298 m68k_interrupt_function_p(tree func
)
302 if (TREE_CODE (func
) != FUNCTION_DECL
)
305 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
306 return (a
!= NULL_TREE
);
309 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
310 struct attribute_spec.handler. */
312 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
313 tree args ATTRIBUTE_UNUSED
,
314 int flags ATTRIBUTE_UNUSED
,
317 if (TREE_CODE (*node
) != FUNCTION_DECL
)
319 warning ("`%s' attribute only applies to functions",
320 IDENTIFIER_POINTER (name
));
321 *no_add_attrs
= true;
328 m68k_compute_frame_layout (void)
331 unsigned int mask
, rmask
;
332 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
334 /* Only compute the frame once per function.
335 Don't cache information until reload has been completed. */
336 if (current_frame
.funcdef_no
== current_function_funcdef_no
340 current_frame
.size
= (get_frame_size () + 3) & -4;
342 mask
= rmask
= saved
= 0;
343 for (regno
= 0; regno
< 16; regno
++)
344 if (m68k_save_reg (regno
, interrupt_handler
))
347 rmask
|= 1 << (15 - regno
);
350 current_frame
.offset
= saved
* 4;
351 current_frame
.reg_no
= saved
;
352 current_frame
.reg_mask
= mask
;
353 current_frame
.reg_rev_mask
= rmask
;
355 if (TARGET_68881
/* || TARGET_CFV4E */)
357 mask
= rmask
= saved
= 0;
358 for (regno
= 16; regno
< 24; regno
++)
359 if (m68k_save_reg (regno
, interrupt_handler
))
361 mask
|= 1 << (23 - regno
);
362 rmask
|= 1 << (regno
- 16);
365 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
366 current_frame
.offset
+= current_frame
.foffset
;
367 current_frame
.fpu_no
= saved
;
368 current_frame
.fpu_mask
= mask
;
369 current_frame
.fpu_rev_mask
= rmask
;
372 /* Remember what function this frame refers to. */
373 current_frame
.funcdef_no
= current_function_funcdef_no
;
377 m68k_initial_elimination_offset (int from
, int to
)
379 /* FIXME: The correct offset to compute here would appear to be
380 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
381 but for some obscure reason, this must be 0 to get correct code. */
382 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
385 m68k_compute_frame_layout ();
387 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
388 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
389 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
390 return current_frame
.offset
+ current_frame
.size
;
395 /* Return true if we need to save REGNO. */
397 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
399 if (flag_pic
&& current_function_uses_pic_offset_table
400 && regno
== PIC_OFFSET_TABLE_REGNUM
)
403 if (current_function_calls_eh_return
)
408 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
409 if (test
== INVALID_REGNUM
)
416 /* Fixed regs we never touch. */
417 if (fixed_regs
[regno
])
420 /* The frame pointer (if it is such) is handled specially. */
421 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
424 /* Interrupt handlers must also save call_used_regs
425 if they are live or when calling nested functions. */
426 if (interrupt_handler
)
428 if (regs_ever_live
[regno
])
431 if (!current_function_is_leaf
&& call_used_regs
[regno
])
435 /* Never need to save registers that aren't touched. */
436 if (!regs_ever_live
[regno
])
439 /* Otherwise save everything that isn't call-clobbered. */
440 return !call_used_regs
[regno
];
443 /* This function generates the assembly code for function entry.
444 STREAM is a stdio stream to output the code to.
445 SIZE is an int: how many units of temporary storage to allocate.
446 Refer to the array `regs_ever_live' to determine which registers
447 to save; `regs_ever_live[I]' is nonzero if register number I
448 is ever used in the function. This function is responsible for
449 knowing which registers should not be saved even if used. */
452 /* Note that the order of the bit mask for fmovem is the opposite
453 of the order for movem! */
456 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
458 int num_saved_regs
= 0;
459 HOST_WIDE_INT fsize_with_regs
;
460 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
462 m68k_compute_frame_layout();
464 /* If the stack limit is a symbol, we can check it here,
465 before actually allocating the space. */
466 if (current_function_limit_stack
467 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
469 #if defined (MOTOROLA)
470 asm_fprintf (stream
, "\tcmp.l %I%s+%wd,%Rsp\n\ttrapcs\n",
471 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
473 asm_fprintf (stream
, "\tcmpl %I%s+%wd,%Rsp\n\ttrapcs\n",
474 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
478 /* on ColdFire add register save into initial stack frame setup, if possible */
480 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
481 num_saved_regs
= current_frame
.reg_no
;
483 fsize_with_regs
= current_frame
.size
+ num_saved_regs
* 4;
485 if (frame_pointer_needed
)
487 if (current_frame
.size
== 0 && TARGET_68040
)
489 /* on the 68040, pea + move is faster than link.w 0 */
491 fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
492 reg_names
[FRAME_POINTER_REGNUM
],
493 reg_names
[STACK_POINTER_REGNUM
],
494 reg_names
[FRAME_POINTER_REGNUM
]);
496 fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
497 reg_names
[FRAME_POINTER_REGNUM
],
498 reg_names
[STACK_POINTER_REGNUM
],
499 reg_names
[FRAME_POINTER_REGNUM
]);
502 else if (fsize_with_regs
< 0x8000)
505 asm_fprintf (stream
, "\tlink.w %s,%I%wd\n",
506 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
508 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
509 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
512 else if (TARGET_68020
)
515 asm_fprintf (stream
, "\tlink.l %s,%I%wd\n",
516 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
518 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
519 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
524 /* Adding negative number is faster on the 68040. */
526 asm_fprintf (stream
, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
527 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
529 asm_fprintf (stream
, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
530 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
533 if (dwarf2out_do_frame ())
536 l
= (char *) dwarf2out_cfi_label ();
538 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
539 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
540 cfa_offset
+= current_frame
.size
;
543 else if (fsize_with_regs
) /* !frame_pointer_needed */
545 if (fsize_with_regs
< 0x8000)
547 if (fsize_with_regs
<= 8)
549 if (!TARGET_COLDFIRE
)
551 /* asm_fprintf() cannot handle %. */
553 asm_fprintf (stream
, "\tsubq.w %I%wd,%Rsp\n", fsize_with_regs
);
555 asm_fprintf (stream
, "\tsubqw %I%wd,%Rsp\n", fsize_with_regs
);
560 /* asm_fprintf() cannot handle %. */
562 asm_fprintf (stream
, "\tsubq.l %I%wd,%Rsp\n", fsize_with_regs
);
564 asm_fprintf (stream
, "\tsubql %I%wd,%Rsp\n", fsize_with_regs
);
568 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
570 /* On the CPU32 it is faster to use two subqw instructions to
571 subtract a small integer (8 < N <= 16) to a register. */
572 /* asm_fprintf() cannot handle %. */
575 "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
576 fsize_with_regs
- 8);
578 asm_fprintf (stream
, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
579 fsize_with_regs
- 8);
582 else if (TARGET_68040
)
584 /* Adding negative number is faster on the 68040. */
585 /* asm_fprintf() cannot handle %. */
587 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", -fsize_with_regs
);
589 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", -fsize_with_regs
);
595 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", -fsize_with_regs
);
597 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", -fsize_with_regs
);
601 else /* fsize_with_regs >= 0x8000 */
604 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", -fsize_with_regs
);
606 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", -fsize_with_regs
);
609 if (dwarf2out_do_frame ())
611 cfa_offset
+= current_frame
.size
+ 4;
612 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
614 } /* !frame_pointer_needed */
618 if (current_frame
.fpu_mask
)
621 asm_fprintf (stream
, "\tfmovm %I0x%x,-(%Rsp)\n", current_frame
.fpu_mask
);
623 asm_fprintf (stream
, "\tfmovem %I0x%x,%Rsp@-\n", current_frmae
.fpu_mask
);
625 if (dwarf2out_do_frame ())
627 char *l
= (char *) dwarf2out_cfi_label ();
630 cfa_offset
+= current_frame
.fpu_no
* 12;
631 if (! frame_pointer_needed
)
632 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
633 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
634 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
635 dwarf2out_reg_save (l
, regno
,
636 -cfa_offset
+ n_regs
++ * 12);
641 /* If the stack limit is not a symbol, check it here.
642 This has the disadvantage that it may be too late... */
643 if (current_function_limit_stack
)
645 if (REG_P (stack_limit_rtx
))
647 #if defined (MOTOROLA)
648 asm_fprintf (stream
, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
649 reg_names
[REGNO (stack_limit_rtx
)]);
651 asm_fprintf (stream
, "\tcmpl %s,%Rsp\n\ttrapcs\n",
652 reg_names
[REGNO (stack_limit_rtx
)]);
655 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
656 warning ("stack limit expression is not supported");
659 if (num_saved_regs
<= 2)
661 /* Store each separately in the same order moveml uses.
662 Using two movel instructions instead of a single moveml
663 is about 15% faster for the 68020 and 68030 at no expense
668 for (i
= 0; i
< 16; i
++)
669 if (current_frame
.reg_rev_mask
& (1 << i
))
673 "\t%Omove.l %s,-(%Rsp)\n",
675 "\tmovel %s,%Rsp@-\n",
678 if (dwarf2out_do_frame ())
680 char *l
= (char *) dwarf2out_cfi_label ();
683 if (! frame_pointer_needed
)
684 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
685 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
689 else if (current_frame
.reg_rev_mask
)
693 /* The ColdFire does not support the predecrement form of the
694 MOVEM instruction, so we must adjust the stack pointer and
695 then use the plain address register indirect mode.
696 The required register save space was combined earlier with
697 the fsize_with_regs amount. */
700 asm_fprintf (stream
, "\tmovm.l %I0x%x,(%Rsp)\n", current_frame
.reg_mask
);
702 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@\n", current_frame
.reg_mask
);
708 asm_fprintf (stream
, "\tmovm.l %I0x%x,-(%Rsp)\n", current_frame
.reg_mask
);
710 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@-\n", current_frame
.reg_mask
);
713 if (dwarf2out_do_frame ())
715 char *l
= (char *) dwarf2out_cfi_label ();
718 cfa_offset
+= current_frame
.reg_no
* 4;
719 if (! frame_pointer_needed
)
720 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
721 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
722 if (current_frame
.reg_mask
& (1 << regno
))
723 dwarf2out_reg_save (l
, regno
,
724 -cfa_offset
+ n_regs
++ * 4);
727 if (!TARGET_SEP_DATA
&& flag_pic
&&
728 (current_function_uses_pic_offset_table
||
729 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
731 if (TARGET_ID_SHARED_LIBRARY
)
733 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
734 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
735 m68k_library_id_string
,
736 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
741 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
742 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
744 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
745 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
746 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
747 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
748 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
754 /* Return true if this function's epilogue can be output as RTL. */
757 use_return_insn (void)
759 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
762 /* We can output the epilogue as RTL only if no registers need to be
764 m68k_compute_frame_layout();
765 return current_frame
.reg_no
? false : true;
768 /* This function generates the assembly code for function exit,
769 on machines that need it.
771 The function epilogue should not depend on the current stack pointer!
772 It should use the frame pointer only, if there is a frame pointer.
773 This is mandatory because of alloca; we also take advantage of it to
774 omit stack adjustments before returning. */
777 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
779 HOST_WIDE_INT fsize
, fsize_with_regs
;
781 bool restore_from_sp
= false;
782 rtx insn
= get_last_insn ();
784 m68k_compute_frame_layout();
786 /* If the last insn was a BARRIER, we don't have to write any code. */
787 if (GET_CODE (insn
) == NOTE
)
788 insn
= prev_nonnote_insn (insn
);
789 if (insn
&& GET_CODE (insn
) == BARRIER
)
791 /* Output just a no-op so that debuggers don't get confused
792 about which function the pc is in at this address. */
793 fprintf (stream
, "\tnop\n");
797 #ifdef FUNCTION_EXTRA_EPILOGUE
798 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
801 fsize
= current_frame
.size
;
803 /* FIXME : leaf_function_p below is too strong.
804 What we really need to know there is if there could be pending
805 stack adjustment needed at that point. */
806 restore_from_sp
= ! frame_pointer_needed
807 || (! current_function_calls_alloca
&& leaf_function_p ());
809 /* fsize_with_regs is the size we need to adjust the sp when
811 fsize_with_regs
= fsize
;
813 /* Because the ColdFire doesn't support moveml with
814 complex address modes, we must adjust the stack manually
815 after restoring registers. When the frame pointer isn't used,
816 we can merge movem adjustment into frame unlinking
817 made immediately after it. */
818 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
819 fsize_with_regs
+= current_frame
.reg_no
* 4;
821 if (current_frame
.offset
+ fsize
>= 0x8000
823 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
825 /* Because the ColdFire doesn't support moveml with
826 complex address modes we make an extra correction here */
830 asm_fprintf (stream
, "\t%Omove.l %I%d,%Ra1\n",
831 -fsize
- current_frame
.offset
);
833 asm_fprintf (stream
, "\tmovel %I%d,%Ra1\n",
834 -fsize
- current_frame
.offset
);
840 asm_fprintf (stream
, "\t%Omove.l %I%wd,%Ra1\n", -fsize
);
842 asm_fprintf (stream
, "\tmovel %I%wd,%Ra1\n", -fsize
);
846 fsize
= 0, big
= true;
848 if (current_frame
.reg_no
<= 2)
850 /* Restore each separately in the same order moveml does.
851 Using two movel instructions instead of a single moveml
852 is about 15% faster for the 68020 and 68030 at no expense
856 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
858 for (i
= 0; i
< 16; i
++)
859 if (current_frame
.reg_mask
& (1 << i
))
864 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
866 reg_names
[FRAME_POINTER_REGNUM
],
869 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
870 reg_names
[FRAME_POINTER_REGNUM
],
874 else if (restore_from_sp
)
877 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
880 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
887 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
889 reg_names
[FRAME_POINTER_REGNUM
],
892 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
893 reg_names
[FRAME_POINTER_REGNUM
],
901 else if (current_frame
.reg_mask
)
903 /* The ColdFire requires special handling due to its limited moveml insn */
909 asm_fprintf (stream
, "\tadd.l %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
910 asm_fprintf (stream
, "\tmovm.l (%Ra1),%I0x%x\n", current_frame
.reg_mask
);
912 asm_fprintf (stream
, "\taddl %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
913 asm_fprintf (stream
, "\tmoveml %Ra1@,%I0x%x\n", current_frame
.reg_mask
);
916 else if (restore_from_sp
)
919 asm_fprintf (stream
, "\tmovm.l (%Rsp),%I0x%x\n", current_frame
.reg_mask
);
921 asm_fprintf (stream
, "\tmoveml %Rsp@,%I0x%x\n", current_frame
.reg_mask
);
927 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
928 current_frame
.offset
+ fsize
,
929 reg_names
[FRAME_POINTER_REGNUM
],
930 current_frame
.reg_mask
);
932 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
933 reg_names
[FRAME_POINTER_REGNUM
],
935 current_frame
.reg_mask
);
939 else /* !TARGET_COLDFIRE */
944 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
945 current_frame
.offset
+ fsize
,
946 reg_names
[FRAME_POINTER_REGNUM
],
947 current_frame
.reg_mask
);
949 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
950 reg_names
[FRAME_POINTER_REGNUM
],
951 current_frame
.offset
+ fsize
,
952 current_frame
.reg_mask
);
955 else if (restore_from_sp
)
958 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%I0x%x\n",
959 current_frame
.reg_mask
);
961 asm_fprintf (stream
, "\tmoveml %Rsp@+,%I0x%x\n",
962 current_frame
.reg_mask
);
968 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
969 current_frame
.offset
+ fsize
,
970 reg_names
[FRAME_POINTER_REGNUM
],
971 current_frame
.reg_mask
);
973 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
974 reg_names
[FRAME_POINTER_REGNUM
],
975 current_frame
.offset
+ fsize
,
976 current_frame
.reg_mask
);
981 if (current_frame
.fpu_rev_mask
)
986 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
987 current_frame
.foffset
+ fsize
,
988 reg_names
[FRAME_POINTER_REGNUM
],
989 current_frame
.fpu_rev_mask
);
991 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
992 reg_names
[FRAME_POINTER_REGNUM
],
993 current_frame
.foffset
+ fsize
,
994 current_frame
.fpu_rev_mask
);
997 else if (restore_from_sp
)
1000 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
1001 current_frame
.fpu_rev_mask
);
1003 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
1004 current_frame
.fpu_rev_mask
);
1010 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1011 current_frame
.foffset
+ fsize
,
1012 reg_names
[FRAME_POINTER_REGNUM
],
1013 current_frame
.fpu_mask
);
1015 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1016 reg_names
[FRAME_POINTER_REGNUM
],
1017 current_frame
.foffset
+ fsize
,
1018 current_frame
.fpu_rev_mask
);
1022 if (frame_pointer_needed
)
1023 fprintf (stream
, "\tunlk %s\n",
1024 reg_names
[FRAME_POINTER_REGNUM
]);
1025 else if (fsize_with_regs
)
1027 if (fsize_with_regs
<= 8)
1029 if (!TARGET_COLDFIRE
)
1032 asm_fprintf (stream
, "\taddq.w %I%wd,%Rsp\n", fsize_with_regs
);
1034 asm_fprintf (stream
, "\taddqw %I%wd,%Rsp\n", fsize_with_regs
);
1037 else /* TARGET_COLDFIRE */
1040 asm_fprintf (stream
, "\taddq.l %I%wd,%Rsp\n", fsize_with_regs
);
1042 asm_fprintf (stream
, "\taddql %I%wd,%Rsp\n", fsize_with_regs
);
1046 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
1048 /* On the CPU32 it is faster to use two addqw instructions to
1049 add a small integer (8 < N <= 16) to a register. */
1051 asm_fprintf (stream
, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
1052 fsize_with_regs
- 8);
1054 asm_fprintf (stream
, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
1055 fsize_with_regs
- 8);
1058 else if (fsize_with_regs
< 0x8000)
1063 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", fsize_with_regs
);
1065 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", fsize_with_regs
);
1071 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", fsize_with_regs
);
1073 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", fsize_with_regs
);
1080 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", fsize_with_regs
);
1082 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", fsize_with_regs
);
1086 if (current_function_calls_eh_return
)
1089 asm_fprintf (stream
, "\tadd.l %Ra0,%Rsp\n");
1091 asm_fprintf (stream
, "\taddl %Ra0,%Rsp\n");
1094 if (m68k_interrupt_function_p (current_function_decl
))
1095 fprintf (stream
, "\trte\n");
1096 else if (current_function_pops_args
)
1097 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1099 fprintf (stream
, "\trts\n");
1102 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1105 not_sp_operand (rtx op
, enum machine_mode mode
)
1107 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
1110 /* Return true if X is a valid comparison operator for the dbcc
1113 Note it rejects floating point comparison operators.
1114 (In the future we could use Fdbcc).
1116 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1119 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1121 switch (GET_CODE (x
))
1123 case EQ
: case NE
: case GTU
: case LTU
:
1127 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1129 case GT
: case LT
: case GE
: case LE
:
1130 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1136 /* Return nonzero if flags are currently in the 68881 flag register. */
1138 flags_in_68881 (void)
1140 /* We could add support for these in the future */
1141 return cc_status
.flags
& CC_IN_68881
;
1144 /* Output a BSR instruction suitable for PIC code. */
1146 m68k_output_pic_call(rtx dest
)
1150 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1152 /* We output a BSR instruction if we're using -fpic or we're building for
1153 * a target that supports long branches. If we're building -fPIC on the
1154 * 68000, 68010 or ColdFire we generate one of two sequences:
1155 * a shorter one that uses a GOT entry or a longer one that doesn't.
1156 * We'll use the -Os command-line flag to decide which to generate.
1157 * Both sequences take the same time to execute on the ColdFire.
1159 else if (TARGET_PCREL
)
1161 else if ((flag_pic
== 1) || TARGET_68020
)
1164 #elif defined(USE_GAS)
1165 out
= "bsr.l %0@PLTPC";
1167 out
= "bsr %0@PLTPC";
1169 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1170 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1172 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1174 output_asm_insn(out
, &dest
);
1177 /* Output a dbCC; jCC sequence. Note we do not handle the
1178 floating point version of this sequence (Fdbcc). We also
1179 do not handle alternative conditions when CC_NO_OVERFLOW is
1180 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1181 kick those out before we get here. */
1184 output_dbcc_and_branch (rtx
*operands
)
1186 switch (GET_CODE (operands
[3]))
1190 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
1192 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1198 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
1200 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1206 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
1208 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1214 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
1216 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1222 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
1224 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1230 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
1232 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1238 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
1240 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1246 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
1248 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1254 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
1256 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1262 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
1264 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1272 /* If the decrement is to be done in SImode, then we have
1273 to compensate for the fact that dbcc decrements in HImode. */
1274 switch (GET_MODE (operands
[0]))
1278 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
1280 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1293 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1296 enum rtx_code op_code
= GET_CODE (op
);
1298 /* This does not produce a useful cc. */
1301 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1302 below. Swap the operands and change the op if these requirements
1303 are not fulfilled. */
1304 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1308 operand1
= operand2
;
1310 op_code
= swap_condition (op_code
);
1312 loperands
[0] = operand1
;
1313 if (GET_CODE (operand1
) == REG
)
1314 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1316 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1317 if (operand2
!= const0_rtx
)
1319 loperands
[2] = operand2
;
1320 if (GET_CODE (operand2
) == REG
)
1321 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1323 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1325 loperands
[4] = gen_label_rtx();
1326 if (operand2
!= const0_rtx
)
1329 #ifdef SGS_CMP_ORDER
1330 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1332 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1335 #ifdef SGS_CMP_ORDER
1336 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1338 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1344 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1345 output_asm_insn ("tst%.l %0", loperands
);
1348 #ifdef SGS_CMP_ORDER
1349 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1351 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1356 output_asm_insn ("jbne %l4", loperands
);
1358 output_asm_insn ("jne %l4", loperands
);
1361 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1362 output_asm_insn ("tst%.l %1", loperands
);
1365 #ifdef SGS_CMP_ORDER
1366 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1368 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1373 loperands
[5] = dest
;
1378 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1379 CODE_LABEL_NUMBER (loperands
[4]));
1380 output_asm_insn ("seq %5", loperands
);
1384 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1385 CODE_LABEL_NUMBER (loperands
[4]));
1386 output_asm_insn ("sne %5", loperands
);
1390 loperands
[6] = gen_label_rtx();
1392 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1394 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1396 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1397 CODE_LABEL_NUMBER (loperands
[4]));
1398 output_asm_insn ("sgt %5", loperands
);
1399 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1400 CODE_LABEL_NUMBER (loperands
[6]));
1404 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1405 CODE_LABEL_NUMBER (loperands
[4]));
1406 output_asm_insn ("shi %5", loperands
);
1410 loperands
[6] = gen_label_rtx();
1412 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1414 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1416 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1417 CODE_LABEL_NUMBER (loperands
[4]));
1418 output_asm_insn ("slt %5", loperands
);
1419 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1420 CODE_LABEL_NUMBER (loperands
[6]));
1424 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1425 CODE_LABEL_NUMBER (loperands
[4]));
1426 output_asm_insn ("scs %5", loperands
);
1430 loperands
[6] = gen_label_rtx();
1432 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1434 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1436 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1437 CODE_LABEL_NUMBER (loperands
[4]));
1438 output_asm_insn ("sge %5", loperands
);
1439 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1440 CODE_LABEL_NUMBER (loperands
[6]));
1444 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1445 CODE_LABEL_NUMBER (loperands
[4]));
1446 output_asm_insn ("scc %5", loperands
);
1450 loperands
[6] = gen_label_rtx();
1452 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1454 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1456 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1457 CODE_LABEL_NUMBER (loperands
[4]));
1458 output_asm_insn ("sle %5", loperands
);
1459 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1460 CODE_LABEL_NUMBER (loperands
[6]));
1464 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1465 CODE_LABEL_NUMBER (loperands
[4]));
1466 output_asm_insn ("sls %5", loperands
);
1476 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1478 operands
[0] = countop
;
1479 operands
[1] = dataop
;
1481 if (GET_CODE (countop
) == CONST_INT
)
1483 register int count
= INTVAL (countop
);
1484 /* If COUNT is bigger than size of storage unit in use,
1485 advance to the containing unit of same size. */
1486 if (count
> signpos
)
1488 int offset
= (count
& ~signpos
) / 8;
1489 count
= count
& signpos
;
1490 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1492 if (count
== signpos
)
1493 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1495 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1497 /* These three statements used to use next_insns_test_no...
1498 but it appears that this should do the same job. */
1500 && next_insn_tests_no_inequality (insn
))
1503 && next_insn_tests_no_inequality (insn
))
1506 && next_insn_tests_no_inequality (insn
))
1509 cc_status
.flags
= CC_NOT_NEGATIVE
;
1511 return "btst %0,%1";
1514 /* Returns true if OP is either a symbol reference or a sum of a symbol
1515 reference and a constant. */
1518 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1520 switch (GET_CODE (op
))
1528 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1529 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1530 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1532 #if 0 /* Deleted, with corresponding change in m68k.h,
1533 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1535 return GET_MODE (op
) == mode
;
1543 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1546 extend_operator(rtx x
, enum machine_mode mode
)
1548 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1550 switch (GET_CODE(x
))
1561 /* Legitimize PIC addresses. If the address is already
1562 position-independent, we return ORIG. Newly generated
1563 position-independent addresses go to REG. If we need more
1564 than one register, we lose.
1566 An address is legitimized by making an indirect reference
1567 through the Global Offset Table with the name of the symbol
1570 The assembler and linker are responsible for placing the
1571 address of the symbol in the GOT. The function prologue
1572 is responsible for initializing a5 to the starting address
1575 The assembler is also responsible for translating a symbol name
1576 into a constant displacement from the start of the GOT.
1578 A quick example may make things a little clearer:
1580 When not generating PIC code to store the value 12345 into _foo
1581 we would generate the following code:
1585 When generating PIC two transformations are made. First, the compiler
1586 loads the address of foo into a register. So the first transformation makes:
1591 The code in movsi will intercept the lea instruction and call this
1592 routine which will transform the instructions into:
1594 movel a5@(_foo:w), a0
1598 That (in a nutshell) is how *all* symbol and label references are
1602 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1607 /* First handle a simple SYMBOL_REF or LABEL_REF */
1608 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1613 pic_ref
= gen_rtx_MEM (Pmode
,
1614 gen_rtx_PLUS (Pmode
,
1615 pic_offset_table_rtx
, orig
));
1616 current_function_uses_pic_offset_table
= 1;
1617 RTX_UNCHANGING_P (pic_ref
) = 1;
1618 emit_move_insn (reg
, pic_ref
);
1621 else if (GET_CODE (orig
) == CONST
)
1625 /* Make sure this has not already been legitimized. */
1626 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1627 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1633 /* legitimize both operands of the PLUS */
1634 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1636 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1637 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1638 base
== reg
? 0 : reg
);
1642 if (GET_CODE (orig
) == CONST_INT
)
1643 return plus_constant (base
, INTVAL (orig
));
1644 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1645 /* Likewise, should we set special REG_NOTEs here? */
1651 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1653 static CONST_METHOD
const_method (rtx
);
1655 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1658 const_method (rtx constant
)
1663 i
= INTVAL (constant
);
1667 /* The ColdFire doesn't have byte or word operations. */
1668 /* FIXME: This may not be useful for the m68060 either */
1669 if (!TARGET_COLDFIRE
)
1671 /* if -256 < N < 256 but N is not in range for a moveq
1672 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1673 if (USE_MOVQ (i
^ 0xff))
1675 /* Likewise, try with not.w */
1676 if (USE_MOVQ (i
^ 0xffff))
1678 /* This is the only value where neg.w is useful */
1681 /* Try also with swap */
1683 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1686 /* Otherwise, use move.l */
1691 const_int_cost (rtx constant
)
1693 switch (const_method (constant
))
1696 /* Constants between -128 and 127 are cheap due to moveq */
1702 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1712 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1717 /* Constant zero is super cheap due to clr instruction. */
1718 if (x
== const0_rtx
)
1721 *total
= const_int_cost (x
);
1731 /* Make 0.0 cheaper than other floating constants to
1732 encourage creating tstsf and tstdf insns. */
1733 if (outer_code
== COMPARE
1734 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1740 /* These are vaguely right for a 68020. */
1741 /* The costs for long multiply have been adjusted to work properly
1742 in synth_mult on the 68020, relative to an average of the time
1743 for add and the time for shift, taking away a little more because
1744 sometimes move insns are needed. */
1745 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1746 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1747 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1748 TARGET_CFV3 ? 2 : 5)
1749 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1752 /* An lea costs about three times as much as a simple add. */
1753 if (GET_MODE (x
) == SImode
1754 && GET_CODE (XEXP (x
, 1)) == REG
1755 && GET_CODE (XEXP (x
, 0)) == MULT
1756 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1757 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1758 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1759 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1760 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1762 /* lea an@(dx:l:i),am */
1763 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1773 *total
= COSTS_N_INSNS(1);
1776 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1778 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1780 if (INTVAL (XEXP (x
, 1)) < 16)
1781 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1783 /* We're using clrw + swap for these cases. */
1784 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1787 *total
= COSTS_N_INSNS (10); /* worst case */
1790 /* A shift by a big integer takes an extra instruction. */
1791 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1792 && (INTVAL (XEXP (x
, 1)) == 16))
1794 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1797 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1798 && !(INTVAL (XEXP (x
, 1)) > 0
1799 && INTVAL (XEXP (x
, 1)) <= 8))
1801 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1807 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1808 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1809 && GET_MODE (x
) == SImode
)
1810 *total
= COSTS_N_INSNS (MULW_COST
);
1811 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1812 *total
= COSTS_N_INSNS (MULW_COST
);
1814 *total
= COSTS_N_INSNS (MULL_COST
);
1821 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1822 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1823 else if (TARGET_CF_HWDIV
)
1824 *total
= COSTS_N_INSNS (18);
1826 *total
= COSTS_N_INSNS (43); /* div.l */
1835 output_move_const_into_data_reg (rtx
*operands
)
1839 i
= INTVAL (operands
[1]);
1840 switch (const_method (operands
[1]))
1843 return "moveq %1,%0";
1845 operands
[1] = GEN_INT (i
^ 0xff);
1846 return "moveq %1,%0\n\tnot%.b %0";
1848 operands
[1] = GEN_INT (i
^ 0xffff);
1849 return "moveq %1,%0\n\tnot%.w %0";
1851 return "moveq %#-128,%0\n\tneg%.w %0";
1856 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1857 return "moveq %1,%0\n\tswap %0";
1860 return "move%.l %1,%0";
1867 output_move_simode_const (rtx
*operands
)
1869 if (operands
[1] == const0_rtx
1870 && (DATA_REG_P (operands
[0])
1871 || GET_CODE (operands
[0]) == MEM
)
1872 /* clr insns on 68000 read before writing.
1873 This isn't so on the 68010, but we have no TARGET_68010. */
1874 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1875 || !(GET_CODE (operands
[0]) == MEM
1876 && MEM_VOLATILE_P (operands
[0]))))
1878 else if (operands
[1] == const0_rtx
1879 && ADDRESS_REG_P (operands
[0]))
1880 return "sub%.l %0,%0";
1881 else if (DATA_REG_P (operands
[0]))
1882 return output_move_const_into_data_reg (operands
);
1883 else if (ADDRESS_REG_P (operands
[0])
1884 && INTVAL (operands
[1]) < 0x8000
1885 && INTVAL (operands
[1]) >= -0x8000)
1886 return "move%.w %1,%0";
1887 else if (GET_CODE (operands
[0]) == MEM
1888 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1889 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1890 && INTVAL (operands
[1]) < 0x8000
1891 && INTVAL (operands
[1]) >= -0x8000)
1893 return "move%.l %1,%0";
1897 output_move_simode (rtx
*operands
)
1899 if (GET_CODE (operands
[1]) == CONST_INT
)
1900 return output_move_simode_const (operands
);
1901 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1902 || GET_CODE (operands
[1]) == CONST
)
1903 && push_operand (operands
[0], SImode
))
1905 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1906 || GET_CODE (operands
[1]) == CONST
)
1907 && ADDRESS_REG_P (operands
[0]))
1908 return "lea %a1,%0";
1909 return "move%.l %1,%0";
1913 output_move_himode (rtx
*operands
)
1915 if (GET_CODE (operands
[1]) == CONST_INT
)
1917 if (operands
[1] == const0_rtx
1918 && (DATA_REG_P (operands
[0])
1919 || GET_CODE (operands
[0]) == MEM
)
1920 /* clr insns on 68000 read before writing.
1921 This isn't so on the 68010, but we have no TARGET_68010. */
1922 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1923 || !(GET_CODE (operands
[0]) == MEM
1924 && MEM_VOLATILE_P (operands
[0]))))
1926 else if (operands
[1] == const0_rtx
1927 && ADDRESS_REG_P (operands
[0]))
1928 return "sub%.l %0,%0";
1929 else if (DATA_REG_P (operands
[0])
1930 && INTVAL (operands
[1]) < 128
1931 && INTVAL (operands
[1]) >= -128)
1933 return "moveq %1,%0";
1935 else if (INTVAL (operands
[1]) < 0x8000
1936 && INTVAL (operands
[1]) >= -0x8000)
1937 return "move%.w %1,%0";
1939 else if (CONSTANT_P (operands
[1]))
1940 return "move%.l %1,%0";
1941 /* Recognize the insn before a tablejump, one that refers
1942 to a table of offsets. Such an insn will need to refer
1943 to a label on the insn. So output one. Use the label-number
1944 of the table of offsets to generate this label. This code,
1945 and similar code below, assumes that there will be at most one
1946 reference to each table. */
1947 if (GET_CODE (operands
[1]) == MEM
1948 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1949 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1950 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1952 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1953 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1955 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1956 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1958 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1959 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1960 #endif /* not SGS */
1961 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1962 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1963 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1964 #ifdef SGS_SWITCH_TABLES
1965 /* Set flag saying we need to define the symbol
1966 LD%n (with value L%n-LI%n) at the end of the switch table. */
1967 switch_table_difference_label_flag
= 1;
1968 #endif /* SGS_SWITCH_TABLES */
1969 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1971 return "move%.w %1,%0";
1975 output_move_qimode (rtx
*operands
)
1979 /* This is probably useless, since it loses for pushing a struct
1980 of several bytes a byte at a time. */
1981 /* 68k family always modifies the stack pointer by at least 2, even for
1982 byte pushes. The 5200 (ColdFire) does not do this. */
1983 if (GET_CODE (operands
[0]) == MEM
1984 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1985 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1986 && ! ADDRESS_REG_P (operands
[1])
1987 && ! TARGET_COLDFIRE
)
1989 xoperands
[1] = operands
[1];
1991 = gen_rtx_MEM (QImode
,
1992 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1993 /* Just pushing a byte puts it in the high byte of the halfword. */
1994 /* We must put it in the low-order, high-numbered byte. */
1995 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1997 xoperands
[3] = stack_pointer_rtx
;
1998 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
2001 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
2005 /* clr and st insns on 68000 read before writing.
2006 This isn't so on the 68010, but we have no TARGET_68010. */
2007 if (!ADDRESS_REG_P (operands
[0])
2008 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2009 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2011 if (operands
[1] == const0_rtx
)
2013 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2014 && GET_CODE (operands
[1]) == CONST_INT
2015 && (INTVAL (operands
[1]) & 255) == 255)
2021 if (GET_CODE (operands
[1]) == CONST_INT
2022 && DATA_REG_P (operands
[0])
2023 && INTVAL (operands
[1]) < 128
2024 && INTVAL (operands
[1]) >= -128)
2026 return "moveq %1,%0";
2028 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2029 return "sub%.l %0,%0";
2030 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2031 return "move%.l %1,%0";
2032 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2033 from address registers. */
2034 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2035 return "move%.w %1,%0";
2036 return "move%.b %1,%0";
2040 output_move_stricthi (rtx
*operands
)
2042 if (operands
[1] == const0_rtx
2043 /* clr insns on 68000 read before writing.
2044 This isn't so on the 68010, but we have no TARGET_68010. */
2045 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2046 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2048 return "move%.w %1,%0";
2052 output_move_strictqi (rtx
*operands
)
2054 if (operands
[1] == const0_rtx
2055 /* clr insns on 68000 read before writing.
2056 This isn't so on the 68010, but we have no TARGET_68010. */
2057 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2058 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2060 return "move%.b %1,%0";
2063 /* Return the best assembler insn template
2064 for moving operands[1] into operands[0] as a fullword. */
2067 singlemove_string (rtx
*operands
)
2069 if (GET_CODE (operands
[1]) == CONST_INT
)
2070 return output_move_simode_const (operands
);
2071 return "move%.l %1,%0";
2075 /* Output assembler code to perform a doubleword move insn
2076 with operands OPERANDS. */
2079 output_move_double (rtx
*operands
)
2083 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2088 rtx addreg0
= 0, addreg1
= 0;
2089 int dest_overlapped_low
= 0;
2090 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2095 /* First classify both operands. */
2097 if (REG_P (operands
[0]))
2099 else if (offsettable_memref_p (operands
[0]))
2101 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2103 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2105 else if (GET_CODE (operands
[0]) == MEM
)
2110 if (REG_P (operands
[1]))
2112 else if (CONSTANT_P (operands
[1]))
2114 else if (offsettable_memref_p (operands
[1]))
2116 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2118 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2120 else if (GET_CODE (operands
[1]) == MEM
)
2125 /* Check for the cases that the operand constraints are not
2126 supposed to allow to happen. Abort if we get one,
2127 because generating code for these cases is painful. */
2129 if (optype0
== RNDOP
|| optype1
== RNDOP
)
2132 /* If one operand is decrementing and one is incrementing
2133 decrement the former register explicitly
2134 and change that operand into ordinary indexing. */
2136 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2138 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2140 output_asm_insn ("sub%.l %#12,%0", operands
);
2142 output_asm_insn ("subq%.l %#8,%0", operands
);
2143 if (GET_MODE (operands
[1]) == XFmode
)
2144 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2145 else if (GET_MODE (operands
[0]) == DFmode
)
2146 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2148 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2151 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2153 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2155 output_asm_insn ("sub%.l %#12,%1", operands
);
2157 output_asm_insn ("subq%.l %#8,%1", operands
);
2158 if (GET_MODE (operands
[1]) == XFmode
)
2159 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2160 else if (GET_MODE (operands
[1]) == DFmode
)
2161 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2163 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2167 /* If an operand is an unoffsettable memory ref, find a register
2168 we can increment temporarily to make it refer to the second word. */
2170 if (optype0
== MEMOP
)
2171 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2173 if (optype1
== MEMOP
)
2174 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2176 /* Ok, we can do one word at a time.
2177 Normally we do the low-numbered word first,
2178 but if either operand is autodecrementing then we
2179 do the high-numbered word first.
2181 In either case, set up in LATEHALF the operands to use
2182 for the high-numbered word and in some cases alter the
2183 operands in OPERANDS to be suitable for the low-numbered word. */
2187 if (optype0
== REGOP
)
2189 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2190 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2192 else if (optype0
== OFFSOP
)
2194 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2195 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2199 middlehalf
[0] = operands
[0];
2200 latehalf
[0] = operands
[0];
2203 if (optype1
== REGOP
)
2205 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2206 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2208 else if (optype1
== OFFSOP
)
2210 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2211 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2213 else if (optype1
== CNSTOP
)
2215 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2220 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2221 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2222 operands
[1] = GEN_INT (l
[0]);
2223 middlehalf
[1] = GEN_INT (l
[1]);
2224 latehalf
[1] = GEN_INT (l
[2]);
2226 else if (CONSTANT_P (operands
[1]))
2228 /* actually, no non-CONST_DOUBLE constant should ever
2231 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2232 latehalf
[1] = constm1_rtx
;
2234 latehalf
[1] = const0_rtx
;
2239 middlehalf
[1] = operands
[1];
2240 latehalf
[1] = operands
[1];
2244 /* size is not 12: */
2246 if (optype0
== REGOP
)
2247 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2248 else if (optype0
== OFFSOP
)
2249 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2251 latehalf
[0] = operands
[0];
2253 if (optype1
== REGOP
)
2254 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2255 else if (optype1
== OFFSOP
)
2256 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2257 else if (optype1
== CNSTOP
)
2258 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2260 latehalf
[1] = operands
[1];
2263 /* If insn is effectively movd N(sp),-(sp) then we will do the
2264 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2265 for the low word as well, to compensate for the first decrement of sp. */
2266 if (optype0
== PUSHOP
2267 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2268 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2269 operands
[1] = middlehalf
[1] = latehalf
[1];
2271 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2272 if the upper part of reg N does not appear in the MEM, arrange to
2273 emit the move late-half first. Otherwise, compute the MEM address
2274 into the upper part of N and use that as a pointer to the memory
2276 if (optype0
== REGOP
2277 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2279 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2281 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2282 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2284 /* If both halves of dest are used in the src memory address,
2285 compute the address into latehalf of dest.
2286 Note that this can't happen if the dest is two data regs. */
2288 xops
[0] = latehalf
[0];
2289 xops
[1] = XEXP (operands
[1], 0);
2290 output_asm_insn ("lea %a1,%0", xops
);
2291 if (GET_MODE (operands
[1]) == XFmode
)
2293 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2294 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2295 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2299 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2300 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2304 && reg_overlap_mentioned_p (middlehalf
[0],
2305 XEXP (operands
[1], 0)))
2307 /* Check for two regs used by both source and dest.
2308 Note that this can't happen if the dest is all data regs.
2309 It can happen if the dest is d6, d7, a0.
2310 But in that case, latehalf is an addr reg, so
2311 the code at compadr does ok. */
2313 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2314 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2317 /* JRV says this can't happen: */
2318 if (addreg0
|| addreg1
)
2321 /* Only the middle reg conflicts; simply put it last. */
2322 output_asm_insn (singlemove_string (operands
), operands
);
2323 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2324 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2327 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2328 /* If the low half of dest is mentioned in the source memory
2329 address, the arrange to emit the move late half first. */
2330 dest_overlapped_low
= 1;
2333 /* If one or both operands autodecrementing,
2334 do the two words, high-numbered first. */
2336 /* Likewise, the first move would clobber the source of the second one,
2337 do them in the other order. This happens only for registers;
2338 such overlap can't happen in memory unless the user explicitly
2339 sets it up, and that is an undefined circumstance. */
2341 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2342 || (optype0
== REGOP
&& optype1
== REGOP
2343 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2344 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2345 || dest_overlapped_low
)
2347 /* Make any unoffsettable addresses point at high-numbered word. */
2351 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2353 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2358 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2360 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2364 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2366 /* Undo the adds we just did. */
2368 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2370 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2374 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2376 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2378 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2381 /* Do low-numbered word. */
2382 return singlemove_string (operands
);
2385 /* Normal case: do the two words, low-numbered first. */
2387 output_asm_insn (singlemove_string (operands
), operands
);
2389 /* Do the middle one of the three words for long double */
2393 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2395 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2397 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2400 /* Make any unoffsettable addresses point at high-numbered word. */
2402 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2404 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2407 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2409 /* Undo the adds we just did. */
2413 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2415 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2420 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2422 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2428 /* Return a REG that occurs in ADDR with coefficient 1.
2429 ADDR can be effectively incremented by incrementing REG. */
2432 find_addr_reg (rtx addr
)
2434 while (GET_CODE (addr
) == PLUS
)
2436 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2437 addr
= XEXP (addr
, 0);
2438 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2439 addr
= XEXP (addr
, 1);
2440 else if (CONSTANT_P (XEXP (addr
, 0)))
2441 addr
= XEXP (addr
, 1);
2442 else if (CONSTANT_P (XEXP (addr
, 1)))
2443 addr
= XEXP (addr
, 0);
2447 if (GET_CODE (addr
) == REG
)
2452 /* Output assembler code to perform a 32-bit 3-operand add. */
2455 output_addsi3 (rtx
*operands
)
2457 if (! operands_match_p (operands
[0], operands
[1]))
2459 if (!ADDRESS_REG_P (operands
[1]))
2461 rtx tmp
= operands
[1];
2463 operands
[1] = operands
[2];
2467 /* These insns can result from reloads to access
2468 stack slots over 64k from the frame pointer. */
2469 if (GET_CODE (operands
[2]) == CONST_INT
2470 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2471 return "move%.l %2,%0\n\tadd%.l %1,%0";
2473 if (GET_CODE (operands
[2]) == REG
)
2474 return "lea 0(%1,%2.l),%0";
2476 return "lea %c2(%1),%0";
2477 #elif defined(MOTOROLA)
2478 if (GET_CODE (operands
[2]) == REG
)
2479 return "lea (%1,%2.l),%0";
2481 return "lea (%c2,%1),%0";
2482 #else /* not MOTOROLA (MIT syntax) */
2483 if (GET_CODE (operands
[2]) == REG
)
2484 return "lea %1@(0,%2:l),%0";
2486 return "lea %1@(%c2),%0";
2487 #endif /* not MOTOROLA */
2489 if (GET_CODE (operands
[2]) == CONST_INT
)
2491 if (INTVAL (operands
[2]) > 0
2492 && INTVAL (operands
[2]) <= 8)
2493 return "addq%.l %2,%0";
2494 if (INTVAL (operands
[2]) < 0
2495 && INTVAL (operands
[2]) >= -8)
2497 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2498 return "subq%.l %2,%0";
2500 /* On the CPU32 it is faster to use two addql instructions to
2501 add a small integer (8 < N <= 16) to a register.
2502 Likewise for subql. */
2503 if (TARGET_CPU32
&& REG_P (operands
[0]))
2505 if (INTVAL (operands
[2]) > 8
2506 && INTVAL (operands
[2]) <= 16)
2508 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2509 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2511 if (INTVAL (operands
[2]) < -8
2512 && INTVAL (operands
[2]) >= -16)
2514 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2515 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2518 if (ADDRESS_REG_P (operands
[0])
2519 && INTVAL (operands
[2]) >= -0x8000
2520 && INTVAL (operands
[2]) < 0x8000)
2523 return "add%.w %2,%0";
2526 return "lea (%c2,%0),%0";
2528 return "lea %0@(%c2),%0";
2532 return "add%.l %2,%0";
2535 /* Store in cc_status the expressions that the condition codes will
2536 describe after execution of an instruction whose pattern is EXP.
2537 Do not alter them if the instruction would not alter the cc's. */
2539 /* On the 68000, all the insns to store in an address register fail to
2540 set the cc's. However, in some cases these instructions can make it
2541 possibly invalid to use the saved cc's. In those cases we clear out
2542 some or all of the saved cc's so they won't be used. */
2545 notice_update_cc (rtx exp
, rtx insn
)
2547 if (GET_CODE (exp
) == SET
)
2549 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2553 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2555 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2556 cc_status
.value1
= 0;
2557 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2558 cc_status
.value2
= 0;
2560 else if (!FP_REG_P (SET_DEST (exp
))
2561 && SET_DEST (exp
) != cc0_rtx
2562 && (FP_REG_P (SET_SRC (exp
))
2563 || GET_CODE (SET_SRC (exp
)) == FIX
2564 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2565 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2569 /* A pair of move insns doesn't produce a useful overall cc. */
2570 else if (!FP_REG_P (SET_DEST (exp
))
2571 && !FP_REG_P (SET_SRC (exp
))
2572 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2573 && (GET_CODE (SET_SRC (exp
)) == REG
2574 || GET_CODE (SET_SRC (exp
)) == MEM
2575 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2579 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2583 else if (XEXP (exp
, 0) != pc_rtx
)
2585 cc_status
.flags
= 0;
2586 cc_status
.value1
= XEXP (exp
, 0);
2587 cc_status
.value2
= XEXP (exp
, 1);
2590 else if (GET_CODE (exp
) == PARALLEL
2591 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2593 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2595 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2597 cc_status
.flags
= 0;
2598 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2599 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2604 if (cc_status
.value2
!= 0
2605 && ADDRESS_REG_P (cc_status
.value2
)
2606 && GET_MODE (cc_status
.value2
) == QImode
)
2608 if (cc_status
.value2
!= 0)
2609 switch (GET_CODE (cc_status
.value2
))
2611 case PLUS
: case MINUS
: case MULT
:
2612 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2613 #if 0 /* These instructions always clear the overflow bit */
2614 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2615 case ROTATE
: case ROTATERT
:
2617 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2618 cc_status
.flags
|= CC_NO_OVERFLOW
;
2621 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2622 ends with a move insn moving r2 in r2's mode.
2623 Thus, the cc's are set for r2.
2624 This can set N bit spuriously. */
2625 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2630 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2632 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2633 cc_status
.value2
= 0;
2634 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2635 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2636 cc_status
.flags
= CC_IN_68881
;
2640 output_move_const_double (rtx
*operands
)
2642 int code
= standard_68881_constant_p (operands
[1]);
2646 static char buf
[40];
2648 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2651 return "fmove%.d %1,%0";
2655 output_move_const_single (rtx
*operands
)
2657 int code
= standard_68881_constant_p (operands
[1]);
2661 static char buf
[40];
2663 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2666 return "fmove%.s %f1,%0";
2669 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2670 from the "fmovecr" instruction.
2671 The value, anded with 0xff, gives the code to use in fmovecr
2672 to get the desired constant. */
2674 /* This code has been fixed for cross-compilation. */
2676 static int inited_68881_table
= 0;
2678 static const char *const strings_68881
[7] = {
2688 static const int codes_68881
[7] = {
2698 REAL_VALUE_TYPE values_68881
[7];
2700 /* Set up values_68881 array by converting the decimal values
2701 strings_68881 to binary. */
2704 init_68881_table (void)
2708 enum machine_mode mode
;
2711 for (i
= 0; i
< 7; i
++)
2715 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2716 values_68881
[i
] = r
;
2718 inited_68881_table
= 1;
2722 standard_68881_constant_p (rtx x
)
2727 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2728 used at all on those chips. */
2729 if (TARGET_68040
|| TARGET_68060
)
2732 if (! inited_68881_table
)
2733 init_68881_table ();
2735 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2737 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2739 for (i
= 0; i
< 6; i
++)
2741 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2742 return (codes_68881
[i
]);
2745 if (GET_MODE (x
) == SFmode
)
2748 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2749 return (codes_68881
[6]);
2751 /* larger powers of ten in the constants ram are not used
2752 because they are not equal to a `double' C constant. */
2756 /* If X is a floating-point constant, return the logarithm of X base 2,
2757 or 0 if X is not a power of 2. */
2760 floating_exact_log2 (rtx x
)
2762 REAL_VALUE_TYPE r
, r1
;
2765 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2767 if (REAL_VALUES_LESS (r
, dconst1
))
2770 exp
= real_exponent (&r
);
2771 real_2expN (&r1
, exp
);
2772 if (REAL_VALUES_EQUAL (r1
, r
))
2778 /* A C compound statement to output to stdio stream STREAM the
2779 assembler syntax for an instruction operand X. X is an RTL
2782 CODE is a value that can be used to specify one of several ways
2783 of printing the operand. It is used when identical operands
2784 must be printed differently depending on the context. CODE
2785 comes from the `%' specification that was used to request
2786 printing of the operand. If the specification was just `%DIGIT'
2787 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2788 is the ASCII code for LTR.
2790 If X is a register, this macro should print the register's name.
2791 The names can be found in an array `reg_names' whose type is
2792 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2794 When the machine description has a specification `%PUNCT' (a `%'
2795 followed by a punctuation character), this macro is called with
2796 a null pointer for X and the punctuation character for CODE.
2798 The m68k specific codes are:
2800 '.' for dot needed in Motorola-style opcode names.
2801 '-' for an operand pushing on the stack:
2802 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2803 '+' for an operand pushing on the stack:
2804 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2805 '@' for a reference to the top word on the stack:
2806 sp@, (sp) or (%sp) depending on the style of syntax.
2807 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2808 but & in SGS syntax).
2809 '!' for the cc register (used in an `and to cc' insn).
2810 '$' for the letter `s' in an op code, but only on the 68040.
2811 '&' for the letter `d' in an op code, but only on the 68040.
2812 '/' for register prefix needed by longlong.h.
2814 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2815 'd' to force memory addressing to be absolute, not relative.
2816 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2817 'o' for operands to go directly to output_operand_address (bypassing
2818 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2819 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2820 or print pair of registers as rx:ry.
2825 print_operand (FILE *file
, rtx op
, int letter
)
2829 #if defined (MOTOROLA)
2830 fprintf (file
, ".");
2833 else if (letter
== '#')
2835 asm_fprintf (file
, "%I");
2837 else if (letter
== '-')
2840 asm_fprintf (file
, "-(%Rsp)");
2842 asm_fprintf (file
, "%Rsp@-");
2845 else if (letter
== '+')
2848 asm_fprintf (file
, "(%Rsp)+");
2850 asm_fprintf (file
, "%Rsp@+");
2853 else if (letter
== '@')
2856 asm_fprintf (file
, "(%Rsp)");
2858 asm_fprintf (file
, "%Rsp@");
2861 else if (letter
== '!')
2863 asm_fprintf (file
, "%Rfpcr");
2865 else if (letter
== '$')
2867 if (TARGET_68040_ONLY
)
2869 fprintf (file
, "s");
2872 else if (letter
== '&')
2874 if (TARGET_68040_ONLY
)
2876 fprintf (file
, "d");
2879 else if (letter
== '/')
2881 asm_fprintf (file
, "%R");
2883 else if (letter
== 'o')
2885 /* This is only for direct addresses with TARGET_PCREL */
2886 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2889 output_addr_const (file
, XEXP (op
, 0));
2891 else if (GET_CODE (op
) == REG
)
2894 /* Print out the second register name of a register pair.
2895 I.e., R (6) => 7. */
2896 fputs (reg_names
[REGNO (op
) + 1], file
);
2898 fputs (reg_names
[REGNO (op
)], file
);
2900 else if (GET_CODE (op
) == MEM
)
2902 output_address (XEXP (op
, 0));
2903 if (letter
== 'd' && ! TARGET_68020
2904 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2905 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2906 && INTVAL (XEXP (op
, 0)) < 0x8000
2907 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2910 fprintf (file
, ".l");
2912 fprintf (file
, ":l");
2916 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2919 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2920 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2922 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2925 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2926 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2928 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2931 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2932 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2936 /* Use `print_operand_address' instead of `output_addr_const'
2937 to ensure that we print relevant PIC stuff. */
2938 asm_fprintf (file
, "%I");
2940 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2941 print_operand_address (file
, op
);
2943 output_addr_const (file
, op
);
2948 /* A C compound statement to output to stdio stream STREAM the
2949 assembler syntax for an instruction operand that is a memory
2950 reference whose address is ADDR. ADDR is an RTL expression.
2952 Note that this contains a kludge that knows that the only reason
2953 we have an address (plus (label_ref...) (reg...)) when not generating
2954 PIC code is in the insn before a tablejump, and we know that m68k.md
2955 generates a label LInnn: on such an insn.
2957 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2958 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2960 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2961 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2962 we want. This difference can be accommodated by using an assembler
2963 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2964 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2965 macro. See m68k/sgs.h for an example; for versions without the bug.
2966 Some assemblers refuse all the above solutions. The workaround is to
2967 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2970 They also do not like things like "pea 1.w", so we simple leave off
2971 the .w on small constants.
2973 This routine is responsible for distinguishing between -fpic and -fPIC
2974 style relocations in an address. When generating -fpic code the
2975 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2976 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2978 #ifndef ASM_OUTPUT_CASE_FETCH
2981 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2982 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2984 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2985 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2988 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2989 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2991 #endif /* ASM_OUTPUT_CASE_FETCH */
2994 print_operand_address (FILE *file
, rtx addr
)
2996 register rtx reg1
, reg2
, breg
, ireg
;
2999 switch (GET_CODE (addr
))
3003 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
3005 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
3010 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
3012 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
3017 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
3019 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
3023 reg1
= reg2
= ireg
= breg
= offset
= 0;
3024 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3026 offset
= XEXP (addr
, 0);
3027 addr
= XEXP (addr
, 1);
3029 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3031 offset
= XEXP (addr
, 1);
3032 addr
= XEXP (addr
, 0);
3034 if (GET_CODE (addr
) != PLUS
)
3038 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3040 reg1
= XEXP (addr
, 0);
3041 addr
= XEXP (addr
, 1);
3043 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3045 reg1
= XEXP (addr
, 1);
3046 addr
= XEXP (addr
, 0);
3048 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3050 reg1
= XEXP (addr
, 0);
3051 addr
= XEXP (addr
, 1);
3053 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3055 reg1
= XEXP (addr
, 1);
3056 addr
= XEXP (addr
, 0);
3058 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3060 reg1
= XEXP (addr
, 0);
3061 addr
= XEXP (addr
, 1);
3063 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3065 reg1
= XEXP (addr
, 1);
3066 addr
= XEXP (addr
, 0);
3068 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3069 || GET_CODE (addr
) == SIGN_EXTEND
)
3081 #if 0 /* for OLD_INDEXING */
3082 else if (GET_CODE (addr
) == PLUS
)
3084 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3086 reg2
= XEXP (addr
, 0);
3087 addr
= XEXP (addr
, 1);
3089 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3091 reg2
= XEXP (addr
, 1);
3092 addr
= XEXP (addr
, 0);
3104 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3105 || GET_CODE (reg1
) == MULT
))
3106 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3111 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3116 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3117 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3120 if (GET_CODE (ireg
) == MULT
)
3122 scale
= INTVAL (XEXP (ireg
, 1));
3123 ireg
= XEXP (ireg
, 0);
3125 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3127 ASM_OUTPUT_CASE_FETCH (file
,
3128 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3129 reg_names
[REGNO (XEXP (ireg
, 0))]);
3130 fprintf (file
, "w");
3134 ASM_OUTPUT_CASE_FETCH (file
,
3135 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3136 reg_names
[REGNO (ireg
)]);
3137 fprintf (file
, "l");
3142 fprintf (file
, "*%d", scale
);
3144 fprintf (file
, ":%d", scale
);
3150 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3151 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3153 ASM_OUTPUT_CASE_FETCH (file
,
3154 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3155 reg_names
[REGNO (breg
)]);
3156 fprintf (file
, "l)");
3159 if (ireg
!= 0 || breg
!= 0)
3166 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3173 output_addr_const (file
, addr
);
3174 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3176 fprintf (file
, "@GOT");
3178 fprintf (file
, ".w");
3181 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3187 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3190 output_addr_const (file
, addr
);
3191 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3192 fprintf (file
, ":w");
3193 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3194 fprintf (file
, ":l");
3196 if (addr
!= 0 && ireg
!= 0)
3201 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3203 scale
= INTVAL (XEXP (ireg
, 1));
3204 ireg
= XEXP (ireg
, 0);
3206 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3209 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3211 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3217 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3219 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3225 fprintf (file
, "*%d", scale
);
3227 fprintf (file
, ":%d", scale
);
3233 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3234 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3236 ASM_OUTPUT_CASE_FETCH (file
,
3237 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3238 reg_names
[REGNO (reg1
)]);
3239 fprintf (file
, "l)");
3242 /* FALL-THROUGH (is this really what we want?) */
3244 if (GET_CODE (addr
) == CONST_INT
3245 && INTVAL (addr
) < 0x8000
3246 && INTVAL (addr
) >= -0x8000)
3250 /* Many SGS assemblers croak on size specifiers for constants. */
3251 fprintf (file
, "%d", (int) INTVAL (addr
));
3253 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3256 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3259 else if (GET_CODE (addr
) == CONST_INT
)
3261 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3263 else if (TARGET_PCREL
)
3266 output_addr_const (file
, addr
);
3268 asm_fprintf (file
, ":w,%Rpc)");
3270 asm_fprintf (file
, ":l,%Rpc)");
3274 /* Special case for SYMBOL_REF if the symbol name ends in
3275 `.<letter>', this can be mistaken as a size suffix. Put
3276 the name in parentheses. */
3277 if (GET_CODE (addr
) == SYMBOL_REF
3278 && strlen (XSTR (addr
, 0)) > 2
3279 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3282 output_addr_const (file
, addr
);
3286 output_addr_const (file
, addr
);
3292 /* Check for cases where a clr insns can be omitted from code using
3293 strict_low_part sets. For example, the second clrl here is not needed:
3294 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3296 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3297 insn we are checking for redundancy. TARGET is the register set by the
3301 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3306 p
= prev_nonnote_insn (first_insn
);
3310 /* If it isn't an insn, then give up. */
3311 if (GET_CODE (p
) != INSN
)
3314 if (reg_set_p (target
, p
))
3316 rtx set
= single_set (p
);
3319 /* If it isn't an easy to recognize insn, then give up. */
3323 dest
= SET_DEST (set
);
3325 /* If this sets the entire target register to zero, then our
3326 first_insn is redundant. */
3327 if (rtx_equal_p (dest
, target
)
3328 && SET_SRC (set
) == const0_rtx
)
3330 else if (GET_CODE (dest
) == STRICT_LOW_PART
3331 && GET_CODE (XEXP (dest
, 0)) == REG
3332 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3333 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3334 <= GET_MODE_SIZE (mode
)))
3335 /* This is a strict low part set which modifies less than
3336 we are using, so it is safe. */
3342 p
= prev_nonnote_insn (p
);
3349 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3350 range carefully since this predicate is used in DImode contexts. Also, we
3351 need some extra crud to make it work when hosted on 64-bit machines. */
3354 const_uint32_operand (rtx op
, enum machine_mode mode
)
3356 /* It doesn't make sense to ask this question with a mode that is
3357 not larger than 32 bits. */
3358 if (GET_MODE_BITSIZE (mode
) <= 32)
3361 #if HOST_BITS_PER_WIDE_INT > 32
3362 /* All allowed constants will fit a CONST_INT. */
3363 return (GET_CODE (op
) == CONST_INT
3364 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3366 return (GET_CODE (op
) == CONST_INT
3367 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3371 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3372 to check the range carefully since this predicate is used in DImode
3376 const_sint32_operand (rtx op
, enum machine_mode mode
)
3378 /* It doesn't make sense to ask this question with a mode that is
3379 not larger than 32 bits. */
3380 if (GET_MODE_BITSIZE (mode
) <= 32)
3383 /* All allowed constants will fit a CONST_INT. */
3384 return (GET_CODE (op
) == CONST_INT
3385 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3388 /* Operand predicates for implementing asymmetric pc-relative addressing
3389 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3390 when used as a source operand, but not as a destination operand.
3392 We model this by restricting the meaning of the basic predicates
3393 (general_operand, memory_operand, etc) to forbid the use of this
3394 addressing mode, and then define the following predicates that permit
3395 this addressing mode. These predicates can then be used for the
3396 source operands of the appropriate instructions.
3398 n.b. While it is theoretically possible to change all machine patterns
3399 to use this addressing more where permitted by the architecture,
3400 it has only been implemented for "common" cases: SImode, HImode, and
3401 QImode operands, and only for the principle operations that would
3402 require this addressing mode: data movement and simple integer operations.
3404 In parallel with these new predicates, two new constraint letters
3405 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3406 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3407 In the pcrel case 's' is only valid in combination with 'a' registers.
3408 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3409 of how these constraints are used.
3411 The use of these predicates is strictly optional, though patterns that
3412 don't will cause an extra reload register to be allocated where one
3415 lea (abc:w,%pc),%a0 ; need to reload address
3416 moveq &1,%d1 ; since write to pc-relative space
3417 movel %d1,%a0@ ; is not allowed
3419 lea (abc:w,%pc),%a1 ; no need to reload address here
3420 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3422 For more info, consult tiemann@cygnus.com.
3425 All of the ugliness with predicates and constraints is due to the
3426 simple fact that the m68k does not allow a pc-relative addressing
3427 mode as a destination. gcc does not distinguish between source and
3428 destination addresses. Hence, if we claim that pc-relative address
3429 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3430 end up with invalid code. To get around this problem, we left
3431 pc-relative modes as invalid addresses, and then added special
3432 predicates and constraints to accept them.
3434 A cleaner way to handle this is to modify gcc to distinguish
3435 between source and destination addresses. We can then say that
3436 pc-relative is a valid source address but not a valid destination
3437 address, and hopefully avoid a lot of the predicate and constraint
3438 hackery. Unfortunately, this would be a pretty big change. It would
3439 be a useful change for a number of ports, but there aren't any current
3440 plans to undertake this.
3442 ***************************************************************************/
3445 /* Special case of a general operand that's used as a source operand.
3446 Use this to permit reads from PC-relative memory when -mpcrel
3450 general_src_operand (rtx op
, enum machine_mode mode
)
3453 && GET_CODE (op
) == MEM
3454 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3455 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3456 || GET_CODE (XEXP (op
, 0)) == CONST
))
3458 return general_operand (op
, mode
);
3461 /* Special case of a nonimmediate operand that's used as a source.
3462 Use this to permit reads from PC-relative memory when -mpcrel
3466 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3468 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3469 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3470 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3471 || GET_CODE (XEXP (op
, 0)) == CONST
))
3473 return nonimmediate_operand (op
, mode
);
3476 /* Special case of a memory operand that's used as a source.
3477 Use this to permit reads from PC-relative memory when -mpcrel
3481 memory_src_operand (rtx op
, enum machine_mode mode
)
3483 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3484 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3485 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3486 || GET_CODE (XEXP (op
, 0)) == CONST
))
3488 return memory_operand (op
, mode
);
3491 /* Predicate that accepts only a pc-relative address. This is needed
3492 because pc-relative addresses don't satisfy the predicate
3493 "general_src_operand". */
3496 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3498 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3499 || GET_CODE (op
) == CONST
);
3503 output_andsi3 (rtx
*operands
)
3506 if (GET_CODE (operands
[2]) == CONST_INT
3507 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3508 && (DATA_REG_P (operands
[0])
3509 || offsettable_memref_p (operands
[0]))
3510 && !TARGET_COLDFIRE
)
3512 if (GET_CODE (operands
[0]) != REG
)
3513 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3514 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3515 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3517 if (operands
[2] == const0_rtx
)
3519 return "and%.w %2,%0";
3521 if (GET_CODE (operands
[2]) == CONST_INT
3522 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3523 && (DATA_REG_P (operands
[0])
3524 || offsettable_memref_p (operands
[0])))
3526 if (DATA_REG_P (operands
[0]))
3528 operands
[1] = GEN_INT (logval
);
3532 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3533 operands
[1] = GEN_INT (logval
% 8);
3535 /* This does not set condition codes in a standard way. */
3537 return "bclr %1,%0";
3539 return "and%.l %2,%0";
3543 output_iorsi3 (rtx
*operands
)
3545 register int logval
;
3546 if (GET_CODE (operands
[2]) == CONST_INT
3547 && INTVAL (operands
[2]) >> 16 == 0
3548 && (DATA_REG_P (operands
[0])
3549 || offsettable_memref_p (operands
[0]))
3550 && !TARGET_COLDFIRE
)
3552 if (GET_CODE (operands
[0]) != REG
)
3553 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3554 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3556 if (INTVAL (operands
[2]) == 0xffff)
3557 return "mov%.w %2,%0";
3558 return "or%.w %2,%0";
3560 if (GET_CODE (operands
[2]) == CONST_INT
3561 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3562 && (DATA_REG_P (operands
[0])
3563 || offsettable_memref_p (operands
[0])))
3565 if (DATA_REG_P (operands
[0]))
3566 operands
[1] = GEN_INT (logval
);
3569 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3570 operands
[1] = GEN_INT (logval
% 8);
3573 return "bset %1,%0";
3575 return "or%.l %2,%0";
3579 output_xorsi3 (rtx
*operands
)
3581 register int logval
;
3582 if (GET_CODE (operands
[2]) == CONST_INT
3583 && INTVAL (operands
[2]) >> 16 == 0
3584 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3585 && !TARGET_COLDFIRE
)
3587 if (! DATA_REG_P (operands
[0]))
3588 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3589 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3591 if (INTVAL (operands
[2]) == 0xffff)
3593 return "eor%.w %2,%0";
3595 if (GET_CODE (operands
[2]) == CONST_INT
3596 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3597 && (DATA_REG_P (operands
[0])
3598 || offsettable_memref_p (operands
[0])))
3600 if (DATA_REG_P (operands
[0]))
3601 operands
[1] = GEN_INT (logval
);
3604 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3605 operands
[1] = GEN_INT (logval
% 8);
3608 return "bchg %1,%0";
3610 return "eor%.l %2,%0";
3613 #ifdef M68K_TARGET_COFF
3615 /* Output assembly to switch to section NAME with attribute FLAGS. */
3618 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3622 if (flags
& SECTION_WRITE
)
3627 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3630 #endif /* M68K_TARGET_COFF */
3634 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3635 unsigned long labelno
)
3637 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3638 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3640 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3644 m68k_hp320_file_start (void)
3646 /* version 1: 68010.
3647 2: 68020 without FPU.
3648 3: 68020 with FPU. */
3649 fprintf (asm_out_file
, "\tversion %d\n",
3650 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3655 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3656 HOST_WIDE_INT delta
,
3657 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3663 if (delta
> 0 && delta
<= 8)
3665 asm_fprintf (file
, "\taddq.l %I%d,4(%Rsp)\n", (int) delta
);
3667 asm_fprintf (file
, "\taddql %I%d,%Rsp@(4)\n", (int) delta
);
3669 else if (delta
< 0 && delta
>= -8)
3671 asm_fprintf (file
, "\tsubq.l %I%d,4(%Rsp)\n", (int) -delta
);
3673 asm_fprintf (file
, "\tsubql %I%d,%Rsp@(4)\n", (int) -delta
);
3677 asm_fprintf (file
, "\tadd.l %I%wd,4(%Rsp)\n", delta
);
3679 asm_fprintf (file
, "\taddl %I%wd,%Rsp@(4)\n", delta
);
3682 xops
[0] = DECL_RTL (function
);
3684 /* Logic taken from call patterns in m68k.md. */
3689 else if ((flag_pic
== 1) || TARGET_68020
)
3696 fmt
= "bra.l %0@PLTPC";
3698 fmt
= "bra %0@PLTPC";
3709 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3710 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3712 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3716 #if defined (MOTOROLA) && !defined (USE_GAS)
3723 output_asm_insn (fmt
, xops
);