1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
45 /* Needed for use_return_insn. */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg (rtx
);
53 static const char *singlemove_string (rtx
*);
54 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
55 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
56 #ifdef M68K_TARGET_COFF
57 static void m68k_coff_asm_named_section (const char *, unsigned int);
58 #endif /* M68K_TARGET_COFF */
60 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
61 static void m68k_hp320_file_start (void);
63 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
65 static int m68k_save_reg (unsigned int);
66 static int const_int_cost (rtx
);
67 static bool m68k_rtx_costs (rtx
, int, int, int *);
70 /* Alignment to use for loops and jumps */
71 /* Specify power of two alignment used for loops. */
72 const char *m68k_align_loops_string
;
73 /* Specify power of two alignment used for non-loop jumps. */
74 const char *m68k_align_jumps_string
;
75 /* Specify power of two alignment used for functions. */
76 const char *m68k_align_funcs_string
;
77 /* Specify the identification number of the library being built */
78 const char *m68k_library_id_string
;
80 /* Specify power of two alignment used for loops. */
82 /* Specify power of two alignment used for non-loop jumps. */
84 /* Specify power of two alignment used for functions. */
87 /* Nonzero if the last compare/test insn had FP operands. The
88 sCC expanders peek at this to determine what to do for the
89 68060, which has no fsCC instructions. */
90 int m68k_last_compare_had_fp_operands
;
92 /* Initialize the GCC target structure. */
94 #if INT_OP_GROUP == INT_OP_DOT_WORD
95 #undef TARGET_ASM_ALIGNED_HI_OP
96 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
99 #if INT_OP_GROUP == INT_OP_NO_DOT
100 #undef TARGET_ASM_BYTE_OP
101 #define TARGET_ASM_BYTE_OP "\tbyte\t"
102 #undef TARGET_ASM_ALIGNED_HI_OP
103 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
104 #undef TARGET_ASM_ALIGNED_SI_OP
105 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
108 #if INT_OP_GROUP == INT_OP_DC
109 #undef TARGET_ASM_BYTE_OP
110 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
111 #undef TARGET_ASM_ALIGNED_HI_OP
112 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
113 #undef TARGET_ASM_ALIGNED_SI_OP
114 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
117 #undef TARGET_ASM_UNALIGNED_HI_OP
118 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
119 #undef TARGET_ASM_UNALIGNED_SI_OP
120 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
122 #undef TARGET_ASM_FUNCTION_PROLOGUE
123 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
124 #undef TARGET_ASM_FUNCTION_EPILOGUE
125 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
127 #undef TARGET_ASM_INTERNAL_LABEL
128 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
131 #undef TARGET_ASM_OUTPUT_MI_THUNK
132 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
133 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
134 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
136 #undef TARGET_ASM_FILE_START_APP_OFF
137 #define TARGET_ASM_FILE_START_APP_OFF true
139 #undef TARGET_RTX_COSTS
140 #define TARGET_RTX_COSTS m68k_rtx_costs
142 struct gcc_target targetm
= TARGET_INITIALIZER
;
144 /* Sometimes certain combinations of command options do not make
145 sense on a particular target machine. You can define a macro
146 `OVERRIDE_OPTIONS' to take account of this. This macro, if
147 defined, is executed once just after all the command options have
150 Don't use this macro to turn on various extra optimizations for
151 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
154 override_options (void)
161 /* Validate -malign-loops= value, or provide default */
162 m68k_align_loops
= def_align
;
163 if (m68k_align_loops_string
)
165 i
= atoi (m68k_align_loops_string
);
166 if (i
< 1 || i
> MAX_CODE_ALIGN
)
167 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
169 m68k_align_loops
= i
;
172 /* Library identification */
173 if (m68k_library_id_string
)
177 if (! TARGET_ID_SHARED_LIBRARY
)
178 error ("-mshared-library-id= specified without -mid-shared-library");
179 id
= atoi (m68k_library_id_string
);
180 if (id
< 0 || id
> MAX_LIBRARY_ID
)
181 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
183 /* From now on, m68k_library_id_string will contain the library offset. */
184 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
187 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
189 m68k_library_id_string
= "_current_shared_library_a5_offset_";
191 /* Sanity check to ensure that msep-data and mid-sahred-library are not
192 * both specified together. Doing so simply doesn't make sense.
194 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
195 error ("cannot specify both -msep-data and -mid-shared-library");
197 /* If we're generating code for a separate A5 relative data segment,
198 * we've got to enable -fPIC as well. This might be relaxable to
199 * -fpic but it hasn't been tested properly.
201 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
204 /* Validate -malign-jumps= value, or provide default */
205 m68k_align_jumps
= def_align
;
206 if (m68k_align_jumps_string
)
208 i
= atoi (m68k_align_jumps_string
);
209 if (i
< 1 || i
> MAX_CODE_ALIGN
)
210 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
212 m68k_align_jumps
= i
;
215 /* Validate -malign-functions= value, or provide default */
216 m68k_align_funcs
= def_align
;
217 if (m68k_align_funcs_string
)
219 i
= atoi (m68k_align_funcs_string
);
220 if (i
< 1 || i
> MAX_CODE_ALIGN
)
221 error ("-malign-functions=%d is not between 1 and %d",
224 m68k_align_funcs
= i
;
227 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
229 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
230 error("-fPIC is not currently supported on the 68000 or 68010\n");
232 /* ??? A historic way of turning on pic, or is this intended to
233 be an embedded thing that doesn't have the same name binding
234 significance that it does on hosted ELF systems? */
235 if (TARGET_PCREL
&& flag_pic
== 0)
238 /* Turn off function cse if we are doing PIC. We always want function call
239 to be done as `bsr foo@PLTPC', so it will force the assembler to create
240 the PLT entry for `foo'. Doing function cse will cause the address of
241 `foo' to be loaded into a register, which is exactly what we want to
242 avoid when we are doing PIC on svr4 m68k. */
244 flag_no_function_cse
= 1;
246 SUBTARGET_OVERRIDE_OPTIONS
;
248 /* Tell the compiler which flavor of XFmode we're using. */
249 REAL_MODE_FORMAT (XFmode
) = &ieee_extended_motorola_format
;
252 /* Structure describing stack frame layout. */
254 HOST_WIDE_INT offset
;
256 /* data and address register */
258 unsigned int reg_mask
;
259 unsigned int reg_rev_mask
;
262 unsigned int fpu_mask
;
263 unsigned int fpu_rev_mask
;
266 /* offsets relative to ARG_POINTER. */
267 HOST_WIDE_INT frame_pointer_offset
;
268 HOST_WIDE_INT stack_pointer_offset
;
272 m68k_compute_frame_layout (struct m68k_frame
*frame
)
275 unsigned int mask
, rmask
;
277 frame
->size
= (get_frame_size () + 3) & -4;
279 mask
= rmask
= saved
= 0;
280 for (regno
= 0; regno
< 16; regno
++)
281 if (m68k_save_reg (regno
))
284 rmask
|= 1 << (15 - regno
);
287 frame
->offset
= saved
* 4;
288 frame
->reg_no
= saved
;
289 frame
->reg_mask
= mask
;
290 frame
->reg_rev_mask
= rmask
;
292 if (TARGET_68881
/* || TARGET_CFV4E */)
294 mask
= rmask
= saved
= 0;
295 for (regno
= 16; regno
< 24; regno
++)
296 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
298 mask
|= 1 << (23 - regno
);
299 rmask
|= 1 << (regno
- 16);
302 frame
->offset
+= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
303 frame
->fpu_no
= saved
;
304 frame
->fpu_mask
= mask
;
305 frame
->fpu_rev_mask
= rmask
;
310 m68k_initial_elimination_offset (int from
, int to
)
312 struct m68k_frame frame
;
314 /* FIXME: The correct offset to compute here would appear to be
315 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
316 but for some obscure reason, this must be 0 to get correct code. */
317 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
320 m68k_compute_frame_layout (&frame
);
322 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
323 return frame
.offset
+ frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
324 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
325 return frame
.offset
+ frame
.size
;
330 /* Return 1 if we need to save REGNO. */
332 m68k_save_reg (unsigned int regno
)
334 if (flag_pic
&& current_function_uses_pic_offset_table
335 && regno
== PIC_OFFSET_TABLE_REGNUM
)
338 if (current_function_calls_eh_return
)
343 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
344 if (test
== INVALID_REGNUM
)
351 return (regs_ever_live
[regno
]
352 && !call_used_regs
[regno
]
353 && !fixed_regs
[regno
]
354 && !(regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
));
357 /* This function generates the assembly code for function entry.
358 STREAM is a stdio stream to output the code to.
359 SIZE is an int: how many units of temporary storage to allocate.
360 Refer to the array `regs_ever_live' to determine which registers
361 to save; `regs_ever_live[I]' is nonzero if register number I
362 is ever used in the function. This function is responsible for
363 knowing which registers should not be saved even if used. */
366 /* Note that the order of the bit mask for fmovem is the opposite
367 of the order for movem! */
370 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size
)
373 register int mask
= 0;
374 int num_saved_regs
= 0;
375 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
376 HOST_WIDE_INT fsize_with_regs
;
377 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
379 /* If the stack limit is a symbol, we can check it here,
380 before actually allocating the space. */
381 if (current_function_limit_stack
382 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
384 #if defined (MOTOROLA)
385 asm_fprintf (stream
, "\tcmp.l %I%s+%wd,%Rsp\n\ttrapcs\n",
386 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
388 asm_fprintf (stream
, "\tcmpl %I%s+%wd,%Rsp\n\ttrapcs\n",
389 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
395 /* on Coldfire add register save into initial stack frame setup, if possible */
396 for (regno
= 0; regno
< 16; regno
++)
397 if (m68k_save_reg (regno
))
400 if (num_saved_regs
<= 2)
406 fsize_with_regs
= fsize
+ num_saved_regs
* 4;
408 if (frame_pointer_needed
)
410 if (fsize
== 0 && TARGET_68040
)
412 /* on the 68040, pea + move is faster than link.w 0 */
414 fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
415 reg_names
[FRAME_POINTER_REGNUM
],
416 reg_names
[STACK_POINTER_REGNUM
],
417 reg_names
[FRAME_POINTER_REGNUM
]);
419 fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
420 reg_names
[FRAME_POINTER_REGNUM
],
421 reg_names
[STACK_POINTER_REGNUM
],
422 reg_names
[FRAME_POINTER_REGNUM
]);
425 else if (fsize_with_regs
< 0x8000)
428 asm_fprintf (stream
, "\tlink.w %s,%I%wd\n",
429 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
431 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
432 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
435 else if (TARGET_68020
)
438 asm_fprintf (stream
, "\tlink.l %s,%I%wd\n",
439 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
441 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
442 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
447 /* Adding negative number is faster on the 68040. */
449 asm_fprintf (stream
, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
450 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
452 asm_fprintf (stream
, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
453 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
456 if (dwarf2out_do_frame ())
459 l
= (char *) dwarf2out_cfi_label ();
461 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
462 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
466 else if (fsize_with_regs
) /* !frame_pointer_needed */
468 if (fsize_with_regs
< 0x8000)
470 if (fsize_with_regs
<= 8)
472 if (!TARGET_COLDFIRE
)
474 /* asm_fprintf() cannot handle %. */
476 asm_fprintf (stream
, "\tsubq.w %I%wd,%Rsp\n", fsize_with_regs
);
478 asm_fprintf (stream
, "\tsubqw %I%wd,%Rsp\n", fsize_with_regs
);
483 /* asm_fprintf() cannot handle %. */
485 asm_fprintf (stream
, "\tsubq.l %I%wd,%Rsp\n", fsize_with_regs
);
487 asm_fprintf (stream
, "\tsubql %I%wd,%Rsp\n", fsize_with_regs
);
491 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
493 /* On the CPU32 it is faster to use two subqw instructions to
494 subtract a small integer (8 < N <= 16) to a register. */
495 /* asm_fprintf() cannot handle %. */
498 "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
499 fsize_with_regs
- 8);
501 asm_fprintf (stream
, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
502 fsize_with_regs
- 8);
505 else if (TARGET_68040
)
507 /* Adding negative number is faster on the 68040. */
508 /* asm_fprintf() cannot handle %. */
510 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", -fsize_with_regs
);
512 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", -fsize_with_regs
);
518 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", -fsize_with_regs
);
520 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", -fsize_with_regs
);
524 else /* fsize_with_regs >= 0x8000 */
527 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", -fsize_with_regs
);
529 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", -fsize_with_regs
);
532 if (dwarf2out_do_frame ())
534 cfa_offset
+= fsize
+ 4;
535 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
537 } /* !frame_pointer_needed */
543 for (regno
= 16; regno
< 24; regno
++)
544 if (m68k_save_reg (regno
))
546 mask
|= 1 << (regno
- 16);
549 if ((mask
& 0xff) != 0)
552 asm_fprintf (stream
, "\tfmovm %I0x%x,-(%Rsp)\n", mask
& 0xff);
554 asm_fprintf (stream
, "\tfmovem %I0x%x,%Rsp@-\n", mask
& 0xff);
556 if (dwarf2out_do_frame ())
558 char *l
= (char *) dwarf2out_cfi_label ();
561 cfa_offset
+= num_saved_regs
* 12;
562 if (! frame_pointer_needed
)
563 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
564 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
565 if (mask
& (1 << (regno
- 16)))
566 dwarf2out_reg_save (l
, regno
,
567 -cfa_offset
+ n_regs
++ * 12);
573 for (regno
= 0; regno
< 16; regno
++)
574 if (m68k_save_reg (regno
))
576 mask
|= 1 << (15 - regno
);
580 /* If the stack limit is not a symbol, check it here.
581 This has the disadvantage that it may be too late... */
582 if (current_function_limit_stack
)
584 if (REG_P (stack_limit_rtx
))
586 #if defined (MOTOROLA)
587 asm_fprintf (stream
, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
588 reg_names
[REGNO (stack_limit_rtx
)]);
590 asm_fprintf (stream
, "\tcmpl %s,%Rsp\n\ttrapcs\n",
591 reg_names
[REGNO (stack_limit_rtx
)]);
594 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
595 warning ("stack limit expression is not supported");
598 if (num_saved_regs
<= 2)
600 /* Store each separately in the same order moveml uses.
601 Using two movel instructions instead of a single moveml
602 is about 15% faster for the 68020 and 68030 at no expense
607 /* Undo the work from above. */
608 for (i
= 0; i
< 16; i
++)
613 "\t%Omove.l %s,-(%Rsp)\n",
615 "\tmovel %s,%Rsp@-\n",
618 if (dwarf2out_do_frame ())
620 char *l
= (char *) dwarf2out_cfi_label ();
623 if (! frame_pointer_needed
)
624 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
625 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
633 /* The coldfire does not support the predecrement form of the
634 movml instruction, so we must adjust the stack pointer and
635 then use the plain address register indirect mode. We also
636 have to invert the register save mask to use the new mode.
638 The required register save space was combined earlier with
639 the fsize amount. Don't add it again. */
644 for (i
= 0; i
< 16; i
++)
646 newmask
|= (1 << (15-i
));
649 asm_fprintf (stream
, "\tmovm.l %I0x%x,(%Rsp)\n", newmask
);
651 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@\n", newmask
);
657 asm_fprintf (stream
, "\tmovm.l %I0x%x,-(%Rsp)\n", mask
);
659 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@-\n", mask
);
662 if (dwarf2out_do_frame ())
664 char *l
= (char *) dwarf2out_cfi_label ();
667 cfa_offset
+= num_saved_regs
* 4;
668 if (! frame_pointer_needed
)
669 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
670 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
671 if (mask
& (1 << (15 - regno
)))
672 dwarf2out_reg_save (l
, regno
,
673 -cfa_offset
+ n_regs
++ * 4);
676 if (!TARGET_SEP_DATA
&& flag_pic
&&
677 (current_function_uses_pic_offset_table
||
678 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
680 if (TARGET_ID_SHARED_LIBRARY
)
682 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
683 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
684 m68k_library_id_string
,
685 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
690 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
691 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
693 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
694 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
695 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
696 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
697 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
703 /* Return true if this function's epilogue can be output as RTL. */
710 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
713 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
714 if (m68k_save_reg (regno
))
720 /* This function generates the assembly code for function exit,
721 on machines that need it.
723 The function epilogue should not depend on the current stack pointer!
724 It should use the frame pointer only, if there is a frame pointer.
725 This is mandatory because of alloca; we also take advantage of it to
726 omit stack adjustments before returning. */
729 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size
)
732 register int mask
, fmask
;
734 HOST_WIDE_INT offset
, foffset
;
735 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
736 HOST_WIDE_INT fsize_with_regs
;
738 rtx insn
= get_last_insn ();
739 int restore_from_sp
= 0;
741 /* If the last insn was a BARRIER, we don't have to write any code. */
742 if (GET_CODE (insn
) == NOTE
)
743 insn
= prev_nonnote_insn (insn
);
744 if (insn
&& GET_CODE (insn
) == BARRIER
)
746 /* Output just a no-op so that debuggers don't get confused
747 about which function the pc is in at this address. */
748 fprintf (stream
, "\tnop\n");
752 #ifdef FUNCTION_EXTRA_EPILOGUE
753 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
755 nregs
= 0; fmask
= 0;
758 for (regno
= 16; regno
< 24; regno
++)
759 if (m68k_save_reg (regno
))
762 fmask
|= 1 << (23 - regno
);
765 foffset
= nregs
* 12;
767 for (regno
= 0; regno
< 16; regno
++)
768 if (m68k_save_reg (regno
))
773 offset
= foffset
+ nregs
* 4;
774 /* FIXME : leaf_function_p below is too strong.
775 What we really need to know there is if there could be pending
776 stack adjustment needed at that point. */
777 restore_from_sp
= ! frame_pointer_needed
778 || (! current_function_calls_alloca
&& leaf_function_p ());
780 /* fsize_with_regs is the size we need to adjust the sp when
782 fsize_with_regs
= fsize
;
784 /* Because the ColdFire doesn't support moveml with
785 complex address modes, we must adjust the stack manually
786 after restoring registers. When the frame pointer isn't used,
787 we can merge movem adjustment into frame unlinking
788 made immediately after it. */
789 if (TARGET_COLDFIRE
&& restore_from_sp
&& (nregs
> 2))
790 fsize_with_regs
+= nregs
* 4;
792 if (offset
+ fsize
>= 0x8000
796 /* Because the ColdFire doesn't support moveml with
797 complex address modes we make an extra correction here */
801 asm_fprintf (stream
, "\t%Omove.l %I%d,%Ra1\n", -fsize
- offset
);
803 asm_fprintf (stream
, "\tmovel %I%d,%Ra1\n", -fsize
- offset
);
809 asm_fprintf (stream
, "\t%Omove.l %I%wd,%Ra1\n", -fsize
);
811 asm_fprintf (stream
, "\tmovel %I%wd,%Ra1\n", -fsize
);
819 /* Restore each separately in the same order moveml does.
820 Using two movel instructions instead of a single moveml
821 is about 15% faster for the 68020 and 68030 at no expense
826 /* Undo the work from above. */
827 for (i
= 0; i
< 16; i
++)
833 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
835 reg_names
[FRAME_POINTER_REGNUM
],
838 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
839 reg_names
[FRAME_POINTER_REGNUM
],
840 offset
+ fsize
, reg_names
[i
]);
843 else if (restore_from_sp
)
846 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
849 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
856 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
858 reg_names
[FRAME_POINTER_REGNUM
],
861 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
862 reg_names
[FRAME_POINTER_REGNUM
],
863 offset
+ fsize
, reg_names
[i
]);
871 /* The ColdFire requires special handling due to its limited moveml insn */
877 asm_fprintf (stream
, "\tadd.l %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
878 asm_fprintf (stream
, "\tmovm.l (%Ra1),%I0x%x\n", mask
);
880 asm_fprintf (stream
, "\taddl %s,%Ra1\n", reg_names
[FRAME_POINTER_REGNUM
]);
881 asm_fprintf (stream
, "\tmoveml %Ra1@,%I0x%x\n", mask
);
884 else if (restore_from_sp
)
887 asm_fprintf (stream
, "\tmovm.l (%Rsp),%I0x%x\n", mask
);
889 asm_fprintf (stream
, "\tmoveml %Rsp@,%I0x%x\n", mask
);
895 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
897 reg_names
[FRAME_POINTER_REGNUM
],
900 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
901 reg_names
[FRAME_POINTER_REGNUM
],
902 offset
+ fsize
, mask
);
906 else /* !TARGET_COLDFIRE */
911 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
913 reg_names
[FRAME_POINTER_REGNUM
],
916 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
917 reg_names
[FRAME_POINTER_REGNUM
],
918 offset
+ fsize
, mask
);
921 else if (restore_from_sp
)
924 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%I0x%x\n", mask
);
926 asm_fprintf (stream
, "\tmoveml %Rsp@+,%I0x%x\n", mask
);
932 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
934 reg_names
[FRAME_POINTER_REGNUM
],
937 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
938 reg_names
[FRAME_POINTER_REGNUM
],
939 offset
+ fsize
, mask
);
949 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
951 reg_names
[FRAME_POINTER_REGNUM
],
954 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
955 reg_names
[FRAME_POINTER_REGNUM
],
956 foffset
+ fsize
, fmask
);
959 else if (restore_from_sp
)
962 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n", fmask
);
964 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n", fmask
);
970 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
972 reg_names
[FRAME_POINTER_REGNUM
],
975 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
976 reg_names
[FRAME_POINTER_REGNUM
],
977 foffset
+ fsize
, fmask
);
981 if (frame_pointer_needed
)
982 fprintf (stream
, "\tunlk %s\n",
983 reg_names
[FRAME_POINTER_REGNUM
]);
984 else if (fsize_with_regs
)
986 if (fsize_with_regs
<= 8)
988 if (!TARGET_COLDFIRE
)
991 asm_fprintf (stream
, "\taddq.w %I%wd,%Rsp\n", fsize_with_regs
);
993 asm_fprintf (stream
, "\taddqw %I%wd,%Rsp\n", fsize_with_regs
);
996 else /* TARGET_COLDFIRE */
999 asm_fprintf (stream
, "\taddq.l %I%wd,%Rsp\n", fsize_with_regs
);
1001 asm_fprintf (stream
, "\taddql %I%wd,%Rsp\n", fsize_with_regs
);
1005 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
1007 /* On the CPU32 it is faster to use two addqw instructions to
1008 add a small integer (8 < N <= 16) to a register. */
1009 /* asm_fprintf() cannot handle %. */
1011 asm_fprintf (stream
, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
1012 fsize_with_regs
- 8);
1014 asm_fprintf (stream
, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
1015 fsize_with_regs
- 8);
1018 else if (fsize_with_regs
< 0x8000)
1022 /* asm_fprintf() cannot handle %. */
1024 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", fsize_with_regs
);
1026 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", fsize_with_regs
);
1032 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", fsize_with_regs
);
1034 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", fsize_with_regs
);
1040 /* asm_fprintf() cannot handle %. */
1042 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", fsize_with_regs
);
1044 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", fsize_with_regs
);
1048 if (current_function_calls_eh_return
)
1051 asm_fprintf (stream
, "\tadd.l %Ra0,%Rsp\n");
1053 asm_fprintf (stream
, "\taddl %Ra0,%Rsp\n");
1056 if (current_function_pops_args
)
1057 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1059 fprintf (stream
, "\trts\n");
1062 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1065 not_sp_operand (rtx op
, enum machine_mode mode
)
1067 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
1070 /* Return true if X is a valid comparison operator for the dbcc
1073 Note it rejects floating point comparison operators.
1074 (In the future we could use Fdbcc).
1076 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1079 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1081 switch (GET_CODE (x
))
1083 case EQ
: case NE
: case GTU
: case LTU
:
1087 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1089 case GT
: case LT
: case GE
: case LE
:
1090 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1096 /* Return nonzero if flags are currently in the 68881 flag register. */
1098 flags_in_68881 (void)
1100 /* We could add support for these in the future */
1101 return cc_status
.flags
& CC_IN_68881
;
1104 /* Output a BSR instruction suitable for PIC code. */
1106 m68k_output_pic_call(rtx dest
)
1110 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1112 /* We output a BSR instruction if we've using -fpic or we're building for
1113 * a target that supports long branches. If we're building -fPIC on the
1114 * 68000, 68010 or ColdFire we generate one of two sequences:
1115 * a shorter one that uses a GOT entry or a longer one that doesn't.
1116 * We'll use the -Os command-line flag to decide which to generate.
1117 * Both sequences take the same time to execute on the ColdFire.
1119 else if (TARGET_PCREL
)
1121 else if ((flag_pic
== 1) || TARGET_68020
)
1124 #elif defined(USE_GAS)
1125 out
= "bsr.l %0@PLTPC";
1127 out
= "bsr %0@PLTPC";
1129 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1130 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1132 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1134 output_asm_insn(out
, &dest
);
1137 /* Output a dbCC; jCC sequence. Note we do not handle the
1138 floating point version of this sequence (Fdbcc). We also
1139 do not handle alternative conditions when CC_NO_OVERFLOW is
1140 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1141 kick those out before we get here. */
1144 output_dbcc_and_branch (rtx
*operands
)
1146 switch (GET_CODE (operands
[3]))
1150 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
1152 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1158 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
1160 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1166 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
1168 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1174 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
1176 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1182 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
1184 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1190 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
1192 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1198 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
1200 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1206 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
1208 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1214 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
1216 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1222 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
1224 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1232 /* If the decrement is to be done in SImode, then we have
1233 to compensate for the fact that dbcc decrements in HImode. */
1234 switch (GET_MODE (operands
[0]))
1238 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
1240 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1253 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1256 enum rtx_code op_code
= GET_CODE (op
);
1258 /* This does not produce a useful cc. */
1261 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1262 below. Swap the operands and change the op if these requirements
1263 are not fulfilled. */
1264 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1268 operand1
= operand2
;
1270 op_code
= swap_condition (op_code
);
1272 loperands
[0] = operand1
;
1273 if (GET_CODE (operand1
) == REG
)
1274 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1276 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1277 if (operand2
!= const0_rtx
)
1279 loperands
[2] = operand2
;
1280 if (GET_CODE (operand2
) == REG
)
1281 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1283 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1285 loperands
[4] = gen_label_rtx();
1286 if (operand2
!= const0_rtx
)
1289 #ifdef SGS_CMP_ORDER
1290 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1292 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1295 #ifdef SGS_CMP_ORDER
1296 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1298 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1304 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1305 output_asm_insn ("tst%.l %0", loperands
);
1308 #ifdef SGS_CMP_ORDER
1309 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1311 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1316 output_asm_insn ("jbne %l4", loperands
);
1318 output_asm_insn ("jne %l4", loperands
);
1321 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1322 output_asm_insn ("tst%.l %1", loperands
);
1325 #ifdef SGS_CMP_ORDER
1326 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1328 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1333 loperands
[5] = dest
;
1338 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1339 CODE_LABEL_NUMBER (loperands
[4]));
1340 output_asm_insn ("seq %5", loperands
);
1344 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1345 CODE_LABEL_NUMBER (loperands
[4]));
1346 output_asm_insn ("sne %5", loperands
);
1350 loperands
[6] = gen_label_rtx();
1352 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1354 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1356 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1357 CODE_LABEL_NUMBER (loperands
[4]));
1358 output_asm_insn ("sgt %5", loperands
);
1359 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1360 CODE_LABEL_NUMBER (loperands
[6]));
1364 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1365 CODE_LABEL_NUMBER (loperands
[4]));
1366 output_asm_insn ("shi %5", loperands
);
1370 loperands
[6] = gen_label_rtx();
1372 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1374 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1376 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1377 CODE_LABEL_NUMBER (loperands
[4]));
1378 output_asm_insn ("slt %5", loperands
);
1379 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1380 CODE_LABEL_NUMBER (loperands
[6]));
1384 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1385 CODE_LABEL_NUMBER (loperands
[4]));
1386 output_asm_insn ("scs %5", loperands
);
1390 loperands
[6] = gen_label_rtx();
1392 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1394 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1396 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1397 CODE_LABEL_NUMBER (loperands
[4]));
1398 output_asm_insn ("sge %5", loperands
);
1399 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1400 CODE_LABEL_NUMBER (loperands
[6]));
1404 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1405 CODE_LABEL_NUMBER (loperands
[4]));
1406 output_asm_insn ("scc %5", loperands
);
1410 loperands
[6] = gen_label_rtx();
1412 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1414 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1416 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1417 CODE_LABEL_NUMBER (loperands
[4]));
1418 output_asm_insn ("sle %5", loperands
);
1419 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1420 CODE_LABEL_NUMBER (loperands
[6]));
1424 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1425 CODE_LABEL_NUMBER (loperands
[4]));
1426 output_asm_insn ("sls %5", loperands
);
1436 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1438 operands
[0] = countop
;
1439 operands
[1] = dataop
;
1441 if (GET_CODE (countop
) == CONST_INT
)
1443 register int count
= INTVAL (countop
);
1444 /* If COUNT is bigger than size of storage unit in use,
1445 advance to the containing unit of same size. */
1446 if (count
> signpos
)
1448 int offset
= (count
& ~signpos
) / 8;
1449 count
= count
& signpos
;
1450 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1452 if (count
== signpos
)
1453 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1455 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1457 /* These three statements used to use next_insns_test_no...
1458 but it appears that this should do the same job. */
1460 && next_insn_tests_no_inequality (insn
))
1463 && next_insn_tests_no_inequality (insn
))
1466 && next_insn_tests_no_inequality (insn
))
1469 cc_status
.flags
= CC_NOT_NEGATIVE
;
1471 return "btst %0,%1";
1474 /* Returns true if OP is either a symbol reference or a sum of a symbol
1475 reference and a constant. */
1478 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1480 switch (GET_CODE (op
))
1488 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1489 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1490 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1492 #if 0 /* Deleted, with corresponding change in m68k.h,
1493 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1495 return GET_MODE (op
) == mode
;
1503 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1506 extend_operator(rtx x
, enum machine_mode mode
)
1508 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1510 switch (GET_CODE(x
))
1521 /* Legitimize PIC addresses. If the address is already
1522 position-independent, we return ORIG. Newly generated
1523 position-independent addresses go to REG. If we need more
1524 than one register, we lose.
1526 An address is legitimized by making an indirect reference
1527 through the Global Offset Table with the name of the symbol
1530 The assembler and linker are responsible for placing the
1531 address of the symbol in the GOT. The function prologue
1532 is responsible for initializing a5 to the starting address
1535 The assembler is also responsible for translating a symbol name
1536 into a constant displacement from the start of the GOT.
1538 A quick example may make things a little clearer:
1540 When not generating PIC code to store the value 12345 into _foo
1541 we would generate the following code:
1545 When generating PIC two transformations are made. First, the compiler
1546 loads the address of foo into a register. So the first transformation makes:
1551 The code in movsi will intercept the lea instruction and call this
1552 routine which will transform the instructions into:
1554 movel a5@(_foo:w), a0
1558 That (in a nutshell) is how *all* symbol and label references are
1562 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1567 /* First handle a simple SYMBOL_REF or LABEL_REF */
1568 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1573 pic_ref
= gen_rtx_MEM (Pmode
,
1574 gen_rtx_PLUS (Pmode
,
1575 pic_offset_table_rtx
, orig
));
1576 current_function_uses_pic_offset_table
= 1;
1577 RTX_UNCHANGING_P (pic_ref
) = 1;
1578 emit_move_insn (reg
, pic_ref
);
1581 else if (GET_CODE (orig
) == CONST
)
1585 /* Make sure this is CONST has not already been legitimized */
1586 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1587 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1593 /* legitimize both operands of the PLUS */
1594 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1596 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1597 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1598 base
== reg
? 0 : reg
);
1602 if (GET_CODE (orig
) == CONST_INT
)
1603 return plus_constant (base
, INTVAL (orig
));
1604 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1605 /* Likewise, should we set special REG_NOTEs here? */
1611 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1613 static CONST_METHOD
const_method (rtx
);
1615 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1618 const_method (rtx constant
)
1623 i
= INTVAL (constant
);
1627 /* The Coldfire doesn't have byte or word operations. */
1628 /* FIXME: This may not be useful for the m68060 either */
1629 if (!TARGET_COLDFIRE
)
1631 /* if -256 < N < 256 but N is not in range for a moveq
1632 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1633 if (USE_MOVQ (i
^ 0xff))
1635 /* Likewise, try with not.w */
1636 if (USE_MOVQ (i
^ 0xffff))
1638 /* This is the only value where neg.w is useful */
1641 /* Try also with swap */
1643 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1646 /* Otherwise, use move.l */
1651 const_int_cost (rtx constant
)
1653 switch (const_method (constant
))
1656 /* Constants between -128 and 127 are cheap due to moveq */
1662 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1672 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1677 /* Constant zero is super cheap due to clr instruction. */
1678 if (x
== const0_rtx
)
1681 *total
= const_int_cost (x
);
1691 /* Make 0.0 cheaper than other floating constants to
1692 encourage creating tstsf and tstdf insns. */
1693 if (outer_code
== COMPARE
1694 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1700 /* These are vaguely right for a 68020. */
1701 /* The costs for long multiply have been adjusted to work properly
1702 in synth_mult on the 68020, relative to an average of the time
1703 for add and the time for shift, taking away a little more because
1704 sometimes move insns are needed. */
1705 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1706 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1707 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1708 TARGET_CFV3 ? 2 : 5)
1709 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1712 /* An lea costs about three times as much as a simple add. */
1713 if (GET_MODE (x
) == SImode
1714 && GET_CODE (XEXP (x
, 1)) == REG
1715 && GET_CODE (XEXP (x
, 0)) == MULT
1716 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1717 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1718 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1719 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1720 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1722 /* lea an@(dx:l:i),am */
1723 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1733 *total
= COSTS_N_INSNS(1);
1736 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1738 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1740 if (INTVAL (XEXP (x
, 1)) < 16)
1741 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1743 /* We're using clrw + swap for these cases. */
1744 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1747 *total
= COSTS_N_INSNS (10); /* worst case */
1750 /* A shift by a big integer takes an extra instruction. */
1751 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1752 && (INTVAL (XEXP (x
, 1)) == 16))
1754 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1757 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1758 && !(INTVAL (XEXP (x
, 1)) > 0
1759 && INTVAL (XEXP (x
, 1)) <= 8))
1761 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1767 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1768 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1769 && GET_MODE (x
) == SImode
)
1770 *total
= COSTS_N_INSNS (MULW_COST
);
1771 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1772 *total
= COSTS_N_INSNS (MULW_COST
);
1774 *total
= COSTS_N_INSNS (MULL_COST
);
1781 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1782 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1783 else if (TARGET_CF_HWDIV
)
1784 *total
= COSTS_N_INSNS (18);
1786 *total
= COSTS_N_INSNS (43); /* div.l */
1795 output_move_const_into_data_reg (rtx
*operands
)
1799 i
= INTVAL (operands
[1]);
1800 switch (const_method (operands
[1]))
1803 return "moveq %1,%0";
1805 operands
[1] = GEN_INT (i
^ 0xff);
1806 return "moveq %1,%0\n\tnot%.b %0";
1808 operands
[1] = GEN_INT (i
^ 0xffff);
1809 return "moveq %1,%0\n\tnot%.w %0";
1811 return "moveq %#-128,%0\n\tneg%.w %0";
1816 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1817 return "moveq %1,%0\n\tswap %0";
1820 return "move%.l %1,%0";
1827 output_move_simode_const (rtx
*operands
)
1829 if (operands
[1] == const0_rtx
1830 && (DATA_REG_P (operands
[0])
1831 || GET_CODE (operands
[0]) == MEM
)
1832 /* clr insns on 68000 read before writing.
1833 This isn't so on the 68010, but we have no TARGET_68010. */
1834 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1835 || !(GET_CODE (operands
[0]) == MEM
1836 && MEM_VOLATILE_P (operands
[0]))))
1838 else if (operands
[1] == const0_rtx
1839 && ADDRESS_REG_P (operands
[0]))
1840 return "sub%.l %0,%0";
1841 else if (DATA_REG_P (operands
[0]))
1842 return output_move_const_into_data_reg (operands
);
1843 else if (ADDRESS_REG_P (operands
[0])
1844 && INTVAL (operands
[1]) < 0x8000
1845 && INTVAL (operands
[1]) >= -0x8000)
1846 return "move%.w %1,%0";
1847 else if (GET_CODE (operands
[0]) == MEM
1848 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1849 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1850 && INTVAL (operands
[1]) < 0x8000
1851 && INTVAL (operands
[1]) >= -0x8000)
1853 return "move%.l %1,%0";
1857 output_move_simode (rtx
*operands
)
1859 if (GET_CODE (operands
[1]) == CONST_INT
)
1860 return output_move_simode_const (operands
);
1861 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1862 || GET_CODE (operands
[1]) == CONST
)
1863 && push_operand (operands
[0], SImode
))
1865 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1866 || GET_CODE (operands
[1]) == CONST
)
1867 && ADDRESS_REG_P (operands
[0]))
1868 return "lea %a1,%0";
1869 return "move%.l %1,%0";
1873 output_move_himode (rtx
*operands
)
1875 if (GET_CODE (operands
[1]) == CONST_INT
)
1877 if (operands
[1] == const0_rtx
1878 && (DATA_REG_P (operands
[0])
1879 || GET_CODE (operands
[0]) == MEM
)
1880 /* clr insns on 68000 read before writing.
1881 This isn't so on the 68010, but we have no TARGET_68010. */
1882 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1883 || !(GET_CODE (operands
[0]) == MEM
1884 && MEM_VOLATILE_P (operands
[0]))))
1886 else if (operands
[1] == const0_rtx
1887 && ADDRESS_REG_P (operands
[0]))
1888 return "sub%.l %0,%0";
1889 else if (DATA_REG_P (operands
[0])
1890 && INTVAL (operands
[1]) < 128
1891 && INTVAL (operands
[1]) >= -128)
1893 return "moveq %1,%0";
1895 else if (INTVAL (operands
[1]) < 0x8000
1896 && INTVAL (operands
[1]) >= -0x8000)
1897 return "move%.w %1,%0";
1899 else if (CONSTANT_P (operands
[1]))
1900 return "move%.l %1,%0";
1901 /* Recognize the insn before a tablejump, one that refers
1902 to a table of offsets. Such an insn will need to refer
1903 to a label on the insn. So output one. Use the label-number
1904 of the table of offsets to generate this label. This code,
1905 and similar code below, assumes that there will be at most one
1906 reference to each table. */
1907 if (GET_CODE (operands
[1]) == MEM
1908 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1909 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1910 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1912 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1913 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1915 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1916 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1918 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1919 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1920 #endif /* not SGS */
1921 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1922 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1923 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1924 #ifdef SGS_SWITCH_TABLES
1925 /* Set flag saying we need to define the symbol
1926 LD%n (with value L%n-LI%n) at the end of the switch table. */
1927 switch_table_difference_label_flag
= 1;
1928 #endif /* SGS_SWITCH_TABLES */
1929 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1931 return "move%.w %1,%0";
1935 output_move_qimode (rtx
*operands
)
1939 /* This is probably useless, since it loses for pushing a struct
1940 of several bytes a byte at a time. */
1941 /* 68k family always modifies the stack pointer by at least 2, even for
1942 byte pushes. The 5200 (coldfire) does not do this. */
1943 if (GET_CODE (operands
[0]) == MEM
1944 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1945 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1946 && ! ADDRESS_REG_P (operands
[1])
1947 && ! TARGET_COLDFIRE
)
1949 xoperands
[1] = operands
[1];
1951 = gen_rtx_MEM (QImode
,
1952 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1953 /* Just pushing a byte puts it in the high byte of the halfword. */
1954 /* We must put it in the low-order, high-numbered byte. */
1955 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1957 xoperands
[3] = stack_pointer_rtx
;
1958 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1961 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1965 /* clr and st insns on 68000 read before writing.
1966 This isn't so on the 68010, but we have no TARGET_68010. */
1967 if (!ADDRESS_REG_P (operands
[0])
1968 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1969 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1971 if (operands
[1] == const0_rtx
)
1973 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1974 && GET_CODE (operands
[1]) == CONST_INT
1975 && (INTVAL (operands
[1]) & 255) == 255)
1981 if (GET_CODE (operands
[1]) == CONST_INT
1982 && DATA_REG_P (operands
[0])
1983 && INTVAL (operands
[1]) < 128
1984 && INTVAL (operands
[1]) >= -128)
1986 return "moveq %1,%0";
1988 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1989 return "sub%.l %0,%0";
1990 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1991 return "move%.l %1,%0";
1992 /* 68k family (including the 5200 coldfire) does not support byte moves to
1993 from address registers. */
1994 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1995 return "move%.w %1,%0";
1996 return "move%.b %1,%0";
2000 output_move_stricthi (rtx
*operands
)
2002 if (operands
[1] == const0_rtx
2003 /* clr insns on 68000 read before writing.
2004 This isn't so on the 68010, but we have no TARGET_68010. */
2005 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2006 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2008 return "move%.w %1,%0";
2012 output_move_strictqi (rtx
*operands
)
2014 if (operands
[1] == const0_rtx
2015 /* clr insns on 68000 read before writing.
2016 This isn't so on the 68010, but we have no TARGET_68010. */
2017 && ((TARGET_68020
|| TARGET_COLDFIRE
)
2018 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2020 return "move%.b %1,%0";
2023 /* Return the best assembler insn template
2024 for moving operands[1] into operands[0] as a fullword. */
2027 singlemove_string (rtx
*operands
)
2029 if (GET_CODE (operands
[1]) == CONST_INT
)
2030 return output_move_simode_const (operands
);
2031 return "move%.l %1,%0";
2035 /* Output assembler code to perform a doubleword move insn
2036 with operands OPERANDS. */
2039 output_move_double (rtx
*operands
)
2043 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2048 rtx addreg0
= 0, addreg1
= 0;
2049 int dest_overlapped_low
= 0;
2050 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2055 /* First classify both operands. */
2057 if (REG_P (operands
[0]))
2059 else if (offsettable_memref_p (operands
[0]))
2061 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2063 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2065 else if (GET_CODE (operands
[0]) == MEM
)
2070 if (REG_P (operands
[1]))
2072 else if (CONSTANT_P (operands
[1]))
2074 else if (offsettable_memref_p (operands
[1]))
2076 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2078 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2080 else if (GET_CODE (operands
[1]) == MEM
)
2085 /* Check for the cases that the operand constraints are not
2086 supposed to allow to happen. Abort if we get one,
2087 because generating code for these cases is painful. */
2089 if (optype0
== RNDOP
|| optype1
== RNDOP
)
2092 /* If one operand is decrementing and one is incrementing
2093 decrement the former register explicitly
2094 and change that operand into ordinary indexing. */
2096 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2098 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2100 output_asm_insn ("sub%.l %#12,%0", operands
);
2102 output_asm_insn ("subq%.l %#8,%0", operands
);
2103 if (GET_MODE (operands
[1]) == XFmode
)
2104 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2105 else if (GET_MODE (operands
[0]) == DFmode
)
2106 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2108 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2111 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2113 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2115 output_asm_insn ("sub%.l %#12,%1", operands
);
2117 output_asm_insn ("subq%.l %#8,%1", operands
);
2118 if (GET_MODE (operands
[1]) == XFmode
)
2119 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2120 else if (GET_MODE (operands
[1]) == DFmode
)
2121 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2123 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2127 /* If an operand is an unoffsettable memory ref, find a register
2128 we can increment temporarily to make it refer to the second word. */
2130 if (optype0
== MEMOP
)
2131 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2133 if (optype1
== MEMOP
)
2134 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2136 /* Ok, we can do one word at a time.
2137 Normally we do the low-numbered word first,
2138 but if either operand is autodecrementing then we
2139 do the high-numbered word first.
2141 In either case, set up in LATEHALF the operands to use
2142 for the high-numbered word and in some cases alter the
2143 operands in OPERANDS to be suitable for the low-numbered word. */
2147 if (optype0
== REGOP
)
2149 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2150 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2152 else if (optype0
== OFFSOP
)
2154 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2155 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2159 middlehalf
[0] = operands
[0];
2160 latehalf
[0] = operands
[0];
2163 if (optype1
== REGOP
)
2165 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2166 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2168 else if (optype1
== OFFSOP
)
2170 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2171 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2173 else if (optype1
== CNSTOP
)
2175 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2180 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2181 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2182 operands
[1] = GEN_INT (l
[0]);
2183 middlehalf
[1] = GEN_INT (l
[1]);
2184 latehalf
[1] = GEN_INT (l
[2]);
2186 else if (CONSTANT_P (operands
[1]))
2188 /* actually, no non-CONST_DOUBLE constant should ever
2191 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2192 latehalf
[1] = constm1_rtx
;
2194 latehalf
[1] = const0_rtx
;
2199 middlehalf
[1] = operands
[1];
2200 latehalf
[1] = operands
[1];
2204 /* size is not 12: */
2206 if (optype0
== REGOP
)
2207 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2208 else if (optype0
== OFFSOP
)
2209 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2211 latehalf
[0] = operands
[0];
2213 if (optype1
== REGOP
)
2214 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2215 else if (optype1
== OFFSOP
)
2216 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2217 else if (optype1
== CNSTOP
)
2218 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2220 latehalf
[1] = operands
[1];
2223 /* If insn is effectively movd N(sp),-(sp) then we will do the
2224 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2225 for the low word as well, to compensate for the first decrement of sp. */
2226 if (optype0
== PUSHOP
2227 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2228 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2229 operands
[1] = middlehalf
[1] = latehalf
[1];
2231 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2232 if the upper part of reg N does not appear in the MEM, arrange to
2233 emit the move late-half first. Otherwise, compute the MEM address
2234 into the upper part of N and use that as a pointer to the memory
2236 if (optype0
== REGOP
2237 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2239 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2241 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2242 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2244 /* If both halves of dest are used in the src memory address,
2245 compute the address into latehalf of dest.
2246 Note that this can't happen if the dest is two data regs. */
2248 xops
[0] = latehalf
[0];
2249 xops
[1] = XEXP (operands
[1], 0);
2250 output_asm_insn ("lea %a1,%0", xops
);
2251 if (GET_MODE (operands
[1]) == XFmode
)
2253 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2254 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2255 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2259 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2260 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2264 && reg_overlap_mentioned_p (middlehalf
[0],
2265 XEXP (operands
[1], 0)))
2267 /* Check for two regs used by both source and dest.
2268 Note that this can't happen if the dest is all data regs.
2269 It can happen if the dest is d6, d7, a0.
2270 But in that case, latehalf is an addr reg, so
2271 the code at compadr does ok. */
2273 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2274 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2277 /* JRV says this can't happen: */
2278 if (addreg0
|| addreg1
)
2281 /* Only the middle reg conflicts; simply put it last. */
2282 output_asm_insn (singlemove_string (operands
), operands
);
2283 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2284 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2287 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2288 /* If the low half of dest is mentioned in the source memory
2289 address, the arrange to emit the move late half first. */
2290 dest_overlapped_low
= 1;
2293 /* If one or both operands autodecrementing,
2294 do the two words, high-numbered first. */
2296 /* Likewise, the first move would clobber the source of the second one,
2297 do them in the other order. This happens only for registers;
2298 such overlap can't happen in memory unless the user explicitly
2299 sets it up, and that is an undefined circumstance. */
2301 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2302 || (optype0
== REGOP
&& optype1
== REGOP
2303 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2304 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2305 || dest_overlapped_low
)
2307 /* Make any unoffsettable addresses point at high-numbered word. */
2311 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2313 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2318 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2320 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2324 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2326 /* Undo the adds we just did. */
2328 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2330 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2334 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2336 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2338 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2341 /* Do low-numbered word. */
2342 return singlemove_string (operands
);
2345 /* Normal case: do the two words, low-numbered first. */
2347 output_asm_insn (singlemove_string (operands
), operands
);
2349 /* Do the middle one of the three words for long double */
2353 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2355 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2357 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2360 /* Make any unoffsettable addresses point at high-numbered word. */
2362 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2364 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2367 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2369 /* Undo the adds we just did. */
2373 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2375 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2380 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2382 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2388 /* Return a REG that occurs in ADDR with coefficient 1.
2389 ADDR can be effectively incremented by incrementing REG. */
2392 find_addr_reg (rtx addr
)
2394 while (GET_CODE (addr
) == PLUS
)
2396 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2397 addr
= XEXP (addr
, 0);
2398 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2399 addr
= XEXP (addr
, 1);
2400 else if (CONSTANT_P (XEXP (addr
, 0)))
2401 addr
= XEXP (addr
, 1);
2402 else if (CONSTANT_P (XEXP (addr
, 1)))
2403 addr
= XEXP (addr
, 0);
2407 if (GET_CODE (addr
) == REG
)
2412 /* Output assembler code to perform a 32 bit 3 operand add. */
2415 output_addsi3 (rtx
*operands
)
2417 if (! operands_match_p (operands
[0], operands
[1]))
2419 if (!ADDRESS_REG_P (operands
[1]))
2421 rtx tmp
= operands
[1];
2423 operands
[1] = operands
[2];
2427 /* These insns can result from reloads to access
2428 stack slots over 64k from the frame pointer. */
2429 if (GET_CODE (operands
[2]) == CONST_INT
2430 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2431 return "move%.l %2,%0\n\tadd%.l %1,%0";
2433 if (GET_CODE (operands
[2]) == REG
)
2434 return "lea 0(%1,%2.l),%0";
2436 return "lea %c2(%1),%0";
2437 #elif defined(MOTOROLA)
2438 if (GET_CODE (operands
[2]) == REG
)
2439 return "lea (%1,%2.l),%0";
2441 return "lea (%c2,%1),%0";
2442 #else /* not MOTOROLA (MIT syntax) */
2443 if (GET_CODE (operands
[2]) == REG
)
2444 return "lea %1@(0,%2:l),%0";
2446 return "lea %1@(%c2),%0";
2447 #endif /* not MOTOROLA */
2449 if (GET_CODE (operands
[2]) == CONST_INT
)
2451 if (INTVAL (operands
[2]) > 0
2452 && INTVAL (operands
[2]) <= 8)
2453 return "addq%.l %2,%0";
2454 if (INTVAL (operands
[2]) < 0
2455 && INTVAL (operands
[2]) >= -8)
2457 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2458 return "subq%.l %2,%0";
2460 /* On the CPU32 it is faster to use two addql instructions to
2461 add a small integer (8 < N <= 16) to a register.
2462 Likewise for subql. */
2463 if (TARGET_CPU32
&& REG_P (operands
[0]))
2465 if (INTVAL (operands
[2]) > 8
2466 && INTVAL (operands
[2]) <= 16)
2468 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2469 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2471 if (INTVAL (operands
[2]) < -8
2472 && INTVAL (operands
[2]) >= -16)
2474 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2475 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2478 if (ADDRESS_REG_P (operands
[0])
2479 && INTVAL (operands
[2]) >= -0x8000
2480 && INTVAL (operands
[2]) < 0x8000)
2483 return "add%.w %2,%0";
2486 return "lea (%c2,%0),%0";
2488 return "lea %0@(%c2),%0";
2492 return "add%.l %2,%0";
2495 /* Store in cc_status the expressions that the condition codes will
2496 describe after execution of an instruction whose pattern is EXP.
2497 Do not alter them if the instruction would not alter the cc's. */
2499 /* On the 68000, all the insns to store in an address register fail to
2500 set the cc's. However, in some cases these instructions can make it
2501 possibly invalid to use the saved cc's. In those cases we clear out
2502 some or all of the saved cc's so they won't be used. */
2505 notice_update_cc (rtx exp
, rtx insn
)
2507 if (GET_CODE (exp
) == SET
)
2509 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2513 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2515 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2516 cc_status
.value1
= 0;
2517 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2518 cc_status
.value2
= 0;
2520 else if (!FP_REG_P (SET_DEST (exp
))
2521 && SET_DEST (exp
) != cc0_rtx
2522 && (FP_REG_P (SET_SRC (exp
))
2523 || GET_CODE (SET_SRC (exp
)) == FIX
2524 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2525 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2529 /* A pair of move insns doesn't produce a useful overall cc. */
2530 else if (!FP_REG_P (SET_DEST (exp
))
2531 && !FP_REG_P (SET_SRC (exp
))
2532 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2533 && (GET_CODE (SET_SRC (exp
)) == REG
2534 || GET_CODE (SET_SRC (exp
)) == MEM
2535 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2539 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2543 else if (XEXP (exp
, 0) != pc_rtx
)
2545 cc_status
.flags
= 0;
2546 cc_status
.value1
= XEXP (exp
, 0);
2547 cc_status
.value2
= XEXP (exp
, 1);
2550 else if (GET_CODE (exp
) == PARALLEL
2551 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2553 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2555 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2557 cc_status
.flags
= 0;
2558 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2559 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2564 if (cc_status
.value2
!= 0
2565 && ADDRESS_REG_P (cc_status
.value2
)
2566 && GET_MODE (cc_status
.value2
) == QImode
)
2568 if (cc_status
.value2
!= 0)
2569 switch (GET_CODE (cc_status
.value2
))
2571 case PLUS
: case MINUS
: case MULT
:
2572 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2573 #if 0 /* These instructions always clear the overflow bit */
2574 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2575 case ROTATE
: case ROTATERT
:
2577 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2578 cc_status
.flags
|= CC_NO_OVERFLOW
;
2581 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2582 ends with a move insn moving r2 in r2's mode.
2583 Thus, the cc's are set for r2.
2584 This can set N bit spuriously. */
2585 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2590 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2592 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2593 cc_status
.value2
= 0;
2594 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2595 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2596 cc_status
.flags
= CC_IN_68881
;
2600 output_move_const_double (rtx
*operands
)
2602 int code
= standard_68881_constant_p (operands
[1]);
2606 static char buf
[40];
2608 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2611 return "fmove%.d %1,%0";
2615 output_move_const_single (rtx
*operands
)
2617 int code
= standard_68881_constant_p (operands
[1]);
2621 static char buf
[40];
2623 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2626 return "fmove%.s %f1,%0";
2629 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2630 from the "fmovecr" instruction.
2631 The value, anded with 0xff, gives the code to use in fmovecr
2632 to get the desired constant. */
2634 /* This code has been fixed for cross-compilation. */
2636 static int inited_68881_table
= 0;
2638 static const char *const strings_68881
[7] = {
2648 static const int codes_68881
[7] = {
2658 REAL_VALUE_TYPE values_68881
[7];
2660 /* Set up values_68881 array by converting the decimal values
2661 strings_68881 to binary. */
2664 init_68881_table (void)
2668 enum machine_mode mode
;
2671 for (i
= 0; i
< 7; i
++)
2675 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2676 values_68881
[i
] = r
;
2678 inited_68881_table
= 1;
2682 standard_68881_constant_p (rtx x
)
2687 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2688 used at all on those chips. */
2689 if (TARGET_68040
|| TARGET_68060
)
2692 if (! inited_68881_table
)
2693 init_68881_table ();
2695 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2697 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2699 for (i
= 0; i
< 6; i
++)
2701 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2702 return (codes_68881
[i
]);
2705 if (GET_MODE (x
) == SFmode
)
2708 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2709 return (codes_68881
[6]);
2711 /* larger powers of ten in the constants ram are not used
2712 because they are not equal to a `double' C constant. */
2716 /* If X is a floating-point constant, return the logarithm of X base 2,
2717 or 0 if X is not a power of 2. */
2720 floating_exact_log2 (rtx x
)
2722 REAL_VALUE_TYPE r
, r1
;
2725 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2727 if (REAL_VALUES_LESS (r
, dconst1
))
2730 exp
= real_exponent (&r
);
2731 real_2expN (&r1
, exp
);
2732 if (REAL_VALUES_EQUAL (r1
, r
))
2738 /* A C compound statement to output to stdio stream STREAM the
2739 assembler syntax for an instruction operand X. X is an RTL
2742 CODE is a value that can be used to specify one of several ways
2743 of printing the operand. It is used when identical operands
2744 must be printed differently depending on the context. CODE
2745 comes from the `%' specification that was used to request
2746 printing of the operand. If the specification was just `%DIGIT'
2747 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2748 is the ASCII code for LTR.
2750 If X is a register, this macro should print the register's name.
2751 The names can be found in an array `reg_names' whose type is
2752 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2754 When the machine description has a specification `%PUNCT' (a `%'
2755 followed by a punctuation character), this macro is called with
2756 a null pointer for X and the punctuation character for CODE.
2758 The m68k specific codes are:
2760 '.' for dot needed in Motorola-style opcode names.
2761 '-' for an operand pushing on the stack:
2762 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2763 '+' for an operand pushing on the stack:
2764 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2765 '@' for a reference to the top word on the stack:
2766 sp@, (sp) or (%sp) depending on the style of syntax.
2767 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2768 but & in SGS syntax).
2769 '!' for the cc register (used in an `and to cc' insn).
2770 '$' for the letter `s' in an op code, but only on the 68040.
2771 '&' for the letter `d' in an op code, but only on the 68040.
2772 '/' for register prefix needed by longlong.h.
2774 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2775 'd' to force memory addressing to be absolute, not relative.
2776 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2777 'o' for operands to go directly to output_operand_address (bypassing
2778 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2779 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2780 or print pair of registers as rx:ry.
2785 print_operand (FILE *file
, rtx op
, int letter
)
2789 #if defined (MOTOROLA)
2790 fprintf (file
, ".");
2793 else if (letter
== '#')
2795 asm_fprintf (file
, "%I");
2797 else if (letter
== '-')
2800 asm_fprintf (file
, "-(%Rsp)");
2802 asm_fprintf (file
, "%Rsp@-");
2805 else if (letter
== '+')
2808 asm_fprintf (file
, "(%Rsp)+");
2810 asm_fprintf (file
, "%Rsp@+");
2813 else if (letter
== '@')
2816 asm_fprintf (file
, "(%Rsp)");
2818 asm_fprintf (file
, "%Rsp@");
2821 else if (letter
== '!')
2823 asm_fprintf (file
, "%Rfpcr");
2825 else if (letter
== '$')
2827 if (TARGET_68040_ONLY
)
2829 fprintf (file
, "s");
2832 else if (letter
== '&')
2834 if (TARGET_68040_ONLY
)
2836 fprintf (file
, "d");
2839 else if (letter
== '/')
2841 asm_fprintf (file
, "%R");
2843 else if (letter
== 'o')
2845 /* This is only for direct addresses with TARGET_PCREL */
2846 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2849 output_addr_const (file
, XEXP (op
, 0));
2851 else if (GET_CODE (op
) == REG
)
2854 /* Print out the second register name of a register pair.
2855 I.e., R (6) => 7. */
2856 fputs (reg_names
[REGNO (op
) + 1], file
);
2858 fputs (reg_names
[REGNO (op
)], file
);
2860 else if (GET_CODE (op
) == MEM
)
2862 output_address (XEXP (op
, 0));
2863 if (letter
== 'd' && ! TARGET_68020
2864 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2865 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2866 && INTVAL (XEXP (op
, 0)) < 0x8000
2867 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2870 fprintf (file
, ".l");
2872 fprintf (file
, ":l");
2876 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2879 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2880 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2882 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2885 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2886 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2888 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2891 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2892 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2896 /* Use `print_operand_address' instead of `output_addr_const'
2897 to ensure that we print relevant PIC stuff. */
2898 asm_fprintf (file
, "%I");
2900 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2901 print_operand_address (file
, op
);
2903 output_addr_const (file
, op
);
2908 /* A C compound statement to output to stdio stream STREAM the
2909 assembler syntax for an instruction operand that is a memory
2910 reference whose address is ADDR. ADDR is an RTL expression.
2912 Note that this contains a kludge that knows that the only reason
2913 we have an address (plus (label_ref...) (reg...)) when not generating
2914 PIC code is in the insn before a tablejump, and we know that m68k.md
2915 generates a label LInnn: on such an insn.
2917 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2918 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2920 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2921 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2922 we want. This difference can be accommodated by using an assembler
2923 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2924 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2925 macro. See m68k/sgs.h for an example; for versions without the bug.
2926 Some assemblers refuse all the above solutions. The workaround is to
2927 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2930 They also do not like things like "pea 1.w", so we simple leave off
2931 the .w on small constants.
2933 This routine is responsible for distinguishing between -fpic and -fPIC
2934 style relocations in an address. When generating -fpic code the
2935 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2936 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2938 #ifndef ASM_OUTPUT_CASE_FETCH
2941 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2942 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2944 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2945 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2948 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2949 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2951 #endif /* ASM_OUTPUT_CASE_FETCH */
2954 print_operand_address (FILE *file
, rtx addr
)
2956 register rtx reg1
, reg2
, breg
, ireg
;
2959 switch (GET_CODE (addr
))
2963 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2965 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2970 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2972 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2977 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2979 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2983 reg1
= reg2
= ireg
= breg
= offset
= 0;
2984 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2986 offset
= XEXP (addr
, 0);
2987 addr
= XEXP (addr
, 1);
2989 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2991 offset
= XEXP (addr
, 1);
2992 addr
= XEXP (addr
, 0);
2994 if (GET_CODE (addr
) != PLUS
)
2998 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3000 reg1
= XEXP (addr
, 0);
3001 addr
= XEXP (addr
, 1);
3003 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3005 reg1
= XEXP (addr
, 1);
3006 addr
= XEXP (addr
, 0);
3008 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3010 reg1
= XEXP (addr
, 0);
3011 addr
= XEXP (addr
, 1);
3013 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3015 reg1
= XEXP (addr
, 1);
3016 addr
= XEXP (addr
, 0);
3018 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3020 reg1
= XEXP (addr
, 0);
3021 addr
= XEXP (addr
, 1);
3023 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3025 reg1
= XEXP (addr
, 1);
3026 addr
= XEXP (addr
, 0);
3028 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3029 || GET_CODE (addr
) == SIGN_EXTEND
)
3041 #if 0 /* for OLD_INDEXING */
3042 else if (GET_CODE (addr
) == PLUS
)
3044 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3046 reg2
= XEXP (addr
, 0);
3047 addr
= XEXP (addr
, 1);
3049 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3051 reg2
= XEXP (addr
, 1);
3052 addr
= XEXP (addr
, 0);
3064 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3065 || GET_CODE (reg1
) == MULT
))
3066 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3071 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3076 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3077 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3080 if (GET_CODE (ireg
) == MULT
)
3082 scale
= INTVAL (XEXP (ireg
, 1));
3083 ireg
= XEXP (ireg
, 0);
3085 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3087 ASM_OUTPUT_CASE_FETCH (file
,
3088 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3089 reg_names
[REGNO (XEXP (ireg
, 0))]);
3090 fprintf (file
, "w");
3094 ASM_OUTPUT_CASE_FETCH (file
,
3095 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3096 reg_names
[REGNO (ireg
)]);
3097 fprintf (file
, "l");
3102 fprintf (file
, "*%d", scale
);
3104 fprintf (file
, ":%d", scale
);
3110 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3111 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3113 ASM_OUTPUT_CASE_FETCH (file
,
3114 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3115 reg_names
[REGNO (breg
)]);
3116 fprintf (file
, "l)");
3119 if (ireg
!= 0 || breg
!= 0)
3126 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3133 output_addr_const (file
, addr
);
3134 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3136 fprintf (file
, "@GOT");
3138 fprintf (file
, ".w");
3141 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3147 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3150 output_addr_const (file
, addr
);
3151 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3152 fprintf (file
, ":w");
3153 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3154 fprintf (file
, ":l");
3156 if (addr
!= 0 && ireg
!= 0)
3161 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3163 scale
= INTVAL (XEXP (ireg
, 1));
3164 ireg
= XEXP (ireg
, 0);
3166 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3169 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3171 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3177 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3179 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3185 fprintf (file
, "*%d", scale
);
3187 fprintf (file
, ":%d", scale
);
3193 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3194 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3196 ASM_OUTPUT_CASE_FETCH (file
,
3197 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3198 reg_names
[REGNO (reg1
)]);
3199 fprintf (file
, "l)");
3202 /* FALL-THROUGH (is this really what we want?) */
3204 if (GET_CODE (addr
) == CONST_INT
3205 && INTVAL (addr
) < 0x8000
3206 && INTVAL (addr
) >= -0x8000)
3210 /* Many SGS assemblers croak on size specifiers for constants. */
3211 fprintf (file
, "%d", (int) INTVAL (addr
));
3213 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3216 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3219 else if (GET_CODE (addr
) == CONST_INT
)
3221 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3223 else if (TARGET_PCREL
)
3226 output_addr_const (file
, addr
);
3228 asm_fprintf (file
, ":w,%Rpc)");
3230 asm_fprintf (file
, ":l,%Rpc)");
3234 /* Special case for SYMBOL_REF if the symbol name ends in
3235 `.<letter>', this can be mistaken as a size suffix. Put
3236 the name in parentheses. */
3237 if (GET_CODE (addr
) == SYMBOL_REF
3238 && strlen (XSTR (addr
, 0)) > 2
3239 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3242 output_addr_const (file
, addr
);
3246 output_addr_const (file
, addr
);
3252 /* Check for cases where a clr insns can be omitted from code using
3253 strict_low_part sets. For example, the second clrl here is not needed:
3254 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3256 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3257 insn we are checking for redundancy. TARGET is the register set by the
3261 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3266 p
= prev_nonnote_insn (first_insn
);
3270 /* If it isn't an insn, then give up. */
3271 if (GET_CODE (p
) != INSN
)
3274 if (reg_set_p (target
, p
))
3276 rtx set
= single_set (p
);
3279 /* If it isn't an easy to recognize insn, then give up. */
3283 dest
= SET_DEST (set
);
3285 /* If this sets the entire target register to zero, then our
3286 first_insn is redundant. */
3287 if (rtx_equal_p (dest
, target
)
3288 && SET_SRC (set
) == const0_rtx
)
3290 else if (GET_CODE (dest
) == STRICT_LOW_PART
3291 && GET_CODE (XEXP (dest
, 0)) == REG
3292 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3293 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3294 <= GET_MODE_SIZE (mode
)))
3295 /* This is a strict low part set which modifies less than
3296 we are using, so it is safe. */
3302 p
= prev_nonnote_insn (p
);
3309 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3310 range carefully since this predicate is used in DImode contexts. Also, we
3311 need some extra crud to make it work when hosted on 64-bit machines. */
3314 const_uint32_operand (rtx op
, enum machine_mode mode
)
3316 /* It doesn't make sense to ask this question with a mode that is
3317 not larger than 32 bits. */
3318 if (GET_MODE_BITSIZE (mode
) <= 32)
3321 #if HOST_BITS_PER_WIDE_INT > 32
3322 /* All allowed constants will fit a CONST_INT. */
3323 return (GET_CODE (op
) == CONST_INT
3324 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3326 return (GET_CODE (op
) == CONST_INT
3327 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3331 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3332 to check the range carefully since this predicate is used in DImode
3336 const_sint32_operand (rtx op
, enum machine_mode mode
)
3338 /* It doesn't make sense to ask this question with a mode that is
3339 not larger than 32 bits. */
3340 if (GET_MODE_BITSIZE (mode
) <= 32)
3343 /* All allowed constants will fit a CONST_INT. */
3344 return (GET_CODE (op
) == CONST_INT
3345 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3348 /* Operand predicates for implementing asymmetric pc-relative addressing
3349 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3350 when used as a source operand, but not as a destination operand.
3352 We model this by restricting the meaning of the basic predicates
3353 (general_operand, memory_operand, etc) to forbid the use of this
3354 addressing mode, and then define the following predicates that permit
3355 this addressing mode. These predicates can then be used for the
3356 source operands of the appropriate instructions.
3358 n.b. While it is theoretically possible to change all machine patterns
3359 to use this addressing more where permitted by the architecture,
3360 it has only been implemented for "common" cases: SImode, HImode, and
3361 QImode operands, and only for the principle operations that would
3362 require this addressing mode: data movement and simple integer operations.
3364 In parallel with these new predicates, two new constraint letters
3365 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3366 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3367 In the pcrel case 's' is only valid in combination with 'a' registers.
3368 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3369 of how these constraints are used.
3371 The use of these predicates is strictly optional, though patterns that
3372 don't will cause an extra reload register to be allocated where one
3375 lea (abc:w,%pc),%a0 ; need to reload address
3376 moveq &1,%d1 ; since write to pc-relative space
3377 movel %d1,%a0@ ; is not allowed
3379 lea (abc:w,%pc),%a1 ; no need to reload address here
3380 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3382 For more info, consult tiemann@cygnus.com.
3385 All of the ugliness with predicates and constraints is due to the
3386 simple fact that the m68k does not allow a pc-relative addressing
3387 mode as a destination. gcc does not distinguish between source and
3388 destination addresses. Hence, if we claim that pc-relative address
3389 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3390 end up with invalid code. To get around this problem, we left
3391 pc-relative modes as invalid addresses, and then added special
3392 predicates and constraints to accept them.
3394 A cleaner way to handle this is to modify gcc to distinguish
3395 between source and destination addresses. We can then say that
3396 pc-relative is a valid source address but not a valid destination
3397 address, and hopefully avoid a lot of the predicate and constraint
3398 hackery. Unfortunately, this would be a pretty big change. It would
3399 be a useful change for a number of ports, but there aren't any current
3400 plans to undertake this.
3402 ***************************************************************************/
3405 /* Special case of a general operand that's used as a source operand.
3406 Use this to permit reads from PC-relative memory when -mpcrel
3410 general_src_operand (rtx op
, enum machine_mode mode
)
3413 && GET_CODE (op
) == MEM
3414 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3415 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3416 || GET_CODE (XEXP (op
, 0)) == CONST
))
3418 return general_operand (op
, mode
);
3421 /* Special case of a nonimmediate operand that's used as a source.
3422 Use this to permit reads from PC-relative memory when -mpcrel
3426 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3428 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3429 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3430 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3431 || GET_CODE (XEXP (op
, 0)) == CONST
))
3433 return nonimmediate_operand (op
, mode
);
3436 /* Special case of a memory operand that's used as a source.
3437 Use this to permit reads from PC-relative memory when -mpcrel
3441 memory_src_operand (rtx op
, enum machine_mode mode
)
3443 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3444 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3445 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3446 || GET_CODE (XEXP (op
, 0)) == CONST
))
3448 return memory_operand (op
, mode
);
3451 /* Predicate that accepts only a pc-relative address. This is needed
3452 because pc-relative addresses don't satisfy the predicate
3453 "general_src_operand". */
3456 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3458 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3459 || GET_CODE (op
) == CONST
);
3463 output_andsi3 (rtx
*operands
)
3466 if (GET_CODE (operands
[2]) == CONST_INT
3467 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3468 && (DATA_REG_P (operands
[0])
3469 || offsettable_memref_p (operands
[0]))
3470 && !TARGET_COLDFIRE
)
3472 if (GET_CODE (operands
[0]) != REG
)
3473 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3474 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3475 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3477 if (operands
[2] == const0_rtx
)
3479 return "and%.w %2,%0";
3481 if (GET_CODE (operands
[2]) == CONST_INT
3482 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3483 && (DATA_REG_P (operands
[0])
3484 || offsettable_memref_p (operands
[0])))
3486 if (DATA_REG_P (operands
[0]))
3488 operands
[1] = GEN_INT (logval
);
3492 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3493 operands
[1] = GEN_INT (logval
% 8);
3495 /* This does not set condition codes in a standard way. */
3497 return "bclr %1,%0";
3499 return "and%.l %2,%0";
3503 output_iorsi3 (rtx
*operands
)
3505 register int logval
;
3506 if (GET_CODE (operands
[2]) == CONST_INT
3507 && INTVAL (operands
[2]) >> 16 == 0
3508 && (DATA_REG_P (operands
[0])
3509 || offsettable_memref_p (operands
[0]))
3510 && !TARGET_COLDFIRE
)
3512 if (GET_CODE (operands
[0]) != REG
)
3513 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3514 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3516 if (INTVAL (operands
[2]) == 0xffff)
3517 return "mov%.w %2,%0";
3518 return "or%.w %2,%0";
3520 if (GET_CODE (operands
[2]) == CONST_INT
3521 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3522 && (DATA_REG_P (operands
[0])
3523 || offsettable_memref_p (operands
[0])))
3525 if (DATA_REG_P (operands
[0]))
3526 operands
[1] = GEN_INT (logval
);
3529 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3530 operands
[1] = GEN_INT (logval
% 8);
3533 return "bset %1,%0";
3535 return "or%.l %2,%0";
3539 output_xorsi3 (rtx
*operands
)
3541 register int logval
;
3542 if (GET_CODE (operands
[2]) == CONST_INT
3543 && INTVAL (operands
[2]) >> 16 == 0
3544 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3545 && !TARGET_COLDFIRE
)
3547 if (! DATA_REG_P (operands
[0]))
3548 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3549 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3551 if (INTVAL (operands
[2]) == 0xffff)
3553 return "eor%.w %2,%0";
3555 if (GET_CODE (operands
[2]) == CONST_INT
3556 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3557 && (DATA_REG_P (operands
[0])
3558 || offsettable_memref_p (operands
[0])))
3560 if (DATA_REG_P (operands
[0]))
3561 operands
[1] = GEN_INT (logval
);
3564 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3565 operands
[1] = GEN_INT (logval
% 8);
3568 return "bchg %1,%0";
3570 return "eor%.l %2,%0";
3573 #ifdef M68K_TARGET_COFF
3575 /* Output assembly to switch to section NAME with attribute FLAGS. */
3578 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3582 if (flags
& SECTION_WRITE
)
3587 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3590 #endif /* M68K_TARGET_COFF */
3594 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3595 unsigned long labelno
)
3597 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3598 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3600 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3604 m68k_hp320_file_start (void)
3606 /* version 1: 68010.
3607 2: 68020 without FPU.
3608 3: 68020 with FPU. */
3609 fprintf (asm_out_file
, "\tversion %d\n",
3610 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3615 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3616 HOST_WIDE_INT delta
,
3617 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3623 if (delta
> 0 && delta
<= 8)
3625 asm_fprintf (file
, "\taddq.l %I%d,4(%Rsp)\n", (int) delta
);
3627 asm_fprintf (file
, "\taddql %I%d,%Rsp@(4)\n", (int) delta
);
3629 else if (delta
< 0 && delta
>= -8)
3631 asm_fprintf (file
, "\tsubq.l %I%d,4(%Rsp)\n", (int) -delta
);
3633 asm_fprintf (file
, "\tsubql %I%d,%Rsp@(4)\n", (int) -delta
);
3637 asm_fprintf (file
, "\tadd.l %I%wd,4(%Rsp)\n", delta
);
3639 asm_fprintf (file
, "\taddl %I%wd,%Rsp@(4)\n", delta
);
3642 xops
[0] = DECL_RTL (function
);
3644 /* Logic taken from call patterns in m68k.md. */
3649 else if ((flag_pic
== 1) || TARGET_68020
)
3656 fmt
= "bra.l %0@PLTPC";
3658 fmt
= "bra %0@PLTPC";
3669 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3670 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3672 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3676 #if defined (MOTOROLA) && !defined (USE_GAS)
3683 output_asm_insn (fmt
, xops
);