1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* The minimum number of integer registers that we want to save with the
74 movem instruction. Using two movel instructions instead of a single
75 moveml is about 15% faster for the 68020 and 68030 at no expense in
77 #define MIN_MOVEM_REGS 3
79 /* The minimum number of floating point registers that we want to save
80 with the fmovem instruction. */
81 #define MIN_FMOVEM_REGS 1
83 /* Structure describing stack frame layout. */
86 /* Stack pointer to frame pointer offset. */
89 /* Offset of FPU registers. */
90 HOST_WIDE_INT foffset
;
92 /* Frame size in bytes (rounded up). */
95 /* Data and address register. */
97 unsigned int reg_mask
;
101 unsigned int fpu_mask
;
103 /* Offsets relative to ARG_POINTER. */
104 HOST_WIDE_INT frame_pointer_offset
;
105 HOST_WIDE_INT stack_pointer_offset
;
107 /* Function which the above information refers to. */
111 /* Current frame information calculated by m68k_compute_frame_layout(). */
112 static struct m68k_frame current_frame
;
114 /* Structure describing an m68k address.
116 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
117 with null fields evaluating to 0. Here:
119 - BASE satisfies m68k_legitimate_base_reg_p
120 - INDEX satisfies m68k_legitimate_index_reg_p
121 - OFFSET satisfies m68k_legitimate_constant_address_p
123 INDEX is either HImode or SImode. The other fields are SImode.
125 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
126 the address is (BASE)+. */
127 struct m68k_address
{
135 static bool m68k_handle_option (size_t, const char *, int);
136 static rtx
find_addr_reg (rtx
);
137 static const char *singlemove_string (rtx
*);
138 #ifdef M68K_TARGET_COFF
139 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
140 #endif /* M68K_TARGET_COFF */
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_rtx_costs (rtx
, int, int, int *);
152 /* Specify the identification number of the library being built */
153 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
155 /* Nonzero if the last compare/test insn had FP operands. The
156 sCC expanders peek at this to determine what to do for the
157 68060, which has no fsCC instructions. */
158 int m68k_last_compare_had_fp_operands
;
160 /* Initialize the GCC target structure. */
162 #if INT_OP_GROUP == INT_OP_DOT_WORD
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
167 #if INT_OP_GROUP == INT_OP_NO_DOT
168 #undef TARGET_ASM_BYTE_OP
169 #define TARGET_ASM_BYTE_OP "\tbyte\t"
170 #undef TARGET_ASM_ALIGNED_HI_OP
171 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
172 #undef TARGET_ASM_ALIGNED_SI_OP
173 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
176 #if INT_OP_GROUP == INT_OP_DC
177 #undef TARGET_ASM_BYTE_OP
178 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
179 #undef TARGET_ASM_ALIGNED_HI_OP
180 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
181 #undef TARGET_ASM_ALIGNED_SI_OP
182 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
185 #undef TARGET_ASM_UNALIGNED_HI_OP
186 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
187 #undef TARGET_ASM_UNALIGNED_SI_OP
188 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
190 #undef TARGET_ASM_OUTPUT_MI_THUNK
191 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
192 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
193 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
195 #undef TARGET_ASM_FILE_START_APP_OFF
196 #define TARGET_ASM_FILE_START_APP_OFF true
198 #undef TARGET_DEFAULT_TARGET_FLAGS
199 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
200 #undef TARGET_HANDLE_OPTION
201 #define TARGET_HANDLE_OPTION m68k_handle_option
203 #undef TARGET_RTX_COSTS
204 #define TARGET_RTX_COSTS m68k_rtx_costs
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
209 #undef TARGET_PROMOTE_PROTOTYPES
210 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
212 #undef TARGET_STRUCT_VALUE_RTX
213 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
215 #undef TARGET_CANNOT_FORCE_CONST_MEM
216 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
218 static const struct attribute_spec m68k_attribute_table
[] =
220 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
221 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
222 { NULL
, 0, 0, false, false, false, NULL
}
225 struct gcc_target targetm
= TARGET_INITIALIZER
;
227 /* Base flags for 68k ISAs. */
228 #define FL_FOR_isa_00 FL_ISA_68000
229 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
230 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
231 generated 68881 code for 68020 and 68030 targets unless explicitly told
233 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
234 | FL_BITFIELD | FL_68881)
235 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
236 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
238 /* Base flags for ColdFire ISAs. */
239 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
240 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
241 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
242 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
243 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
247 /* Traditional 68000 instruction sets. */
253 /* ColdFire instruction set variants. */
261 /* Information about one of the -march, -mcpu or -mtune arguments. */
262 struct m68k_target_selection
264 /* The argument being described. */
267 /* For -mcpu, this is the device selected by the option.
268 For -mtune and -march, it is a representative device
269 for the microarchitecture or ISA respectively. */
270 enum target_device device
;
272 /* The M68K_DEVICE fields associated with DEVICE. See the comment
273 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
275 enum uarch_type microarch
;
280 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
281 static const struct m68k_target_selection all_devices
[] =
283 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
284 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
285 #include "m68k-devices.def"
287 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
290 /* A list of all ISAs, mapping each one to a representative device.
291 Used for -march selection. */
292 static const struct m68k_target_selection all_isas
[] =
294 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
295 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
296 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
297 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
298 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
299 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
300 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
301 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
303 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
305 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
309 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
312 /* A list of all microarchitectures, mapping each one to a representative
313 device. Used for -mtune selection. */
314 static const struct m68k_target_selection all_microarchs
[] =
316 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
317 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
318 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
319 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
320 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
321 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
322 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
323 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
324 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
325 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
326 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
328 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
329 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
333 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
336 /* The entries associated with the -mcpu, -march and -mtune settings,
337 or null for options that have not been used. */
338 const struct m68k_target_selection
*m68k_cpu_entry
;
339 const struct m68k_target_selection
*m68k_arch_entry
;
340 const struct m68k_target_selection
*m68k_tune_entry
;
342 /* Which CPU we are generating code for. */
343 enum target_device m68k_cpu
;
345 /* Which microarchitecture to tune for. */
346 enum uarch_type m68k_tune
;
348 /* Which FPU to use. */
349 enum fpu_type m68k_fpu
;
351 /* The set of FL_* flags that apply to the target processor. */
352 unsigned int m68k_cpu_flags
;
354 /* Asm templates for calling or jumping to an arbitrary symbolic address,
355 or NULL if such calls or jumps are not supported. The address is held
357 const char *m68k_symbolic_call
;
358 const char *m68k_symbolic_jump
;
360 /* See whether TABLE has an entry with name NAME. Return true and
361 store the entry in *ENTRY if so, otherwise return false and
362 leave *ENTRY alone. */
365 m68k_find_selection (const struct m68k_target_selection
**entry
,
366 const struct m68k_target_selection
*table
,
371 for (i
= 0; table
[i
].name
; i
++)
372 if (strcmp (table
[i
].name
, name
) == 0)
380 /* Implement TARGET_HANDLE_OPTION. */
383 m68k_handle_option (size_t code
, const char *arg
, int value
)
388 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
391 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
394 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
397 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
400 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
403 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
406 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
409 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
412 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
419 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
423 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
426 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
428 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
431 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
433 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
436 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
439 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
442 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
445 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
449 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
451 case OPT_mshared_library_id_
:
452 if (value
> MAX_LIBRARY_ID
)
453 error ("-mshared-library-id=%s is not between 0 and %d",
454 arg
, MAX_LIBRARY_ID
);
456 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
464 /* Sometimes certain combinations of command options do not make
465 sense on a particular target machine. You can define a macro
466 `OVERRIDE_OPTIONS' to take account of this. This macro, if
467 defined, is executed once just after all the command options have
470 Don't use this macro to turn on various extra optimizations for
471 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
474 override_options (void)
476 const struct m68k_target_selection
*entry
;
477 unsigned long target_mask
;
485 -march=ARCH should generate code that runs any processor
486 implementing architecture ARCH. -mcpu=CPU should override -march
487 and should generate code that runs on processor CPU, making free
488 use of any instructions that CPU understands. -mtune=UARCH applies
489 on top of -mcpu or -march and optimizes the code for UARCH. It does
490 not change the target architecture. */
493 /* Complain if the -march setting is for a different microarchitecture,
494 or includes flags that the -mcpu setting doesn't. */
496 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
497 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
498 warning (0, "-mcpu=%s conflicts with -march=%s",
499 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
501 entry
= m68k_cpu_entry
;
504 entry
= m68k_arch_entry
;
507 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
509 m68k_cpu_flags
= entry
->flags
;
511 /* Use the architecture setting to derive default values for
514 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
515 target_mask
|= MASK_BITFIELD
;
516 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
517 target_mask
|= MASK_CF_HWDIV
;
518 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
519 target_mask
|= MASK_HARD_FLOAT
;
520 target_flags
|= target_mask
& ~target_flags_explicit
;
522 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
523 m68k_cpu
= entry
->device
;
525 m68k_tune
= m68k_tune_entry
->microarch
;
526 #ifdef M68K_DEFAULT_TUNE
527 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
528 m68k_tune
= M68K_DEFAULT_TUNE
;
531 m68k_tune
= entry
->microarch
;
533 /* Set the type of FPU. */
534 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
535 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
538 if (TARGET_COLDFIRE_FPU
)
540 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
541 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
544 /* Sanity check to ensure that msep-data and mid-sahred-library are not
545 * both specified together. Doing so simply doesn't make sense.
547 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
548 error ("cannot specify both -msep-data and -mid-shared-library");
550 /* If we're generating code for a separate A5 relative data segment,
551 * we've got to enable -fPIC as well. This might be relaxable to
552 * -fpic but it hasn't been tested properly.
554 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
557 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
558 error if the target does not support them. */
559 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
560 error ("-mpcrel -fPIC is not currently supported on selected cpu");
562 /* ??? A historic way of turning on pic, or is this intended to
563 be an embedded thing that doesn't have the same name binding
564 significance that it does on hosted ELF systems? */
565 if (TARGET_PCREL
&& flag_pic
== 0)
570 #if MOTOROLA && !defined (USE_GAS)
571 m68k_symbolic_call
= "jsr %a0";
572 m68k_symbolic_jump
= "jmp %a0";
574 m68k_symbolic_call
= "jbsr %a0";
575 m68k_symbolic_jump
= "jra %a0";
578 else if (TARGET_ID_SHARED_LIBRARY
)
579 /* All addresses must be loaded from the GOT. */
581 else if (TARGET_68020
|| TARGET_ISAB
)
585 m68k_symbolic_call
= "bsr.l %c0";
586 m68k_symbolic_jump
= "bra.l %c0";
591 m68k_symbolic_call
= "bsr.l %p0";
592 m68k_symbolic_jump
= "bra.l %p0";
594 m68k_symbolic_call
= "bsr %p0";
595 m68k_symbolic_jump
= "bra %p0";
598 /* Turn off function cse if we are doing PIC. We always want
599 function call to be done as `bsr foo@PLTPC'. */
600 /* ??? It's traditional to do this for -mpcrel too, but it isn't
601 clear how intentional that is. */
602 flag_no_function_cse
= 1;
605 SUBTARGET_OVERRIDE_OPTIONS
;
608 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
609 given argument and NAME is the argument passed to -mcpu. Return NULL
610 if -mcpu was not passed. */
613 m68k_cpp_cpu_ident (const char *prefix
)
617 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
620 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
621 given argument and NAME is the name of the representative device for
622 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
625 m68k_cpp_cpu_family (const char *prefix
)
629 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
632 /* Return nonzero if FUNC is an interrupt function as specified by the
633 "interrupt_handler" attribute. */
635 m68k_interrupt_function_p (tree func
)
639 if (TREE_CODE (func
) != FUNCTION_DECL
)
642 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
643 return (a
!= NULL_TREE
);
646 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
647 struct attribute_spec.handler. */
649 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
650 tree args ATTRIBUTE_UNUSED
,
651 int flags ATTRIBUTE_UNUSED
,
654 if (TREE_CODE (*node
) != FUNCTION_DECL
)
656 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
657 IDENTIFIER_POINTER (name
));
658 *no_add_attrs
= true;
665 m68k_compute_frame_layout (void)
669 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
671 /* Only compute the frame once per function.
672 Don't cache information until reload has been completed. */
673 if (current_frame
.funcdef_no
== current_function_funcdef_no
677 current_frame
.size
= (get_frame_size () + 3) & -4;
680 for (regno
= 0; regno
< 16; regno
++)
681 if (m68k_save_reg (regno
, interrupt_handler
))
683 mask
|= 1 << (regno
- D0_REG
);
686 current_frame
.offset
= saved
* 4;
687 current_frame
.reg_no
= saved
;
688 current_frame
.reg_mask
= mask
;
690 current_frame
.foffset
= 0;
692 if (TARGET_HARD_FLOAT
)
694 for (regno
= 16; regno
< 24; regno
++)
695 if (m68k_save_reg (regno
, interrupt_handler
))
697 mask
|= 1 << (regno
- FP0_REG
);
700 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
701 current_frame
.offset
+= current_frame
.foffset
;
703 current_frame
.fpu_no
= saved
;
704 current_frame
.fpu_mask
= mask
;
706 /* Remember what function this frame refers to. */
707 current_frame
.funcdef_no
= current_function_funcdef_no
;
711 m68k_initial_elimination_offset (int from
, int to
)
714 /* The arg pointer points 8 bytes before the start of the arguments,
715 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
716 frame pointer in most frames. */
717 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
718 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
719 return argptr_offset
;
721 m68k_compute_frame_layout ();
723 gcc_assert (to
== STACK_POINTER_REGNUM
);
726 case ARG_POINTER_REGNUM
:
727 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
728 case FRAME_POINTER_REGNUM
:
729 return current_frame
.offset
+ current_frame
.size
;
735 /* Refer to the array `regs_ever_live' to determine which registers
736 to save; `regs_ever_live[I]' is nonzero if register number I
737 is ever used in the function. This function is responsible for
738 knowing which registers should not be saved even if used.
739 Return true if we need to save REGNO. */
742 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
744 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
746 if (current_function_uses_pic_offset_table
)
748 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
752 if (current_function_calls_eh_return
)
757 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
758 if (test
== INVALID_REGNUM
)
765 /* Fixed regs we never touch. */
766 if (fixed_regs
[regno
])
769 /* The frame pointer (if it is such) is handled specially. */
770 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
773 /* Interrupt handlers must also save call_used_regs
774 if they are live or when calling nested functions. */
775 if (interrupt_handler
)
777 if (regs_ever_live
[regno
])
780 if (!current_function_is_leaf
&& call_used_regs
[regno
])
784 /* Never need to save registers that aren't touched. */
785 if (!regs_ever_live
[regno
])
788 /* Otherwise save everything that isn't call-clobbered. */
789 return !call_used_regs
[regno
];
792 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
793 the lowest memory address. COUNT is the number of registers to be
794 moved, with register REGNO + I being moved if bit I of MASK is set.
795 STORE_P specifies the direction of the move and ADJUST_STACK_P says
796 whether or not this is pre-decrement (if STORE_P) or post-increment
797 (if !STORE_P) operation. */
800 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
801 unsigned int count
, unsigned int regno
,
802 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
805 rtx body
, addr
, src
, operands
[2];
806 enum machine_mode mode
;
808 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
809 mode
= reg_raw_mode
[regno
];
814 src
= plus_constant (base
, (count
815 * GET_MODE_SIZE (mode
)
816 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
817 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
820 for (; mask
!= 0; mask
>>= 1, regno
++)
823 addr
= plus_constant (base
, offset
);
824 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
825 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
826 XVECEXP (body
, 0, i
++)
827 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
828 offset
+= GET_MODE_SIZE (mode
);
830 gcc_assert (i
== XVECLEN (body
, 0));
832 return emit_insn (body
);
835 /* Make INSN a frame-related instruction. */
838 m68k_set_frame_related (rtx insn
)
843 RTX_FRAME_RELATED_P (insn
) = 1;
844 body
= PATTERN (insn
);
845 if (GET_CODE (body
) == PARALLEL
)
846 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
847 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
850 /* Emit RTL for the "prologue" define_expand. */
853 m68k_expand_prologue (void)
855 HOST_WIDE_INT fsize_with_regs
;
856 rtx limit
, src
, dest
, insn
;
858 m68k_compute_frame_layout ();
860 /* If the stack limit is a symbol, we can check it here,
861 before actually allocating the space. */
862 if (current_function_limit_stack
863 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
865 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
866 if (!LEGITIMATE_CONSTANT_P (limit
))
868 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
869 limit
= gen_rtx_REG (Pmode
, D0_REG
);
871 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
872 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
873 cc0_rtx
, const0_rtx
),
877 fsize_with_regs
= current_frame
.size
;
880 /* ColdFire's move multiple instructions do not allow pre-decrement
881 addressing. Add the size of movem saves to the initial stack
882 allocation instead. */
883 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
884 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
885 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
886 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
889 if (frame_pointer_needed
)
891 if (fsize_with_regs
== 0 && TUNE_68040
)
893 /* On the 68040, two separate moves are faster than link.w 0. */
894 dest
= gen_frame_mem (Pmode
,
895 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
896 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
897 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
900 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
901 m68k_set_frame_related
902 (emit_insn (gen_link (frame_pointer_rtx
,
903 GEN_INT (-4 - fsize_with_regs
))));
906 m68k_set_frame_related
907 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
908 m68k_set_frame_related
909 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
911 GEN_INT (-fsize_with_regs
))));
914 else if (fsize_with_regs
!= 0)
915 m68k_set_frame_related
916 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
918 GEN_INT (-fsize_with_regs
))));
920 if (current_frame
.fpu_mask
)
922 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
924 m68k_set_frame_related
925 (m68k_emit_movem (stack_pointer_rtx
,
926 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
927 current_frame
.fpu_no
, FP0_REG
,
928 current_frame
.fpu_mask
, true, true));
933 /* If we're using moveml to save the integer registers,
934 the stack pointer will point to the bottom of the moveml
935 save area. Find the stack offset of the first FP register. */
936 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
939 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
940 m68k_set_frame_related
941 (m68k_emit_movem (stack_pointer_rtx
, offset
,
942 current_frame
.fpu_no
, FP0_REG
,
943 current_frame
.fpu_mask
, true, false));
947 /* If the stack limit is not a symbol, check it here.
948 This has the disadvantage that it may be too late... */
949 if (current_function_limit_stack
)
951 if (REG_P (stack_limit_rtx
))
953 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
954 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
955 cc0_rtx
, const0_rtx
),
958 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
959 warning (0, "stack limit expression is not supported");
962 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
964 /* Store each register separately in the same order moveml does. */
967 for (i
= 16; i
-- > 0; )
968 if (current_frame
.reg_mask
& (1 << i
))
970 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
971 dest
= gen_frame_mem (SImode
,
972 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
973 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
979 /* The required register save space has already been allocated.
980 The first register should be stored at (%sp). */
981 m68k_set_frame_related
982 (m68k_emit_movem (stack_pointer_rtx
, 0,
983 current_frame
.reg_no
, D0_REG
,
984 current_frame
.reg_mask
, true, false));
986 m68k_set_frame_related
987 (m68k_emit_movem (stack_pointer_rtx
,
988 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
989 current_frame
.reg_no
, D0_REG
,
990 current_frame
.reg_mask
, true, true));
995 && (current_function_uses_pic_offset_table
996 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
998 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
999 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
1005 /* Return true if a simple (return) instruction is sufficient for this
1006 instruction (i.e. if no epilogue is needed). */
1009 m68k_use_return_insn (void)
1011 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1014 m68k_compute_frame_layout ();
1015 return current_frame
.offset
== 0;
1018 /* Emit RTL for the "epilogue" define_expand.
1020 The function epilogue should not depend on the current stack pointer!
1021 It should use the frame pointer only, if there is a frame pointer.
1022 This is mandatory because of alloca; we also take advantage of it to
1023 omit stack adjustments before returning. */
1026 m68k_expand_epilogue (void)
1028 HOST_WIDE_INT fsize
, fsize_with_regs
;
1029 bool big
, restore_from_sp
;
1031 m68k_compute_frame_layout ();
1033 fsize
= current_frame
.size
;
1035 restore_from_sp
= false;
1037 /* FIXME : current_function_is_leaf below is too strong.
1038 What we really need to know there is if there could be pending
1039 stack adjustment needed at that point. */
1040 restore_from_sp
= (!frame_pointer_needed
1041 || (!current_function_calls_alloca
1042 && current_function_is_leaf
));
1044 /* fsize_with_regs is the size we need to adjust the sp when
1045 popping the frame. */
1046 fsize_with_regs
= fsize
;
1047 if (TARGET_COLDFIRE
&& restore_from_sp
)
1049 /* ColdFire's move multiple instructions do not allow post-increment
1050 addressing. Add the size of movem loads to the final deallocation
1052 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1053 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1054 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1055 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1058 if (current_frame
.offset
+ fsize
>= 0x8000
1060 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1063 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1064 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1066 /* ColdFire's move multiple instructions do not support the
1067 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1068 stack-based restore. */
1069 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1070 GEN_INT (-(current_frame
.offset
+ fsize
)));
1071 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1072 gen_rtx_REG (Pmode
, A1_REG
),
1073 frame_pointer_rtx
));
1074 restore_from_sp
= true;
1078 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1084 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1086 /* Restore each register separately in the same order moveml does. */
1088 HOST_WIDE_INT offset
;
1090 offset
= current_frame
.offset
+ fsize
;
1091 for (i
= 0; i
< 16; i
++)
1092 if (current_frame
.reg_mask
& (1 << i
))
1098 /* Generate the address -OFFSET(%fp,%a1.l). */
1099 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1100 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1101 addr
= plus_constant (addr
, -offset
);
1103 else if (restore_from_sp
)
1104 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1106 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1107 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1108 gen_frame_mem (SImode
, addr
));
1109 offset
-= GET_MODE_SIZE (SImode
);
1112 else if (current_frame
.reg_mask
)
1115 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1116 gen_rtx_REG (Pmode
, A1_REG
),
1118 -(current_frame
.offset
+ fsize
),
1119 current_frame
.reg_no
, D0_REG
,
1120 current_frame
.reg_mask
, false, false);
1121 else if (restore_from_sp
)
1122 m68k_emit_movem (stack_pointer_rtx
, 0,
1123 current_frame
.reg_no
, D0_REG
,
1124 current_frame
.reg_mask
, false,
1127 m68k_emit_movem (frame_pointer_rtx
,
1128 -(current_frame
.offset
+ fsize
),
1129 current_frame
.reg_no
, D0_REG
,
1130 current_frame
.reg_mask
, false, false);
1133 if (current_frame
.fpu_no
> 0)
1136 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1137 gen_rtx_REG (Pmode
, A1_REG
),
1139 -(current_frame
.foffset
+ fsize
),
1140 current_frame
.fpu_no
, FP0_REG
,
1141 current_frame
.fpu_mask
, false, false);
1142 else if (restore_from_sp
)
1144 if (TARGET_COLDFIRE
)
1148 /* If we used moveml to restore the integer registers, the
1149 stack pointer will still point to the bottom of the moveml
1150 save area. Find the stack offset of the first FP
1152 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1155 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1156 m68k_emit_movem (stack_pointer_rtx
, offset
,
1157 current_frame
.fpu_no
, FP0_REG
,
1158 current_frame
.fpu_mask
, false, false);
1161 m68k_emit_movem (stack_pointer_rtx
, 0,
1162 current_frame
.fpu_no
, FP0_REG
,
1163 current_frame
.fpu_mask
, false, true);
1166 m68k_emit_movem (frame_pointer_rtx
,
1167 -(current_frame
.foffset
+ fsize
),
1168 current_frame
.fpu_no
, FP0_REG
,
1169 current_frame
.fpu_mask
, false, false);
1172 if (frame_pointer_needed
)
1173 emit_insn (gen_unlink (frame_pointer_rtx
));
1174 else if (fsize_with_regs
)
1175 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1177 GEN_INT (fsize_with_regs
)));
1179 if (current_function_calls_eh_return
)
1180 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1182 EH_RETURN_STACKADJ_RTX
));
1184 emit_insn (gen_rtx_RETURN (VOIDmode
));
1187 /* Return true if X is a valid comparison operator for the dbcc
1190 Note it rejects floating point comparison operators.
1191 (In the future we could use Fdbcc).
1193 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1196 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1198 switch (GET_CODE (x
))
1200 case EQ
: case NE
: case GTU
: case LTU
:
1204 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1206 case GT
: case LT
: case GE
: case LE
:
1207 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1213 /* Return nonzero if flags are currently in the 68881 flag register. */
1215 flags_in_68881 (void)
1217 /* We could add support for these in the future */
1218 return cc_status
.flags
& CC_IN_68881
;
1221 /* Convert X to a legitimate function call memory reference and return the
1225 m68k_legitimize_call_address (rtx x
)
1227 gcc_assert (MEM_P (x
));
1228 if (call_operand (XEXP (x
, 0), VOIDmode
))
1230 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1233 /* Output a dbCC; jCC sequence. Note we do not handle the
1234 floating point version of this sequence (Fdbcc). We also
1235 do not handle alternative conditions when CC_NO_OVERFLOW is
1236 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1237 kick those out before we get here. */
1240 output_dbcc_and_branch (rtx
*operands
)
1242 switch (GET_CODE (operands
[3]))
1245 output_asm_insn (MOTOROLA
1246 ? "dbeq %0,%l1\n\tjbeq %l2"
1247 : "dbeq %0,%l1\n\tjeq %l2",
1252 output_asm_insn (MOTOROLA
1253 ? "dbne %0,%l1\n\tjbne %l2"
1254 : "dbne %0,%l1\n\tjne %l2",
1259 output_asm_insn (MOTOROLA
1260 ? "dbgt %0,%l1\n\tjbgt %l2"
1261 : "dbgt %0,%l1\n\tjgt %l2",
1266 output_asm_insn (MOTOROLA
1267 ? "dbhi %0,%l1\n\tjbhi %l2"
1268 : "dbhi %0,%l1\n\tjhi %l2",
1273 output_asm_insn (MOTOROLA
1274 ? "dblt %0,%l1\n\tjblt %l2"
1275 : "dblt %0,%l1\n\tjlt %l2",
1280 output_asm_insn (MOTOROLA
1281 ? "dbcs %0,%l1\n\tjbcs %l2"
1282 : "dbcs %0,%l1\n\tjcs %l2",
1287 output_asm_insn (MOTOROLA
1288 ? "dbge %0,%l1\n\tjbge %l2"
1289 : "dbge %0,%l1\n\tjge %l2",
1294 output_asm_insn (MOTOROLA
1295 ? "dbcc %0,%l1\n\tjbcc %l2"
1296 : "dbcc %0,%l1\n\tjcc %l2",
1301 output_asm_insn (MOTOROLA
1302 ? "dble %0,%l1\n\tjble %l2"
1303 : "dble %0,%l1\n\tjle %l2",
1308 output_asm_insn (MOTOROLA
1309 ? "dbls %0,%l1\n\tjbls %l2"
1310 : "dbls %0,%l1\n\tjls %l2",
1318 /* If the decrement is to be done in SImode, then we have
1319 to compensate for the fact that dbcc decrements in HImode. */
1320 switch (GET_MODE (operands
[0]))
1323 output_asm_insn (MOTOROLA
1324 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1325 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1338 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1341 enum rtx_code op_code
= GET_CODE (op
);
1343 /* This does not produce a useful cc. */
1346 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1347 below. Swap the operands and change the op if these requirements
1348 are not fulfilled. */
1349 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1353 operand1
= operand2
;
1355 op_code
= swap_condition (op_code
);
1357 loperands
[0] = operand1
;
1358 if (GET_CODE (operand1
) == REG
)
1359 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1361 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1362 if (operand2
!= const0_rtx
)
1364 loperands
[2] = operand2
;
1365 if (GET_CODE (operand2
) == REG
)
1366 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1368 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1370 loperands
[4] = gen_label_rtx ();
1371 if (operand2
!= const0_rtx
)
1373 output_asm_insn (MOTOROLA
1374 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1375 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1380 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1381 output_asm_insn ("tst%.l %0", loperands
);
1383 output_asm_insn ("cmp%.w #0,%0", loperands
);
1385 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1387 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1388 output_asm_insn ("tst%.l %1", loperands
);
1390 output_asm_insn ("cmp%.w #0,%1", loperands
);
1393 loperands
[5] = dest
;
1398 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1399 CODE_LABEL_NUMBER (loperands
[4]));
1400 output_asm_insn ("seq %5", loperands
);
1404 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1405 CODE_LABEL_NUMBER (loperands
[4]));
1406 output_asm_insn ("sne %5", loperands
);
1410 loperands
[6] = gen_label_rtx ();
1411 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1413 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1414 CODE_LABEL_NUMBER (loperands
[4]));
1415 output_asm_insn ("sgt %5", loperands
);
1416 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1417 CODE_LABEL_NUMBER (loperands
[6]));
1421 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1422 CODE_LABEL_NUMBER (loperands
[4]));
1423 output_asm_insn ("shi %5", loperands
);
1427 loperands
[6] = gen_label_rtx ();
1428 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1430 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1431 CODE_LABEL_NUMBER (loperands
[4]));
1432 output_asm_insn ("slt %5", loperands
);
1433 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1434 CODE_LABEL_NUMBER (loperands
[6]));
1438 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1439 CODE_LABEL_NUMBER (loperands
[4]));
1440 output_asm_insn ("scs %5", loperands
);
1444 loperands
[6] = gen_label_rtx ();
1445 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1447 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1448 CODE_LABEL_NUMBER (loperands
[4]));
1449 output_asm_insn ("sge %5", loperands
);
1450 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1451 CODE_LABEL_NUMBER (loperands
[6]));
1455 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1456 CODE_LABEL_NUMBER (loperands
[4]));
1457 output_asm_insn ("scc %5", loperands
);
1461 loperands
[6] = gen_label_rtx ();
1462 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1464 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1465 CODE_LABEL_NUMBER (loperands
[4]));
1466 output_asm_insn ("sle %5", loperands
);
1467 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1468 CODE_LABEL_NUMBER (loperands
[6]));
1472 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1473 CODE_LABEL_NUMBER (loperands
[4]));
1474 output_asm_insn ("sls %5", loperands
);
1484 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1486 operands
[0] = countop
;
1487 operands
[1] = dataop
;
1489 if (GET_CODE (countop
) == CONST_INT
)
1491 register int count
= INTVAL (countop
);
1492 /* If COUNT is bigger than size of storage unit in use,
1493 advance to the containing unit of same size. */
1494 if (count
> signpos
)
1496 int offset
= (count
& ~signpos
) / 8;
1497 count
= count
& signpos
;
1498 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1500 if (count
== signpos
)
1501 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1503 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1505 /* These three statements used to use next_insns_test_no...
1506 but it appears that this should do the same job. */
1508 && next_insn_tests_no_inequality (insn
))
1511 && next_insn_tests_no_inequality (insn
))
1514 && next_insn_tests_no_inequality (insn
))
1517 cc_status
.flags
= CC_NOT_NEGATIVE
;
1519 return "btst %0,%1";
1522 /* Return true if X is a legitimate base register. STRICT_P says
1523 whether we need strict checking. */
1526 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1528 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1529 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1534 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1535 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1538 /* Return true if X is a legitimate index register. STRICT_P says
1539 whether we need strict checking. */
1542 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1544 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1549 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1550 : !FP_REGNO_P (REGNO (x
))));
1553 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1554 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1555 ADDRESS if so. STRICT_P says whether we need strict checking. */
1558 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1562 /* Check for a scale factor. */
1564 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1565 && GET_CODE (x
) == MULT
1566 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1567 && (INTVAL (XEXP (x
, 1)) == 2
1568 || INTVAL (XEXP (x
, 1)) == 4
1569 || (INTVAL (XEXP (x
, 1)) == 8
1570 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1572 scale
= INTVAL (XEXP (x
, 1));
1576 /* Check for a word extension. */
1577 if (!TARGET_COLDFIRE
1578 && GET_CODE (x
) == SIGN_EXTEND
1579 && GET_MODE (XEXP (x
, 0)) == HImode
)
1582 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1584 address
->scale
= scale
;
1592 /* Return true if X is an illegitimate symbolic constant. */
1595 m68k_illegitimate_symbolic_constant_p (rtx x
)
1599 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1601 split_const (x
, &base
, &offset
);
1602 if (GET_CODE (base
) == SYMBOL_REF
1603 && !offset_within_block_p (base
, INTVAL (offset
)))
1609 /* Return true if X is a legitimate constant address that can reach
1610 bytes in the range [X, X + REACH). STRICT_P says whether we need
1614 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1618 if (!CONSTANT_ADDRESS_P (x
))
1622 && !(strict_p
&& TARGET_PCREL
)
1623 && symbolic_operand (x
, VOIDmode
))
1626 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1628 split_const (x
, &base
, &offset
);
1629 if (GET_CODE (base
) == SYMBOL_REF
1630 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1637 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1638 labels will become jump tables. */
1641 m68k_jump_table_ref_p (rtx x
)
1643 if (GET_CODE (x
) != LABEL_REF
)
1647 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1650 x
= next_nonnote_insn (x
);
1651 return x
&& JUMP_TABLE_DATA_P (x
);
1654 /* Return true if X is a legitimate address for values of mode MODE.
1655 STRICT_P says whether strict checking is needed. If the address
1656 is valid, describe its components in *ADDRESS. */
1659 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1660 bool strict_p
, struct m68k_address
*address
)
1664 memset (address
, 0, sizeof (*address
));
1666 if (mode
== BLKmode
)
1669 reach
= GET_MODE_SIZE (mode
);
1671 /* Check for (An) (mode 2). */
1672 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1678 /* Check for -(An) and (An)+ (modes 3 and 4). */
1679 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1680 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1682 address
->code
= GET_CODE (x
);
1683 address
->base
= XEXP (x
, 0);
1687 /* Check for (d16,An) (mode 5). */
1688 if (GET_CODE (x
) == PLUS
1689 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1690 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1691 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1693 address
->base
= XEXP (x
, 0);
1694 address
->offset
= XEXP (x
, 1);
1698 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1699 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1702 && GET_CODE (x
) == PLUS
1703 && XEXP (x
, 0) == pic_offset_table_rtx
1704 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1705 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1707 address
->base
= XEXP (x
, 0);
1708 address
->offset
= XEXP (x
, 1);
1712 /* The ColdFire FPU only accepts addressing modes 2-5. */
1713 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1716 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1717 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1718 All these modes are variations of mode 7. */
1719 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1721 address
->offset
= x
;
1725 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1728 ??? do_tablejump creates these addresses before placing the target
1729 label, so we have to assume that unplaced labels are jump table
1730 references. It seems unlikely that we would ever generate indexed
1731 accesses to unplaced labels in other cases. */
1732 if (GET_CODE (x
) == PLUS
1733 && m68k_jump_table_ref_p (XEXP (x
, 1))
1734 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1736 address
->offset
= XEXP (x
, 1);
1740 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1741 (bd,An,Xn.SIZE*SCALE) addresses. */
1745 /* Check for a nonzero base displacement. */
1746 if (GET_CODE (x
) == PLUS
1747 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1749 address
->offset
= XEXP (x
, 1);
1753 /* Check for a suppressed index register. */
1754 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1760 /* Check for a suppressed base register. Do not allow this case
1761 for non-symbolic offsets as it effectively gives gcc freedom
1762 to treat data registers as base registers, which can generate
1765 && symbolic_operand (address
->offset
, VOIDmode
)
1766 && m68k_decompose_index (x
, strict_p
, address
))
1771 /* Check for a nonzero base displacement. */
1772 if (GET_CODE (x
) == PLUS
1773 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1774 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1776 address
->offset
= XEXP (x
, 1);
1781 /* We now expect the sum of a base and an index. */
1782 if (GET_CODE (x
) == PLUS
)
1784 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1785 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1787 address
->base
= XEXP (x
, 0);
1791 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1792 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1794 address
->base
= XEXP (x
, 1);
1801 /* Return true if X is a legitimate address for values of mode MODE.
1802 STRICT_P says whether strict checking is needed. */
1805 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1807 struct m68k_address address
;
1809 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1812 /* Return true if X is a memory, describing its address in ADDRESS if so.
1813 Apply strict checking if called during or after reload. */
1816 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1819 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1820 reload_in_progress
|| reload_completed
,
1824 /* Return true if X matches the 'Q' constraint. It must be a memory
1825 with a base address and no constant offset or index. */
1828 m68k_matches_q_p (rtx x
)
1830 struct m68k_address address
;
1832 return (m68k_legitimate_mem_p (x
, &address
)
1833 && address
.code
== UNKNOWN
1839 /* Return true if X matches the 'U' constraint. It must be a base address
1840 with a constant offset and no index. */
1843 m68k_matches_u_p (rtx x
)
1845 struct m68k_address address
;
1847 return (m68k_legitimate_mem_p (x
, &address
)
1848 && address
.code
== UNKNOWN
1854 /* Legitimize PIC addresses. If the address is already
1855 position-independent, we return ORIG. Newly generated
1856 position-independent addresses go to REG. If we need more
1857 than one register, we lose.
1859 An address is legitimized by making an indirect reference
1860 through the Global Offset Table with the name of the symbol
1863 The assembler and linker are responsible for placing the
1864 address of the symbol in the GOT. The function prologue
1865 is responsible for initializing a5 to the starting address
1868 The assembler is also responsible for translating a symbol name
1869 into a constant displacement from the start of the GOT.
1871 A quick example may make things a little clearer:
1873 When not generating PIC code to store the value 12345 into _foo
1874 we would generate the following code:
1878 When generating PIC two transformations are made. First, the compiler
1879 loads the address of foo into a register. So the first transformation makes:
1884 The code in movsi will intercept the lea instruction and call this
1885 routine which will transform the instructions into:
1887 movel a5@(_foo:w), a0
1891 That (in a nutshell) is how *all* symbol and label references are
1895 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1900 /* First handle a simple SYMBOL_REF or LABEL_REF */
1901 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1905 pic_ref
= gen_rtx_MEM (Pmode
,
1906 gen_rtx_PLUS (Pmode
,
1907 pic_offset_table_rtx
, orig
));
1908 current_function_uses_pic_offset_table
= 1;
1909 MEM_READONLY_P (pic_ref
) = 1;
1910 emit_move_insn (reg
, pic_ref
);
1913 else if (GET_CODE (orig
) == CONST
)
1917 /* Make sure this has not already been legitimized. */
1918 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1919 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1924 /* legitimize both operands of the PLUS */
1925 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1927 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1928 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1929 base
== reg
? 0 : reg
);
1931 if (GET_CODE (orig
) == CONST_INT
)
1932 return plus_constant (base
, INTVAL (orig
));
1933 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1934 /* Likewise, should we set special REG_NOTEs here? */
1940 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1942 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1944 /* Return the type of move that should be used for integer I. */
1947 const_method (HOST_WIDE_INT i
)
1954 /* The ColdFire doesn't have byte or word operations. */
1955 /* FIXME: This may not be useful for the m68060 either. */
1956 if (!TARGET_COLDFIRE
)
1958 /* if -256 < N < 256 but N is not in range for a moveq
1959 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1960 if (USE_MOVQ (i
^ 0xff))
1962 /* Likewise, try with not.w */
1963 if (USE_MOVQ (i
^ 0xffff))
1965 /* This is the only value where neg.w is useful */
1970 /* Try also with swap. */
1972 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1977 /* Try using MVZ/MVS with an immediate value to load constants. */
1978 if (i
>= 0 && i
<= 65535)
1980 if (i
>= -32768 && i
<= 32767)
1984 /* Otherwise, use move.l */
1988 /* Return the cost of moving constant I into a data register. */
1991 const_int_cost (HOST_WIDE_INT i
)
1993 switch (const_method (i
))
1996 /* Constants between -128 and 127 are cheap due to moveq. */
2004 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2014 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2019 /* Constant zero is super cheap due to clr instruction. */
2020 if (x
== const0_rtx
)
2023 *total
= const_int_cost (INTVAL (x
));
2033 /* Make 0.0 cheaper than other floating constants to
2034 encourage creating tstsf and tstdf insns. */
2035 if (outer_code
== COMPARE
2036 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2042 /* These are vaguely right for a 68020. */
2043 /* The costs for long multiply have been adjusted to work properly
2044 in synth_mult on the 68020, relative to an average of the time
2045 for add and the time for shift, taking away a little more because
2046 sometimes move insns are needed. */
2047 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2053 : TARGET_COLDFIRE ? 3 : 13)
2058 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2059 : TARGET_COLDFIRE ? 2 : 8)
2062 (TARGET_CF_HWDIV ? 11 \
2063 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2066 /* An lea costs about three times as much as a simple add. */
2067 if (GET_MODE (x
) == SImode
2068 && GET_CODE (XEXP (x
, 1)) == REG
2069 && GET_CODE (XEXP (x
, 0)) == MULT
2070 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2071 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2072 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2073 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2074 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2076 /* lea an@(dx:l:i),am */
2077 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2087 *total
= COSTS_N_INSNS(1);
2092 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2094 if (INTVAL (XEXP (x
, 1)) < 16)
2095 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2097 /* We're using clrw + swap for these cases. */
2098 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2101 *total
= COSTS_N_INSNS (10); /* Worst case. */
2104 /* A shift by a big integer takes an extra instruction. */
2105 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2106 && (INTVAL (XEXP (x
, 1)) == 16))
2108 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2111 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2112 && !(INTVAL (XEXP (x
, 1)) > 0
2113 && INTVAL (XEXP (x
, 1)) <= 8))
2115 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2121 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2122 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2123 && GET_MODE (x
) == SImode
)
2124 *total
= COSTS_N_INSNS (MULW_COST
);
2125 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2126 *total
= COSTS_N_INSNS (MULW_COST
);
2128 *total
= COSTS_N_INSNS (MULL_COST
);
2135 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2136 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2137 else if (TARGET_CF_HWDIV
)
2138 *total
= COSTS_N_INSNS (18);
2140 *total
= COSTS_N_INSNS (43); /* div.l */
2148 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2152 output_move_const_into_data_reg (rtx
*operands
)
2156 i
= INTVAL (operands
[1]);
2157 switch (const_method (i
))
2160 return "mvzw %1,%0";
2162 return "mvsw %1,%0";
2164 return "moveq %1,%0";
2167 operands
[1] = GEN_INT (i
^ 0xff);
2168 return "moveq %1,%0\n\tnot%.b %0";
2171 operands
[1] = GEN_INT (i
^ 0xffff);
2172 return "moveq %1,%0\n\tnot%.w %0";
2175 return "moveq #-128,%0\n\tneg%.w %0";
2180 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2181 return "moveq %1,%0\n\tswap %0";
2184 return "move%.l %1,%0";
2190 /* Return true if I can be handled by ISA B's mov3q instruction. */
2193 valid_mov3q_const (HOST_WIDE_INT i
)
2195 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2198 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2199 I is the value of OPERANDS[1]. */
2202 output_move_simode_const (rtx
*operands
)
2208 src
= INTVAL (operands
[1]);
2210 && (DATA_REG_P (dest
) || MEM_P (dest
))
2211 /* clr insns on 68000 read before writing. */
2212 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2213 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2215 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2216 return "mov3q%.l %1,%0";
2217 else if (src
== 0 && ADDRESS_REG_P (dest
))
2218 return "sub%.l %0,%0";
2219 else if (DATA_REG_P (dest
))
2220 return output_move_const_into_data_reg (operands
);
2221 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2223 if (valid_mov3q_const (src
))
2224 return "mov3q%.l %1,%0";
2225 return "move%.w %1,%0";
2227 else if (MEM_P (dest
)
2228 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2229 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2230 && IN_RANGE (src
, -0x8000, 0x7fff))
2232 if (valid_mov3q_const (src
))
2233 return "mov3q%.l %1,%-";
2236 return "move%.l %1,%0";
2240 output_move_simode (rtx
*operands
)
2242 if (GET_CODE (operands
[1]) == CONST_INT
)
2243 return output_move_simode_const (operands
);
2244 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2245 || GET_CODE (operands
[1]) == CONST
)
2246 && push_operand (operands
[0], SImode
))
2248 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2249 || GET_CODE (operands
[1]) == CONST
)
2250 && ADDRESS_REG_P (operands
[0]))
2251 return "lea %a1,%0";
2252 return "move%.l %1,%0";
2256 output_move_himode (rtx
*operands
)
2258 if (GET_CODE (operands
[1]) == CONST_INT
)
2260 if (operands
[1] == const0_rtx
2261 && (DATA_REG_P (operands
[0])
2262 || GET_CODE (operands
[0]) == MEM
)
2263 /* clr insns on 68000 read before writing. */
2264 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2265 || !(GET_CODE (operands
[0]) == MEM
2266 && MEM_VOLATILE_P (operands
[0]))))
2268 else if (operands
[1] == const0_rtx
2269 && ADDRESS_REG_P (operands
[0]))
2270 return "sub%.l %0,%0";
2271 else if (DATA_REG_P (operands
[0])
2272 && INTVAL (operands
[1]) < 128
2273 && INTVAL (operands
[1]) >= -128)
2274 return "moveq %1,%0";
2275 else if (INTVAL (operands
[1]) < 0x8000
2276 && INTVAL (operands
[1]) >= -0x8000)
2277 return "move%.w %1,%0";
2279 else if (CONSTANT_P (operands
[1]))
2280 return "move%.l %1,%0";
2281 /* Recognize the insn before a tablejump, one that refers
2282 to a table of offsets. Such an insn will need to refer
2283 to a label on the insn. So output one. Use the label-number
2284 of the table of offsets to generate this label. This code,
2285 and similar code below, assumes that there will be at most one
2286 reference to each table. */
2287 if (GET_CODE (operands
[1]) == MEM
2288 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2289 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2290 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2292 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2294 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2295 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2297 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2298 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2300 return "move%.w %1,%0";
2304 output_move_qimode (rtx
*operands
)
2306 /* 68k family always modifies the stack pointer by at least 2, even for
2307 byte pushes. The 5200 (ColdFire) does not do this. */
2309 /* This case is generated by pushqi1 pattern now. */
2310 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2311 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2312 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2313 && ! ADDRESS_REG_P (operands
[1])
2314 && ! TARGET_COLDFIRE
));
2316 /* clr and st insns on 68000 read before writing. */
2317 if (!ADDRESS_REG_P (operands
[0])
2318 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2319 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2321 if (operands
[1] == const0_rtx
)
2323 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2324 && GET_CODE (operands
[1]) == CONST_INT
2325 && (INTVAL (operands
[1]) & 255) == 255)
2331 if (GET_CODE (operands
[1]) == CONST_INT
2332 && DATA_REG_P (operands
[0])
2333 && INTVAL (operands
[1]) < 128
2334 && INTVAL (operands
[1]) >= -128)
2335 return "moveq %1,%0";
2336 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2337 return "sub%.l %0,%0";
2338 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2339 return "move%.l %1,%0";
2340 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2341 from address registers. */
2342 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2343 return "move%.w %1,%0";
2344 return "move%.b %1,%0";
2348 output_move_stricthi (rtx
*operands
)
2350 if (operands
[1] == const0_rtx
2351 /* clr insns on 68000 read before writing. */
2352 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2353 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2355 return "move%.w %1,%0";
2359 output_move_strictqi (rtx
*operands
)
2361 if (operands
[1] == const0_rtx
2362 /* clr insns on 68000 read before writing. */
2363 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2364 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2366 return "move%.b %1,%0";
2369 /* Return the best assembler insn template
2370 for moving operands[1] into operands[0] as a fullword. */
2373 singlemove_string (rtx
*operands
)
2375 if (GET_CODE (operands
[1]) == CONST_INT
)
2376 return output_move_simode_const (operands
);
2377 return "move%.l %1,%0";
2381 /* Output assembler code to perform a doubleword move insn
2382 with operands OPERANDS. */
2385 output_move_double (rtx
*operands
)
2389 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2394 rtx addreg0
= 0, addreg1
= 0;
2395 int dest_overlapped_low
= 0;
2396 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2401 /* First classify both operands. */
2403 if (REG_P (operands
[0]))
2405 else if (offsettable_memref_p (operands
[0]))
2407 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2409 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2411 else if (GET_CODE (operands
[0]) == MEM
)
2416 if (REG_P (operands
[1]))
2418 else if (CONSTANT_P (operands
[1]))
2420 else if (offsettable_memref_p (operands
[1]))
2422 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2424 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2426 else if (GET_CODE (operands
[1]) == MEM
)
2431 /* Check for the cases that the operand constraints are not supposed
2432 to allow to happen. Generating code for these cases is
2434 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2436 /* If one operand is decrementing and one is incrementing
2437 decrement the former register explicitly
2438 and change that operand into ordinary indexing. */
2440 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2442 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2444 output_asm_insn ("sub%.l #12,%0", operands
);
2446 output_asm_insn ("subq%.l #8,%0", operands
);
2447 if (GET_MODE (operands
[1]) == XFmode
)
2448 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2449 else if (GET_MODE (operands
[0]) == DFmode
)
2450 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2452 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2455 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2457 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2459 output_asm_insn ("sub%.l #12,%1", operands
);
2461 output_asm_insn ("subq%.l #8,%1", operands
);
2462 if (GET_MODE (operands
[1]) == XFmode
)
2463 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2464 else if (GET_MODE (operands
[1]) == DFmode
)
2465 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2467 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2471 /* If an operand is an unoffsettable memory ref, find a register
2472 we can increment temporarily to make it refer to the second word. */
2474 if (optype0
== MEMOP
)
2475 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2477 if (optype1
== MEMOP
)
2478 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2480 /* Ok, we can do one word at a time.
2481 Normally we do the low-numbered word first,
2482 but if either operand is autodecrementing then we
2483 do the high-numbered word first.
2485 In either case, set up in LATEHALF the operands to use
2486 for the high-numbered word and in some cases alter the
2487 operands in OPERANDS to be suitable for the low-numbered word. */
2491 if (optype0
== REGOP
)
2493 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2494 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2496 else if (optype0
== OFFSOP
)
2498 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2499 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2503 middlehalf
[0] = operands
[0];
2504 latehalf
[0] = operands
[0];
2507 if (optype1
== REGOP
)
2509 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2510 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2512 else if (optype1
== OFFSOP
)
2514 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2515 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2517 else if (optype1
== CNSTOP
)
2519 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2524 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2525 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2526 operands
[1] = GEN_INT (l
[0]);
2527 middlehalf
[1] = GEN_INT (l
[1]);
2528 latehalf
[1] = GEN_INT (l
[2]);
2532 /* No non-CONST_DOUBLE constant should ever appear
2534 gcc_assert (!CONSTANT_P (operands
[1]));
2539 middlehalf
[1] = operands
[1];
2540 latehalf
[1] = operands
[1];
2544 /* size is not 12: */
2546 if (optype0
== REGOP
)
2547 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2548 else if (optype0
== OFFSOP
)
2549 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2551 latehalf
[0] = operands
[0];
2553 if (optype1
== REGOP
)
2554 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2555 else if (optype1
== OFFSOP
)
2556 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2557 else if (optype1
== CNSTOP
)
2558 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2560 latehalf
[1] = operands
[1];
2563 /* If insn is effectively movd N(sp),-(sp) then we will do the
2564 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2565 for the low word as well, to compensate for the first decrement of sp. */
2566 if (optype0
== PUSHOP
2567 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2568 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2569 operands
[1] = middlehalf
[1] = latehalf
[1];
2571 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2572 if the upper part of reg N does not appear in the MEM, arrange to
2573 emit the move late-half first. Otherwise, compute the MEM address
2574 into the upper part of N and use that as a pointer to the memory
2576 if (optype0
== REGOP
2577 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2579 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2581 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2582 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2584 /* If both halves of dest are used in the src memory address,
2585 compute the address into latehalf of dest.
2586 Note that this can't happen if the dest is two data regs. */
2588 xops
[0] = latehalf
[0];
2589 xops
[1] = XEXP (operands
[1], 0);
2590 output_asm_insn ("lea %a1,%0", xops
);
2591 if (GET_MODE (operands
[1]) == XFmode
)
2593 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2594 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2595 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2599 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2600 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2604 && reg_overlap_mentioned_p (middlehalf
[0],
2605 XEXP (operands
[1], 0)))
2607 /* Check for two regs used by both source and dest.
2608 Note that this can't happen if the dest is all data regs.
2609 It can happen if the dest is d6, d7, a0.
2610 But in that case, latehalf is an addr reg, so
2611 the code at compadr does ok. */
2613 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2614 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2617 /* JRV says this can't happen: */
2618 gcc_assert (!addreg0
&& !addreg1
);
2620 /* Only the middle reg conflicts; simply put it last. */
2621 output_asm_insn (singlemove_string (operands
), operands
);
2622 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2623 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2626 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2627 /* If the low half of dest is mentioned in the source memory
2628 address, the arrange to emit the move late half first. */
2629 dest_overlapped_low
= 1;
2632 /* If one or both operands autodecrementing,
2633 do the two words, high-numbered first. */
2635 /* Likewise, the first move would clobber the source of the second one,
2636 do them in the other order. This happens only for registers;
2637 such overlap can't happen in memory unless the user explicitly
2638 sets it up, and that is an undefined circumstance. */
2640 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2641 || (optype0
== REGOP
&& optype1
== REGOP
2642 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2643 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2644 || dest_overlapped_low
)
2646 /* Make any unoffsettable addresses point at high-numbered word. */
2650 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2652 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2657 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2659 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2663 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2665 /* Undo the adds we just did. */
2667 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2669 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2673 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2675 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2677 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2680 /* Do low-numbered word. */
2681 return singlemove_string (operands
);
2684 /* Normal case: do the two words, low-numbered first. */
2686 output_asm_insn (singlemove_string (operands
), operands
);
2688 /* Do the middle one of the three words for long double */
2692 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2694 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2696 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2699 /* Make any unoffsettable addresses point at high-numbered word. */
2701 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2703 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2706 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2708 /* Undo the adds we just did. */
2712 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2714 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2719 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2721 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2728 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2729 new rtx with the correct mode. */
2732 force_mode (enum machine_mode mode
, rtx orig
)
2734 if (mode
== GET_MODE (orig
))
2737 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2740 return gen_rtx_REG (mode
, REGNO (orig
));
2744 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2746 return reg_renumber
&& FP_REG_P (op
);
2749 /* Emit insns to move operands[1] into operands[0].
2751 Return 1 if we have written out everything that needs to be done to
2752 do the move. Otherwise, return 0 and the caller will emit the move
2755 Note SCRATCH_REG may not be in the proper mode depending on how it
2756 will be used. This routine is responsible for creating a new copy
2757 of SCRATCH_REG in the proper mode. */
2760 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2762 register rtx operand0
= operands
[0];
2763 register rtx operand1
= operands
[1];
2767 && reload_in_progress
&& GET_CODE (operand0
) == REG
2768 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2769 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2770 else if (scratch_reg
2771 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2772 && GET_CODE (SUBREG_REG (operand0
)) == REG
2773 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2775 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2776 the code which tracks sets/uses for delete_output_reload. */
2777 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2778 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2779 SUBREG_BYTE (operand0
));
2780 operand0
= alter_subreg (&temp
);
2784 && reload_in_progress
&& GET_CODE (operand1
) == REG
2785 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2786 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2787 else if (scratch_reg
2788 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2789 && GET_CODE (SUBREG_REG (operand1
)) == REG
2790 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2792 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2793 the code which tracks sets/uses for delete_output_reload. */
2794 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2795 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2796 SUBREG_BYTE (operand1
));
2797 operand1
= alter_subreg (&temp
);
2800 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2801 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2802 != XEXP (operand0
, 0)))
2803 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2804 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2805 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2806 != XEXP (operand1
, 0)))
2807 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2809 /* Handle secondary reloads for loads/stores of FP registers where
2810 the address is symbolic by using the scratch register */
2811 if (fp_reg_operand (operand0
, mode
)
2812 && ((GET_CODE (operand1
) == MEM
2813 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2814 || ((GET_CODE (operand1
) == SUBREG
2815 && GET_CODE (XEXP (operand1
, 0)) == MEM
2816 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2819 if (GET_CODE (operand1
) == SUBREG
)
2820 operand1
= XEXP (operand1
, 0);
2822 /* SCRATCH_REG will hold an address. We want
2823 it in SImode regardless of what mode it was originally given
2825 scratch_reg
= force_mode (SImode
, scratch_reg
);
2827 /* D might not fit in 14 bits either; for such cases load D into
2829 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2831 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2832 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2834 XEXP (XEXP (operand1
, 0), 0),
2838 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2839 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2840 gen_rtx_MEM (mode
, scratch_reg
)));
2843 else if (fp_reg_operand (operand1
, mode
)
2844 && ((GET_CODE (operand0
) == MEM
2845 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2846 || ((GET_CODE (operand0
) == SUBREG
)
2847 && GET_CODE (XEXP (operand0
, 0)) == MEM
2848 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2851 if (GET_CODE (operand0
) == SUBREG
)
2852 operand0
= XEXP (operand0
, 0);
2854 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2855 it in SIMODE regardless of what mode it was originally given
2857 scratch_reg
= force_mode (SImode
, scratch_reg
);
2859 /* D might not fit in 14 bits either; for such cases load D into
2861 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2863 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2864 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2867 XEXP (XEXP (operand0
, 0),
2872 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2873 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2877 /* Handle secondary reloads for loads of FP registers from constant
2878 expressions by forcing the constant into memory.
2880 use scratch_reg to hold the address of the memory location.
2882 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2883 NO_REGS when presented with a const_int and an register class
2884 containing only FP registers. Doing so unfortunately creates
2885 more problems than it solves. Fix this for 2.5. */
2886 else if (fp_reg_operand (operand0
, mode
)
2887 && CONSTANT_P (operand1
)
2892 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2893 it in SIMODE regardless of what mode it was originally given
2895 scratch_reg
= force_mode (SImode
, scratch_reg
);
2897 /* Force the constant into memory and put the address of the
2898 memory location into scratch_reg. */
2899 xoperands
[0] = scratch_reg
;
2900 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2901 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2903 /* Now load the destination register. */
2904 emit_insn (gen_rtx_SET (mode
, operand0
,
2905 gen_rtx_MEM (mode
, scratch_reg
)));
2909 /* Now have insn-emit do whatever it normally does. */
2913 /* Split one or more DImode RTL references into pairs of SImode
2914 references. The RTL can be REG, offsettable MEM, integer constant, or
2915 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2916 split and "num" is its length. lo_half and hi_half are output arrays
2917 that parallel "operands". */
2920 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2924 rtx op
= operands
[num
];
2926 /* simplify_subreg refuses to split volatile memory addresses,
2927 but we still have to handle it. */
2928 if (GET_CODE (op
) == MEM
)
2930 lo_half
[num
] = adjust_address (op
, SImode
, 4);
2931 hi_half
[num
] = adjust_address (op
, SImode
, 0);
2935 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2936 GET_MODE (op
) == VOIDmode
2937 ? DImode
: GET_MODE (op
), 4);
2938 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2939 GET_MODE (op
) == VOIDmode
2940 ? DImode
: GET_MODE (op
), 0);
2945 /* Split X into a base and a constant offset, storing them in *BASE
2946 and *OFFSET respectively. */
2949 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
2952 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2954 *offset
+= INTVAL (XEXP (x
, 1));
2960 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
2961 instruction. STORE_P says whether the move is a load or store.
2963 If the instruction uses post-increment or pre-decrement addressing,
2964 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
2965 adjustment. This adjustment will be made by the first element of
2966 PARALLEL, with the loads or stores starting at element 1. If the
2967 instruction does not use post-increment or pre-decrement addressing,
2968 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
2969 start at element 0. */
2972 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
2973 HOST_WIDE_INT automod_offset
, bool store_p
)
2975 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
2976 HOST_WIDE_INT offset
, mem_offset
;
2978 enum reg_class rclass
;
2980 len
= XVECLEN (pattern
, 0);
2981 first
= (automod_base
!= NULL
);
2985 /* Stores must be pre-decrement and loads must be post-increment. */
2986 if (store_p
!= (automod_offset
< 0))
2989 /* Work out the base and offset for lowest memory location. */
2990 base
= automod_base
;
2991 offset
= (automod_offset
< 0 ? automod_offset
: 0);
2995 /* Allow any valid base and offset in the first access. */
3002 for (i
= first
; i
< len
; i
++)
3004 /* We need a plain SET. */
3005 set
= XVECEXP (pattern
, 0, i
);
3006 if (GET_CODE (set
) != SET
)
3009 /* Check that we have a memory location... */
3010 mem
= XEXP (set
, !store_p
);
3011 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3014 /* ...with the right address. */
3017 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3018 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3019 There are no mode restrictions for 680x0 besides the
3020 automodification rules enforced above. */
3022 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3027 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3028 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3032 /* Check that we have a register of the required mode and class. */
3033 reg
= XEXP (set
, store_p
);
3035 || !HARD_REGISTER_P (reg
)
3036 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3041 /* The register must belong to RCLASS and have a higher number
3042 than the register in the previous SET. */
3043 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3044 || REGNO (last_reg
) >= REGNO (reg
))
3049 /* Work out which register class we need. */
3050 if (INT_REGNO_P (REGNO (reg
)))
3051 rclass
= GENERAL_REGS
;
3052 else if (FP_REGNO_P (REGNO (reg
)))
3059 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3062 /* If we have an automodification, check whether the final offset is OK. */
3063 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3066 /* Reject unprofitable cases. */
3067 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3073 /* Return the assembly code template for a movem or fmovem instruction
3074 whose pattern is given by PATTERN. Store the template's operands
3077 If the instruction uses post-increment or pre-decrement addressing,
3078 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3079 is true if this is a store instruction. */
3082 m68k_output_movem (rtx
*operands
, rtx pattern
,
3083 HOST_WIDE_INT automod_offset
, bool store_p
)
3088 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3090 first
= (automod_offset
!= 0);
3091 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3093 /* When using movem with pre-decrement addressing, register X + D0_REG
3094 is controlled by bit 15 - X. For all other addressing modes,
3095 register X + D0_REG is controlled by bit X. Confusingly, the
3096 register mask for fmovem is in the opposite order to that for
3100 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3101 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3102 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3103 if (automod_offset
< 0)
3105 if (FP_REGNO_P (regno
))
3106 mask
|= 1 << (regno
- FP0_REG
);
3108 mask
|= 1 << (15 - (regno
- D0_REG
));
3112 if (FP_REGNO_P (regno
))
3113 mask
|= 1 << (7 - (regno
- FP0_REG
));
3115 mask
|= 1 << (regno
- D0_REG
);
3120 if (automod_offset
== 0)
3121 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3122 else if (automod_offset
< 0)
3123 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3125 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3126 operands
[1] = GEN_INT (mask
);
3127 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3130 return MOTOROLA
? "fmovm %1,%a0" : "fmovem %1,%a0";
3132 return MOTOROLA
? "fmovm %a0,%1" : "fmovem %a0,%1";
3137 return MOTOROLA
? "movm.l %1,%a0" : "moveml %1,%a0";
3139 return MOTOROLA
? "movm.l %a0,%1" : "moveml %a0,%1";
3143 /* Return a REG that occurs in ADDR with coefficient 1.
3144 ADDR can be effectively incremented by incrementing REG. */
3147 find_addr_reg (rtx addr
)
3149 while (GET_CODE (addr
) == PLUS
)
3151 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3152 addr
= XEXP (addr
, 0);
3153 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3154 addr
= XEXP (addr
, 1);
3155 else if (CONSTANT_P (XEXP (addr
, 0)))
3156 addr
= XEXP (addr
, 1);
3157 else if (CONSTANT_P (XEXP (addr
, 1)))
3158 addr
= XEXP (addr
, 0);
3162 gcc_assert (GET_CODE (addr
) == REG
);
3166 /* Output assembler code to perform a 32-bit 3-operand add. */
3169 output_addsi3 (rtx
*operands
)
3171 if (! operands_match_p (operands
[0], operands
[1]))
3173 if (!ADDRESS_REG_P (operands
[1]))
3175 rtx tmp
= operands
[1];
3177 operands
[1] = operands
[2];
3181 /* These insns can result from reloads to access
3182 stack slots over 64k from the frame pointer. */
3183 if (GET_CODE (operands
[2]) == CONST_INT
3184 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3185 return "move%.l %2,%0\n\tadd%.l %1,%0";
3186 if (GET_CODE (operands
[2]) == REG
)
3187 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3188 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3190 if (GET_CODE (operands
[2]) == CONST_INT
)
3192 if (INTVAL (operands
[2]) > 0
3193 && INTVAL (operands
[2]) <= 8)
3194 return "addq%.l %2,%0";
3195 if (INTVAL (operands
[2]) < 0
3196 && INTVAL (operands
[2]) >= -8)
3198 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3199 return "subq%.l %2,%0";
3201 /* On the CPU32 it is faster to use two addql instructions to
3202 add a small integer (8 < N <= 16) to a register.
3203 Likewise for subql. */
3204 if (TUNE_CPU32
&& REG_P (operands
[0]))
3206 if (INTVAL (operands
[2]) > 8
3207 && INTVAL (operands
[2]) <= 16)
3209 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3210 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3212 if (INTVAL (operands
[2]) < -8
3213 && INTVAL (operands
[2]) >= -16)
3215 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3216 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3219 if (ADDRESS_REG_P (operands
[0])
3220 && INTVAL (operands
[2]) >= -0x8000
3221 && INTVAL (operands
[2]) < 0x8000)
3224 return "add%.w %2,%0";
3226 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3229 return "add%.l %2,%0";
3232 /* Store in cc_status the expressions that the condition codes will
3233 describe after execution of an instruction whose pattern is EXP.
3234 Do not alter them if the instruction would not alter the cc's. */
3236 /* On the 68000, all the insns to store in an address register fail to
3237 set the cc's. However, in some cases these instructions can make it
3238 possibly invalid to use the saved cc's. In those cases we clear out
3239 some or all of the saved cc's so they won't be used. */
3242 notice_update_cc (rtx exp
, rtx insn
)
3244 if (GET_CODE (exp
) == SET
)
3246 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3248 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3250 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3251 cc_status
.value1
= 0;
3252 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3253 cc_status
.value2
= 0;
3255 /* fmoves to memory or data registers do not set the condition
3256 codes. Normal moves _do_ set the condition codes, but not in
3257 a way that is appropriate for comparison with 0, because -0.0
3258 would be treated as a negative nonzero number. Note that it
3259 isn't appropriate to conditionalize this restriction on
3260 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3261 we care about the difference between -0.0 and +0.0. */
3262 else if (!FP_REG_P (SET_DEST (exp
))
3263 && SET_DEST (exp
) != cc0_rtx
3264 && (FP_REG_P (SET_SRC (exp
))
3265 || GET_CODE (SET_SRC (exp
)) == FIX
3266 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3268 /* A pair of move insns doesn't produce a useful overall cc. */
3269 else if (!FP_REG_P (SET_DEST (exp
))
3270 && !FP_REG_P (SET_SRC (exp
))
3271 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3272 && (GET_CODE (SET_SRC (exp
)) == REG
3273 || GET_CODE (SET_SRC (exp
)) == MEM
3274 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3276 else if (SET_DEST (exp
) != pc_rtx
)
3278 cc_status
.flags
= 0;
3279 cc_status
.value1
= SET_DEST (exp
);
3280 cc_status
.value2
= SET_SRC (exp
);
3283 else if (GET_CODE (exp
) == PARALLEL
3284 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3286 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3287 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3289 if (ADDRESS_REG_P (dest
))
3291 else if (dest
!= pc_rtx
)
3293 cc_status
.flags
= 0;
3294 cc_status
.value1
= dest
;
3295 cc_status
.value2
= src
;
3300 if (cc_status
.value2
!= 0
3301 && ADDRESS_REG_P (cc_status
.value2
)
3302 && GET_MODE (cc_status
.value2
) == QImode
)
3304 if (cc_status
.value2
!= 0)
3305 switch (GET_CODE (cc_status
.value2
))
3307 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3308 case ROTATE
: case ROTATERT
:
3309 /* These instructions always clear the overflow bit, and set
3310 the carry to the bit shifted out. */
3311 /* ??? We don't currently have a way to signal carry not valid,
3312 nor do we check for it in the branch insns. */
3316 case PLUS
: case MINUS
: case MULT
:
3317 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3318 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3319 cc_status
.flags
|= CC_NO_OVERFLOW
;
3322 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3323 ends with a move insn moving r2 in r2's mode.
3324 Thus, the cc's are set for r2.
3325 This can set N bit spuriously. */
3326 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3331 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3333 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3334 cc_status
.value2
= 0;
3335 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3336 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3337 cc_status
.flags
= CC_IN_68881
;
3341 output_move_const_double (rtx
*operands
)
3343 int code
= standard_68881_constant_p (operands
[1]);
3347 static char buf
[40];
3349 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3352 return "fmove%.d %1,%0";
3356 output_move_const_single (rtx
*operands
)
3358 int code
= standard_68881_constant_p (operands
[1]);
3362 static char buf
[40];
3364 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3367 return "fmove%.s %f1,%0";
3370 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3371 from the "fmovecr" instruction.
3372 The value, anded with 0xff, gives the code to use in fmovecr
3373 to get the desired constant. */
3375 /* This code has been fixed for cross-compilation. */
3377 static int inited_68881_table
= 0;
3379 static const char *const strings_68881
[7] = {
3389 static const int codes_68881
[7] = {
3399 REAL_VALUE_TYPE values_68881
[7];
3401 /* Set up values_68881 array by converting the decimal values
3402 strings_68881 to binary. */
3405 init_68881_table (void)
3409 enum machine_mode mode
;
3412 for (i
= 0; i
< 7; i
++)
3416 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3417 values_68881
[i
] = r
;
3419 inited_68881_table
= 1;
3423 standard_68881_constant_p (rtx x
)
3428 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3429 used at all on those chips. */
3433 if (! inited_68881_table
)
3434 init_68881_table ();
3436 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3438 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3440 for (i
= 0; i
< 6; i
++)
3442 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3443 return (codes_68881
[i
]);
3446 if (GET_MODE (x
) == SFmode
)
3449 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3450 return (codes_68881
[6]);
3452 /* larger powers of ten in the constants ram are not used
3453 because they are not equal to a `double' C constant. */
3457 /* If X is a floating-point constant, return the logarithm of X base 2,
3458 or 0 if X is not a power of 2. */
3461 floating_exact_log2 (rtx x
)
3463 REAL_VALUE_TYPE r
, r1
;
3466 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3468 if (REAL_VALUES_LESS (r
, dconst1
))
3471 exp
= real_exponent (&r
);
3472 real_2expN (&r1
, exp
);
3473 if (REAL_VALUES_EQUAL (r1
, r
))
3479 /* A C compound statement to output to stdio stream STREAM the
3480 assembler syntax for an instruction operand X. X is an RTL
3483 CODE is a value that can be used to specify one of several ways
3484 of printing the operand. It is used when identical operands
3485 must be printed differently depending on the context. CODE
3486 comes from the `%' specification that was used to request
3487 printing of the operand. If the specification was just `%DIGIT'
3488 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3489 is the ASCII code for LTR.
3491 If X is a register, this macro should print the register's name.
3492 The names can be found in an array `reg_names' whose type is
3493 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3495 When the machine description has a specification `%PUNCT' (a `%'
3496 followed by a punctuation character), this macro is called with
3497 a null pointer for X and the punctuation character for CODE.
3499 The m68k specific codes are:
3501 '.' for dot needed in Motorola-style opcode names.
3502 '-' for an operand pushing on the stack:
3503 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3504 '+' for an operand pushing on the stack:
3505 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3506 '@' for a reference to the top word on the stack:
3507 sp@, (sp) or (%sp) depending on the style of syntax.
3508 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3509 but & in SGS syntax).
3510 '!' for the cc register (used in an `and to cc' insn).
3511 '$' for the letter `s' in an op code, but only on the 68040.
3512 '&' for the letter `d' in an op code, but only on the 68040.
3513 '/' for register prefix needed by longlong.h.
3514 '?' for m68k_library_id_string
3516 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3517 'd' to force memory addressing to be absolute, not relative.
3518 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3519 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3520 or print pair of registers as rx:ry.
3521 'p' print an address with @PLTPC attached, but only if the operand
3522 is not locally-bound. */
3525 print_operand (FILE *file
, rtx op
, int letter
)
3530 fprintf (file
, ".");
3532 else if (letter
== '#')
3533 asm_fprintf (file
, "%I");
3534 else if (letter
== '-')
3535 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3536 else if (letter
== '+')
3537 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3538 else if (letter
== '@')
3539 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3540 else if (letter
== '!')
3541 asm_fprintf (file
, "%Rfpcr");
3542 else if (letter
== '$')
3545 fprintf (file
, "s");
3547 else if (letter
== '&')
3550 fprintf (file
, "d");
3552 else if (letter
== '/')
3553 asm_fprintf (file
, "%R");
3554 else if (letter
== '?')
3555 asm_fprintf (file
, m68k_library_id_string
);
3556 else if (letter
== 'p')
3558 output_addr_const (file
, op
);
3559 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3560 fprintf (file
, "@PLTPC");
3562 else if (GET_CODE (op
) == REG
)
3565 /* Print out the second register name of a register pair.
3566 I.e., R (6) => 7. */
3567 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3569 fputs (M68K_REGNAME(REGNO (op
)), file
);
3571 else if (GET_CODE (op
) == MEM
)
3573 output_address (XEXP (op
, 0));
3574 if (letter
== 'd' && ! TARGET_68020
3575 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3576 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3577 && INTVAL (XEXP (op
, 0)) < 0x8000
3578 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3579 fprintf (file
, MOTOROLA
? ".l" : ":l");
3581 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3584 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3585 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3587 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3590 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3591 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3593 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3596 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3597 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3601 /* Use `print_operand_address' instead of `output_addr_const'
3602 to ensure that we print relevant PIC stuff. */
3603 asm_fprintf (file
, "%I");
3605 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3606 print_operand_address (file
, op
);
3608 output_addr_const (file
, op
);
3613 /* A C compound statement to output to stdio stream STREAM the
3614 assembler syntax for an instruction operand that is a memory
3615 reference whose address is ADDR. ADDR is an RTL expression.
3617 Note that this contains a kludge that knows that the only reason
3618 we have an address (plus (label_ref...) (reg...)) when not generating
3619 PIC code is in the insn before a tablejump, and we know that m68k.md
3620 generates a label LInnn: on such an insn.
3622 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3623 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3625 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3626 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3627 we want. This difference can be accommodated by using an assembler
3628 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3629 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3630 macro. See m68k/sgs.h for an example; for versions without the bug.
3631 Some assemblers refuse all the above solutions. The workaround is to
3632 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3635 They also do not like things like "pea 1.w", so we simple leave off
3636 the .w on small constants.
3638 This routine is responsible for distinguishing between -fpic and -fPIC
3639 style relocations in an address. When generating -fpic code the
3640 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3641 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3644 print_operand_address (FILE *file
, rtx addr
)
3646 struct m68k_address address
;
3648 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3651 if (address
.code
== PRE_DEC
)
3652 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3653 M68K_REGNAME (REGNO (address
.base
)));
3654 else if (address
.code
== POST_INC
)
3655 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3656 M68K_REGNAME (REGNO (address
.base
)));
3657 else if (!address
.base
&& !address
.index
)
3659 /* A constant address. */
3660 gcc_assert (address
.offset
== addr
);
3661 if (GET_CODE (addr
) == CONST_INT
)
3663 /* (xxx).w or (xxx).l. */
3664 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3665 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3667 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3669 else if (TARGET_PCREL
)
3671 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3673 output_addr_const (file
, addr
);
3674 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3678 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3679 name ends in `.<letter>', as the last 2 characters can be
3680 mistaken as a size suffix. Put the name in parentheses. */
3681 if (GET_CODE (addr
) == SYMBOL_REF
3682 && strlen (XSTR (addr
, 0)) > 2
3683 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3686 output_addr_const (file
, addr
);
3690 output_addr_const (file
, addr
);
3697 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3698 label being acceesed, otherwise it is -1. */
3699 labelno
= (address
.offset
3701 && GET_CODE (address
.offset
) == LABEL_REF
3702 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3706 /* Print the "offset(base" component. */
3708 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3713 output_addr_const (file
, address
.offset
);
3714 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3716 fprintf (file
, "@GOT");
3717 if (flag_pic
== 1 && TARGET_68020
)
3718 fprintf (file
, ".w");
3723 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3725 /* Print the ",index" component, if any. */
3730 fprintf (file
, "%s.%c",
3731 M68K_REGNAME (REGNO (address
.index
)),
3732 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3733 if (address
.scale
!= 1)
3734 fprintf (file
, "*%d", address
.scale
);
3738 else /* !MOTOROLA */
3740 if (!address
.offset
&& !address
.index
)
3741 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3744 /* Print the "base@(offset" component. */
3746 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3750 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3751 fprintf (file
, "@(");
3754 output_addr_const (file
, address
.offset
);
3755 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3759 fprintf (file
, ":w"); break;
3761 fprintf (file
, ":l"); break;
3767 /* Print the ",index" component, if any. */
3770 fprintf (file
, ",%s:%c",
3771 M68K_REGNAME (REGNO (address
.index
)),
3772 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3773 if (address
.scale
!= 1)
3774 fprintf (file
, ":%d", address
.scale
);
3782 /* Check for cases where a clr insns can be omitted from code using
3783 strict_low_part sets. For example, the second clrl here is not needed:
3784 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3786 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3787 insn we are checking for redundancy. TARGET is the register set by the
3791 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3796 p
= prev_nonnote_insn (first_insn
);
3800 /* If it isn't an insn, then give up. */
3801 if (GET_CODE (p
) != INSN
)
3804 if (reg_set_p (target
, p
))
3806 rtx set
= single_set (p
);
3809 /* If it isn't an easy to recognize insn, then give up. */
3813 dest
= SET_DEST (set
);
3815 /* If this sets the entire target register to zero, then our
3816 first_insn is redundant. */
3817 if (rtx_equal_p (dest
, target
)
3818 && SET_SRC (set
) == const0_rtx
)
3820 else if (GET_CODE (dest
) == STRICT_LOW_PART
3821 && GET_CODE (XEXP (dest
, 0)) == REG
3822 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3823 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3824 <= GET_MODE_SIZE (mode
)))
3825 /* This is a strict low part set which modifies less than
3826 we are using, so it is safe. */
3832 p
= prev_nonnote_insn (p
);
3838 /* Operand predicates for implementing asymmetric pc-relative addressing
3839 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3840 when used as a source operand, but not as a destination operand.
3842 We model this by restricting the meaning of the basic predicates
3843 (general_operand, memory_operand, etc) to forbid the use of this
3844 addressing mode, and then define the following predicates that permit
3845 this addressing mode. These predicates can then be used for the
3846 source operands of the appropriate instructions.
3848 n.b. While it is theoretically possible to change all machine patterns
3849 to use this addressing more where permitted by the architecture,
3850 it has only been implemented for "common" cases: SImode, HImode, and
3851 QImode operands, and only for the principle operations that would
3852 require this addressing mode: data movement and simple integer operations.
3854 In parallel with these new predicates, two new constraint letters
3855 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3856 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3857 In the pcrel case 's' is only valid in combination with 'a' registers.
3858 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3859 of how these constraints are used.
3861 The use of these predicates is strictly optional, though patterns that
3862 don't will cause an extra reload register to be allocated where one
3865 lea (abc:w,%pc),%a0 ; need to reload address
3866 moveq &1,%d1 ; since write to pc-relative space
3867 movel %d1,%a0@ ; is not allowed
3869 lea (abc:w,%pc),%a1 ; no need to reload address here
3870 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3872 For more info, consult tiemann@cygnus.com.
3875 All of the ugliness with predicates and constraints is due to the
3876 simple fact that the m68k does not allow a pc-relative addressing
3877 mode as a destination. gcc does not distinguish between source and
3878 destination addresses. Hence, if we claim that pc-relative address
3879 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3880 end up with invalid code. To get around this problem, we left
3881 pc-relative modes as invalid addresses, and then added special
3882 predicates and constraints to accept them.
3884 A cleaner way to handle this is to modify gcc to distinguish
3885 between source and destination addresses. We can then say that
3886 pc-relative is a valid source address but not a valid destination
3887 address, and hopefully avoid a lot of the predicate and constraint
3888 hackery. Unfortunately, this would be a pretty big change. It would
3889 be a useful change for a number of ports, but there aren't any current
3890 plans to undertake this.
3892 ***************************************************************************/
3896 output_andsi3 (rtx
*operands
)
3899 if (GET_CODE (operands
[2]) == CONST_INT
3900 && (INTVAL (operands
[2]) | 0xffff) == -1
3901 && (DATA_REG_P (operands
[0])
3902 || offsettable_memref_p (operands
[0]))
3903 && !TARGET_COLDFIRE
)
3905 if (GET_CODE (operands
[0]) != REG
)
3906 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3907 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3908 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3910 if (operands
[2] == const0_rtx
)
3912 return "and%.w %2,%0";
3914 if (GET_CODE (operands
[2]) == CONST_INT
3915 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3916 && (DATA_REG_P (operands
[0])
3917 || offsettable_memref_p (operands
[0])))
3919 if (DATA_REG_P (operands
[0]))
3920 operands
[1] = GEN_INT (logval
);
3923 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3924 operands
[1] = GEN_INT (logval
% 8);
3926 /* This does not set condition codes in a standard way. */
3928 return "bclr %1,%0";
3930 return "and%.l %2,%0";
3934 output_iorsi3 (rtx
*operands
)
3936 register int logval
;
3937 if (GET_CODE (operands
[2]) == CONST_INT
3938 && INTVAL (operands
[2]) >> 16 == 0
3939 && (DATA_REG_P (operands
[0])
3940 || offsettable_memref_p (operands
[0]))
3941 && !TARGET_COLDFIRE
)
3943 if (GET_CODE (operands
[0]) != REG
)
3944 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3945 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3947 if (INTVAL (operands
[2]) == 0xffff)
3948 return "mov%.w %2,%0";
3949 return "or%.w %2,%0";
3951 if (GET_CODE (operands
[2]) == CONST_INT
3952 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3953 && (DATA_REG_P (operands
[0])
3954 || offsettable_memref_p (operands
[0])))
3956 if (DATA_REG_P (operands
[0]))
3957 operands
[1] = GEN_INT (logval
);
3960 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3961 operands
[1] = GEN_INT (logval
% 8);
3964 return "bset %1,%0";
3966 return "or%.l %2,%0";
3970 output_xorsi3 (rtx
*operands
)
3972 register int logval
;
3973 if (GET_CODE (operands
[2]) == CONST_INT
3974 && INTVAL (operands
[2]) >> 16 == 0
3975 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3976 && !TARGET_COLDFIRE
)
3978 if (! DATA_REG_P (operands
[0]))
3979 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3980 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3982 if (INTVAL (operands
[2]) == 0xffff)
3984 return "eor%.w %2,%0";
3986 if (GET_CODE (operands
[2]) == CONST_INT
3987 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3988 && (DATA_REG_P (operands
[0])
3989 || offsettable_memref_p (operands
[0])))
3991 if (DATA_REG_P (operands
[0]))
3992 operands
[1] = GEN_INT (logval
);
3995 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3996 operands
[1] = GEN_INT (logval
% 8);
3999 return "bchg %1,%0";
4001 return "eor%.l %2,%0";
4004 /* Return the instruction that should be used for a call to address X,
4005 which is known to be in operand 0. */
4010 if (symbolic_operand (x
, VOIDmode
))
4011 return m68k_symbolic_call
;
4016 #ifdef M68K_TARGET_COFF
4018 /* Output assembly to switch to section NAME with attribute FLAGS. */
4021 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4022 tree decl ATTRIBUTE_UNUSED
)
4026 if (flags
& SECTION_WRITE
)
4031 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4034 #endif /* M68K_TARGET_COFF */
4037 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4038 HOST_WIDE_INT delta
,
4039 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
4045 if (delta
> 0 && delta
<= 8)
4046 asm_fprintf (file
, (MOTOROLA
4047 ? "\taddq.l %I%d,4(%Rsp)\n"
4048 : "\taddql %I%d,%Rsp@(4)\n"),
4050 else if (delta
< 0 && delta
>= -8)
4051 asm_fprintf (file
, (MOTOROLA
4052 ? "\tsubq.l %I%d,4(%Rsp)\n"
4053 : "\tsubql %I%d,%Rsp@(4)\n"),
4055 else if (TARGET_COLDFIRE
)
4057 /* ColdFire can't add/sub a constant to memory unless it is in
4058 the range of addq/subq. So load the value into %d0 and
4059 then add it to 4(%sp). */
4060 if (delta
>= -128 && delta
<= 127)
4061 asm_fprintf (file
, (MOTOROLA
4062 ? "\tmoveq.l %I%wd,%Rd0\n"
4063 : "\tmoveql %I%wd,%Rd0\n"),
4066 asm_fprintf (file
, (MOTOROLA
4067 ? "\tmove.l %I%wd,%Rd0\n"
4068 : "\tmovel %I%wd,%Rd0\n"),
4070 asm_fprintf (file
, (MOTOROLA
4071 ? "\tadd.l %Rd0,4(%Rsp)\n"
4072 : "\taddl %Rd0,%Rsp@(4)\n"));
4075 asm_fprintf (file
, (MOTOROLA
4076 ? "\tadd.l %I%wd,4(%Rsp)\n"
4077 : "\taddl %I%wd,%Rsp@(4)\n"),
4080 xops
[0] = DECL_RTL (function
);
4082 gcc_assert (MEM_P (xops
[0])
4083 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
4084 xops
[0] = XEXP (xops
[0], 0);
4086 fmt
= m68k_symbolic_jump
;
4087 if (m68k_symbolic_jump
== NULL
)
4088 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
4090 output_asm_insn (fmt
, xops
);
4093 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4096 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4097 int incoming ATTRIBUTE_UNUSED
)
4099 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4102 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4104 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4105 unsigned int new_reg
)
4108 /* Interrupt functions can only use registers that have already been
4109 saved by the prologue, even if they would normally be
4112 if (m68k_interrupt_function_p (current_function_decl
)
4113 && !regs_ever_live
[new_reg
])
4119 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
4120 On the 68000, the cpu registers can hold any mode except bytes in address
4121 registers, but the 68881 registers can hold only SFmode or DFmode. */
4123 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4125 if (DATA_REGNO_P (regno
))
4127 /* Data Registers, can hold aggregate if fits in. */
4128 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4131 else if (ADDRESS_REGNO_P (regno
))
4133 /* Address Registers, can't hold bytes, can hold aggregate if
4135 if (GET_MODE_SIZE (mode
) == 1)
4137 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4140 else if (FP_REGNO_P (regno
))
4142 /* FPU registers, hold float or complex float of long double or
4144 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4145 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4146 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4152 /* Return floating point values in a 68881 register. This makes 68881 code
4153 a little bit faster. It also makes -msoft-float code incompatible with
4154 hard-float code, so people have to be careful not to mix the two.
4155 For ColdFire it was decided the ABI incompatibility is undesirable.
4156 If there is need for a hard-float ABI it is probably worth doing it
4157 properly and also passing function arguments in FP registers. */
4159 m68k_libcall_value (enum machine_mode mode
)
4166 return gen_rtx_REG (mode
, 16);
4171 return gen_rtx_REG (mode
, 0);
4175 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4177 enum machine_mode mode
;
4179 mode
= TYPE_MODE (valtype
);
4185 return gen_rtx_REG (mode
, 16);
4191 /* If the function returns a pointer, push that into %a0. */
4192 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4193 /* For compatibility with the large body of existing code which
4194 does not always properly declare external functions returning
4195 pointer types, the m68k/SVR4 convention is to copy the value
4196 returned for pointer functions from a0 to d0 in the function
4197 epilogue, so that callers that have neglected to properly
4198 declare the callee can still find the correct return value in
4200 return gen_rtx_PARALLEL
4203 gen_rtx_EXPR_LIST (VOIDmode
,
4204 gen_rtx_REG (mode
, A0_REG
),
4206 gen_rtx_EXPR_LIST (VOIDmode
,
4207 gen_rtx_REG (mode
, D0_REG
),
4209 else if (POINTER_TYPE_P (valtype
))
4210 return gen_rtx_REG (mode
, A0_REG
);
4212 return gen_rtx_REG (mode
, D0_REG
);