1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static rtx
find_addr_reg (rtx
);
107 static const char *singlemove_string (rtx
*);
108 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
109 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
110 #ifdef M68K_TARGET_COFF
111 static void m68k_coff_asm_named_section (const char *, unsigned int);
112 #endif /* M68K_TARGET_COFF */
113 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
114 HOST_WIDE_INT
, tree
);
115 static rtx
m68k_struct_value_rtx (tree
, int);
116 static bool m68k_interrupt_function_p (tree func
);
117 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
118 tree args
, int flags
,
120 static void m68k_compute_frame_layout (void);
121 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
122 static int const_int_cost (rtx
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Alignment to use for loops and jumps */
127 /* Specify power of two alignment used for loops. */
128 const char *m68k_align_loops_string
;
129 /* Specify power of two alignment used for non-loop jumps. */
130 const char *m68k_align_jumps_string
;
131 /* Specify power of two alignment used for functions. */
132 const char *m68k_align_funcs_string
;
133 /* Specify the identification number of the library being built */
134 const char *m68k_library_id_string
;
136 /* Specify power of two alignment used for loops. */
137 int m68k_align_loops
;
138 /* Specify power of two alignment used for non-loop jumps. */
139 int m68k_align_jumps
;
140 /* Specify power of two alignment used for functions. */
141 int m68k_align_funcs
;
143 /* Nonzero if the last compare/test insn had FP operands. The
144 sCC expanders peek at this to determine what to do for the
145 68060, which has no fsCC instructions. */
146 int m68k_last_compare_had_fp_operands
;
148 /* Initialize the GCC target structure. */
150 #if INT_OP_GROUP == INT_OP_DOT_WORD
151 #undef TARGET_ASM_ALIGNED_HI_OP
152 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
155 #if INT_OP_GROUP == INT_OP_NO_DOT
156 #undef TARGET_ASM_BYTE_OP
157 #define TARGET_ASM_BYTE_OP "\tbyte\t"
158 #undef TARGET_ASM_ALIGNED_HI_OP
159 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
160 #undef TARGET_ASM_ALIGNED_SI_OP
161 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
164 #if INT_OP_GROUP == INT_OP_DC
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
173 #undef TARGET_ASM_UNALIGNED_HI_OP
174 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
175 #undef TARGET_ASM_UNALIGNED_SI_OP
176 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
183 #undef TARGET_ASM_OUTPUT_MI_THUNK
184 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
185 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
186 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
188 #undef TARGET_ASM_FILE_START_APP_OFF
189 #define TARGET_ASM_FILE_START_APP_OFF true
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS m68k_rtx_costs
194 #undef TARGET_ATTRIBUTE_TABLE
195 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
197 #undef TARGET_PROMOTE_PROTOTYPES
198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
200 #undef TARGET_STRUCT_VALUE_RTX
201 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
203 static const struct attribute_spec m68k_attribute_table
[] =
205 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
206 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
207 { NULL
, 0, 0, false, false, false, NULL
}
210 struct gcc_target targetm
= TARGET_INITIALIZER
;
212 /* Sometimes certain combinations of command options do not make
213 sense on a particular target machine. You can define a macro
214 `OVERRIDE_OPTIONS' to take account of this. This macro, if
215 defined, is executed once just after all the command options have
218 Don't use this macro to turn on various extra optimizations for
219 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
222 override_options (void)
229 /* Validate -malign-loops= value, or provide default */
230 m68k_align_loops
= def_align
;
231 if (m68k_align_loops_string
)
233 i
= atoi (m68k_align_loops_string
);
234 if (i
< 1 || i
> MAX_CODE_ALIGN
)
235 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
237 m68k_align_loops
= i
;
240 /* Library identification */
241 if (m68k_library_id_string
)
245 if (! TARGET_ID_SHARED_LIBRARY
)
246 error ("-mshared-library-id= specified without -mid-shared-library");
247 id
= atoi (m68k_library_id_string
);
248 if (id
< 0 || id
> MAX_LIBRARY_ID
)
249 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
251 /* From now on, m68k_library_id_string will contain the library offset. */
252 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
255 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
257 m68k_library_id_string
= "_current_shared_library_a5_offset_";
259 /* Sanity check to ensure that msep-data and mid-sahred-library are not
260 * both specified together. Doing so simply doesn't make sense.
262 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
263 error ("cannot specify both -msep-data and -mid-shared-library");
265 /* If we're generating code for a separate A5 relative data segment,
266 * we've got to enable -fPIC as well. This might be relaxable to
267 * -fpic but it hasn't been tested properly.
269 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
272 /* Validate -malign-jumps= value, or provide default */
273 m68k_align_jumps
= def_align
;
274 if (m68k_align_jumps_string
)
276 i
= atoi (m68k_align_jumps_string
);
277 if (i
< 1 || i
> MAX_CODE_ALIGN
)
278 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
280 m68k_align_jumps
= i
;
283 /* Validate -malign-functions= value, or provide default */
284 m68k_align_funcs
= def_align
;
285 if (m68k_align_funcs_string
)
287 i
= atoi (m68k_align_funcs_string
);
288 if (i
< 1 || i
> MAX_CODE_ALIGN
)
289 error ("-malign-functions=%d is not between 1 and %d",
292 m68k_align_funcs
= i
;
295 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
297 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
298 error("-fPIC is not currently supported on the 68000 or 68010\n");
300 /* ??? A historic way of turning on pic, or is this intended to
301 be an embedded thing that doesn't have the same name binding
302 significance that it does on hosted ELF systems? */
303 if (TARGET_PCREL
&& flag_pic
== 0)
306 /* Turn off function cse if we are doing PIC. We always want function call
307 to be done as `bsr foo@PLTPC', so it will force the assembler to create
308 the PLT entry for `foo'. Doing function cse will cause the address of
309 `foo' to be loaded into a register, which is exactly what we want to
310 avoid when we are doing PIC on svr4 m68k. */
312 flag_no_function_cse
= 1;
314 SUBTARGET_OVERRIDE_OPTIONS
;
317 /* Return nonzero if FUNC is an interrupt function as specified by the
318 "interrupt_handler" attribute. */
320 m68k_interrupt_function_p(tree func
)
324 if (TREE_CODE (func
) != FUNCTION_DECL
)
327 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
328 return (a
!= NULL_TREE
);
331 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
332 struct attribute_spec.handler. */
334 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
335 tree args ATTRIBUTE_UNUSED
,
336 int flags ATTRIBUTE_UNUSED
,
339 if (TREE_CODE (*node
) != FUNCTION_DECL
)
341 warning ("`%s' attribute only applies to functions",
342 IDENTIFIER_POINTER (name
));
343 *no_add_attrs
= true;
350 m68k_compute_frame_layout (void)
353 unsigned int mask
, rmask
;
354 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
356 /* Only compute the frame once per function.
357 Don't cache information until reload has been completed. */
358 if (current_frame
.funcdef_no
== current_function_funcdef_no
362 current_frame
.size
= (get_frame_size () + 3) & -4;
364 mask
= rmask
= saved
= 0;
365 for (regno
= 0; regno
< 16; regno
++)
366 if (m68k_save_reg (regno
, interrupt_handler
))
369 rmask
|= 1 << (15 - regno
);
372 current_frame
.offset
= saved
* 4;
373 current_frame
.reg_no
= saved
;
374 current_frame
.reg_mask
= mask
;
375 current_frame
.reg_rev_mask
= rmask
;
377 current_frame
.foffset
= 0;
378 mask
= rmask
= saved
= 0;
379 if (TARGET_68881
/* || TARGET_CFV4E */)
381 for (regno
= 16; regno
< 24; regno
++)
382 if (m68k_save_reg (regno
, interrupt_handler
))
384 mask
|= 1 << (regno
- 16);
385 rmask
|= 1 << (23 - regno
);
388 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
389 current_frame
.offset
+= current_frame
.foffset
;
391 current_frame
.fpu_no
= saved
;
392 current_frame
.fpu_mask
= mask
;
393 current_frame
.fpu_rev_mask
= rmask
;
395 /* Remember what function this frame refers to. */
396 current_frame
.funcdef_no
= current_function_funcdef_no
;
400 m68k_initial_elimination_offset (int from
, int to
)
402 /* FIXME: The correct offset to compute here would appear to be
403 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
404 but for some obscure reason, this must be 0 to get correct code. */
405 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
408 m68k_compute_frame_layout ();
410 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
411 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
412 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
413 return current_frame
.offset
+ current_frame
.size
;
418 /* Refer to the array `regs_ever_live' to determine which registers
419 to save; `regs_ever_live[I]' is nonzero if register number I
420 is ever used in the function. This function is responsible for
421 knowing which registers should not be saved even if used.
422 Return true if we need to save REGNO. */
425 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
427 if (flag_pic
&& current_function_uses_pic_offset_table
428 && regno
== PIC_OFFSET_TABLE_REGNUM
)
431 if (current_function_calls_eh_return
)
436 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
437 if (test
== INVALID_REGNUM
)
444 /* Fixed regs we never touch. */
445 if (fixed_regs
[regno
])
448 /* The frame pointer (if it is such) is handled specially. */
449 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
452 /* Interrupt handlers must also save call_used_regs
453 if they are live or when calling nested functions. */
454 if (interrupt_handler
)
456 if (regs_ever_live
[regno
])
459 if (!current_function_is_leaf
&& call_used_regs
[regno
])
463 /* Never need to save registers that aren't touched. */
464 if (!regs_ever_live
[regno
])
467 /* Otherwise save everything that isn't call-clobbered. */
468 return !call_used_regs
[regno
];
471 /* This function generates the assembly code for function entry.
472 STREAM is a stdio stream to output the code to.
473 SIZE is an int: how many units of temporary storage to allocate. */
476 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
478 HOST_WIDE_INT fsize_with_regs
;
479 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
481 m68k_compute_frame_layout();
483 /* If the stack limit is a symbol, we can check it here,
484 before actually allocating the space. */
485 if (current_function_limit_stack
486 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
487 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
488 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
490 /* On ColdFire add register save into initial stack frame setup, if possible. */
491 fsize_with_regs
= current_frame
.size
;
492 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
493 fsize_with_regs
+= current_frame
.reg_no
* 4;
495 if (frame_pointer_needed
)
497 if (current_frame
.size
== 0 && TARGET_68040
)
498 /* on the 68040, pea + move is faster than link.w 0 */
499 fprintf (stream
, MOTOROLA
?
500 "\tpea (%s)\n\tmove.l %s,%s\n" :
501 "\tpea %s@\n\tmovel %s,%s\n",
502 M68K_REGNAME(FRAME_POINTER_REGNUM
),
503 M68K_REGNAME(STACK_POINTER_REGNUM
),
504 M68K_REGNAME(FRAME_POINTER_REGNUM
));
505 else if (fsize_with_regs
< 0x8000)
506 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
507 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
508 else if (TARGET_68020
)
509 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
510 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
512 /* Adding negative number is faster on the 68040. */
513 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
514 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
515 M68K_REGNAME(FRAME_POINTER_REGNUM
), -fsize_with_regs
);
517 if (dwarf2out_do_frame ())
520 l
= (char *) dwarf2out_cfi_label ();
522 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
523 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
524 cfa_offset
+= current_frame
.size
;
527 else if (fsize_with_regs
) /* !frame_pointer_needed */
529 if (fsize_with_regs
< 0x8000)
531 if (fsize_with_regs
<= 8)
533 if (!TARGET_COLDFIRE
)
534 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
537 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
540 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
541 /* On the CPU32 it is faster to use two subqw instructions to
542 subtract a small integer (8 < N <= 16) to a register. */
544 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
545 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
546 fsize_with_regs
- 8);
547 else if (TARGET_68040
)
548 /* Adding negative number is faster on the 68040. */
549 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
552 asm_fprintf (stream
, MOTOROLA
?
553 "\tlea (%wd,%Rsp),%Rsp\n" :
554 "\tlea %Rsp@(%wd),%Rsp\n",
557 else /* fsize_with_regs >= 0x8000 */
558 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
560 if (dwarf2out_do_frame ())
562 cfa_offset
+= current_frame
.size
+ 4;
563 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
565 } /* !frame_pointer_needed */
567 if (current_frame
.fpu_mask
)
569 asm_fprintf (stream
, MOTOROLA
?
570 "\tfmovm %I0x%x,-(%Rsp)\n" :
571 "\tfmovem %I0x%x,%Rsp@-\n",
572 current_frame
.fpu_mask
);
574 if (dwarf2out_do_frame ())
576 char *l
= (char *) dwarf2out_cfi_label ();
579 cfa_offset
+= current_frame
.fpu_no
* 12;
580 if (! frame_pointer_needed
)
581 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
582 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
583 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
584 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
588 /* If the stack limit is not a symbol, check it here.
589 This has the disadvantage that it may be too late... */
590 if (current_function_limit_stack
)
592 if (REG_P (stack_limit_rtx
))
593 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
594 M68K_REGNAME(REGNO (stack_limit_rtx
)));
595 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
596 warning ("stack limit expression is not supported");
599 if (current_frame
.reg_no
<= 2)
601 /* Store each separately in the same order moveml uses.
602 Using two movel instructions instead of a single moveml
603 is about 15% faster for the 68020 and 68030 at no expense
608 for (i
= 0; i
< 16; i
++)
609 if (current_frame
.reg_rev_mask
& (1 << i
))
611 asm_fprintf (stream
, MOTOROLA
?
612 "\t%Omove.l %s,-(%Rsp)\n" :
613 "\tmovel %s,%Rsp@-\n",
614 M68K_REGNAME(15 - i
));
615 if (dwarf2out_do_frame ())
617 char *l
= (char *) dwarf2out_cfi_label ();
620 if (! frame_pointer_needed
)
621 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
622 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
626 else if (current_frame
.reg_rev_mask
)
629 /* The ColdFire does not support the predecrement form of the
630 MOVEM instruction, so we must adjust the stack pointer and
631 then use the plain address register indirect mode.
632 The required register save space was combined earlier with
633 the fsize_with_regs amount. */
635 asm_fprintf (stream
, MOTOROLA
?
636 "\tmovm.l %I0x%x,(%Rsp)\n" :
637 "\tmoveml %I0x%x,%Rsp@\n",
638 current_frame
.reg_mask
);
640 asm_fprintf (stream
, MOTOROLA
?
641 "\tmovm.l %I0x%x,-(%Rsp)\n" :
642 "\tmoveml %I0x%x,%Rsp@-\n",
643 current_frame
.reg_rev_mask
);
644 if (dwarf2out_do_frame ())
646 char *l
= (char *) dwarf2out_cfi_label ();
649 cfa_offset
+= current_frame
.reg_no
* 4;
650 if (! frame_pointer_needed
)
651 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
652 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
653 if (current_frame
.reg_mask
& (1 << regno
))
654 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
657 if (!TARGET_SEP_DATA
&& flag_pic
&&
658 (current_function_uses_pic_offset_table
||
659 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
661 if (TARGET_ID_SHARED_LIBRARY
)
663 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
664 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
665 m68k_library_id_string
,
666 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
671 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
672 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
675 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
676 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
677 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
678 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
),
679 M68K_REGNAME(PIC_OFFSET_TABLE_REGNUM
));
685 /* Return true if this function's epilogue can be output as RTL. */
688 use_return_insn (void)
690 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
693 /* We can output the epilogue as RTL only if no registers need to be
695 m68k_compute_frame_layout();
696 return current_frame
.reg_no
? false : true;
699 /* This function generates the assembly code for function exit,
700 on machines that need it.
702 The function epilogue should not depend on the current stack pointer!
703 It should use the frame pointer only, if there is a frame pointer.
704 This is mandatory because of alloca; we also take advantage of it to
705 omit stack adjustments before returning. */
708 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
710 HOST_WIDE_INT fsize
, fsize_with_regs
;
712 bool restore_from_sp
= false;
713 rtx insn
= get_last_insn ();
715 m68k_compute_frame_layout();
717 /* If the last insn was a BARRIER, we don't have to write any code. */
718 if (GET_CODE (insn
) == NOTE
)
719 insn
= prev_nonnote_insn (insn
);
720 if (insn
&& GET_CODE (insn
) == BARRIER
)
722 /* Output just a no-op so that debuggers don't get confused
723 about which function the pc is in at this address. */
724 fprintf (stream
, "\tnop\n");
728 #ifdef FUNCTION_EXTRA_EPILOGUE
729 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
732 fsize
= current_frame
.size
;
734 /* FIXME : leaf_function_p below is too strong.
735 What we really need to know there is if there could be pending
736 stack adjustment needed at that point. */
737 restore_from_sp
= ! frame_pointer_needed
738 || (! current_function_calls_alloca
&& leaf_function_p ());
740 /* fsize_with_regs is the size we need to adjust the sp when
741 popping the frame. */
742 fsize_with_regs
= fsize
;
744 /* Because the ColdFire doesn't support moveml with
745 complex address modes, we must adjust the stack manually
746 after restoring registers. When the frame pointer isn't used,
747 we can merge movem adjustment into frame unlinking
748 made immediately after it. */
749 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
750 fsize_with_regs
+= current_frame
.reg_no
* 4;
752 if (current_frame
.offset
+ fsize
>= 0x8000
754 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
756 /* Because the ColdFire doesn't support moveml with
757 complex address modes we make an extra correction here. */
759 fsize
+= current_frame
.offset
;
761 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
762 fsize
= 0, big
= true;
764 if (current_frame
.reg_no
<= 2)
766 /* Restore each separately in the same order moveml does.
767 Using two movel instructions instead of a single moveml
768 is about 15% faster for the 68020 and 68030 at no expense
772 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
774 for (i
= 0; i
< 16; i
++)
775 if (current_frame
.reg_mask
& (1 << i
))
780 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
782 M68K_REGNAME(FRAME_POINTER_REGNUM
),
785 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
786 M68K_REGNAME(FRAME_POINTER_REGNUM
),
790 else if (restore_from_sp
)
791 asm_fprintf (stream
, MOTOROLA
?
792 "\t%Omove.l (%Rsp)+,%s\n" :
793 "\tmovel %Rsp@+,%s\n",
798 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
800 M68K_REGNAME(FRAME_POINTER_REGNUM
),
803 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
804 M68K_REGNAME(FRAME_POINTER_REGNUM
),
811 else if (current_frame
.reg_mask
)
813 /* The ColdFire requires special handling due to its limited moveml insn. */
818 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
819 M68K_REGNAME(FRAME_POINTER_REGNUM
));
820 asm_fprintf (stream
, MOTOROLA
?
821 "\tmovm.l (%Ra1),%I0x%x\n" :
822 "\tmoveml %Ra1@,%I0x%x\n",
823 current_frame
.reg_mask
);
825 else if (restore_from_sp
)
826 asm_fprintf (stream
, MOTOROLA
?
827 "\tmovm.l (%Rsp),%I0x%x\n" :
828 "\tmoveml %Rsp@,%I0x%x\n",
829 current_frame
.reg_mask
);
833 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
834 current_frame
.offset
+ fsize
,
835 M68K_REGNAME(FRAME_POINTER_REGNUM
),
836 current_frame
.reg_mask
);
838 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
839 M68K_REGNAME(FRAME_POINTER_REGNUM
),
840 current_frame
.offset
+ fsize
,
841 current_frame
.reg_mask
);
844 else /* !TARGET_COLDFIRE */
849 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
850 current_frame
.offset
+ fsize
,
851 M68K_REGNAME(FRAME_POINTER_REGNUM
),
852 current_frame
.reg_mask
);
854 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
855 M68K_REGNAME(FRAME_POINTER_REGNUM
),
856 current_frame
.offset
+ fsize
,
857 current_frame
.reg_mask
);
859 else if (restore_from_sp
)
861 asm_fprintf (stream
, MOTOROLA
?
862 "\tmovm.l (%Rsp)+,%I0x%x\n" :
863 "\tmoveml %Rsp@+,%I0x%x\n",
864 current_frame
.reg_mask
);
869 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
870 current_frame
.offset
+ fsize
,
871 M68K_REGNAME(FRAME_POINTER_REGNUM
),
872 current_frame
.reg_mask
);
874 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
875 M68K_REGNAME(FRAME_POINTER_REGNUM
),
876 current_frame
.offset
+ fsize
,
877 current_frame
.reg_mask
);
881 if (current_frame
.fpu_rev_mask
)
886 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
887 current_frame
.foffset
+ fsize
,
888 M68K_REGNAME(FRAME_POINTER_REGNUM
),
889 current_frame
.fpu_rev_mask
);
891 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
892 M68K_REGNAME(FRAME_POINTER_REGNUM
),
893 current_frame
.foffset
+ fsize
,
894 current_frame
.fpu_rev_mask
);
896 else if (restore_from_sp
)
899 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
900 current_frame
.fpu_rev_mask
);
902 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
903 current_frame
.fpu_rev_mask
);
908 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
909 current_frame
.foffset
+ fsize
,
910 M68K_REGNAME(FRAME_POINTER_REGNUM
),
911 current_frame
.fpu_rev_mask
);
913 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
914 M68K_REGNAME(FRAME_POINTER_REGNUM
),
915 current_frame
.foffset
+ fsize
,
916 current_frame
.fpu_rev_mask
);
919 if (frame_pointer_needed
)
920 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME(FRAME_POINTER_REGNUM
));
921 else if (fsize_with_regs
)
923 if (fsize_with_regs
<= 8)
925 if (!TARGET_COLDFIRE
)
926 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
929 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
932 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
934 /* On the CPU32 it is faster to use two addqw instructions to
935 add a small integer (8 < N <= 16) to a register. */
936 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
937 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
938 fsize_with_regs
- 8);
940 else if (fsize_with_regs
< 0x8000)
943 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
946 asm_fprintf (stream
, MOTOROLA
?
947 "\tlea (%wd,%Rsp),%Rsp\n" :
948 "\tlea %Rsp@(%wd),%Rsp\n",
952 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
954 if (current_function_calls_eh_return
)
955 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
956 if (m68k_interrupt_function_p (current_function_decl
))
957 fprintf (stream
, "\trte\n");
958 else if (current_function_pops_args
)
959 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
961 fprintf (stream
, "\trts\n");
964 /* Similar to general_operand, but exclude stack_pointer_rtx. */
967 not_sp_operand (rtx op
, enum machine_mode mode
)
969 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
972 /* Return true if X is a valid comparison operator for the dbcc
975 Note it rejects floating point comparison operators.
976 (In the future we could use Fdbcc).
978 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
981 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
983 switch (GET_CODE (x
))
985 case EQ
: case NE
: case GTU
: case LTU
:
989 /* Reject some when CC_NO_OVERFLOW is set. This may be over
991 case GT
: case LT
: case GE
: case LE
:
992 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
998 /* Return nonzero if flags are currently in the 68881 flag register. */
1000 flags_in_68881 (void)
1002 /* We could add support for these in the future */
1003 return cc_status
.flags
& CC_IN_68881
;
1006 /* Output a BSR instruction suitable for PIC code. */
1008 m68k_output_pic_call(rtx dest
)
1012 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1014 /* We output a BSR instruction if we're using -fpic or we're building for
1015 * a target that supports long branches. If we're building -fPIC on the
1016 * 68000, 68010 or ColdFire we generate one of two sequences:
1017 * a shorter one that uses a GOT entry or a longer one that doesn't.
1018 * We'll use the -Os command-line flag to decide which to generate.
1019 * Both sequences take the same time to execute on the ColdFire.
1021 else if (TARGET_PCREL
)
1023 else if ((flag_pic
== 1) || TARGET_68020
)
1024 #if defined(USE_GAS)
1025 out
= "bsr.l %0@PLTPC";
1027 out
= "bsr %0@PLTPC";
1029 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1030 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1032 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1034 output_asm_insn(out
, &dest
);
1037 /* Output a dbCC; jCC sequence. Note we do not handle the
1038 floating point version of this sequence (Fdbcc). We also
1039 do not handle alternative conditions when CC_NO_OVERFLOW is
1040 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1041 kick those out before we get here. */
1044 output_dbcc_and_branch (rtx
*operands
)
1046 switch (GET_CODE (operands
[3]))
1049 output_asm_insn (MOTOROLA
?
1050 "dbeq %0,%l1\n\tjbeq %l2" :
1051 "dbeq %0,%l1\n\tjeq %l2",
1056 output_asm_insn (MOTOROLA
?
1057 "dbne %0,%l1\n\tjbne %l2" :
1058 "dbne %0,%l1\n\tjne %l2",
1063 output_asm_insn (MOTOROLA
?
1064 "dbgt %0,%l1\n\tjbgt %l2" :
1065 "dbgt %0,%l1\n\tjgt %l2",
1070 output_asm_insn (MOTOROLA
?
1071 "dbhi %0,%l1\n\tjbhi %l2" :
1072 "dbhi %0,%l1\n\tjhi %l2",
1077 output_asm_insn (MOTOROLA
?
1078 "dblt %0,%l1\n\tjblt %l2" :
1079 "dblt %0,%l1\n\tjlt %l2",
1084 output_asm_insn (MOTOROLA
?
1085 "dbcs %0,%l1\n\tjbcs %l2" :
1086 "dbcs %0,%l1\n\tjcs %l2",
1091 output_asm_insn (MOTOROLA
?
1092 "dbge %0,%l1\n\tjbge %l2" :
1093 "dbge %0,%l1\n\tjge %l2",
1098 output_asm_insn (MOTOROLA
?
1099 "dbcc %0,%l1\n\tjbcc %l2" :
1100 "dbcc %0,%l1\n\tjcc %l2",
1105 output_asm_insn (MOTOROLA
?
1106 "dble %0,%l1\n\tjble %l2" :
1107 "dble %0,%l1\n\tjle %l2",
1112 output_asm_insn (MOTOROLA
?
1113 "dbls %0,%l1\n\tjbls %l2" :
1114 "dbls %0,%l1\n\tjls %l2",
1122 /* If the decrement is to be done in SImode, then we have
1123 to compensate for the fact that dbcc decrements in HImode. */
1124 switch (GET_MODE (operands
[0]))
1127 output_asm_insn (MOTOROLA
?
1128 "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1" :
1129 "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1142 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1145 enum rtx_code op_code
= GET_CODE (op
);
1147 /* This does not produce a useful cc. */
1150 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1151 below. Swap the operands and change the op if these requirements
1152 are not fulfilled. */
1153 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1157 operand1
= operand2
;
1159 op_code
= swap_condition (op_code
);
1161 loperands
[0] = operand1
;
1162 if (GET_CODE (operand1
) == REG
)
1163 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1165 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1166 if (operand2
!= const0_rtx
)
1168 loperands
[2] = operand2
;
1169 if (GET_CODE (operand2
) == REG
)
1170 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1172 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1174 loperands
[4] = gen_label_rtx();
1175 if (operand2
!= const0_rtx
)
1177 output_asm_insn (MOTOROLA
?
1178 "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1" :
1179 "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1184 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1185 output_asm_insn ("tst%.l %0", loperands
);
1188 output_asm_insn ("cmp%.w #0,%0", loperands
);
1191 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1193 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1194 output_asm_insn ("tst%.l %1", loperands
);
1196 output_asm_insn ("cmp%.w #0,%1", loperands
);
1199 loperands
[5] = dest
;
1204 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1205 CODE_LABEL_NUMBER (loperands
[4]));
1206 output_asm_insn ("seq %5", loperands
);
1210 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1211 CODE_LABEL_NUMBER (loperands
[4]));
1212 output_asm_insn ("sne %5", loperands
);
1216 loperands
[6] = gen_label_rtx();
1217 output_asm_insn (MOTOROLA
?
1218 "shi %5\n\tjbra %l6" :
1219 "shi %5\n\tjra %l6",
1221 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1222 CODE_LABEL_NUMBER (loperands
[4]));
1223 output_asm_insn ("sgt %5", loperands
);
1224 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1225 CODE_LABEL_NUMBER (loperands
[6]));
1229 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1230 CODE_LABEL_NUMBER (loperands
[4]));
1231 output_asm_insn ("shi %5", loperands
);
1235 loperands
[6] = gen_label_rtx();
1236 output_asm_insn (MOTOROLA
?
1237 "scs %5\n\tjbra %l6" :
1238 "scs %5\n\tjra %l6",
1240 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1241 CODE_LABEL_NUMBER (loperands
[4]));
1242 output_asm_insn ("slt %5", loperands
);
1243 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1244 CODE_LABEL_NUMBER (loperands
[6]));
1248 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1249 CODE_LABEL_NUMBER (loperands
[4]));
1250 output_asm_insn ("scs %5", loperands
);
1254 loperands
[6] = gen_label_rtx();
1255 output_asm_insn (MOTOROLA
?
1256 "scc %5\n\tjbra %l6" :
1257 "scc %5\n\tjra %l6",
1259 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1260 CODE_LABEL_NUMBER (loperands
[4]));
1261 output_asm_insn ("sge %5", loperands
);
1262 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1263 CODE_LABEL_NUMBER (loperands
[6]));
1267 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1268 CODE_LABEL_NUMBER (loperands
[4]));
1269 output_asm_insn ("scc %5", loperands
);
1273 loperands
[6] = gen_label_rtx();
1274 output_asm_insn (MOTOROLA
?
1275 "sls %5\n\tjbra %l6" :
1276 "sls %5\n\tjra %l6",
1278 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1279 CODE_LABEL_NUMBER (loperands
[4]));
1280 output_asm_insn ("sle %5", loperands
);
1281 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1282 CODE_LABEL_NUMBER (loperands
[6]));
1286 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1287 CODE_LABEL_NUMBER (loperands
[4]));
1288 output_asm_insn ("sls %5", loperands
);
1298 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1300 operands
[0] = countop
;
1301 operands
[1] = dataop
;
1303 if (GET_CODE (countop
) == CONST_INT
)
1305 register int count
= INTVAL (countop
);
1306 /* If COUNT is bigger than size of storage unit in use,
1307 advance to the containing unit of same size. */
1308 if (count
> signpos
)
1310 int offset
= (count
& ~signpos
) / 8;
1311 count
= count
& signpos
;
1312 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1314 if (count
== signpos
)
1315 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1317 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1319 /* These three statements used to use next_insns_test_no...
1320 but it appears that this should do the same job. */
1322 && next_insn_tests_no_inequality (insn
))
1325 && next_insn_tests_no_inequality (insn
))
1328 && next_insn_tests_no_inequality (insn
))
1331 cc_status
.flags
= CC_NOT_NEGATIVE
;
1333 return "btst %0,%1";
1336 /* Returns true if OP is either a symbol reference or a sum of a symbol
1337 reference and a constant. */
1340 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1342 switch (GET_CODE (op
))
1350 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1351 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1352 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1354 #if 0 /* Deleted, with corresponding change in m68k.h,
1355 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1357 return GET_MODE (op
) == mode
;
1365 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1368 extend_operator(rtx x
, enum machine_mode mode
)
1370 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1372 switch (GET_CODE(x
))
1383 /* Legitimize PIC addresses. If the address is already
1384 position-independent, we return ORIG. Newly generated
1385 position-independent addresses go to REG. If we need more
1386 than one register, we lose.
1388 An address is legitimized by making an indirect reference
1389 through the Global Offset Table with the name of the symbol
1392 The assembler and linker are responsible for placing the
1393 address of the symbol in the GOT. The function prologue
1394 is responsible for initializing a5 to the starting address
1397 The assembler is also responsible for translating a symbol name
1398 into a constant displacement from the start of the GOT.
1400 A quick example may make things a little clearer:
1402 When not generating PIC code to store the value 12345 into _foo
1403 we would generate the following code:
1407 When generating PIC two transformations are made. First, the compiler
1408 loads the address of foo into a register. So the first transformation makes:
1413 The code in movsi will intercept the lea instruction and call this
1414 routine which will transform the instructions into:
1416 movel a5@(_foo:w), a0
1420 That (in a nutshell) is how *all* symbol and label references are
1424 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1429 /* First handle a simple SYMBOL_REF or LABEL_REF */
1430 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1435 pic_ref
= gen_rtx_MEM (Pmode
,
1436 gen_rtx_PLUS (Pmode
,
1437 pic_offset_table_rtx
, orig
));
1438 current_function_uses_pic_offset_table
= 1;
1439 RTX_UNCHANGING_P (pic_ref
) = 1;
1440 emit_move_insn (reg
, pic_ref
);
1443 else if (GET_CODE (orig
) == CONST
)
1447 /* Make sure this has not already been legitimized. */
1448 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1449 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1455 /* legitimize both operands of the PLUS */
1456 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1458 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1459 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1460 base
== reg
? 0 : reg
);
1464 if (GET_CODE (orig
) == CONST_INT
)
1465 return plus_constant (base
, INTVAL (orig
));
1466 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1467 /* Likewise, should we set special REG_NOTEs here? */
1473 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1475 static CONST_METHOD
const_method (rtx
);
1477 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1480 const_method (rtx constant
)
1485 i
= INTVAL (constant
);
1489 /* The ColdFire doesn't have byte or word operations. */
1490 /* FIXME: This may not be useful for the m68060 either. */
1491 if (!TARGET_COLDFIRE
)
1493 /* if -256 < N < 256 but N is not in range for a moveq
1494 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1495 if (USE_MOVQ (i
^ 0xff))
1497 /* Likewise, try with not.w */
1498 if (USE_MOVQ (i
^ 0xffff))
1500 /* This is the only value where neg.w is useful */
1503 /* Try also with swap */
1505 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1508 /* Otherwise, use move.l */
1513 const_int_cost (rtx constant
)
1515 switch (const_method (constant
))
1518 /* Constants between -128 and 127 are cheap due to moveq */
1524 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1534 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1539 /* Constant zero is super cheap due to clr instruction. */
1540 if (x
== const0_rtx
)
1543 *total
= const_int_cost (x
);
1553 /* Make 0.0 cheaper than other floating constants to
1554 encourage creating tstsf and tstdf insns. */
1555 if (outer_code
== COMPARE
1556 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1562 /* These are vaguely right for a 68020. */
1563 /* The costs for long multiply have been adjusted to work properly
1564 in synth_mult on the 68020, relative to an average of the time
1565 for add and the time for shift, taking away a little more because
1566 sometimes move insns are needed. */
1567 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1568 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1569 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1570 TARGET_CFV3 ? 2 : 5)
1571 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1574 /* An lea costs about three times as much as a simple add. */
1575 if (GET_MODE (x
) == SImode
1576 && GET_CODE (XEXP (x
, 1)) == REG
1577 && GET_CODE (XEXP (x
, 0)) == MULT
1578 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1579 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1580 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1581 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1582 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1584 /* lea an@(dx:l:i),am */
1585 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1595 *total
= COSTS_N_INSNS(1);
1598 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1600 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1602 if (INTVAL (XEXP (x
, 1)) < 16)
1603 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1605 /* We're using clrw + swap for these cases. */
1606 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1609 *total
= COSTS_N_INSNS (10); /* worst case */
1612 /* A shift by a big integer takes an extra instruction. */
1613 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1614 && (INTVAL (XEXP (x
, 1)) == 16))
1616 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1619 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1620 && !(INTVAL (XEXP (x
, 1)) > 0
1621 && INTVAL (XEXP (x
, 1)) <= 8))
1623 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1629 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1630 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1631 && GET_MODE (x
) == SImode
)
1632 *total
= COSTS_N_INSNS (MULW_COST
);
1633 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1634 *total
= COSTS_N_INSNS (MULW_COST
);
1636 *total
= COSTS_N_INSNS (MULL_COST
);
1643 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1644 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1645 else if (TARGET_CF_HWDIV
)
1646 *total
= COSTS_N_INSNS (18);
1648 *total
= COSTS_N_INSNS (43); /* div.l */
1657 output_move_const_into_data_reg (rtx
*operands
)
1661 i
= INTVAL (operands
[1]);
1662 switch (const_method (operands
[1]))
1665 return "moveq %1,%0";
1668 operands
[1] = GEN_INT (i
^ 0xff);
1669 return "moveq %1,%0\n\tnot%.b %0";
1672 operands
[1] = GEN_INT (i
^ 0xffff);
1673 return "moveq %1,%0\n\tnot%.w %0";
1676 return "moveq #-128,%0\n\tneg%.w %0";
1681 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1682 return "moveq %1,%0\n\tswap %0";
1685 return "move%.l %1,%0";
1692 output_move_simode_const (rtx
*operands
)
1694 if (operands
[1] == const0_rtx
1695 && (DATA_REG_P (operands
[0])
1696 || GET_CODE (operands
[0]) == MEM
)
1697 /* clr insns on 68000 read before writing.
1698 This isn't so on the 68010, but we have no TARGET_68010. */
1699 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1700 || !(GET_CODE (operands
[0]) == MEM
1701 && MEM_VOLATILE_P (operands
[0]))))
1703 else if (operands
[1] == const0_rtx
1704 && ADDRESS_REG_P (operands
[0]))
1705 return "sub%.l %0,%0";
1706 else if (DATA_REG_P (operands
[0]))
1707 return output_move_const_into_data_reg (operands
);
1708 else if (ADDRESS_REG_P (operands
[0])
1709 && INTVAL (operands
[1]) < 0x8000
1710 && INTVAL (operands
[1]) >= -0x8000)
1711 return "move%.w %1,%0";
1712 else if (GET_CODE (operands
[0]) == MEM
1713 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1714 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1715 && INTVAL (operands
[1]) < 0x8000
1716 && INTVAL (operands
[1]) >= -0x8000)
1718 return "move%.l %1,%0";
1722 output_move_simode (rtx
*operands
)
1724 if (GET_CODE (operands
[1]) == CONST_INT
)
1725 return output_move_simode_const (operands
);
1726 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1727 || GET_CODE (operands
[1]) == CONST
)
1728 && push_operand (operands
[0], SImode
))
1730 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1731 || GET_CODE (operands
[1]) == CONST
)
1732 && ADDRESS_REG_P (operands
[0]))
1733 return "lea %a1,%0";
1734 return "move%.l %1,%0";
1738 output_move_himode (rtx
*operands
)
1740 if (GET_CODE (operands
[1]) == CONST_INT
)
1742 if (operands
[1] == const0_rtx
1743 && (DATA_REG_P (operands
[0])
1744 || GET_CODE (operands
[0]) == MEM
)
1745 /* clr insns on 68000 read before writing.
1746 This isn't so on the 68010, but we have no TARGET_68010. */
1747 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1748 || !(GET_CODE (operands
[0]) == MEM
1749 && MEM_VOLATILE_P (operands
[0]))))
1751 else if (operands
[1] == const0_rtx
1752 && ADDRESS_REG_P (operands
[0]))
1753 return "sub%.l %0,%0";
1754 else if (DATA_REG_P (operands
[0])
1755 && INTVAL (operands
[1]) < 128
1756 && INTVAL (operands
[1]) >= -128)
1758 return "moveq %1,%0";
1760 else if (INTVAL (operands
[1]) < 0x8000
1761 && INTVAL (operands
[1]) >= -0x8000)
1762 return "move%.w %1,%0";
1764 else if (CONSTANT_P (operands
[1]))
1765 return "move%.l %1,%0";
1766 /* Recognize the insn before a tablejump, one that refers
1767 to a table of offsets. Such an insn will need to refer
1768 to a label on the insn. So output one. Use the label-number
1769 of the table of offsets to generate this label. This code,
1770 and similar code below, assumes that there will be at most one
1771 reference to each table. */
1772 if (GET_CODE (operands
[1]) == MEM
1773 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1774 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1775 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1777 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1779 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1780 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1782 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1783 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1785 return "move%.w %1,%0";
1789 output_move_qimode (rtx
*operands
)
1793 /* This is probably useless, since it loses for pushing a struct
1794 of several bytes a byte at a time. */
1795 /* 68k family always modifies the stack pointer by at least 2, even for
1796 byte pushes. The 5200 (ColdFire) does not do this. */
1797 if (GET_CODE (operands
[0]) == MEM
1798 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1799 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1800 && ! ADDRESS_REG_P (operands
[1])
1801 && ! TARGET_COLDFIRE
)
1803 xoperands
[1] = operands
[1];
1805 = gen_rtx_MEM (QImode
,
1806 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1807 /* Just pushing a byte puts it in the high byte of the halfword. */
1808 /* We must put it in the low-order, high-numbered byte. */
1809 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1811 xoperands
[3] = stack_pointer_rtx
;
1812 output_asm_insn ("subq%.l #2,%3\n\tmove%.b %1,%2", xoperands
);
1815 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1819 /* clr and st insns on 68000 read before writing.
1820 This isn't so on the 68010, but we have no TARGET_68010. */
1821 if (!ADDRESS_REG_P (operands
[0])
1822 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1823 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1825 if (operands
[1] == const0_rtx
)
1827 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1828 && GET_CODE (operands
[1]) == CONST_INT
1829 && (INTVAL (operands
[1]) & 255) == 255)
1835 if (GET_CODE (operands
[1]) == CONST_INT
1836 && DATA_REG_P (operands
[0])
1837 && INTVAL (operands
[1]) < 128
1838 && INTVAL (operands
[1]) >= -128)
1840 return "moveq %1,%0";
1842 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1843 return "sub%.l %0,%0";
1844 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1845 return "move%.l %1,%0";
1846 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1847 from address registers. */
1848 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1849 return "move%.w %1,%0";
1850 return "move%.b %1,%0";
1854 output_move_stricthi (rtx
*operands
)
1856 if (operands
[1] == const0_rtx
1857 /* clr insns on 68000 read before writing.
1858 This isn't so on the 68010, but we have no TARGET_68010. */
1859 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1860 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1862 return "move%.w %1,%0";
1866 output_move_strictqi (rtx
*operands
)
1868 if (operands
[1] == const0_rtx
1869 /* clr insns on 68000 read before writing.
1870 This isn't so on the 68010, but we have no TARGET_68010. */
1871 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1872 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1874 return "move%.b %1,%0";
1877 /* Return the best assembler insn template
1878 for moving operands[1] into operands[0] as a fullword. */
1881 singlemove_string (rtx
*operands
)
1883 if (GET_CODE (operands
[1]) == CONST_INT
)
1884 return output_move_simode_const (operands
);
1885 return "move%.l %1,%0";
1889 /* Output assembler code to perform a doubleword move insn
1890 with operands OPERANDS. */
1893 output_move_double (rtx
*operands
)
1897 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1902 rtx addreg0
= 0, addreg1
= 0;
1903 int dest_overlapped_low
= 0;
1904 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1909 /* First classify both operands. */
1911 if (REG_P (operands
[0]))
1913 else if (offsettable_memref_p (operands
[0]))
1915 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1917 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1919 else if (GET_CODE (operands
[0]) == MEM
)
1924 if (REG_P (operands
[1]))
1926 else if (CONSTANT_P (operands
[1]))
1928 else if (offsettable_memref_p (operands
[1]))
1930 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1932 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1934 else if (GET_CODE (operands
[1]) == MEM
)
1939 /* Check for the cases that the operand constraints are not
1940 supposed to allow to happen. Abort if we get one,
1941 because generating code for these cases is painful. */
1943 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1946 /* If one operand is decrementing and one is incrementing
1947 decrement the former register explicitly
1948 and change that operand into ordinary indexing. */
1950 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1952 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1954 output_asm_insn ("sub%.l #12,%0", operands
);
1956 output_asm_insn ("subq%.l #8,%0", operands
);
1957 if (GET_MODE (operands
[1]) == XFmode
)
1958 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1959 else if (GET_MODE (operands
[0]) == DFmode
)
1960 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1962 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1965 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1967 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1969 output_asm_insn ("sub%.l #12,%1", operands
);
1971 output_asm_insn ("subq%.l #8,%1", operands
);
1972 if (GET_MODE (operands
[1]) == XFmode
)
1973 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1974 else if (GET_MODE (operands
[1]) == DFmode
)
1975 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1977 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1981 /* If an operand is an unoffsettable memory ref, find a register
1982 we can increment temporarily to make it refer to the second word. */
1984 if (optype0
== MEMOP
)
1985 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1987 if (optype1
== MEMOP
)
1988 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1990 /* Ok, we can do one word at a time.
1991 Normally we do the low-numbered word first,
1992 but if either operand is autodecrementing then we
1993 do the high-numbered word first.
1995 In either case, set up in LATEHALF the operands to use
1996 for the high-numbered word and in some cases alter the
1997 operands in OPERANDS to be suitable for the low-numbered word. */
2001 if (optype0
== REGOP
)
2003 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2004 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2006 else if (optype0
== OFFSOP
)
2008 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2009 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2013 middlehalf
[0] = operands
[0];
2014 latehalf
[0] = operands
[0];
2017 if (optype1
== REGOP
)
2019 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2020 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2022 else if (optype1
== OFFSOP
)
2024 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2025 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2027 else if (optype1
== CNSTOP
)
2029 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2034 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2035 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2036 operands
[1] = GEN_INT (l
[0]);
2037 middlehalf
[1] = GEN_INT (l
[1]);
2038 latehalf
[1] = GEN_INT (l
[2]);
2040 else if (CONSTANT_P (operands
[1]))
2042 /* actually, no non-CONST_DOUBLE constant should ever
2045 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2046 latehalf
[1] = constm1_rtx
;
2048 latehalf
[1] = const0_rtx
;
2053 middlehalf
[1] = operands
[1];
2054 latehalf
[1] = operands
[1];
2058 /* size is not 12: */
2060 if (optype0
== REGOP
)
2061 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2062 else if (optype0
== OFFSOP
)
2063 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2065 latehalf
[0] = operands
[0];
2067 if (optype1
== REGOP
)
2068 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2069 else if (optype1
== OFFSOP
)
2070 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2071 else if (optype1
== CNSTOP
)
2072 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2074 latehalf
[1] = operands
[1];
2077 /* If insn is effectively movd N(sp),-(sp) then we will do the
2078 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2079 for the low word as well, to compensate for the first decrement of sp. */
2080 if (optype0
== PUSHOP
2081 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2082 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2083 operands
[1] = middlehalf
[1] = latehalf
[1];
2085 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2086 if the upper part of reg N does not appear in the MEM, arrange to
2087 emit the move late-half first. Otherwise, compute the MEM address
2088 into the upper part of N and use that as a pointer to the memory
2090 if (optype0
== REGOP
2091 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2093 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2095 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2096 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2098 /* If both halves of dest are used in the src memory address,
2099 compute the address into latehalf of dest.
2100 Note that this can't happen if the dest is two data regs. */
2102 xops
[0] = latehalf
[0];
2103 xops
[1] = XEXP (operands
[1], 0);
2104 output_asm_insn ("lea %a1,%0", xops
);
2105 if (GET_MODE (operands
[1]) == XFmode
)
2107 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2108 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2109 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2113 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2114 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2118 && reg_overlap_mentioned_p (middlehalf
[0],
2119 XEXP (operands
[1], 0)))
2121 /* Check for two regs used by both source and dest.
2122 Note that this can't happen if the dest is all data regs.
2123 It can happen if the dest is d6, d7, a0.
2124 But in that case, latehalf is an addr reg, so
2125 the code at compadr does ok. */
2127 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2128 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2131 /* JRV says this can't happen: */
2132 if (addreg0
|| addreg1
)
2135 /* Only the middle reg conflicts; simply put it last. */
2136 output_asm_insn (singlemove_string (operands
), operands
);
2137 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2138 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2141 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2142 /* If the low half of dest is mentioned in the source memory
2143 address, the arrange to emit the move late half first. */
2144 dest_overlapped_low
= 1;
2147 /* If one or both operands autodecrementing,
2148 do the two words, high-numbered first. */
2150 /* Likewise, the first move would clobber the source of the second one,
2151 do them in the other order. This happens only for registers;
2152 such overlap can't happen in memory unless the user explicitly
2153 sets it up, and that is an undefined circumstance. */
2155 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2156 || (optype0
== REGOP
&& optype1
== REGOP
2157 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2158 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2159 || dest_overlapped_low
)
2161 /* Make any unoffsettable addresses point at high-numbered word. */
2165 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2167 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2172 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2174 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2178 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2180 /* Undo the adds we just did. */
2182 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2184 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2188 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2190 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2192 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2195 /* Do low-numbered word. */
2196 return singlemove_string (operands
);
2199 /* Normal case: do the two words, low-numbered first. */
2201 output_asm_insn (singlemove_string (operands
), operands
);
2203 /* Do the middle one of the three words for long double */
2207 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2209 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2211 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2214 /* Make any unoffsettable addresses point at high-numbered word. */
2216 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2218 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2221 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2223 /* Undo the adds we just did. */
2227 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2229 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2234 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2236 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2242 /* Return a REG that occurs in ADDR with coefficient 1.
2243 ADDR can be effectively incremented by incrementing REG. */
2246 find_addr_reg (rtx addr
)
2248 while (GET_CODE (addr
) == PLUS
)
2250 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2251 addr
= XEXP (addr
, 0);
2252 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2253 addr
= XEXP (addr
, 1);
2254 else if (CONSTANT_P (XEXP (addr
, 0)))
2255 addr
= XEXP (addr
, 1);
2256 else if (CONSTANT_P (XEXP (addr
, 1)))
2257 addr
= XEXP (addr
, 0);
2261 if (GET_CODE (addr
) == REG
)
2266 /* Output assembler code to perform a 32-bit 3-operand add. */
2269 output_addsi3 (rtx
*operands
)
2271 if (! operands_match_p (operands
[0], operands
[1]))
2273 if (!ADDRESS_REG_P (operands
[1]))
2275 rtx tmp
= operands
[1];
2277 operands
[1] = operands
[2];
2281 /* These insns can result from reloads to access
2282 stack slots over 64k from the frame pointer. */
2283 if (GET_CODE (operands
[2]) == CONST_INT
2284 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2285 return "move%.l %2,%0\n\tadd%.l %1,%0";
2286 if (GET_CODE (operands
[2]) == REG
)
2287 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2288 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2290 if (GET_CODE (operands
[2]) == CONST_INT
)
2292 if (INTVAL (operands
[2]) > 0
2293 && INTVAL (operands
[2]) <= 8)
2294 return "addq%.l %2,%0";
2295 if (INTVAL (operands
[2]) < 0
2296 && INTVAL (operands
[2]) >= -8)
2298 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2299 return "subq%.l %2,%0";
2301 /* On the CPU32 it is faster to use two addql instructions to
2302 add a small integer (8 < N <= 16) to a register.
2303 Likewise for subql. */
2304 if (TARGET_CPU32
&& REG_P (operands
[0]))
2306 if (INTVAL (operands
[2]) > 8
2307 && INTVAL (operands
[2]) <= 16)
2309 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2310 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2312 if (INTVAL (operands
[2]) < -8
2313 && INTVAL (operands
[2]) >= -16)
2315 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2316 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2319 if (ADDRESS_REG_P (operands
[0])
2320 && INTVAL (operands
[2]) >= -0x8000
2321 && INTVAL (operands
[2]) < 0x8000)
2324 return "add%.w %2,%0";
2326 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2329 return "add%.l %2,%0";
2332 /* Store in cc_status the expressions that the condition codes will
2333 describe after execution of an instruction whose pattern is EXP.
2334 Do not alter them if the instruction would not alter the cc's. */
2336 /* On the 68000, all the insns to store in an address register fail to
2337 set the cc's. However, in some cases these instructions can make it
2338 possibly invalid to use the saved cc's. In those cases we clear out
2339 some or all of the saved cc's so they won't be used. */
2342 notice_update_cc (rtx exp
, rtx insn
)
2344 if (GET_CODE (exp
) == SET
)
2346 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2350 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2352 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2353 cc_status
.value1
= 0;
2354 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2355 cc_status
.value2
= 0;
2357 else if (!FP_REG_P (SET_DEST (exp
))
2358 && SET_DEST (exp
) != cc0_rtx
2359 && (FP_REG_P (SET_SRC (exp
))
2360 || GET_CODE (SET_SRC (exp
)) == FIX
2361 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2362 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2366 /* A pair of move insns doesn't produce a useful overall cc. */
2367 else if (!FP_REG_P (SET_DEST (exp
))
2368 && !FP_REG_P (SET_SRC (exp
))
2369 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2370 && (GET_CODE (SET_SRC (exp
)) == REG
2371 || GET_CODE (SET_SRC (exp
)) == MEM
2372 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2376 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2380 else if (XEXP (exp
, 0) != pc_rtx
)
2382 cc_status
.flags
= 0;
2383 cc_status
.value1
= XEXP (exp
, 0);
2384 cc_status
.value2
= XEXP (exp
, 1);
2387 else if (GET_CODE (exp
) == PARALLEL
2388 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2390 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2392 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2394 cc_status
.flags
= 0;
2395 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2396 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2401 if (cc_status
.value2
!= 0
2402 && ADDRESS_REG_P (cc_status
.value2
)
2403 && GET_MODE (cc_status
.value2
) == QImode
)
2405 if (cc_status
.value2
!= 0)
2406 switch (GET_CODE (cc_status
.value2
))
2408 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2409 case ROTATE
: case ROTATERT
:
2410 /* These instructions always clear the overflow bit, and set
2411 the carry to the bit shifted out. */
2412 /* ??? We don't currently have a way to signal carry not valid,
2413 nor do we check for it in the branch insns. */
2417 case PLUS
: case MINUS
: case MULT
:
2418 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2419 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2420 cc_status
.flags
|= CC_NO_OVERFLOW
;
2423 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2424 ends with a move insn moving r2 in r2's mode.
2425 Thus, the cc's are set for r2.
2426 This can set N bit spuriously. */
2427 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2432 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2434 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2435 cc_status
.value2
= 0;
2436 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2437 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2438 cc_status
.flags
= CC_IN_68881
;
2442 output_move_const_double (rtx
*operands
)
2444 int code
= standard_68881_constant_p (operands
[1]);
2448 static char buf
[40];
2450 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2453 return "fmove%.d %1,%0";
2457 output_move_const_single (rtx
*operands
)
2459 int code
= standard_68881_constant_p (operands
[1]);
2463 static char buf
[40];
2465 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2468 return "fmove%.s %f1,%0";
2471 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2472 from the "fmovecr" instruction.
2473 The value, anded with 0xff, gives the code to use in fmovecr
2474 to get the desired constant. */
2476 /* This code has been fixed for cross-compilation. */
2478 static int inited_68881_table
= 0;
2480 static const char *const strings_68881
[7] = {
2490 static const int codes_68881
[7] = {
2500 REAL_VALUE_TYPE values_68881
[7];
2502 /* Set up values_68881 array by converting the decimal values
2503 strings_68881 to binary. */
2506 init_68881_table (void)
2510 enum machine_mode mode
;
2513 for (i
= 0; i
< 7; i
++)
2517 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2518 values_68881
[i
] = r
;
2520 inited_68881_table
= 1;
2524 standard_68881_constant_p (rtx x
)
2529 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2530 used at all on those chips. */
2531 if (TARGET_68040
|| TARGET_68060
)
2534 if (! inited_68881_table
)
2535 init_68881_table ();
2537 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2539 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2541 for (i
= 0; i
< 6; i
++)
2543 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2544 return (codes_68881
[i
]);
2547 if (GET_MODE (x
) == SFmode
)
2550 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2551 return (codes_68881
[6]);
2553 /* larger powers of ten in the constants ram are not used
2554 because they are not equal to a `double' C constant. */
2558 /* If X is a floating-point constant, return the logarithm of X base 2,
2559 or 0 if X is not a power of 2. */
2562 floating_exact_log2 (rtx x
)
2564 REAL_VALUE_TYPE r
, r1
;
2567 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2569 if (REAL_VALUES_LESS (r
, dconst1
))
2572 exp
= real_exponent (&r
);
2573 real_2expN (&r1
, exp
);
2574 if (REAL_VALUES_EQUAL (r1
, r
))
2580 /* A C compound statement to output to stdio stream STREAM the
2581 assembler syntax for an instruction operand X. X is an RTL
2584 CODE is a value that can be used to specify one of several ways
2585 of printing the operand. It is used when identical operands
2586 must be printed differently depending on the context. CODE
2587 comes from the `%' specification that was used to request
2588 printing of the operand. If the specification was just `%DIGIT'
2589 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2590 is the ASCII code for LTR.
2592 If X is a register, this macro should print the register's name.
2593 The names can be found in an array `reg_names' whose type is
2594 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2596 When the machine description has a specification `%PUNCT' (a `%'
2597 followed by a punctuation character), this macro is called with
2598 a null pointer for X and the punctuation character for CODE.
2600 The m68k specific codes are:
2602 '.' for dot needed in Motorola-style opcode names.
2603 '-' for an operand pushing on the stack:
2604 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2605 '+' for an operand pushing on the stack:
2606 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2607 '@' for a reference to the top word on the stack:
2608 sp@, (sp) or (%sp) depending on the style of syntax.
2609 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2610 but & in SGS syntax).
2611 '!' for the cc register (used in an `and to cc' insn).
2612 '$' for the letter `s' in an op code, but only on the 68040.
2613 '&' for the letter `d' in an op code, but only on the 68040.
2614 '/' for register prefix needed by longlong.h.
2616 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2617 'd' to force memory addressing to be absolute, not relative.
2618 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2619 'o' for operands to go directly to output_operand_address (bypassing
2620 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2621 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2622 or print pair of registers as rx:ry.
2627 print_operand (FILE *file
, rtx op
, int letter
)
2632 fprintf (file
, ".");
2634 else if (letter
== '#')
2635 asm_fprintf (file
, "%I");
2636 else if (letter
== '-')
2637 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2638 else if (letter
== '+')
2639 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2640 else if (letter
== '@')
2641 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2642 else if (letter
== '!')
2643 asm_fprintf (file
, "%Rfpcr");
2644 else if (letter
== '$')
2646 if (TARGET_68040_ONLY
)
2647 fprintf (file
, "s");
2649 else if (letter
== '&')
2651 if (TARGET_68040_ONLY
)
2652 fprintf (file
, "d");
2654 else if (letter
== '/')
2655 asm_fprintf (file
, "%R");
2656 else if (letter
== 'o')
2658 /* This is only for direct addresses with TARGET_PCREL */
2659 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2662 output_addr_const (file
, XEXP (op
, 0));
2664 else if (GET_CODE (op
) == REG
)
2667 /* Print out the second register name of a register pair.
2668 I.e., R (6) => 7. */
2669 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2671 fputs (M68K_REGNAME(REGNO (op
)), file
);
2673 else if (GET_CODE (op
) == MEM
)
2675 output_address (XEXP (op
, 0));
2676 if (letter
== 'd' && ! TARGET_68020
2677 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2678 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2679 && INTVAL (XEXP (op
, 0)) < 0x8000
2680 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2681 fprintf (file
, MOTOROLA
? ".l" : ":l");
2683 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2686 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2687 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2689 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2692 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2693 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2695 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2698 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2699 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2703 /* Use `print_operand_address' instead of `output_addr_const'
2704 to ensure that we print relevant PIC stuff. */
2705 asm_fprintf (file
, "%I");
2707 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2708 print_operand_address (file
, op
);
2710 output_addr_const (file
, op
);
2715 /* A C compound statement to output to stdio stream STREAM the
2716 assembler syntax for an instruction operand that is a memory
2717 reference whose address is ADDR. ADDR is an RTL expression.
2719 Note that this contains a kludge that knows that the only reason
2720 we have an address (plus (label_ref...) (reg...)) when not generating
2721 PIC code is in the insn before a tablejump, and we know that m68k.md
2722 generates a label LInnn: on such an insn.
2724 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2725 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2727 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2728 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2729 we want. This difference can be accommodated by using an assembler
2730 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2731 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2732 macro. See m68k/sgs.h for an example; for versions without the bug.
2733 Some assemblers refuse all the above solutions. The workaround is to
2734 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2737 They also do not like things like "pea 1.w", so we simple leave off
2738 the .w on small constants.
2740 This routine is responsible for distinguishing between -fpic and -fPIC
2741 style relocations in an address. When generating -fpic code the
2742 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2743 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2746 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2747 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2748 #else /* !MOTOROLA */
2749 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2750 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2751 #endif /* !MOTOROLA */
2754 print_operand_address (FILE *file
, rtx addr
)
2756 register rtx reg1
, reg2
, breg
, ireg
;
2759 switch (GET_CODE (addr
))
2762 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME(REGNO (addr
)));
2765 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2766 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2769 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2770 M68K_REGNAME(REGNO (XEXP (addr
, 0))));
2773 reg1
= reg2
= ireg
= breg
= offset
= 0;
2774 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2776 offset
= XEXP (addr
, 0);
2777 addr
= XEXP (addr
, 1);
2779 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2781 offset
= XEXP (addr
, 1);
2782 addr
= XEXP (addr
, 0);
2784 if (GET_CODE (addr
) != PLUS
)
2788 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2790 reg1
= XEXP (addr
, 0);
2791 addr
= XEXP (addr
, 1);
2793 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2795 reg1
= XEXP (addr
, 1);
2796 addr
= XEXP (addr
, 0);
2798 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2800 reg1
= XEXP (addr
, 0);
2801 addr
= XEXP (addr
, 1);
2803 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2805 reg1
= XEXP (addr
, 1);
2806 addr
= XEXP (addr
, 0);
2808 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2810 reg1
= XEXP (addr
, 0);
2811 addr
= XEXP (addr
, 1);
2813 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2815 reg1
= XEXP (addr
, 1);
2816 addr
= XEXP (addr
, 0);
2818 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2819 || GET_CODE (addr
) == SIGN_EXTEND
)
2831 #if 0 /* for OLD_INDEXING */
2832 else if (GET_CODE (addr
) == PLUS
)
2834 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2836 reg2
= XEXP (addr
, 0);
2837 addr
= XEXP (addr
, 1);
2839 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2841 reg2
= XEXP (addr
, 1);
2842 addr
= XEXP (addr
, 0);
2854 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2855 || GET_CODE (reg1
) == MULT
))
2856 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2861 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2866 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2867 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2870 if (GET_CODE (ireg
) == MULT
)
2872 scale
= INTVAL (XEXP (ireg
, 1));
2873 ireg
= XEXP (ireg
, 0);
2875 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2877 ASM_OUTPUT_CASE_FETCH (file
,
2878 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2879 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2880 fprintf (file
, "w");
2884 ASM_OUTPUT_CASE_FETCH (file
,
2885 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2886 M68K_REGNAME(REGNO (ireg
)));
2887 fprintf (file
, "l");
2890 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2894 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2895 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2897 ASM_OUTPUT_CASE_FETCH (file
,
2898 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2899 M68K_REGNAME(REGNO (breg
)));
2900 fprintf (file
, "l)");
2903 if (ireg
!= 0 || breg
!= 0)
2910 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2918 output_addr_const (file
, addr
);
2919 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2921 fprintf (file
, "@GOT");
2923 fprintf (file
, ".w");
2926 fprintf (file
, "(%s", M68K_REGNAME(REGNO (breg
)));
2930 else /* !MOTOROLA */
2932 fprintf (file
, "%s@(", M68K_REGNAME(REGNO (breg
)));
2935 output_addr_const (file
, addr
);
2936 if (breg
== pic_offset_table_rtx
)
2940 fprintf (file
, ":w"); break;
2942 fprintf (file
, ":l"); break;
2950 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2952 scale
= INTVAL (XEXP (ireg
, 1));
2953 ireg
= XEXP (ireg
, 0);
2955 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2956 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
2957 M68K_REGNAME(REGNO (XEXP (ireg
, 0))));
2959 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
2960 M68K_REGNAME(REGNO (ireg
)));
2962 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2966 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2967 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2969 ASM_OUTPUT_CASE_FETCH (file
,
2970 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2971 M68K_REGNAME(REGNO (reg1
)));
2972 fprintf (file
, "l)");
2975 /* FALL-THROUGH (is this really what we want?) */
2977 if (GET_CODE (addr
) == CONST_INT
2978 && INTVAL (addr
) < 0x8000
2979 && INTVAL (addr
) >= -0x8000)
2981 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
2983 else if (GET_CODE (addr
) == CONST_INT
)
2985 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
2987 else if (TARGET_PCREL
)
2990 output_addr_const (file
, addr
);
2992 asm_fprintf (file
, ":w,%Rpc)");
2994 asm_fprintf (file
, ":l,%Rpc)");
2998 /* Special case for SYMBOL_REF if the symbol name ends in
2999 `.<letter>', this can be mistaken as a size suffix. Put
3000 the name in parentheses. */
3001 if (GET_CODE (addr
) == SYMBOL_REF
3002 && strlen (XSTR (addr
, 0)) > 2
3003 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3006 output_addr_const (file
, addr
);
3010 output_addr_const (file
, addr
);
3016 /* Check for cases where a clr insns can be omitted from code using
3017 strict_low_part sets. For example, the second clrl here is not needed:
3018 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3020 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3021 insn we are checking for redundancy. TARGET is the register set by the
3025 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3030 p
= prev_nonnote_insn (first_insn
);
3034 /* If it isn't an insn, then give up. */
3035 if (GET_CODE (p
) != INSN
)
3038 if (reg_set_p (target
, p
))
3040 rtx set
= single_set (p
);
3043 /* If it isn't an easy to recognize insn, then give up. */
3047 dest
= SET_DEST (set
);
3049 /* If this sets the entire target register to zero, then our
3050 first_insn is redundant. */
3051 if (rtx_equal_p (dest
, target
)
3052 && SET_SRC (set
) == const0_rtx
)
3054 else if (GET_CODE (dest
) == STRICT_LOW_PART
3055 && GET_CODE (XEXP (dest
, 0)) == REG
3056 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3057 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3058 <= GET_MODE_SIZE (mode
)))
3059 /* This is a strict low part set which modifies less than
3060 we are using, so it is safe. */
3066 p
= prev_nonnote_insn (p
);
3072 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3073 range carefully since this predicate is used in DImode contexts. Also, we
3074 need some extra crud to make it work when hosted on 64-bit machines. */
3077 const_uint32_operand (rtx op
, enum machine_mode mode
)
3079 /* It doesn't make sense to ask this question with a mode that is
3080 not larger than 32 bits. */
3081 if (GET_MODE_BITSIZE (mode
) <= 32)
3084 #if HOST_BITS_PER_WIDE_INT > 32
3085 /* All allowed constants will fit a CONST_INT. */
3086 return (GET_CODE (op
) == CONST_INT
3087 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3089 return (GET_CODE (op
) == CONST_INT
3090 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3094 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3095 to check the range carefully since this predicate is used in DImode
3099 const_sint32_operand (rtx op
, enum machine_mode mode
)
3101 /* It doesn't make sense to ask this question with a mode that is
3102 not larger than 32 bits. */
3103 if (GET_MODE_BITSIZE (mode
) <= 32)
3106 /* All allowed constants will fit a CONST_INT. */
3107 return (GET_CODE (op
) == CONST_INT
3108 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3111 /* Operand predicates for implementing asymmetric pc-relative addressing
3112 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3113 when used as a source operand, but not as a destination operand.
3115 We model this by restricting the meaning of the basic predicates
3116 (general_operand, memory_operand, etc) to forbid the use of this
3117 addressing mode, and then define the following predicates that permit
3118 this addressing mode. These predicates can then be used for the
3119 source operands of the appropriate instructions.
3121 n.b. While it is theoretically possible to change all machine patterns
3122 to use this addressing more where permitted by the architecture,
3123 it has only been implemented for "common" cases: SImode, HImode, and
3124 QImode operands, and only for the principle operations that would
3125 require this addressing mode: data movement and simple integer operations.
3127 In parallel with these new predicates, two new constraint letters
3128 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3129 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3130 In the pcrel case 's' is only valid in combination with 'a' registers.
3131 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3132 of how these constraints are used.
3134 The use of these predicates is strictly optional, though patterns that
3135 don't will cause an extra reload register to be allocated where one
3138 lea (abc:w,%pc),%a0 ; need to reload address
3139 moveq &1,%d1 ; since write to pc-relative space
3140 movel %d1,%a0@ ; is not allowed
3142 lea (abc:w,%pc),%a1 ; no need to reload address here
3143 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3145 For more info, consult tiemann@cygnus.com.
3148 All of the ugliness with predicates and constraints is due to the
3149 simple fact that the m68k does not allow a pc-relative addressing
3150 mode as a destination. gcc does not distinguish between source and
3151 destination addresses. Hence, if we claim that pc-relative address
3152 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3153 end up with invalid code. To get around this problem, we left
3154 pc-relative modes as invalid addresses, and then added special
3155 predicates and constraints to accept them.
3157 A cleaner way to handle this is to modify gcc to distinguish
3158 between source and destination addresses. We can then say that
3159 pc-relative is a valid source address but not a valid destination
3160 address, and hopefully avoid a lot of the predicate and constraint
3161 hackery. Unfortunately, this would be a pretty big change. It would
3162 be a useful change for a number of ports, but there aren't any current
3163 plans to undertake this.
3165 ***************************************************************************/
3168 /* Special case of a general operand that's used as a source operand.
3169 Use this to permit reads from PC-relative memory when -mpcrel
3173 general_src_operand (rtx op
, enum machine_mode mode
)
3176 && GET_CODE (op
) == MEM
3177 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3178 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3179 || GET_CODE (XEXP (op
, 0)) == CONST
))
3181 return general_operand (op
, mode
);
3184 /* Special case of a nonimmediate operand that's used as a source.
3185 Use this to permit reads from PC-relative memory when -mpcrel
3189 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3191 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3192 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3193 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3194 || GET_CODE (XEXP (op
, 0)) == CONST
))
3196 return nonimmediate_operand (op
, mode
);
3199 /* Special case of a memory operand that's used as a source.
3200 Use this to permit reads from PC-relative memory when -mpcrel
3204 memory_src_operand (rtx op
, enum machine_mode mode
)
3206 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3207 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3208 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3209 || GET_CODE (XEXP (op
, 0)) == CONST
))
3211 return memory_operand (op
, mode
);
3214 /* Predicate that accepts only a pc-relative address. This is needed
3215 because pc-relative addresses don't satisfy the predicate
3216 "general_src_operand". */
3219 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3221 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3222 || GET_CODE (op
) == CONST
);
3226 output_andsi3 (rtx
*operands
)
3229 if (GET_CODE (operands
[2]) == CONST_INT
3230 && (INTVAL (operands
[2]) | 0xffff) == (HOST_WIDE_INT
)0xffffffff
3231 && (DATA_REG_P (operands
[0])
3232 || offsettable_memref_p (operands
[0]))
3233 && !TARGET_COLDFIRE
)
3235 if (GET_CODE (operands
[0]) != REG
)
3236 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3237 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3238 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3240 if (operands
[2] == const0_rtx
)
3242 return "and%.w %2,%0";
3244 if (GET_CODE (operands
[2]) == CONST_INT
3245 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3246 && (DATA_REG_P (operands
[0])
3247 || offsettable_memref_p (operands
[0])))
3249 if (DATA_REG_P (operands
[0]))
3251 operands
[1] = GEN_INT (logval
);
3255 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3256 operands
[1] = GEN_INT (logval
% 8);
3258 /* This does not set condition codes in a standard way. */
3260 return "bclr %1,%0";
3262 return "and%.l %2,%0";
3266 output_iorsi3 (rtx
*operands
)
3268 register int logval
;
3269 if (GET_CODE (operands
[2]) == CONST_INT
3270 && INTVAL (operands
[2]) >> 16 == 0
3271 && (DATA_REG_P (operands
[0])
3272 || offsettable_memref_p (operands
[0]))
3273 && !TARGET_COLDFIRE
)
3275 if (GET_CODE (operands
[0]) != REG
)
3276 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3277 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3279 if (INTVAL (operands
[2]) == 0xffff)
3280 return "mov%.w %2,%0";
3281 return "or%.w %2,%0";
3283 if (GET_CODE (operands
[2]) == CONST_INT
3284 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3285 && (DATA_REG_P (operands
[0])
3286 || offsettable_memref_p (operands
[0])))
3288 if (DATA_REG_P (operands
[0]))
3289 operands
[1] = GEN_INT (logval
);
3292 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3293 operands
[1] = GEN_INT (logval
% 8);
3296 return "bset %1,%0";
3298 return "or%.l %2,%0";
3302 output_xorsi3 (rtx
*operands
)
3304 register int logval
;
3305 if (GET_CODE (operands
[2]) == CONST_INT
3306 && INTVAL (operands
[2]) >> 16 == 0
3307 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3308 && !TARGET_COLDFIRE
)
3310 if (! DATA_REG_P (operands
[0]))
3311 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3312 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3314 if (INTVAL (operands
[2]) == 0xffff)
3316 return "eor%.w %2,%0";
3318 if (GET_CODE (operands
[2]) == CONST_INT
3319 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3320 && (DATA_REG_P (operands
[0])
3321 || offsettable_memref_p (operands
[0])))
3323 if (DATA_REG_P (operands
[0]))
3324 operands
[1] = GEN_INT (logval
);
3327 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3328 operands
[1] = GEN_INT (logval
% 8);
3331 return "bchg %1,%0";
3333 return "eor%.l %2,%0";
3336 #ifdef M68K_TARGET_COFF
3338 /* Output assembly to switch to section NAME with attribute FLAGS. */
3341 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3345 if (flags
& SECTION_WRITE
)
3350 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3353 #endif /* M68K_TARGET_COFF */
3356 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3357 HOST_WIDE_INT delta
,
3358 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3364 if (delta
> 0 && delta
<= 8)
3365 asm_fprintf (file
, MOTOROLA
?
3366 "\taddq.l %I%d,4(%Rsp)\n" :
3367 "\taddql %I%d,%Rsp@(4)\n",
3369 else if (delta
< 0 && delta
>= -8)
3370 asm_fprintf (file
, MOTOROLA
?
3371 "\tsubq.l %I%d,4(%Rsp)\n" :
3372 "\tsubql %I%d,%Rsp@(4)\n",
3375 asm_fprintf (file
, MOTOROLA
?
3376 "\tadd.l %I%wd,4(%Rsp)\n" :
3377 "\taddl %I%wd,%Rsp@(4)\n",
3380 xops
[0] = DECL_RTL (function
);
3382 /* Logic taken from call patterns in m68k.md. */
3387 else if ((flag_pic
== 1) || TARGET_68020
)
3390 #if defined(USE_GAS)
3391 fmt
= "bra.l %0@PLTPC";
3393 fmt
= "bra %0@PLTPC";
3395 else /* !MOTOROLA */
3402 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3403 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3405 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3409 #if MOTOROLA && !defined (USE_GAS)
3416 output_asm_insn (fmt
, xops
);
3419 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3422 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3423 int incoming ATTRIBUTE_UNUSED
)
3425 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);