1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static bool m68k_rtx_costs (rtx
, int, int, int *);
126 /* Specify the identification number of the library being built */
127 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
129 /* Nonzero if the last compare/test insn had FP operands. The
130 sCC expanders peek at this to determine what to do for the
131 68060, which has no fsCC instructions. */
132 int m68k_last_compare_had_fp_operands
;
134 /* Initialize the GCC target structure. */
136 #if INT_OP_GROUP == INT_OP_DOT_WORD
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
141 #if INT_OP_GROUP == INT_OP_NO_DOT
142 #undef TARGET_ASM_BYTE_OP
143 #define TARGET_ASM_BYTE_OP "\tbyte\t"
144 #undef TARGET_ASM_ALIGNED_HI_OP
145 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
146 #undef TARGET_ASM_ALIGNED_SI_OP
147 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
150 #if INT_OP_GROUP == INT_OP_DC
151 #undef TARGET_ASM_BYTE_OP
152 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
155 #undef TARGET_ASM_ALIGNED_SI_OP
156 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
159 #undef TARGET_ASM_UNALIGNED_HI_OP
160 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
161 #undef TARGET_ASM_UNALIGNED_SI_OP
162 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
164 #undef TARGET_ASM_FUNCTION_PROLOGUE
165 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
166 #undef TARGET_ASM_FUNCTION_EPILOGUE
167 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
169 #undef TARGET_ASM_OUTPUT_MI_THUNK
170 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
171 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
172 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
174 #undef TARGET_ASM_FILE_START_APP_OFF
175 #define TARGET_ASM_FILE_START_APP_OFF true
177 #undef TARGET_DEFAULT_TARGET_FLAGS
178 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
179 #undef TARGET_HANDLE_OPTION
180 #define TARGET_HANDLE_OPTION m68k_handle_option
182 #undef TARGET_RTX_COSTS
183 #define TARGET_RTX_COSTS m68k_rtx_costs
185 #undef TARGET_ATTRIBUTE_TABLE
186 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
188 #undef TARGET_PROMOTE_PROTOTYPES
189 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
191 #undef TARGET_STRUCT_VALUE_RTX
192 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
194 static const struct attribute_spec m68k_attribute_table
[] =
196 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
197 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
198 { NULL
, 0, 0, false, false, false, NULL
}
201 struct gcc_target targetm
= TARGET_INITIALIZER
;
203 /* Base flags for 68k ISAs. */
204 #define FL_FOR_isa_00 FL_ISA_68000
205 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
206 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
207 generated 68881 code for 68020 and 68030 targets unless explicitly told
209 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
210 | FL_BITFIELD | FL_68881)
211 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
212 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
214 /* Base flags for ColdFire ISAs. */
215 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
216 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
217 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
218 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
219 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
223 /* Traditional 68000 instruction sets. */
229 /* ColdFire instruction set variants. */
237 /* Information about one of the -march, -mcpu or -mtune arguments. */
238 struct m68k_target_selection
240 /* The argument being described. */
243 /* For -mcpu, this is the device selected by the option.
244 For -mtune and -march, it is a representative device
245 for the microarchitecture or ISA respectively. */
246 enum target_device device
;
248 /* The M68K_DEVICE fields associated with DEVICE. See the comment
249 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
251 enum uarch_type microarch
;
256 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
257 static const struct m68k_target_selection all_devices
[] =
259 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
260 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
261 #include "m68k-devices.def"
263 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
266 /* A list of all ISAs, mapping each one to a representative device.
267 Used for -march selection. */
268 static const struct m68k_target_selection all_isas
[] =
270 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
271 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
272 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
273 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
274 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
275 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
276 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
277 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
279 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
281 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
282 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
285 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
288 /* A list of all microarchitectures, mapping each one to a representative
289 device. Used for -mtune selection. */
290 static const struct m68k_target_selection all_microarchs
[] =
292 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
293 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
294 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
295 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
296 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
297 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
298 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
299 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
300 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
301 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
302 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
304 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
305 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
309 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
312 /* The entries associated with the -mcpu, -march and -mtune settings,
313 or null for options that have not been used. */
314 const struct m68k_target_selection
*m68k_cpu_entry
;
315 const struct m68k_target_selection
*m68k_arch_entry
;
316 const struct m68k_target_selection
*m68k_tune_entry
;
318 /* Which CPU we are generating code for. */
319 enum target_device m68k_cpu
;
321 /* Which microarchitecture to tune for. */
322 enum uarch_type m68k_tune
;
324 /* Which FPU to use. */
325 enum fpu_type m68k_fpu
;
327 /* The set of FL_* flags that apply to the target processor. */
328 unsigned int m68k_cpu_flags
;
330 /* Asm templates for calling or jumping to an arbitrary symbolic address,
331 or NULL if such calls or jumps are not supported. The address is held
333 const char *m68k_symbolic_call
;
334 const char *m68k_symbolic_jump
;
336 /* See whether TABLE has an entry with name NAME. Return true and
337 store the entry in *ENTRY if so, otherwise return false and
338 leave *ENTRY alone. */
341 m68k_find_selection (const struct m68k_target_selection
**entry
,
342 const struct m68k_target_selection
*table
,
347 for (i
= 0; table
[i
].name
; i
++)
348 if (strcmp (table
[i
].name
, name
) == 0)
356 /* Implement TARGET_HANDLE_OPTION. */
359 m68k_handle_option (size_t code
, const char *arg
, int value
)
364 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
367 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
370 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
373 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
376 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
379 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
382 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
385 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
388 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
392 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
395 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
399 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
402 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
404 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
407 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
409 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
412 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
415 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
418 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
421 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
425 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
427 case OPT_mshared_library_id_
:
428 if (value
> MAX_LIBRARY_ID
)
429 error ("-mshared-library-id=%s is not between 0 and %d",
430 arg
, MAX_LIBRARY_ID
);
432 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
440 /* Sometimes certain combinations of command options do not make
441 sense on a particular target machine. You can define a macro
442 `OVERRIDE_OPTIONS' to take account of this. This macro, if
443 defined, is executed once just after all the command options have
446 Don't use this macro to turn on various extra optimizations for
447 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
450 override_options (void)
452 const struct m68k_target_selection
*entry
;
453 unsigned long target_mask
;
461 -march=ARCH should generate code that runs any processor
462 implementing architecture ARCH. -mcpu=CPU should override -march
463 and should generate code that runs on processor CPU, making free
464 use of any instructions that CPU understands. -mtune=UARCH applies
465 on top of -mcpu or -march and optimises the code for UARCH. It does
466 not change the target architecture. */
469 /* Complain if the -march setting is for a different microarchitecture,
470 or includes flags that the -mcpu setting doesn't. */
472 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
473 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
474 warning (0, "-mcpu=%s conflicts with -march=%s",
475 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
477 entry
= m68k_cpu_entry
;
480 entry
= m68k_arch_entry
;
483 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
485 m68k_cpu_flags
= entry
->flags
;
487 /* Use the architecture setting to derive default values for
490 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
491 target_mask
|= MASK_BITFIELD
;
492 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
493 target_mask
|= MASK_CF_HWDIV
;
494 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
495 target_mask
|= MASK_HARD_FLOAT
;
496 target_flags
|= target_mask
& ~target_flags_explicit
;
498 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
499 m68k_cpu
= entry
->device
;
501 m68k_tune
= m68k_tune_entry
->microarch
;
502 #ifdef M68K_DEFAULT_TUNE
503 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
504 m68k_tune
= M68K_DEFAULT_TUNE
;
507 m68k_tune
= entry
->microarch
;
509 /* Set the type of FPU. */
510 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
511 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
514 if (TARGET_COLDFIRE_FPU
)
516 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
517 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
520 /* Sanity check to ensure that msep-data and mid-sahred-library are not
521 * both specified together. Doing so simply doesn't make sense.
523 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
524 error ("cannot specify both -msep-data and -mid-shared-library");
526 /* If we're generating code for a separate A5 relative data segment,
527 * we've got to enable -fPIC as well. This might be relaxable to
528 * -fpic but it hasn't been tested properly.
530 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
533 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
534 error if the target does not support them. */
535 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
536 error ("-mpcrel -fPIC is not currently supported on selected cpu");
538 /* ??? A historic way of turning on pic, or is this intended to
539 be an embedded thing that doesn't have the same name binding
540 significance that it does on hosted ELF systems? */
541 if (TARGET_PCREL
&& flag_pic
== 0)
546 #if MOTOROLA && !defined (USE_GAS)
547 m68k_symbolic_call
= "jsr %a0";
548 m68k_symbolic_jump
= "jmp %a0";
550 m68k_symbolic_call
= "jbsr %a0";
551 m68k_symbolic_jump
= "jra %a0";
554 else if (TARGET_ID_SHARED_LIBRARY
)
555 /* All addresses must be loaded from the GOT. */
557 else if (TARGET_68020
|| TARGET_ISAB
)
561 m68k_symbolic_call
= "bsr.l %c0";
562 m68k_symbolic_jump
= "bra.l %c0";
567 m68k_symbolic_call
= "bsr.l %p0";
568 m68k_symbolic_jump
= "bra.l %p0";
570 m68k_symbolic_call
= "bsr %p0";
571 m68k_symbolic_jump
= "bra %p0";
574 /* Turn off function cse if we are doing PIC. We always want
575 function call to be done as `bsr foo@PLTPC'. */
576 /* ??? It's traditional to do this for -mpcrel too, but it isn't
577 clear how intentional that is. */
578 flag_no_function_cse
= 1;
581 SUBTARGET_OVERRIDE_OPTIONS
;
584 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
585 given argument and NAME is the argument passed to -mcpu. Return NULL
586 if -mcpu was not passed. */
589 m68k_cpp_cpu_ident (const char *prefix
)
593 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
596 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
597 given argument and NAME is the name of the representative device for
598 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
601 m68k_cpp_cpu_family (const char *prefix
)
605 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
608 /* Return nonzero if FUNC is an interrupt function as specified by the
609 "interrupt_handler" attribute. */
611 m68k_interrupt_function_p(tree func
)
615 if (TREE_CODE (func
) != FUNCTION_DECL
)
618 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
619 return (a
!= NULL_TREE
);
622 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
623 struct attribute_spec.handler. */
625 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
626 tree args ATTRIBUTE_UNUSED
,
627 int flags ATTRIBUTE_UNUSED
,
630 if (TREE_CODE (*node
) != FUNCTION_DECL
)
632 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
633 IDENTIFIER_POINTER (name
));
634 *no_add_attrs
= true;
641 m68k_compute_frame_layout (void)
644 unsigned int mask
, rmask
;
645 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
647 /* Only compute the frame once per function.
648 Don't cache information until reload has been completed. */
649 if (current_frame
.funcdef_no
== current_function_funcdef_no
653 current_frame
.size
= (get_frame_size () + 3) & -4;
655 mask
= rmask
= saved
= 0;
656 for (regno
= 0; regno
< 16; regno
++)
657 if (m68k_save_reg (regno
, interrupt_handler
))
660 rmask
|= 1 << (15 - regno
);
663 current_frame
.offset
= saved
* 4;
664 current_frame
.reg_no
= saved
;
665 current_frame
.reg_mask
= mask
;
666 current_frame
.reg_rev_mask
= rmask
;
668 current_frame
.foffset
= 0;
669 mask
= rmask
= saved
= 0;
670 if (TARGET_HARD_FLOAT
)
672 for (regno
= 16; regno
< 24; regno
++)
673 if (m68k_save_reg (regno
, interrupt_handler
))
675 mask
|= 1 << (regno
- 16);
676 rmask
|= 1 << (23 - regno
);
679 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
680 current_frame
.offset
+= current_frame
.foffset
;
682 current_frame
.fpu_no
= saved
;
683 current_frame
.fpu_mask
= mask
;
684 current_frame
.fpu_rev_mask
= rmask
;
686 /* Remember what function this frame refers to. */
687 current_frame
.funcdef_no
= current_function_funcdef_no
;
691 m68k_initial_elimination_offset (int from
, int to
)
694 /* The arg pointer points 8 bytes before the start of the arguments,
695 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
696 frame pointer in most frames. */
697 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
698 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
699 return argptr_offset
;
701 m68k_compute_frame_layout ();
703 gcc_assert (to
== STACK_POINTER_REGNUM
);
706 case ARG_POINTER_REGNUM
:
707 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
708 case FRAME_POINTER_REGNUM
:
709 return current_frame
.offset
+ current_frame
.size
;
715 /* Refer to the array `regs_ever_live' to determine which registers
716 to save; `regs_ever_live[I]' is nonzero if register number I
717 is ever used in the function. This function is responsible for
718 knowing which registers should not be saved even if used.
719 Return true if we need to save REGNO. */
722 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
724 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
726 if (current_function_uses_pic_offset_table
)
728 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
732 if (current_function_calls_eh_return
)
737 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
738 if (test
== INVALID_REGNUM
)
745 /* Fixed regs we never touch. */
746 if (fixed_regs
[regno
])
749 /* The frame pointer (if it is such) is handled specially. */
750 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
753 /* Interrupt handlers must also save call_used_regs
754 if they are live or when calling nested functions. */
755 if (interrupt_handler
)
757 if (regs_ever_live
[regno
])
760 if (!current_function_is_leaf
&& call_used_regs
[regno
])
764 /* Never need to save registers that aren't touched. */
765 if (!regs_ever_live
[regno
])
768 /* Otherwise save everything that isn't call-clobbered. */
769 return !call_used_regs
[regno
];
772 /* This function generates the assembly code for function entry.
773 STREAM is a stdio stream to output the code to.
774 SIZE is an int: how many units of temporary storage to allocate. */
777 m68k_output_function_prologue (FILE *stream
,
778 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
780 HOST_WIDE_INT fsize_with_regs
;
781 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
783 m68k_compute_frame_layout();
785 /* If the stack limit is a symbol, we can check it here,
786 before actually allocating the space. */
787 if (current_function_limit_stack
788 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
789 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
790 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
792 /* On ColdFire add register save into initial stack frame setup, if possible. */
793 fsize_with_regs
= current_frame
.size
;
796 if (current_frame
.reg_no
> 2)
797 fsize_with_regs
+= current_frame
.reg_no
* 4;
798 if (current_frame
.fpu_no
)
799 fsize_with_regs
+= current_frame
.fpu_no
* 8;
802 if (frame_pointer_needed
)
804 if (current_frame
.size
== 0 && TUNE_68040
)
805 /* on the 68040, pea + move is faster than link.w 0 */
806 fprintf (stream
, (MOTOROLA
807 ? "\tpea (%s)\n\tmove.l %s,%s\n"
808 : "\tpea %s@\n\tmovel %s,%s\n"),
809 M68K_REGNAME (FRAME_POINTER_REGNUM
),
810 M68K_REGNAME (STACK_POINTER_REGNUM
),
811 M68K_REGNAME (FRAME_POINTER_REGNUM
));
812 else if (fsize_with_regs
< 0x8000)
813 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
814 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
815 else if (TARGET_68020
)
816 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
817 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
819 /* Adding negative number is faster on the 68040. */
821 "\tlink" ASM_DOTW
" %s,%I0\n"
822 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
823 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
825 else if (fsize_with_regs
) /* !frame_pointer_needed */
827 if (fsize_with_regs
< 0x8000)
829 if (fsize_with_regs
<= 8)
831 if (!TARGET_COLDFIRE
)
832 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
835 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
838 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
839 /* On the CPU32 it is faster to use two subqw instructions to
840 subtract a small integer (8 < N <= 16) to a register. */
842 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
843 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
844 fsize_with_regs
- 8);
846 /* Adding negative number is faster on the 68040. */
847 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
850 asm_fprintf (stream
, (MOTOROLA
851 ? "\tlea (%wd,%Rsp),%Rsp\n"
852 : "\tlea %Rsp@(%wd),%Rsp\n"),
855 else /* fsize_with_regs >= 0x8000 */
856 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
858 } /* !frame_pointer_needed */
860 if (dwarf2out_do_frame ())
862 if (frame_pointer_needed
)
865 l
= (char *) dwarf2out_cfi_label ();
867 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
868 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
869 cfa_offset
+= current_frame
.size
;
873 cfa_offset
+= current_frame
.size
;
874 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
878 if (current_frame
.fpu_mask
)
882 asm_fprintf (stream
, (MOTOROLA
883 ? "\tfmovm %I0x%x,-(%Rsp)\n"
884 : "\tfmovem %I0x%x,%Rsp@-\n"),
885 current_frame
.fpu_mask
);
891 /* stack already has registers in it. Find the offset from
892 the bottom of stack to where the FP registers go */
893 if (current_frame
.reg_no
<= 2)
896 offset
= current_frame
.reg_no
* 4;
899 "\tfmovem %I0x%x,%d(%Rsp)\n",
900 current_frame
.fpu_rev_mask
,
904 "\tfmovem %I0x%x,(%Rsp)\n",
905 current_frame
.fpu_rev_mask
);
908 if (dwarf2out_do_frame ())
910 char *l
= (char *) dwarf2out_cfi_label ();
913 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
914 if (! frame_pointer_needed
)
915 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
916 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
917 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
918 dwarf2out_reg_save (l
, regno
, -cfa_offset
919 + n_regs
++ * TARGET_FP_REG_SIZE
);
923 /* If the stack limit is not a symbol, check it here.
924 This has the disadvantage that it may be too late... */
925 if (current_function_limit_stack
)
927 if (REG_P (stack_limit_rtx
))
928 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
929 M68K_REGNAME (REGNO (stack_limit_rtx
)));
930 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
931 warning (0, "stack limit expression is not supported");
934 if (current_frame
.reg_no
<= 2)
936 /* Store each separately in the same order moveml uses.
937 Using two movel instructions instead of a single moveml
938 is about 15% faster for the 68020 and 68030 at no expense
943 for (i
= 0; i
< 16; i
++)
944 if (current_frame
.reg_rev_mask
& (1 << i
))
946 asm_fprintf (stream
, (MOTOROLA
947 ? "\t%Omove.l %s,-(%Rsp)\n"
948 : "\tmovel %s,%Rsp@-\n"),
949 M68K_REGNAME (15 - i
));
950 if (dwarf2out_do_frame ())
952 char *l
= (char *) dwarf2out_cfi_label ();
955 if (! frame_pointer_needed
)
956 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
957 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
961 else if (current_frame
.reg_rev_mask
)
964 /* The ColdFire does not support the predecrement form of the
965 MOVEM instruction, so we must adjust the stack pointer and
966 then use the plain address register indirect mode.
967 The required register save space was combined earlier with
968 the fsize_with_regs amount. */
970 asm_fprintf (stream
, (MOTOROLA
971 ? "\tmovm.l %I0x%x,(%Rsp)\n"
972 : "\tmoveml %I0x%x,%Rsp@\n"),
973 current_frame
.reg_mask
);
975 asm_fprintf (stream
, (MOTOROLA
976 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
977 : "\tmoveml %I0x%x,%Rsp@-\n"),
978 current_frame
.reg_rev_mask
);
979 if (dwarf2out_do_frame ())
981 char *l
= (char *) dwarf2out_cfi_label ();
984 cfa_offset
+= current_frame
.reg_no
* 4;
985 if (! frame_pointer_needed
)
986 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
987 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
988 if (current_frame
.reg_mask
& (1 << regno
))
989 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
992 if (!TARGET_SEP_DATA
&& flag_pic
993 && (current_function_uses_pic_offset_table
994 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
996 if (TARGET_ID_SHARED_LIBRARY
)
998 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
999 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1000 m68k_library_id_string
,
1001 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1006 asm_fprintf (stream
,
1007 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
1008 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1011 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
1012 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1013 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
1014 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1015 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1021 /* Return true if a simple (return) instruction is sufficient for this
1022 instruction (i.e. if no epilogue is needed). */
1025 m68k_use_return_insn (void)
1027 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1030 m68k_compute_frame_layout ();
1031 return current_frame
.offset
== 0;
1034 /* This function generates the assembly code for function exit,
1035 on machines that need it.
1037 The function epilogue should not depend on the current stack pointer!
1038 It should use the frame pointer only, if there is a frame pointer.
1039 This is mandatory because of alloca; we also take advantage of it to
1040 omit stack adjustments before returning. */
1043 m68k_output_function_epilogue (FILE *stream
,
1044 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1046 HOST_WIDE_INT fsize
, fsize_with_regs
;
1048 bool restore_from_sp
= false;
1049 rtx insn
= get_last_insn ();
1051 m68k_compute_frame_layout ();
1053 /* If the last insn was a BARRIER, we don't have to write any code. */
1054 if (GET_CODE (insn
) == NOTE
)
1055 insn
= prev_nonnote_insn (insn
);
1056 if (insn
&& GET_CODE (insn
) == BARRIER
)
1059 fsize
= current_frame
.size
;
1061 /* FIXME: leaf_function_p below is too strong.
1062 What we really need to know there is if there could be pending
1063 stack adjustment needed at that point. */
1065 = (! frame_pointer_needed
1066 || (! current_function_calls_alloca
&& leaf_function_p ()));
1068 /* fsize_with_regs is the size we need to adjust the sp when
1069 popping the frame. */
1070 fsize_with_regs
= fsize
;
1072 /* Because the ColdFire doesn't support moveml with
1073 complex address modes, we must adjust the stack manually
1074 after restoring registers. When the frame pointer isn't used,
1075 we can merge movem adjustment into frame unlinking
1076 made immediately after it. */
1077 if (TARGET_COLDFIRE
&& restore_from_sp
)
1079 if (current_frame
.reg_no
> 2)
1080 fsize_with_regs
+= current_frame
.reg_no
* 4;
1081 if (current_frame
.fpu_no
)
1082 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1085 if (current_frame
.offset
+ fsize
>= 0x8000
1086 && ! restore_from_sp
1087 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1089 /* Because the ColdFire doesn't support moveml with
1090 complex address modes we make an extra correction here. */
1091 if (TARGET_COLDFIRE
)
1092 fsize
+= current_frame
.offset
;
1094 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1095 fsize
= 0, big
= true;
1097 if (current_frame
.reg_no
<= 2)
1099 /* Restore each separately in the same order moveml does.
1100 Using two movel instructions instead of a single moveml
1101 is about 15% faster for the 68020 and 68030 at no expense
1105 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1107 for (i
= 0; i
< 16; i
++)
1108 if (current_frame
.reg_mask
& (1 << i
))
1113 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1115 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1118 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1119 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1123 else if (restore_from_sp
)
1124 asm_fprintf (stream
, (MOTOROLA
1125 ? "\t%Omove.l (%Rsp)+,%s\n"
1126 : "\tmovel %Rsp@+,%s\n"),
1131 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1133 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1136 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1137 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1144 else if (current_frame
.reg_mask
)
1146 /* The ColdFire requires special handling due to its limited moveml
1148 if (TARGET_COLDFIRE
)
1152 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1153 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1154 asm_fprintf (stream
, (MOTOROLA
1155 ? "\tmovm.l (%Ra1),%I0x%x\n"
1156 : "\tmoveml %Ra1@,%I0x%x\n"),
1157 current_frame
.reg_mask
);
1159 else if (restore_from_sp
)
1160 asm_fprintf (stream
, (MOTOROLA
1161 ? "\tmovm.l (%Rsp),%I0x%x\n"
1162 : "\tmoveml %Rsp@,%I0x%x\n"),
1163 current_frame
.reg_mask
);
1167 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1168 current_frame
.offset
+ fsize
,
1169 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1170 current_frame
.reg_mask
);
1172 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1173 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1174 current_frame
.offset
+ fsize
,
1175 current_frame
.reg_mask
);
1178 else /* !TARGET_COLDFIRE */
1183 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1184 current_frame
.offset
+ fsize
,
1185 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1186 current_frame
.reg_mask
);
1188 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1189 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1190 current_frame
.offset
+ fsize
,
1191 current_frame
.reg_mask
);
1193 else if (restore_from_sp
)
1195 asm_fprintf (stream
, (MOTOROLA
1196 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1197 : "\tmoveml %Rsp@+,%I0x%x\n"),
1198 current_frame
.reg_mask
);
1203 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1204 current_frame
.offset
+ fsize
,
1205 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1206 current_frame
.reg_mask
);
1208 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1209 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1210 current_frame
.offset
+ fsize
,
1211 current_frame
.reg_mask
);
1215 if (current_frame
.fpu_rev_mask
)
1219 if (TARGET_COLDFIRE
)
1221 if (current_frame
.reg_no
)
1222 asm_fprintf (stream
, MOTOROLA
?
1223 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1224 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1225 current_frame
.reg_no
* 4,
1226 current_frame
.fpu_rev_mask
);
1228 asm_fprintf (stream
, MOTOROLA
?
1229 "\tfmovem.d (%Ra1),%I0x%x\n" :
1230 "\tfmovmd (%Ra1),%I0x%x\n",
1231 current_frame
.fpu_rev_mask
);
1234 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1235 current_frame
.foffset
+ fsize
,
1236 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1237 current_frame
.fpu_rev_mask
);
1239 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1240 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1241 current_frame
.foffset
+ fsize
,
1242 current_frame
.fpu_rev_mask
);
1244 else if (restore_from_sp
)
1246 if (TARGET_COLDFIRE
)
1250 /* Stack already has registers in it. Find the offset from
1251 the bottom of stack to where the FP registers go. */
1252 if (current_frame
.reg_no
<= 2)
1255 offset
= current_frame
.reg_no
* 4;
1257 asm_fprintf (stream
,
1258 "\tfmovem %Rsp@(%d), %I0x%x\n",
1259 offset
, current_frame
.fpu_rev_mask
);
1261 asm_fprintf (stream
,
1262 "\tfmovem %Rsp@, %I0x%x\n",
1263 current_frame
.fpu_rev_mask
);
1266 asm_fprintf (stream
, MOTOROLA
?
1267 "\tfmovm (%Rsp)+,%I0x%x\n" :
1268 "\tfmovem %Rsp@+,%I0x%x\n",
1269 current_frame
.fpu_rev_mask
);
1273 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1274 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1275 current_frame
.foffset
+ fsize
,
1276 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1277 current_frame
.fpu_rev_mask
);
1279 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1280 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1281 current_frame
.foffset
+ fsize
,
1282 current_frame
.fpu_rev_mask
);
1285 if (frame_pointer_needed
)
1286 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1287 else if (fsize_with_regs
)
1289 if (fsize_with_regs
<= 8)
1291 if (!TARGET_COLDFIRE
)
1292 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1295 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1298 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1300 /* On the CPU32 it is faster to use two addqw instructions to
1301 add a small integer (8 < N <= 16) to a register. */
1302 asm_fprintf (stream
,
1303 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1304 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1305 fsize_with_regs
- 8);
1307 else if (fsize_with_regs
< 0x8000)
1310 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1313 asm_fprintf (stream
, (MOTOROLA
1314 ? "\tlea (%wd,%Rsp),%Rsp\n"
1315 : "\tlea %Rsp@(%wd),%Rsp\n"),
1319 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1321 if (current_function_calls_eh_return
)
1322 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1323 if (m68k_interrupt_function_p (current_function_decl
))
1324 fprintf (stream
, "\trte\n");
1325 else if (current_function_pops_args
)
1326 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1328 fprintf (stream
, "\trts\n");
1331 /* Return true if X is a valid comparison operator for the dbcc
1334 Note it rejects floating point comparison operators.
1335 (In the future we could use Fdbcc).
1337 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1340 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1342 switch (GET_CODE (x
))
1344 case EQ
: case NE
: case GTU
: case LTU
:
1348 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1350 case GT
: case LT
: case GE
: case LE
:
1351 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1357 /* Return nonzero if flags are currently in the 68881 flag register. */
1359 flags_in_68881 (void)
1361 /* We could add support for these in the future */
1362 return cc_status
.flags
& CC_IN_68881
;
1365 /* Convert X to a legitimate function call memory reference and return the
1369 m68k_legitimize_call_address (rtx x
)
1371 gcc_assert (MEM_P (x
));
1372 if (call_operand (XEXP (x
, 0), VOIDmode
))
1374 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1377 /* Output a dbCC; jCC sequence. Note we do not handle the
1378 floating point version of this sequence (Fdbcc). We also
1379 do not handle alternative conditions when CC_NO_OVERFLOW is
1380 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1381 kick those out before we get here. */
1384 output_dbcc_and_branch (rtx
*operands
)
1386 switch (GET_CODE (operands
[3]))
1389 output_asm_insn (MOTOROLA
1390 ? "dbeq %0,%l1\n\tjbeq %l2"
1391 : "dbeq %0,%l1\n\tjeq %l2",
1396 output_asm_insn (MOTOROLA
1397 ? "dbne %0,%l1\n\tjbne %l2"
1398 : "dbne %0,%l1\n\tjne %l2",
1403 output_asm_insn (MOTOROLA
1404 ? "dbgt %0,%l1\n\tjbgt %l2"
1405 : "dbgt %0,%l1\n\tjgt %l2",
1410 output_asm_insn (MOTOROLA
1411 ? "dbhi %0,%l1\n\tjbhi %l2"
1412 : "dbhi %0,%l1\n\tjhi %l2",
1417 output_asm_insn (MOTOROLA
1418 ? "dblt %0,%l1\n\tjblt %l2"
1419 : "dblt %0,%l1\n\tjlt %l2",
1424 output_asm_insn (MOTOROLA
1425 ? "dbcs %0,%l1\n\tjbcs %l2"
1426 : "dbcs %0,%l1\n\tjcs %l2",
1431 output_asm_insn (MOTOROLA
1432 ? "dbge %0,%l1\n\tjbge %l2"
1433 : "dbge %0,%l1\n\tjge %l2",
1438 output_asm_insn (MOTOROLA
1439 ? "dbcc %0,%l1\n\tjbcc %l2"
1440 : "dbcc %0,%l1\n\tjcc %l2",
1445 output_asm_insn (MOTOROLA
1446 ? "dble %0,%l1\n\tjble %l2"
1447 : "dble %0,%l1\n\tjle %l2",
1452 output_asm_insn (MOTOROLA
1453 ? "dbls %0,%l1\n\tjbls %l2"
1454 : "dbls %0,%l1\n\tjls %l2",
1462 /* If the decrement is to be done in SImode, then we have
1463 to compensate for the fact that dbcc decrements in HImode. */
1464 switch (GET_MODE (operands
[0]))
1467 output_asm_insn (MOTOROLA
1468 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1469 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1482 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1485 enum rtx_code op_code
= GET_CODE (op
);
1487 /* This does not produce a useful cc. */
1490 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1491 below. Swap the operands and change the op if these requirements
1492 are not fulfilled. */
1493 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1497 operand1
= operand2
;
1499 op_code
= swap_condition (op_code
);
1501 loperands
[0] = operand1
;
1502 if (GET_CODE (operand1
) == REG
)
1503 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1505 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1506 if (operand2
!= const0_rtx
)
1508 loperands
[2] = operand2
;
1509 if (GET_CODE (operand2
) == REG
)
1510 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1512 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1514 loperands
[4] = gen_label_rtx ();
1515 if (operand2
!= const0_rtx
)
1517 output_asm_insn (MOTOROLA
1518 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1519 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1524 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1525 output_asm_insn ("tst%.l %0", loperands
);
1527 output_asm_insn ("cmp%.w #0,%0", loperands
);
1529 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1531 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1532 output_asm_insn ("tst%.l %1", loperands
);
1534 output_asm_insn ("cmp%.w #0,%1", loperands
);
1537 loperands
[5] = dest
;
1542 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1543 CODE_LABEL_NUMBER (loperands
[4]));
1544 output_asm_insn ("seq %5", loperands
);
1548 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1549 CODE_LABEL_NUMBER (loperands
[4]));
1550 output_asm_insn ("sne %5", loperands
);
1554 loperands
[6] = gen_label_rtx ();
1555 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1557 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1558 CODE_LABEL_NUMBER (loperands
[4]));
1559 output_asm_insn ("sgt %5", loperands
);
1560 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1561 CODE_LABEL_NUMBER (loperands
[6]));
1565 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1566 CODE_LABEL_NUMBER (loperands
[4]));
1567 output_asm_insn ("shi %5", loperands
);
1571 loperands
[6] = gen_label_rtx ();
1572 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1574 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1575 CODE_LABEL_NUMBER (loperands
[4]));
1576 output_asm_insn ("slt %5", loperands
);
1577 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1578 CODE_LABEL_NUMBER (loperands
[6]));
1582 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1583 CODE_LABEL_NUMBER (loperands
[4]));
1584 output_asm_insn ("scs %5", loperands
);
1588 loperands
[6] = gen_label_rtx ();
1589 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1591 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1592 CODE_LABEL_NUMBER (loperands
[4]));
1593 output_asm_insn ("sge %5", loperands
);
1594 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1595 CODE_LABEL_NUMBER (loperands
[6]));
1599 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1600 CODE_LABEL_NUMBER (loperands
[4]));
1601 output_asm_insn ("scc %5", loperands
);
1605 loperands
[6] = gen_label_rtx ();
1606 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1608 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1609 CODE_LABEL_NUMBER (loperands
[4]));
1610 output_asm_insn ("sle %5", loperands
);
1611 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1612 CODE_LABEL_NUMBER (loperands
[6]));
1616 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1617 CODE_LABEL_NUMBER (loperands
[4]));
1618 output_asm_insn ("sls %5", loperands
);
1628 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1630 operands
[0] = countop
;
1631 operands
[1] = dataop
;
1633 if (GET_CODE (countop
) == CONST_INT
)
1635 register int count
= INTVAL (countop
);
1636 /* If COUNT is bigger than size of storage unit in use,
1637 advance to the containing unit of same size. */
1638 if (count
> signpos
)
1640 int offset
= (count
& ~signpos
) / 8;
1641 count
= count
& signpos
;
1642 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1644 if (count
== signpos
)
1645 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1647 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1649 /* These three statements used to use next_insns_test_no...
1650 but it appears that this should do the same job. */
1652 && next_insn_tests_no_inequality (insn
))
1655 && next_insn_tests_no_inequality (insn
))
1658 && next_insn_tests_no_inequality (insn
))
1661 cc_status
.flags
= CC_NOT_NEGATIVE
;
1663 return "btst %0,%1";
1666 /* Legitimize PIC addresses. If the address is already
1667 position-independent, we return ORIG. Newly generated
1668 position-independent addresses go to REG. If we need more
1669 than one register, we lose.
1671 An address is legitimized by making an indirect reference
1672 through the Global Offset Table with the name of the symbol
1675 The assembler and linker are responsible for placing the
1676 address of the symbol in the GOT. The function prologue
1677 is responsible for initializing a5 to the starting address
1680 The assembler is also responsible for translating a symbol name
1681 into a constant displacement from the start of the GOT.
1683 A quick example may make things a little clearer:
1685 When not generating PIC code to store the value 12345 into _foo
1686 we would generate the following code:
1690 When generating PIC two transformations are made. First, the compiler
1691 loads the address of foo into a register. So the first transformation makes:
1696 The code in movsi will intercept the lea instruction and call this
1697 routine which will transform the instructions into:
1699 movel a5@(_foo:w), a0
1703 That (in a nutshell) is how *all* symbol and label references are
1707 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1712 /* First handle a simple SYMBOL_REF or LABEL_REF */
1713 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1717 pic_ref
= gen_rtx_MEM (Pmode
,
1718 gen_rtx_PLUS (Pmode
,
1719 pic_offset_table_rtx
, orig
));
1720 current_function_uses_pic_offset_table
= 1;
1721 MEM_READONLY_P (pic_ref
) = 1;
1722 emit_move_insn (reg
, pic_ref
);
1725 else if (GET_CODE (orig
) == CONST
)
1729 /* Make sure this has not already been legitimized. */
1730 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1731 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1736 /* legitimize both operands of the PLUS */
1737 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1739 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1740 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1741 base
== reg
? 0 : reg
);
1743 if (GET_CODE (orig
) == CONST_INT
)
1744 return plus_constant (base
, INTVAL (orig
));
1745 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1746 /* Likewise, should we set special REG_NOTEs here? */
1752 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1754 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1756 /* Return the type of move that should be used for integer I. */
1759 const_method (HOST_WIDE_INT i
)
1766 /* The ColdFire doesn't have byte or word operations. */
1767 /* FIXME: This may not be useful for the m68060 either. */
1768 if (!TARGET_COLDFIRE
)
1770 /* if -256 < N < 256 but N is not in range for a moveq
1771 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1772 if (USE_MOVQ (i
^ 0xff))
1774 /* Likewise, try with not.w */
1775 if (USE_MOVQ (i
^ 0xffff))
1777 /* This is the only value where neg.w is useful */
1782 /* Try also with swap. */
1784 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1789 /* Try using MVZ/MVS with an immediate value to load constants. */
1790 if (i
>= 0 && i
<= 65535)
1792 if (i
>= -32768 && i
<= 32767)
1796 /* Otherwise, use move.l */
1800 /* Return the cost of moving constant I into a data register. */
1803 const_int_cost (HOST_WIDE_INT i
)
1805 switch (const_method (i
))
1808 /* Constants between -128 and 127 are cheap due to moveq. */
1816 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1826 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1831 /* Constant zero is super cheap due to clr instruction. */
1832 if (x
== const0_rtx
)
1835 *total
= const_int_cost (INTVAL (x
));
1845 /* Make 0.0 cheaper than other floating constants to
1846 encourage creating tstsf and tstdf insns. */
1847 if (outer_code
== COMPARE
1848 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1854 /* These are vaguely right for a 68020. */
1855 /* The costs for long multiply have been adjusted to work properly
1856 in synth_mult on the 68020, relative to an average of the time
1857 for add and the time for shift, taking away a little more because
1858 sometimes move insns are needed. */
1859 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1865 : TARGET_COLDFIRE ? 3 : 13)
1870 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
1871 : TARGET_COLDFIRE ? 2 : 8)
1874 (TARGET_CF_HWDIV ? 11 \
1875 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
1878 /* An lea costs about three times as much as a simple add. */
1879 if (GET_MODE (x
) == SImode
1880 && GET_CODE (XEXP (x
, 1)) == REG
1881 && GET_CODE (XEXP (x
, 0)) == MULT
1882 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1883 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1884 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1885 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1886 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1888 /* lea an@(dx:l:i),am */
1889 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1899 *total
= COSTS_N_INSNS(1);
1904 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1906 if (INTVAL (XEXP (x
, 1)) < 16)
1907 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1909 /* We're using clrw + swap for these cases. */
1910 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1913 *total
= COSTS_N_INSNS (10); /* Worst case. */
1916 /* A shift by a big integer takes an extra instruction. */
1917 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1918 && (INTVAL (XEXP (x
, 1)) == 16))
1920 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1923 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1924 && !(INTVAL (XEXP (x
, 1)) > 0
1925 && INTVAL (XEXP (x
, 1)) <= 8))
1927 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1933 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1934 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1935 && GET_MODE (x
) == SImode
)
1936 *total
= COSTS_N_INSNS (MULW_COST
);
1937 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1938 *total
= COSTS_N_INSNS (MULW_COST
);
1940 *total
= COSTS_N_INSNS (MULL_COST
);
1947 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1948 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1949 else if (TARGET_CF_HWDIV
)
1950 *total
= COSTS_N_INSNS (18);
1952 *total
= COSTS_N_INSNS (43); /* div.l */
1960 /* Return an instruction to move CONST_INT OPERANDS[1] into data regsiter
1964 output_move_const_into_data_reg (rtx
*operands
)
1968 i
= INTVAL (operands
[1]);
1969 switch (const_method (i
))
1972 return "mvzw %1,%0";
1974 return "mvsw %1,%0";
1976 return "moveq %1,%0";
1979 operands
[1] = GEN_INT (i
^ 0xff);
1980 return "moveq %1,%0\n\tnot%.b %0";
1983 operands
[1] = GEN_INT (i
^ 0xffff);
1984 return "moveq %1,%0\n\tnot%.w %0";
1987 return "moveq #-128,%0\n\tneg%.w %0";
1992 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1993 return "moveq %1,%0\n\tswap %0";
1996 return "move%.l %1,%0";
2002 /* Return true if I can be handled by ISA B's mov3q instruction. */
2005 valid_mov3q_const (HOST_WIDE_INT i
)
2007 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2010 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2011 I is the value of OPERANDS[1]. */
2014 output_move_simode_const (rtx
*operands
)
2020 src
= INTVAL (operands
[1]);
2022 && (DATA_REG_P (dest
) || MEM_P (dest
))
2023 /* clr insns on 68000 read before writing. */
2024 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2025 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2027 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2028 return "mov3q%.l %1,%0";
2029 else if (src
== 0 && ADDRESS_REG_P (dest
))
2030 return "sub%.l %0,%0";
2031 else if (DATA_REG_P (dest
))
2032 return output_move_const_into_data_reg (operands
);
2033 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2035 if (valid_mov3q_const (src
))
2036 return "mov3q%.l %1,%0";
2037 return "move%.w %1,%0";
2039 else if (MEM_P (dest
)
2040 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2041 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2042 && IN_RANGE (src
, -0x8000, 0x7fff))
2044 if (valid_mov3q_const (src
))
2045 return "mov3q%.l %1,%-";
2048 return "move%.l %1,%0";
2052 output_move_simode (rtx
*operands
)
2054 if (GET_CODE (operands
[1]) == CONST_INT
)
2055 return output_move_simode_const (operands
);
2056 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2057 || GET_CODE (operands
[1]) == CONST
)
2058 && push_operand (operands
[0], SImode
))
2060 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2061 || GET_CODE (operands
[1]) == CONST
)
2062 && ADDRESS_REG_P (operands
[0]))
2063 return "lea %a1,%0";
2064 return "move%.l %1,%0";
2068 output_move_himode (rtx
*operands
)
2070 if (GET_CODE (operands
[1]) == CONST_INT
)
2072 if (operands
[1] == const0_rtx
2073 && (DATA_REG_P (operands
[0])
2074 || GET_CODE (operands
[0]) == MEM
)
2075 /* clr insns on 68000 read before writing. */
2076 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2077 || !(GET_CODE (operands
[0]) == MEM
2078 && MEM_VOLATILE_P (operands
[0]))))
2080 else if (operands
[1] == const0_rtx
2081 && ADDRESS_REG_P (operands
[0]))
2082 return "sub%.l %0,%0";
2083 else if (DATA_REG_P (operands
[0])
2084 && INTVAL (operands
[1]) < 128
2085 && INTVAL (operands
[1]) >= -128)
2086 return "moveq %1,%0";
2087 else if (INTVAL (operands
[1]) < 0x8000
2088 && INTVAL (operands
[1]) >= -0x8000)
2089 return "move%.w %1,%0";
2091 else if (CONSTANT_P (operands
[1]))
2092 return "move%.l %1,%0";
2093 /* Recognize the insn before a tablejump, one that refers
2094 to a table of offsets. Such an insn will need to refer
2095 to a label on the insn. So output one. Use the label-number
2096 of the table of offsets to generate this label. This code,
2097 and similar code below, assumes that there will be at most one
2098 reference to each table. */
2099 if (GET_CODE (operands
[1]) == MEM
2100 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2101 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2102 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2104 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2106 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2107 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2109 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2110 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2112 return "move%.w %1,%0";
2116 output_move_qimode (rtx
*operands
)
2118 /* 68k family always modifies the stack pointer by at least 2, even for
2119 byte pushes. The 5200 (ColdFire) does not do this. */
2121 /* This case is generated by pushqi1 pattern now. */
2122 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2123 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2124 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2125 && ! ADDRESS_REG_P (operands
[1])
2126 && ! TARGET_COLDFIRE
));
2128 /* clr and st insns on 68000 read before writing. */
2129 if (!ADDRESS_REG_P (operands
[0])
2130 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2131 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2133 if (operands
[1] == const0_rtx
)
2135 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2136 && GET_CODE (operands
[1]) == CONST_INT
2137 && (INTVAL (operands
[1]) & 255) == 255)
2143 if (GET_CODE (operands
[1]) == CONST_INT
2144 && DATA_REG_P (operands
[0])
2145 && INTVAL (operands
[1]) < 128
2146 && INTVAL (operands
[1]) >= -128)
2147 return "moveq %1,%0";
2148 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2149 return "sub%.l %0,%0";
2150 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2151 return "move%.l %1,%0";
2152 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2153 from address registers. */
2154 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2155 return "move%.w %1,%0";
2156 return "move%.b %1,%0";
2160 output_move_stricthi (rtx
*operands
)
2162 if (operands
[1] == const0_rtx
2163 /* clr insns on 68000 read before writing. */
2164 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2165 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2167 return "move%.w %1,%0";
2171 output_move_strictqi (rtx
*operands
)
2173 if (operands
[1] == const0_rtx
2174 /* clr insns on 68000 read before writing. */
2175 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2176 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2178 return "move%.b %1,%0";
2181 /* Return the best assembler insn template
2182 for moving operands[1] into operands[0] as a fullword. */
2185 singlemove_string (rtx
*operands
)
2187 if (GET_CODE (operands
[1]) == CONST_INT
)
2188 return output_move_simode_const (operands
);
2189 return "move%.l %1,%0";
2193 /* Output assembler code to perform a doubleword move insn
2194 with operands OPERANDS. */
2197 output_move_double (rtx
*operands
)
2201 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2206 rtx addreg0
= 0, addreg1
= 0;
2207 int dest_overlapped_low
= 0;
2208 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2213 /* First classify both operands. */
2215 if (REG_P (operands
[0]))
2217 else if (offsettable_memref_p (operands
[0]))
2219 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2221 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2223 else if (GET_CODE (operands
[0]) == MEM
)
2228 if (REG_P (operands
[1]))
2230 else if (CONSTANT_P (operands
[1]))
2232 else if (offsettable_memref_p (operands
[1]))
2234 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2236 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2238 else if (GET_CODE (operands
[1]) == MEM
)
2243 /* Check for the cases that the operand constraints are not supposed
2244 to allow to happen. Generating code for these cases is
2246 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2248 /* If one operand is decrementing and one is incrementing
2249 decrement the former register explicitly
2250 and change that operand into ordinary indexing. */
2252 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2254 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2256 output_asm_insn ("sub%.l #12,%0", operands
);
2258 output_asm_insn ("subq%.l #8,%0", operands
);
2259 if (GET_MODE (operands
[1]) == XFmode
)
2260 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2261 else if (GET_MODE (operands
[0]) == DFmode
)
2262 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2264 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2267 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2269 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2271 output_asm_insn ("sub%.l #12,%1", operands
);
2273 output_asm_insn ("subq%.l #8,%1", operands
);
2274 if (GET_MODE (operands
[1]) == XFmode
)
2275 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2276 else if (GET_MODE (operands
[1]) == DFmode
)
2277 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2279 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2283 /* If an operand is an unoffsettable memory ref, find a register
2284 we can increment temporarily to make it refer to the second word. */
2286 if (optype0
== MEMOP
)
2287 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2289 if (optype1
== MEMOP
)
2290 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2292 /* Ok, we can do one word at a time.
2293 Normally we do the low-numbered word first,
2294 but if either operand is autodecrementing then we
2295 do the high-numbered word first.
2297 In either case, set up in LATEHALF the operands to use
2298 for the high-numbered word and in some cases alter the
2299 operands in OPERANDS to be suitable for the low-numbered word. */
2303 if (optype0
== REGOP
)
2305 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2306 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2308 else if (optype0
== OFFSOP
)
2310 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2311 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2315 middlehalf
[0] = operands
[0];
2316 latehalf
[0] = operands
[0];
2319 if (optype1
== REGOP
)
2321 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2322 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2324 else if (optype1
== OFFSOP
)
2326 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2327 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2329 else if (optype1
== CNSTOP
)
2331 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2336 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2337 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2338 operands
[1] = GEN_INT (l
[0]);
2339 middlehalf
[1] = GEN_INT (l
[1]);
2340 latehalf
[1] = GEN_INT (l
[2]);
2344 /* No non-CONST_DOUBLE constant should ever appear
2346 gcc_assert (!CONSTANT_P (operands
[1]));
2351 middlehalf
[1] = operands
[1];
2352 latehalf
[1] = operands
[1];
2356 /* size is not 12: */
2358 if (optype0
== REGOP
)
2359 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2360 else if (optype0
== OFFSOP
)
2361 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2363 latehalf
[0] = operands
[0];
2365 if (optype1
== REGOP
)
2366 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2367 else if (optype1
== OFFSOP
)
2368 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2369 else if (optype1
== CNSTOP
)
2370 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2372 latehalf
[1] = operands
[1];
2375 /* If insn is effectively movd N(sp),-(sp) then we will do the
2376 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2377 for the low word as well, to compensate for the first decrement of sp. */
2378 if (optype0
== PUSHOP
2379 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2380 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2381 operands
[1] = middlehalf
[1] = latehalf
[1];
2383 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2384 if the upper part of reg N does not appear in the MEM, arrange to
2385 emit the move late-half first. Otherwise, compute the MEM address
2386 into the upper part of N and use that as a pointer to the memory
2388 if (optype0
== REGOP
2389 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2391 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2393 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2394 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2396 /* If both halves of dest are used in the src memory address,
2397 compute the address into latehalf of dest.
2398 Note that this can't happen if the dest is two data regs. */
2400 xops
[0] = latehalf
[0];
2401 xops
[1] = XEXP (operands
[1], 0);
2402 output_asm_insn ("lea %a1,%0", xops
);
2403 if (GET_MODE (operands
[1]) == XFmode
)
2405 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2406 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2407 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2411 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2412 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2416 && reg_overlap_mentioned_p (middlehalf
[0],
2417 XEXP (operands
[1], 0)))
2419 /* Check for two regs used by both source and dest.
2420 Note that this can't happen if the dest is all data regs.
2421 It can happen if the dest is d6, d7, a0.
2422 But in that case, latehalf is an addr reg, so
2423 the code at compadr does ok. */
2425 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2426 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2429 /* JRV says this can't happen: */
2430 gcc_assert (!addreg0
&& !addreg1
);
2432 /* Only the middle reg conflicts; simply put it last. */
2433 output_asm_insn (singlemove_string (operands
), operands
);
2434 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2435 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2438 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2439 /* If the low half of dest is mentioned in the source memory
2440 address, the arrange to emit the move late half first. */
2441 dest_overlapped_low
= 1;
2444 /* If one or both operands autodecrementing,
2445 do the two words, high-numbered first. */
2447 /* Likewise, the first move would clobber the source of the second one,
2448 do them in the other order. This happens only for registers;
2449 such overlap can't happen in memory unless the user explicitly
2450 sets it up, and that is an undefined circumstance. */
2452 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2453 || (optype0
== REGOP
&& optype1
== REGOP
2454 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2455 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2456 || dest_overlapped_low
)
2458 /* Make any unoffsettable addresses point at high-numbered word. */
2462 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2464 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2469 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2471 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2475 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2477 /* Undo the adds we just did. */
2479 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2481 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2485 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2487 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2489 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2492 /* Do low-numbered word. */
2493 return singlemove_string (operands
);
2496 /* Normal case: do the two words, low-numbered first. */
2498 output_asm_insn (singlemove_string (operands
), operands
);
2500 /* Do the middle one of the three words for long double */
2504 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2506 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2508 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2511 /* Make any unoffsettable addresses point at high-numbered word. */
2513 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2515 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2518 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2520 /* Undo the adds we just did. */
2524 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2526 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2531 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2533 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2540 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2541 new rtx with the correct mode. */
2544 force_mode (enum machine_mode mode
, rtx orig
)
2546 if (mode
== GET_MODE (orig
))
2549 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2552 return gen_rtx_REG (mode
, REGNO (orig
));
2556 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2558 return reg_renumber
&& FP_REG_P (op
);
2561 /* Emit insns to move operands[1] into operands[0].
2563 Return 1 if we have written out everything that needs to be done to
2564 do the move. Otherwise, return 0 and the caller will emit the move
2567 Note SCRATCH_REG may not be in the proper mode depending on how it
2568 will be used. This routine is responsible for creating a new copy
2569 of SCRATCH_REG in the proper mode. */
2572 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2574 register rtx operand0
= operands
[0];
2575 register rtx operand1
= operands
[1];
2579 && reload_in_progress
&& GET_CODE (operand0
) == REG
2580 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2581 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2582 else if (scratch_reg
2583 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2584 && GET_CODE (SUBREG_REG (operand0
)) == REG
2585 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2587 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2588 the code which tracks sets/uses for delete_output_reload. */
2589 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2590 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2591 SUBREG_BYTE (operand0
));
2592 operand0
= alter_subreg (&temp
);
2596 && reload_in_progress
&& GET_CODE (operand1
) == REG
2597 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2598 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2599 else if (scratch_reg
2600 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2601 && GET_CODE (SUBREG_REG (operand1
)) == REG
2602 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2604 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2605 the code which tracks sets/uses for delete_output_reload. */
2606 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2607 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2608 SUBREG_BYTE (operand1
));
2609 operand1
= alter_subreg (&temp
);
2612 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2613 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2614 != XEXP (operand0
, 0)))
2615 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2616 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2617 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2618 != XEXP (operand1
, 0)))
2619 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2621 /* Handle secondary reloads for loads/stores of FP registers where
2622 the address is symbolic by using the scratch register */
2623 if (fp_reg_operand (operand0
, mode
)
2624 && ((GET_CODE (operand1
) == MEM
2625 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2626 || ((GET_CODE (operand1
) == SUBREG
2627 && GET_CODE (XEXP (operand1
, 0)) == MEM
2628 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2631 if (GET_CODE (operand1
) == SUBREG
)
2632 operand1
= XEXP (operand1
, 0);
2634 /* SCRATCH_REG will hold an address. We want
2635 it in SImode regardless of what mode it was originally given
2637 scratch_reg
= force_mode (SImode
, scratch_reg
);
2639 /* D might not fit in 14 bits either; for such cases load D into
2641 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2643 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2644 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2646 XEXP (XEXP (operand1
, 0), 0),
2650 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2651 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2652 gen_rtx_MEM (mode
, scratch_reg
)));
2655 else if (fp_reg_operand (operand1
, mode
)
2656 && ((GET_CODE (operand0
) == MEM
2657 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2658 || ((GET_CODE (operand0
) == SUBREG
)
2659 && GET_CODE (XEXP (operand0
, 0)) == MEM
2660 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2663 if (GET_CODE (operand0
) == SUBREG
)
2664 operand0
= XEXP (operand0
, 0);
2666 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2667 it in SIMODE regardless of what mode it was originally given
2669 scratch_reg
= force_mode (SImode
, scratch_reg
);
2671 /* D might not fit in 14 bits either; for such cases load D into
2673 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2675 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2676 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2679 XEXP (XEXP (operand0
, 0),
2684 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2685 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2689 /* Handle secondary reloads for loads of FP registers from constant
2690 expressions by forcing the constant into memory.
2692 use scratch_reg to hold the address of the memory location.
2694 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2695 NO_REGS when presented with a const_int and an register class
2696 containing only FP registers. Doing so unfortunately creates
2697 more problems than it solves. Fix this for 2.5. */
2698 else if (fp_reg_operand (operand0
, mode
)
2699 && CONSTANT_P (operand1
)
2704 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2705 it in SIMODE regardless of what mode it was originally given
2707 scratch_reg
= force_mode (SImode
, scratch_reg
);
2709 /* Force the constant into memory and put the address of the
2710 memory location into scratch_reg. */
2711 xoperands
[0] = scratch_reg
;
2712 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2713 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2715 /* Now load the destination register. */
2716 emit_insn (gen_rtx_SET (mode
, operand0
,
2717 gen_rtx_MEM (mode
, scratch_reg
)));
2721 /* Now have insn-emit do whatever it normally does. */
2725 /* Return a REG that occurs in ADDR with coefficient 1.
2726 ADDR can be effectively incremented by incrementing REG. */
2729 find_addr_reg (rtx addr
)
2731 while (GET_CODE (addr
) == PLUS
)
2733 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2734 addr
= XEXP (addr
, 0);
2735 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2736 addr
= XEXP (addr
, 1);
2737 else if (CONSTANT_P (XEXP (addr
, 0)))
2738 addr
= XEXP (addr
, 1);
2739 else if (CONSTANT_P (XEXP (addr
, 1)))
2740 addr
= XEXP (addr
, 0);
2744 gcc_assert (GET_CODE (addr
) == REG
);
2748 /* Output assembler code to perform a 32-bit 3-operand add. */
2751 output_addsi3 (rtx
*operands
)
2753 if (! operands_match_p (operands
[0], operands
[1]))
2755 if (!ADDRESS_REG_P (operands
[1]))
2757 rtx tmp
= operands
[1];
2759 operands
[1] = operands
[2];
2763 /* These insns can result from reloads to access
2764 stack slots over 64k from the frame pointer. */
2765 if (GET_CODE (operands
[2]) == CONST_INT
2766 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2767 return "move%.l %2,%0\n\tadd%.l %1,%0";
2768 if (GET_CODE (operands
[2]) == REG
)
2769 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2770 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2772 if (GET_CODE (operands
[2]) == CONST_INT
)
2774 if (INTVAL (operands
[2]) > 0
2775 && INTVAL (operands
[2]) <= 8)
2776 return "addq%.l %2,%0";
2777 if (INTVAL (operands
[2]) < 0
2778 && INTVAL (operands
[2]) >= -8)
2780 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2781 return "subq%.l %2,%0";
2783 /* On the CPU32 it is faster to use two addql instructions to
2784 add a small integer (8 < N <= 16) to a register.
2785 Likewise for subql. */
2786 if (TUNE_CPU32
&& REG_P (operands
[0]))
2788 if (INTVAL (operands
[2]) > 8
2789 && INTVAL (operands
[2]) <= 16)
2791 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2792 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2794 if (INTVAL (operands
[2]) < -8
2795 && INTVAL (operands
[2]) >= -16)
2797 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2798 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2801 if (ADDRESS_REG_P (operands
[0])
2802 && INTVAL (operands
[2]) >= -0x8000
2803 && INTVAL (operands
[2]) < 0x8000)
2806 return "add%.w %2,%0";
2808 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2811 return "add%.l %2,%0";
2814 /* Store in cc_status the expressions that the condition codes will
2815 describe after execution of an instruction whose pattern is EXP.
2816 Do not alter them if the instruction would not alter the cc's. */
2818 /* On the 68000, all the insns to store in an address register fail to
2819 set the cc's. However, in some cases these instructions can make it
2820 possibly invalid to use the saved cc's. In those cases we clear out
2821 some or all of the saved cc's so they won't be used. */
2824 notice_update_cc (rtx exp
, rtx insn
)
2826 if (GET_CODE (exp
) == SET
)
2828 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2830 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2832 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2833 cc_status
.value1
= 0;
2834 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2835 cc_status
.value2
= 0;
2837 else if (!FP_REG_P (SET_DEST (exp
))
2838 && SET_DEST (exp
) != cc0_rtx
2839 && (FP_REG_P (SET_SRC (exp
))
2840 || GET_CODE (SET_SRC (exp
)) == FIX
2841 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2842 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2844 /* A pair of move insns doesn't produce a useful overall cc. */
2845 else if (!FP_REG_P (SET_DEST (exp
))
2846 && !FP_REG_P (SET_SRC (exp
))
2847 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2848 && (GET_CODE (SET_SRC (exp
)) == REG
2849 || GET_CODE (SET_SRC (exp
)) == MEM
2850 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2852 else if (SET_DEST (exp
) != pc_rtx
)
2854 cc_status
.flags
= 0;
2855 cc_status
.value1
= SET_DEST (exp
);
2856 cc_status
.value2
= SET_SRC (exp
);
2859 else if (GET_CODE (exp
) == PARALLEL
2860 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2862 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2863 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2865 if (ADDRESS_REG_P (dest
))
2867 else if (dest
!= pc_rtx
)
2869 cc_status
.flags
= 0;
2870 cc_status
.value1
= dest
;
2871 cc_status
.value2
= src
;
2876 if (cc_status
.value2
!= 0
2877 && ADDRESS_REG_P (cc_status
.value2
)
2878 && GET_MODE (cc_status
.value2
) == QImode
)
2880 if (cc_status
.value2
!= 0)
2881 switch (GET_CODE (cc_status
.value2
))
2883 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2884 case ROTATE
: case ROTATERT
:
2885 /* These instructions always clear the overflow bit, and set
2886 the carry to the bit shifted out. */
2887 /* ??? We don't currently have a way to signal carry not valid,
2888 nor do we check for it in the branch insns. */
2892 case PLUS
: case MINUS
: case MULT
:
2893 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2894 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2895 cc_status
.flags
|= CC_NO_OVERFLOW
;
2898 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2899 ends with a move insn moving r2 in r2's mode.
2900 Thus, the cc's are set for r2.
2901 This can set N bit spuriously. */
2902 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2907 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2909 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2910 cc_status
.value2
= 0;
2911 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2912 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2913 cc_status
.flags
= CC_IN_68881
;
2917 output_move_const_double (rtx
*operands
)
2919 int code
= standard_68881_constant_p (operands
[1]);
2923 static char buf
[40];
2925 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2928 return "fmove%.d %1,%0";
2932 output_move_const_single (rtx
*operands
)
2934 int code
= standard_68881_constant_p (operands
[1]);
2938 static char buf
[40];
2940 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2943 return "fmove%.s %f1,%0";
2946 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2947 from the "fmovecr" instruction.
2948 The value, anded with 0xff, gives the code to use in fmovecr
2949 to get the desired constant. */
2951 /* This code has been fixed for cross-compilation. */
2953 static int inited_68881_table
= 0;
2955 static const char *const strings_68881
[7] = {
2965 static const int codes_68881
[7] = {
2975 REAL_VALUE_TYPE values_68881
[7];
2977 /* Set up values_68881 array by converting the decimal values
2978 strings_68881 to binary. */
2981 init_68881_table (void)
2985 enum machine_mode mode
;
2988 for (i
= 0; i
< 7; i
++)
2992 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2993 values_68881
[i
] = r
;
2995 inited_68881_table
= 1;
2999 standard_68881_constant_p (rtx x
)
3004 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3005 used at all on those chips. */
3009 if (! inited_68881_table
)
3010 init_68881_table ();
3012 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3014 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3016 for (i
= 0; i
< 6; i
++)
3018 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3019 return (codes_68881
[i
]);
3022 if (GET_MODE (x
) == SFmode
)
3025 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3026 return (codes_68881
[6]);
3028 /* larger powers of ten in the constants ram are not used
3029 because they are not equal to a `double' C constant. */
3033 /* If X is a floating-point constant, return the logarithm of X base 2,
3034 or 0 if X is not a power of 2. */
3037 floating_exact_log2 (rtx x
)
3039 REAL_VALUE_TYPE r
, r1
;
3042 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3044 if (REAL_VALUES_LESS (r
, dconst1
))
3047 exp
= real_exponent (&r
);
3048 real_2expN (&r1
, exp
);
3049 if (REAL_VALUES_EQUAL (r1
, r
))
3055 /* A C compound statement to output to stdio stream STREAM the
3056 assembler syntax for an instruction operand X. X is an RTL
3059 CODE is a value that can be used to specify one of several ways
3060 of printing the operand. It is used when identical operands
3061 must be printed differently depending on the context. CODE
3062 comes from the `%' specification that was used to request
3063 printing of the operand. If the specification was just `%DIGIT'
3064 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3065 is the ASCII code for LTR.
3067 If X is a register, this macro should print the register's name.
3068 The names can be found in an array `reg_names' whose type is
3069 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3071 When the machine description has a specification `%PUNCT' (a `%'
3072 followed by a punctuation character), this macro is called with
3073 a null pointer for X and the punctuation character for CODE.
3075 The m68k specific codes are:
3077 '.' for dot needed in Motorola-style opcode names.
3078 '-' for an operand pushing on the stack:
3079 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3080 '+' for an operand pushing on the stack:
3081 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3082 '@' for a reference to the top word on the stack:
3083 sp@, (sp) or (%sp) depending on the style of syntax.
3084 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3085 but & in SGS syntax).
3086 '!' for the cc register (used in an `and to cc' insn).
3087 '$' for the letter `s' in an op code, but only on the 68040.
3088 '&' for the letter `d' in an op code, but only on the 68040.
3089 '/' for register prefix needed by longlong.h.
3091 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3092 'd' to force memory addressing to be absolute, not relative.
3093 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3094 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3095 or print pair of registers as rx:ry.
3096 'p' print an address with @PLTPC attached, but only if the operand
3097 is not locally-bound. */
3100 print_operand (FILE *file
, rtx op
, int letter
)
3105 fprintf (file
, ".");
3107 else if (letter
== '#')
3108 asm_fprintf (file
, "%I");
3109 else if (letter
== '-')
3110 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3111 else if (letter
== '+')
3112 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3113 else if (letter
== '@')
3114 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3115 else if (letter
== '!')
3116 asm_fprintf (file
, "%Rfpcr");
3117 else if (letter
== '$')
3120 fprintf (file
, "s");
3122 else if (letter
== '&')
3125 fprintf (file
, "d");
3127 else if (letter
== '/')
3128 asm_fprintf (file
, "%R");
3129 else if (letter
== 'p')
3131 output_addr_const (file
, op
);
3132 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3133 fprintf (file
, "@PLTPC");
3135 else if (GET_CODE (op
) == REG
)
3138 /* Print out the second register name of a register pair.
3139 I.e., R (6) => 7. */
3140 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3142 fputs (M68K_REGNAME(REGNO (op
)), file
);
3144 else if (GET_CODE (op
) == MEM
)
3146 output_address (XEXP (op
, 0));
3147 if (letter
== 'd' && ! TARGET_68020
3148 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3149 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3150 && INTVAL (XEXP (op
, 0)) < 0x8000
3151 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3152 fprintf (file
, MOTOROLA
? ".l" : ":l");
3154 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3157 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3158 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3160 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3163 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3164 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3166 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3169 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3170 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3174 /* Use `print_operand_address' instead of `output_addr_const'
3175 to ensure that we print relevant PIC stuff. */
3176 asm_fprintf (file
, "%I");
3178 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3179 print_operand_address (file
, op
);
3181 output_addr_const (file
, op
);
3186 /* A C compound statement to output to stdio stream STREAM the
3187 assembler syntax for an instruction operand that is a memory
3188 reference whose address is ADDR. ADDR is an RTL expression.
3190 Note that this contains a kludge that knows that the only reason
3191 we have an address (plus (label_ref...) (reg...)) when not generating
3192 PIC code is in the insn before a tablejump, and we know that m68k.md
3193 generates a label LInnn: on such an insn.
3195 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3196 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3198 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3199 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3200 we want. This difference can be accommodated by using an assembler
3201 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3202 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3203 macro. See m68k/sgs.h for an example; for versions without the bug.
3204 Some assemblers refuse all the above solutions. The workaround is to
3205 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3208 They also do not like things like "pea 1.w", so we simple leave off
3209 the .w on small constants.
3211 This routine is responsible for distinguishing between -fpic and -fPIC
3212 style relocations in an address. When generating -fpic code the
3213 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3214 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3217 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3218 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3219 #else /* !MOTOROLA */
3220 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3221 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3222 #endif /* !MOTOROLA */
3225 print_operand_address (FILE *file
, rtx addr
)
3227 register rtx reg1
, reg2
, breg
, ireg
;
3230 switch (GET_CODE (addr
))
3233 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3236 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3237 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3240 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3241 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3244 reg1
= reg2
= ireg
= breg
= offset
= 0;
3245 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3247 offset
= XEXP (addr
, 0);
3248 addr
= XEXP (addr
, 1);
3250 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3252 offset
= XEXP (addr
, 1);
3253 addr
= XEXP (addr
, 0);
3255 if (GET_CODE (addr
) != PLUS
)
3259 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3261 reg1
= XEXP (addr
, 0);
3262 addr
= XEXP (addr
, 1);
3264 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3266 reg1
= XEXP (addr
, 1);
3267 addr
= XEXP (addr
, 0);
3269 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3271 reg1
= XEXP (addr
, 0);
3272 addr
= XEXP (addr
, 1);
3274 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3276 reg1
= XEXP (addr
, 1);
3277 addr
= XEXP (addr
, 0);
3279 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3281 reg1
= XEXP (addr
, 0);
3282 addr
= XEXP (addr
, 1);
3284 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3286 reg1
= XEXP (addr
, 1);
3287 addr
= XEXP (addr
, 0);
3289 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3290 || GET_CODE (addr
) == SIGN_EXTEND
)
3298 #if 0 /* for OLD_INDEXING */
3299 else if (GET_CODE (addr
) == PLUS
)
3301 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3303 reg2
= XEXP (addr
, 0);
3304 addr
= XEXP (addr
, 1);
3306 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3308 reg2
= XEXP (addr
, 1);
3309 addr
= XEXP (addr
, 0);
3318 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3319 || GET_CODE (reg1
) == MULT
))
3320 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3325 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3330 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3331 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3334 if (GET_CODE (ireg
) == MULT
)
3336 scale
= INTVAL (XEXP (ireg
, 1));
3337 ireg
= XEXP (ireg
, 0);
3339 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3341 ASM_OUTPUT_CASE_FETCH (file
,
3342 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3343 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3344 fprintf (file
, "w");
3348 ASM_OUTPUT_CASE_FETCH (file
,
3349 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3350 M68K_REGNAME (REGNO (ireg
)));
3351 fprintf (file
, "l");
3354 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3358 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3359 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3361 ASM_OUTPUT_CASE_FETCH (file
,
3362 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3363 M68K_REGNAME (REGNO (breg
)));
3364 fprintf (file
, "l)");
3367 if (ireg
!= 0 || breg
!= 0)
3372 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3378 output_addr_const (file
, addr
);
3379 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3381 fprintf (file
, "@GOT");
3383 fprintf (file
, ".w");
3386 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3390 else /* !MOTOROLA */
3392 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3395 output_addr_const (file
, addr
);
3396 if (breg
== pic_offset_table_rtx
)
3400 fprintf (file
, ":w");
3403 fprintf (file
, ":l");
3412 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3414 scale
= INTVAL (XEXP (ireg
, 1));
3415 ireg
= XEXP (ireg
, 0);
3417 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3418 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3419 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3421 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3422 M68K_REGNAME (REGNO (ireg
)));
3424 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3428 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3429 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3431 ASM_OUTPUT_CASE_FETCH (file
,
3432 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3433 M68K_REGNAME (REGNO (reg1
)));
3434 fprintf (file
, "l)");
3437 /* FALL-THROUGH (is this really what we want?) */
3439 if (GET_CODE (addr
) == CONST_INT
3440 && INTVAL (addr
) < 0x8000
3441 && INTVAL (addr
) >= -0x8000)
3443 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3445 else if (GET_CODE (addr
) == CONST_INT
)
3447 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3449 else if (TARGET_PCREL
)
3452 output_addr_const (file
, addr
);
3454 asm_fprintf (file
, ":w,%Rpc)");
3456 asm_fprintf (file
, ":l,%Rpc)");
3460 /* Special case for SYMBOL_REF if the symbol name ends in
3461 `.<letter>', this can be mistaken as a size suffix. Put
3462 the name in parentheses. */
3463 if (GET_CODE (addr
) == SYMBOL_REF
3464 && strlen (XSTR (addr
, 0)) > 2
3465 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3468 output_addr_const (file
, addr
);
3472 output_addr_const (file
, addr
);
3478 /* Check for cases where a clr insns can be omitted from code using
3479 strict_low_part sets. For example, the second clrl here is not needed:
3480 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3482 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3483 insn we are checking for redundancy. TARGET is the register set by the
3487 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3492 p
= prev_nonnote_insn (first_insn
);
3496 /* If it isn't an insn, then give up. */
3497 if (GET_CODE (p
) != INSN
)
3500 if (reg_set_p (target
, p
))
3502 rtx set
= single_set (p
);
3505 /* If it isn't an easy to recognize insn, then give up. */
3509 dest
= SET_DEST (set
);
3511 /* If this sets the entire target register to zero, then our
3512 first_insn is redundant. */
3513 if (rtx_equal_p (dest
, target
)
3514 && SET_SRC (set
) == const0_rtx
)
3516 else if (GET_CODE (dest
) == STRICT_LOW_PART
3517 && GET_CODE (XEXP (dest
, 0)) == REG
3518 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3519 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3520 <= GET_MODE_SIZE (mode
)))
3521 /* This is a strict low part set which modifies less than
3522 we are using, so it is safe. */
3528 p
= prev_nonnote_insn (p
);
3534 /* Operand predicates for implementing asymmetric pc-relative addressing
3535 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3536 when used as a source operand, but not as a destination operand.
3538 We model this by restricting the meaning of the basic predicates
3539 (general_operand, memory_operand, etc) to forbid the use of this
3540 addressing mode, and then define the following predicates that permit
3541 this addressing mode. These predicates can then be used for the
3542 source operands of the appropriate instructions.
3544 n.b. While it is theoretically possible to change all machine patterns
3545 to use this addressing more where permitted by the architecture,
3546 it has only been implemented for "common" cases: SImode, HImode, and
3547 QImode operands, and only for the principle operations that would
3548 require this addressing mode: data movement and simple integer operations.
3550 In parallel with these new predicates, two new constraint letters
3551 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3552 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3553 In the pcrel case 's' is only valid in combination with 'a' registers.
3554 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3555 of how these constraints are used.
3557 The use of these predicates is strictly optional, though patterns that
3558 don't will cause an extra reload register to be allocated where one
3561 lea (abc:w,%pc),%a0 ; need to reload address
3562 moveq &1,%d1 ; since write to pc-relative space
3563 movel %d1,%a0@ ; is not allowed
3565 lea (abc:w,%pc),%a1 ; no need to reload address here
3566 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3568 For more info, consult tiemann@cygnus.com.
3571 All of the ugliness with predicates and constraints is due to the
3572 simple fact that the m68k does not allow a pc-relative addressing
3573 mode as a destination. gcc does not distinguish between source and
3574 destination addresses. Hence, if we claim that pc-relative address
3575 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3576 end up with invalid code. To get around this problem, we left
3577 pc-relative modes as invalid addresses, and then added special
3578 predicates and constraints to accept them.
3580 A cleaner way to handle this is to modify gcc to distinguish
3581 between source and destination addresses. We can then say that
3582 pc-relative is a valid source address but not a valid destination
3583 address, and hopefully avoid a lot of the predicate and constraint
3584 hackery. Unfortunately, this would be a pretty big change. It would
3585 be a useful change for a number of ports, but there aren't any current
3586 plans to undertake this.
3588 ***************************************************************************/
3592 output_andsi3 (rtx
*operands
)
3595 if (GET_CODE (operands
[2]) == CONST_INT
3596 && (INTVAL (operands
[2]) | 0xffff) == -1
3597 && (DATA_REG_P (operands
[0])
3598 || offsettable_memref_p (operands
[0]))
3599 && !TARGET_COLDFIRE
)
3601 if (GET_CODE (operands
[0]) != REG
)
3602 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3603 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3604 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3606 if (operands
[2] == const0_rtx
)
3608 return "and%.w %2,%0";
3610 if (GET_CODE (operands
[2]) == CONST_INT
3611 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3612 && (DATA_REG_P (operands
[0])
3613 || offsettable_memref_p (operands
[0])))
3615 if (DATA_REG_P (operands
[0]))
3616 operands
[1] = GEN_INT (logval
);
3619 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3620 operands
[1] = GEN_INT (logval
% 8);
3622 /* This does not set condition codes in a standard way. */
3624 return "bclr %1,%0";
3626 return "and%.l %2,%0";
3630 output_iorsi3 (rtx
*operands
)
3632 register int logval
;
3633 if (GET_CODE (operands
[2]) == CONST_INT
3634 && INTVAL (operands
[2]) >> 16 == 0
3635 && (DATA_REG_P (operands
[0])
3636 || offsettable_memref_p (operands
[0]))
3637 && !TARGET_COLDFIRE
)
3639 if (GET_CODE (operands
[0]) != REG
)
3640 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3641 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3643 if (INTVAL (operands
[2]) == 0xffff)
3644 return "mov%.w %2,%0";
3645 return "or%.w %2,%0";
3647 if (GET_CODE (operands
[2]) == CONST_INT
3648 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3649 && (DATA_REG_P (operands
[0])
3650 || offsettable_memref_p (operands
[0])))
3652 if (DATA_REG_P (operands
[0]))
3653 operands
[1] = GEN_INT (logval
);
3656 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3657 operands
[1] = GEN_INT (logval
% 8);
3660 return "bset %1,%0";
3662 return "or%.l %2,%0";
3666 output_xorsi3 (rtx
*operands
)
3668 register int logval
;
3669 if (GET_CODE (operands
[2]) == CONST_INT
3670 && INTVAL (operands
[2]) >> 16 == 0
3671 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3672 && !TARGET_COLDFIRE
)
3674 if (! DATA_REG_P (operands
[0]))
3675 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3676 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3678 if (INTVAL (operands
[2]) == 0xffff)
3680 return "eor%.w %2,%0";
3682 if (GET_CODE (operands
[2]) == CONST_INT
3683 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3684 && (DATA_REG_P (operands
[0])
3685 || offsettable_memref_p (operands
[0])))
3687 if (DATA_REG_P (operands
[0]))
3688 operands
[1] = GEN_INT (logval
);
3691 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3692 operands
[1] = GEN_INT (logval
% 8);
3695 return "bchg %1,%0";
3697 return "eor%.l %2,%0";
3700 /* Return the instruction that should be used for a call to address X,
3701 which is known to be in operand 0. */
3706 if (symbolic_operand (x
, VOIDmode
))
3707 return m68k_symbolic_call
;
3712 #ifdef M68K_TARGET_COFF
3714 /* Output assembly to switch to section NAME with attribute FLAGS. */
3717 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3718 tree decl ATTRIBUTE_UNUSED
)
3722 if (flags
& SECTION_WRITE
)
3727 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3730 #endif /* M68K_TARGET_COFF */
3733 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3734 HOST_WIDE_INT delta
,
3735 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3741 if (delta
> 0 && delta
<= 8)
3742 asm_fprintf (file
, (MOTOROLA
3743 ? "\taddq.l %I%d,4(%Rsp)\n"
3744 : "\taddql %I%d,%Rsp@(4)\n"),
3746 else if (delta
< 0 && delta
>= -8)
3747 asm_fprintf (file
, (MOTOROLA
3748 ? "\tsubq.l %I%d,4(%Rsp)\n"
3749 : "\tsubql %I%d,%Rsp@(4)\n"),
3751 else if (TARGET_COLDFIRE
)
3753 /* ColdFire can't add/sub a constant to memory unless it is in
3754 the range of addq/subq. So load the value into %d0 and
3755 then add it to 4(%sp). */
3756 if (delta
>= -128 && delta
<= 127)
3757 asm_fprintf (file
, (MOTOROLA
3758 ? "\tmoveq.l %I%wd,%Rd0\n"
3759 : "\tmoveql %I%wd,%Rd0\n"),
3762 asm_fprintf (file
, (MOTOROLA
3763 ? "\tmove.l %I%wd,%Rd0\n"
3764 : "\tmovel %I%wd,%Rd0\n"),
3766 asm_fprintf (file
, (MOTOROLA
3767 ? "\tadd.l %Rd0,4(%Rsp)\n"
3768 : "\taddl %Rd0,%Rsp@(4)\n"));
3771 asm_fprintf (file
, (MOTOROLA
3772 ? "\tadd.l %I%wd,4(%Rsp)\n"
3773 : "\taddl %I%wd,%Rsp@(4)\n"),
3776 xops
[0] = DECL_RTL (function
);
3778 gcc_assert (MEM_P (xops
[0])
3779 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
3780 xops
[0] = XEXP (xops
[0], 0);
3782 fmt
= m68k_symbolic_jump
;
3783 if (m68k_symbolic_jump
== NULL
)
3784 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3786 output_asm_insn (fmt
, xops
);
3789 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3792 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3793 int incoming ATTRIBUTE_UNUSED
)
3795 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3798 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3800 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3801 unsigned int new_reg
)
3804 /* Interrupt functions can only use registers that have already been
3805 saved by the prologue, even if they would normally be
3808 if (m68k_interrupt_function_p (current_function_decl
)
3809 && !regs_ever_live
[new_reg
])
3815 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3816 On the 68000, the cpu registers can hold any mode except bytes in address
3817 registers, but the 68881 registers can hold only SFmode or DFmode. */
3819 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3821 if (DATA_REGNO_P (regno
))
3823 /* Data Registers, can hold aggregate if fits in. */
3824 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3827 else if (ADDRESS_REGNO_P (regno
))
3829 /* Address Registers, can't hold bytes, can hold aggregate if
3831 if (GET_MODE_SIZE (mode
) == 1)
3833 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3836 else if (FP_REGNO_P (regno
))
3838 /* FPU registers, hold float or complex float of long double or
3840 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3841 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3842 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3848 /* Return floating point values in a 68881 register. This makes 68881 code
3849 a little bit faster. It also makes -msoft-float code incompatible with
3850 hard-float code, so people have to be careful not to mix the two.
3851 For ColdFire it was decided the ABI incompatibility is undesirable.
3852 If there is need for a hard-float ABI it is probably worth doing it
3853 properly and also passing function arguments in FP registers. */
3855 m68k_libcall_value (enum machine_mode mode
)
3862 return gen_rtx_REG (mode
, 16);
3867 return gen_rtx_REG (mode
, 0);
3871 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3873 enum machine_mode mode
;
3875 mode
= TYPE_MODE (valtype
);
3881 return gen_rtx_REG (mode
, 16);
3887 /* If the function returns a pointer, push that into %a0. */
3888 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
3889 /* For compatibility with the large body of existing code which
3890 does not always properly declare external functions returning
3891 pointer types, the m68k/SVR4 convention is to copy the value
3892 returned for pointer functions from a0 to d0 in the function
3893 epilogue, so that callers that have neglected to properly
3894 declare the callee can still find the correct return value in
3896 return gen_rtx_PARALLEL
3899 gen_rtx_EXPR_LIST (VOIDmode
,
3900 gen_rtx_REG (mode
, A0_REG
),
3902 gen_rtx_EXPR_LIST (VOIDmode
,
3903 gen_rtx_REG (mode
, D0_REG
),
3905 else if (POINTER_TYPE_P (valtype
))
3906 return gen_rtx_REG (mode
, A0_REG
);
3908 return gen_rtx_REG (mode
, D0_REG
);