1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string
;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string
;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string
;
64 /* Specify power of two alignment used for loops. */
66 /* Specify power of two alignment used for non-loop jumps. */
68 /* Specify power of two alignment used for functions. */
72 /* Sometimes certain combinations of command options do not make
73 sense on a particular target machine. You can define a macro
74 `OVERRIDE_OPTIONS' to take account of this. This macro, if
75 defined, is executed once just after all the command options have
78 Don't use this macro to turn on various extra optimizations for
79 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
88 /* Validate -malign-loops= value, or provide default */
89 if (m68k_align_loops_string
)
91 m68k_align_loops
= atoi (m68k_align_loops_string
);
92 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
93 fatal ("-malign-loops=%d is not between 1 and %d",
94 m68k_align_loops
, MAX_CODE_ALIGN
);
97 m68k_align_loops
= def_align
;
99 /* Validate -malign-jumps= value, or provide default */
100 if (m68k_align_jumps_string
)
102 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
103 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
104 fatal ("-malign-jumps=%d is not between 1 and %d",
105 m68k_align_jumps
, MAX_CODE_ALIGN
);
108 m68k_align_jumps
= def_align
;
110 /* Validate -malign-functions= value, or provide default */
111 if (m68k_align_funcs_string
)
113 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
114 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
115 fatal ("-malign-functions=%d is not between 1 and %d",
116 m68k_align_funcs
, MAX_CODE_ALIGN
);
119 m68k_align_funcs
= def_align
;
122 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
123 function at any time during the compilation process. In the future
124 we should try and eliminate the USE if we can easily determine that
125 all PIC references were deleted from the current function. That would
126 save an address register */
131 if (flag_pic
&& current_function_uses_pic_offset_table
)
133 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
134 emit_insn_after (insn
, get_insns ());
140 /* This function generates the assembly code for function entry.
141 STREAM is a stdio stream to output the code to.
142 SIZE is an int: how many units of temporary storage to allocate.
143 Refer to the array `regs_ever_live' to determine which registers
144 to save; `regs_ever_live[I]' is nonzero if register number I
145 is ever used in the function. This function is responsible for
146 knowing which registers should not be saved even if used. */
149 /* Note that the order of the bit mask for fmovem is the opposite
150 of the order for movem! */
154 output_function_prologue (stream
, size
)
159 register int mask
= 0;
160 int num_saved_regs
= 0;
161 extern char call_used_regs
[];
162 int fsize
= (size
+ 3) & -4;
165 if (frame_pointer_needed
)
167 if (fsize
== 0 && TARGET_68040
)
169 /* on the 68040, pea + move is faster than link.w 0 */
171 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
172 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
173 reg_names
[FRAME_POINTER_REGNUM
]);
175 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
176 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
177 reg_names
[FRAME_POINTER_REGNUM
]);
180 else if (fsize
< 0x8000)
183 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
184 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
186 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
187 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
190 else if (TARGET_68020
)
193 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
194 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
196 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
197 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 /* Adding negative number is faster on the 68040. */
204 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
205 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
207 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
208 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
214 /* Adding negative number is faster on the 68040. */
215 if (fsize
+ 4 < 0x8000)
220 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
222 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
227 /* asm_fprintf() cannot handle %. */
229 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
231 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
237 /* asm_fprintf() cannot handle %. */
239 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
241 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
245 #ifdef SUPPORT_SUN_FPA
246 for (regno
= 24; regno
< 56; regno
++)
247 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
250 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
253 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
260 for (regno
= 16; regno
< 24; regno
++)
261 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
262 mask
|= 1 << (regno
- 16);
263 if ((mask
& 0xff) != 0)
266 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
268 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
273 for (regno
= 0; regno
< 16; regno
++)
274 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
276 mask
|= 1 << (15 - regno
);
279 if (frame_pointer_needed
)
281 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
286 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
289 if (num_saved_regs
<= 2)
291 /* Store each separately in the same order moveml uses.
292 Using two movel instructions instead of a single moveml
293 is about 15% faster for the 68020 and 68030 at no expense
298 /* Undo the work from above. */
299 for (i
= 0; i
< 16; i
++)
303 "\t%Omove.l %s,-(%Rsp)\n",
305 "\tmovel %s,%Rsp@-\n",
313 /* The coldfire does not support the predecrement form of the
314 movml instruction, so we must adjust the stack pointer and
315 then use the plain address register indirect mode. We also
316 have to invert the register save mask to use the new mode.
318 FIXME: if num_saved_regs was calculated earlier, we could
319 combine the stack pointer adjustment with any adjustment
320 done when the initial stack frame is created. This would
321 save an instruction */
326 for (i
= 0; i
< 16; i
++)
328 newmask
|= (1 << (15-i
));
331 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
332 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
334 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
335 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
341 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
343 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
347 if (flag_pic
&& current_function_uses_pic_offset_table
)
350 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
351 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
353 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
354 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
355 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
356 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
357 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
362 /* Return true if this function's epilogue can be output as RTL. */
369 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
372 /* Copied from output_function_epilogue (). We should probably create a
373 separate layout routine to perform the common work. */
375 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
376 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
382 /* This function generates the assembly code for function exit,
383 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
385 The function epilogue should not depend on the current stack pointer!
386 It should use the frame pointer only, if there is a frame pointer.
387 This is mandatory because of alloca; we also take advantage of it to
388 omit stack adjustments before returning. */
391 output_function_epilogue (stream
, size
)
396 register int mask
, fmask
;
398 int offset
, foffset
, fpoffset
;
399 extern char call_used_regs
[];
400 int fsize
= (size
+ 3) & -4;
402 rtx insn
= get_last_insn ();
403 int restore_from_sp
= 0;
405 /* If the last insn was a BARRIER, we don't have to write any code. */
406 if (GET_CODE (insn
) == NOTE
)
407 insn
= prev_nonnote_insn (insn
);
408 if (insn
&& GET_CODE (insn
) == BARRIER
)
410 /* Output just a no-op so that debuggers don't get confused
411 about which function the pc is in at this address. */
412 asm_fprintf (stream
, "\tnop\n");
416 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
417 if (profile_block_flag
== 2)
419 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
423 #ifdef FUNCTION_EXTRA_EPILOGUE
424 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
426 nregs
= 0; fmask
= 0; fpoffset
= 0;
427 #ifdef SUPPORT_SUN_FPA
428 for (regno
= 24 ; regno
< 56 ; regno
++)
429 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
431 fpoffset
= nregs
* 8;
436 for (regno
= 16; regno
< 24; regno
++)
437 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
440 fmask
|= 1 << (23 - regno
);
443 foffset
= fpoffset
+ nregs
* 12;
445 if (frame_pointer_needed
)
446 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
447 for (regno
= 0; regno
< 16; regno
++)
448 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
453 offset
= foffset
+ nregs
* 4;
454 /* FIXME : leaf_function_p below is too strong.
455 What we really need to know there is if there could be pending
456 stack adjustment needed at that point. */
457 restore_from_sp
= ! frame_pointer_needed
458 || (! current_function_calls_alloca
&& leaf_function_p ());
459 if (offset
+ fsize
>= 0x8000
461 && (mask
|| fmask
|| fpoffset
))
464 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
466 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
470 if (TARGET_5200
|| nregs
<= 2)
472 /* Restore each separately in the same order moveml does.
473 Using two movel instructions instead of a single moveml
474 is about 15% faster for the 68020 and 68030 at no expense
479 /* Undo the work from above. */
480 for (i
= 0; i
< 16; i
++)
486 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
488 reg_names
[FRAME_POINTER_REGNUM
],
491 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
492 reg_names
[FRAME_POINTER_REGNUM
],
493 offset
+ fsize
, reg_names
[i
]);
496 else if (restore_from_sp
)
499 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
502 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
509 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
511 reg_names
[FRAME_POINTER_REGNUM
],
514 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
515 reg_names
[FRAME_POINTER_REGNUM
],
516 offset
+ fsize
, reg_names
[i
]);
527 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
529 reg_names
[FRAME_POINTER_REGNUM
],
532 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
533 reg_names
[FRAME_POINTER_REGNUM
],
534 offset
+ fsize
, mask
);
537 else if (restore_from_sp
)
540 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
542 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
548 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
550 reg_names
[FRAME_POINTER_REGNUM
],
553 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
554 reg_names
[FRAME_POINTER_REGNUM
],
555 offset
+ fsize
, mask
);
564 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
566 reg_names
[FRAME_POINTER_REGNUM
],
569 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
570 reg_names
[FRAME_POINTER_REGNUM
],
571 foffset
+ fsize
, fmask
);
574 else if (restore_from_sp
)
577 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
579 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
585 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
587 reg_names
[FRAME_POINTER_REGNUM
],
590 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
591 reg_names
[FRAME_POINTER_REGNUM
],
592 foffset
+ fsize
, fmask
);
597 for (regno
= 55; regno
>= 24; regno
--)
598 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
603 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
605 reg_names
[FRAME_POINTER_REGNUM
],
608 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
609 reg_names
[FRAME_POINTER_REGNUM
],
610 fpoffset
+ fsize
, reg_names
[regno
]);
613 else if (restore_from_sp
)
616 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
619 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
626 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
628 reg_names
[FRAME_POINTER_REGNUM
],
631 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
632 reg_names
[FRAME_POINTER_REGNUM
],
633 fpoffset
+ fsize
, reg_names
[regno
]);
638 if (frame_pointer_needed
)
639 fprintf (stream
, "\tunlk %s\n",
640 reg_names
[FRAME_POINTER_REGNUM
]);
643 if (fsize
+ 4 < 0x8000)
648 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
650 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
655 /* asm_fprintf() cannot handle %. */
657 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
659 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
665 /* asm_fprintf() cannot handle %. */
667 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
669 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
673 if (current_function_pops_args
)
674 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
676 fprintf (stream
, "\trts\n");
679 /* Similar to general_operand, but exclude stack_pointer_rtx. */
682 not_sp_operand (op
, mode
)
684 enum machine_mode mode
;
686 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
689 /* Return TRUE if X is a valid comparison operator for the dbcc
692 Note it rejects floating point comparison operators.
693 (In the future we could use Fdbcc).
695 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
698 valid_dbcc_comparison_p (x
, mode
)
700 enum machine_mode mode
;
702 switch (GET_CODE (x
))
704 case EQ
: case NE
: case GTU
: case LTU
:
708 /* Reject some when CC_NO_OVERFLOW is set. This may be over
710 case GT
: case LT
: case GE
: case LE
:
711 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
717 /* Return non-zero if flags are currently in the 68881 flag register. */
721 /* We could add support for these in the future */
722 return cc_status
.flags
& CC_IN_68881
;
725 /* Output a dbCC; jCC sequence. Note we do not handle the
726 floating point version of this sequence (Fdbcc). We also
727 do not handle alternative conditions when CC_NO_OVERFLOW is
728 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
729 kick those out before we get here. */
731 output_dbcc_and_branch (operands
)
734 switch (GET_CODE (operands
[3]))
738 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
740 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
746 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
748 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
754 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
756 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
762 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
764 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
770 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
772 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
778 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
780 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
786 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
788 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
794 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
796 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
802 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
804 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
810 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
812 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
820 /* If the decrement is to be done in SImode, then we have
821 to compensate for the fact that dbcc decrements in HImode. */
822 switch (GET_MODE (operands
[0]))
826 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
828 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
841 output_scc_di(op
, operand1
, operand2
, dest
)
848 enum rtx_code op_code
= GET_CODE (op
);
850 /* The m68k cmp.l instruction requires operand1 to be a reg as used
851 below. Swap the operands and change the op if these requirements
852 are not fulfilled. */
853 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
859 op_code
= swap_condition (op_code
);
861 loperands
[0] = operand1
;
862 if (GET_CODE (operand1
) == REG
)
863 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
865 loperands
[1] = adj_offsettable_operand (operand1
, 4);
866 if (operand2
!= const0_rtx
)
868 loperands
[2] = operand2
;
869 if (GET_CODE (operand2
) == REG
)
870 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
872 loperands
[3] = adj_offsettable_operand (operand2
, 4);
874 loperands
[4] = gen_label_rtx();
875 if (operand2
!= const0_rtx
)
878 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
880 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
884 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
886 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
891 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
893 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
900 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
901 CODE_LABEL_NUMBER (loperands
[4]));
902 output_asm_insn ("seq %5", loperands
);
906 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
907 CODE_LABEL_NUMBER (loperands
[4]));
908 output_asm_insn ("sne %5", loperands
);
912 loperands
[6] = gen_label_rtx();
914 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
916 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
918 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
919 CODE_LABEL_NUMBER (loperands
[4]));
920 output_asm_insn ("sgt %5", loperands
);
921 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
922 CODE_LABEL_NUMBER (loperands
[6]));
926 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
927 CODE_LABEL_NUMBER (loperands
[4]));
928 output_asm_insn ("shi %5", loperands
);
932 loperands
[6] = gen_label_rtx();
934 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
936 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
938 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
939 CODE_LABEL_NUMBER (loperands
[4]));
940 output_asm_insn ("slt %5", loperands
);
941 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
942 CODE_LABEL_NUMBER (loperands
[6]));
946 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
947 CODE_LABEL_NUMBER (loperands
[4]));
948 output_asm_insn ("scs %5", loperands
);
952 loperands
[6] = gen_label_rtx();
954 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
956 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
958 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
959 CODE_LABEL_NUMBER (loperands
[4]));
960 output_asm_insn ("sge %5", loperands
);
961 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
962 CODE_LABEL_NUMBER (loperands
[6]));
966 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
967 CODE_LABEL_NUMBER (loperands
[4]));
968 output_asm_insn ("scc %5", loperands
);
972 loperands
[6] = gen_label_rtx();
974 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
976 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
978 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
979 CODE_LABEL_NUMBER (loperands
[4]));
980 output_asm_insn ("sle %5", loperands
);
981 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
982 CODE_LABEL_NUMBER (loperands
[6]));
986 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
987 CODE_LABEL_NUMBER (loperands
[4]));
988 output_asm_insn ("sls %5", loperands
);
998 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1000 rtx countop
, dataop
;
1004 operands
[0] = countop
;
1005 operands
[1] = dataop
;
1007 if (GET_CODE (countop
) == CONST_INT
)
1009 register int count
= INTVAL (countop
);
1010 /* If COUNT is bigger than size of storage unit in use,
1011 advance to the containing unit of same size. */
1012 if (count
> signpos
)
1014 int offset
= (count
& ~signpos
) / 8;
1015 count
= count
& signpos
;
1016 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1018 if (count
== signpos
)
1019 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1021 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1023 /* These three statements used to use next_insns_test_no...
1024 but it appears that this should do the same job. */
1026 && next_insn_tests_no_inequality (insn
))
1029 && next_insn_tests_no_inequality (insn
))
1032 && next_insn_tests_no_inequality (insn
))
1035 cc_status
.flags
= CC_NOT_NEGATIVE
;
1037 return "btst %0,%1";
1040 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1041 reference and a constant. */
1044 symbolic_operand (op
, mode
)
1046 enum machine_mode mode
;
1048 switch (GET_CODE (op
))
1056 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1057 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1058 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1060 #if 0 /* Deleted, with corresponding change in m68k.h,
1061 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1063 return GET_MODE (op
) == mode
;
1071 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1074 extend_operator(x
, mode
)
1076 enum machine_mode mode
;
1078 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1080 switch (GET_CODE(x
))
1091 /* Legitimize PIC addresses. If the address is already
1092 position-independent, we return ORIG. Newly generated
1093 position-independent addresses go to REG. If we need more
1094 than one register, we lose.
1096 An address is legitimized by making an indirect reference
1097 through the Global Offset Table with the name of the symbol
1100 The assembler and linker are responsible for placing the
1101 address of the symbol in the GOT. The function prologue
1102 is responsible for initializing a5 to the starting address
1105 The assembler is also responsible for translating a symbol name
1106 into a constant displacement from the start of the GOT.
1108 A quick example may make things a little clearer:
1110 When not generating PIC code to store the value 12345 into _foo
1111 we would generate the following code:
1115 When generating PIC two transformations are made. First, the compiler
1116 loads the address of foo into a register. So the first transformation makes:
1121 The code in movsi will intercept the lea instruction and call this
1122 routine which will transform the instructions into:
1124 movel a5@(_foo:w), a0
1128 That (in a nutshell) is how *all* symbol and label references are
1132 legitimize_pic_address (orig
, mode
, reg
)
1134 enum machine_mode mode
;
1138 /* First handle a simple SYMBOL_REF or LABEL_REF */
1139 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1144 pic_ref
= gen_rtx (MEM
, Pmode
,
1145 gen_rtx (PLUS
, Pmode
,
1146 pic_offset_table_rtx
, orig
));
1147 current_function_uses_pic_offset_table
= 1;
1148 RTX_UNCHANGING_P (pic_ref
) = 1;
1149 emit_move_insn (reg
, pic_ref
);
1152 else if (GET_CODE (orig
) == CONST
)
1156 /* Make sure this is CONST has not already been legitimized */
1157 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1158 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1164 /* legitimize both operands of the PLUS */
1165 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1167 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1168 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1169 base
== reg
? 0 : reg
);
1173 if (GET_CODE (orig
) == CONST_INT
)
1174 return plus_constant_for_output (base
, INTVAL (orig
));
1175 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1176 /* Likewise, should we set special REG_NOTEs here? */
1182 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1184 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1187 const_method (constant
)
1193 i
= INTVAL (constant
);
1197 /* The Coldfire doesn't have byte or word operations. */
1198 /* FIXME: This may not be useful for the m68060 either */
1201 /* if -256 < N < 256 but N is not in range for a moveq
1202 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1203 if (USE_MOVQ (i
^ 0xff))
1205 /* Likewise, try with not.w */
1206 if (USE_MOVQ (i
^ 0xffff))
1208 /* This is the only value where neg.w is useful */
1211 /* Try also with swap */
1213 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1216 /* Otherwise, use move.l */
1220 const_int_cost (constant
)
1223 switch (const_method (constant
))
1226 /* Constants between -128 and 127 are cheap due to moveq */
1232 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1242 output_move_const_into_data_reg (operands
)
1247 i
= INTVAL (operands
[1]);
1248 switch (const_method (operands
[1]))
1251 #if defined (MOTOROLA) && !defined (CRDS)
1252 return "moveq%.l %1,%0";
1254 return "moveq %1,%0";
1257 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1258 #if defined (MOTOROLA) && !defined (CRDS)
1259 return "moveq%.l %1,%0\n\tnot%.b %0";
1261 return "moveq %1,%0\n\tnot%.b %0";
1264 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1265 #if defined (MOTOROLA) && !defined (CRDS)
1266 return "moveq%.l %1,%0\n\tnot%.w %0";
1268 return "moveq %1,%0\n\tnot%.w %0";
1271 #if defined (MOTOROLA) && !defined (CRDS)
1272 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1274 return "moveq %#-128,%0\n\tneg%.w %0";
1280 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1281 #if defined (MOTOROLA) && !defined (CRDS)
1282 return "moveq%.l %1,%0\n\tswap %0";
1284 return "moveq %1,%0\n\tswap %0";
1288 return "move%.l %1,%0";
1295 output_move_simode_const (operands
)
1298 if (operands
[1] == const0_rtx
1299 && (DATA_REG_P (operands
[0])
1300 || GET_CODE (operands
[0]) == MEM
)
1301 /* clr insns on 68000 read before writing.
1302 This isn't so on the 68010, but we have no TARGET_68010. */
1304 || !(GET_CODE (operands
[0]) == MEM
1305 && MEM_VOLATILE_P (operands
[0]))))
1307 else if (DATA_REG_P (operands
[0]))
1308 return output_move_const_into_data_reg (operands
);
1309 else if (ADDRESS_REG_P (operands
[0])
1310 && INTVAL (operands
[1]) < 0x8000
1311 && INTVAL (operands
[1]) >= -0x8000)
1312 return "move%.w %1,%0";
1313 else if (GET_CODE (operands
[0]) == MEM
1314 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1315 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1316 && INTVAL (operands
[1]) < 0x8000
1317 && INTVAL (operands
[1]) >= -0x8000)
1319 return "move%.l %1,%0";
1322 /* Return the best assembler insn template
1323 for moving operands[1] into operands[0] as a fullword. */
1326 singlemove_string (operands
)
1329 #ifdef SUPPORT_SUN_FPA
1330 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1331 return "fpmoves %1,%0";
1333 if (GET_CODE (operands
[1]) == CONST_INT
)
1334 return output_move_simode_const (operands
);
1335 return "move%.l %1,%0";
1339 /* Output assembler code to perform a doubleword move insn
1340 with operands OPERANDS. */
1343 output_move_double (operands
)
1348 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1353 rtx addreg0
= 0, addreg1
= 0;
1354 int dest_overlapped_low
= 0;
1355 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1360 /* First classify both operands. */
1362 if (REG_P (operands
[0]))
1364 else if (offsettable_memref_p (operands
[0]))
1366 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1368 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1370 else if (GET_CODE (operands
[0]) == MEM
)
1375 if (REG_P (operands
[1]))
1377 else if (CONSTANT_P (operands
[1]))
1379 else if (offsettable_memref_p (operands
[1]))
1381 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1383 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1385 else if (GET_CODE (operands
[1]) == MEM
)
1390 /* Check for the cases that the operand constraints are not
1391 supposed to allow to happen. Abort if we get one,
1392 because generating code for these cases is painful. */
1394 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1397 /* If one operand is decrementing and one is incrementing
1398 decrement the former register explicitly
1399 and change that operand into ordinary indexing. */
1401 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1403 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1405 output_asm_insn ("sub%.l %#12,%0", operands
);
1407 output_asm_insn ("subq%.l %#8,%0", operands
);
1408 if (GET_MODE (operands
[1]) == XFmode
)
1409 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1410 else if (GET_MODE (operands
[0]) == DFmode
)
1411 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1413 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1416 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1418 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1420 output_asm_insn ("sub%.l %#12,%1", operands
);
1422 output_asm_insn ("subq%.l %#8,%1", operands
);
1423 if (GET_MODE (operands
[1]) == XFmode
)
1424 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1425 else if (GET_MODE (operands
[1]) == DFmode
)
1426 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1428 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1432 /* If an operand is an unoffsettable memory ref, find a register
1433 we can increment temporarily to make it refer to the second word. */
1435 if (optype0
== MEMOP
)
1436 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1438 if (optype1
== MEMOP
)
1439 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1441 /* Ok, we can do one word at a time.
1442 Normally we do the low-numbered word first,
1443 but if either operand is autodecrementing then we
1444 do the high-numbered word first.
1446 In either case, set up in LATEHALF the operands to use
1447 for the high-numbered word and in some cases alter the
1448 operands in OPERANDS to be suitable for the low-numbered word. */
1452 if (optype0
== REGOP
)
1454 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1455 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1457 else if (optype0
== OFFSOP
)
1459 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1460 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1464 middlehalf
[0] = operands
[0];
1465 latehalf
[0] = operands
[0];
1468 if (optype1
== REGOP
)
1470 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1471 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1473 else if (optype1
== OFFSOP
)
1475 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1476 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1478 else if (optype1
== CNSTOP
)
1480 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1485 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1486 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1487 operands
[1] = GEN_INT (l
[0]);
1488 middlehalf
[1] = GEN_INT (l
[1]);
1489 latehalf
[1] = GEN_INT (l
[2]);
1491 else if (CONSTANT_P (operands
[1]))
1493 /* actually, no non-CONST_DOUBLE constant should ever
1496 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1497 latehalf
[1] = constm1_rtx
;
1499 latehalf
[1] = const0_rtx
;
1504 middlehalf
[1] = operands
[1];
1505 latehalf
[1] = operands
[1];
1509 /* size is not 12: */
1511 if (optype0
== REGOP
)
1512 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1513 else if (optype0
== OFFSOP
)
1514 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1516 latehalf
[0] = operands
[0];
1518 if (optype1
== REGOP
)
1519 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1520 else if (optype1
== OFFSOP
)
1521 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1522 else if (optype1
== CNSTOP
)
1523 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1525 latehalf
[1] = operands
[1];
1528 /* If insn is effectively movd N(sp),-(sp) then we will do the
1529 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1530 for the low word as well, to compensate for the first decrement of sp. */
1531 if (optype0
== PUSHOP
1532 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1533 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1534 operands
[1] = middlehalf
[1] = latehalf
[1];
1536 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1537 if the upper part of reg N does not appear in the MEM, arrange to
1538 emit the move late-half first. Otherwise, compute the MEM address
1539 into the upper part of N and use that as a pointer to the memory
1541 if (optype0
== REGOP
1542 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1544 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1546 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1547 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1549 /* If both halves of dest are used in the src memory address,
1550 compute the address into latehalf of dest.
1551 Note that this can't happen if the dest is two data regs. */
1553 xops
[0] = latehalf
[0];
1554 xops
[1] = XEXP (operands
[1], 0);
1555 output_asm_insn ("lea %a1,%0", xops
);
1556 if( GET_MODE (operands
[1]) == XFmode
)
1558 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1559 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1560 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1564 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1565 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1569 && reg_overlap_mentioned_p (middlehalf
[0],
1570 XEXP (operands
[1], 0)))
1572 /* Check for two regs used by both source and dest.
1573 Note that this can't happen if the dest is all data regs.
1574 It can happen if the dest is d6, d7, a0.
1575 But in that case, latehalf is an addr reg, so
1576 the code at compadr does ok. */
1578 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1579 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1582 /* JRV says this can't happen: */
1583 if (addreg0
|| addreg1
)
1586 /* Only the middle reg conflicts; simply put it last. */
1587 output_asm_insn (singlemove_string (operands
), operands
);
1588 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1589 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1592 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1593 /* If the low half of dest is mentioned in the source memory
1594 address, the arrange to emit the move late half first. */
1595 dest_overlapped_low
= 1;
1598 /* If one or both operands autodecrementing,
1599 do the two words, high-numbered first. */
1601 /* Likewise, the first move would clobber the source of the second one,
1602 do them in the other order. This happens only for registers;
1603 such overlap can't happen in memory unless the user explicitly
1604 sets it up, and that is an undefined circumstance. */
1606 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1607 || (optype0
== REGOP
&& optype1
== REGOP
1608 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1609 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1610 || dest_overlapped_low
)
1612 /* Make any unoffsettable addresses point at high-numbered word. */
1616 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1618 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1623 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1625 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1629 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1631 /* Undo the adds we just did. */
1633 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1635 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1639 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1641 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1643 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1646 /* Do low-numbered word. */
1647 return singlemove_string (operands
);
1650 /* Normal case: do the two words, low-numbered first. */
1652 output_asm_insn (singlemove_string (operands
), operands
);
1654 /* Do the middle one of the three words for long double */
1658 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1660 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1662 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1665 /* Make any unoffsettable addresses point at high-numbered word. */
1667 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1669 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1672 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1674 /* Undo the adds we just did. */
1678 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1680 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1685 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1687 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1693 /* Return a REG that occurs in ADDR with coefficient 1.
1694 ADDR can be effectively incremented by incrementing REG. */
1697 find_addr_reg (addr
)
1700 while (GET_CODE (addr
) == PLUS
)
1702 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1703 addr
= XEXP (addr
, 0);
1704 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1705 addr
= XEXP (addr
, 1);
1706 else if (CONSTANT_P (XEXP (addr
, 0)))
1707 addr
= XEXP (addr
, 1);
1708 else if (CONSTANT_P (XEXP (addr
, 1)))
1709 addr
= XEXP (addr
, 0);
1713 if (GET_CODE (addr
) == REG
)
1718 /* Store in cc_status the expressions that the condition codes will
1719 describe after execution of an instruction whose pattern is EXP.
1720 Do not alter them if the instruction would not alter the cc's. */
1722 /* On the 68000, all the insns to store in an address register fail to
1723 set the cc's. However, in some cases these instructions can make it
1724 possibly invalid to use the saved cc's. In those cases we clear out
1725 some or all of the saved cc's so they won't be used. */
1727 notice_update_cc (exp
, insn
)
1731 /* If the cc is being set from the fpa and the expression is not an
1732 explicit floating point test instruction (which has code to deal with
1733 this), reinit the CC. */
1734 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1735 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1736 && !(GET_CODE (exp
) == PARALLEL
1737 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1738 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1742 else if (GET_CODE (exp
) == SET
)
1744 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1748 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1750 if (cc_status
.value1
1751 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1752 cc_status
.value1
= 0;
1753 if (cc_status
.value2
1754 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1755 cc_status
.value2
= 0;
1757 else if (!FP_REG_P (SET_DEST (exp
))
1758 && SET_DEST (exp
) != cc0_rtx
1759 && (FP_REG_P (SET_SRC (exp
))
1760 || GET_CODE (SET_SRC (exp
)) == FIX
1761 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1762 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1766 /* A pair of move insns doesn't produce a useful overall cc. */
1767 else if (!FP_REG_P (SET_DEST (exp
))
1768 && !FP_REG_P (SET_SRC (exp
))
1769 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1770 && (GET_CODE (SET_SRC (exp
)) == REG
1771 || GET_CODE (SET_SRC (exp
)) == MEM
1772 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1776 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1780 else if (XEXP (exp
, 0) != pc_rtx
)
1782 cc_status
.flags
= 0;
1783 cc_status
.value1
= XEXP (exp
, 0);
1784 cc_status
.value2
= XEXP (exp
, 1);
1787 else if (GET_CODE (exp
) == PARALLEL
1788 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1790 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1792 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1794 cc_status
.flags
= 0;
1795 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1796 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1801 if (cc_status
.value2
!= 0
1802 && ADDRESS_REG_P (cc_status
.value2
)
1803 && GET_MODE (cc_status
.value2
) == QImode
)
1805 if (cc_status
.value2
!= 0
1806 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1807 switch (GET_CODE (cc_status
.value2
))
1809 case PLUS
: case MINUS
: case MULT
:
1810 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1811 #if 0 /* These instructions always clear the overflow bit */
1812 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1813 case ROTATE
: case ROTATERT
:
1815 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1816 cc_status
.flags
|= CC_NO_OVERFLOW
;
1819 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1820 ends with a move insn moving r2 in r2's mode.
1821 Thus, the cc's are set for r2.
1822 This can set N bit spuriously. */
1823 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1825 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1827 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1828 cc_status
.value2
= 0;
1829 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1830 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1831 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1832 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1833 cc_status
.flags
= CC_IN_68881
;
1837 output_move_const_double (operands
)
1840 #ifdef SUPPORT_SUN_FPA
1841 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1843 int code
= standard_sun_fpa_constant_p (operands
[1]);
1847 static char buf
[40];
1849 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1852 return "fpmove%.d %1,%0";
1857 int code
= standard_68881_constant_p (operands
[1]);
1861 static char buf
[40];
1863 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1866 return "fmove%.d %1,%0";
1871 output_move_const_single (operands
)
1874 #ifdef SUPPORT_SUN_FPA
1877 int code
= standard_sun_fpa_constant_p (operands
[1]);
1881 static char buf
[40];
1883 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1886 return "fpmove%.s %1,%0";
1889 #endif /* defined SUPPORT_SUN_FPA */
1891 int code
= standard_68881_constant_p (operands
[1]);
1895 static char buf
[40];
1897 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1900 return "fmove%.s %f1,%0";
1904 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1905 from the "fmovecr" instruction.
1906 The value, anded with 0xff, gives the code to use in fmovecr
1907 to get the desired constant. */
1909 /* This code has been fixed for cross-compilation. */
1911 static int inited_68881_table
= 0;
1913 char *strings_68881
[7] = {
1923 int codes_68881
[7] = {
1933 REAL_VALUE_TYPE values_68881
[7];
1935 /* Set up values_68881 array by converting the decimal values
1936 strings_68881 to binary. */
1943 enum machine_mode mode
;
1946 for (i
= 0; i
< 7; i
++)
1950 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
1951 values_68881
[i
] = r
;
1953 inited_68881_table
= 1;
1957 standard_68881_constant_p (x
)
1962 enum machine_mode mode
;
1964 #ifdef NO_ASM_FMOVECR
1968 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
1972 #ifndef REAL_ARITHMETIC
1973 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1974 if (! flag_pretend_float
)
1979 if (! inited_68881_table
)
1980 init_68881_table ();
1982 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1984 for (i
= 0; i
< 6; i
++)
1986 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
1987 return (codes_68881
[i
]);
1990 if (GET_MODE (x
) == SFmode
)
1993 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
1994 return (codes_68881
[6]);
1996 /* larger powers of ten in the constants ram are not used
1997 because they are not equal to a `double' C constant. */
2001 /* If X is a floating-point constant, return the logarithm of X base 2,
2002 or 0 if X is not a power of 2. */
2005 floating_exact_log2 (x
)
2008 REAL_VALUE_TYPE r
, r1
;
2011 #ifndef REAL_ARITHMETIC
2012 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2013 if (! flag_pretend_float
)
2018 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2020 if (REAL_VALUES_LESS (r
, dconst0
))
2025 while (REAL_VALUES_LESS (r1
, r
))
2027 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2028 if (REAL_VALUES_EQUAL (r1
, r
))
2035 #ifdef SUPPORT_SUN_FPA
2036 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2037 from the Sun FPA's constant RAM.
2038 The value returned, anded with 0x1ff, gives the code to use in fpmove
2039 to get the desired constant. */
2041 static int inited_FPA_table
= 0;
2043 char *strings_FPA
[38] = {
2044 /* small rationals */
2057 /* Decimal equivalents of double precision values */
2058 "2.718281828459045091", /* D_E */
2059 "6.283185307179586477", /* 2 pi */
2060 "3.141592653589793116", /* D_PI */
2061 "1.570796326794896619", /* pi/2 */
2062 "1.414213562373095145", /* D_SQRT2 */
2063 "0.7071067811865475244", /* 1/sqrt(2) */
2064 "-1.570796326794896619", /* -pi/2 */
2065 "1.442695040888963387", /* D_LOG2ofE */
2066 "3.321928024887362182", /* D_LOG2of10 */
2067 "0.6931471805599452862", /* D_LOGEof2 */
2068 "2.302585092994045901", /* D_LOGEof10 */
2069 "0.3010299956639811980", /* D_LOG10of2 */
2070 "0.4342944819032518167", /* D_LOG10ofE */
2071 /* Decimal equivalents of single precision values */
2072 "2.718281745910644531", /* S_E */
2073 "6.283185307179586477", /* 2 pi */
2074 "3.141592741012573242", /* S_PI */
2075 "1.570796326794896619", /* pi/2 */
2076 "1.414213538169860840", /* S_SQRT2 */
2077 "0.7071067811865475244", /* 1/sqrt(2) */
2078 "-1.570796326794896619", /* -pi/2 */
2079 "1.442695021629333496", /* S_LOG2ofE */
2080 "3.321928024291992188", /* S_LOG2of10 */
2081 "0.6931471824645996094", /* S_LOGEof2 */
2082 "2.302585124969482442", /* S_LOGEof10 */
2083 "0.3010300099849700928", /* S_LOG10of2 */
2084 "0.4342944920063018799", /* S_LOG10ofE */
2088 int codes_FPA
[38] = {
2089 /* small rationals */
2102 /* double precision */
2116 /* single precision */
2132 REAL_VALUE_TYPE values_FPA
[38];
2134 /* This code has been fixed for cross-compilation. */
2139 enum machine_mode mode
;
2144 for (i
= 0; i
< 38; i
++)
2148 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2151 inited_FPA_table
= 1;
2156 standard_sun_fpa_constant_p (x
)
2162 #ifndef REAL_ARITHMETIC
2163 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2164 if (! flag_pretend_float
)
2169 if (! inited_FPA_table
)
2172 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2174 for (i
=0; i
<12; i
++)
2176 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2177 return (codes_FPA
[i
]);
2180 if (GET_MODE (x
) == SFmode
)
2182 for (i
=25; i
<38; i
++)
2184 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2185 return (codes_FPA
[i
]);
2190 for (i
=12; i
<25; i
++)
2192 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2193 return (codes_FPA
[i
]);
2198 #endif /* define SUPPORT_SUN_FPA */
2200 /* A C compound statement to output to stdio stream STREAM the
2201 assembler syntax for an instruction operand X. X is an RTL
2204 CODE is a value that can be used to specify one of several ways
2205 of printing the operand. It is used when identical operands
2206 must be printed differently depending on the context. CODE
2207 comes from the `%' specification that was used to request
2208 printing of the operand. If the specification was just `%DIGIT'
2209 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2210 is the ASCII code for LTR.
2212 If X is a register, this macro should print the register's name.
2213 The names can be found in an array `reg_names' whose type is
2214 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2216 When the machine description has a specification `%PUNCT' (a `%'
2217 followed by a punctuation character), this macro is called with
2218 a null pointer for X and the punctuation character for CODE.
2220 The m68k specific codes are:
2222 '.' for dot needed in Motorola-style opcode names.
2223 '-' for an operand pushing on the stack:
2224 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2225 '+' for an operand pushing on the stack:
2226 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2227 '@' for a reference to the top word on the stack:
2228 sp@, (sp) or (%sp) depending on the style of syntax.
2229 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2230 but & in SGS syntax).
2231 '!' for the cc register (used in an `and to cc' insn).
2232 '$' for the letter `s' in an op code, but only on the 68040.
2233 '&' for the letter `d' in an op code, but only on the 68040.
2234 '/' for register prefix needed by longlong.h.
2236 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2237 'd' to force memory addressing to be absolute, not relative.
2238 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2239 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2240 than directly). Second part of 'y' below.
2241 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2242 or print pair of registers as rx:ry.
2243 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2244 CONST_DOUBLE's as SunFPA constant RAM registers if
2245 possible, so it should not be used except for the SunFPA.
2250 print_operand (file
, op
, letter
)
2251 FILE *file
; /* file to write to */
2252 rtx op
; /* operand to print */
2253 int letter
; /* %<letter> or 0 */
2260 asm_fprintf (file
, ".");
2263 else if (letter
== '#')
2265 asm_fprintf (file
, "%0I");
2267 else if (letter
== '-')
2270 asm_fprintf (file
, "-(%Rsp)");
2272 asm_fprintf (file
, "%Rsp@-");
2275 else if (letter
== '+')
2278 asm_fprintf (file
, "(%Rsp)+");
2280 asm_fprintf (file
, "%Rsp@+");
2283 else if (letter
== '@')
2286 asm_fprintf (file
, "(%Rsp)");
2288 asm_fprintf (file
, "%Rsp@");
2291 else if (letter
== '!')
2293 asm_fprintf (file
, "%Rfpcr");
2295 else if (letter
== '$')
2297 if (TARGET_68040_ONLY
)
2299 fprintf (file
, "s");
2302 else if (letter
== '&')
2304 if (TARGET_68040_ONLY
)
2306 fprintf (file
, "d");
2309 else if (letter
== '/')
2311 asm_fprintf (file
, "%R");
2313 else if (GET_CODE (op
) == REG
)
2315 #ifdef SUPPORT_SUN_FPA
2317 && (letter
== 'y' || letter
== 'x')
2318 && GET_MODE (op
) == DFmode
)
2320 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2321 reg_names
[REGNO (op
)+1]);
2327 /* Print out the second register name of a register pair.
2328 I.e., R (6) => 7. */
2329 fputs (reg_names
[REGNO (op
) + 1], file
);
2331 fputs (reg_names
[REGNO (op
)], file
);
2334 else if (GET_CODE (op
) == MEM
)
2336 output_address (XEXP (op
, 0));
2337 if (letter
== 'd' && ! TARGET_68020
2338 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2339 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2340 && INTVAL (XEXP (op
, 0)) < 0x8000
2341 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2344 fprintf (file
, ".l");
2346 fprintf (file
, ":l");
2350 #ifdef SUPPORT_SUN_FPA
2351 else if ((letter
== 'y' || letter
== 'w')
2352 && GET_CODE (op
) == CONST_DOUBLE
2353 && (i
= standard_sun_fpa_constant_p (op
)))
2355 fprintf (file
, "%%%d", i
& 0x1ff);
2358 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2361 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2362 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2364 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2367 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2368 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2370 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2373 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2374 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2378 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2383 /* A C compound statement to output to stdio stream STREAM the
2384 assembler syntax for an instruction operand that is a memory
2385 reference whose address is ADDR. ADDR is an RTL expression.
2387 Note that this contains a kludge that knows that the only reason
2388 we have an address (plus (label_ref...) (reg...)) when not generating
2389 PIC code is in the insn before a tablejump, and we know that m68k.md
2390 generates a label LInnn: on such an insn.
2392 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2393 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2395 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2396 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2397 we want. This difference can be accommodated by using an assembler
2398 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2399 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2400 macro. See m68k/sgs.h for an example; for versions without the bug.
2401 Some assemblers refuse all the above solutions. The workaround is to
2402 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2405 They also do not like things like "pea 1.w", so we simple leave off
2406 the .w on small constants.
2408 This routine is responsible for distinguishing between -fpic and -fPIC
2409 style relocations in an address. When generating -fpic code the
2410 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2411 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2413 #ifndef ASM_OUTPUT_CASE_FETCH
2416 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2417 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2419 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2420 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2423 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2424 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2426 #endif /* ASM_OUTPUT_CASE_FETCH */
2429 print_operand_address (file
, addr
)
2433 register rtx reg1
, reg2
, breg
, ireg
;
2436 switch (GET_CODE (addr
))
2440 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2442 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2447 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2449 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2454 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2456 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2460 reg1
= reg2
= ireg
= breg
= offset
= 0;
2461 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2463 offset
= XEXP (addr
, 0);
2464 addr
= XEXP (addr
, 1);
2466 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2468 offset
= XEXP (addr
, 1);
2469 addr
= XEXP (addr
, 0);
2471 if (GET_CODE (addr
) != PLUS
)
2475 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2477 reg1
= XEXP (addr
, 0);
2478 addr
= XEXP (addr
, 1);
2480 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2482 reg1
= XEXP (addr
, 1);
2483 addr
= XEXP (addr
, 0);
2485 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2487 reg1
= XEXP (addr
, 0);
2488 addr
= XEXP (addr
, 1);
2490 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2492 reg1
= XEXP (addr
, 1);
2493 addr
= XEXP (addr
, 0);
2495 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2497 reg1
= XEXP (addr
, 0);
2498 addr
= XEXP (addr
, 1);
2500 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2502 reg1
= XEXP (addr
, 1);
2503 addr
= XEXP (addr
, 0);
2505 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2506 || GET_CODE (addr
) == SIGN_EXTEND
)
2518 #if 0 /* for OLD_INDEXING */
2519 else if (GET_CODE (addr
) == PLUS
)
2521 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2523 reg2
= XEXP (addr
, 0);
2524 addr
= XEXP (addr
, 1);
2526 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2528 reg2
= XEXP (addr
, 1);
2529 addr
= XEXP (addr
, 0);
2541 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2542 || GET_CODE (reg1
) == MULT
))
2543 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2548 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2553 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2554 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2557 if (GET_CODE (ireg
) == MULT
)
2559 scale
= INTVAL (XEXP (ireg
, 1));
2560 ireg
= XEXP (ireg
, 0);
2562 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2564 ASM_OUTPUT_CASE_FETCH (file
,
2565 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2566 reg_names
[REGNO (XEXP (ireg
, 0))]);
2567 fprintf (file
, "w");
2571 ASM_OUTPUT_CASE_FETCH (file
,
2572 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2573 reg_names
[REGNO (ireg
)]);
2574 fprintf (file
, "l");
2579 fprintf (file
, "*%d", scale
);
2581 fprintf (file
, ":%d", scale
);
2587 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2588 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2590 ASM_OUTPUT_CASE_FETCH (file
,
2591 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2592 reg_names
[REGNO (breg
)]);
2593 fprintf (file
, "l)");
2596 if (ireg
!= 0 || breg
!= 0)
2603 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2610 output_addr_const (file
, addr
);
2611 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2612 fprintf (file
, "@GOT");
2614 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2620 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2623 output_addr_const (file
, addr
);
2624 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2625 fprintf (file
, ":w");
2626 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2627 fprintf (file
, ":l");
2629 if (addr
!= 0 && ireg
!= 0)
2634 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2636 scale
= INTVAL (XEXP (ireg
, 1));
2637 ireg
= XEXP (ireg
, 0);
2639 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2642 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2644 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2650 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2652 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2658 fprintf (file
, "*%d", scale
);
2660 fprintf (file
, ":%d", scale
);
2666 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2667 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2669 ASM_OUTPUT_CASE_FETCH (file
,
2670 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2671 reg_names
[REGNO (reg1
)]);
2672 fprintf (file
, "l)");
2675 /* FALL-THROUGH (is this really what we want? */
2677 if (GET_CODE (addr
) == CONST_INT
2678 && INTVAL (addr
) < 0x8000
2679 && INTVAL (addr
) >= -0x8000)
2683 /* Many SGS assemblers croak on size specifiers for constants. */
2684 fprintf (file
, "%d", INTVAL (addr
));
2686 fprintf (file
, "%d.w", INTVAL (addr
));
2689 fprintf (file
, "%d:w", INTVAL (addr
));
2694 output_addr_const (file
, addr
);
2700 /* Check for cases where a clr insns can be omitted from code using
2701 strict_low_part sets. For example, the second clrl here is not needed:
2702 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2704 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2705 insn we are checking for redundancy. TARGET is the register set by the
2709 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2710 enum machine_mode mode
;
2716 p
= prev_nonnote_insn (first_insn
);
2720 /* If it isn't an insn, then give up. */
2721 if (GET_CODE (p
) != INSN
)
2724 if (reg_set_p (target
, p
))
2726 rtx set
= single_set (p
);
2729 /* If it isn't an easy to recognize insn, then give up. */
2733 dest
= SET_DEST (set
);
2735 /* If this sets the entire target register to zero, then our
2736 first_insn is redundant. */
2737 if (rtx_equal_p (dest
, target
)
2738 && SET_SRC (set
) == const0_rtx
)
2740 else if (GET_CODE (dest
) == STRICT_LOW_PART
2741 && GET_CODE (XEXP (dest
, 0)) == REG
2742 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2743 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2744 <= GET_MODE_SIZE (mode
)))
2745 /* This is a strict low part set which modifies less than
2746 we are using, so it is safe. */
2752 p
= prev_nonnote_insn (p
);
2759 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2760 range carefully since this predicate is used in DImode contexts. Also, we
2761 need some extra crud to make it work when hosted on 64-bit machines. */
2764 const_uint32_operand (op
, mode
)
2766 enum machine_mode mode
;
2768 #if HOST_BITS_PER_WIDE_INT > 32
2769 /* All allowed constants will fit a CONST_INT. */
2770 return (GET_CODE (op
) == CONST_INT
2771 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
2773 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
2774 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
2778 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2779 to check the range carefully since this predicate is used in DImode
2783 const_sint32_operand (op
, mode
)
2785 enum machine_mode mode
;
2787 /* All allowed constants will fit a CONST_INT. */
2788 return (GET_CODE (op
) == CONST_INT
2789 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));