1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Some output-actions in m68k.md need these. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
34 /* Needed for use_return_insn. */
37 #ifdef SUPPORT_SUN_FPA
39 /* Index into this array by (register number >> 3) to find the
40 smallest class which contains that register. */
41 enum reg_class regno_reg_class
[]
42 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
43 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
45 #endif /* defined SUPPORT_SUN_FPA */
47 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
48 if SGS_SWITCH_TABLE. */
49 int switch_table_difference_label_flag
;
51 static rtx
find_addr_reg ();
52 rtx
legitimize_pic_address ();
55 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
56 function at any time during the compilation process. In the future
57 we should try and eliminate the USE if we can easily determine that
58 all PIC references were deleted from the current function. That would
59 save an address register */
64 if (flag_pic
&& current_function_uses_pic_offset_table
)
65 emit_insn (gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
));
69 /* This function generates the assembly code for function entry.
70 STREAM is a stdio stream to output the code to.
71 SIZE is an int: how many units of temporary storage to allocate.
72 Refer to the array `regs_ever_live' to determine which registers
73 to save; `regs_ever_live[I]' is nonzero if register number I
74 is ever used in the function. This function is responsible for
75 knowing which registers should not be saved even if used. */
78 /* Note that the order of the bit mask for fmovem is the opposite
79 of the order for movem! */
83 output_function_prologue (stream
, size
)
88 register int mask
= 0;
89 int num_saved_regs
= 0;
90 extern char call_used_regs
[];
91 int fsize
= (size
+ 3) & -4;
94 if (frame_pointer_needed
)
96 /* Adding negative number is faster on the 68040. */
97 if (fsize
< 0x8000 && !TARGET_68040
)
100 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
101 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
103 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
104 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
107 else if (TARGET_68020
)
110 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
111 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
113 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
114 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
120 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
121 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
123 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
124 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
130 /* Adding negative number is faster on the 68040. */
131 if (fsize
+ 4 < 0x8000)
134 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
136 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
142 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
144 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
148 #ifdef SUPPORT_SUN_FPA
149 for (regno
= 24; regno
< 56; regno
++)
150 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
153 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
156 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
161 for (regno
= 16; regno
< 24; regno
++)
162 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
163 mask
|= 1 << (regno
- 16);
164 if ((mask
& 0xff) != 0)
167 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
169 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
173 for (regno
= 0; regno
< 16; regno
++)
174 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
176 mask
|= 1 << (15 - regno
);
179 if (frame_pointer_needed
)
181 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
186 fprintf (stream
, "\ttstl sp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
189 if (num_saved_regs
<= 2)
191 /* Store each separately in the same order moveml uses.
192 Using two movel instructions instead of a single moveml
193 is about 15% faster for the 68020 and 68030 at no expense
198 /* Undo the work from above. */
199 for (i
= 0; i
< 16; i
++)
203 "\t%Omove.l %s,-(%Rsp)\n",
205 "\tmovel %s,%Rsp@-\n",
212 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
214 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
217 if (flag_pic
&& current_function_uses_pic_offset_table
)
220 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
221 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
223 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
224 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
225 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
226 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
227 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
232 /* Return true if this function's epilogue can be output as RTL. */
239 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
242 /* Copied from output_function_epilogue (). We should probably create a
243 separate layout routine to perform the common work. */
245 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
246 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
252 /* This function generates the assembly code for function exit,
253 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
255 The function epilogue should not depend on the current stack pointer!
256 It should use the frame pointer only, if there is a frame pointer.
257 This is mandatory because of alloca; we also take advantage of it to
258 omit stack adjustments before returning. */
261 output_function_epilogue (stream
, size
)
266 register int mask
, fmask
;
268 int offset
, foffset
, fpoffset
;
269 extern char call_used_regs
[];
270 int fsize
= (size
+ 3) & -4;
272 rtx insn
= get_last_insn ();
274 /* If the last insn was a BARRIER, we don't have to write any code. */
275 if (GET_CODE (insn
) == NOTE
)
276 insn
= prev_nonnote_insn (insn
);
277 if (insn
&& GET_CODE (insn
) == BARRIER
)
279 /* Output just a no-op so that debuggers don't get confused
280 about which function the pc is in at this address. */
281 asm_fprintf (stream
, "\tnop\n");
285 #ifdef FUNCTION_EXTRA_EPILOGUE
286 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
288 nregs
= 0; fmask
= 0; fpoffset
= 0;
289 #ifdef SUPPORT_SUN_FPA
290 for (regno
= 24 ; regno
< 56 ; regno
++)
291 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
293 fpoffset
= nregs
* 8;
296 for (regno
= 16; regno
< 24; regno
++)
297 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
300 fmask
|= 1 << (23 - regno
);
302 foffset
= fpoffset
+ nregs
* 12;
304 if (frame_pointer_needed
)
305 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
306 for (regno
= 0; regno
< 16; regno
++)
307 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
312 offset
= foffset
+ nregs
* 4;
313 if (offset
+ fsize
>= 0x8000
314 && frame_pointer_needed
315 && (mask
|| fmask
|| fpoffset
))
318 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra0\n", -fsize
);
320 asm_fprintf (stream
, "\tmovel %0I%d,%Ra0\n", -fsize
);
326 /* Restore each separately in the same order moveml does.
327 Using two movel instructions instead of a single moveml
328 is about 15% faster for the 68020 and 68030 at no expense
333 /* Undo the work from above. */
334 for (i
= 0; i
< 16; i
++)
340 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra0.l),%s\n",
342 reg_names
[FRAME_POINTER_REGNUM
],
345 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra0:l),%s\n",
346 reg_names
[FRAME_POINTER_REGNUM
],
347 offset
+ fsize
, reg_names
[i
]);
350 else if (! frame_pointer_needed
)
353 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
356 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
363 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
365 reg_names
[FRAME_POINTER_REGNUM
],
368 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
369 reg_names
[FRAME_POINTER_REGNUM
],
370 offset
+ fsize
, reg_names
[i
]);
381 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra0.l),%0I0x%x\n",
383 reg_names
[FRAME_POINTER_REGNUM
],
386 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra0:l),%0I0x%x\n",
387 reg_names
[FRAME_POINTER_REGNUM
],
388 offset
+ fsize
, mask
);
391 else if (! frame_pointer_needed
)
394 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
396 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
402 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
404 reg_names
[FRAME_POINTER_REGNUM
],
407 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
408 reg_names
[FRAME_POINTER_REGNUM
],
409 offset
+ fsize
, mask
);
418 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra0.l),%0I0x%x\n",
420 reg_names
[FRAME_POINTER_REGNUM
],
423 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra0:l),%0I0x%x\n",
424 reg_names
[FRAME_POINTER_REGNUM
],
425 foffset
+ fsize
, fmask
);
428 else if (! frame_pointer_needed
)
431 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
433 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
439 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
441 reg_names
[FRAME_POINTER_REGNUM
],
444 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
445 reg_names
[FRAME_POINTER_REGNUM
],
446 foffset
+ fsize
, fmask
);
451 for (regno
= 55; regno
>= 24; regno
--)
452 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
457 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra0.l), %s\n",
459 reg_names
[FRAME_POINTER_REGNUM
],
462 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra0:l), %s\n",
463 reg_names
[FRAME_POINTER_REGNUM
],
464 fpoffset
+ fsize
, reg_names
[regno
]);
467 else if (! frame_pointer_needed
)
470 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
473 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
480 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
482 reg_names
[FRAME_POINTER_REGNUM
],
485 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
486 reg_names
[FRAME_POINTER_REGNUM
],
487 fpoffset
+ fsize
, reg_names
[regno
]);
492 if (frame_pointer_needed
)
493 fprintf (stream
, "\tunlk %s\n",
494 reg_names
[FRAME_POINTER_REGNUM
]);
497 if (fsize
+ 4 < 0x8000)
500 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
502 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
508 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
510 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
514 if (current_function_pops_args
)
515 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
517 fprintf (stream
, "\trts\n");
520 /* Similar to general_operand, but exclude stack_pointer_rtx. */
523 not_sp_operand (op
, mode
)
525 enum machine_mode mode
;
527 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
530 /* Return TRUE if X is a valid comparison operator for the dbcc
533 Note it rejects floating point comparison operators.
534 (In the future we could use Fdbcc).
536 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
539 valid_dbcc_comparison_p (x
, mode
)
541 enum machine_mode mode
;
543 /* We could add support for these in the future */
544 if (cc_prev_status
.flags
& CC_IN_68881
)
547 switch (GET_CODE (x
))
550 case EQ
: case NE
: case GTU
: case LTU
:
554 /* Reject some when CC_NO_OVERFLOW is set. This may be over
556 case GT
: case LT
: case GE
: case LE
:
557 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
563 /* Output a dbCC; jCC sequence. Note we do not handle the
564 floating point version of this sequence (Fdbcc). We also
565 do not handle alternative conditions when CC_NO_OVERFLOW is
566 set. It is assumed that valid_dbcc_comparison_p will kick
567 those out before we get here. */
569 output_dbcc_and_branch (operands
)
573 switch (GET_CODE (operands
[3]))
577 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
579 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
585 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
587 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
593 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
595 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
601 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
603 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
609 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
611 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
617 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
619 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
625 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
627 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
633 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
635 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
641 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
643 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
649 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
651 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
659 /* If the decrement is to be done in SImode, then we have
660 to compensate for the fact that dbcc decrements in HImode. */
661 switch (GET_MODE (operands
[0]))
665 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
667 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
680 output_btst (operands
, countop
, dataop
, insn
, signpos
)
686 operands
[0] = countop
;
687 operands
[1] = dataop
;
689 if (GET_CODE (countop
) == CONST_INT
)
691 register int count
= INTVAL (countop
);
692 /* If COUNT is bigger than size of storage unit in use,
693 advance to the containing unit of same size. */
696 int offset
= (count
& ~signpos
) / 8;
697 count
= count
& signpos
;
698 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
700 if (count
== signpos
)
701 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
703 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
705 /* These three statements used to use next_insns_test_no...
706 but it appears that this should do the same job. */
708 && next_insn_tests_no_inequality (insn
))
711 && next_insn_tests_no_inequality (insn
))
714 && next_insn_tests_no_inequality (insn
))
717 cc_status
.flags
= CC_NOT_NEGATIVE
;
722 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
723 reference and a constant. */
726 symbolic_operand (op
, mode
)
728 enum machine_mode mode
;
730 switch (GET_CODE (op
))
738 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
739 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
740 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
742 #if 0 /* Deleted, with corresponding change in m68k.h,
743 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
745 return GET_MODE (op
) == mode
;
754 /* Legitimize PIC addresses. If the address is already
755 position-independent, we return ORIG. Newly generated
756 position-independent addresses go to REG. If we need more
757 than one register, we lose.
759 An address is legitimized by making an indirect reference
760 through the Global Offset Table with the name of the symbol
763 The assembler and linker are responsible for placing the
764 address of the symbol in the GOT. The function prologue
765 is responsible for initializing a5 to the starting address
768 The assembler is also responsible for translating a symbol name
769 into a constant displacement from the start of the GOT.
771 A quick example may make things a little clearer:
773 When not generating PIC code to store the value 12345 into _foo
774 we would generate the following code:
778 When generating PIC two transformations are made. First, the compiler
779 loads the address of foo into a register. So the first transformation makes:
784 The code in movsi will intercept the lea instruction and call this
785 routine which will transform the instructions into:
787 movel a5@(_foo:w), a0
791 That (in a nutshell) is how *all* symbol and label references are
795 legitimize_pic_address (orig
, mode
, reg
)
797 enum machine_mode mode
;
801 /* First handle a simple SYMBOL_REF or LABEL_REF */
802 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
807 pic_ref
= gen_rtx (MEM
, Pmode
,
808 gen_rtx (PLUS
, Pmode
,
809 pic_offset_table_rtx
, orig
));
810 current_function_uses_pic_offset_table
= 1;
811 RTX_UNCHANGING_P (pic_ref
) = 1;
812 emit_move_insn (reg
, pic_ref
);
815 else if (GET_CODE (orig
) == CONST
)
819 /* Make sure this is CONST has not already been legitimized */
820 if (GET_CODE (XEXP (orig
, 0)) == PLUS
821 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
827 /* legitimize both operands of the PLUS */
828 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
830 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
831 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
832 base
== reg
? 0 : reg
);
836 if (GET_CODE (orig
) == CONST_INT
)
837 return plus_constant_for_output (base
, INTVAL (orig
));
838 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
839 /* Likewise, should we set special REG_NOTEs here? */
845 /* Return the best assembler insn template
846 for moving operands[1] into operands[0] as a fullword. */
849 singlemove_string (operands
)
852 #ifdef SUPPORT_SUN_FPA
853 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
854 return "fpmoves %1,%0";
856 if (DATA_REG_P (operands
[0])
857 && GET_CODE (operands
[1]) == CONST_INT
858 && INTVAL (operands
[1]) < 128
859 && INTVAL (operands
[1]) >= -128)
861 #if defined (MOTOROLA) && !defined (CRDS)
862 return "moveq%.l %1,%0";
864 return "moveq %1,%0";
867 if (operands
[1] != const0_rtx
)
868 return "move%.l %1,%0";
869 if (! ADDRESS_REG_P (operands
[0]))
871 return "sub%.l %0,%0";
875 /* Output assembler code to perform a doubleword move insn
876 with operands OPERANDS. */
879 output_move_double (operands
)
884 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
889 rtx addreg0
= 0, addreg1
= 0;
890 int dest_overlapped_low
= 0;
891 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
896 /* First classify both operands. */
898 if (REG_P (operands
[0]))
900 else if (offsettable_memref_p (operands
[0]))
902 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
904 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
906 else if (GET_CODE (operands
[0]) == MEM
)
911 if (REG_P (operands
[1]))
913 else if (CONSTANT_P (operands
[1]))
915 else if (offsettable_memref_p (operands
[1]))
917 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
919 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
921 else if (GET_CODE (operands
[1]) == MEM
)
926 /* Check for the cases that the operand constraints are not
927 supposed to allow to happen. Abort if we get one,
928 because generating code for these cases is painful. */
930 if (optype0
== RNDOP
|| optype1
== RNDOP
)
933 /* If one operand is decrementing and one is incrementing
934 decrement the former register explicitly
935 and change that operand into ordinary indexing. */
937 if (optype0
== PUSHOP
&& optype1
== POPOP
)
939 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
941 output_asm_insn ("sub%.l %#12,%0", operands
);
943 output_asm_insn ("subq%.l %#8,%0", operands
);
944 if (GET_MODE (operands
[1]) == XFmode
)
945 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
946 else if (GET_MODE (operands
[0]) == DFmode
)
947 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
949 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
952 if (optype0
== POPOP
&& optype1
== PUSHOP
)
954 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
956 output_asm_insn ("sub%.l %#12,%1", operands
);
958 output_asm_insn ("subq%.l %#8,%1", operands
);
959 if (GET_MODE (operands
[1]) == XFmode
)
960 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
961 else if (GET_MODE (operands
[1]) == DFmode
)
962 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
964 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
968 /* If an operand is an unoffsettable memory ref, find a register
969 we can increment temporarily to make it refer to the second word. */
971 if (optype0
== MEMOP
)
972 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
974 if (optype1
== MEMOP
)
975 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
977 /* Ok, we can do one word at a time.
978 Normally we do the low-numbered word first,
979 but if either operand is autodecrementing then we
980 do the high-numbered word first.
982 In either case, set up in LATEHALF the operands to use
983 for the high-numbered word and in some cases alter the
984 operands in OPERANDS to be suitable for the low-numbered word. */
988 if (optype0
== REGOP
)
990 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
991 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
993 else if (optype0
== OFFSOP
)
995 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
996 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1000 middlehalf
[0] = operands
[0];
1001 latehalf
[0] = operands
[0];
1004 if (optype1
== REGOP
)
1006 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1007 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1009 else if (optype1
== OFFSOP
)
1011 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1012 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1014 else if (optype1
== CNSTOP
)
1016 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1021 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1022 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1023 operands
[1] = GEN_INT (l
[0]);
1024 middlehalf
[1] = GEN_INT (l
[1]);
1025 latehalf
[1] = GEN_INT (l
[2]);
1027 else if (CONSTANT_P (operands
[1]))
1029 /* actually, no non-CONST_DOUBLE constant should ever
1032 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1033 latehalf
[1] = constm1_rtx
;
1035 latehalf
[1] = const0_rtx
;
1040 middlehalf
[1] = operands
[1];
1041 latehalf
[1] = operands
[1];
1045 /* size is not 12: */
1047 if (optype0
== REGOP
)
1048 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1049 else if (optype0
== OFFSOP
)
1050 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1052 latehalf
[0] = operands
[0];
1054 if (optype1
== REGOP
)
1055 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1056 else if (optype1
== OFFSOP
)
1057 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1058 else if (optype1
== CNSTOP
)
1059 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1061 latehalf
[1] = operands
[1];
1064 /* If insn is effectively movd N(sp),-(sp) then we will do the
1065 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1066 for the low word as well, to compensate for the first decrement of sp. */
1067 if (optype0
== PUSHOP
1068 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1069 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1070 operands
[1] = latehalf
[1];
1072 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1073 if the upper part of reg N does not appear in the MEM, arrange to
1074 emit the move late-half first. Otherwise, compute the MEM address
1075 into the upper part of N and use that as a pointer to the memory
1077 if (optype0
== REGOP
1078 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1080 if (reg_overlap_mentioned_p (operands
[0], XEXP (operands
[1], 0))
1081 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1083 /* If both halves of dest are used in the src memory address,
1084 compute the address into latehalf of dest. */
1086 xops
[0] = latehalf
[0];
1087 xops
[1] = XEXP (operands
[1], 0);
1088 output_asm_insn ("lea %a1,%0", xops
);
1089 if( GET_MODE (operands
[1]) == XFmode
)
1091 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1092 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1093 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1097 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1098 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1102 && reg_overlap_mentioned_p (middlehalf
[0],
1103 XEXP (operands
[1], 0)))
1105 /* Check for two regs used by both source and dest. */
1106 if (reg_overlap_mentioned_p (operands
[0], XEXP (operands
[1], 0))
1107 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1110 /* JRV says this can't happen: */
1111 if (addreg0
|| addreg1
)
1114 /* Only the middle reg conflicts; simply put it last. */
1115 output_asm_insn (singlemove_string (operands
), operands
);
1116 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1117 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1120 else if (reg_overlap_mentioned_p (operands
[0], XEXP (operands
[1], 0)))
1121 /* If the low half of dest is mentioned in the source memory
1122 address, the arrange to emit the move late half first. */
1123 dest_overlapped_low
= 1;
1126 /* If one or both operands autodecrementing,
1127 do the two words, high-numbered first. */
1129 /* Likewise, the first move would clobber the source of the second one,
1130 do them in the other order. This happens only for registers;
1131 such overlap can't happen in memory unless the user explicitly
1132 sets it up, and that is an undefined circumstance. */
1134 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1135 || (optype0
== REGOP
&& optype1
== REGOP
1136 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1137 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1138 || dest_overlapped_low
)
1140 /* Make any unoffsettable addresses point at high-numbered word. */
1144 output_asm_insn ("addql %#8,%0", &addreg0
);
1146 output_asm_insn ("addql %#4,%0", &addreg0
);
1151 output_asm_insn ("addql %#8,%0", &addreg1
);
1153 output_asm_insn ("addql %#4,%0", &addreg1
);
1157 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1159 /* Undo the adds we just did. */
1161 output_asm_insn ("subql %#4,%0", &addreg0
);
1163 output_asm_insn ("subql %#4,%0", &addreg1
);
1167 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1169 output_asm_insn ("subql %#4,%0", &addreg0
);
1171 output_asm_insn ("subql %#4,%0", &addreg1
);
1174 /* Do low-numbered word. */
1175 return singlemove_string (operands
);
1178 /* Normal case: do the two words, low-numbered first. */
1180 output_asm_insn (singlemove_string (operands
), operands
);
1182 /* Do the middle one of the three words for long double */
1186 output_asm_insn ("addql %#4,%0", &addreg0
);
1188 output_asm_insn ("addql %#4,%0", &addreg1
);
1190 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1193 /* Make any unoffsettable addresses point at high-numbered word. */
1195 output_asm_insn ("addql %#4,%0", &addreg0
);
1197 output_asm_insn ("addql %#4,%0", &addreg1
);
1200 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1202 /* Undo the adds we just did. */
1206 output_asm_insn ("subql %#8,%0", &addreg0
);
1208 output_asm_insn ("subql %#4,%0", &addreg0
);
1213 output_asm_insn ("subql %#8,%0", &addreg1
);
1215 output_asm_insn ("subql %#4,%0", &addreg1
);
1221 /* Return a REG that occurs in ADDR with coefficient 1.
1222 ADDR can be effectively incremented by incrementing REG. */
1225 find_addr_reg (addr
)
1228 while (GET_CODE (addr
) == PLUS
)
1230 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1231 addr
= XEXP (addr
, 0);
1232 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1233 addr
= XEXP (addr
, 1);
1234 else if (CONSTANT_P (XEXP (addr
, 0)))
1235 addr
= XEXP (addr
, 1);
1236 else if (CONSTANT_P (XEXP (addr
, 1)))
1237 addr
= XEXP (addr
, 0);
1241 if (GET_CODE (addr
) == REG
)
1246 /* Store in cc_status the expressions that the condition codes will
1247 describe after execution of an instruction whose pattern is EXP.
1248 Do not alter them if the instruction would not alter the cc's. */
1250 /* On the 68000, all the insns to store in an address register fail to
1251 set the cc's. However, in some cases these instructions can make it
1252 possibly invalid to use the saved cc's. In those cases we clear out
1253 some or all of the saved cc's so they won't be used. */
1255 notice_update_cc (exp
, insn
)
1259 /* If the cc is being set from the fpa and the expression is not an
1260 explicit floating point test instruction (which has code to deal with
1261 this), reinit the CC. */
1262 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1263 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1264 && !(GET_CODE (exp
) == PARALLEL
1265 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1266 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1270 else if (GET_CODE (exp
) == SET
)
1272 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1276 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1278 if (cc_status
.value1
1279 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1280 cc_status
.value1
= 0;
1281 if (cc_status
.value2
1282 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1283 cc_status
.value2
= 0;
1285 else if (!FP_REG_P (SET_DEST (exp
))
1286 && SET_DEST (exp
) != cc0_rtx
1287 && (FP_REG_P (SET_SRC (exp
))
1288 || GET_CODE (SET_SRC (exp
)) == FIX
1289 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1290 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1294 /* A pair of move insns doesn't produce a useful overall cc. */
1295 else if (!FP_REG_P (SET_DEST (exp
))
1296 && !FP_REG_P (SET_SRC (exp
))
1297 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1298 && (GET_CODE (SET_SRC (exp
)) == REG
1299 || GET_CODE (SET_SRC (exp
)) == MEM
1300 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1304 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1308 else if (XEXP (exp
, 0) != pc_rtx
)
1310 cc_status
.flags
= 0;
1311 cc_status
.value1
= XEXP (exp
, 0);
1312 cc_status
.value2
= XEXP (exp
, 1);
1315 else if (GET_CODE (exp
) == PARALLEL
1316 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1318 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1320 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1322 cc_status
.flags
= 0;
1323 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1324 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1329 if (cc_status
.value2
!= 0
1330 && ADDRESS_REG_P (cc_status
.value2
)
1331 && GET_MODE (cc_status
.value2
) == QImode
)
1333 if (cc_status
.value2
!= 0
1334 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1335 switch (GET_CODE (cc_status
.value2
))
1337 case PLUS
: case MINUS
: case MULT
:
1338 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1339 case ASHIFT
: case LSHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1340 case ROTATE
: case ROTATERT
:
1341 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1342 cc_status
.flags
|= CC_NO_OVERFLOW
;
1345 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1346 ends with a move insn moving r2 in r2's mode.
1347 Thus, the cc's are set for r2.
1348 This can set N bit spuriously. */
1349 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1351 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1353 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1354 cc_status
.value2
= 0;
1355 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1356 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1357 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1358 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1359 cc_status
.flags
= CC_IN_68881
;
1363 output_move_const_double (operands
)
1366 #ifdef SUPPORT_SUN_FPA
1367 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1369 int code
= standard_sun_fpa_constant_p (operands
[1]);
1373 static char buf
[40];
1375 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1378 return "fpmove%.d %1,%0";
1383 int code
= standard_68881_constant_p (operands
[1]);
1387 static char buf
[40];
1389 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1392 return "fmove%.d %1,%0";
1397 output_move_const_single (operands
)
1400 #ifdef SUPPORT_SUN_FPA
1403 int code
= standard_sun_fpa_constant_p (operands
[1]);
1407 static char buf
[40];
1409 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1412 return "fpmove%.s %1,%0";
1415 #endif /* defined SUPPORT_SUN_FPA */
1417 int code
= standard_68881_constant_p (operands
[1]);
1421 static char buf
[40];
1423 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1426 return "fmove%.s %f1,%0";
1430 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1431 from the "fmovecr" instruction.
1432 The value, anded with 0xff, gives the code to use in fmovecr
1433 to get the desired constant. */
1435 /* This code has been fixed for cross-compilation. */
1437 static int inited_68881_table
= 0;
1439 char *strings_68881
[7] = {
1449 int codes_68881
[7] = {
1459 REAL_VALUE_TYPE values_68881
[7];
1461 /* Set up values_68881 array by converting the decimal values
1462 strings_68881 to binary. */
1469 enum machine_mode mode
;
1472 for (i
= 0; i
< 7; i
++)
1476 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
1477 values_68881
[i
] = r
;
1479 inited_68881_table
= 1;
1483 standard_68881_constant_p (x
)
1488 enum machine_mode mode
;
1490 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
1494 #ifndef REAL_ARITHMETIC
1495 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1496 if (! flag_pretend_float
)
1501 if (! inited_68881_table
)
1502 init_68881_table ();
1504 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1506 for (i
= 0; i
< 6; i
++)
1508 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
1509 return (codes_68881
[i
]);
1512 if (GET_MODE (x
) == SFmode
)
1515 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
1516 return (codes_68881
[6]);
1518 /* larger powers of ten in the constants ram are not used
1519 because they are not equal to a `double' C constant. */
1523 /* If X is a floating-point constant, return the logarithm of X base 2,
1524 or 0 if X is not a power of 2. */
1527 floating_exact_log2 (x
)
1530 REAL_VALUE_TYPE r
, r1
;
1533 #ifndef REAL_ARITHMETIC
1534 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1535 if (! flag_pretend_float
)
1540 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1542 if (REAL_VALUES_LESS (r
, dconst0
))
1547 while (REAL_VALUES_LESS (r1
, r
))
1549 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
1550 if (REAL_VALUES_EQUAL (r1
, r
))
1557 #ifdef SUPPORT_SUN_FPA
1558 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1559 from the Sun FPA's constant RAM.
1560 The value returned, anded with 0x1ff, gives the code to use in fpmove
1561 to get the desired constant. */
1563 static int inited_FPA_table
= 0;
1565 char *strings_FPA
[38] = {
1566 /* small rationals */
1579 /* Decimal equivalents of double precision values */
1580 "2.718281828459045091", /* D_E */
1581 "6.283185307179586477", /* 2 pi */
1582 "3.141592653589793116", /* D_PI */
1583 "1.570796326794896619", /* pi/2 */
1584 "1.414213562373095145", /* D_SQRT2 */
1585 "0.7071067811865475244", /* 1/sqrt(2) */
1586 "-1.570796326794896619", /* -pi/2 */
1587 "1.442695040888963387", /* D_LOG2ofE */
1588 "3.321928024887362182", /* D_LOG2of10 */
1589 "0.6931471805599452862", /* D_LOGEof2 */
1590 "2.302585092994045901", /* D_LOGEof10 */
1591 "0.3010299956639811980", /* D_LOG10of2 */
1592 "0.4342944819032518167", /* D_LOG10ofE */
1593 /* Decimal equivalents of single precision values */
1594 "2.718281745910644531", /* S_E */
1595 "6.283185307179586477", /* 2 pi */
1596 "3.141592741012573242", /* S_PI */
1597 "1.570796326794896619", /* pi/2 */
1598 "1.414213538169860840", /* S_SQRT2 */
1599 "0.7071067811865475244", /* 1/sqrt(2) */
1600 "-1.570796326794896619", /* -pi/2 */
1601 "1.442695021629333496", /* S_LOG2ofE */
1602 "3.321928024291992188", /* S_LOG2of10 */
1603 "0.6931471824645996094", /* S_LOGEof2 */
1604 "2.302585124969482442", /* S_LOGEof10 */
1605 "0.3010300099849700928", /* S_LOG10of2 */
1606 "0.4342944920063018799", /* S_LOG10ofE */
1610 int codes_FPA
[38] = {
1611 /* small rationals */
1624 /* double precision */
1638 /* single precision */
1654 REAL_VALUE_TYPE values_FPA
[38];
1656 /* This code has been fixed for cross-compilation. */
1661 enum machine_mode mode
;
1666 for (i
= 0; i
< 38; i
++)
1670 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
1673 inited_FPA_table
= 1;
1678 standard_sun_fpa_constant_p (x
)
1684 #ifndef REAL_ARITHMETIC
1685 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1686 if (! flag_pretend_float
)
1691 if (! inited_FPA_table
)
1694 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1696 for (i
=0; i
<12; i
++)
1698 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
1699 return (codes_FPA
[i
]);
1702 if (GET_MODE (x
) == SFmode
)
1704 for (i
=25; i
<38; i
++)
1706 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
1707 return (codes_FPA
[i
]);
1712 for (i
=12; i
<25; i
++)
1714 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
1715 return (codes_FPA
[i
]);
1720 #endif /* define SUPPORT_SUN_FPA */
1722 /* A C compound statement to output to stdio stream STREAM the
1723 assembler syntax for an instruction operand X. X is an RTL
1726 CODE is a value that can be used to specify one of several ways
1727 of printing the operand. It is used when identical operands
1728 must be printed differently depending on the context. CODE
1729 comes from the `%' specification that was used to request
1730 printing of the operand. If the specification was just `%DIGIT'
1731 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1732 is the ASCII code for LTR.
1734 If X is a register, this macro should print the register's name.
1735 The names can be found in an array `reg_names' whose type is
1736 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1738 When the machine description has a specification `%PUNCT' (a `%'
1739 followed by a punctuation character), this macro is called with
1740 a null pointer for X and the punctuation character for CODE.
1742 The m68k specific codes are:
1744 '.' for dot needed in Motorola-style opcode names.
1745 '-' for an operand pushing on the stack:
1746 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1747 '+' for an operand pushing on the stack:
1748 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1749 '@' for a reference to the top word on the stack:
1750 sp@, (sp) or (%sp) depending on the style of syntax.
1751 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1752 but & in SGS syntax).
1753 '!' for the cc register (used in an `and to cc' insn).
1754 '$' for the letter `s' in an op code, but only on the 68040.
1755 '&' for the letter `d' in an op code, but only on the 68040.
1756 '/' for register prefix needed by longlong.h.
1758 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1759 'd' to force memory addressing to be absolute, not relative.
1760 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1761 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1762 than directly). Second part of 'y' below.
1763 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1764 or print pair of registers as rx:ry.
1765 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1766 CONST_DOUBLE's as SunFPA constant RAM registers if
1767 possible, so it should not be used except for the SunFPA.
1772 print_operand (file
, op
, letter
)
1773 FILE *file
; /* file to write to */
1774 rtx op
; /* operand to print */
1775 int letter
; /* %<letter> or 0 */
1782 asm_fprintf (file
, ".");
1785 else if (letter
== '#')
1787 asm_fprintf (file
, "%0I");
1789 else if (letter
== '-')
1792 asm_fprintf (file
, "-(%Rsp)");
1794 asm_fprintf (file
, "%Rsp@-");
1797 else if (letter
== '+')
1800 asm_fprintf (file
, "(%Rsp)+");
1802 asm_fprintf (file
, "%Rsp@+");
1805 else if (letter
== '@')
1808 asm_fprintf (file
, "(%Rsp)");
1810 asm_fprintf (file
, "%Rsp@");
1813 else if (letter
== '!')
1815 asm_fprintf (file
, "%Rfpcr");
1817 else if (letter
== '$')
1819 if (TARGET_68040_ONLY
)
1821 fprintf (file
, "s");
1824 else if (letter
== '&')
1826 if (TARGET_68040_ONLY
)
1828 fprintf (file
, "d");
1831 else if (letter
== '/')
1833 asm_fprintf (file
, "%R");
1835 else if (GET_CODE (op
) == REG
)
1838 && (letter
== 'y' || letter
== 'x')
1839 && GET_MODE (op
) == DFmode
)
1841 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
1842 reg_names
[REGNO (op
)+1]);
1846 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
1849 else if (GET_CODE (op
) == MEM
)
1851 output_address (XEXP (op
, 0));
1852 if (letter
== 'd' && ! TARGET_68020
1853 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
1854 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
1855 && INTVAL (XEXP (op
, 0)) < 0x8000
1856 && INTVAL (XEXP (op
, 0)) >= -0x8000))
1858 fprintf (file
, ":l");
1861 #ifdef SUPPORT_SUN_FPA
1862 else if ((letter
== 'y' || letter
== 'w')
1863 && GET_CODE (op
) == CONST_DOUBLE
1864 && (i
= standard_sun_fpa_constant_p (op
)))
1866 fprintf (file
, "%%%d", i
& 0x1ff);
1869 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
1872 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1873 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
1875 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
1878 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1879 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
1881 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
1884 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1885 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
1889 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
1894 /* A C compound statement to output to stdio stream STREAM the
1895 assembler syntax for an instruction operand that is a memory
1896 reference whose address is ADDR. ADDR is an RTL expression.
1898 Note that this contains a kludge that knows that the only reason
1899 we have an address (plus (label_ref...) (reg...)) when not generating
1900 PIC code is in the insn before a tablejump, and we know that m68k.md
1901 generates a label LInnn: on such an insn.
1903 It is possible for PIC to generate a (plus (label_ref...) (reg...))
1904 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
1906 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
1907 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
1908 we want. This difference can be accommodated by using an assembler
1909 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
1910 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
1911 macro. See m68k/sgs.h for an example; for versions without the bug.
1913 They also do not like things like "pea 1.w", so we simple leave off
1914 the .w on small constants.
1916 This routine is responsible for distinguishing between -fpic and -fPIC
1917 style relocations in an address. When generating -fpic code the
1918 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
1919 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
1922 print_operand_address (file
, addr
)
1926 register rtx reg1
, reg2
, breg
, ireg
;
1929 switch (GET_CODE (addr
))
1933 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
1935 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
1940 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
1942 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
1947 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
1949 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
1953 reg1
= reg2
= ireg
= breg
= offset
= 0;
1954 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
1956 offset
= XEXP (addr
, 0);
1957 addr
= XEXP (addr
, 1);
1959 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
1961 offset
= XEXP (addr
, 1);
1962 addr
= XEXP (addr
, 0);
1964 if (GET_CODE (addr
) != PLUS
)
1968 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
1970 reg1
= XEXP (addr
, 0);
1971 addr
= XEXP (addr
, 1);
1973 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
1975 reg1
= XEXP (addr
, 1);
1976 addr
= XEXP (addr
, 0);
1978 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
1980 reg1
= XEXP (addr
, 0);
1981 addr
= XEXP (addr
, 1);
1983 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
1985 reg1
= XEXP (addr
, 1);
1986 addr
= XEXP (addr
, 0);
1988 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
1990 reg1
= XEXP (addr
, 0);
1991 addr
= XEXP (addr
, 1);
1993 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1995 reg1
= XEXP (addr
, 1);
1996 addr
= XEXP (addr
, 0);
1998 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
1999 || GET_CODE (addr
) == SIGN_EXTEND
)
2011 #if 0 /* for OLD_INDEXING */
2012 else if (GET_CODE (addr
) == PLUS
)
2014 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2016 reg2
= XEXP (addr
, 0);
2017 addr
= XEXP (addr
, 1);
2019 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2021 reg2
= XEXP (addr
, 1);
2022 addr
= XEXP (addr
, 0);
2034 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2035 || GET_CODE (reg1
) == MULT
))
2036 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2041 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2046 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2047 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2050 if (GET_CODE (ireg
) == MULT
)
2052 scale
= INTVAL (XEXP (ireg
, 1));
2053 ireg
= XEXP (ireg
, 0);
2055 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2059 asm_fprintf (file
, "%LLD%d(%Rpc,%s.w",
2060 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2061 reg_names
[REGNO (XEXP (ireg
, 0))]);
2063 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,%s.w",
2064 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2065 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2066 reg_names
[REGNO (XEXP (ireg
, 0))]);
2069 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b,%s:w",
2070 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2071 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2072 reg_names
[REGNO (XEXP (ireg
, 0))]);
2079 asm_fprintf (file
, "%LLD%d(%Rpc,%s.l",
2080 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2081 reg_names
[REGNO (ireg
)]);
2083 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,%s.l",
2084 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2085 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2086 reg_names
[REGNO (ireg
)]);
2089 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l",
2090 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2091 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2092 reg_names
[REGNO (ireg
)]);
2098 fprintf (file
, "*%d", scale
);
2100 fprintf (file
, ":%d", scale
);
2106 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2107 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2111 asm_fprintf (file
, "%LLD%d(%Rpc,%s.l",
2112 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2113 reg_names
[REGNO (breg
)]);
2115 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,%s.l",
2116 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2117 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2118 reg_names
[REGNO (breg
)]);
2121 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l",
2122 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2123 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2124 reg_names
[REGNO (breg
)]);
2129 if (ireg
!= 0 || breg
!= 0)
2136 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2143 output_addr_const (file
, addr
);
2144 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2145 fprintf (file
, "@GOT");
2147 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2153 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2156 output_addr_const (file
, addr
);
2157 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2158 fprintf (file
, ":w");
2159 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2160 fprintf (file
, ":l");
2162 if (addr
!= 0 && ireg
!= 0)
2167 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2169 scale
= INTVAL (XEXP (ireg
, 1));
2170 ireg
= XEXP (ireg
, 0);
2172 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2175 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2177 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2183 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2185 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2191 fprintf (file
, "*%d", scale
);
2193 fprintf (file
, ":%d", scale
);
2199 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2200 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2204 asm_fprintf (file
, "%LLD%d(%Rpc,%s.l)",
2205 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2206 reg_names
[REGNO (reg1
)]);
2208 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,%s.l)",
2209 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2210 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2211 reg_names
[REGNO (reg1
)]);
2214 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b,%s:l)",
2215 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2216 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2217 reg_names
[REGNO (reg1
)]);
2221 /* FALL-THROUGH (is this really what we want? */
2223 if (GET_CODE (addr
) == CONST_INT
2224 && INTVAL (addr
) < 0x8000
2225 && INTVAL (addr
) >= -0x8000)
2229 /* Many SGS assemblers croak on size specifiers for constants. */
2230 fprintf (file
, "%d", INTVAL (addr
));
2232 fprintf (file
, "%d.w", INTVAL (addr
));
2235 fprintf (file
, "%d:w", INTVAL (addr
));
2240 output_addr_const (file
, addr
);
2246 /* Check for cases where a clr insns can be omitted from code using
2247 strict_low_part sets. For example, the second clrl here is not needed:
2248 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2250 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2251 insn we are checking for redundancy. TARGET is the register set by the
2255 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2256 enum machine_mode mode
;
2262 p
= prev_nonnote_insn (first_insn
);
2266 /* If it isn't an insn, then give up. */
2267 if (GET_CODE (p
) != INSN
)
2270 if (reg_set_p (target
, p
))
2272 rtx set
= single_set (p
);
2275 /* If it isn't an easy to recognize insn, then give up. */
2279 dest
= SET_DEST (set
);
2281 /* If this sets the entire target register to zero, then our
2282 first_insn is redundant. */
2283 if (rtx_equal_p (dest
, target
)
2284 && SET_SRC (set
) == const0_rtx
)
2286 else if (GET_CODE (dest
) == STRICT_LOW_PART
2287 && GET_CODE (XEXP (dest
, 0)) == REG
2288 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2289 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2290 <= GET_MODE_SIZE (mode
)))
2291 /* This is a strict low part set which modifies less than
2292 we are using, so it is safe. */
2298 p
= prev_nonnote_insn (p
);