1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 static bool m68k_handle_option (size_t, const char *, int);
107 static rtx
find_addr_reg (rtx
);
108 static const char *singlemove_string (rtx
*);
109 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
110 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
111 #ifdef M68K_TARGET_COFF
112 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
113 #endif /* M68K_TARGET_COFF */
114 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
115 HOST_WIDE_INT
, tree
);
116 static rtx
m68k_struct_value_rtx (tree
, int);
117 static bool m68k_interrupt_function_p (tree func
);
118 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
119 tree args
, int flags
,
121 static void m68k_compute_frame_layout (void);
122 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
123 static int const_int_cost (rtx
);
124 static bool m68k_rtx_costs (rtx
, int, int, int *);
127 /* Specify the identification number of the library being built */
128 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
130 /* Nonzero if the last compare/test insn had FP operands. The
131 sCC expanders peek at this to determine what to do for the
132 68060, which has no fsCC instructions. */
133 int m68k_last_compare_had_fp_operands
;
135 /* Initialize the GCC target structure. */
137 #if INT_OP_GROUP == INT_OP_DOT_WORD
138 #undef TARGET_ASM_ALIGNED_HI_OP
139 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
142 #if INT_OP_GROUP == INT_OP_NO_DOT
143 #undef TARGET_ASM_BYTE_OP
144 #define TARGET_ASM_BYTE_OP "\tbyte\t"
145 #undef TARGET_ASM_ALIGNED_HI_OP
146 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
147 #undef TARGET_ASM_ALIGNED_SI_OP
148 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
151 #if INT_OP_GROUP == INT_OP_DC
152 #undef TARGET_ASM_BYTE_OP
153 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
154 #undef TARGET_ASM_ALIGNED_HI_OP
155 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
156 #undef TARGET_ASM_ALIGNED_SI_OP
157 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
165 #undef TARGET_ASM_FUNCTION_PROLOGUE
166 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
167 #undef TARGET_ASM_FUNCTION_EPILOGUE
168 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
170 #undef TARGET_ASM_OUTPUT_MI_THUNK
171 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
172 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
173 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
175 #undef TARGET_ASM_FILE_START_APP_OFF
176 #define TARGET_ASM_FILE_START_APP_OFF true
178 #undef TARGET_DEFAULT_TARGET_FLAGS
179 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_STRICT_ALIGNMENT)
180 #undef TARGET_HANDLE_OPTION
181 #define TARGET_HANDLE_OPTION m68k_handle_option
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS m68k_rtx_costs
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
192 #undef TARGET_STRUCT_VALUE_RTX
193 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
195 static const struct attribute_spec m68k_attribute_table
[] =
197 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
198 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
199 { NULL
, 0, 0, false, false, false, NULL
}
202 struct gcc_target targetm
= TARGET_INITIALIZER
;
204 /* These bits are controlled by all CPU selection options. Many options
205 also control MASK_68881, but some (notably -m68020) leave it alone. */
207 #define MASK_ALL_CPU_BITS \
208 (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \
209 | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_BITFIELD)
211 /* Implement TARGET_HANDLE_OPTION. */
214 m68k_handle_option (size_t code
, const char *arg
, int value
)
219 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
220 target_flags
|= MASK_5200
;
224 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
225 target_flags
|= MASK_5200
| MASK_CF_HWDIV
;
229 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
230 target_flags
|= MASK_528x
| MASK_CF_HWDIV
;
234 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
235 target_flags
|= MASK_CFV3
| MASK_CF_HWDIV
;
239 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
240 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
;
244 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
245 target_flags
|= MASK_CFV4
| MASK_CF_HWDIV
| MASK_CFV4E
;
250 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
255 target_flags
&= ~MASK_ALL_CPU_BITS
;
256 target_flags
|= MASK_68020
| MASK_BITFIELD
;
260 target_flags
&= ~MASK_ALL_CPU_BITS
;
261 target_flags
|= MASK_BITFIELD
| MASK_68881
| MASK_68020
| MASK_68040
;
265 target_flags
&= ~MASK_ALL_CPU_BITS
;
266 target_flags
|= (MASK_BITFIELD
| MASK_68881
| MASK_68020
267 | MASK_68040
| MASK_68060
);
271 target_flags
&= ~MASK_ALL_CPU_BITS
;
272 target_flags
|= MASK_68020
| MASK_68030
| MASK_BITFIELD
;
276 target_flags
&= ~MASK_ALL_CPU_BITS
;
277 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
278 | MASK_68040_ONLY
| MASK_68040
);
282 target_flags
&= ~MASK_ALL_CPU_BITS
;
283 target_flags
|= (MASK_68020
| MASK_68881
| MASK_BITFIELD
284 | MASK_68040_ONLY
| MASK_68060
);
288 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
293 target_flags
&= ~(MASK_ALL_CPU_BITS
| MASK_68881
);
294 target_flags
|= MASK_68020
;
297 case OPT_mshared_library_id_
:
298 if (value
> MAX_LIBRARY_ID
)
299 error ("-mshared-library-id=%s is not between 0 and %d",
300 arg
, MAX_LIBRARY_ID
);
302 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
310 /* Sometimes certain combinations of command options do not make
311 sense on a particular target machine. You can define a macro
312 `OVERRIDE_OPTIONS' to take account of this. This macro, if
313 defined, is executed once just after all the command options have
316 Don't use this macro to turn on various extra optimizations for
317 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
320 override_options (void)
322 /* Sanity check to ensure that msep-data and mid-sahred-library are not
323 * both specified together. Doing so simply doesn't make sense.
325 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
326 error ("cannot specify both -msep-data and -mid-shared-library");
328 /* If we're generating code for a separate A5 relative data segment,
329 * we've got to enable -fPIC as well. This might be relaxable to
330 * -fpic but it hasn't been tested properly.
332 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
335 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
337 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
338 error ("-fPIC is not currently supported on the 68000 or 68010");
340 /* ??? A historic way of turning on pic, or is this intended to
341 be an embedded thing that doesn't have the same name binding
342 significance that it does on hosted ELF systems? */
343 if (TARGET_PCREL
&& flag_pic
== 0)
346 /* Turn off function cse if we are doing PIC. We always want function call
347 to be done as `bsr foo@PLTPC', so it will force the assembler to create
348 the PLT entry for `foo'. Doing function cse will cause the address of
349 `foo' to be loaded into a register, which is exactly what we want to
350 avoid when we are doing PIC on svr4 m68k. */
352 flag_no_function_cse
= 1;
354 SUBTARGET_OVERRIDE_OPTIONS
;
357 /* Return nonzero if FUNC is an interrupt function as specified by the
358 "interrupt_handler" attribute. */
360 m68k_interrupt_function_p(tree func
)
364 if (TREE_CODE (func
) != FUNCTION_DECL
)
367 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
368 return (a
!= NULL_TREE
);
371 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
372 struct attribute_spec.handler. */
374 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
375 tree args ATTRIBUTE_UNUSED
,
376 int flags ATTRIBUTE_UNUSED
,
379 if (TREE_CODE (*node
) != FUNCTION_DECL
)
381 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
382 IDENTIFIER_POINTER (name
));
383 *no_add_attrs
= true;
390 m68k_compute_frame_layout (void)
393 unsigned int mask
, rmask
;
394 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
396 /* Only compute the frame once per function.
397 Don't cache information until reload has been completed. */
398 if (current_frame
.funcdef_no
== current_function_funcdef_no
402 current_frame
.size
= (get_frame_size () + 3) & -4;
404 mask
= rmask
= saved
= 0;
405 for (regno
= 0; regno
< 16; regno
++)
406 if (m68k_save_reg (regno
, interrupt_handler
))
409 rmask
|= 1 << (15 - regno
);
412 current_frame
.offset
= saved
* 4;
413 current_frame
.reg_no
= saved
;
414 current_frame
.reg_mask
= mask
;
415 current_frame
.reg_rev_mask
= rmask
;
417 current_frame
.foffset
= 0;
418 mask
= rmask
= saved
= 0;
419 if (TARGET_HARD_FLOAT
)
421 for (regno
= 16; regno
< 24; regno
++)
422 if (m68k_save_reg (regno
, interrupt_handler
))
424 mask
|= 1 << (regno
- 16);
425 rmask
|= 1 << (23 - regno
);
428 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
429 current_frame
.offset
+= current_frame
.foffset
;
431 current_frame
.fpu_no
= saved
;
432 current_frame
.fpu_mask
= mask
;
433 current_frame
.fpu_rev_mask
= rmask
;
435 /* Remember what function this frame refers to. */
436 current_frame
.funcdef_no
= current_function_funcdef_no
;
440 m68k_initial_elimination_offset (int from
, int to
)
443 /* The arg pointer points 8 bytes before the start of the arguments,
444 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
445 frame pointer in most frames. */
446 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
447 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
448 return argptr_offset
;
450 m68k_compute_frame_layout ();
452 gcc_assert (to
== STACK_POINTER_REGNUM
);
455 case ARG_POINTER_REGNUM
:
456 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
457 case FRAME_POINTER_REGNUM
:
458 return current_frame
.offset
+ current_frame
.size
;
464 /* Refer to the array `regs_ever_live' to determine which registers
465 to save; `regs_ever_live[I]' is nonzero if register number I
466 is ever used in the function. This function is responsible for
467 knowing which registers should not be saved even if used.
468 Return true if we need to save REGNO. */
471 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
473 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
475 if (current_function_uses_pic_offset_table
)
477 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
481 if (current_function_calls_eh_return
)
486 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
487 if (test
== INVALID_REGNUM
)
494 /* Fixed regs we never touch. */
495 if (fixed_regs
[regno
])
498 /* The frame pointer (if it is such) is handled specially. */
499 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
502 /* Interrupt handlers must also save call_used_regs
503 if they are live or when calling nested functions. */
504 if (interrupt_handler
)
506 if (regs_ever_live
[regno
])
509 if (!current_function_is_leaf
&& call_used_regs
[regno
])
513 /* Never need to save registers that aren't touched. */
514 if (!regs_ever_live
[regno
])
517 /* Otherwise save everything that isn't call-clobbered. */
518 return !call_used_regs
[regno
];
521 /* This function generates the assembly code for function entry.
522 STREAM is a stdio stream to output the code to.
523 SIZE is an int: how many units of temporary storage to allocate. */
526 m68k_output_function_prologue (FILE *stream
,
527 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
529 HOST_WIDE_INT fsize_with_regs
;
530 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
532 m68k_compute_frame_layout();
534 /* If the stack limit is a symbol, we can check it here,
535 before actually allocating the space. */
536 if (current_function_limit_stack
537 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
538 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
539 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
541 /* On ColdFire add register save into initial stack frame setup, if possible. */
542 fsize_with_regs
= current_frame
.size
;
545 if (current_frame
.reg_no
> 2)
546 fsize_with_regs
+= current_frame
.reg_no
* 4;
547 if (current_frame
.fpu_no
)
548 fsize_with_regs
+= current_frame
.fpu_no
* 8;
551 if (frame_pointer_needed
)
553 if (current_frame
.size
== 0 && TARGET_68040
)
554 /* on the 68040, pea + move is faster than link.w 0 */
555 fprintf (stream
, (MOTOROLA
556 ? "\tpea (%s)\n\tmove.l %s,%s\n"
557 : "\tpea %s@\n\tmovel %s,%s\n"),
558 M68K_REGNAME (FRAME_POINTER_REGNUM
),
559 M68K_REGNAME (STACK_POINTER_REGNUM
),
560 M68K_REGNAME (FRAME_POINTER_REGNUM
));
561 else if (fsize_with_regs
< 0x8000)
562 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
563 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
564 else if (TARGET_68020
)
565 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
566 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
568 /* Adding negative number is faster on the 68040. */
570 "\tlink" ASM_DOTW
" %s,%I0\n"
571 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
572 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
574 else if (fsize_with_regs
) /* !frame_pointer_needed */
576 if (fsize_with_regs
< 0x8000)
578 if (fsize_with_regs
<= 8)
580 if (!TARGET_COLDFIRE
)
581 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
584 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
587 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
588 /* On the CPU32 it is faster to use two subqw instructions to
589 subtract a small integer (8 < N <= 16) to a register. */
591 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
592 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
593 fsize_with_regs
- 8);
594 else if (TARGET_68040
)
595 /* Adding negative number is faster on the 68040. */
596 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
599 asm_fprintf (stream
, (MOTOROLA
600 ? "\tlea (%wd,%Rsp),%Rsp\n"
601 : "\tlea %Rsp@(%wd),%Rsp\n"),
604 else /* fsize_with_regs >= 0x8000 */
605 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
607 } /* !frame_pointer_needed */
609 if (dwarf2out_do_frame ())
611 if (frame_pointer_needed
)
614 l
= (char *) dwarf2out_cfi_label ();
616 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
617 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
618 cfa_offset
+= current_frame
.size
;
622 cfa_offset
+= current_frame
.size
;
623 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
627 if (current_frame
.fpu_mask
)
631 asm_fprintf (stream
, (MOTOROLA
632 ? "\tfmovm %I0x%x,-(%Rsp)\n"
633 : "\tfmovem %I0x%x,%Rsp@-\n"),
634 current_frame
.fpu_mask
);
640 /* stack already has registers in it. Find the offset from
641 the bottom of stack to where the FP registers go */
642 if (current_frame
.reg_no
<= 2)
645 offset
= current_frame
.reg_no
* 4;
648 "\tfmovem %I0x%x,%d(%Rsp)\n",
649 current_frame
.fpu_rev_mask
,
653 "\tfmovem %I0x%x,(%Rsp)\n",
654 current_frame
.fpu_rev_mask
);
657 if (dwarf2out_do_frame ())
659 char *l
= (char *) dwarf2out_cfi_label ();
662 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
663 if (! frame_pointer_needed
)
664 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
665 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
666 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
667 dwarf2out_reg_save (l
, regno
, -cfa_offset
668 + n_regs
++ * TARGET_FP_REG_SIZE
);
672 /* If the stack limit is not a symbol, check it here.
673 This has the disadvantage that it may be too late... */
674 if (current_function_limit_stack
)
676 if (REG_P (stack_limit_rtx
))
677 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
678 M68K_REGNAME (REGNO (stack_limit_rtx
)));
679 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
680 warning (0, "stack limit expression is not supported");
683 if (current_frame
.reg_no
<= 2)
685 /* Store each separately in the same order moveml uses.
686 Using two movel instructions instead of a single moveml
687 is about 15% faster for the 68020 and 68030 at no expense
692 for (i
= 0; i
< 16; i
++)
693 if (current_frame
.reg_rev_mask
& (1 << i
))
695 asm_fprintf (stream
, (MOTOROLA
696 ? "\t%Omove.l %s,-(%Rsp)\n"
697 : "\tmovel %s,%Rsp@-\n"),
698 M68K_REGNAME (15 - i
));
699 if (dwarf2out_do_frame ())
701 char *l
= (char *) dwarf2out_cfi_label ();
704 if (! frame_pointer_needed
)
705 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
706 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
710 else if (current_frame
.reg_rev_mask
)
713 /* The ColdFire does not support the predecrement form of the
714 MOVEM instruction, so we must adjust the stack pointer and
715 then use the plain address register indirect mode.
716 The required register save space was combined earlier with
717 the fsize_with_regs amount. */
719 asm_fprintf (stream
, (MOTOROLA
720 ? "\tmovm.l %I0x%x,(%Rsp)\n"
721 : "\tmoveml %I0x%x,%Rsp@\n"),
722 current_frame
.reg_mask
);
724 asm_fprintf (stream
, (MOTOROLA
725 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
726 : "\tmoveml %I0x%x,%Rsp@-\n"),
727 current_frame
.reg_rev_mask
);
728 if (dwarf2out_do_frame ())
730 char *l
= (char *) dwarf2out_cfi_label ();
733 cfa_offset
+= current_frame
.reg_no
* 4;
734 if (! frame_pointer_needed
)
735 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
736 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
737 if (current_frame
.reg_mask
& (1 << regno
))
738 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
741 if (!TARGET_SEP_DATA
&& flag_pic
742 && (current_function_uses_pic_offset_table
743 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
745 if (TARGET_ID_SHARED_LIBRARY
)
747 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
748 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
749 m68k_library_id_string
,
750 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
756 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
757 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
760 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
761 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
762 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
763 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
764 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
770 /* Return true if this function's epilogue can be output as RTL. */
773 use_return_insn (void)
775 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
778 /* We can output the epilogue as RTL only if no registers need to be
780 m68k_compute_frame_layout ();
781 return current_frame
.reg_no
? false : true;
784 /* This function generates the assembly code for function exit,
785 on machines that need it.
787 The function epilogue should not depend on the current stack pointer!
788 It should use the frame pointer only, if there is a frame pointer.
789 This is mandatory because of alloca; we also take advantage of it to
790 omit stack adjustments before returning. */
793 m68k_output_function_epilogue (FILE *stream
,
794 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
796 HOST_WIDE_INT fsize
, fsize_with_regs
;
798 bool restore_from_sp
= false;
799 rtx insn
= get_last_insn ();
801 m68k_compute_frame_layout ();
803 /* If the last insn was a BARRIER, we don't have to write any code. */
804 if (GET_CODE (insn
) == NOTE
)
805 insn
= prev_nonnote_insn (insn
);
806 if (insn
&& GET_CODE (insn
) == BARRIER
)
808 /* Output just a no-op so that debuggers don't get confused
809 about which function the pc is in at this address. */
810 fprintf (stream
, "\tnop\n");
814 #ifdef FUNCTION_EXTRA_EPILOGUE
815 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
818 fsize
= current_frame
.size
;
820 /* FIXME: leaf_function_p below is too strong.
821 What we really need to know there is if there could be pending
822 stack adjustment needed at that point. */
824 = (! frame_pointer_needed
825 || (! current_function_calls_alloca
&& leaf_function_p ()));
827 /* fsize_with_regs is the size we need to adjust the sp when
828 popping the frame. */
829 fsize_with_regs
= fsize
;
831 /* Because the ColdFire doesn't support moveml with
832 complex address modes, we must adjust the stack manually
833 after restoring registers. When the frame pointer isn't used,
834 we can merge movem adjustment into frame unlinking
835 made immediately after it. */
836 if (TARGET_COLDFIRE
&& restore_from_sp
)
838 if (current_frame
.reg_no
> 2)
839 fsize_with_regs
+= current_frame
.reg_no
* 4;
840 if (current_frame
.fpu_no
)
841 fsize_with_regs
+= current_frame
.fpu_no
* 8;
844 if (current_frame
.offset
+ fsize
>= 0x8000
846 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
848 /* Because the ColdFire doesn't support moveml with
849 complex address modes we make an extra correction here. */
851 fsize
+= current_frame
.offset
;
853 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
854 fsize
= 0, big
= true;
856 if (current_frame
.reg_no
<= 2)
858 /* Restore each separately in the same order moveml does.
859 Using two movel instructions instead of a single moveml
860 is about 15% faster for the 68020 and 68030 at no expense
864 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
866 for (i
= 0; i
< 16; i
++)
867 if (current_frame
.reg_mask
& (1 << i
))
872 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
874 M68K_REGNAME (FRAME_POINTER_REGNUM
),
877 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
878 M68K_REGNAME (FRAME_POINTER_REGNUM
),
882 else if (restore_from_sp
)
883 asm_fprintf (stream
, (MOTOROLA
884 ? "\t%Omove.l (%Rsp)+,%s\n"
885 : "\tmovel %Rsp@+,%s\n"),
890 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
892 M68K_REGNAME (FRAME_POINTER_REGNUM
),
895 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
896 M68K_REGNAME (FRAME_POINTER_REGNUM
),
903 else if (current_frame
.reg_mask
)
905 /* The ColdFire requires special handling due to its limited moveml
911 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
912 M68K_REGNAME (FRAME_POINTER_REGNUM
));
913 asm_fprintf (stream
, (MOTOROLA
914 ? "\tmovm.l (%Ra1),%I0x%x\n"
915 : "\tmoveml %Ra1@,%I0x%x\n"),
916 current_frame
.reg_mask
);
918 else if (restore_from_sp
)
919 asm_fprintf (stream
, (MOTOROLA
920 ? "\tmovm.l (%Rsp),%I0x%x\n"
921 : "\tmoveml %Rsp@,%I0x%x\n"),
922 current_frame
.reg_mask
);
926 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
927 current_frame
.offset
+ fsize
,
928 M68K_REGNAME (FRAME_POINTER_REGNUM
),
929 current_frame
.reg_mask
);
931 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
932 M68K_REGNAME (FRAME_POINTER_REGNUM
),
933 current_frame
.offset
+ fsize
,
934 current_frame
.reg_mask
);
937 else /* !TARGET_COLDFIRE */
942 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
943 current_frame
.offset
+ fsize
,
944 M68K_REGNAME (FRAME_POINTER_REGNUM
),
945 current_frame
.reg_mask
);
947 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
948 M68K_REGNAME (FRAME_POINTER_REGNUM
),
949 current_frame
.offset
+ fsize
,
950 current_frame
.reg_mask
);
952 else if (restore_from_sp
)
954 asm_fprintf (stream
, (MOTOROLA
955 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
956 : "\tmoveml %Rsp@+,%I0x%x\n"),
957 current_frame
.reg_mask
);
962 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
963 current_frame
.offset
+ fsize
,
964 M68K_REGNAME (FRAME_POINTER_REGNUM
),
965 current_frame
.reg_mask
);
967 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
968 M68K_REGNAME (FRAME_POINTER_REGNUM
),
969 current_frame
.offset
+ fsize
,
970 current_frame
.reg_mask
);
974 if (current_frame
.fpu_rev_mask
)
980 if (current_frame
.reg_no
)
981 asm_fprintf (stream
, MOTOROLA
?
982 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
983 "\tfmovmd (%d,%Ra1),%I0x%x\n",
984 current_frame
.reg_no
* 4,
985 current_frame
.fpu_rev_mask
);
987 asm_fprintf (stream
, MOTOROLA
?
988 "\tfmovem.d (%Ra1),%I0x%x\n" :
989 "\tfmovmd (%Ra1),%I0x%x\n",
990 current_frame
.fpu_rev_mask
);
993 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
994 current_frame
.foffset
+ fsize
,
995 M68K_REGNAME (FRAME_POINTER_REGNUM
),
996 current_frame
.fpu_rev_mask
);
998 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
999 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1000 current_frame
.foffset
+ fsize
,
1001 current_frame
.fpu_rev_mask
);
1003 else if (restore_from_sp
)
1005 if (TARGET_COLDFIRE
)
1009 /* stack already has registers in it. Find the offset from
1010 the bottom of stack to where the FP registers go */
1011 if (current_frame
.reg_no
<= 2)
1014 offset
= current_frame
.reg_no
* 4;
1016 asm_fprintf (stream
,
1017 "\tfmovem %Rsp@(%wd), %I0x%x\n",
1018 offset
, current_frame
.fpu_rev_mask
);
1020 asm_fprintf (stream
,
1021 "\tfmovem %Rsp@, %I0x%x\n",
1022 current_frame
.fpu_rev_mask
);
1025 asm_fprintf (stream
, MOTOROLA
?
1026 "\tfmovm (%Rsp)+,%I0x%x\n" :
1027 "\tfmovem %Rsp@+,%I0x%x\n",
1028 current_frame
.fpu_rev_mask
);
1032 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1033 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1034 current_frame
.foffset
+ fsize
,
1035 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1036 current_frame
.fpu_rev_mask
);
1038 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1039 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1040 current_frame
.foffset
+ fsize
,
1041 current_frame
.fpu_rev_mask
);
1044 if (frame_pointer_needed
)
1045 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1046 else if (fsize_with_regs
)
1048 if (fsize_with_regs
<= 8)
1050 if (!TARGET_COLDFIRE
)
1051 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1054 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1057 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
1059 /* On the CPU32 it is faster to use two addqw instructions to
1060 add a small integer (8 < N <= 16) to a register. */
1061 asm_fprintf (stream
,
1062 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1063 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1064 fsize_with_regs
- 8);
1066 else if (fsize_with_regs
< 0x8000)
1069 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1072 asm_fprintf (stream
, (MOTOROLA
1073 ? "\tlea (%wd,%Rsp),%Rsp\n"
1074 : "\tlea %Rsp@(%wd),%Rsp\n"),
1078 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1080 if (current_function_calls_eh_return
)
1081 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1082 if (m68k_interrupt_function_p (current_function_decl
))
1083 fprintf (stream
, "\trte\n");
1084 else if (current_function_pops_args
)
1085 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1087 fprintf (stream
, "\trts\n");
1090 /* Return true if X is a valid comparison operator for the dbcc
1093 Note it rejects floating point comparison operators.
1094 (In the future we could use Fdbcc).
1096 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1099 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1101 switch (GET_CODE (x
))
1103 case EQ
: case NE
: case GTU
: case LTU
:
1107 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1109 case GT
: case LT
: case GE
: case LE
:
1110 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1116 /* Return nonzero if flags are currently in the 68881 flag register. */
1118 flags_in_68881 (void)
1120 /* We could add support for these in the future */
1121 return cc_status
.flags
& CC_IN_68881
;
1124 /* Output a BSR instruction suitable for PIC code. */
1126 m68k_output_pic_call (rtx dest
)
1130 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1132 /* We output a BSR instruction if we're building for a target that
1133 supports long branches. Otherwise we generate one of two sequences:
1134 a shorter one that uses a GOT entry or a longer one that doesn't.
1135 We'll use the -Os command-line flag to decide which to generate.
1136 Both sequences take the same time to execute on the ColdFire. */
1137 else if (TARGET_PCREL
)
1139 else if (TARGET_68020
)
1140 #if defined(USE_GAS)
1141 out
= "bsr.l %0@PLTPC";
1143 out
= "bsr %0@PLTPC";
1145 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1146 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1148 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1150 output_asm_insn (out
, &dest
);
1153 /* Output a dbCC; jCC sequence. Note we do not handle the
1154 floating point version of this sequence (Fdbcc). We also
1155 do not handle alternative conditions when CC_NO_OVERFLOW is
1156 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1157 kick those out before we get here. */
1160 output_dbcc_and_branch (rtx
*operands
)
1162 switch (GET_CODE (operands
[3]))
1165 output_asm_insn (MOTOROLA
1166 ? "dbeq %0,%l1\n\tjbeq %l2"
1167 : "dbeq %0,%l1\n\tjeq %l2",
1172 output_asm_insn (MOTOROLA
1173 ? "dbne %0,%l1\n\tjbne %l2"
1174 : "dbne %0,%l1\n\tjne %l2",
1179 output_asm_insn (MOTOROLA
1180 ? "dbgt %0,%l1\n\tjbgt %l2"
1181 : "dbgt %0,%l1\n\tjgt %l2",
1186 output_asm_insn (MOTOROLA
1187 ? "dbhi %0,%l1\n\tjbhi %l2"
1188 : "dbhi %0,%l1\n\tjhi %l2",
1193 output_asm_insn (MOTOROLA
1194 ? "dblt %0,%l1\n\tjblt %l2"
1195 : "dblt %0,%l1\n\tjlt %l2",
1200 output_asm_insn (MOTOROLA
1201 ? "dbcs %0,%l1\n\tjbcs %l2"
1202 : "dbcs %0,%l1\n\tjcs %l2",
1207 output_asm_insn (MOTOROLA
1208 ? "dbge %0,%l1\n\tjbge %l2"
1209 : "dbge %0,%l1\n\tjge %l2",
1214 output_asm_insn (MOTOROLA
1215 ? "dbcc %0,%l1\n\tjbcc %l2"
1216 : "dbcc %0,%l1\n\tjcc %l2",
1221 output_asm_insn (MOTOROLA
1222 ? "dble %0,%l1\n\tjble %l2"
1223 : "dble %0,%l1\n\tjle %l2",
1228 output_asm_insn (MOTOROLA
1229 ? "dbls %0,%l1\n\tjbls %l2"
1230 : "dbls %0,%l1\n\tjls %l2",
1238 /* If the decrement is to be done in SImode, then we have
1239 to compensate for the fact that dbcc decrements in HImode. */
1240 switch (GET_MODE (operands
[0]))
1243 output_asm_insn (MOTOROLA
1244 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1245 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1258 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1261 enum rtx_code op_code
= GET_CODE (op
);
1263 /* This does not produce a useful cc. */
1266 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1267 below. Swap the operands and change the op if these requirements
1268 are not fulfilled. */
1269 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1273 operand1
= operand2
;
1275 op_code
= swap_condition (op_code
);
1277 loperands
[0] = operand1
;
1278 if (GET_CODE (operand1
) == REG
)
1279 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1281 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1282 if (operand2
!= const0_rtx
)
1284 loperands
[2] = operand2
;
1285 if (GET_CODE (operand2
) == REG
)
1286 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1288 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1290 loperands
[4] = gen_label_rtx ();
1291 if (operand2
!= const0_rtx
)
1293 output_asm_insn (MOTOROLA
1294 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1295 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1300 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1301 output_asm_insn ("tst%.l %0", loperands
);
1303 output_asm_insn ("cmp%.w #0,%0", loperands
);
1305 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1307 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1308 output_asm_insn ("tst%.l %1", loperands
);
1310 output_asm_insn ("cmp%.w #0,%1", loperands
);
1313 loperands
[5] = dest
;
1318 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1319 CODE_LABEL_NUMBER (loperands
[4]));
1320 output_asm_insn ("seq %5", loperands
);
1324 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1325 CODE_LABEL_NUMBER (loperands
[4]));
1326 output_asm_insn ("sne %5", loperands
);
1330 loperands
[6] = gen_label_rtx ();
1331 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1333 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1334 CODE_LABEL_NUMBER (loperands
[4]));
1335 output_asm_insn ("sgt %5", loperands
);
1336 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1337 CODE_LABEL_NUMBER (loperands
[6]));
1341 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1342 CODE_LABEL_NUMBER (loperands
[4]));
1343 output_asm_insn ("shi %5", loperands
);
1347 loperands
[6] = gen_label_rtx ();
1348 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1350 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1351 CODE_LABEL_NUMBER (loperands
[4]));
1352 output_asm_insn ("slt %5", loperands
);
1353 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1354 CODE_LABEL_NUMBER (loperands
[6]));
1358 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1359 CODE_LABEL_NUMBER (loperands
[4]));
1360 output_asm_insn ("scs %5", loperands
);
1364 loperands
[6] = gen_label_rtx ();
1365 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1367 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1368 CODE_LABEL_NUMBER (loperands
[4]));
1369 output_asm_insn ("sge %5", loperands
);
1370 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1371 CODE_LABEL_NUMBER (loperands
[6]));
1375 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1376 CODE_LABEL_NUMBER (loperands
[4]));
1377 output_asm_insn ("scc %5", loperands
);
1381 loperands
[6] = gen_label_rtx ();
1382 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1384 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1385 CODE_LABEL_NUMBER (loperands
[4]));
1386 output_asm_insn ("sle %5", loperands
);
1387 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1388 CODE_LABEL_NUMBER (loperands
[6]));
1392 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1393 CODE_LABEL_NUMBER (loperands
[4]));
1394 output_asm_insn ("sls %5", loperands
);
1404 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1406 operands
[0] = countop
;
1407 operands
[1] = dataop
;
1409 if (GET_CODE (countop
) == CONST_INT
)
1411 register int count
= INTVAL (countop
);
1412 /* If COUNT is bigger than size of storage unit in use,
1413 advance to the containing unit of same size. */
1414 if (count
> signpos
)
1416 int offset
= (count
& ~signpos
) / 8;
1417 count
= count
& signpos
;
1418 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1420 if (count
== signpos
)
1421 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1423 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1425 /* These three statements used to use next_insns_test_no...
1426 but it appears that this should do the same job. */
1428 && next_insn_tests_no_inequality (insn
))
1431 && next_insn_tests_no_inequality (insn
))
1434 && next_insn_tests_no_inequality (insn
))
1437 cc_status
.flags
= CC_NOT_NEGATIVE
;
1439 return "btst %0,%1";
1442 /* Legitimize PIC addresses. If the address is already
1443 position-independent, we return ORIG. Newly generated
1444 position-independent addresses go to REG. If we need more
1445 than one register, we lose.
1447 An address is legitimized by making an indirect reference
1448 through the Global Offset Table with the name of the symbol
1451 The assembler and linker are responsible for placing the
1452 address of the symbol in the GOT. The function prologue
1453 is responsible for initializing a5 to the starting address
1456 The assembler is also responsible for translating a symbol name
1457 into a constant displacement from the start of the GOT.
1459 A quick example may make things a little clearer:
1461 When not generating PIC code to store the value 12345 into _foo
1462 we would generate the following code:
1466 When generating PIC two transformations are made. First, the compiler
1467 loads the address of foo into a register. So the first transformation makes:
1472 The code in movsi will intercept the lea instruction and call this
1473 routine which will transform the instructions into:
1475 movel a5@(_foo:w), a0
1479 That (in a nutshell) is how *all* symbol and label references are
1483 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1488 /* First handle a simple SYMBOL_REF or LABEL_REF */
1489 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1493 pic_ref
= gen_rtx_MEM (Pmode
,
1494 gen_rtx_PLUS (Pmode
,
1495 pic_offset_table_rtx
, orig
));
1496 current_function_uses_pic_offset_table
= 1;
1497 MEM_READONLY_P (pic_ref
) = 1;
1498 emit_move_insn (reg
, pic_ref
);
1501 else if (GET_CODE (orig
) == CONST
)
1505 /* Make sure this has not already been legitimized. */
1506 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1507 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1512 /* legitimize both operands of the PLUS */
1513 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1515 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1516 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1517 base
== reg
? 0 : reg
);
1519 if (GET_CODE (orig
) == CONST_INT
)
1520 return plus_constant (base
, INTVAL (orig
));
1521 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1522 /* Likewise, should we set special REG_NOTEs here? */
1528 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1530 static CONST_METHOD
const_method (rtx
);
1532 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1535 const_method (rtx constant
)
1540 i
= INTVAL (constant
);
1544 /* The ColdFire doesn't have byte or word operations. */
1545 /* FIXME: This may not be useful for the m68060 either. */
1546 if (!TARGET_COLDFIRE
)
1548 /* if -256 < N < 256 but N is not in range for a moveq
1549 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1550 if (USE_MOVQ (i
^ 0xff))
1552 /* Likewise, try with not.w */
1553 if (USE_MOVQ (i
^ 0xffff))
1555 /* This is the only value where neg.w is useful */
1560 /* Try also with swap. */
1562 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1567 /* Try using MVZ/MVS with an immediate value to load constants. */
1568 if (i
>= 0 && i
<= 65535)
1570 if (i
>= -32768 && i
<= 32767)
1574 /* Otherwise, use move.l */
1579 const_int_cost (rtx constant
)
1581 switch (const_method (constant
))
1584 /* Constants between -128 and 127 are cheap due to moveq. */
1592 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
1602 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1607 /* Constant zero is super cheap due to clr instruction. */
1608 if (x
== const0_rtx
)
1611 *total
= const_int_cost (x
);
1621 /* Make 0.0 cheaper than other floating constants to
1622 encourage creating tstsf and tstdf insns. */
1623 if (outer_code
== COMPARE
1624 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1630 /* These are vaguely right for a 68020. */
1631 /* The costs for long multiply have been adjusted to work properly
1632 in synth_mult on the 68020, relative to an average of the time
1633 for add and the time for shift, taking away a little more because
1634 sometimes move insns are needed. */
1635 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
1637 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 \
1638 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 \
1639 : TARGET_COLDFIRE ? 10 : 13)
1640 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 \
1641 : (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
1642 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1645 /* An lea costs about three times as much as a simple add. */
1646 if (GET_MODE (x
) == SImode
1647 && GET_CODE (XEXP (x
, 1)) == REG
1648 && GET_CODE (XEXP (x
, 0)) == MULT
1649 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1650 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1651 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1652 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1653 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1655 /* lea an@(dx:l:i),am */
1656 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1666 *total
= COSTS_N_INSNS(1);
1669 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1671 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1673 if (INTVAL (XEXP (x
, 1)) < 16)
1674 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1676 /* We're using clrw + swap for these cases. */
1677 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1680 *total
= COSTS_N_INSNS (10); /* Worst case. */
1683 /* A shift by a big integer takes an extra instruction. */
1684 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1685 && (INTVAL (XEXP (x
, 1)) == 16))
1687 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1690 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1691 && !(INTVAL (XEXP (x
, 1)) > 0
1692 && INTVAL (XEXP (x
, 1)) <= 8))
1694 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1700 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1701 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1702 && GET_MODE (x
) == SImode
)
1703 *total
= COSTS_N_INSNS (MULW_COST
);
1704 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1705 *total
= COSTS_N_INSNS (MULW_COST
);
1707 *total
= COSTS_N_INSNS (MULL_COST
);
1714 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1715 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1716 else if (TARGET_CF_HWDIV
)
1717 *total
= COSTS_N_INSNS (18);
1719 *total
= COSTS_N_INSNS (43); /* div.l */
1728 output_move_const_into_data_reg (rtx
*operands
)
1732 i
= INTVAL (operands
[1]);
1733 switch (const_method (operands
[1]))
1736 return "mvzw %1,%0";
1738 return "mvsw %1,%0";
1740 return "moveq %1,%0";
1743 operands
[1] = GEN_INT (i
^ 0xff);
1744 return "moveq %1,%0\n\tnot%.b %0";
1747 operands
[1] = GEN_INT (i
^ 0xffff);
1748 return "moveq %1,%0\n\tnot%.w %0";
1751 return "moveq #-128,%0\n\tneg%.w %0";
1756 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1757 return "moveq %1,%0\n\tswap %0";
1760 return "move%.l %1,%0";
1766 /* Return 1 if 'constant' can be represented by
1767 mov3q on a ColdFire V4 core. */
1769 valid_mov3q_const (rtx constant
)
1773 if (TARGET_CFV4
&& GET_CODE (constant
) == CONST_INT
)
1775 i
= INTVAL (constant
);
1776 if (i
== -1 || (i
>= 1 && i
<= 7))
1784 output_move_simode_const (rtx
*operands
)
1786 if (operands
[1] == const0_rtx
1787 && (DATA_REG_P (operands
[0])
1788 || GET_CODE (operands
[0]) == MEM
)
1789 /* clr insns on 68000 read before writing.
1790 This isn't so on the 68010, but we have no TARGET_68010. */
1791 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1792 || !(GET_CODE (operands
[0]) == MEM
1793 && MEM_VOLATILE_P (operands
[0]))))
1795 else if ((GET_MODE (operands
[0]) == SImode
)
1796 && valid_mov3q_const (operands
[1]))
1797 return "mov3q%.l %1,%0";
1798 else if (operands
[1] == const0_rtx
1799 && ADDRESS_REG_P (operands
[0]))
1800 return "sub%.l %0,%0";
1801 else if (DATA_REG_P (operands
[0]))
1802 return output_move_const_into_data_reg (operands
);
1803 else if (ADDRESS_REG_P (operands
[0])
1804 && INTVAL (operands
[1]) < 0x8000
1805 && INTVAL (operands
[1]) >= -0x8000)
1807 if (valid_mov3q_const (operands
[1]))
1808 return "mov3q%.l %1,%0";
1809 return "move%.w %1,%0";
1811 else if (GET_CODE (operands
[0]) == MEM
1812 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1813 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1814 && INTVAL (operands
[1]) < 0x8000
1815 && INTVAL (operands
[1]) >= -0x8000)
1817 if (valid_mov3q_const (operands
[1]))
1818 return "mov3q%.l %1,%-";
1821 return "move%.l %1,%0";
1825 output_move_simode (rtx
*operands
)
1827 if (GET_CODE (operands
[1]) == CONST_INT
)
1828 return output_move_simode_const (operands
);
1829 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1830 || GET_CODE (operands
[1]) == CONST
)
1831 && push_operand (operands
[0], SImode
))
1833 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1834 || GET_CODE (operands
[1]) == CONST
)
1835 && ADDRESS_REG_P (operands
[0]))
1836 return "lea %a1,%0";
1837 return "move%.l %1,%0";
1841 output_move_himode (rtx
*operands
)
1843 if (GET_CODE (operands
[1]) == CONST_INT
)
1845 if (operands
[1] == const0_rtx
1846 && (DATA_REG_P (operands
[0])
1847 || GET_CODE (operands
[0]) == MEM
)
1848 /* clr insns on 68000 read before writing.
1849 This isn't so on the 68010, but we have no TARGET_68010. */
1850 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1851 || !(GET_CODE (operands
[0]) == MEM
1852 && MEM_VOLATILE_P (operands
[0]))))
1854 else if (operands
[1] == const0_rtx
1855 && ADDRESS_REG_P (operands
[0]))
1856 return "sub%.l %0,%0";
1857 else if (DATA_REG_P (operands
[0])
1858 && INTVAL (operands
[1]) < 128
1859 && INTVAL (operands
[1]) >= -128)
1860 return "moveq %1,%0";
1861 else if (INTVAL (operands
[1]) < 0x8000
1862 && INTVAL (operands
[1]) >= -0x8000)
1863 return "move%.w %1,%0";
1865 else if (CONSTANT_P (operands
[1]))
1866 return "move%.l %1,%0";
1867 /* Recognize the insn before a tablejump, one that refers
1868 to a table of offsets. Such an insn will need to refer
1869 to a label on the insn. So output one. Use the label-number
1870 of the table of offsets to generate this label. This code,
1871 and similar code below, assumes that there will be at most one
1872 reference to each table. */
1873 if (GET_CODE (operands
[1]) == MEM
1874 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1875 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1876 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1878 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1880 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1881 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1883 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1884 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1886 return "move%.w %1,%0";
1890 output_move_qimode (rtx
*operands
)
1892 /* 68k family always modifies the stack pointer by at least 2, even for
1893 byte pushes. The 5200 (ColdFire) does not do this. */
1895 /* This case is generated by pushqi1 pattern now. */
1896 gcc_assert (!(GET_CODE (operands
[0]) == MEM
1897 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1898 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1899 && ! ADDRESS_REG_P (operands
[1])
1900 && ! TARGET_COLDFIRE
));
1902 /* clr and st insns on 68000 read before writing.
1903 This isn't so on the 68010, but we have no TARGET_68010. */
1904 if (!ADDRESS_REG_P (operands
[0])
1905 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1906 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1908 if (operands
[1] == const0_rtx
)
1910 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1911 && GET_CODE (operands
[1]) == CONST_INT
1912 && (INTVAL (operands
[1]) & 255) == 255)
1918 if (GET_CODE (operands
[1]) == CONST_INT
1919 && DATA_REG_P (operands
[0])
1920 && INTVAL (operands
[1]) < 128
1921 && INTVAL (operands
[1]) >= -128)
1922 return "moveq %1,%0";
1923 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1924 return "sub%.l %0,%0";
1925 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1926 return "move%.l %1,%0";
1927 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1928 from address registers. */
1929 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1930 return "move%.w %1,%0";
1931 return "move%.b %1,%0";
1935 output_move_stricthi (rtx
*operands
)
1937 if (operands
[1] == const0_rtx
1938 /* clr insns on 68000 read before writing.
1939 This isn't so on the 68010, but we have no TARGET_68010. */
1940 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1941 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1943 return "move%.w %1,%0";
1947 output_move_strictqi (rtx
*operands
)
1949 if (operands
[1] == const0_rtx
1950 /* clr insns on 68000 read before writing.
1951 This isn't so on the 68010, but we have no TARGET_68010. */
1952 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1953 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1955 return "move%.b %1,%0";
1958 /* Return the best assembler insn template
1959 for moving operands[1] into operands[0] as a fullword. */
1962 singlemove_string (rtx
*operands
)
1964 if (GET_CODE (operands
[1]) == CONST_INT
)
1965 return output_move_simode_const (operands
);
1966 return "move%.l %1,%0";
1970 /* Output assembler code to perform a doubleword move insn
1971 with operands OPERANDS. */
1974 output_move_double (rtx
*operands
)
1978 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1983 rtx addreg0
= 0, addreg1
= 0;
1984 int dest_overlapped_low
= 0;
1985 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1990 /* First classify both operands. */
1992 if (REG_P (operands
[0]))
1994 else if (offsettable_memref_p (operands
[0]))
1996 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1998 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2000 else if (GET_CODE (operands
[0]) == MEM
)
2005 if (REG_P (operands
[1]))
2007 else if (CONSTANT_P (operands
[1]))
2009 else if (offsettable_memref_p (operands
[1]))
2011 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2013 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2015 else if (GET_CODE (operands
[1]) == MEM
)
2020 /* Check for the cases that the operand constraints are not supposed
2021 to allow to happen. Generating code for these cases is
2023 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2025 /* If one operand is decrementing and one is incrementing
2026 decrement the former register explicitly
2027 and change that operand into ordinary indexing. */
2029 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2031 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2033 output_asm_insn ("sub%.l #12,%0", operands
);
2035 output_asm_insn ("subq%.l #8,%0", operands
);
2036 if (GET_MODE (operands
[1]) == XFmode
)
2037 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2038 else if (GET_MODE (operands
[0]) == DFmode
)
2039 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2041 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2044 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2046 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2048 output_asm_insn ("sub%.l #12,%1", operands
);
2050 output_asm_insn ("subq%.l #8,%1", operands
);
2051 if (GET_MODE (operands
[1]) == XFmode
)
2052 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2053 else if (GET_MODE (operands
[1]) == DFmode
)
2054 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2056 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2060 /* If an operand is an unoffsettable memory ref, find a register
2061 we can increment temporarily to make it refer to the second word. */
2063 if (optype0
== MEMOP
)
2064 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2066 if (optype1
== MEMOP
)
2067 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2069 /* Ok, we can do one word at a time.
2070 Normally we do the low-numbered word first,
2071 but if either operand is autodecrementing then we
2072 do the high-numbered word first.
2074 In either case, set up in LATEHALF the operands to use
2075 for the high-numbered word and in some cases alter the
2076 operands in OPERANDS to be suitable for the low-numbered word. */
2080 if (optype0
== REGOP
)
2082 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2083 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2085 else if (optype0
== OFFSOP
)
2087 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2088 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2092 middlehalf
[0] = operands
[0];
2093 latehalf
[0] = operands
[0];
2096 if (optype1
== REGOP
)
2098 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2099 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2101 else if (optype1
== OFFSOP
)
2103 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2104 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2106 else if (optype1
== CNSTOP
)
2108 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2113 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2114 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2115 operands
[1] = GEN_INT (l
[0]);
2116 middlehalf
[1] = GEN_INT (l
[1]);
2117 latehalf
[1] = GEN_INT (l
[2]);
2121 /* No non-CONST_DOUBLE constant should ever appear
2123 gcc_assert (!CONSTANT_P (operands
[1]));
2128 middlehalf
[1] = operands
[1];
2129 latehalf
[1] = operands
[1];
2133 /* size is not 12: */
2135 if (optype0
== REGOP
)
2136 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2137 else if (optype0
== OFFSOP
)
2138 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2140 latehalf
[0] = operands
[0];
2142 if (optype1
== REGOP
)
2143 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2144 else if (optype1
== OFFSOP
)
2145 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2146 else if (optype1
== CNSTOP
)
2147 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2149 latehalf
[1] = operands
[1];
2152 /* If insn is effectively movd N(sp),-(sp) then we will do the
2153 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2154 for the low word as well, to compensate for the first decrement of sp. */
2155 if (optype0
== PUSHOP
2156 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2157 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2158 operands
[1] = middlehalf
[1] = latehalf
[1];
2160 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2161 if the upper part of reg N does not appear in the MEM, arrange to
2162 emit the move late-half first. Otherwise, compute the MEM address
2163 into the upper part of N and use that as a pointer to the memory
2165 if (optype0
== REGOP
2166 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2168 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2170 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2171 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2173 /* If both halves of dest are used in the src memory address,
2174 compute the address into latehalf of dest.
2175 Note that this can't happen if the dest is two data regs. */
2177 xops
[0] = latehalf
[0];
2178 xops
[1] = XEXP (operands
[1], 0);
2179 output_asm_insn ("lea %a1,%0", xops
);
2180 if (GET_MODE (operands
[1]) == XFmode
)
2182 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2183 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2184 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2188 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2189 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2193 && reg_overlap_mentioned_p (middlehalf
[0],
2194 XEXP (operands
[1], 0)))
2196 /* Check for two regs used by both source and dest.
2197 Note that this can't happen if the dest is all data regs.
2198 It can happen if the dest is d6, d7, a0.
2199 But in that case, latehalf is an addr reg, so
2200 the code at compadr does ok. */
2202 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2203 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2206 /* JRV says this can't happen: */
2207 gcc_assert (!addreg0
&& !addreg1
);
2209 /* Only the middle reg conflicts; simply put it last. */
2210 output_asm_insn (singlemove_string (operands
), operands
);
2211 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2212 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2215 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2216 /* If the low half of dest is mentioned in the source memory
2217 address, the arrange to emit the move late half first. */
2218 dest_overlapped_low
= 1;
2221 /* If one or both operands autodecrementing,
2222 do the two words, high-numbered first. */
2224 /* Likewise, the first move would clobber the source of the second one,
2225 do them in the other order. This happens only for registers;
2226 such overlap can't happen in memory unless the user explicitly
2227 sets it up, and that is an undefined circumstance. */
2229 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2230 || (optype0
== REGOP
&& optype1
== REGOP
2231 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2232 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2233 || dest_overlapped_low
)
2235 /* Make any unoffsettable addresses point at high-numbered word. */
2239 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2241 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2246 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2248 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2252 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2254 /* Undo the adds we just did. */
2256 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2258 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2262 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2264 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2266 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2269 /* Do low-numbered word. */
2270 return singlemove_string (operands
);
2273 /* Normal case: do the two words, low-numbered first. */
2275 output_asm_insn (singlemove_string (operands
), operands
);
2277 /* Do the middle one of the three words for long double */
2281 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2283 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2285 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2288 /* Make any unoffsettable addresses point at high-numbered word. */
2290 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2292 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2295 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2297 /* Undo the adds we just did. */
2301 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2303 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2308 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2310 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2317 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2318 new rtx with the correct mode. */
2321 force_mode (enum machine_mode mode
, rtx orig
)
2323 if (mode
== GET_MODE (orig
))
2326 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2329 return gen_rtx_REG (mode
, REGNO (orig
));
2333 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2335 return reg_renumber
&& FP_REG_P (op
);
2338 /* Emit insns to move operands[1] into operands[0].
2340 Return 1 if we have written out everything that needs to be done to
2341 do the move. Otherwise, return 0 and the caller will emit the move
2344 Note SCRATCH_REG may not be in the proper mode depending on how it
2345 will be used. This routine is resposible for creating a new copy
2346 of SCRATCH_REG in the proper mode. */
2349 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2351 register rtx operand0
= operands
[0];
2352 register rtx operand1
= operands
[1];
2356 && reload_in_progress
&& GET_CODE (operand0
) == REG
2357 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2358 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2359 else if (scratch_reg
2360 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2361 && GET_CODE (SUBREG_REG (operand0
)) == REG
2362 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2364 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2365 the code which tracks sets/uses for delete_output_reload. */
2366 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2367 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2368 SUBREG_BYTE (operand0
));
2369 operand0
= alter_subreg (&temp
);
2373 && reload_in_progress
&& GET_CODE (operand1
) == REG
2374 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2375 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2376 else if (scratch_reg
2377 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2378 && GET_CODE (SUBREG_REG (operand1
)) == REG
2379 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2381 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2382 the code which tracks sets/uses for delete_output_reload. */
2383 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2384 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2385 SUBREG_BYTE (operand1
));
2386 operand1
= alter_subreg (&temp
);
2389 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2390 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2391 != XEXP (operand0
, 0)))
2392 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2393 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2394 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2395 != XEXP (operand1
, 0)))
2396 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2398 /* Handle secondary reloads for loads/stores of FP registers where
2399 the address is symbolic by using the scratch register */
2400 if (fp_reg_operand (operand0
, mode
)
2401 && ((GET_CODE (operand1
) == MEM
2402 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2403 || ((GET_CODE (operand1
) == SUBREG
2404 && GET_CODE (XEXP (operand1
, 0)) == MEM
2405 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2408 if (GET_CODE (operand1
) == SUBREG
)
2409 operand1
= XEXP (operand1
, 0);
2411 /* SCRATCH_REG will hold an address. We want
2412 it in SImode regardless of what mode it was originally given
2414 scratch_reg
= force_mode (SImode
, scratch_reg
);
2416 /* D might not fit in 14 bits either; for such cases load D into
2418 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2420 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2421 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2423 XEXP (XEXP (operand1
, 0), 0),
2427 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2428 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2429 gen_rtx_MEM (mode
, scratch_reg
)));
2432 else if (fp_reg_operand (operand1
, mode
)
2433 && ((GET_CODE (operand0
) == MEM
2434 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2435 || ((GET_CODE (operand0
) == SUBREG
)
2436 && GET_CODE (XEXP (operand0
, 0)) == MEM
2437 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2440 if (GET_CODE (operand0
) == SUBREG
)
2441 operand0
= XEXP (operand0
, 0);
2443 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2444 it in SIMODE regardless of what mode it was originally given
2446 scratch_reg
= force_mode (SImode
, scratch_reg
);
2448 /* D might not fit in 14 bits either; for such cases load D into
2450 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2452 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2453 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2456 XEXP (XEXP (operand0
, 0),
2461 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2462 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2466 /* Handle secondary reloads for loads of FP registers from constant
2467 expressions by forcing the constant into memory.
2469 use scratch_reg to hold the address of the memory location.
2471 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2472 NO_REGS when presented with a const_int and an register class
2473 containing only FP registers. Doing so unfortunately creates
2474 more problems than it solves. Fix this for 2.5. */
2475 else if (fp_reg_operand (operand0
, mode
)
2476 && CONSTANT_P (operand1
)
2481 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2482 it in SIMODE regardless of what mode it was originally given
2484 scratch_reg
= force_mode (SImode
, scratch_reg
);
2486 /* Force the constant into memory and put the address of the
2487 memory location into scratch_reg. */
2488 xoperands
[0] = scratch_reg
;
2489 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2490 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2492 /* Now load the destination register. */
2493 emit_insn (gen_rtx_SET (mode
, operand0
,
2494 gen_rtx_MEM (mode
, scratch_reg
)));
2498 /* Now have insn-emit do whatever it normally does. */
2502 /* Return a REG that occurs in ADDR with coefficient 1.
2503 ADDR can be effectively incremented by incrementing REG. */
2506 find_addr_reg (rtx addr
)
2508 while (GET_CODE (addr
) == PLUS
)
2510 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2511 addr
= XEXP (addr
, 0);
2512 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2513 addr
= XEXP (addr
, 1);
2514 else if (CONSTANT_P (XEXP (addr
, 0)))
2515 addr
= XEXP (addr
, 1);
2516 else if (CONSTANT_P (XEXP (addr
, 1)))
2517 addr
= XEXP (addr
, 0);
2521 gcc_assert (GET_CODE (addr
) == REG
);
2525 /* Output assembler code to perform a 32-bit 3-operand add. */
2528 output_addsi3 (rtx
*operands
)
2530 if (! operands_match_p (operands
[0], operands
[1]))
2532 if (!ADDRESS_REG_P (operands
[1]))
2534 rtx tmp
= operands
[1];
2536 operands
[1] = operands
[2];
2540 /* These insns can result from reloads to access
2541 stack slots over 64k from the frame pointer. */
2542 if (GET_CODE (operands
[2]) == CONST_INT
2543 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2544 return "move%.l %2,%0\n\tadd%.l %1,%0";
2545 if (GET_CODE (operands
[2]) == REG
)
2546 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2547 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2549 if (GET_CODE (operands
[2]) == CONST_INT
)
2551 if (INTVAL (operands
[2]) > 0
2552 && INTVAL (operands
[2]) <= 8)
2553 return "addq%.l %2,%0";
2554 if (INTVAL (operands
[2]) < 0
2555 && INTVAL (operands
[2]) >= -8)
2557 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2558 return "subq%.l %2,%0";
2560 /* On the CPU32 it is faster to use two addql instructions to
2561 add a small integer (8 < N <= 16) to a register.
2562 Likewise for subql. */
2563 if (TARGET_CPU32
&& REG_P (operands
[0]))
2565 if (INTVAL (operands
[2]) > 8
2566 && INTVAL (operands
[2]) <= 16)
2568 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2569 return "addq%.l #8,%0\n\taddq%.l %2,%0";
2571 if (INTVAL (operands
[2]) < -8
2572 && INTVAL (operands
[2]) >= -16)
2574 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2575 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
2578 if (ADDRESS_REG_P (operands
[0])
2579 && INTVAL (operands
[2]) >= -0x8000
2580 && INTVAL (operands
[2]) < 0x8000)
2583 return "add%.w %2,%0";
2585 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2588 return "add%.l %2,%0";
2591 /* Store in cc_status the expressions that the condition codes will
2592 describe after execution of an instruction whose pattern is EXP.
2593 Do not alter them if the instruction would not alter the cc's. */
2595 /* On the 68000, all the insns to store in an address register fail to
2596 set the cc's. However, in some cases these instructions can make it
2597 possibly invalid to use the saved cc's. In those cases we clear out
2598 some or all of the saved cc's so they won't be used. */
2601 notice_update_cc (rtx exp
, rtx insn
)
2603 if (GET_CODE (exp
) == SET
)
2605 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2607 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2609 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2610 cc_status
.value1
= 0;
2611 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2612 cc_status
.value2
= 0;
2614 else if (!FP_REG_P (SET_DEST (exp
))
2615 && SET_DEST (exp
) != cc0_rtx
2616 && (FP_REG_P (SET_SRC (exp
))
2617 || GET_CODE (SET_SRC (exp
)) == FIX
2618 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2619 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2621 /* A pair of move insns doesn't produce a useful overall cc. */
2622 else if (!FP_REG_P (SET_DEST (exp
))
2623 && !FP_REG_P (SET_SRC (exp
))
2624 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2625 && (GET_CODE (SET_SRC (exp
)) == REG
2626 || GET_CODE (SET_SRC (exp
)) == MEM
2627 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2629 else if (SET_DEST (exp
) != pc_rtx
)
2631 cc_status
.flags
= 0;
2632 cc_status
.value1
= SET_DEST (exp
);
2633 cc_status
.value2
= SET_SRC (exp
);
2636 else if (GET_CODE (exp
) == PARALLEL
2637 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2639 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
2640 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
2642 if (ADDRESS_REG_P (dest
))
2644 else if (dest
!= pc_rtx
)
2646 cc_status
.flags
= 0;
2647 cc_status
.value1
= dest
;
2648 cc_status
.value2
= src
;
2653 if (cc_status
.value2
!= 0
2654 && ADDRESS_REG_P (cc_status
.value2
)
2655 && GET_MODE (cc_status
.value2
) == QImode
)
2657 if (cc_status
.value2
!= 0)
2658 switch (GET_CODE (cc_status
.value2
))
2660 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2661 case ROTATE
: case ROTATERT
:
2662 /* These instructions always clear the overflow bit, and set
2663 the carry to the bit shifted out. */
2664 /* ??? We don't currently have a way to signal carry not valid,
2665 nor do we check for it in the branch insns. */
2669 case PLUS
: case MINUS
: case MULT
:
2670 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2671 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2672 cc_status
.flags
|= CC_NO_OVERFLOW
;
2675 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2676 ends with a move insn moving r2 in r2's mode.
2677 Thus, the cc's are set for r2.
2678 This can set N bit spuriously. */
2679 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2684 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2686 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2687 cc_status
.value2
= 0;
2688 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2689 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2690 cc_status
.flags
= CC_IN_68881
;
2694 output_move_const_double (rtx
*operands
)
2696 int code
= standard_68881_constant_p (operands
[1]);
2700 static char buf
[40];
2702 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2705 return "fmove%.d %1,%0";
2709 output_move_const_single (rtx
*operands
)
2711 int code
= standard_68881_constant_p (operands
[1]);
2715 static char buf
[40];
2717 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
2720 return "fmove%.s %f1,%0";
2723 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2724 from the "fmovecr" instruction.
2725 The value, anded with 0xff, gives the code to use in fmovecr
2726 to get the desired constant. */
2728 /* This code has been fixed for cross-compilation. */
2730 static int inited_68881_table
= 0;
2732 static const char *const strings_68881
[7] = {
2742 static const int codes_68881
[7] = {
2752 REAL_VALUE_TYPE values_68881
[7];
2754 /* Set up values_68881 array by converting the decimal values
2755 strings_68881 to binary. */
2758 init_68881_table (void)
2762 enum machine_mode mode
;
2765 for (i
= 0; i
< 7; i
++)
2769 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2770 values_68881
[i
] = r
;
2772 inited_68881_table
= 1;
2776 standard_68881_constant_p (rtx x
)
2781 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2782 used at all on those chips. */
2783 if (TARGET_68040
|| TARGET_68060
)
2786 if (! inited_68881_table
)
2787 init_68881_table ();
2789 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2791 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2793 for (i
= 0; i
< 6; i
++)
2795 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2796 return (codes_68881
[i
]);
2799 if (GET_MODE (x
) == SFmode
)
2802 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2803 return (codes_68881
[6]);
2805 /* larger powers of ten in the constants ram are not used
2806 because they are not equal to a `double' C constant. */
2810 /* If X is a floating-point constant, return the logarithm of X base 2,
2811 or 0 if X is not a power of 2. */
2814 floating_exact_log2 (rtx x
)
2816 REAL_VALUE_TYPE r
, r1
;
2819 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2821 if (REAL_VALUES_LESS (r
, dconst1
))
2824 exp
= real_exponent (&r
);
2825 real_2expN (&r1
, exp
);
2826 if (REAL_VALUES_EQUAL (r1
, r
))
2832 /* A C compound statement to output to stdio stream STREAM the
2833 assembler syntax for an instruction operand X. X is an RTL
2836 CODE is a value that can be used to specify one of several ways
2837 of printing the operand. It is used when identical operands
2838 must be printed differently depending on the context. CODE
2839 comes from the `%' specification that was used to request
2840 printing of the operand. If the specification was just `%DIGIT'
2841 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2842 is the ASCII code for LTR.
2844 If X is a register, this macro should print the register's name.
2845 The names can be found in an array `reg_names' whose type is
2846 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2848 When the machine description has a specification `%PUNCT' (a `%'
2849 followed by a punctuation character), this macro is called with
2850 a null pointer for X and the punctuation character for CODE.
2852 The m68k specific codes are:
2854 '.' for dot needed in Motorola-style opcode names.
2855 '-' for an operand pushing on the stack:
2856 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2857 '+' for an operand pushing on the stack:
2858 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2859 '@' for a reference to the top word on the stack:
2860 sp@, (sp) or (%sp) depending on the style of syntax.
2861 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2862 but & in SGS syntax).
2863 '!' for the cc register (used in an `and to cc' insn).
2864 '$' for the letter `s' in an op code, but only on the 68040.
2865 '&' for the letter `d' in an op code, but only on the 68040.
2866 '/' for register prefix needed by longlong.h.
2868 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2869 'd' to force memory addressing to be absolute, not relative.
2870 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2871 'o' for operands to go directly to output_operand_address (bypassing
2872 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2873 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2874 or print pair of registers as rx:ry.
2879 print_operand (FILE *file
, rtx op
, int letter
)
2884 fprintf (file
, ".");
2886 else if (letter
== '#')
2887 asm_fprintf (file
, "%I");
2888 else if (letter
== '-')
2889 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2890 else if (letter
== '+')
2891 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2892 else if (letter
== '@')
2893 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2894 else if (letter
== '!')
2895 asm_fprintf (file
, "%Rfpcr");
2896 else if (letter
== '$')
2898 if (TARGET_68040_ONLY
)
2899 fprintf (file
, "s");
2901 else if (letter
== '&')
2903 if (TARGET_68040_ONLY
)
2904 fprintf (file
, "d");
2906 else if (letter
== '/')
2907 asm_fprintf (file
, "%R");
2908 else if (letter
== 'o')
2910 /* This is only for direct addresses with TARGET_PCREL */
2911 gcc_assert (GET_CODE (op
) == MEM
2912 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
2914 output_addr_const (file
, XEXP (op
, 0));
2916 else if (GET_CODE (op
) == REG
)
2919 /* Print out the second register name of a register pair.
2920 I.e., R (6) => 7. */
2921 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
2923 fputs (M68K_REGNAME(REGNO (op
)), file
);
2925 else if (GET_CODE (op
) == MEM
)
2927 output_address (XEXP (op
, 0));
2928 if (letter
== 'd' && ! TARGET_68020
2929 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2930 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2931 && INTVAL (XEXP (op
, 0)) < 0x8000
2932 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2933 fprintf (file
, MOTOROLA
? ".l" : ":l");
2935 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2938 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2939 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2941 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2944 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2945 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2947 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2950 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2951 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2955 /* Use `print_operand_address' instead of `output_addr_const'
2956 to ensure that we print relevant PIC stuff. */
2957 asm_fprintf (file
, "%I");
2959 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2960 print_operand_address (file
, op
);
2962 output_addr_const (file
, op
);
2967 /* A C compound statement to output to stdio stream STREAM the
2968 assembler syntax for an instruction operand that is a memory
2969 reference whose address is ADDR. ADDR is an RTL expression.
2971 Note that this contains a kludge that knows that the only reason
2972 we have an address (plus (label_ref...) (reg...)) when not generating
2973 PIC code is in the insn before a tablejump, and we know that m68k.md
2974 generates a label LInnn: on such an insn.
2976 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2977 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2979 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2980 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2981 we want. This difference can be accommodated by using an assembler
2982 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2983 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2984 macro. See m68k/sgs.h for an example; for versions without the bug.
2985 Some assemblers refuse all the above solutions. The workaround is to
2986 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2989 They also do not like things like "pea 1.w", so we simple leave off
2990 the .w on small constants.
2992 This routine is responsible for distinguishing between -fpic and -fPIC
2993 style relocations in an address. When generating -fpic code the
2994 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
2995 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
2998 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
2999 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3000 #else /* !MOTOROLA */
3001 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname) \
3002 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3003 #endif /* !MOTOROLA */
3006 print_operand_address (FILE *file
, rtx addr
)
3008 register rtx reg1
, reg2
, breg
, ireg
;
3011 switch (GET_CODE (addr
))
3014 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", M68K_REGNAME (REGNO (addr
)));
3017 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3018 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3021 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3022 M68K_REGNAME (REGNO (XEXP (addr
, 0))));
3025 reg1
= reg2
= ireg
= breg
= offset
= 0;
3026 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3028 offset
= XEXP (addr
, 0);
3029 addr
= XEXP (addr
, 1);
3031 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3033 offset
= XEXP (addr
, 1);
3034 addr
= XEXP (addr
, 0);
3036 if (GET_CODE (addr
) != PLUS
)
3040 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3042 reg1
= XEXP (addr
, 0);
3043 addr
= XEXP (addr
, 1);
3045 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3047 reg1
= XEXP (addr
, 1);
3048 addr
= XEXP (addr
, 0);
3050 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3052 reg1
= XEXP (addr
, 0);
3053 addr
= XEXP (addr
, 1);
3055 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3057 reg1
= XEXP (addr
, 1);
3058 addr
= XEXP (addr
, 0);
3060 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3062 reg1
= XEXP (addr
, 0);
3063 addr
= XEXP (addr
, 1);
3065 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3067 reg1
= XEXP (addr
, 1);
3068 addr
= XEXP (addr
, 0);
3070 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3071 || GET_CODE (addr
) == SIGN_EXTEND
)
3079 #if 0 /* for OLD_INDEXING */
3080 else if (GET_CODE (addr
) == PLUS
)
3082 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3084 reg2
= XEXP (addr
, 0);
3085 addr
= XEXP (addr
, 1);
3087 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3089 reg2
= XEXP (addr
, 1);
3090 addr
= XEXP (addr
, 0);
3099 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3100 || GET_CODE (reg1
) == MULT
))
3101 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3106 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3111 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3112 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3115 if (GET_CODE (ireg
) == MULT
)
3117 scale
= INTVAL (XEXP (ireg
, 1));
3118 ireg
= XEXP (ireg
, 0);
3120 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3122 ASM_OUTPUT_CASE_FETCH (file
,
3123 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3124 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3125 fprintf (file
, "w");
3129 ASM_OUTPUT_CASE_FETCH (file
,
3130 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3131 M68K_REGNAME (REGNO (ireg
)));
3132 fprintf (file
, "l");
3135 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3139 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3140 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3142 ASM_OUTPUT_CASE_FETCH (file
,
3143 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3144 M68K_REGNAME (REGNO (breg
)));
3145 fprintf (file
, "l)");
3148 if (ireg
!= 0 || breg
!= 0)
3153 gcc_assert (flag_pic
|| !addr
|| GET_CODE (addr
) != LABEL_REF
);
3159 output_addr_const (file
, addr
);
3160 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3162 fprintf (file
, "@GOT");
3164 fprintf (file
, ".w");
3167 fprintf (file
, "(%s", M68K_REGNAME (REGNO (breg
)));
3171 else /* !MOTOROLA */
3173 fprintf (file
, "%s@(", M68K_REGNAME (REGNO (breg
)));
3176 output_addr_const (file
, addr
);
3177 if (breg
== pic_offset_table_rtx
)
3181 fprintf (file
, ":w");
3184 fprintf (file
, ":l");
3193 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3195 scale
= INTVAL (XEXP (ireg
, 1));
3196 ireg
= XEXP (ireg
, 0);
3198 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3199 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3200 M68K_REGNAME (REGNO (XEXP (ireg
, 0))));
3202 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3203 M68K_REGNAME (REGNO (ireg
)));
3205 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3209 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3210 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3212 ASM_OUTPUT_CASE_FETCH (file
,
3213 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3214 M68K_REGNAME (REGNO (reg1
)));
3215 fprintf (file
, "l)");
3218 /* FALL-THROUGH (is this really what we want?) */
3220 if (GET_CODE (addr
) == CONST_INT
3221 && INTVAL (addr
) < 0x8000
3222 && INTVAL (addr
) >= -0x8000)
3224 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3226 else if (GET_CODE (addr
) == CONST_INT
)
3228 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3230 else if (TARGET_PCREL
)
3233 output_addr_const (file
, addr
);
3235 asm_fprintf (file
, ":w,%Rpc)");
3237 asm_fprintf (file
, ":l,%Rpc)");
3241 /* Special case for SYMBOL_REF if the symbol name ends in
3242 `.<letter>', this can be mistaken as a size suffix. Put
3243 the name in parentheses. */
3244 if (GET_CODE (addr
) == SYMBOL_REF
3245 && strlen (XSTR (addr
, 0)) > 2
3246 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3249 output_addr_const (file
, addr
);
3253 output_addr_const (file
, addr
);
3259 /* Check for cases where a clr insns can be omitted from code using
3260 strict_low_part sets. For example, the second clrl here is not needed:
3261 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3263 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3264 insn we are checking for redundancy. TARGET is the register set by the
3268 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3273 p
= prev_nonnote_insn (first_insn
);
3277 /* If it isn't an insn, then give up. */
3278 if (GET_CODE (p
) != INSN
)
3281 if (reg_set_p (target
, p
))
3283 rtx set
= single_set (p
);
3286 /* If it isn't an easy to recognize insn, then give up. */
3290 dest
= SET_DEST (set
);
3292 /* If this sets the entire target register to zero, then our
3293 first_insn is redundant. */
3294 if (rtx_equal_p (dest
, target
)
3295 && SET_SRC (set
) == const0_rtx
)
3297 else if (GET_CODE (dest
) == STRICT_LOW_PART
3298 && GET_CODE (XEXP (dest
, 0)) == REG
3299 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3300 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3301 <= GET_MODE_SIZE (mode
)))
3302 /* This is a strict low part set which modifies less than
3303 we are using, so it is safe. */
3309 p
= prev_nonnote_insn (p
);
3315 /* Operand predicates for implementing asymmetric pc-relative addressing
3316 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3317 when used as a source operand, but not as a destination operand.
3319 We model this by restricting the meaning of the basic predicates
3320 (general_operand, memory_operand, etc) to forbid the use of this
3321 addressing mode, and then define the following predicates that permit
3322 this addressing mode. These predicates can then be used for the
3323 source operands of the appropriate instructions.
3325 n.b. While it is theoretically possible to change all machine patterns
3326 to use this addressing more where permitted by the architecture,
3327 it has only been implemented for "common" cases: SImode, HImode, and
3328 QImode operands, and only for the principle operations that would
3329 require this addressing mode: data movement and simple integer operations.
3331 In parallel with these new predicates, two new constraint letters
3332 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3333 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3334 In the pcrel case 's' is only valid in combination with 'a' registers.
3335 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3336 of how these constraints are used.
3338 The use of these predicates is strictly optional, though patterns that
3339 don't will cause an extra reload register to be allocated where one
3342 lea (abc:w,%pc),%a0 ; need to reload address
3343 moveq &1,%d1 ; since write to pc-relative space
3344 movel %d1,%a0@ ; is not allowed
3346 lea (abc:w,%pc),%a1 ; no need to reload address here
3347 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3349 For more info, consult tiemann@cygnus.com.
3352 All of the ugliness with predicates and constraints is due to the
3353 simple fact that the m68k does not allow a pc-relative addressing
3354 mode as a destination. gcc does not distinguish between source and
3355 destination addresses. Hence, if we claim that pc-relative address
3356 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3357 end up with invalid code. To get around this problem, we left
3358 pc-relative modes as invalid addresses, and then added special
3359 predicates and constraints to accept them.
3361 A cleaner way to handle this is to modify gcc to distinguish
3362 between source and destination addresses. We can then say that
3363 pc-relative is a valid source address but not a valid destination
3364 address, and hopefully avoid a lot of the predicate and constraint
3365 hackery. Unfortunately, this would be a pretty big change. It would
3366 be a useful change for a number of ports, but there aren't any current
3367 plans to undertake this.
3369 ***************************************************************************/
3373 output_andsi3 (rtx
*operands
)
3376 if (GET_CODE (operands
[2]) == CONST_INT
3377 && (INTVAL (operands
[2]) | 0xffff) == -1
3378 && (DATA_REG_P (operands
[0])
3379 || offsettable_memref_p (operands
[0]))
3380 && !TARGET_COLDFIRE
)
3382 if (GET_CODE (operands
[0]) != REG
)
3383 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3384 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3385 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3387 if (operands
[2] == const0_rtx
)
3389 return "and%.w %2,%0";
3391 if (GET_CODE (operands
[2]) == CONST_INT
3392 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3393 && (DATA_REG_P (operands
[0])
3394 || offsettable_memref_p (operands
[0])))
3396 if (DATA_REG_P (operands
[0]))
3397 operands
[1] = GEN_INT (logval
);
3400 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3401 operands
[1] = GEN_INT (logval
% 8);
3403 /* This does not set condition codes in a standard way. */
3405 return "bclr %1,%0";
3407 return "and%.l %2,%0";
3411 output_iorsi3 (rtx
*operands
)
3413 register int logval
;
3414 if (GET_CODE (operands
[2]) == CONST_INT
3415 && INTVAL (operands
[2]) >> 16 == 0
3416 && (DATA_REG_P (operands
[0])
3417 || offsettable_memref_p (operands
[0]))
3418 && !TARGET_COLDFIRE
)
3420 if (GET_CODE (operands
[0]) != REG
)
3421 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3422 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3424 if (INTVAL (operands
[2]) == 0xffff)
3425 return "mov%.w %2,%0";
3426 return "or%.w %2,%0";
3428 if (GET_CODE (operands
[2]) == CONST_INT
3429 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3430 && (DATA_REG_P (operands
[0])
3431 || offsettable_memref_p (operands
[0])))
3433 if (DATA_REG_P (operands
[0]))
3434 operands
[1] = GEN_INT (logval
);
3437 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3438 operands
[1] = GEN_INT (logval
% 8);
3441 return "bset %1,%0";
3443 return "or%.l %2,%0";
3447 output_xorsi3 (rtx
*operands
)
3449 register int logval
;
3450 if (GET_CODE (operands
[2]) == CONST_INT
3451 && INTVAL (operands
[2]) >> 16 == 0
3452 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3453 && !TARGET_COLDFIRE
)
3455 if (! DATA_REG_P (operands
[0]))
3456 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3457 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3459 if (INTVAL (operands
[2]) == 0xffff)
3461 return "eor%.w %2,%0";
3463 if (GET_CODE (operands
[2]) == CONST_INT
3464 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3465 && (DATA_REG_P (operands
[0])
3466 || offsettable_memref_p (operands
[0])))
3468 if (DATA_REG_P (operands
[0]))
3469 operands
[1] = GEN_INT (logval
);
3472 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3473 operands
[1] = GEN_INT (logval
% 8);
3476 return "bchg %1,%0";
3478 return "eor%.l %2,%0";
3481 #ifdef M68K_TARGET_COFF
3483 /* Output assembly to switch to section NAME with attribute FLAGS. */
3486 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3487 tree decl ATTRIBUTE_UNUSED
)
3491 if (flags
& SECTION_WRITE
)
3496 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3499 #endif /* M68K_TARGET_COFF */
3502 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3503 HOST_WIDE_INT delta
,
3504 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3510 if (delta
> 0 && delta
<= 8)
3511 asm_fprintf (file
, (MOTOROLA
3512 ? "\taddq.l %I%d,4(%Rsp)\n"
3513 : "\taddql %I%d,%Rsp@(4)\n"),
3515 else if (delta
< 0 && delta
>= -8)
3516 asm_fprintf (file
, (MOTOROLA
3517 ? "\tsubq.l %I%d,4(%Rsp)\n"
3518 : "\tsubql %I%d,%Rsp@(4)\n"),
3520 else if (TARGET_COLDFIRE
)
3522 /* ColdFire can't add/sub a constant to memory unless it is in
3523 the range of addq/subq. So load the value into %d0 and
3524 then add it to 4(%sp). */
3525 if (delta
>= -128 && delta
<= 127)
3526 asm_fprintf (file
, (MOTOROLA
3527 ? "\tmoveq.l %I%wd,%Rd0\n"
3528 : "\tmoveql %I%wd,%Rd0\n"),
3531 asm_fprintf (file
, (MOTOROLA
3532 ? "\tmove.l %I%wd,%Rd0\n"
3533 : "\tmovel %I%wd,%Rd0\n"),
3535 asm_fprintf (file
, (MOTOROLA
3536 ? "\tadd.l %Rd0,4(%Rsp)\n"
3537 : "\taddl %Rd0,%Rsp@(4)\n"));
3540 asm_fprintf (file
, (MOTOROLA
3541 ? "\tadd.l %I%wd,4(%Rsp)\n"
3542 : "\taddl %I%wd,%Rsp@(4)\n"),
3545 xops
[0] = DECL_RTL (function
);
3547 /* Logic taken from call patterns in m68k.md. */
3552 else if (flag_pic
== 1 || TARGET_68020
)
3556 #if defined (USE_GAS)
3557 fmt
= "bra.l %0@PLTPC";
3559 fmt
= "bra %0@PLTPC";
3562 else /* !MOTOROLA */
3571 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3572 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3574 fmt
= "lea %0-.-8,%%a1\n\tjmp 0(%%pc,%%a1)";
3578 #if MOTOROLA && !defined (USE_GAS)
3585 output_asm_insn (fmt
, xops
);
3588 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3591 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3592 int incoming ATTRIBUTE_UNUSED
)
3594 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
3597 /* Return nonzero if register old_reg can be renamed to register new_reg. */
3599 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
3600 unsigned int new_reg
)
3603 /* Interrupt functions can only use registers that have already been
3604 saved by the prologue, even if they would normally be
3607 if (m68k_interrupt_function_p (current_function_decl
)
3608 && !regs_ever_live
[new_reg
])
3614 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
3615 On the 68000, the cpu registers can hold any mode except bytes in address
3616 registers, but the 68881 registers can hold only SFmode or DFmode. */
3618 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
3622 /* Data Registers, can hold aggregate if fits in. */
3623 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
3626 else if (regno
< 16)
3628 /* Address Registers, can't hold bytes, can hold aggregate if
3630 if (GET_MODE_SIZE (mode
) == 1)
3632 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
3635 else if (regno
< 24)
3637 /* FPU registers, hold float or complex float of long double or
3639 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3640 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3641 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
3647 /* Return floating point values in a 68881 register. This makes 68881 code
3648 a little bit faster. It also makes -msoft-float code incompatible with
3649 hard-float code, so people have to be careful not to mix the two.
3650 For ColdFire it was decided the ABI incopmatibility is undesirable.
3651 If there is need for a hard-float ABI it is probably worth doing it
3652 properly and also passing function arguments in FP registers. */
3654 m68k_libcall_value (enum machine_mode mode
)
3661 return gen_rtx_REG (mode
, 16);
3666 return gen_rtx_REG (mode
, 0);
3670 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3672 enum machine_mode mode
;
3674 mode
= TYPE_MODE (valtype
);
3680 return gen_rtx_REG (mode
, 16);
3686 /* If the function returns a pointer, push that into %a0 */
3687 if (POINTER_TYPE_P (valtype
))
3688 return gen_rtx_REG (mode
, 8);
3690 return gen_rtx_REG (mode
, 0);