1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
47 if-statements and ?: on it. This way we have compile-time error checking
48 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
49 to optimize away all constant tests. */
52 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
54 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
57 /* The ASM_DOT macro allows easy string pasting to handle the differences
58 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
59 support the %. option. */
62 # define ASM_DOTW ".w"
63 # define ASM_DOTL ".l"
71 /* Structure describing stack frame layout. */
74 /* Stack pointer to frame pointer offset. */
77 /* Offset of FPU registers. */
78 HOST_WIDE_INT foffset
;
80 /* Frame size in bytes (rounded up). */
83 /* Data and address register. */
85 unsigned int reg_mask
;
86 unsigned int reg_rev_mask
;
90 unsigned int fpu_mask
;
91 unsigned int fpu_rev_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
105 if SGS_SWITCH_TABLE. */
106 int switch_table_difference_label_flag
;
108 static rtx
find_addr_reg (rtx
);
109 static const char *singlemove_string (rtx
*);
110 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
111 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
112 #ifdef M68K_TARGET_COFF
113 static void m68k_coff_asm_named_section (const char *, unsigned int);
114 #endif /* M68K_TARGET_COFF */
116 static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
117 static void m68k_hp320_file_start (void);
119 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
120 HOST_WIDE_INT
, tree
);
121 static bool m68k_interrupt_function_p (tree func
);
122 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
123 tree args
, int flags
,
125 static void m68k_compute_frame_layout (void);
126 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
127 static int const_int_cost (rtx
);
128 static bool m68k_rtx_costs (rtx
, int, int, int *);
131 /* Alignment to use for loops and jumps */
132 /* Specify power of two alignment used for loops. */
133 const char *m68k_align_loops_string
;
134 /* Specify power of two alignment used for non-loop jumps. */
135 const char *m68k_align_jumps_string
;
136 /* Specify power of two alignment used for functions. */
137 const char *m68k_align_funcs_string
;
138 /* Specify the identification number of the library being built */
139 const char *m68k_library_id_string
;
141 /* Specify power of two alignment used for loops. */
142 int m68k_align_loops
;
143 /* Specify power of two alignment used for non-loop jumps. */
144 int m68k_align_jumps
;
145 /* Specify power of two alignment used for functions. */
146 int m68k_align_funcs
;
148 /* Nonzero if the last compare/test insn had FP operands. The
149 sCC expanders peek at this to determine what to do for the
150 68060, which has no fsCC instructions. */
151 int m68k_last_compare_had_fp_operands
;
153 /* Initialize the GCC target structure. */
155 #if INT_OP_GROUP == INT_OP_DOT_WORD
156 #undef TARGET_ASM_ALIGNED_HI_OP
157 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
160 #if INT_OP_GROUP == INT_OP_NO_DOT
161 #undef TARGET_ASM_BYTE_OP
162 #define TARGET_ASM_BYTE_OP "\tbyte\t"
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
169 #if INT_OP_GROUP == INT_OP_DC
170 #undef TARGET_ASM_BYTE_OP
171 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
178 #undef TARGET_ASM_UNALIGNED_HI_OP
179 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
180 #undef TARGET_ASM_UNALIGNED_SI_OP
181 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
183 #undef TARGET_ASM_FUNCTION_PROLOGUE
184 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
185 #undef TARGET_ASM_FUNCTION_EPILOGUE
186 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
188 #undef TARGET_ASM_INTERNAL_LABEL
189 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
192 #undef TARGET_ASM_OUTPUT_MI_THUNK
193 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
194 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
195 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
197 #undef TARGET_ASM_FILE_START_APP_OFF
198 #define TARGET_ASM_FILE_START_APP_OFF true
200 #undef TARGET_RTX_COSTS
201 #define TARGET_RTX_COSTS m68k_rtx_costs
203 #undef TARGET_ATTRIBUTE_TABLE
204 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
206 static const struct attribute_spec m68k_attribute_table
[] =
208 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
209 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
210 { NULL
, 0, 0, false, false, false, NULL
}
213 struct gcc_target targetm
= TARGET_INITIALIZER
;
215 /* Sometimes certain combinations of command options do not make
216 sense on a particular target machine. You can define a macro
217 `OVERRIDE_OPTIONS' to take account of this. This macro, if
218 defined, is executed once just after all the command options have
221 Don't use this macro to turn on various extra optimizations for
222 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
225 override_options (void)
232 /* Validate -malign-loops= value, or provide default */
233 m68k_align_loops
= def_align
;
234 if (m68k_align_loops_string
)
236 i
= atoi (m68k_align_loops_string
);
237 if (i
< 1 || i
> MAX_CODE_ALIGN
)
238 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
240 m68k_align_loops
= i
;
243 /* Library identification */
244 if (m68k_library_id_string
)
248 if (! TARGET_ID_SHARED_LIBRARY
)
249 error ("-mshared-library-id= specified without -mid-shared-library");
250 id
= atoi (m68k_library_id_string
);
251 if (id
< 0 || id
> MAX_LIBRARY_ID
)
252 error ("-mshared-library-id=%d is not between 0 and %d", id
, MAX_LIBRARY_ID
);
254 /* From now on, m68k_library_id_string will contain the library offset. */
255 asprintf ((char **)&m68k_library_id_string
, "%d", (id
* -4) - 4);
258 /* If TARGET_ID_SHARED_LIBRARY is enabled, this will point to the
260 m68k_library_id_string
= "_current_shared_library_a5_offset_";
262 /* Sanity check to ensure that msep-data and mid-sahred-library are not
263 * both specified together. Doing so simply doesn't make sense.
265 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
266 error ("cannot specify both -msep-data and -mid-shared-library");
268 /* If we're generating code for a separate A5 relative data segment,
269 * we've got to enable -fPIC as well. This might be relaxable to
270 * -fpic but it hasn't been tested properly.
272 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
275 /* Validate -malign-jumps= value, or provide default */
276 m68k_align_jumps
= def_align
;
277 if (m68k_align_jumps_string
)
279 i
= atoi (m68k_align_jumps_string
);
280 if (i
< 1 || i
> MAX_CODE_ALIGN
)
281 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
283 m68k_align_jumps
= i
;
286 /* Validate -malign-functions= value, or provide default */
287 m68k_align_funcs
= def_align
;
288 if (m68k_align_funcs_string
)
290 i
= atoi (m68k_align_funcs_string
);
291 if (i
< 1 || i
> MAX_CODE_ALIGN
)
292 error ("-malign-functions=%d is not between 1 and %d",
295 m68k_align_funcs
= i
;
298 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
300 if (!TARGET_68020
&& !TARGET_COLDFIRE
&& (flag_pic
== 2))
301 error("-fPIC is not currently supported on the 68000 or 68010\n");
303 /* ??? A historic way of turning on pic, or is this intended to
304 be an embedded thing that doesn't have the same name binding
305 significance that it does on hosted ELF systems? */
306 if (TARGET_PCREL
&& flag_pic
== 0)
309 /* Turn off function cse if we are doing PIC. We always want function call
310 to be done as `bsr foo@PLTPC', so it will force the assembler to create
311 the PLT entry for `foo'. Doing function cse will cause the address of
312 `foo' to be loaded into a register, which is exactly what we want to
313 avoid when we are doing PIC on svr4 m68k. */
315 flag_no_function_cse
= 1;
317 SUBTARGET_OVERRIDE_OPTIONS
;
320 /* Return nonzero if FUNC is an interrupt function as specified by the
321 "interrupt_handler" attribute. */
323 m68k_interrupt_function_p(tree func
)
327 if (TREE_CODE (func
) != FUNCTION_DECL
)
330 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
331 return (a
!= NULL_TREE
);
334 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
335 struct attribute_spec.handler. */
337 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
338 tree args ATTRIBUTE_UNUSED
,
339 int flags ATTRIBUTE_UNUSED
,
342 if (TREE_CODE (*node
) != FUNCTION_DECL
)
344 warning ("`%s' attribute only applies to functions",
345 IDENTIFIER_POINTER (name
));
346 *no_add_attrs
= true;
353 m68k_compute_frame_layout (void)
356 unsigned int mask
, rmask
;
357 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
359 /* Only compute the frame once per function.
360 Don't cache information until reload has been completed. */
361 if (current_frame
.funcdef_no
== current_function_funcdef_no
365 current_frame
.size
= (get_frame_size () + 3) & -4;
367 mask
= rmask
= saved
= 0;
368 for (regno
= 0; regno
< 16; regno
++)
369 if (m68k_save_reg (regno
, interrupt_handler
))
372 rmask
|= 1 << (15 - regno
);
375 current_frame
.offset
= saved
* 4;
376 current_frame
.reg_no
= saved
;
377 current_frame
.reg_mask
= mask
;
378 current_frame
.reg_rev_mask
= rmask
;
380 current_frame
.foffset
= 0;
381 mask
= rmask
= saved
= 0;
382 if (TARGET_68881
/* || TARGET_CFV4E */)
384 for (regno
= 16; regno
< 24; regno
++)
385 if (m68k_save_reg (regno
, interrupt_handler
))
387 mask
|= 1 << (regno
- 16);
388 rmask
|= 1 << (23 - regno
);
391 current_frame
.foffset
= saved
* 12 /* (TARGET_CFV4E ? 8 : 12) */;
392 current_frame
.offset
+= current_frame
.foffset
;
394 current_frame
.fpu_no
= saved
;
395 current_frame
.fpu_mask
= mask
;
396 current_frame
.fpu_rev_mask
= rmask
;
398 /* Remember what function this frame refers to. */
399 current_frame
.funcdef_no
= current_function_funcdef_no
;
403 m68k_initial_elimination_offset (int from
, int to
)
405 /* FIXME: The correct offset to compute here would appear to be
406 (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
407 but for some obscure reason, this must be 0 to get correct code. */
408 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
411 m68k_compute_frame_layout ();
413 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
414 return current_frame
.offset
+ current_frame
.size
+ (frame_pointer_needed
? -UNITS_PER_WORD
* 2 : -UNITS_PER_WORD
);
415 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
416 return current_frame
.offset
+ current_frame
.size
;
421 /* Refer to the array `regs_ever_live' to determine which registers
422 to save; `regs_ever_live[I]' is nonzero if register number I
423 is ever used in the function. This function is responsible for
424 knowing which registers should not be saved even if used.
425 Return true if we need to save REGNO. */
428 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
430 if (flag_pic
&& current_function_uses_pic_offset_table
431 && regno
== PIC_OFFSET_TABLE_REGNUM
)
434 if (current_function_calls_eh_return
)
439 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
440 if (test
== INVALID_REGNUM
)
447 /* Fixed regs we never touch. */
448 if (fixed_regs
[regno
])
451 /* The frame pointer (if it is such) is handled specially. */
452 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
455 /* Interrupt handlers must also save call_used_regs
456 if they are live or when calling nested functions. */
457 if (interrupt_handler
)
459 if (regs_ever_live
[regno
])
462 if (!current_function_is_leaf
&& call_used_regs
[regno
])
466 /* Never need to save registers that aren't touched. */
467 if (!regs_ever_live
[regno
])
470 /* Otherwise save everything that isn't call-clobbered. */
471 return !call_used_regs
[regno
];
474 /* This function generates the assembly code for function entry.
475 STREAM is a stdio stream to output the code to.
476 SIZE is an int: how many units of temporary storage to allocate. */
479 m68k_output_function_prologue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
481 HOST_WIDE_INT fsize_with_regs
;
482 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
484 m68k_compute_frame_layout();
486 /* If the stack limit is a symbol, we can check it here,
487 before actually allocating the space. */
488 if (current_function_limit_stack
489 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
490 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
491 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
493 /* On ColdFire add register save into initial stack frame setup, if possible. */
494 fsize_with_regs
= current_frame
.size
;
495 if (TARGET_COLDFIRE
&& current_frame
.reg_no
> 2)
496 fsize_with_regs
+= current_frame
.reg_no
* 4;
498 if (frame_pointer_needed
)
500 if (current_frame
.size
== 0 && TARGET_68040
)
501 /* on the 68040, pea + move is faster than link.w 0 */
502 fprintf (stream
, MOTOROLA
?
503 "\tpea (%s)\n\tmove.l %s,%s\n" :
504 "\tpea %s@\n\tmovel %s,%s\n",
505 reg_names
[FRAME_POINTER_REGNUM
],
506 reg_names
[STACK_POINTER_REGNUM
],
507 reg_names
[FRAME_POINTER_REGNUM
]);
508 else if (fsize_with_regs
< 0x8000)
509 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
510 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
511 else if (TARGET_68020
)
512 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
513 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
515 /* Adding negative number is faster on the 68040. */
516 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I0\n"
517 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
518 reg_names
[FRAME_POINTER_REGNUM
], -fsize_with_regs
);
520 if (dwarf2out_do_frame ())
523 l
= (char *) dwarf2out_cfi_label ();
525 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
526 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
527 cfa_offset
+= current_frame
.size
;
530 else if (fsize_with_regs
) /* !frame_pointer_needed */
532 if (fsize_with_regs
< 0x8000)
534 if (fsize_with_regs
<= 8)
536 if (!TARGET_COLDFIRE
)
537 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
540 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
543 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
544 /* On the CPU32 it is faster to use two subqw instructions to
545 subtract a small integer (8 < N <= 16) to a register. */
547 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
548 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
549 fsize_with_regs
- 8);
550 else if (TARGET_68040
)
551 /* Adding negative number is faster on the 68040. */
552 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
555 asm_fprintf (stream
, MOTOROLA
?
556 "\tlea (%wd,%Rsp),%Rsp\n" :
557 "\tlea %Rsp@(%wd),%Rsp\n",
560 else /* fsize_with_regs >= 0x8000 */
561 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", -fsize_with_regs
);
563 if (dwarf2out_do_frame ())
565 cfa_offset
+= current_frame
.size
+ 4;
566 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
568 } /* !frame_pointer_needed */
570 if (current_frame
.fpu_mask
)
572 asm_fprintf (stream
, MOTOROLA
?
573 "\tfmovm %I0x%x,-(%Rsp)\n" :
574 "\tfmovem %I0x%x,%Rsp@-\n",
575 current_frame
.fpu_mask
);
577 if (dwarf2out_do_frame ())
579 char *l
= (char *) dwarf2out_cfi_label ();
582 cfa_offset
+= current_frame
.fpu_no
* 12;
583 if (! frame_pointer_needed
)
584 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
585 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
586 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
587 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 12);
591 /* If the stack limit is not a symbol, check it here.
592 This has the disadvantage that it may be too late... */
593 if (current_function_limit_stack
)
595 if (REG_P (stack_limit_rtx
))
596 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
597 reg_names
[REGNO (stack_limit_rtx
)]);
598 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
599 warning ("stack limit expression is not supported");
602 if (current_frame
.reg_no
<= 2)
604 /* Store each separately in the same order moveml uses.
605 Using two movel instructions instead of a single moveml
606 is about 15% faster for the 68020 and 68030 at no expense
611 for (i
= 0; i
< 16; i
++)
612 if (current_frame
.reg_rev_mask
& (1 << i
))
614 asm_fprintf (stream
, MOTOROLA
?
615 "\t%Omove.l %s,-(%Rsp)\n" :
616 "\tmovel %s,%Rsp@-\n",
618 if (dwarf2out_do_frame ())
620 char *l
= (char *) dwarf2out_cfi_label ();
623 if (! frame_pointer_needed
)
624 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
625 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
629 else if (current_frame
.reg_rev_mask
)
632 /* The ColdFire does not support the predecrement form of the
633 MOVEM instruction, so we must adjust the stack pointer and
634 then use the plain address register indirect mode.
635 The required register save space was combined earlier with
636 the fsize_with_regs amount. */
638 asm_fprintf (stream
, MOTOROLA
?
639 "\tmovm.l %I0x%x,(%Rsp)\n" :
640 "\tmoveml %I0x%x,%Rsp@\n",
641 current_frame
.reg_mask
);
643 asm_fprintf (stream
, MOTOROLA
?
644 "\tmovm.l %I0x%x,-(%Rsp)\n" :
645 "\tmoveml %I0x%x,%Rsp@-\n",
646 current_frame
.reg_rev_mask
);
647 if (dwarf2out_do_frame ())
649 char *l
= (char *) dwarf2out_cfi_label ();
652 cfa_offset
+= current_frame
.reg_no
* 4;
653 if (! frame_pointer_needed
)
654 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
655 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
656 if (current_frame
.reg_mask
& (1 << regno
))
657 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
660 if (!TARGET_SEP_DATA
&& flag_pic
&&
661 (current_function_uses_pic_offset_table
||
662 (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
664 if (TARGET_ID_SHARED_LIBRARY
)
666 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
667 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
668 m68k_library_id_string
,
669 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
674 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
675 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
678 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
679 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
680 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
681 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
682 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
688 /* Return true if this function's epilogue can be output as RTL. */
691 use_return_insn (void)
693 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
696 /* We can output the epilogue as RTL only if no registers need to be
698 m68k_compute_frame_layout();
699 return current_frame
.reg_no
? false : true;
702 /* This function generates the assembly code for function exit,
703 on machines that need it.
705 The function epilogue should not depend on the current stack pointer!
706 It should use the frame pointer only, if there is a frame pointer.
707 This is mandatory because of alloca; we also take advantage of it to
708 omit stack adjustments before returning. */
711 m68k_output_function_epilogue (FILE *stream
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
713 HOST_WIDE_INT fsize
, fsize_with_regs
;
715 bool restore_from_sp
= false;
716 rtx insn
= get_last_insn ();
718 m68k_compute_frame_layout();
720 /* If the last insn was a BARRIER, we don't have to write any code. */
721 if (GET_CODE (insn
) == NOTE
)
722 insn
= prev_nonnote_insn (insn
);
723 if (insn
&& GET_CODE (insn
) == BARRIER
)
725 /* Output just a no-op so that debuggers don't get confused
726 about which function the pc is in at this address. */
727 fprintf (stream
, "\tnop\n");
731 #ifdef FUNCTION_EXTRA_EPILOGUE
732 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
735 fsize
= current_frame
.size
;
737 /* FIXME : leaf_function_p below is too strong.
738 What we really need to know there is if there could be pending
739 stack adjustment needed at that point. */
740 restore_from_sp
= ! frame_pointer_needed
741 || (! current_function_calls_alloca
&& leaf_function_p ());
743 /* fsize_with_regs is the size we need to adjust the sp when
744 popping the frame. */
745 fsize_with_regs
= fsize
;
747 /* Because the ColdFire doesn't support moveml with
748 complex address modes, we must adjust the stack manually
749 after restoring registers. When the frame pointer isn't used,
750 we can merge movem adjustment into frame unlinking
751 made immediately after it. */
752 if (TARGET_COLDFIRE
&& restore_from_sp
&& (current_frame
.reg_no
> 2))
753 fsize_with_regs
+= current_frame
.reg_no
* 4;
755 if (current_frame
.offset
+ fsize
>= 0x8000
757 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
759 /* Because the ColdFire doesn't support moveml with
760 complex address modes we make an extra correction here. */
762 fsize
+= current_frame
.offset
;
764 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
765 fsize
= 0, big
= true;
767 if (current_frame
.reg_no
<= 2)
769 /* Restore each separately in the same order moveml does.
770 Using two movel instructions instead of a single moveml
771 is about 15% faster for the 68020 and 68030 at no expense
775 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
777 for (i
= 0; i
< 16; i
++)
778 if (current_frame
.reg_mask
& (1 << i
))
783 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
785 reg_names
[FRAME_POINTER_REGNUM
],
788 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
789 reg_names
[FRAME_POINTER_REGNUM
],
793 else if (restore_from_sp
)
794 asm_fprintf (stream
, MOTOROLA
?
795 "\t%Omove.l (%Rsp)+,%s\n" :
796 "\tmovel %Rsp@+,%s\n",
801 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
803 reg_names
[FRAME_POINTER_REGNUM
],
806 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
807 reg_names
[FRAME_POINTER_REGNUM
],
814 else if (current_frame
.reg_mask
)
816 /* The ColdFire requires special handling due to its limited moveml insn. */
821 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
822 reg_names
[FRAME_POINTER_REGNUM
]);
823 asm_fprintf (stream
, MOTOROLA
?
824 "\tmovm.l (%Ra1),%I0x%x\n" :
825 "\tmoveml %Ra1@,%I0x%x\n",
826 current_frame
.reg_mask
);
828 else if (restore_from_sp
)
829 asm_fprintf (stream
, MOTOROLA
?
830 "\tmovm.l (%Rsp),%I0x%x\n" :
831 "\tmoveml %Rsp@,%I0x%x\n",
832 current_frame
.reg_mask
);
836 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
837 current_frame
.offset
+ fsize
,
838 reg_names
[FRAME_POINTER_REGNUM
],
839 current_frame
.reg_mask
);
841 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
842 reg_names
[FRAME_POINTER_REGNUM
],
843 current_frame
.offset
+ fsize
,
844 current_frame
.reg_mask
);
847 else /* !TARGET_COLDFIRE */
852 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
853 current_frame
.offset
+ fsize
,
854 reg_names
[FRAME_POINTER_REGNUM
],
855 current_frame
.reg_mask
);
857 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
858 reg_names
[FRAME_POINTER_REGNUM
],
859 current_frame
.offset
+ fsize
,
860 current_frame
.reg_mask
);
862 else if (restore_from_sp
)
864 asm_fprintf (stream
, MOTOROLA
?
865 "\tmovm.l (%Rsp)+,%I0x%x\n" :
866 "\tmoveml %Rsp@+,%I0x%x\n",
867 current_frame
.reg_mask
);
872 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
873 current_frame
.offset
+ fsize
,
874 reg_names
[FRAME_POINTER_REGNUM
],
875 current_frame
.reg_mask
);
877 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
878 reg_names
[FRAME_POINTER_REGNUM
],
879 current_frame
.offset
+ fsize
,
880 current_frame
.reg_mask
);
884 if (current_frame
.fpu_rev_mask
)
889 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
890 current_frame
.foffset
+ fsize
,
891 reg_names
[FRAME_POINTER_REGNUM
],
892 current_frame
.fpu_rev_mask
);
894 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
895 reg_names
[FRAME_POINTER_REGNUM
],
896 current_frame
.foffset
+ fsize
,
897 current_frame
.fpu_rev_mask
);
899 else if (restore_from_sp
)
902 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n",
903 current_frame
.fpu_rev_mask
);
905 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n",
906 current_frame
.fpu_rev_mask
);
911 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
912 current_frame
.foffset
+ fsize
,
913 reg_names
[FRAME_POINTER_REGNUM
],
914 current_frame
.fpu_rev_mask
);
916 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
917 reg_names
[FRAME_POINTER_REGNUM
],
918 current_frame
.foffset
+ fsize
,
919 current_frame
.fpu_rev_mask
);
922 if (frame_pointer_needed
)
923 fprintf (stream
, "\tunlk %s\n",
924 reg_names
[FRAME_POINTER_REGNUM
]);
925 else if (fsize_with_regs
)
927 if (fsize_with_regs
<= 8)
929 if (!TARGET_COLDFIRE
)
930 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
933 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
936 else if (fsize_with_regs
<= 16 && TARGET_CPU32
)
938 /* On the CPU32 it is faster to use two addqw instructions to
939 add a small integer (8 < N <= 16) to a register. */
940 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I8,%Rsp\n"
941 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
942 fsize_with_regs
- 8);
944 else if (fsize_with_regs
< 0x8000)
947 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
950 asm_fprintf (stream
, MOTOROLA
?
951 "\tlea (%wd,%Rsp),%Rsp\n" :
952 "\tlea %Rsp@(%wd),%Rsp\n",
956 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
958 if (current_function_calls_eh_return
)
959 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
960 if (m68k_interrupt_function_p (current_function_decl
))
961 fprintf (stream
, "\trte\n");
962 else if (current_function_pops_args
)
963 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
965 fprintf (stream
, "\trts\n");
968 /* Similar to general_operand, but exclude stack_pointer_rtx. */
971 not_sp_operand (rtx op
, enum machine_mode mode
)
973 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
976 /* Return true if X is a valid comparison operator for the dbcc
979 Note it rejects floating point comparison operators.
980 (In the future we could use Fdbcc).
982 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
985 valid_dbcc_comparison_p (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
987 switch (GET_CODE (x
))
989 case EQ
: case NE
: case GTU
: case LTU
:
993 /* Reject some when CC_NO_OVERFLOW is set. This may be over
995 case GT
: case LT
: case GE
: case LE
:
996 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1002 /* Return nonzero if flags are currently in the 68881 flag register. */
1004 flags_in_68881 (void)
1006 /* We could add support for these in the future */
1007 return cc_status
.flags
& CC_IN_68881
;
1010 /* Output a BSR instruction suitable for PIC code. */
1012 m68k_output_pic_call(rtx dest
)
1016 if (!(GET_CODE (dest
) == MEM
&& GET_CODE (XEXP (dest
, 0)) == SYMBOL_REF
))
1018 /* We output a BSR instruction if we're using -fpic or we're building for
1019 * a target that supports long branches. If we're building -fPIC on the
1020 * 68000, 68010 or ColdFire we generate one of two sequences:
1021 * a shorter one that uses a GOT entry or a longer one that doesn't.
1022 * We'll use the -Os command-line flag to decide which to generate.
1023 * Both sequences take the same time to execute on the ColdFire.
1025 else if (TARGET_PCREL
)
1027 else if ((flag_pic
== 1) || TARGET_68020
)
1030 #elif defined(USE_GAS)
1031 out
= "bsr.l %0@PLTPC";
1033 out
= "bsr %0@PLTPC";
1035 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
1036 out
= "move.l %0@GOT(%%a5), %%a1\n\tjsr (%%a1)";
1038 out
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
1040 output_asm_insn(out
, &dest
);
1043 /* Output a dbCC; jCC sequence. Note we do not handle the
1044 floating point version of this sequence (Fdbcc). We also
1045 do not handle alternative conditions when CC_NO_OVERFLOW is
1046 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1047 kick those out before we get here. */
1050 output_dbcc_and_branch (rtx
*operands
)
1052 switch (GET_CODE (operands
[3]))
1055 output_asm_insn (MOTOROLA
?
1056 "dbeq %0,%l1\n\tjbeq %l2" :
1057 "dbeq %0,%l1\n\tjeq %l2",
1062 output_asm_insn (MOTOROLA
?
1063 "dbne %0,%l1\n\tjbne %l2" :
1064 "dbne %0,%l1\n\tjne %l2",
1069 output_asm_insn (MOTOROLA
?
1070 "dbgt %0,%l1\n\tjbgt %l2" :
1071 "dbgt %0,%l1\n\tjgt %l2",
1076 output_asm_insn (MOTOROLA
?
1077 "dbhi %0,%l1\n\tjbhi %l2" :
1078 "dbhi %0,%l1\n\tjhi %l2",
1083 output_asm_insn (MOTOROLA
?
1084 "dblt %0,%l1\n\tjblt %l2" :
1085 "dblt %0,%l1\n\tjlt %l2",
1090 output_asm_insn (MOTOROLA
?
1091 "dbcs %0,%l1\n\tjbcs %l2" :
1092 "dbcs %0,%l1\n\tjcs %l2",
1097 output_asm_insn (MOTOROLA
?
1098 "dbge %0,%l1\n\tjbge %l2" :
1099 "dbge %0,%l1\n\tjge %l2",
1104 output_asm_insn (MOTOROLA
?
1105 "dbcc %0,%l1\n\tjbcc %l2" :
1106 "dbcc %0,%l1\n\tjcc %l2",
1111 output_asm_insn (MOTOROLA
?
1112 "dble %0,%l1\n\tjble %l2" :
1113 "dble %0,%l1\n\tjle %l2",
1118 output_asm_insn (MOTOROLA
?
1119 "dbls %0,%l1\n\tjbls %l2" :
1120 "dbls %0,%l1\n\tjls %l2",
1128 /* If the decrement is to be done in SImode, then we have
1129 to compensate for the fact that dbcc decrements in HImode. */
1130 switch (GET_MODE (operands
[0]))
1133 output_asm_insn (MOTOROLA
?
1134 "clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1" :
1135 "clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1",
1148 output_scc_di(rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1151 enum rtx_code op_code
= GET_CODE (op
);
1153 /* This does not produce a useful cc. */
1156 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1157 below. Swap the operands and change the op if these requirements
1158 are not fulfilled. */
1159 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1163 operand1
= operand2
;
1165 op_code
= swap_condition (op_code
);
1167 loperands
[0] = operand1
;
1168 if (GET_CODE (operand1
) == REG
)
1169 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1171 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1172 if (operand2
!= const0_rtx
)
1174 loperands
[2] = operand2
;
1175 if (GET_CODE (operand2
) == REG
)
1176 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1178 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1180 loperands
[4] = gen_label_rtx();
1181 if (operand2
!= const0_rtx
)
1184 #ifdef SGS_CMP_ORDER
1185 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1187 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1190 #ifdef SGS_CMP_ORDER
1191 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1193 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1198 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1199 output_asm_insn ("tst%.l %0", loperands
);
1202 #ifdef SGS_CMP_ORDER
1203 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1205 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1209 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1211 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1212 output_asm_insn ("tst%.l %1", loperands
);
1215 #ifdef SGS_CMP_ORDER
1216 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1218 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1223 loperands
[5] = dest
;
1228 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1229 CODE_LABEL_NUMBER (loperands
[4]));
1230 output_asm_insn ("seq %5", loperands
);
1234 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1235 CODE_LABEL_NUMBER (loperands
[4]));
1236 output_asm_insn ("sne %5", loperands
);
1240 loperands
[6] = gen_label_rtx();
1241 output_asm_insn (MOTOROLA
?
1242 "shi %5\n\tjbra %l6" :
1243 "shi %5\n\tjra %l6",
1245 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1246 CODE_LABEL_NUMBER (loperands
[4]));
1247 output_asm_insn ("sgt %5", loperands
);
1248 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1249 CODE_LABEL_NUMBER (loperands
[6]));
1253 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1254 CODE_LABEL_NUMBER (loperands
[4]));
1255 output_asm_insn ("shi %5", loperands
);
1259 loperands
[6] = gen_label_rtx();
1260 output_asm_insn (MOTOROLA
?
1261 "scs %5\n\tjbra %l6" :
1262 "scs %5\n\tjra %l6",
1264 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1265 CODE_LABEL_NUMBER (loperands
[4]));
1266 output_asm_insn ("slt %5", loperands
);
1267 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1268 CODE_LABEL_NUMBER (loperands
[6]));
1272 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1273 CODE_LABEL_NUMBER (loperands
[4]));
1274 output_asm_insn ("scs %5", loperands
);
1278 loperands
[6] = gen_label_rtx();
1279 output_asm_insn (MOTOROLA
?
1280 "scc %5\n\tjbra %l6" :
1281 "scc %5\n\tjra %l6",
1283 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1284 CODE_LABEL_NUMBER (loperands
[4]));
1285 output_asm_insn ("sge %5", loperands
);
1286 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1287 CODE_LABEL_NUMBER (loperands
[6]));
1291 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1292 CODE_LABEL_NUMBER (loperands
[4]));
1293 output_asm_insn ("scc %5", loperands
);
1297 loperands
[6] = gen_label_rtx();
1298 output_asm_insn (MOTOROLA
?
1299 "sls %5\n\tjbra %l6" :
1300 "sls %5\n\tjra %l6",
1302 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1303 CODE_LABEL_NUMBER (loperands
[4]));
1304 output_asm_insn ("sle %5", loperands
);
1305 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1306 CODE_LABEL_NUMBER (loperands
[6]));
1310 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1311 CODE_LABEL_NUMBER (loperands
[4]));
1312 output_asm_insn ("sls %5", loperands
);
1322 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1324 operands
[0] = countop
;
1325 operands
[1] = dataop
;
1327 if (GET_CODE (countop
) == CONST_INT
)
1329 register int count
= INTVAL (countop
);
1330 /* If COUNT is bigger than size of storage unit in use,
1331 advance to the containing unit of same size. */
1332 if (count
> signpos
)
1334 int offset
= (count
& ~signpos
) / 8;
1335 count
= count
& signpos
;
1336 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1338 if (count
== signpos
)
1339 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1341 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1343 /* These three statements used to use next_insns_test_no...
1344 but it appears that this should do the same job. */
1346 && next_insn_tests_no_inequality (insn
))
1349 && next_insn_tests_no_inequality (insn
))
1352 && next_insn_tests_no_inequality (insn
))
1355 cc_status
.flags
= CC_NOT_NEGATIVE
;
1357 return "btst %0,%1";
1360 /* Returns true if OP is either a symbol reference or a sum of a symbol
1361 reference and a constant. */
1364 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1366 switch (GET_CODE (op
))
1374 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1375 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1376 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1378 #if 0 /* Deleted, with corresponding change in m68k.h,
1379 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1381 return GET_MODE (op
) == mode
;
1389 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1392 extend_operator(rtx x
, enum machine_mode mode
)
1394 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1396 switch (GET_CODE(x
))
1407 /* Legitimize PIC addresses. If the address is already
1408 position-independent, we return ORIG. Newly generated
1409 position-independent addresses go to REG. If we need more
1410 than one register, we lose.
1412 An address is legitimized by making an indirect reference
1413 through the Global Offset Table with the name of the symbol
1416 The assembler and linker are responsible for placing the
1417 address of the symbol in the GOT. The function prologue
1418 is responsible for initializing a5 to the starting address
1421 The assembler is also responsible for translating a symbol name
1422 into a constant displacement from the start of the GOT.
1424 A quick example may make things a little clearer:
1426 When not generating PIC code to store the value 12345 into _foo
1427 we would generate the following code:
1431 When generating PIC two transformations are made. First, the compiler
1432 loads the address of foo into a register. So the first transformation makes:
1437 The code in movsi will intercept the lea instruction and call this
1438 routine which will transform the instructions into:
1440 movel a5@(_foo:w), a0
1444 That (in a nutshell) is how *all* symbol and label references are
1448 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1453 /* First handle a simple SYMBOL_REF or LABEL_REF */
1454 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1459 pic_ref
= gen_rtx_MEM (Pmode
,
1460 gen_rtx_PLUS (Pmode
,
1461 pic_offset_table_rtx
, orig
));
1462 current_function_uses_pic_offset_table
= 1;
1463 RTX_UNCHANGING_P (pic_ref
) = 1;
1464 emit_move_insn (reg
, pic_ref
);
1467 else if (GET_CODE (orig
) == CONST
)
1471 /* Make sure this has not already been legitimized. */
1472 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1473 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1479 /* legitimize both operands of the PLUS */
1480 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1482 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1483 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1484 base
== reg
? 0 : reg
);
1488 if (GET_CODE (orig
) == CONST_INT
)
1489 return plus_constant (base
, INTVAL (orig
));
1490 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1491 /* Likewise, should we set special REG_NOTEs here? */
1497 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1499 static CONST_METHOD
const_method (rtx
);
1501 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1504 const_method (rtx constant
)
1509 i
= INTVAL (constant
);
1513 /* The ColdFire doesn't have byte or word operations. */
1514 /* FIXME: This may not be useful for the m68060 either. */
1515 if (!TARGET_COLDFIRE
)
1517 /* if -256 < N < 256 but N is not in range for a moveq
1518 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1519 if (USE_MOVQ (i
^ 0xff))
1521 /* Likewise, try with not.w */
1522 if (USE_MOVQ (i
^ 0xffff))
1524 /* This is the only value where neg.w is useful */
1527 /* Try also with swap */
1529 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1532 /* Otherwise, use move.l */
1537 const_int_cost (rtx constant
)
1539 switch (const_method (constant
))
1542 /* Constants between -128 and 127 are cheap due to moveq */
1548 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1558 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1563 /* Constant zero is super cheap due to clr instruction. */
1564 if (x
== const0_rtx
)
1567 *total
= const_int_cost (x
);
1577 /* Make 0.0 cheaper than other floating constants to
1578 encourage creating tstsf and tstdf insns. */
1579 if (outer_code
== COMPARE
1580 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1586 /* These are vaguely right for a 68020. */
1587 /* The costs for long multiply have been adjusted to work properly
1588 in synth_mult on the 68020, relative to an average of the time
1589 for add and the time for shift, taking away a little more because
1590 sometimes move insns are needed. */
1591 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1592 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1593 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1594 TARGET_CFV3 ? 2 : 5)
1595 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1598 /* An lea costs about three times as much as a simple add. */
1599 if (GET_MODE (x
) == SImode
1600 && GET_CODE (XEXP (x
, 1)) == REG
1601 && GET_CODE (XEXP (x
, 0)) == MULT
1602 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1603 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1604 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1605 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1606 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1608 /* lea an@(dx:l:i),am */
1609 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
1619 *total
= COSTS_N_INSNS(1);
1622 if (! TARGET_68020
&& ! TARGET_COLDFIRE
)
1624 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1626 if (INTVAL (XEXP (x
, 1)) < 16)
1627 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1629 /* We're using clrw + swap for these cases. */
1630 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1633 *total
= COSTS_N_INSNS (10); /* worst case */
1636 /* A shift by a big integer takes an extra instruction. */
1637 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1638 && (INTVAL (XEXP (x
, 1)) == 16))
1640 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1643 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1644 && !(INTVAL (XEXP (x
, 1)) > 0
1645 && INTVAL (XEXP (x
, 1)) <= 8))
1647 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
1653 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1654 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1655 && GET_MODE (x
) == SImode
)
1656 *total
= COSTS_N_INSNS (MULW_COST
);
1657 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1658 *total
= COSTS_N_INSNS (MULW_COST
);
1660 *total
= COSTS_N_INSNS (MULL_COST
);
1667 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1668 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1669 else if (TARGET_CF_HWDIV
)
1670 *total
= COSTS_N_INSNS (18);
1672 *total
= COSTS_N_INSNS (43); /* div.l */
1681 output_move_const_into_data_reg (rtx
*operands
)
1685 i
= INTVAL (operands
[1]);
1686 switch (const_method (operands
[1]))
1689 return "moveq %1,%0";
1691 operands
[1] = GEN_INT (i
^ 0xff);
1692 return "moveq %1,%0\n\tnot%.b %0";
1694 operands
[1] = GEN_INT (i
^ 0xffff);
1695 return "moveq %1,%0\n\tnot%.w %0";
1697 return "moveq %#-128,%0\n\tneg%.w %0";
1702 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1703 return "moveq %1,%0\n\tswap %0";
1706 return "move%.l %1,%0";
1713 output_move_simode_const (rtx
*operands
)
1715 if (operands
[1] == const0_rtx
1716 && (DATA_REG_P (operands
[0])
1717 || GET_CODE (operands
[0]) == MEM
)
1718 /* clr insns on 68000 read before writing.
1719 This isn't so on the 68010, but we have no TARGET_68010. */
1720 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1721 || !(GET_CODE (operands
[0]) == MEM
1722 && MEM_VOLATILE_P (operands
[0]))))
1724 else if (operands
[1] == const0_rtx
1725 && ADDRESS_REG_P (operands
[0]))
1726 return "sub%.l %0,%0";
1727 else if (DATA_REG_P (operands
[0]))
1728 return output_move_const_into_data_reg (operands
);
1729 else if (ADDRESS_REG_P (operands
[0])
1730 && INTVAL (operands
[1]) < 0x8000
1731 && INTVAL (operands
[1]) >= -0x8000)
1732 return "move%.w %1,%0";
1733 else if (GET_CODE (operands
[0]) == MEM
1734 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1735 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1736 && INTVAL (operands
[1]) < 0x8000
1737 && INTVAL (operands
[1]) >= -0x8000)
1739 return "move%.l %1,%0";
1743 output_move_simode (rtx
*operands
)
1745 if (GET_CODE (operands
[1]) == CONST_INT
)
1746 return output_move_simode_const (operands
);
1747 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1748 || GET_CODE (operands
[1]) == CONST
)
1749 && push_operand (operands
[0], SImode
))
1751 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1752 || GET_CODE (operands
[1]) == CONST
)
1753 && ADDRESS_REG_P (operands
[0]))
1754 return "lea %a1,%0";
1755 return "move%.l %1,%0";
1759 output_move_himode (rtx
*operands
)
1761 if (GET_CODE (operands
[1]) == CONST_INT
)
1763 if (operands
[1] == const0_rtx
1764 && (DATA_REG_P (operands
[0])
1765 || GET_CODE (operands
[0]) == MEM
)
1766 /* clr insns on 68000 read before writing.
1767 This isn't so on the 68010, but we have no TARGET_68010. */
1768 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1769 || !(GET_CODE (operands
[0]) == MEM
1770 && MEM_VOLATILE_P (operands
[0]))))
1772 else if (operands
[1] == const0_rtx
1773 && ADDRESS_REG_P (operands
[0]))
1774 return "sub%.l %0,%0";
1775 else if (DATA_REG_P (operands
[0])
1776 && INTVAL (operands
[1]) < 128
1777 && INTVAL (operands
[1]) >= -128)
1779 return "moveq %1,%0";
1781 else if (INTVAL (operands
[1]) < 0x8000
1782 && INTVAL (operands
[1]) >= -0x8000)
1783 return "move%.w %1,%0";
1785 else if (CONSTANT_P (operands
[1]))
1786 return "move%.l %1,%0";
1787 /* Recognize the insn before a tablejump, one that refers
1788 to a table of offsets. Such an insn will need to refer
1789 to a label on the insn. So output one. Use the label-number
1790 of the table of offsets to generate this label. This code,
1791 and similar code below, assumes that there will be at most one
1792 reference to each table. */
1793 if (GET_CODE (operands
[1]) == MEM
1794 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1795 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1796 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1798 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1799 #if MOTOROLA && !defined (SGS_SWITCH_TABLES)
1801 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1802 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1804 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1805 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1806 #endif /* not SGS */
1807 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1808 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1809 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1810 #ifdef SGS_SWITCH_TABLES
1811 /* Set flag saying we need to define the symbol
1812 LD%n (with value L%n-LI%n) at the end of the switch table. */
1813 switch_table_difference_label_flag
= 1;
1814 #endif /* SGS_SWITCH_TABLES */
1815 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1817 return "move%.w %1,%0";
1821 output_move_qimode (rtx
*operands
)
1825 /* This is probably useless, since it loses for pushing a struct
1826 of several bytes a byte at a time. */
1827 /* 68k family always modifies the stack pointer by at least 2, even for
1828 byte pushes. The 5200 (ColdFire) does not do this. */
1829 if (GET_CODE (operands
[0]) == MEM
1830 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1831 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1832 && ! ADDRESS_REG_P (operands
[1])
1833 && ! TARGET_COLDFIRE
)
1835 xoperands
[1] = operands
[1];
1837 = gen_rtx_MEM (QImode
,
1838 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1839 /* Just pushing a byte puts it in the high byte of the halfword. */
1840 /* We must put it in the low-order, high-numbered byte. */
1841 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1843 xoperands
[3] = stack_pointer_rtx
;
1844 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1847 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1851 /* clr and st insns on 68000 read before writing.
1852 This isn't so on the 68010, but we have no TARGET_68010. */
1853 if (!ADDRESS_REG_P (operands
[0])
1854 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1855 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1857 if (operands
[1] == const0_rtx
)
1859 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
1860 && GET_CODE (operands
[1]) == CONST_INT
1861 && (INTVAL (operands
[1]) & 255) == 255)
1867 if (GET_CODE (operands
[1]) == CONST_INT
1868 && DATA_REG_P (operands
[0])
1869 && INTVAL (operands
[1]) < 128
1870 && INTVAL (operands
[1]) >= -128)
1872 return "moveq %1,%0";
1874 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1875 return "sub%.l %0,%0";
1876 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1877 return "move%.l %1,%0";
1878 /* 68k family (including the 5200 ColdFire) does not support byte moves to
1879 from address registers. */
1880 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1881 return "move%.w %1,%0";
1882 return "move%.b %1,%0";
1886 output_move_stricthi (rtx
*operands
)
1888 if (operands
[1] == const0_rtx
1889 /* clr insns on 68000 read before writing.
1890 This isn't so on the 68010, but we have no TARGET_68010. */
1891 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1892 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1894 return "move%.w %1,%0";
1898 output_move_strictqi (rtx
*operands
)
1900 if (operands
[1] == const0_rtx
1901 /* clr insns on 68000 read before writing.
1902 This isn't so on the 68010, but we have no TARGET_68010. */
1903 && ((TARGET_68020
|| TARGET_COLDFIRE
)
1904 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1906 return "move%.b %1,%0";
1909 /* Return the best assembler insn template
1910 for moving operands[1] into operands[0] as a fullword. */
1913 singlemove_string (rtx
*operands
)
1915 if (GET_CODE (operands
[1]) == CONST_INT
)
1916 return output_move_simode_const (operands
);
1917 return "move%.l %1,%0";
1921 /* Output assembler code to perform a doubleword move insn
1922 with operands OPERANDS. */
1925 output_move_double (rtx
*operands
)
1929 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1934 rtx addreg0
= 0, addreg1
= 0;
1935 int dest_overlapped_low
= 0;
1936 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1941 /* First classify both operands. */
1943 if (REG_P (operands
[0]))
1945 else if (offsettable_memref_p (operands
[0]))
1947 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1949 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1951 else if (GET_CODE (operands
[0]) == MEM
)
1956 if (REG_P (operands
[1]))
1958 else if (CONSTANT_P (operands
[1]))
1960 else if (offsettable_memref_p (operands
[1]))
1962 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1964 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1966 else if (GET_CODE (operands
[1]) == MEM
)
1971 /* Check for the cases that the operand constraints are not
1972 supposed to allow to happen. Abort if we get one,
1973 because generating code for these cases is painful. */
1975 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1978 /* If one operand is decrementing and one is incrementing
1979 decrement the former register explicitly
1980 and change that operand into ordinary indexing. */
1982 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1984 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1986 output_asm_insn ("sub%.l %#12,%0", operands
);
1988 output_asm_insn ("subq%.l %#8,%0", operands
);
1989 if (GET_MODE (operands
[1]) == XFmode
)
1990 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1991 else if (GET_MODE (operands
[0]) == DFmode
)
1992 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1994 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1997 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1999 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2001 output_asm_insn ("sub%.l %#12,%1", operands
);
2003 output_asm_insn ("subq%.l %#8,%1", operands
);
2004 if (GET_MODE (operands
[1]) == XFmode
)
2005 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2006 else if (GET_MODE (operands
[1]) == DFmode
)
2007 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2009 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2013 /* If an operand is an unoffsettable memory ref, find a register
2014 we can increment temporarily to make it refer to the second word. */
2016 if (optype0
== MEMOP
)
2017 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2019 if (optype1
== MEMOP
)
2020 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2022 /* Ok, we can do one word at a time.
2023 Normally we do the low-numbered word first,
2024 but if either operand is autodecrementing then we
2025 do the high-numbered word first.
2027 In either case, set up in LATEHALF the operands to use
2028 for the high-numbered word and in some cases alter the
2029 operands in OPERANDS to be suitable for the low-numbered word. */
2033 if (optype0
== REGOP
)
2035 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2036 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2038 else if (optype0
== OFFSOP
)
2040 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2041 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2045 middlehalf
[0] = operands
[0];
2046 latehalf
[0] = operands
[0];
2049 if (optype1
== REGOP
)
2051 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2052 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2054 else if (optype1
== OFFSOP
)
2056 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2057 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2059 else if (optype1
== CNSTOP
)
2061 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2066 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2067 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2068 operands
[1] = GEN_INT (l
[0]);
2069 middlehalf
[1] = GEN_INT (l
[1]);
2070 latehalf
[1] = GEN_INT (l
[2]);
2072 else if (CONSTANT_P (operands
[1]))
2074 /* actually, no non-CONST_DOUBLE constant should ever
2077 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2078 latehalf
[1] = constm1_rtx
;
2080 latehalf
[1] = const0_rtx
;
2085 middlehalf
[1] = operands
[1];
2086 latehalf
[1] = operands
[1];
2090 /* size is not 12: */
2092 if (optype0
== REGOP
)
2093 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2094 else if (optype0
== OFFSOP
)
2095 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2097 latehalf
[0] = operands
[0];
2099 if (optype1
== REGOP
)
2100 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2101 else if (optype1
== OFFSOP
)
2102 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2103 else if (optype1
== CNSTOP
)
2104 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2106 latehalf
[1] = operands
[1];
2109 /* If insn is effectively movd N(sp),-(sp) then we will do the
2110 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2111 for the low word as well, to compensate for the first decrement of sp. */
2112 if (optype0
== PUSHOP
2113 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2114 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2115 operands
[1] = middlehalf
[1] = latehalf
[1];
2117 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2118 if the upper part of reg N does not appear in the MEM, arrange to
2119 emit the move late-half first. Otherwise, compute the MEM address
2120 into the upper part of N and use that as a pointer to the memory
2122 if (optype0
== REGOP
2123 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2125 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2127 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2128 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2130 /* If both halves of dest are used in the src memory address,
2131 compute the address into latehalf of dest.
2132 Note that this can't happen if the dest is two data regs. */
2134 xops
[0] = latehalf
[0];
2135 xops
[1] = XEXP (operands
[1], 0);
2136 output_asm_insn ("lea %a1,%0", xops
);
2137 if (GET_MODE (operands
[1]) == XFmode
)
2139 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2140 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2141 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2145 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2146 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2150 && reg_overlap_mentioned_p (middlehalf
[0],
2151 XEXP (operands
[1], 0)))
2153 /* Check for two regs used by both source and dest.
2154 Note that this can't happen if the dest is all data regs.
2155 It can happen if the dest is d6, d7, a0.
2156 But in that case, latehalf is an addr reg, so
2157 the code at compadr does ok. */
2159 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2160 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2163 /* JRV says this can't happen: */
2164 if (addreg0
|| addreg1
)
2167 /* Only the middle reg conflicts; simply put it last. */
2168 output_asm_insn (singlemove_string (operands
), operands
);
2169 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2170 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2173 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2174 /* If the low half of dest is mentioned in the source memory
2175 address, the arrange to emit the move late half first. */
2176 dest_overlapped_low
= 1;
2179 /* If one or both operands autodecrementing,
2180 do the two words, high-numbered first. */
2182 /* Likewise, the first move would clobber the source of the second one,
2183 do them in the other order. This happens only for registers;
2184 such overlap can't happen in memory unless the user explicitly
2185 sets it up, and that is an undefined circumstance. */
2187 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2188 || (optype0
== REGOP
&& optype1
== REGOP
2189 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2190 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2191 || dest_overlapped_low
)
2193 /* Make any unoffsettable addresses point at high-numbered word. */
2197 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2199 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2204 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2206 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2210 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2212 /* Undo the adds we just did. */
2214 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2216 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2220 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2222 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2224 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2227 /* Do low-numbered word. */
2228 return singlemove_string (operands
);
2231 /* Normal case: do the two words, low-numbered first. */
2233 output_asm_insn (singlemove_string (operands
), operands
);
2235 /* Do the middle one of the three words for long double */
2239 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2241 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2243 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2246 /* Make any unoffsettable addresses point at high-numbered word. */
2248 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2250 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2253 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2255 /* Undo the adds we just did. */
2259 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2261 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2266 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2268 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2274 /* Return a REG that occurs in ADDR with coefficient 1.
2275 ADDR can be effectively incremented by incrementing REG. */
2278 find_addr_reg (rtx addr
)
2280 while (GET_CODE (addr
) == PLUS
)
2282 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2283 addr
= XEXP (addr
, 0);
2284 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2285 addr
= XEXP (addr
, 1);
2286 else if (CONSTANT_P (XEXP (addr
, 0)))
2287 addr
= XEXP (addr
, 1);
2288 else if (CONSTANT_P (XEXP (addr
, 1)))
2289 addr
= XEXP (addr
, 0);
2293 if (GET_CODE (addr
) == REG
)
2298 /* Output assembler code to perform a 32-bit 3-operand add. */
2301 output_addsi3 (rtx
*operands
)
2303 if (! operands_match_p (operands
[0], operands
[1]))
2305 if (!ADDRESS_REG_P (operands
[1]))
2307 rtx tmp
= operands
[1];
2309 operands
[1] = operands
[2];
2313 /* These insns can result from reloads to access
2314 stack slots over 64k from the frame pointer. */
2315 if (GET_CODE (operands
[2]) == CONST_INT
2316 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
2317 return "move%.l %2,%0\n\tadd%.l %1,%0";
2319 if (GET_CODE (operands
[2]) == REG
)
2320 return "lea 0(%1,%2.l),%0";
2322 return "lea %c2(%1),%0";
2326 if (GET_CODE (operands
[2]) == REG
)
2327 return "lea (%1,%2.l),%0";
2329 return "lea (%c2,%1),%0";
2331 else /* !MOTOROLA (MIT syntax) */
2333 if (GET_CODE (operands
[2]) == REG
)
2334 return "lea %1@(0,%2:l),%0";
2336 return "lea %1@(%c2),%0";
2340 if (GET_CODE (operands
[2]) == CONST_INT
)
2342 if (INTVAL (operands
[2]) > 0
2343 && INTVAL (operands
[2]) <= 8)
2344 return "addq%.l %2,%0";
2345 if (INTVAL (operands
[2]) < 0
2346 && INTVAL (operands
[2]) >= -8)
2348 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2349 return "subq%.l %2,%0";
2351 /* On the CPU32 it is faster to use two addql instructions to
2352 add a small integer (8 < N <= 16) to a register.
2353 Likewise for subql. */
2354 if (TARGET_CPU32
&& REG_P (operands
[0]))
2356 if (INTVAL (operands
[2]) > 8
2357 && INTVAL (operands
[2]) <= 16)
2359 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2360 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2362 if (INTVAL (operands
[2]) < -8
2363 && INTVAL (operands
[2]) >= -16)
2365 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2366 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2369 if (ADDRESS_REG_P (operands
[0])
2370 && INTVAL (operands
[2]) >= -0x8000
2371 && INTVAL (operands
[2]) < 0x8000)
2374 return "add%.w %2,%0";
2376 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2379 return "add%.l %2,%0";
2382 /* Store in cc_status the expressions that the condition codes will
2383 describe after execution of an instruction whose pattern is EXP.
2384 Do not alter them if the instruction would not alter the cc's. */
2386 /* On the 68000, all the insns to store in an address register fail to
2387 set the cc's. However, in some cases these instructions can make it
2388 possibly invalid to use the saved cc's. In those cases we clear out
2389 some or all of the saved cc's so they won't be used. */
2392 notice_update_cc (rtx exp
, rtx insn
)
2394 if (GET_CODE (exp
) == SET
)
2396 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2400 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2402 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2403 cc_status
.value1
= 0;
2404 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2405 cc_status
.value2
= 0;
2407 else if (!FP_REG_P (SET_DEST (exp
))
2408 && SET_DEST (exp
) != cc0_rtx
2409 && (FP_REG_P (SET_SRC (exp
))
2410 || GET_CODE (SET_SRC (exp
)) == FIX
2411 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2412 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2416 /* A pair of move insns doesn't produce a useful overall cc. */
2417 else if (!FP_REG_P (SET_DEST (exp
))
2418 && !FP_REG_P (SET_SRC (exp
))
2419 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2420 && (GET_CODE (SET_SRC (exp
)) == REG
2421 || GET_CODE (SET_SRC (exp
)) == MEM
2422 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2426 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2430 else if (XEXP (exp
, 0) != pc_rtx
)
2432 cc_status
.flags
= 0;
2433 cc_status
.value1
= XEXP (exp
, 0);
2434 cc_status
.value2
= XEXP (exp
, 1);
2437 else if (GET_CODE (exp
) == PARALLEL
2438 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2440 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2442 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2444 cc_status
.flags
= 0;
2445 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2446 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2451 if (cc_status
.value2
!= 0
2452 && ADDRESS_REG_P (cc_status
.value2
)
2453 && GET_MODE (cc_status
.value2
) == QImode
)
2455 if (cc_status
.value2
!= 0)
2456 switch (GET_CODE (cc_status
.value2
))
2458 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2459 case ROTATE
: case ROTATERT
:
2460 /* These instructions always clear the overflow bit, and set
2461 the carry to the bit shifted out. */
2462 /* ??? We don't currently have a way to signal carry not valid,
2463 nor do we check for it in the branch insns. */
2467 case PLUS
: case MINUS
: case MULT
:
2468 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2469 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2470 cc_status
.flags
|= CC_NO_OVERFLOW
;
2473 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2474 ends with a move insn moving r2 in r2's mode.
2475 Thus, the cc's are set for r2.
2476 This can set N bit spuriously. */
2477 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2482 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2484 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2485 cc_status
.value2
= 0;
2486 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2487 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2488 cc_status
.flags
= CC_IN_68881
;
2492 output_move_const_double (rtx
*operands
)
2494 int code
= standard_68881_constant_p (operands
[1]);
2498 static char buf
[40];
2500 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2503 return "fmove%.d %1,%0";
2507 output_move_const_single (rtx
*operands
)
2509 int code
= standard_68881_constant_p (operands
[1]);
2513 static char buf
[40];
2515 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2518 return "fmove%.s %f1,%0";
2521 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2522 from the "fmovecr" instruction.
2523 The value, anded with 0xff, gives the code to use in fmovecr
2524 to get the desired constant. */
2526 /* This code has been fixed for cross-compilation. */
2528 static int inited_68881_table
= 0;
2530 static const char *const strings_68881
[7] = {
2540 static const int codes_68881
[7] = {
2550 REAL_VALUE_TYPE values_68881
[7];
2552 /* Set up values_68881 array by converting the decimal values
2553 strings_68881 to binary. */
2556 init_68881_table (void)
2560 enum machine_mode mode
;
2563 for (i
= 0; i
< 7; i
++)
2567 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2568 values_68881
[i
] = r
;
2570 inited_68881_table
= 1;
2574 standard_68881_constant_p (rtx x
)
2579 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2580 used at all on those chips. */
2581 if (TARGET_68040
|| TARGET_68060
)
2584 if (! inited_68881_table
)
2585 init_68881_table ();
2587 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2589 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2591 for (i
= 0; i
< 6; i
++)
2593 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2594 return (codes_68881
[i
]);
2597 if (GET_MODE (x
) == SFmode
)
2600 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2601 return (codes_68881
[6]);
2603 /* larger powers of ten in the constants ram are not used
2604 because they are not equal to a `double' C constant. */
2608 /* If X is a floating-point constant, return the logarithm of X base 2,
2609 or 0 if X is not a power of 2. */
2612 floating_exact_log2 (rtx x
)
2614 REAL_VALUE_TYPE r
, r1
;
2617 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2619 if (REAL_VALUES_LESS (r
, dconst1
))
2622 exp
= real_exponent (&r
);
2623 real_2expN (&r1
, exp
);
2624 if (REAL_VALUES_EQUAL (r1
, r
))
2630 /* A C compound statement to output to stdio stream STREAM the
2631 assembler syntax for an instruction operand X. X is an RTL
2634 CODE is a value that can be used to specify one of several ways
2635 of printing the operand. It is used when identical operands
2636 must be printed differently depending on the context. CODE
2637 comes from the `%' specification that was used to request
2638 printing of the operand. If the specification was just `%DIGIT'
2639 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2640 is the ASCII code for LTR.
2642 If X is a register, this macro should print the register's name.
2643 The names can be found in an array `reg_names' whose type is
2644 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2646 When the machine description has a specification `%PUNCT' (a `%'
2647 followed by a punctuation character), this macro is called with
2648 a null pointer for X and the punctuation character for CODE.
2650 The m68k specific codes are:
2652 '.' for dot needed in Motorola-style opcode names.
2653 '-' for an operand pushing on the stack:
2654 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2655 '+' for an operand pushing on the stack:
2656 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2657 '@' for a reference to the top word on the stack:
2658 sp@, (sp) or (%sp) depending on the style of syntax.
2659 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2660 but & in SGS syntax).
2661 '!' for the cc register (used in an `and to cc' insn).
2662 '$' for the letter `s' in an op code, but only on the 68040.
2663 '&' for the letter `d' in an op code, but only on the 68040.
2664 '/' for register prefix needed by longlong.h.
2666 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2667 'd' to force memory addressing to be absolute, not relative.
2668 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2669 'o' for operands to go directly to output_operand_address (bypassing
2670 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2671 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2672 or print pair of registers as rx:ry.
2677 print_operand (FILE *file
, rtx op
, int letter
)
2682 fprintf (file
, ".");
2684 else if (letter
== '#')
2685 asm_fprintf (file
, "%I");
2686 else if (letter
== '-')
2687 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
2688 else if (letter
== '+')
2689 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
2690 else if (letter
== '@')
2691 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
2692 else if (letter
== '!')
2693 asm_fprintf (file
, "%Rfpcr");
2694 else if (letter
== '$')
2696 if (TARGET_68040_ONLY
)
2697 fprintf (file
, "s");
2699 else if (letter
== '&')
2701 if (TARGET_68040_ONLY
)
2702 fprintf (file
, "d");
2704 else if (letter
== '/')
2705 asm_fprintf (file
, "%R");
2706 else if (letter
== 'o')
2708 /* This is only for direct addresses with TARGET_PCREL */
2709 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2712 output_addr_const (file
, XEXP (op
, 0));
2714 else if (GET_CODE (op
) == REG
)
2717 /* Print out the second register name of a register pair.
2718 I.e., R (6) => 7. */
2719 fputs (reg_names
[REGNO (op
) + 1], file
);
2721 fputs (reg_names
[REGNO (op
)], file
);
2723 else if (GET_CODE (op
) == MEM
)
2725 output_address (XEXP (op
, 0));
2726 if (letter
== 'd' && ! TARGET_68020
2727 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2728 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2729 && INTVAL (XEXP (op
, 0)) < 0x8000
2730 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2731 fprintf (file
, MOTOROLA
? ".l" : ":l");
2733 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2736 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2737 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2739 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2742 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2743 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2745 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2748 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2749 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2753 /* Use `print_operand_address' instead of `output_addr_const'
2754 to ensure that we print relevant PIC stuff. */
2755 asm_fprintf (file
, "%I");
2757 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2758 print_operand_address (file
, op
);
2760 output_addr_const (file
, op
);
2765 /* A C compound statement to output to stdio stream STREAM the
2766 assembler syntax for an instruction operand that is a memory
2767 reference whose address is ADDR. ADDR is an RTL expression.
2769 Note that this contains a kludge that knows that the only reason
2770 we have an address (plus (label_ref...) (reg...)) when not generating
2771 PIC code is in the insn before a tablejump, and we know that m68k.md
2772 generates a label LInnn: on such an insn.
2774 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2775 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2777 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2778 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2779 we want. This difference can be accommodated by using an assembler
2780 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2781 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2782 macro. See m68k/sgs.h for an example; for versions without the bug.
2783 Some assemblers refuse all the above solutions. The workaround is to
2784 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2787 They also do not like things like "pea 1.w", so we simple leave off
2788 the .w on small constants.
2790 This routine is responsible for distinguishing between -fpic and -fPIC
2791 style relocations in an address. When generating -fpic code the
2792 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2793 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2795 #ifndef ASM_OUTPUT_CASE_FETCH
2798 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2799 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2801 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2802 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2804 # else /* !MOTOROLA */
2805 # define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2806 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2807 # endif /* !MOTOROLA */
2808 #endif /* ASM_OUTPUT_CASE_FETCH */
2811 print_operand_address (FILE *file
, rtx addr
)
2813 register rtx reg1
, reg2
, breg
, ireg
;
2816 switch (GET_CODE (addr
))
2819 fprintf (file
, MOTOROLA
? "(%s)" : "%s@", reg_names
[REGNO (addr
)]);
2822 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
2823 reg_names
[REGNO (XEXP (addr
, 0))]);
2826 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
2827 reg_names
[REGNO (XEXP (addr
, 0))]);
2830 reg1
= reg2
= ireg
= breg
= offset
= 0;
2831 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2833 offset
= XEXP (addr
, 0);
2834 addr
= XEXP (addr
, 1);
2836 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2838 offset
= XEXP (addr
, 1);
2839 addr
= XEXP (addr
, 0);
2841 if (GET_CODE (addr
) != PLUS
)
2845 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2847 reg1
= XEXP (addr
, 0);
2848 addr
= XEXP (addr
, 1);
2850 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2852 reg1
= XEXP (addr
, 1);
2853 addr
= XEXP (addr
, 0);
2855 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2857 reg1
= XEXP (addr
, 0);
2858 addr
= XEXP (addr
, 1);
2860 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2862 reg1
= XEXP (addr
, 1);
2863 addr
= XEXP (addr
, 0);
2865 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2867 reg1
= XEXP (addr
, 0);
2868 addr
= XEXP (addr
, 1);
2870 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2872 reg1
= XEXP (addr
, 1);
2873 addr
= XEXP (addr
, 0);
2875 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2876 || GET_CODE (addr
) == SIGN_EXTEND
)
2888 #if 0 /* for OLD_INDEXING */
2889 else if (GET_CODE (addr
) == PLUS
)
2891 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2893 reg2
= XEXP (addr
, 0);
2894 addr
= XEXP (addr
, 1);
2896 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2898 reg2
= XEXP (addr
, 1);
2899 addr
= XEXP (addr
, 0);
2911 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2912 || GET_CODE (reg1
) == MULT
))
2913 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2918 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2923 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2924 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2927 if (GET_CODE (ireg
) == MULT
)
2929 scale
= INTVAL (XEXP (ireg
, 1));
2930 ireg
= XEXP (ireg
, 0);
2932 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2934 ASM_OUTPUT_CASE_FETCH (file
,
2935 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2936 reg_names
[REGNO (XEXP (ireg
, 0))]);
2937 fprintf (file
, "w");
2941 ASM_OUTPUT_CASE_FETCH (file
,
2942 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2943 reg_names
[REGNO (ireg
)]);
2944 fprintf (file
, "l");
2947 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
2951 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2952 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2954 ASM_OUTPUT_CASE_FETCH (file
,
2955 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2956 reg_names
[REGNO (breg
)]);
2957 fprintf (file
, "l)");
2960 if (ireg
!= 0 || breg
!= 0)
2967 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2975 output_addr_const (file
, addr
);
2976 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2978 fprintf (file
, "@GOT");
2980 fprintf (file
, ".w");
2983 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2987 else /* !MOTOROLA */
2989 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2992 output_addr_const (file
, addr
);
2993 if (breg
== pic_offset_table_rtx
)
2997 fprintf (file
, ":w"); break;
2999 fprintf (file
, ":l"); break;
3007 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3009 scale
= INTVAL (XEXP (ireg
, 1));
3010 ireg
= XEXP (ireg
, 0);
3012 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3013 fprintf (file
, MOTOROLA
? "%s.w" : "%s:w",
3014 reg_names
[REGNO (XEXP (ireg
, 0))]);
3016 fprintf (file
, MOTOROLA
? "%s.l" : "%s:l",
3017 reg_names
[REGNO (ireg
)]);
3019 fprintf (file
, MOTOROLA
? "*%d" : ":%d", scale
);
3023 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3024 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3026 ASM_OUTPUT_CASE_FETCH (file
,
3027 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3028 reg_names
[REGNO (reg1
)]);
3029 fprintf (file
, "l)");
3032 /* FALL-THROUGH (is this really what we want?) */
3034 if (GET_CODE (addr
) == CONST_INT
3035 && INTVAL (addr
) < 0x8000
3036 && INTVAL (addr
) >= -0x8000)
3040 /* Many SGS assemblers croak on size specifiers for constants. */
3041 fprintf (file
, "%d", (int) INTVAL (addr
));
3043 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3045 else /* !MOTOROLA */
3046 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3048 else if (GET_CODE (addr
) == CONST_INT
)
3050 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3052 else if (TARGET_PCREL
)
3055 output_addr_const (file
, addr
);
3057 asm_fprintf (file
, ":w,%Rpc)");
3059 asm_fprintf (file
, ":l,%Rpc)");
3063 /* Special case for SYMBOL_REF if the symbol name ends in
3064 `.<letter>', this can be mistaken as a size suffix. Put
3065 the name in parentheses. */
3066 if (GET_CODE (addr
) == SYMBOL_REF
3067 && strlen (XSTR (addr
, 0)) > 2
3068 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3071 output_addr_const (file
, addr
);
3075 output_addr_const (file
, addr
);
3081 /* Check for cases where a clr insns can be omitted from code using
3082 strict_low_part sets. For example, the second clrl here is not needed:
3083 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3085 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3086 insn we are checking for redundancy. TARGET is the register set by the
3090 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3095 p
= prev_nonnote_insn (first_insn
);
3099 /* If it isn't an insn, then give up. */
3100 if (GET_CODE (p
) != INSN
)
3103 if (reg_set_p (target
, p
))
3105 rtx set
= single_set (p
);
3108 /* If it isn't an easy to recognize insn, then give up. */
3112 dest
= SET_DEST (set
);
3114 /* If this sets the entire target register to zero, then our
3115 first_insn is redundant. */
3116 if (rtx_equal_p (dest
, target
)
3117 && SET_SRC (set
) == const0_rtx
)
3119 else if (GET_CODE (dest
) == STRICT_LOW_PART
3120 && GET_CODE (XEXP (dest
, 0)) == REG
3121 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3122 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3123 <= GET_MODE_SIZE (mode
)))
3124 /* This is a strict low part set which modifies less than
3125 we are using, so it is safe. */
3131 p
= prev_nonnote_insn (p
);
3137 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3138 range carefully since this predicate is used in DImode contexts. Also, we
3139 need some extra crud to make it work when hosted on 64-bit machines. */
3142 const_uint32_operand (rtx op
, enum machine_mode mode
)
3144 /* It doesn't make sense to ask this question with a mode that is
3145 not larger than 32 bits. */
3146 if (GET_MODE_BITSIZE (mode
) <= 32)
3149 #if HOST_BITS_PER_WIDE_INT > 32
3150 /* All allowed constants will fit a CONST_INT. */
3151 return (GET_CODE (op
) == CONST_INT
3152 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3154 return (GET_CODE (op
) == CONST_INT
3155 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3159 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3160 to check the range carefully since this predicate is used in DImode
3164 const_sint32_operand (rtx op
, enum machine_mode mode
)
3166 /* It doesn't make sense to ask this question with a mode that is
3167 not larger than 32 bits. */
3168 if (GET_MODE_BITSIZE (mode
) <= 32)
3171 /* All allowed constants will fit a CONST_INT. */
3172 return (GET_CODE (op
) == CONST_INT
3173 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3176 /* Operand predicates for implementing asymmetric pc-relative addressing
3177 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3178 when used as a source operand, but not as a destination operand.
3180 We model this by restricting the meaning of the basic predicates
3181 (general_operand, memory_operand, etc) to forbid the use of this
3182 addressing mode, and then define the following predicates that permit
3183 this addressing mode. These predicates can then be used for the
3184 source operands of the appropriate instructions.
3186 n.b. While it is theoretically possible to change all machine patterns
3187 to use this addressing more where permitted by the architecture,
3188 it has only been implemented for "common" cases: SImode, HImode, and
3189 QImode operands, and only for the principle operations that would
3190 require this addressing mode: data movement and simple integer operations.
3192 In parallel with these new predicates, two new constraint letters
3193 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3194 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3195 In the pcrel case 's' is only valid in combination with 'a' registers.
3196 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3197 of how these constraints are used.
3199 The use of these predicates is strictly optional, though patterns that
3200 don't will cause an extra reload register to be allocated where one
3203 lea (abc:w,%pc),%a0 ; need to reload address
3204 moveq &1,%d1 ; since write to pc-relative space
3205 movel %d1,%a0@ ; is not allowed
3207 lea (abc:w,%pc),%a1 ; no need to reload address here
3208 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3210 For more info, consult tiemann@cygnus.com.
3213 All of the ugliness with predicates and constraints is due to the
3214 simple fact that the m68k does not allow a pc-relative addressing
3215 mode as a destination. gcc does not distinguish between source and
3216 destination addresses. Hence, if we claim that pc-relative address
3217 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3218 end up with invalid code. To get around this problem, we left
3219 pc-relative modes as invalid addresses, and then added special
3220 predicates and constraints to accept them.
3222 A cleaner way to handle this is to modify gcc to distinguish
3223 between source and destination addresses. We can then say that
3224 pc-relative is a valid source address but not a valid destination
3225 address, and hopefully avoid a lot of the predicate and constraint
3226 hackery. Unfortunately, this would be a pretty big change. It would
3227 be a useful change for a number of ports, but there aren't any current
3228 plans to undertake this.
3230 ***************************************************************************/
3233 /* Special case of a general operand that's used as a source operand.
3234 Use this to permit reads from PC-relative memory when -mpcrel
3238 general_src_operand (rtx op
, enum machine_mode mode
)
3241 && GET_CODE (op
) == MEM
3242 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3243 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3244 || GET_CODE (XEXP (op
, 0)) == CONST
))
3246 return general_operand (op
, mode
);
3249 /* Special case of a nonimmediate operand that's used as a source.
3250 Use this to permit reads from PC-relative memory when -mpcrel
3254 nonimmediate_src_operand (rtx op
, enum machine_mode mode
)
3256 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3257 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3258 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3259 || GET_CODE (XEXP (op
, 0)) == CONST
))
3261 return nonimmediate_operand (op
, mode
);
3264 /* Special case of a memory operand that's used as a source.
3265 Use this to permit reads from PC-relative memory when -mpcrel
3269 memory_src_operand (rtx op
, enum machine_mode mode
)
3271 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3272 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3273 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3274 || GET_CODE (XEXP (op
, 0)) == CONST
))
3276 return memory_operand (op
, mode
);
3279 /* Predicate that accepts only a pc-relative address. This is needed
3280 because pc-relative addresses don't satisfy the predicate
3281 "general_src_operand". */
3284 pcrel_address (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3286 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3287 || GET_CODE (op
) == CONST
);
3291 output_andsi3 (rtx
*operands
)
3294 if (GET_CODE (operands
[2]) == CONST_INT
3295 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3296 && (DATA_REG_P (operands
[0])
3297 || offsettable_memref_p (operands
[0]))
3298 && !TARGET_COLDFIRE
)
3300 if (GET_CODE (operands
[0]) != REG
)
3301 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3302 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3303 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3305 if (operands
[2] == const0_rtx
)
3307 return "and%.w %2,%0";
3309 if (GET_CODE (operands
[2]) == CONST_INT
3310 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3311 && (DATA_REG_P (operands
[0])
3312 || offsettable_memref_p (operands
[0])))
3314 if (DATA_REG_P (operands
[0]))
3316 operands
[1] = GEN_INT (logval
);
3320 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3321 operands
[1] = GEN_INT (logval
% 8);
3323 /* This does not set condition codes in a standard way. */
3325 return "bclr %1,%0";
3327 return "and%.l %2,%0";
3331 output_iorsi3 (rtx
*operands
)
3333 register int logval
;
3334 if (GET_CODE (operands
[2]) == CONST_INT
3335 && INTVAL (operands
[2]) >> 16 == 0
3336 && (DATA_REG_P (operands
[0])
3337 || offsettable_memref_p (operands
[0]))
3338 && !TARGET_COLDFIRE
)
3340 if (GET_CODE (operands
[0]) != REG
)
3341 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3342 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3344 if (INTVAL (operands
[2]) == 0xffff)
3345 return "mov%.w %2,%0";
3346 return "or%.w %2,%0";
3348 if (GET_CODE (operands
[2]) == CONST_INT
3349 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3350 && (DATA_REG_P (operands
[0])
3351 || offsettable_memref_p (operands
[0])))
3353 if (DATA_REG_P (operands
[0]))
3354 operands
[1] = GEN_INT (logval
);
3357 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3358 operands
[1] = GEN_INT (logval
% 8);
3361 return "bset %1,%0";
3363 return "or%.l %2,%0";
3367 output_xorsi3 (rtx
*operands
)
3369 register int logval
;
3370 if (GET_CODE (operands
[2]) == CONST_INT
3371 && INTVAL (operands
[2]) >> 16 == 0
3372 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3373 && !TARGET_COLDFIRE
)
3375 if (! DATA_REG_P (operands
[0]))
3376 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3377 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3379 if (INTVAL (operands
[2]) == 0xffff)
3381 return "eor%.w %2,%0";
3383 if (GET_CODE (operands
[2]) == CONST_INT
3384 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3385 && (DATA_REG_P (operands
[0])
3386 || offsettable_memref_p (operands
[0])))
3388 if (DATA_REG_P (operands
[0]))
3389 operands
[1] = GEN_INT (logval
);
3392 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3393 operands
[1] = GEN_INT (logval
% 8);
3396 return "bchg %1,%0";
3398 return "eor%.l %2,%0";
3401 #ifdef M68K_TARGET_COFF
3403 /* Output assembly to switch to section NAME with attribute FLAGS. */
3406 m68k_coff_asm_named_section (const char *name
, unsigned int flags
)
3410 if (flags
& SECTION_WRITE
)
3415 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3418 #endif /* M68K_TARGET_COFF */
3422 m68k_hp320_internal_label (FILE *stream
, const char *prefix
,
3423 unsigned long labelno
)
3425 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3426 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3428 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3432 m68k_hp320_file_start (void)
3434 /* version 1: 68010.
3435 2: 68020 without FPU.
3436 3: 68020 with FPU. */
3437 fprintf (asm_out_file
, "\tversion %d\n",
3438 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3443 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
3444 HOST_WIDE_INT delta
,
3445 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
3451 if (delta
> 0 && delta
<= 8)
3452 asm_fprintf (file
, MOTOROLA
?
3453 "\taddq.l %I%d,4(%Rsp)\n" :
3454 "\taddql %I%d,%Rsp@(4)\n",
3456 else if (delta
< 0 && delta
>= -8)
3457 asm_fprintf (file
, MOTOROLA
?
3458 "\tsubq.l %I%d,4(%Rsp)\n" :
3459 "\tsubql %I%d,%Rsp@(4)\n",
3462 asm_fprintf (file
, MOTOROLA
?
3463 "\tadd.l %I%wd,4(%Rsp)\n" :
3464 "\taddl %I%wd,%Rsp@(4)\n",
3467 xops
[0] = DECL_RTL (function
);
3469 /* Logic taken from call patterns in m68k.md. */
3474 else if ((flag_pic
== 1) || TARGET_68020
)
3479 #elif defined(USE_GAS)
3480 fmt
= "bra.l %0@PLTPC";
3482 fmt
= "bra %0@PLTPC";
3484 else /* !MOTOROLA */
3491 else if (optimize_size
|| TARGET_ID_SHARED_LIBRARY
)
3492 fmt
= "move.l %0@GOT(%%a5), %%a1\n\tjmp (%%a1)";
3494 fmt
= "lea %0-.-8,%%a1\n\tjsr 0(%%pc,%%a1)";
3498 #if MOTOROLA && !defined (USE_GAS)
3505 output_asm_insn (fmt
, xops
);