1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string
;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string
;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string
;
64 /* Specify power of two alignment used for loops. */
66 /* Specify power of two alignment used for non-loop jumps. */
68 /* Specify power of two alignment used for functions. */
72 /* Sometimes certain combinations of command options do not make
73 sense on a particular target machine. You can define a macro
74 `OVERRIDE_OPTIONS' to take account of this. This macro, if
75 defined, is executed once just after all the command options have
78 Don't use this macro to turn on various extra optimizations for
79 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
88 /* Validate -malign-loops= value, or provide default */
89 if (m68k_align_loops_string
)
91 m68k_align_loops
= atoi (m68k_align_loops_string
);
92 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
93 fatal ("-malign-loops=%d is not between 1 and %d",
94 m68k_align_loops
, MAX_CODE_ALIGN
);
97 m68k_align_loops
= def_align
;
99 /* Validate -malign-jumps= value, or provide default */
100 if (m68k_align_jumps_string
)
102 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
103 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
104 fatal ("-malign-jumps=%d is not between 1 and %d",
105 m68k_align_jumps
, MAX_CODE_ALIGN
);
108 m68k_align_jumps
= def_align
;
110 /* Validate -malign-functions= value, or provide default */
111 if (m68k_align_funcs_string
)
113 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
114 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
115 fatal ("-malign-functions=%d is not between 1 and %d",
116 m68k_align_funcs
, MAX_CODE_ALIGN
);
119 m68k_align_funcs
= def_align
;
122 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
123 function at any time during the compilation process. In the future
124 we should try and eliminate the USE if we can easily determine that
125 all PIC references were deleted from the current function. That would
126 save an address register */
131 if (flag_pic
&& current_function_uses_pic_offset_table
)
133 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
134 emit_insn_after (insn
, get_insns ());
140 /* This function generates the assembly code for function entry.
141 STREAM is a stdio stream to output the code to.
142 SIZE is an int: how many units of temporary storage to allocate.
143 Refer to the array `regs_ever_live' to determine which registers
144 to save; `regs_ever_live[I]' is nonzero if register number I
145 is ever used in the function. This function is responsible for
146 knowing which registers should not be saved even if used. */
149 /* Note that the order of the bit mask for fmovem is the opposite
150 of the order for movem! */
154 output_function_prologue (stream
, size
)
159 register int mask
= 0;
160 int num_saved_regs
= 0;
161 extern char call_used_regs
[];
162 int fsize
= (size
+ 3) & -4;
165 if (frame_pointer_needed
)
167 if (fsize
== 0 && TARGET_68040
)
169 /* on the 68040, pea + move is faster than link.w 0 */
171 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
172 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
173 reg_names
[FRAME_POINTER_REGNUM
]);
175 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
176 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
177 reg_names
[FRAME_POINTER_REGNUM
]);
180 else if (fsize
< 0x8000)
183 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
184 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
186 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
187 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
190 else if (TARGET_68020
)
193 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
194 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
196 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
197 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
202 /* Adding negative number is faster on the 68040. */
204 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
205 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
207 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
208 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
214 /* Adding negative number is faster on the 68040. */
215 if (fsize
+ 4 < 0x8000)
220 asm_fprintf (stream
, "\tlea (%0I%d,%Rsp),%Rsp\n", - (fsize
+ 4));
222 asm_fprintf (stream
, "\tlea %Rsp@(%0I%d),%Rsp\n", - (fsize
+ 4));
227 /* asm_fprintf() cannot handle %. */
229 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
231 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
237 /* asm_fprintf() cannot handle %. */
239 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
241 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
245 #ifdef SUPPORT_SUN_FPA
246 for (regno
= 24; regno
< 56; regno
++)
247 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
250 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
253 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
258 for (regno
= 16; regno
< 24; regno
++)
259 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
260 mask
|= 1 << (regno
- 16);
261 if ((mask
& 0xff) != 0)
264 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
266 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
270 for (regno
= 0; regno
< 16; regno
++)
271 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
273 mask
|= 1 << (15 - regno
);
276 if (frame_pointer_needed
)
278 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
283 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
286 if (num_saved_regs
<= 2)
288 /* Store each separately in the same order moveml uses.
289 Using two movel instructions instead of a single moveml
290 is about 15% faster for the 68020 and 68030 at no expense
295 /* Undo the work from above. */
296 for (i
= 0; i
< 16; i
++)
300 "\t%Omove.l %s,-(%Rsp)\n",
302 "\tmovel %s,%Rsp@-\n",
310 /* The coldfire does not support the predecrement form of the
311 movml instruction, so we must adjust the stack pointer and
312 then use the plain address register indirect mode. We also
313 have to invert the register save mask to use the new mode.
315 FIXME: if num_saved_regs was calculated earlier, we could
316 combine the stack pointer adjustment with any adjustment
317 done when the initial stack frame is created. This would
318 save an instruction */
323 for (i
= 0; i
< 16; i
++)
325 newmask
|= (1 << (15-i
));
328 asm_fprintf (stream
, "\tlea (%0I%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
329 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
331 asm_fprintf (stream
, "\tlea %Rsp@(%0I%d),%Rsp\n", -num_saved_regs
*4);
332 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
338 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
340 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
344 if (flag_pic
&& current_function_uses_pic_offset_table
)
347 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
348 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
350 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
351 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
352 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
353 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
354 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
359 /* Return true if this function's epilogue can be output as RTL. */
366 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
369 /* Copied from output_function_epilogue (). We should probably create a
370 separate layout routine to perform the common work. */
372 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
373 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
379 /* This function generates the assembly code for function exit,
380 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
382 The function epilogue should not depend on the current stack pointer!
383 It should use the frame pointer only, if there is a frame pointer.
384 This is mandatory because of alloca; we also take advantage of it to
385 omit stack adjustments before returning. */
388 output_function_epilogue (stream
, size
)
393 register int mask
, fmask
;
395 int offset
, foffset
, fpoffset
;
396 extern char call_used_regs
[];
397 int fsize
= (size
+ 3) & -4;
399 rtx insn
= get_last_insn ();
400 int restore_from_sp
= 0;
402 /* If the last insn was a BARRIER, we don't have to write any code. */
403 if (GET_CODE (insn
) == NOTE
)
404 insn
= prev_nonnote_insn (insn
);
405 if (insn
&& GET_CODE (insn
) == BARRIER
)
407 /* Output just a no-op so that debuggers don't get confused
408 about which function the pc is in at this address. */
409 asm_fprintf (stream
, "\tnop\n");
413 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
414 if (profile_block_flag
== 2)
416 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
420 #ifdef FUNCTION_EXTRA_EPILOGUE
421 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
423 nregs
= 0; fmask
= 0; fpoffset
= 0;
424 #ifdef SUPPORT_SUN_FPA
425 for (regno
= 24 ; regno
< 56 ; regno
++)
426 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
428 fpoffset
= nregs
* 8;
431 for (regno
= 16; regno
< 24; regno
++)
432 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
435 fmask
|= 1 << (23 - regno
);
437 foffset
= fpoffset
+ nregs
* 12;
439 if (frame_pointer_needed
)
440 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
441 for (regno
= 0; regno
< 16; regno
++)
442 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
447 offset
= foffset
+ nregs
* 4;
448 restore_from_sp
= ! frame_pointer_needed
449 || (! current_function_calls_alloca
&& leaf_function_p ());
450 if (offset
+ fsize
>= 0x8000
452 && (mask
|| fmask
|| fpoffset
))
455 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
457 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
461 if (TARGET_5200
|| nregs
<= 2)
463 /* Restore each separately in the same order moveml does.
464 Using two movel instructions instead of a single moveml
465 is about 15% faster for the 68020 and 68030 at no expense
470 /* Undo the work from above. */
471 for (i
= 0; i
< 16; i
++)
477 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
479 reg_names
[FRAME_POINTER_REGNUM
],
482 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
483 reg_names
[FRAME_POINTER_REGNUM
],
484 offset
+ fsize
, reg_names
[i
]);
487 else if (restore_from_sp
)
490 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
493 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
500 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
502 reg_names
[FRAME_POINTER_REGNUM
],
505 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
506 reg_names
[FRAME_POINTER_REGNUM
],
507 offset
+ fsize
, reg_names
[i
]);
518 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
520 reg_names
[FRAME_POINTER_REGNUM
],
523 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
524 reg_names
[FRAME_POINTER_REGNUM
],
525 offset
+ fsize
, mask
);
528 else if (restore_from_sp
)
531 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
533 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
539 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
541 reg_names
[FRAME_POINTER_REGNUM
],
544 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
545 reg_names
[FRAME_POINTER_REGNUM
],
546 offset
+ fsize
, mask
);
555 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
557 reg_names
[FRAME_POINTER_REGNUM
],
560 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
561 reg_names
[FRAME_POINTER_REGNUM
],
562 foffset
+ fsize
, fmask
);
565 else if (restore_from_sp
)
568 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
570 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
576 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
578 reg_names
[FRAME_POINTER_REGNUM
],
581 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
582 reg_names
[FRAME_POINTER_REGNUM
],
583 foffset
+ fsize
, fmask
);
588 for (regno
= 55; regno
>= 24; regno
--)
589 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
594 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
596 reg_names
[FRAME_POINTER_REGNUM
],
599 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
600 reg_names
[FRAME_POINTER_REGNUM
],
601 fpoffset
+ fsize
, reg_names
[regno
]);
604 else if (restore_from_sp
)
607 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
610 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
617 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
619 reg_names
[FRAME_POINTER_REGNUM
],
622 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
623 reg_names
[FRAME_POINTER_REGNUM
],
624 fpoffset
+ fsize
, reg_names
[regno
]);
629 if (frame_pointer_needed
)
630 fprintf (stream
, "\tunlk %s\n",
631 reg_names
[FRAME_POINTER_REGNUM
]);
634 if (fsize
+ 4 < 0x8000)
639 asm_fprintf (stream
, "\tlea (%0I%d,%Rsp),%Rsp\n", fsize
+ 4);
641 asm_fprintf (stream
, "\tlea %Rsp@(%0I%d),%Rsp\n", fsize
+ 4);
646 /* asm_fprintf() cannot handle %. */
648 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
650 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
656 /* asm_fprintf() cannot handle %. */
658 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
660 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
664 if (current_function_pops_args
)
665 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
667 fprintf (stream
, "\trts\n");
670 /* Similar to general_operand, but exclude stack_pointer_rtx. */
673 not_sp_operand (op
, mode
)
675 enum machine_mode mode
;
677 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
680 /* Return TRUE if X is a valid comparison operator for the dbcc
683 Note it rejects floating point comparison operators.
684 (In the future we could use Fdbcc).
686 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
689 valid_dbcc_comparison_p (x
, mode
)
691 enum machine_mode mode
;
693 switch (GET_CODE (x
))
695 case EQ
: case NE
: case GTU
: case LTU
:
699 /* Reject some when CC_NO_OVERFLOW is set. This may be over
701 case GT
: case LT
: case GE
: case LE
:
702 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
708 /* Return non-zero if flags are currently in the 68881 flag register. */
712 /* We could add support for these in the future */
713 return cc_status
.flags
& CC_IN_68881
;
716 /* Output a dbCC; jCC sequence. Note we do not handle the
717 floating point version of this sequence (Fdbcc). We also
718 do not handle alternative conditions when CC_NO_OVERFLOW is
719 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
720 kick those out before we get here. */
722 output_dbcc_and_branch (operands
)
725 switch (GET_CODE (operands
[3]))
729 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
731 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
737 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
739 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
745 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
747 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
753 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
755 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
761 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
763 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
769 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
771 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
777 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
779 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
785 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
787 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
793 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
795 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
801 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
803 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
811 /* If the decrement is to be done in SImode, then we have
812 to compensate for the fact that dbcc decrements in HImode. */
813 switch (GET_MODE (operands
[0]))
817 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
819 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
832 output_scc_di(op
, operand1
, operand2
, dest
)
839 enum rtx_code op_code
= GET_CODE (op
);
841 /* The m68k cmp.l instruction requires operand1 to be a reg as used
842 below. Swap the operands and change the op if these requirements
843 are not fulfilled. */
844 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
850 op_code
= swap_condition (op_code
);
852 loperands
[0] = operand1
;
853 if (GET_CODE (operand1
) == REG
)
854 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
856 loperands
[1] = adj_offsettable_operand (operand1
, 4);
857 if (operand2
!= const0_rtx
)
859 loperands
[2] = operand2
;
860 if (GET_CODE (operand2
) == REG
)
861 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
863 loperands
[3] = adj_offsettable_operand (operand2
, 4);
865 loperands
[4] = gen_label_rtx();
866 if (operand2
!= const0_rtx
)
869 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
871 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
875 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
877 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
882 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
884 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
891 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
892 CODE_LABEL_NUMBER (loperands
[4]));
893 output_asm_insn ("seq %5", loperands
);
897 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
898 CODE_LABEL_NUMBER (loperands
[4]));
899 output_asm_insn ("sne %5", loperands
);
903 loperands
[6] = gen_label_rtx();
905 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
907 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
909 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
910 CODE_LABEL_NUMBER (loperands
[4]));
911 output_asm_insn ("sgt %5", loperands
);
912 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
913 CODE_LABEL_NUMBER (loperands
[6]));
917 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
918 CODE_LABEL_NUMBER (loperands
[4]));
919 output_asm_insn ("shi %5", loperands
);
923 loperands
[6] = gen_label_rtx();
925 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
927 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
929 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
930 CODE_LABEL_NUMBER (loperands
[4]));
931 output_asm_insn ("slt %5", loperands
);
932 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
933 CODE_LABEL_NUMBER (loperands
[6]));
937 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
938 CODE_LABEL_NUMBER (loperands
[4]));
939 output_asm_insn ("scs %5", loperands
);
943 loperands
[6] = gen_label_rtx();
945 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
947 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
949 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
950 CODE_LABEL_NUMBER (loperands
[4]));
951 output_asm_insn ("sge %5", loperands
);
952 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
953 CODE_LABEL_NUMBER (loperands
[6]));
957 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
958 CODE_LABEL_NUMBER (loperands
[4]));
959 output_asm_insn ("scc %5", loperands
);
963 loperands
[6] = gen_label_rtx();
965 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
967 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
969 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
970 CODE_LABEL_NUMBER (loperands
[4]));
971 output_asm_insn ("sle %5", loperands
);
972 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
973 CODE_LABEL_NUMBER (loperands
[6]));
977 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
978 CODE_LABEL_NUMBER (loperands
[4]));
979 output_asm_insn ("sls %5", loperands
);
989 output_btst (operands
, countop
, dataop
, insn
, signpos
)
995 operands
[0] = countop
;
996 operands
[1] = dataop
;
998 if (GET_CODE (countop
) == CONST_INT
)
1000 register int count
= INTVAL (countop
);
1001 /* If COUNT is bigger than size of storage unit in use,
1002 advance to the containing unit of same size. */
1003 if (count
> signpos
)
1005 int offset
= (count
& ~signpos
) / 8;
1006 count
= count
& signpos
;
1007 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1009 if (count
== signpos
)
1010 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1012 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1014 /* These three statements used to use next_insns_test_no...
1015 but it appears that this should do the same job. */
1017 && next_insn_tests_no_inequality (insn
))
1020 && next_insn_tests_no_inequality (insn
))
1023 && next_insn_tests_no_inequality (insn
))
1026 cc_status
.flags
= CC_NOT_NEGATIVE
;
1028 return "btst %0,%1";
1031 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1032 reference and a constant. */
1035 symbolic_operand (op
, mode
)
1037 enum machine_mode mode
;
1039 switch (GET_CODE (op
))
1047 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1048 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1049 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1051 #if 0 /* Deleted, with corresponding change in m68k.h,
1052 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1054 return GET_MODE (op
) == mode
;
1062 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1065 extend_operator(x
, mode
)
1067 enum machine_mode mode
;
1069 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1071 switch (GET_CODE(x
))
1082 /* Legitimize PIC addresses. If the address is already
1083 position-independent, we return ORIG. Newly generated
1084 position-independent addresses go to REG. If we need more
1085 than one register, we lose.
1087 An address is legitimized by making an indirect reference
1088 through the Global Offset Table with the name of the symbol
1091 The assembler and linker are responsible for placing the
1092 address of the symbol in the GOT. The function prologue
1093 is responsible for initializing a5 to the starting address
1096 The assembler is also responsible for translating a symbol name
1097 into a constant displacement from the start of the GOT.
1099 A quick example may make things a little clearer:
1101 When not generating PIC code to store the value 12345 into _foo
1102 we would generate the following code:
1106 When generating PIC two transformations are made. First, the compiler
1107 loads the address of foo into a register. So the first transformation makes:
1112 The code in movsi will intercept the lea instruction and call this
1113 routine which will transform the instructions into:
1115 movel a5@(_foo:w), a0
1119 That (in a nutshell) is how *all* symbol and label references are
1123 legitimize_pic_address (orig
, mode
, reg
)
1125 enum machine_mode mode
;
1129 /* First handle a simple SYMBOL_REF or LABEL_REF */
1130 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1135 pic_ref
= gen_rtx (MEM
, Pmode
,
1136 gen_rtx (PLUS
, Pmode
,
1137 pic_offset_table_rtx
, orig
));
1138 current_function_uses_pic_offset_table
= 1;
1139 RTX_UNCHANGING_P (pic_ref
) = 1;
1140 emit_move_insn (reg
, pic_ref
);
1143 else if (GET_CODE (orig
) == CONST
)
1147 /* Make sure this is CONST has not already been legitimized */
1148 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1149 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1155 /* legitimize both operands of the PLUS */
1156 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1158 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1159 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1160 base
== reg
? 0 : reg
);
1164 if (GET_CODE (orig
) == CONST_INT
)
1165 return plus_constant_for_output (base
, INTVAL (orig
));
1166 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1167 /* Likewise, should we set special REG_NOTEs here? */
1173 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1175 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1178 const_method (constant
)
1184 i
= INTVAL (constant
);
1188 /* The Coldfire doesn't have byte or word operations. */
1189 /* FIXME: This may not be useful for the m68060 either */
1192 /* if -256 < N < 256 but N is not in range for a moveq
1193 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1194 if (USE_MOVQ (i
^ 0xff))
1196 /* Likewise, try with not.w */
1197 if (USE_MOVQ (i
^ 0xffff))
1199 /* This is the only value where neg.w is useful */
1202 /* Try also with swap */
1204 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1207 /* Otherwise, use move.l */
1211 const_int_cost (constant
)
1214 switch (const_method (constant
))
1217 /* Constants between -128 and 127 are cheap due to moveq */
1223 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1233 output_move_const_into_data_reg (operands
)
1238 i
= INTVAL (operands
[1]);
1239 switch (const_method (operands
[1]))
1242 #if defined (MOTOROLA) && !defined (CRDS)
1243 return "moveq%.l %1,%0";
1245 return "moveq %1,%0";
1248 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1249 #if defined (MOTOROLA) && !defined (CRDS)
1250 return "moveq%.l %1,%0\n\tnot%.b %0";
1252 return "moveq %1,%0\n\tnot%.b %0";
1255 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1256 #if defined (MOTOROLA) && !defined (CRDS)
1257 return "moveq%.l %1,%0\n\tnot%.w %0";
1259 return "moveq %1,%0\n\tnot%.w %0";
1262 #if defined (MOTOROLA) && !defined (CRDS)
1263 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1265 return "moveq %#-128,%0\n\tneg%.w %0";
1271 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1272 #if defined (MOTOROLA) && !defined (CRDS)
1273 return "moveq%.l %1,%0\n\tswap %0";
1275 return "moveq %1,%0\n\tswap %0";
1279 return "move%.l %1,%0";
1286 output_move_simode_const (operands
)
1289 if (operands
[1] == const0_rtx
1290 && (DATA_REG_P (operands
[0])
1291 || GET_CODE (operands
[0]) == MEM
)
1292 /* clr insns on 68000 read before writing.
1293 This isn't so on the 68010, but we have no alternative for it. */
1295 || !(GET_CODE (operands
[0]) == MEM
1296 && MEM_VOLATILE_P (operands
[0]))))
1298 else if (DATA_REG_P (operands
[0]))
1299 return output_move_const_into_data_reg (operands
);
1300 else if (ADDRESS_REG_P (operands
[0])
1301 && INTVAL (operands
[1]) < 0x8000
1302 && INTVAL (operands
[1]) >= -0x8000)
1303 return "move%.w %1,%0";
1304 else if (GET_CODE (operands
[0]) == MEM
1305 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1306 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1307 && INTVAL (operands
[1]) < 0x8000
1308 && INTVAL (operands
[1]) >= -0x8000)
1310 return "move%.l %1,%0";
1313 /* Return the best assembler insn template
1314 for moving operands[1] into operands[0] as a fullword. */
1317 singlemove_string (operands
)
1320 #ifdef SUPPORT_SUN_FPA
1321 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1322 return "fpmoves %1,%0";
1324 if (GET_CODE (operands
[1]) == CONST_INT
)
1325 return output_move_simode_const (operands
);
1326 return "move%.l %1,%0";
1330 /* Output assembler code to perform a doubleword move insn
1331 with operands OPERANDS. */
1334 output_move_double (operands
)
1339 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1344 rtx addreg0
= 0, addreg1
= 0;
1345 int dest_overlapped_low
= 0;
1346 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1351 /* First classify both operands. */
1353 if (REG_P (operands
[0]))
1355 else if (offsettable_memref_p (operands
[0]))
1357 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1359 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1361 else if (GET_CODE (operands
[0]) == MEM
)
1366 if (REG_P (operands
[1]))
1368 else if (CONSTANT_P (operands
[1]))
1370 else if (offsettable_memref_p (operands
[1]))
1372 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1374 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1376 else if (GET_CODE (operands
[1]) == MEM
)
1381 /* Check for the cases that the operand constraints are not
1382 supposed to allow to happen. Abort if we get one,
1383 because generating code for these cases is painful. */
1385 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1388 /* If one operand is decrementing and one is incrementing
1389 decrement the former register explicitly
1390 and change that operand into ordinary indexing. */
1392 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1394 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1396 output_asm_insn ("sub%.l %#12,%0", operands
);
1398 output_asm_insn ("subq%.l %#8,%0", operands
);
1399 if (GET_MODE (operands
[1]) == XFmode
)
1400 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1401 else if (GET_MODE (operands
[0]) == DFmode
)
1402 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1404 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1407 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1409 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1411 output_asm_insn ("sub%.l %#12,%1", operands
);
1413 output_asm_insn ("subq%.l %#8,%1", operands
);
1414 if (GET_MODE (operands
[1]) == XFmode
)
1415 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1416 else if (GET_MODE (operands
[1]) == DFmode
)
1417 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1419 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1423 /* If an operand is an unoffsettable memory ref, find a register
1424 we can increment temporarily to make it refer to the second word. */
1426 if (optype0
== MEMOP
)
1427 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1429 if (optype1
== MEMOP
)
1430 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1432 /* Ok, we can do one word at a time.
1433 Normally we do the low-numbered word first,
1434 but if either operand is autodecrementing then we
1435 do the high-numbered word first.
1437 In either case, set up in LATEHALF the operands to use
1438 for the high-numbered word and in some cases alter the
1439 operands in OPERANDS to be suitable for the low-numbered word. */
1443 if (optype0
== REGOP
)
1445 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1446 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1448 else if (optype0
== OFFSOP
)
1450 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1451 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1455 middlehalf
[0] = operands
[0];
1456 latehalf
[0] = operands
[0];
1459 if (optype1
== REGOP
)
1461 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1462 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1464 else if (optype1
== OFFSOP
)
1466 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1467 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1469 else if (optype1
== CNSTOP
)
1471 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1476 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1477 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1478 operands
[1] = GEN_INT (l
[0]);
1479 middlehalf
[1] = GEN_INT (l
[1]);
1480 latehalf
[1] = GEN_INT (l
[2]);
1482 else if (CONSTANT_P (operands
[1]))
1484 /* actually, no non-CONST_DOUBLE constant should ever
1487 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1488 latehalf
[1] = constm1_rtx
;
1490 latehalf
[1] = const0_rtx
;
1495 middlehalf
[1] = operands
[1];
1496 latehalf
[1] = operands
[1];
1500 /* size is not 12: */
1502 if (optype0
== REGOP
)
1503 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1504 else if (optype0
== OFFSOP
)
1505 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1507 latehalf
[0] = operands
[0];
1509 if (optype1
== REGOP
)
1510 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1511 else if (optype1
== OFFSOP
)
1512 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1513 else if (optype1
== CNSTOP
)
1514 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1516 latehalf
[1] = operands
[1];
1519 /* If insn is effectively movd N(sp),-(sp) then we will do the
1520 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1521 for the low word as well, to compensate for the first decrement of sp. */
1522 if (optype0
== PUSHOP
1523 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1524 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1525 operands
[1] = middlehalf
[1] = latehalf
[1];
1527 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1528 if the upper part of reg N does not appear in the MEM, arrange to
1529 emit the move late-half first. Otherwise, compute the MEM address
1530 into the upper part of N and use that as a pointer to the memory
1532 if (optype0
== REGOP
1533 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1535 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1537 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1538 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1540 /* If both halves of dest are used in the src memory address,
1541 compute the address into latehalf of dest.
1542 Note that this can't happen if the dest is two data regs. */
1544 xops
[0] = latehalf
[0];
1545 xops
[1] = XEXP (operands
[1], 0);
1546 output_asm_insn ("lea %a1,%0", xops
);
1547 if( GET_MODE (operands
[1]) == XFmode
)
1549 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1550 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1551 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1555 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1556 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1560 && reg_overlap_mentioned_p (middlehalf
[0],
1561 XEXP (operands
[1], 0)))
1563 /* Check for two regs used by both source and dest.
1564 Note that this can't happen if the dest is all data regs.
1565 It can happen if the dest is d6, d7, a0.
1566 But in that case, latehalf is an addr reg, so
1567 the code at compadr does ok. */
1569 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1570 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1573 /* JRV says this can't happen: */
1574 if (addreg0
|| addreg1
)
1577 /* Only the middle reg conflicts; simply put it last. */
1578 output_asm_insn (singlemove_string (operands
), operands
);
1579 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1580 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1583 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1584 /* If the low half of dest is mentioned in the source memory
1585 address, the arrange to emit the move late half first. */
1586 dest_overlapped_low
= 1;
1589 /* If one or both operands autodecrementing,
1590 do the two words, high-numbered first. */
1592 /* Likewise, the first move would clobber the source of the second one,
1593 do them in the other order. This happens only for registers;
1594 such overlap can't happen in memory unless the user explicitly
1595 sets it up, and that is an undefined circumstance. */
1597 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1598 || (optype0
== REGOP
&& optype1
== REGOP
1599 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1600 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1601 || dest_overlapped_low
)
1603 /* Make any unoffsettable addresses point at high-numbered word. */
1607 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1609 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1614 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1616 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1620 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1622 /* Undo the adds we just did. */
1624 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1626 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1630 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1632 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1634 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1637 /* Do low-numbered word. */
1638 return singlemove_string (operands
);
1641 /* Normal case: do the two words, low-numbered first. */
1643 output_asm_insn (singlemove_string (operands
), operands
);
1645 /* Do the middle one of the three words for long double */
1649 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1651 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1653 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1656 /* Make any unoffsettable addresses point at high-numbered word. */
1658 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1660 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1663 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1665 /* Undo the adds we just did. */
1669 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1671 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1676 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1678 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1684 /* Return a REG that occurs in ADDR with coefficient 1.
1685 ADDR can be effectively incremented by incrementing REG. */
1688 find_addr_reg (addr
)
1691 while (GET_CODE (addr
) == PLUS
)
1693 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1694 addr
= XEXP (addr
, 0);
1695 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1696 addr
= XEXP (addr
, 1);
1697 else if (CONSTANT_P (XEXP (addr
, 0)))
1698 addr
= XEXP (addr
, 1);
1699 else if (CONSTANT_P (XEXP (addr
, 1)))
1700 addr
= XEXP (addr
, 0);
1704 if (GET_CODE (addr
) == REG
)
1709 /* Store in cc_status the expressions that the condition codes will
1710 describe after execution of an instruction whose pattern is EXP.
1711 Do not alter them if the instruction would not alter the cc's. */
1713 /* On the 68000, all the insns to store in an address register fail to
1714 set the cc's. However, in some cases these instructions can make it
1715 possibly invalid to use the saved cc's. In those cases we clear out
1716 some or all of the saved cc's so they won't be used. */
1718 notice_update_cc (exp
, insn
)
1722 /* If the cc is being set from the fpa and the expression is not an
1723 explicit floating point test instruction (which has code to deal with
1724 this), reinit the CC. */
1725 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1726 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1727 && !(GET_CODE (exp
) == PARALLEL
1728 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1729 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1733 else if (GET_CODE (exp
) == SET
)
1735 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1739 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1741 if (cc_status
.value1
1742 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1743 cc_status
.value1
= 0;
1744 if (cc_status
.value2
1745 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1746 cc_status
.value2
= 0;
1748 else if (!FP_REG_P (SET_DEST (exp
))
1749 && SET_DEST (exp
) != cc0_rtx
1750 && (FP_REG_P (SET_SRC (exp
))
1751 || GET_CODE (SET_SRC (exp
)) == FIX
1752 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1753 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1757 /* A pair of move insns doesn't produce a useful overall cc. */
1758 else if (!FP_REG_P (SET_DEST (exp
))
1759 && !FP_REG_P (SET_SRC (exp
))
1760 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1761 && (GET_CODE (SET_SRC (exp
)) == REG
1762 || GET_CODE (SET_SRC (exp
)) == MEM
1763 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
1767 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1771 else if (XEXP (exp
, 0) != pc_rtx
)
1773 cc_status
.flags
= 0;
1774 cc_status
.value1
= XEXP (exp
, 0);
1775 cc_status
.value2
= XEXP (exp
, 1);
1778 else if (GET_CODE (exp
) == PARALLEL
1779 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1781 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1783 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
1785 cc_status
.flags
= 0;
1786 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1787 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
1792 if (cc_status
.value2
!= 0
1793 && ADDRESS_REG_P (cc_status
.value2
)
1794 && GET_MODE (cc_status
.value2
) == QImode
)
1796 if (cc_status
.value2
!= 0
1797 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
1798 switch (GET_CODE (cc_status
.value2
))
1800 case PLUS
: case MINUS
: case MULT
:
1801 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
1802 #if 0 /* These instructions always clear the overflow bit */
1803 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
1804 case ROTATE
: case ROTATERT
:
1806 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
1807 cc_status
.flags
|= CC_NO_OVERFLOW
;
1810 /* (SET r1 (ZERO_EXTEND r2)) on this machine
1811 ends with a move insn moving r2 in r2's mode.
1812 Thus, the cc's are set for r2.
1813 This can set N bit spuriously. */
1814 cc_status
.flags
|= CC_NOT_NEGATIVE
;
1816 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1818 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1819 cc_status
.value2
= 0;
1820 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
1821 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
1822 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1823 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
1824 cc_status
.flags
= CC_IN_68881
;
1828 output_move_const_double (operands
)
1831 #ifdef SUPPORT_SUN_FPA
1832 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
1834 int code
= standard_sun_fpa_constant_p (operands
[1]);
1838 static char buf
[40];
1840 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
1843 return "fpmove%.d %1,%0";
1848 int code
= standard_68881_constant_p (operands
[1]);
1852 static char buf
[40];
1854 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1857 return "fmove%.d %1,%0";
1862 output_move_const_single (operands
)
1865 #ifdef SUPPORT_SUN_FPA
1868 int code
= standard_sun_fpa_constant_p (operands
[1]);
1872 static char buf
[40];
1874 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
1877 return "fpmove%.s %1,%0";
1880 #endif /* defined SUPPORT_SUN_FPA */
1882 int code
= standard_68881_constant_p (operands
[1]);
1886 static char buf
[40];
1888 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
1891 return "fmove%.s %f1,%0";
1895 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
1896 from the "fmovecr" instruction.
1897 The value, anded with 0xff, gives the code to use in fmovecr
1898 to get the desired constant. */
1900 /* This code has been fixed for cross-compilation. */
1902 static int inited_68881_table
= 0;
1904 char *strings_68881
[7] = {
1914 int codes_68881
[7] = {
1924 REAL_VALUE_TYPE values_68881
[7];
1926 /* Set up values_68881 array by converting the decimal values
1927 strings_68881 to binary. */
1934 enum machine_mode mode
;
1937 for (i
= 0; i
< 7; i
++)
1941 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
1942 values_68881
[i
] = r
;
1944 inited_68881_table
= 1;
1948 standard_68881_constant_p (x
)
1953 enum machine_mode mode
;
1955 #ifdef NO_ASM_FMOVECR
1959 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
1963 #ifndef REAL_ARITHMETIC
1964 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1965 if (! flag_pretend_float
)
1970 if (! inited_68881_table
)
1971 init_68881_table ();
1973 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
1975 for (i
= 0; i
< 6; i
++)
1977 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
1978 return (codes_68881
[i
]);
1981 if (GET_MODE (x
) == SFmode
)
1984 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
1985 return (codes_68881
[6]);
1987 /* larger powers of ten in the constants ram are not used
1988 because they are not equal to a `double' C constant. */
1992 /* If X is a floating-point constant, return the logarithm of X base 2,
1993 or 0 if X is not a power of 2. */
1996 floating_exact_log2 (x
)
1999 REAL_VALUE_TYPE r
, r1
;
2002 #ifndef REAL_ARITHMETIC
2003 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2004 if (! flag_pretend_float
)
2009 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2011 if (REAL_VALUES_LESS (r
, dconst0
))
2016 while (REAL_VALUES_LESS (r1
, r
))
2018 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2019 if (REAL_VALUES_EQUAL (r1
, r
))
2026 #ifdef SUPPORT_SUN_FPA
2027 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2028 from the Sun FPA's constant RAM.
2029 The value returned, anded with 0x1ff, gives the code to use in fpmove
2030 to get the desired constant. */
2032 static int inited_FPA_table
= 0;
2034 char *strings_FPA
[38] = {
2035 /* small rationals */
2048 /* Decimal equivalents of double precision values */
2049 "2.718281828459045091", /* D_E */
2050 "6.283185307179586477", /* 2 pi */
2051 "3.141592653589793116", /* D_PI */
2052 "1.570796326794896619", /* pi/2 */
2053 "1.414213562373095145", /* D_SQRT2 */
2054 "0.7071067811865475244", /* 1/sqrt(2) */
2055 "-1.570796326794896619", /* -pi/2 */
2056 "1.442695040888963387", /* D_LOG2ofE */
2057 "3.321928024887362182", /* D_LOG2of10 */
2058 "0.6931471805599452862", /* D_LOGEof2 */
2059 "2.302585092994045901", /* D_LOGEof10 */
2060 "0.3010299956639811980", /* D_LOG10of2 */
2061 "0.4342944819032518167", /* D_LOG10ofE */
2062 /* Decimal equivalents of single precision values */
2063 "2.718281745910644531", /* S_E */
2064 "6.283185307179586477", /* 2 pi */
2065 "3.141592741012573242", /* S_PI */
2066 "1.570796326794896619", /* pi/2 */
2067 "1.414213538169860840", /* S_SQRT2 */
2068 "0.7071067811865475244", /* 1/sqrt(2) */
2069 "-1.570796326794896619", /* -pi/2 */
2070 "1.442695021629333496", /* S_LOG2ofE */
2071 "3.321928024291992188", /* S_LOG2of10 */
2072 "0.6931471824645996094", /* S_LOGEof2 */
2073 "2.302585124969482442", /* S_LOGEof10 */
2074 "0.3010300099849700928", /* S_LOG10of2 */
2075 "0.4342944920063018799", /* S_LOG10ofE */
2079 int codes_FPA
[38] = {
2080 /* small rationals */
2093 /* double precision */
2107 /* single precision */
2123 REAL_VALUE_TYPE values_FPA
[38];
2125 /* This code has been fixed for cross-compilation. */
2130 enum machine_mode mode
;
2135 for (i
= 0; i
< 38; i
++)
2139 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2142 inited_FPA_table
= 1;
2147 standard_sun_fpa_constant_p (x
)
2153 #ifndef REAL_ARITHMETIC
2154 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2155 if (! flag_pretend_float
)
2160 if (! inited_FPA_table
)
2163 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2165 for (i
=0; i
<12; i
++)
2167 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2168 return (codes_FPA
[i
]);
2171 if (GET_MODE (x
) == SFmode
)
2173 for (i
=25; i
<38; i
++)
2175 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2176 return (codes_FPA
[i
]);
2181 for (i
=12; i
<25; i
++)
2183 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2184 return (codes_FPA
[i
]);
2189 #endif /* define SUPPORT_SUN_FPA */
2191 /* A C compound statement to output to stdio stream STREAM the
2192 assembler syntax for an instruction operand X. X is an RTL
2195 CODE is a value that can be used to specify one of several ways
2196 of printing the operand. It is used when identical operands
2197 must be printed differently depending on the context. CODE
2198 comes from the `%' specification that was used to request
2199 printing of the operand. If the specification was just `%DIGIT'
2200 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2201 is the ASCII code for LTR.
2203 If X is a register, this macro should print the register's name.
2204 The names can be found in an array `reg_names' whose type is
2205 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2207 When the machine description has a specification `%PUNCT' (a `%'
2208 followed by a punctuation character), this macro is called with
2209 a null pointer for X and the punctuation character for CODE.
2211 The m68k specific codes are:
2213 '.' for dot needed in Motorola-style opcode names.
2214 '-' for an operand pushing on the stack:
2215 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2216 '+' for an operand pushing on the stack:
2217 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2218 '@' for a reference to the top word on the stack:
2219 sp@, (sp) or (%sp) depending on the style of syntax.
2220 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2221 but & in SGS syntax).
2222 '!' for the cc register (used in an `and to cc' insn).
2223 '$' for the letter `s' in an op code, but only on the 68040.
2224 '&' for the letter `d' in an op code, but only on the 68040.
2225 '/' for register prefix needed by longlong.h.
2227 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2228 'd' to force memory addressing to be absolute, not relative.
2229 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2230 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2231 than directly). Second part of 'y' below.
2232 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2233 or print pair of registers as rx:ry.
2234 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2235 CONST_DOUBLE's as SunFPA constant RAM registers if
2236 possible, so it should not be used except for the SunFPA.
2241 print_operand (file
, op
, letter
)
2242 FILE *file
; /* file to write to */
2243 rtx op
; /* operand to print */
2244 int letter
; /* %<letter> or 0 */
2251 asm_fprintf (file
, ".");
2254 else if (letter
== '#')
2256 asm_fprintf (file
, "%0I");
2258 else if (letter
== '-')
2261 asm_fprintf (file
, "-(%Rsp)");
2263 asm_fprintf (file
, "%Rsp@-");
2266 else if (letter
== '+')
2269 asm_fprintf (file
, "(%Rsp)+");
2271 asm_fprintf (file
, "%Rsp@+");
2274 else if (letter
== '@')
2277 asm_fprintf (file
, "(%Rsp)");
2279 asm_fprintf (file
, "%Rsp@");
2282 else if (letter
== '!')
2284 asm_fprintf (file
, "%Rfpcr");
2286 else if (letter
== '$')
2288 if (TARGET_68040_ONLY
)
2290 fprintf (file
, "s");
2293 else if (letter
== '&')
2295 if (TARGET_68040_ONLY
)
2297 fprintf (file
, "d");
2300 else if (letter
== '/')
2302 asm_fprintf (file
, "%R");
2304 else if (GET_CODE (op
) == REG
)
2306 #ifdef SUPPORT_SUN_FPA
2308 && (letter
== 'y' || letter
== 'x')
2309 && GET_MODE (op
) == DFmode
)
2311 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2312 reg_names
[REGNO (op
)+1]);
2318 /* Print out the second register name of a register pair.
2319 I.e., R (6) => 7. */
2320 fputs (reg_names
[REGNO (op
) + 1], file
);
2322 fputs (reg_names
[REGNO (op
)], file
);
2325 else if (GET_CODE (op
) == MEM
)
2327 output_address (XEXP (op
, 0));
2328 if (letter
== 'd' && ! TARGET_68020
2329 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2330 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2331 && INTVAL (XEXP (op
, 0)) < 0x8000
2332 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2335 fprintf (file
, ".l");
2337 fprintf (file
, ":l");
2341 #ifdef SUPPORT_SUN_FPA
2342 else if ((letter
== 'y' || letter
== 'w')
2343 && GET_CODE (op
) == CONST_DOUBLE
2344 && (i
= standard_sun_fpa_constant_p (op
)))
2346 fprintf (file
, "%%%d", i
& 0x1ff);
2349 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2352 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2353 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2355 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2358 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2359 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2361 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2364 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2365 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2369 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2374 /* A C compound statement to output to stdio stream STREAM the
2375 assembler syntax for an instruction operand that is a memory
2376 reference whose address is ADDR. ADDR is an RTL expression.
2378 Note that this contains a kludge that knows that the only reason
2379 we have an address (plus (label_ref...) (reg...)) when not generating
2380 PIC code is in the insn before a tablejump, and we know that m68k.md
2381 generates a label LInnn: on such an insn.
2383 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2384 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2386 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2387 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2388 we want. This difference can be accommodated by using an assembler
2389 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2390 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2391 macro. See m68k/sgs.h for an example; for versions without the bug.
2392 Some assemblers refuse all the above solutions. The workaround is to
2393 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2396 They also do not like things like "pea 1.w", so we simple leave off
2397 the .w on small constants.
2399 This routine is responsible for distinguishing between -fpic and -fPIC
2400 style relocations in an address. When generating -fpic code the
2401 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2402 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2404 #ifndef ASM_OUTPUT_CASE_FETCH
2407 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2408 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2410 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2411 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2414 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2415 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2417 #endif /* ASM_OUTPUT_CASE_FETCH */
2420 print_operand_address (file
, addr
)
2424 register rtx reg1
, reg2
, breg
, ireg
;
2427 switch (GET_CODE (addr
))
2431 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2433 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2438 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2440 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2445 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2447 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2451 reg1
= reg2
= ireg
= breg
= offset
= 0;
2452 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2454 offset
= XEXP (addr
, 0);
2455 addr
= XEXP (addr
, 1);
2457 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2459 offset
= XEXP (addr
, 1);
2460 addr
= XEXP (addr
, 0);
2462 if (GET_CODE (addr
) != PLUS
)
2466 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2468 reg1
= XEXP (addr
, 0);
2469 addr
= XEXP (addr
, 1);
2471 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2473 reg1
= XEXP (addr
, 1);
2474 addr
= XEXP (addr
, 0);
2476 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2478 reg1
= XEXP (addr
, 0);
2479 addr
= XEXP (addr
, 1);
2481 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2483 reg1
= XEXP (addr
, 1);
2484 addr
= XEXP (addr
, 0);
2486 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2488 reg1
= XEXP (addr
, 0);
2489 addr
= XEXP (addr
, 1);
2491 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2493 reg1
= XEXP (addr
, 1);
2494 addr
= XEXP (addr
, 0);
2496 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2497 || GET_CODE (addr
) == SIGN_EXTEND
)
2509 #if 0 /* for OLD_INDEXING */
2510 else if (GET_CODE (addr
) == PLUS
)
2512 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2514 reg2
= XEXP (addr
, 0);
2515 addr
= XEXP (addr
, 1);
2517 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2519 reg2
= XEXP (addr
, 1);
2520 addr
= XEXP (addr
, 0);
2532 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2533 || GET_CODE (reg1
) == MULT
))
2534 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2539 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2544 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2545 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2548 if (GET_CODE (ireg
) == MULT
)
2550 scale
= INTVAL (XEXP (ireg
, 1));
2551 ireg
= XEXP (ireg
, 0);
2553 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2555 ASM_OUTPUT_CASE_FETCH (file
,
2556 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2557 reg_names
[REGNO (XEXP (ireg
, 0))]);
2558 fprintf (file
, "w");
2562 ASM_OUTPUT_CASE_FETCH (file
,
2563 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2564 reg_names
[REGNO (ireg
)]);
2565 fprintf (file
, "l");
2570 fprintf (file
, "*%d", scale
);
2572 fprintf (file
, ":%d", scale
);
2578 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2579 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2581 ASM_OUTPUT_CASE_FETCH (file
,
2582 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2583 reg_names
[REGNO (breg
)]);
2584 fprintf (file
, "l)");
2587 if (ireg
!= 0 || breg
!= 0)
2594 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2601 output_addr_const (file
, addr
);
2602 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2603 fprintf (file
, "@GOT");
2605 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2611 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2614 output_addr_const (file
, addr
);
2615 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2616 fprintf (file
, ":w");
2617 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2618 fprintf (file
, ":l");
2620 if (addr
!= 0 && ireg
!= 0)
2625 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2627 scale
= INTVAL (XEXP (ireg
, 1));
2628 ireg
= XEXP (ireg
, 0);
2630 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2633 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2635 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2641 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2643 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2649 fprintf (file
, "*%d", scale
);
2651 fprintf (file
, ":%d", scale
);
2657 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2658 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2660 ASM_OUTPUT_CASE_FETCH (file
,
2661 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2662 reg_names
[REGNO (reg1
)]);
2663 fprintf (file
, "l)");
2666 /* FALL-THROUGH (is this really what we want? */
2668 if (GET_CODE (addr
) == CONST_INT
2669 && INTVAL (addr
) < 0x8000
2670 && INTVAL (addr
) >= -0x8000)
2674 /* Many SGS assemblers croak on size specifiers for constants. */
2675 fprintf (file
, "%d", INTVAL (addr
));
2677 fprintf (file
, "%d.w", INTVAL (addr
));
2680 fprintf (file
, "%d:w", INTVAL (addr
));
2685 output_addr_const (file
, addr
);
2691 /* Check for cases where a clr insns can be omitted from code using
2692 strict_low_part sets. For example, the second clrl here is not needed:
2693 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2695 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2696 insn we are checking for redundancy. TARGET is the register set by the
2700 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2701 enum machine_mode mode
;
2707 p
= prev_nonnote_insn (first_insn
);
2711 /* If it isn't an insn, then give up. */
2712 if (GET_CODE (p
) != INSN
)
2715 if (reg_set_p (target
, p
))
2717 rtx set
= single_set (p
);
2720 /* If it isn't an easy to recognize insn, then give up. */
2724 dest
= SET_DEST (set
);
2726 /* If this sets the entire target register to zero, then our
2727 first_insn is redundant. */
2728 if (rtx_equal_p (dest
, target
)
2729 && SET_SRC (set
) == const0_rtx
)
2731 else if (GET_CODE (dest
) == STRICT_LOW_PART
2732 && GET_CODE (XEXP (dest
, 0)) == REG
2733 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2734 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2735 <= GET_MODE_SIZE (mode
)))
2736 /* This is a strict low part set which modifies less than
2737 we are using, so it is safe. */
2743 p
= prev_nonnote_insn (p
);
2750 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2751 range carefully since this predicate is used in DImode contexts. Also, we
2752 need some extra crud to make it work when hosted on 64-bit machines. */
2755 const_uint32_operand (op
, mode
)
2757 enum machine_mode mode
;
2759 #if HOST_BITS_PER_WIDE_INT > 32
2760 /* All allowed constants will fit a CONST_INT. */
2761 return (GET_CODE (op
) == CONST_INT
2762 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
2764 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
2765 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
2769 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
2770 to check the range carefully since this predicate is used in DImode
2774 const_sint32_operand (op
, mode
)
2776 enum machine_mode mode
;
2778 /* All allowed constants will fit a CONST_INT. */
2779 return (GET_CODE (op
) == CONST_INT
2780 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));