1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
35 /* Needed for use_return_insn. */
38 #ifdef SUPPORT_SUN_FPA
40 /* Index into this array by (register number >> 3) to find the
41 smallest class which contains that register. */
42 enum reg_class regno_reg_class
[]
43 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
44 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
46 #endif /* defined SUPPORT_SUN_FPA */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx
find_addr_reg ();
53 rtx
legitimize_pic_address ();
56 /* Alignment to use for loops and jumps */
57 /* Specify power of two alignment used for loops. */
58 char *m68k_align_loops_string
;
59 /* Specify power of two alignment used for non-loop jumps. */
60 char *m68k_align_jumps_string
;
61 /* Specify power of two alignment used for functions. */
62 char *m68k_align_funcs_string
;
64 /* Specify power of two alignment used for loops. */
66 /* Specify power of two alignment used for non-loop jumps. */
68 /* Specify power of two alignment used for functions. */
71 /* Nonzero if the last compare/test insn had FP operands. The
72 sCC expanders peek at this to determine what to do for the
73 68060, which has no fsCC instructions. */
74 int m68k_last_compare_had_fp_operands
;
76 /* Sometimes certain combinations of command options do not make
77 sense on a particular target machine. You can define a macro
78 `OVERRIDE_OPTIONS' to take account of this. This macro, if
79 defined, is executed once just after all the command options have
82 Don't use this macro to turn on various extra optimizations for
83 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
92 /* Validate -malign-loops= value, or provide default */
93 if (m68k_align_loops_string
)
95 m68k_align_loops
= atoi (m68k_align_loops_string
);
96 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
97 fatal ("-malign-loops=%d is not between 1 and %d",
98 m68k_align_loops
, MAX_CODE_ALIGN
);
101 m68k_align_loops
= def_align
;
103 /* Validate -malign-jumps= value, or provide default */
104 if (m68k_align_jumps_string
)
106 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
107 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
108 fatal ("-malign-jumps=%d is not between 1 and %d",
109 m68k_align_jumps
, MAX_CODE_ALIGN
);
112 m68k_align_jumps
= def_align
;
114 /* Validate -malign-functions= value, or provide default */
115 if (m68k_align_funcs_string
)
117 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
118 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
119 fatal ("-malign-functions=%d is not between 1 and %d",
120 m68k_align_funcs
, MAX_CODE_ALIGN
);
123 m68k_align_funcs
= def_align
;
126 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
127 function at any time during the compilation process. In the future
128 we should try and eliminate the USE if we can easily determine that
129 all PIC references were deleted from the current function. That would
130 save an address register */
135 if (flag_pic
&& current_function_uses_pic_offset_table
)
137 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
138 emit_insn_after (insn
, get_insns ());
144 /* This function generates the assembly code for function entry.
145 STREAM is a stdio stream to output the code to.
146 SIZE is an int: how many units of temporary storage to allocate.
147 Refer to the array `regs_ever_live' to determine which registers
148 to save; `regs_ever_live[I]' is nonzero if register number I
149 is ever used in the function. This function is responsible for
150 knowing which registers should not be saved even if used. */
153 /* Note that the order of the bit mask for fmovem is the opposite
154 of the order for movem! */
158 output_function_prologue (stream
, size
)
163 register int mask
= 0;
164 int num_saved_regs
= 0;
165 extern char call_used_regs
[];
166 int fsize
= (size
+ 3) & -4;
169 if (frame_pointer_needed
)
171 if (fsize
== 0 && TARGET_68040
)
173 /* on the 68040, pea + move is faster than link.w 0 */
175 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
176 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
177 reg_names
[FRAME_POINTER_REGNUM
]);
179 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
180 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
181 reg_names
[FRAME_POINTER_REGNUM
]);
184 else if (fsize
< 0x8000)
187 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
188 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
190 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
191 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
194 else if (TARGET_68020
)
197 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
198 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
200 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
201 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
206 /* Adding negative number is faster on the 68040. */
208 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
209 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
211 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
212 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
218 if (fsize
+ 4 < 0x8000)
225 /* asm_fprintf() cannot handle %. */
227 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
229 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
234 /* asm_fprintf() cannot handle %. */
236 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
238 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
242 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
244 /* On the CPU32 it is faster to use two subqw instructions to
245 subtract a small integer (8 < N <= 16) to a register. */
246 /* asm_fprintf() cannot handle %. */
248 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
251 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
256 #endif /* NO_ADDSUB_Q */
259 /* Adding negative number is faster on the 68040. */
260 /* asm_fprintf() cannot handle %. */
262 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
264 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
270 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
272 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
278 /* asm_fprintf() cannot handle %. */
280 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
282 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
286 #ifdef SUPPORT_SUN_FPA
287 for (regno
= 24; regno
< 56; regno
++)
288 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
291 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
294 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
301 for (regno
= 16; regno
< 24; regno
++)
302 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
303 mask
|= 1 << (regno
- 16);
304 if ((mask
& 0xff) != 0)
307 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
309 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
314 for (regno
= 0; regno
< 16; regno
++)
315 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
317 mask
|= 1 << (15 - regno
);
320 if (frame_pointer_needed
)
322 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
329 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
331 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
334 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
338 if (num_saved_regs
<= 2)
340 /* Store each separately in the same order moveml uses.
341 Using two movel instructions instead of a single moveml
342 is about 15% faster for the 68020 and 68030 at no expense
347 /* Undo the work from above. */
348 for (i
= 0; i
< 16; i
++)
352 "\t%Omove.l %s,-(%Rsp)\n",
354 "\tmovel %s,%Rsp@-\n",
362 /* The coldfire does not support the predecrement form of the
363 movml instruction, so we must adjust the stack pointer and
364 then use the plain address register indirect mode. We also
365 have to invert the register save mask to use the new mode.
367 FIXME: if num_saved_regs was calculated earlier, we could
368 combine the stack pointer adjustment with any adjustment
369 done when the initial stack frame is created. This would
370 save an instruction */
375 for (i
= 0; i
< 16; i
++)
377 newmask
|= (1 << (15-i
));
380 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
381 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
383 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
384 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
390 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
392 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
396 if (flag_pic
&& current_function_uses_pic_offset_table
)
399 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
400 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
402 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
403 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
404 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
405 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
406 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
411 /* Return true if this function's epilogue can be output as RTL. */
418 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
421 /* Copied from output_function_epilogue (). We should probably create a
422 separate layout routine to perform the common work. */
424 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
425 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
431 /* This function generates the assembly code for function exit,
432 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
434 The function epilogue should not depend on the current stack pointer!
435 It should use the frame pointer only, if there is a frame pointer.
436 This is mandatory because of alloca; we also take advantage of it to
437 omit stack adjustments before returning. */
440 output_function_epilogue (stream
, size
)
445 register int mask
, fmask
;
447 int offset
, foffset
, fpoffset
;
448 extern char call_used_regs
[];
449 int fsize
= (size
+ 3) & -4;
451 rtx insn
= get_last_insn ();
452 int restore_from_sp
= 0;
454 /* If the last insn was a BARRIER, we don't have to write any code. */
455 if (GET_CODE (insn
) == NOTE
)
456 insn
= prev_nonnote_insn (insn
);
457 if (insn
&& GET_CODE (insn
) == BARRIER
)
459 /* Output just a no-op so that debuggers don't get confused
460 about which function the pc is in at this address. */
461 asm_fprintf (stream
, "\tnop\n");
465 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
466 if (profile_block_flag
== 2)
468 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
472 #ifdef FUNCTION_EXTRA_EPILOGUE
473 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
475 nregs
= 0; fmask
= 0; fpoffset
= 0;
476 #ifdef SUPPORT_SUN_FPA
477 for (regno
= 24 ; regno
< 56 ; regno
++)
478 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
480 fpoffset
= nregs
* 8;
485 for (regno
= 16; regno
< 24; regno
++)
486 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
489 fmask
|= 1 << (23 - regno
);
492 foffset
= fpoffset
+ nregs
* 12;
494 if (frame_pointer_needed
)
495 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
496 for (regno
= 0; regno
< 16; regno
++)
497 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
502 offset
= foffset
+ nregs
* 4;
503 /* FIXME : leaf_function_p below is too strong.
504 What we really need to know there is if there could be pending
505 stack adjustment needed at that point. */
506 restore_from_sp
= ! frame_pointer_needed
507 || (! current_function_calls_alloca
&& leaf_function_p ());
508 if (offset
+ fsize
>= 0x8000
510 && (mask
|| fmask
|| fpoffset
))
513 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
515 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
519 if (TARGET_5200
|| nregs
<= 2)
521 /* Restore each separately in the same order moveml does.
522 Using two movel instructions instead of a single moveml
523 is about 15% faster for the 68020 and 68030 at no expense
528 /* Undo the work from above. */
529 for (i
= 0; i
< 16; i
++)
535 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
537 reg_names
[FRAME_POINTER_REGNUM
],
540 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
541 reg_names
[FRAME_POINTER_REGNUM
],
542 offset
+ fsize
, reg_names
[i
]);
545 else if (restore_from_sp
)
548 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
551 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
558 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
560 reg_names
[FRAME_POINTER_REGNUM
],
563 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
564 reg_names
[FRAME_POINTER_REGNUM
],
565 offset
+ fsize
, reg_names
[i
]);
576 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
578 reg_names
[FRAME_POINTER_REGNUM
],
581 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
582 reg_names
[FRAME_POINTER_REGNUM
],
583 offset
+ fsize
, mask
);
586 else if (restore_from_sp
)
589 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
591 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
597 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
599 reg_names
[FRAME_POINTER_REGNUM
],
602 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
603 reg_names
[FRAME_POINTER_REGNUM
],
604 offset
+ fsize
, mask
);
613 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
615 reg_names
[FRAME_POINTER_REGNUM
],
618 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
619 reg_names
[FRAME_POINTER_REGNUM
],
620 foffset
+ fsize
, fmask
);
623 else if (restore_from_sp
)
626 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
628 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
634 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
636 reg_names
[FRAME_POINTER_REGNUM
],
639 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
640 reg_names
[FRAME_POINTER_REGNUM
],
641 foffset
+ fsize
, fmask
);
646 for (regno
= 55; regno
>= 24; regno
--)
647 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
652 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
654 reg_names
[FRAME_POINTER_REGNUM
],
657 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
658 reg_names
[FRAME_POINTER_REGNUM
],
659 fpoffset
+ fsize
, reg_names
[regno
]);
662 else if (restore_from_sp
)
665 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
668 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
675 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
677 reg_names
[FRAME_POINTER_REGNUM
],
680 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
681 reg_names
[FRAME_POINTER_REGNUM
],
682 fpoffset
+ fsize
, reg_names
[regno
]);
687 if (frame_pointer_needed
)
688 fprintf (stream
, "\tunlk %s\n",
689 reg_names
[FRAME_POINTER_REGNUM
]);
698 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
700 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
706 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
708 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
712 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
714 /* On the CPU32 it is faster to use two addqw instructions to
715 add a small integer (8 < N <= 16) to a register. */
716 /* asm_fprintf() cannot handle %. */
718 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
721 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
726 #endif /* NO_ADDSUB_Q */
727 if (fsize
+ 4 < 0x8000)
731 /* asm_fprintf() cannot handle %. */
733 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
735 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
741 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
743 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
749 /* asm_fprintf() cannot handle %. */
751 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
753 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
757 if (current_function_pops_args
)
758 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
760 fprintf (stream
, "\trts\n");
763 /* Similar to general_operand, but exclude stack_pointer_rtx. */
766 not_sp_operand (op
, mode
)
768 enum machine_mode mode
;
770 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
773 /* Return TRUE if X is a valid comparison operator for the dbcc
776 Note it rejects floating point comparison operators.
777 (In the future we could use Fdbcc).
779 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
782 valid_dbcc_comparison_p (x
, mode
)
784 enum machine_mode mode
;
786 switch (GET_CODE (x
))
788 case EQ
: case NE
: case GTU
: case LTU
:
792 /* Reject some when CC_NO_OVERFLOW is set. This may be over
794 case GT
: case LT
: case GE
: case LE
:
795 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
801 /* Return non-zero if flags are currently in the 68881 flag register. */
805 /* We could add support for these in the future */
806 return cc_status
.flags
& CC_IN_68881
;
809 /* Output a dbCC; jCC sequence. Note we do not handle the
810 floating point version of this sequence (Fdbcc). We also
811 do not handle alternative conditions when CC_NO_OVERFLOW is
812 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
813 kick those out before we get here. */
815 output_dbcc_and_branch (operands
)
818 switch (GET_CODE (operands
[3]))
822 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
824 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
830 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
832 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
838 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
840 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
846 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
848 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
854 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
856 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
862 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
864 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
870 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
872 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
878 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
880 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
886 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
888 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
894 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
896 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
904 /* If the decrement is to be done in SImode, then we have
905 to compensate for the fact that dbcc decrements in HImode. */
906 switch (GET_MODE (operands
[0]))
910 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
912 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
925 output_scc_di(op
, operand1
, operand2
, dest
)
932 enum rtx_code op_code
= GET_CODE (op
);
934 /* This does not produce a usefull cc. */
937 /* The m68k cmp.l instruction requires operand1 to be a reg as used
938 below. Swap the operands and change the op if these requirements
939 are not fulfilled. */
940 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
946 op_code
= swap_condition (op_code
);
948 loperands
[0] = operand1
;
949 if (GET_CODE (operand1
) == REG
)
950 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
952 loperands
[1] = adj_offsettable_operand (operand1
, 4);
953 if (operand2
!= const0_rtx
)
955 loperands
[2] = operand2
;
956 if (GET_CODE (operand2
) == REG
)
957 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
959 loperands
[3] = adj_offsettable_operand (operand2
, 4);
961 loperands
[4] = gen_label_rtx();
962 if (operand2
!= const0_rtx
)
965 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
967 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
971 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
973 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
978 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
980 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
987 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
988 CODE_LABEL_NUMBER (loperands
[4]));
989 output_asm_insn ("seq %5", loperands
);
993 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
994 CODE_LABEL_NUMBER (loperands
[4]));
995 output_asm_insn ("sne %5", loperands
);
999 loperands
[6] = gen_label_rtx();
1001 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1003 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1005 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1006 CODE_LABEL_NUMBER (loperands
[4]));
1007 output_asm_insn ("sgt %5", loperands
);
1008 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1009 CODE_LABEL_NUMBER (loperands
[6]));
1013 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1014 CODE_LABEL_NUMBER (loperands
[4]));
1015 output_asm_insn ("shi %5", loperands
);
1019 loperands
[6] = gen_label_rtx();
1021 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1023 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1025 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1026 CODE_LABEL_NUMBER (loperands
[4]));
1027 output_asm_insn ("slt %5", loperands
);
1028 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1029 CODE_LABEL_NUMBER (loperands
[6]));
1033 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1034 CODE_LABEL_NUMBER (loperands
[4]));
1035 output_asm_insn ("scs %5", loperands
);
1039 loperands
[6] = gen_label_rtx();
1041 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1043 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1045 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1046 CODE_LABEL_NUMBER (loperands
[4]));
1047 output_asm_insn ("sge %5", loperands
);
1048 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1049 CODE_LABEL_NUMBER (loperands
[6]));
1053 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1054 CODE_LABEL_NUMBER (loperands
[4]));
1055 output_asm_insn ("scc %5", loperands
);
1059 loperands
[6] = gen_label_rtx();
1061 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1063 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1065 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1066 CODE_LABEL_NUMBER (loperands
[4]));
1067 output_asm_insn ("sle %5", loperands
);
1068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1069 CODE_LABEL_NUMBER (loperands
[6]));
1073 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1074 CODE_LABEL_NUMBER (loperands
[4]));
1075 output_asm_insn ("sls %5", loperands
);
1085 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1087 rtx countop
, dataop
;
1091 operands
[0] = countop
;
1092 operands
[1] = dataop
;
1094 if (GET_CODE (countop
) == CONST_INT
)
1096 register int count
= INTVAL (countop
);
1097 /* If COUNT is bigger than size of storage unit in use,
1098 advance to the containing unit of same size. */
1099 if (count
> signpos
)
1101 int offset
= (count
& ~signpos
) / 8;
1102 count
= count
& signpos
;
1103 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1105 if (count
== signpos
)
1106 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1108 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1110 /* These three statements used to use next_insns_test_no...
1111 but it appears that this should do the same job. */
1113 && next_insn_tests_no_inequality (insn
))
1116 && next_insn_tests_no_inequality (insn
))
1119 && next_insn_tests_no_inequality (insn
))
1122 cc_status
.flags
= CC_NOT_NEGATIVE
;
1124 return "btst %0,%1";
1127 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1128 reference and a constant. */
1131 symbolic_operand (op
, mode
)
1133 enum machine_mode mode
;
1135 switch (GET_CODE (op
))
1143 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1144 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1145 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1147 #if 0 /* Deleted, with corresponding change in m68k.h,
1148 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1150 return GET_MODE (op
) == mode
;
1158 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1161 extend_operator(x
, mode
)
1163 enum machine_mode mode
;
1165 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1167 switch (GET_CODE(x
))
1178 /* Legitimize PIC addresses. If the address is already
1179 position-independent, we return ORIG. Newly generated
1180 position-independent addresses go to REG. If we need more
1181 than one register, we lose.
1183 An address is legitimized by making an indirect reference
1184 through the Global Offset Table with the name of the symbol
1187 The assembler and linker are responsible for placing the
1188 address of the symbol in the GOT. The function prologue
1189 is responsible for initializing a5 to the starting address
1192 The assembler is also responsible for translating a symbol name
1193 into a constant displacement from the start of the GOT.
1195 A quick example may make things a little clearer:
1197 When not generating PIC code to store the value 12345 into _foo
1198 we would generate the following code:
1202 When generating PIC two transformations are made. First, the compiler
1203 loads the address of foo into a register. So the first transformation makes:
1208 The code in movsi will intercept the lea instruction and call this
1209 routine which will transform the instructions into:
1211 movel a5@(_foo:w), a0
1215 That (in a nutshell) is how *all* symbol and label references are
1219 legitimize_pic_address (orig
, mode
, reg
)
1221 enum machine_mode mode
;
1225 /* First handle a simple SYMBOL_REF or LABEL_REF */
1226 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1231 pic_ref
= gen_rtx (MEM
, Pmode
,
1232 gen_rtx (PLUS
, Pmode
,
1233 pic_offset_table_rtx
, orig
));
1234 current_function_uses_pic_offset_table
= 1;
1235 RTX_UNCHANGING_P (pic_ref
) = 1;
1236 emit_move_insn (reg
, pic_ref
);
1239 else if (GET_CODE (orig
) == CONST
)
1243 /* Make sure this is CONST has not already been legitimized */
1244 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1245 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1251 /* legitimize both operands of the PLUS */
1252 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1254 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1255 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1256 base
== reg
? 0 : reg
);
1260 if (GET_CODE (orig
) == CONST_INT
)
1261 return plus_constant_for_output (base
, INTVAL (orig
));
1262 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1263 /* Likewise, should we set special REG_NOTEs here? */
1269 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1271 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1274 const_method (constant
)
1280 i
= INTVAL (constant
);
1284 /* The Coldfire doesn't have byte or word operations. */
1285 /* FIXME: This may not be useful for the m68060 either */
1288 /* if -256 < N < 256 but N is not in range for a moveq
1289 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1290 if (USE_MOVQ (i
^ 0xff))
1292 /* Likewise, try with not.w */
1293 if (USE_MOVQ (i
^ 0xffff))
1295 /* This is the only value where neg.w is useful */
1298 /* Try also with swap */
1300 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1303 /* Otherwise, use move.l */
1307 const_int_cost (constant
)
1310 switch (const_method (constant
))
1313 /* Constants between -128 and 127 are cheap due to moveq */
1319 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1329 output_move_const_into_data_reg (operands
)
1334 i
= INTVAL (operands
[1]);
1335 switch (const_method (operands
[1]))
1338 #if defined (MOTOROLA) && !defined (CRDS)
1339 return "moveq%.l %1,%0";
1341 return "moveq %1,%0";
1344 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1345 #if defined (MOTOROLA) && !defined (CRDS)
1346 return "moveq%.l %1,%0\n\tnot%.b %0";
1348 return "moveq %1,%0\n\tnot%.b %0";
1351 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1352 #if defined (MOTOROLA) && !defined (CRDS)
1353 return "moveq%.l %1,%0\n\tnot%.w %0";
1355 return "moveq %1,%0\n\tnot%.w %0";
1358 #if defined (MOTOROLA) && !defined (CRDS)
1359 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1361 return "moveq %#-128,%0\n\tneg%.w %0";
1367 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1368 #if defined (MOTOROLA) && !defined (CRDS)
1369 return "moveq%.l %1,%0\n\tswap %0";
1371 return "moveq %1,%0\n\tswap %0";
1375 return "move%.l %1,%0";
1382 output_move_simode_const (operands
)
1385 if (operands
[1] == const0_rtx
1386 && (DATA_REG_P (operands
[0])
1387 || GET_CODE (operands
[0]) == MEM
)
1388 /* clr insns on 68000 read before writing.
1389 This isn't so on the 68010, but we have no TARGET_68010. */
1390 && ((TARGET_68020
|| TARGET_5200
)
1391 || !(GET_CODE (operands
[0]) == MEM
1392 && MEM_VOLATILE_P (operands
[0]))))
1394 else if (DATA_REG_P (operands
[0]))
1395 return output_move_const_into_data_reg (operands
);
1396 else if (ADDRESS_REG_P (operands
[0])
1397 && INTVAL (operands
[1]) < 0x8000
1398 && INTVAL (operands
[1]) >= -0x8000)
1399 return "move%.w %1,%0";
1400 else if (GET_CODE (operands
[0]) == MEM
1401 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1402 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1403 && INTVAL (operands
[1]) < 0x8000
1404 && INTVAL (operands
[1]) >= -0x8000)
1406 return "move%.l %1,%0";
1410 output_move_simode (operands
)
1413 if (GET_CODE (operands
[1]) == CONST_INT
)
1414 return output_move_simode_const (operands
);
1415 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1416 || GET_CODE (operands
[1]) == CONST
)
1417 && push_operand (operands
[0], SImode
))
1419 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1420 || GET_CODE (operands
[1]) == CONST
)
1421 && ADDRESS_REG_P (operands
[0]))
1422 return "lea %a1,%0";
1423 return "move%.l %1,%0";
1427 output_move_himode (operands
)
1430 if (GET_CODE (operands
[1]) == CONST_INT
)
1432 if (operands
[1] == const0_rtx
1433 && (DATA_REG_P (operands
[0])
1434 || GET_CODE (operands
[0]) == MEM
)
1435 /* clr insns on 68000 read before writing.
1436 This isn't so on the 68010, but we have no TARGET_68010. */
1437 && ((TARGET_68020
|| TARGET_5200
)
1438 || !(GET_CODE (operands
[0]) == MEM
1439 && MEM_VOLATILE_P (operands
[0]))))
1441 else if (DATA_REG_P (operands
[0])
1442 && INTVAL (operands
[1]) < 128
1443 && INTVAL (operands
[1]) >= -128)
1445 #if defined(MOTOROLA) && !defined(CRDS)
1446 return "moveq%.l %1,%0";
1448 return "moveq %1,%0";
1451 else if (INTVAL (operands
[1]) < 0x8000
1452 && INTVAL (operands
[1]) >= -0x8000)
1453 return "move%.w %1,%0";
1455 else if (CONSTANT_P (operands
[1]))
1456 return "move%.l %1,%0";
1458 /* Recognize the insn before a tablejump, one that refers
1459 to a table of offsets. Such an insn will need to refer
1460 to a label on the insn. So output one. Use the label-number
1461 of the table of offsets to generate this label. This code,
1462 and similar code below, assumes that there will be at most one
1463 reference to each table. */
1464 if (GET_CODE (operands
[1]) == MEM
1465 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1466 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1467 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1469 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1470 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1472 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1473 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1475 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1476 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1477 #endif /* not SGS */
1478 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1479 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1480 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1481 #ifdef SGS_SWITCH_TABLES
1482 /* Set flag saying we need to define the symbol
1483 LD%n (with value L%n-LI%n) at the end of the switch table. */
1484 switch_table_difference_label_flag
= 1;
1485 #endif /* SGS_SWITCH_TABLES */
1486 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1488 #endif /* SGS_NO_LI */
1489 return "move%.w %1,%0";
1493 output_move_qimode (operands
)
1498 /* This is probably useless, since it loses for pushing a struct
1499 of several bytes a byte at a time. */
1500 if (GET_CODE (operands
[0]) == MEM
1501 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1502 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1503 && ! ADDRESS_REG_P (operands
[1]))
1505 xoperands
[1] = operands
[1];
1507 = gen_rtx (MEM
, QImode
,
1508 gen_rtx (PLUS
, VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1509 /* Just pushing a byte puts it in the high byte of the halfword. */
1510 /* We must put it in the low-order, high-numbered byte. */
1511 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1515 /* clr and st insns on 68000 read before writing.
1516 This isn't so on the 68010, but we have no TARGET_68010. */
1517 if (!ADDRESS_REG_P (operands
[0])
1518 && ((TARGET_68020
|| TARGET_5200
)
1519 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1521 if (operands
[1] == const0_rtx
)
1523 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1524 && GET_CODE (operands
[1]) == CONST_INT
1525 && (INTVAL (operands
[1]) & 255) == 255)
1531 if (GET_CODE (operands
[1]) == CONST_INT
1532 && DATA_REG_P (operands
[0])
1533 && INTVAL (operands
[1]) < 128
1534 && INTVAL (operands
[1]) >= -128)
1536 #if defined(MOTOROLA) && !defined(CRDS)
1537 return "moveq%.l %1,%0";
1539 return "moveq %1,%0";
1542 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1543 return "move%.l %1,%0";
1544 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1545 return "move%.w %1,%0";
1546 return "move%.b %1,%0";
1549 /* Return the best assembler insn template
1550 for moving operands[1] into operands[0] as a fullword. */
1553 singlemove_string (operands
)
1556 #ifdef SUPPORT_SUN_FPA
1557 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1558 return "fpmoves %1,%0";
1560 if (GET_CODE (operands
[1]) == CONST_INT
)
1561 return output_move_simode_const (operands
);
1562 return "move%.l %1,%0";
1566 /* Output assembler code to perform a doubleword move insn
1567 with operands OPERANDS. */
1570 output_move_double (operands
)
1575 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1580 rtx addreg0
= 0, addreg1
= 0;
1581 int dest_overlapped_low
= 0;
1582 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1587 /* First classify both operands. */
1589 if (REG_P (operands
[0]))
1591 else if (offsettable_memref_p (operands
[0]))
1593 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1595 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1597 else if (GET_CODE (operands
[0]) == MEM
)
1602 if (REG_P (operands
[1]))
1604 else if (CONSTANT_P (operands
[1]))
1606 else if (offsettable_memref_p (operands
[1]))
1608 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1610 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1612 else if (GET_CODE (operands
[1]) == MEM
)
1617 /* Check for the cases that the operand constraints are not
1618 supposed to allow to happen. Abort if we get one,
1619 because generating code for these cases is painful. */
1621 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1624 /* If one operand is decrementing and one is incrementing
1625 decrement the former register explicitly
1626 and change that operand into ordinary indexing. */
1628 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1630 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1632 output_asm_insn ("sub%.l %#12,%0", operands
);
1634 output_asm_insn ("subq%.l %#8,%0", operands
);
1635 if (GET_MODE (operands
[1]) == XFmode
)
1636 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1637 else if (GET_MODE (operands
[0]) == DFmode
)
1638 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1640 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1643 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1645 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1647 output_asm_insn ("sub%.l %#12,%1", operands
);
1649 output_asm_insn ("subq%.l %#8,%1", operands
);
1650 if (GET_MODE (operands
[1]) == XFmode
)
1651 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1652 else if (GET_MODE (operands
[1]) == DFmode
)
1653 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1655 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1659 /* If an operand is an unoffsettable memory ref, find a register
1660 we can increment temporarily to make it refer to the second word. */
1662 if (optype0
== MEMOP
)
1663 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1665 if (optype1
== MEMOP
)
1666 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1668 /* Ok, we can do one word at a time.
1669 Normally we do the low-numbered word first,
1670 but if either operand is autodecrementing then we
1671 do the high-numbered word first.
1673 In either case, set up in LATEHALF the operands to use
1674 for the high-numbered word and in some cases alter the
1675 operands in OPERANDS to be suitable for the low-numbered word. */
1679 if (optype0
== REGOP
)
1681 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1682 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1684 else if (optype0
== OFFSOP
)
1686 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1687 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1691 middlehalf
[0] = operands
[0];
1692 latehalf
[0] = operands
[0];
1695 if (optype1
== REGOP
)
1697 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1698 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1700 else if (optype1
== OFFSOP
)
1702 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1703 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1705 else if (optype1
== CNSTOP
)
1707 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1712 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1713 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1714 operands
[1] = GEN_INT (l
[0]);
1715 middlehalf
[1] = GEN_INT (l
[1]);
1716 latehalf
[1] = GEN_INT (l
[2]);
1718 else if (CONSTANT_P (operands
[1]))
1720 /* actually, no non-CONST_DOUBLE constant should ever
1723 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1724 latehalf
[1] = constm1_rtx
;
1726 latehalf
[1] = const0_rtx
;
1731 middlehalf
[1] = operands
[1];
1732 latehalf
[1] = operands
[1];
1736 /* size is not 12: */
1738 if (optype0
== REGOP
)
1739 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1740 else if (optype0
== OFFSOP
)
1741 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1743 latehalf
[0] = operands
[0];
1745 if (optype1
== REGOP
)
1746 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1747 else if (optype1
== OFFSOP
)
1748 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1749 else if (optype1
== CNSTOP
)
1750 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1752 latehalf
[1] = operands
[1];
1755 /* If insn is effectively movd N(sp),-(sp) then we will do the
1756 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1757 for the low word as well, to compensate for the first decrement of sp. */
1758 if (optype0
== PUSHOP
1759 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1760 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1761 operands
[1] = middlehalf
[1] = latehalf
[1];
1763 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1764 if the upper part of reg N does not appear in the MEM, arrange to
1765 emit the move late-half first. Otherwise, compute the MEM address
1766 into the upper part of N and use that as a pointer to the memory
1768 if (optype0
== REGOP
1769 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1771 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1773 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1774 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1776 /* If both halves of dest are used in the src memory address,
1777 compute the address into latehalf of dest.
1778 Note that this can't happen if the dest is two data regs. */
1780 xops
[0] = latehalf
[0];
1781 xops
[1] = XEXP (operands
[1], 0);
1782 output_asm_insn ("lea %a1,%0", xops
);
1783 if( GET_MODE (operands
[1]) == XFmode
)
1785 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1786 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1787 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1791 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1792 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1796 && reg_overlap_mentioned_p (middlehalf
[0],
1797 XEXP (operands
[1], 0)))
1799 /* Check for two regs used by both source and dest.
1800 Note that this can't happen if the dest is all data regs.
1801 It can happen if the dest is d6, d7, a0.
1802 But in that case, latehalf is an addr reg, so
1803 the code at compadr does ok. */
1805 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1806 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1809 /* JRV says this can't happen: */
1810 if (addreg0
|| addreg1
)
1813 /* Only the middle reg conflicts; simply put it last. */
1814 output_asm_insn (singlemove_string (operands
), operands
);
1815 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1816 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1819 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1820 /* If the low half of dest is mentioned in the source memory
1821 address, the arrange to emit the move late half first. */
1822 dest_overlapped_low
= 1;
1825 /* If one or both operands autodecrementing,
1826 do the two words, high-numbered first. */
1828 /* Likewise, the first move would clobber the source of the second one,
1829 do them in the other order. This happens only for registers;
1830 such overlap can't happen in memory unless the user explicitly
1831 sets it up, and that is an undefined circumstance. */
1833 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1834 || (optype0
== REGOP
&& optype1
== REGOP
1835 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1836 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1837 || dest_overlapped_low
)
1839 /* Make any unoffsettable addresses point at high-numbered word. */
1843 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1845 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1850 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1852 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1856 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1858 /* Undo the adds we just did. */
1860 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1862 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1866 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1868 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1870 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1873 /* Do low-numbered word. */
1874 return singlemove_string (operands
);
1877 /* Normal case: do the two words, low-numbered first. */
1879 output_asm_insn (singlemove_string (operands
), operands
);
1881 /* Do the middle one of the three words for long double */
1885 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1887 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1889 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1892 /* Make any unoffsettable addresses point at high-numbered word. */
1894 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1896 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1899 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1901 /* Undo the adds we just did. */
1905 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
1907 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1912 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
1914 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1920 /* Return a REG that occurs in ADDR with coefficient 1.
1921 ADDR can be effectively incremented by incrementing REG. */
1924 find_addr_reg (addr
)
1927 while (GET_CODE (addr
) == PLUS
)
1929 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1930 addr
= XEXP (addr
, 0);
1931 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1932 addr
= XEXP (addr
, 1);
1933 else if (CONSTANT_P (XEXP (addr
, 0)))
1934 addr
= XEXP (addr
, 1);
1935 else if (CONSTANT_P (XEXP (addr
, 1)))
1936 addr
= XEXP (addr
, 0);
1940 if (GET_CODE (addr
) == REG
)
1945 /* Store in cc_status the expressions that the condition codes will
1946 describe after execution of an instruction whose pattern is EXP.
1947 Do not alter them if the instruction would not alter the cc's. */
1949 /* On the 68000, all the insns to store in an address register fail to
1950 set the cc's. However, in some cases these instructions can make it
1951 possibly invalid to use the saved cc's. In those cases we clear out
1952 some or all of the saved cc's so they won't be used. */
1954 notice_update_cc (exp
, insn
)
1958 /* If the cc is being set from the fpa and the expression is not an
1959 explicit floating point test instruction (which has code to deal with
1960 this), reinit the CC. */
1961 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
1962 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
1963 && !(GET_CODE (exp
) == PARALLEL
1964 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1965 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
1969 else if (GET_CODE (exp
) == SET
)
1971 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1975 else if (ADDRESS_REG_P (SET_DEST (exp
)))
1977 if (cc_status
.value1
1978 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
1979 cc_status
.value1
= 0;
1980 if (cc_status
.value2
1981 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
1982 cc_status
.value2
= 0;
1984 else if (!FP_REG_P (SET_DEST (exp
))
1985 && SET_DEST (exp
) != cc0_rtx
1986 && (FP_REG_P (SET_SRC (exp
))
1987 || GET_CODE (SET_SRC (exp
)) == FIX
1988 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
1989 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
1993 /* A pair of move insns doesn't produce a useful overall cc. */
1994 else if (!FP_REG_P (SET_DEST (exp
))
1995 && !FP_REG_P (SET_SRC (exp
))
1996 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
1997 && (GET_CODE (SET_SRC (exp
)) == REG
1998 || GET_CODE (SET_SRC (exp
)) == MEM
1999 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2003 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2007 else if (XEXP (exp
, 0) != pc_rtx
)
2009 cc_status
.flags
= 0;
2010 cc_status
.value1
= XEXP (exp
, 0);
2011 cc_status
.value2
= XEXP (exp
, 1);
2014 else if (GET_CODE (exp
) == PARALLEL
2015 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2017 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2019 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2021 cc_status
.flags
= 0;
2022 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2023 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2028 if (cc_status
.value2
!= 0
2029 && ADDRESS_REG_P (cc_status
.value2
)
2030 && GET_MODE (cc_status
.value2
) == QImode
)
2032 if (cc_status
.value2
!= 0
2033 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2034 switch (GET_CODE (cc_status
.value2
))
2036 case PLUS
: case MINUS
: case MULT
:
2037 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2038 #if 0 /* These instructions always clear the overflow bit */
2039 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2040 case ROTATE
: case ROTATERT
:
2042 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2043 cc_status
.flags
|= CC_NO_OVERFLOW
;
2046 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2047 ends with a move insn moving r2 in r2's mode.
2048 Thus, the cc's are set for r2.
2049 This can set N bit spuriously. */
2050 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2052 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2054 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2055 cc_status
.value2
= 0;
2056 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2057 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2058 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2059 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2060 cc_status
.flags
= CC_IN_68881
;
2064 output_move_const_double (operands
)
2067 #ifdef SUPPORT_SUN_FPA
2068 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2070 int code
= standard_sun_fpa_constant_p (operands
[1]);
2074 static char buf
[40];
2076 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2079 return "fpmove%.d %1,%0";
2084 int code
= standard_68881_constant_p (operands
[1]);
2088 static char buf
[40];
2090 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2093 return "fmove%.d %1,%0";
2098 output_move_const_single (operands
)
2101 #ifdef SUPPORT_SUN_FPA
2104 int code
= standard_sun_fpa_constant_p (operands
[1]);
2108 static char buf
[40];
2110 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2113 return "fpmove%.s %1,%0";
2116 #endif /* defined SUPPORT_SUN_FPA */
2118 int code
= standard_68881_constant_p (operands
[1]);
2122 static char buf
[40];
2124 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2127 return "fmove%.s %f1,%0";
2131 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2132 from the "fmovecr" instruction.
2133 The value, anded with 0xff, gives the code to use in fmovecr
2134 to get the desired constant. */
2136 /* This code has been fixed for cross-compilation. */
2138 static int inited_68881_table
= 0;
2140 char *strings_68881
[7] = {
2150 int codes_68881
[7] = {
2160 REAL_VALUE_TYPE values_68881
[7];
2162 /* Set up values_68881 array by converting the decimal values
2163 strings_68881 to binary. */
2170 enum machine_mode mode
;
2173 for (i
= 0; i
< 7; i
++)
2177 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2178 values_68881
[i
] = r
;
2180 inited_68881_table
= 1;
2184 standard_68881_constant_p (x
)
2189 enum machine_mode mode
;
2191 #ifdef NO_ASM_FMOVECR
2195 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2199 #ifndef REAL_ARITHMETIC
2200 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2201 if (! flag_pretend_float
)
2206 if (! inited_68881_table
)
2207 init_68881_table ();
2209 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2211 for (i
= 0; i
< 6; i
++)
2213 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2214 return (codes_68881
[i
]);
2217 if (GET_MODE (x
) == SFmode
)
2220 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2221 return (codes_68881
[6]);
2223 /* larger powers of ten in the constants ram are not used
2224 because they are not equal to a `double' C constant. */
2228 /* If X is a floating-point constant, return the logarithm of X base 2,
2229 or 0 if X is not a power of 2. */
2232 floating_exact_log2 (x
)
2235 REAL_VALUE_TYPE r
, r1
;
2238 #ifndef REAL_ARITHMETIC
2239 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2240 if (! flag_pretend_float
)
2245 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2247 if (REAL_VALUES_LESS (r
, dconst0
))
2252 while (REAL_VALUES_LESS (r1
, r
))
2254 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2255 if (REAL_VALUES_EQUAL (r1
, r
))
2262 #ifdef SUPPORT_SUN_FPA
2263 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2264 from the Sun FPA's constant RAM.
2265 The value returned, anded with 0x1ff, gives the code to use in fpmove
2266 to get the desired constant. */
2268 static int inited_FPA_table
= 0;
2270 char *strings_FPA
[38] = {
2271 /* small rationals */
2284 /* Decimal equivalents of double precision values */
2285 "2.718281828459045091", /* D_E */
2286 "6.283185307179586477", /* 2 pi */
2287 "3.141592653589793116", /* D_PI */
2288 "1.570796326794896619", /* pi/2 */
2289 "1.414213562373095145", /* D_SQRT2 */
2290 "0.7071067811865475244", /* 1/sqrt(2) */
2291 "-1.570796326794896619", /* -pi/2 */
2292 "1.442695040888963387", /* D_LOG2ofE */
2293 "3.321928024887362182", /* D_LOG2of10 */
2294 "0.6931471805599452862", /* D_LOGEof2 */
2295 "2.302585092994045901", /* D_LOGEof10 */
2296 "0.3010299956639811980", /* D_LOG10of2 */
2297 "0.4342944819032518167", /* D_LOG10ofE */
2298 /* Decimal equivalents of single precision values */
2299 "2.718281745910644531", /* S_E */
2300 "6.283185307179586477", /* 2 pi */
2301 "3.141592741012573242", /* S_PI */
2302 "1.570796326794896619", /* pi/2 */
2303 "1.414213538169860840", /* S_SQRT2 */
2304 "0.7071067811865475244", /* 1/sqrt(2) */
2305 "-1.570796326794896619", /* -pi/2 */
2306 "1.442695021629333496", /* S_LOG2ofE */
2307 "3.321928024291992188", /* S_LOG2of10 */
2308 "0.6931471824645996094", /* S_LOGEof2 */
2309 "2.302585124969482442", /* S_LOGEof10 */
2310 "0.3010300099849700928", /* S_LOG10of2 */
2311 "0.4342944920063018799", /* S_LOG10ofE */
2315 int codes_FPA
[38] = {
2316 /* small rationals */
2329 /* double precision */
2343 /* single precision */
2359 REAL_VALUE_TYPE values_FPA
[38];
2361 /* This code has been fixed for cross-compilation. */
2366 enum machine_mode mode
;
2371 for (i
= 0; i
< 38; i
++)
2375 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2378 inited_FPA_table
= 1;
2383 standard_sun_fpa_constant_p (x
)
2389 #ifndef REAL_ARITHMETIC
2390 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2391 if (! flag_pretend_float
)
2396 if (! inited_FPA_table
)
2399 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2401 for (i
=0; i
<12; i
++)
2403 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2404 return (codes_FPA
[i
]);
2407 if (GET_MODE (x
) == SFmode
)
2409 for (i
=25; i
<38; i
++)
2411 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2412 return (codes_FPA
[i
]);
2417 for (i
=12; i
<25; i
++)
2419 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2420 return (codes_FPA
[i
]);
2425 #endif /* define SUPPORT_SUN_FPA */
2427 /* A C compound statement to output to stdio stream STREAM the
2428 assembler syntax for an instruction operand X. X is an RTL
2431 CODE is a value that can be used to specify one of several ways
2432 of printing the operand. It is used when identical operands
2433 must be printed differently depending on the context. CODE
2434 comes from the `%' specification that was used to request
2435 printing of the operand. If the specification was just `%DIGIT'
2436 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2437 is the ASCII code for LTR.
2439 If X is a register, this macro should print the register's name.
2440 The names can be found in an array `reg_names' whose type is
2441 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2443 When the machine description has a specification `%PUNCT' (a `%'
2444 followed by a punctuation character), this macro is called with
2445 a null pointer for X and the punctuation character for CODE.
2447 The m68k specific codes are:
2449 '.' for dot needed in Motorola-style opcode names.
2450 '-' for an operand pushing on the stack:
2451 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2452 '+' for an operand pushing on the stack:
2453 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2454 '@' for a reference to the top word on the stack:
2455 sp@, (sp) or (%sp) depending on the style of syntax.
2456 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2457 but & in SGS syntax, $ in CRDS/UNOS syntax).
2458 '!' for the cc register (used in an `and to cc' insn).
2459 '$' for the letter `s' in an op code, but only on the 68040.
2460 '&' for the letter `d' in an op code, but only on the 68040.
2461 '/' for register prefix needed by longlong.h.
2463 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2464 'd' to force memory addressing to be absolute, not relative.
2465 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2466 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2467 than directly). Second part of 'y' below.
2468 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2469 or print pair of registers as rx:ry.
2470 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2471 CONST_DOUBLE's as SunFPA constant RAM registers if
2472 possible, so it should not be used except for the SunFPA.
2477 print_operand (file
, op
, letter
)
2478 FILE *file
; /* file to write to */
2479 rtx op
; /* operand to print */
2480 int letter
; /* %<letter> or 0 */
2486 #if defined (MOTOROLA) && !defined (CRDS)
2487 asm_fprintf (file
, ".");
2490 else if (letter
== '#')
2492 asm_fprintf (file
, "%0I");
2494 else if (letter
== '-')
2497 asm_fprintf (file
, "-(%Rsp)");
2499 asm_fprintf (file
, "%Rsp@-");
2502 else if (letter
== '+')
2505 asm_fprintf (file
, "(%Rsp)+");
2507 asm_fprintf (file
, "%Rsp@+");
2510 else if (letter
== '@')
2513 asm_fprintf (file
, "(%Rsp)");
2515 asm_fprintf (file
, "%Rsp@");
2518 else if (letter
== '!')
2520 asm_fprintf (file
, "%Rfpcr");
2522 else if (letter
== '$')
2524 if (TARGET_68040_ONLY
)
2526 fprintf (file
, "s");
2529 else if (letter
== '&')
2531 if (TARGET_68040_ONLY
)
2533 fprintf (file
, "d");
2536 else if (letter
== '/')
2538 asm_fprintf (file
, "%R");
2540 else if (GET_CODE (op
) == REG
)
2542 #ifdef SUPPORT_SUN_FPA
2544 && (letter
== 'y' || letter
== 'x')
2545 && GET_MODE (op
) == DFmode
)
2547 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2548 reg_names
[REGNO (op
)+1]);
2554 /* Print out the second register name of a register pair.
2555 I.e., R (6) => 7. */
2556 fputs (reg_names
[REGNO (op
) + 1], file
);
2558 fputs (reg_names
[REGNO (op
)], file
);
2561 else if (GET_CODE (op
) == MEM
)
2563 output_address (XEXP (op
, 0));
2564 if (letter
== 'd' && ! TARGET_68020
2565 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2566 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2567 && INTVAL (XEXP (op
, 0)) < 0x8000
2568 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2571 fprintf (file
, ".l");
2573 fprintf (file
, ":l");
2577 #ifdef SUPPORT_SUN_FPA
2578 else if ((letter
== 'y' || letter
== 'w')
2579 && GET_CODE (op
) == CONST_DOUBLE
2580 && (i
= standard_sun_fpa_constant_p (op
)))
2582 fprintf (file
, "%%%d", i
& 0x1ff);
2585 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2588 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2589 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2591 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2594 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2595 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2597 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2600 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2601 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2605 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2610 /* A C compound statement to output to stdio stream STREAM the
2611 assembler syntax for an instruction operand that is a memory
2612 reference whose address is ADDR. ADDR is an RTL expression.
2614 Note that this contains a kludge that knows that the only reason
2615 we have an address (plus (label_ref...) (reg...)) when not generating
2616 PIC code is in the insn before a tablejump, and we know that m68k.md
2617 generates a label LInnn: on such an insn.
2619 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2620 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2622 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2623 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2624 we want. This difference can be accommodated by using an assembler
2625 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2626 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2627 macro. See m68k/sgs.h for an example; for versions without the bug.
2628 Some assemblers refuse all the above solutions. The workaround is to
2629 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2632 They also do not like things like "pea 1.w", so we simple leave off
2633 the .w on small constants.
2635 This routine is responsible for distinguishing between -fpic and -fPIC
2636 style relocations in an address. When generating -fpic code the
2637 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2638 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2640 #ifndef ASM_OUTPUT_CASE_FETCH
2643 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2644 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2646 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2647 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2650 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2651 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2653 #endif /* ASM_OUTPUT_CASE_FETCH */
2656 print_operand_address (file
, addr
)
2660 register rtx reg1
, reg2
, breg
, ireg
;
2663 switch (GET_CODE (addr
))
2667 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2669 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2674 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2676 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2681 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2683 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2687 reg1
= reg2
= ireg
= breg
= offset
= 0;
2688 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2690 offset
= XEXP (addr
, 0);
2691 addr
= XEXP (addr
, 1);
2693 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2695 offset
= XEXP (addr
, 1);
2696 addr
= XEXP (addr
, 0);
2698 if (GET_CODE (addr
) != PLUS
)
2702 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2704 reg1
= XEXP (addr
, 0);
2705 addr
= XEXP (addr
, 1);
2707 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2709 reg1
= XEXP (addr
, 1);
2710 addr
= XEXP (addr
, 0);
2712 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2714 reg1
= XEXP (addr
, 0);
2715 addr
= XEXP (addr
, 1);
2717 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2719 reg1
= XEXP (addr
, 1);
2720 addr
= XEXP (addr
, 0);
2722 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2724 reg1
= XEXP (addr
, 0);
2725 addr
= XEXP (addr
, 1);
2727 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2729 reg1
= XEXP (addr
, 1);
2730 addr
= XEXP (addr
, 0);
2732 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2733 || GET_CODE (addr
) == SIGN_EXTEND
)
2745 #if 0 /* for OLD_INDEXING */
2746 else if (GET_CODE (addr
) == PLUS
)
2748 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2750 reg2
= XEXP (addr
, 0);
2751 addr
= XEXP (addr
, 1);
2753 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2755 reg2
= XEXP (addr
, 1);
2756 addr
= XEXP (addr
, 0);
2768 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2769 || GET_CODE (reg1
) == MULT
))
2770 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2775 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2780 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2781 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
2784 if (GET_CODE (ireg
) == MULT
)
2786 scale
= INTVAL (XEXP (ireg
, 1));
2787 ireg
= XEXP (ireg
, 0);
2789 if (GET_CODE (ireg
) == SIGN_EXTEND
)
2791 ASM_OUTPUT_CASE_FETCH (file
,
2792 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2793 reg_names
[REGNO (XEXP (ireg
, 0))]);
2794 fprintf (file
, "w");
2798 ASM_OUTPUT_CASE_FETCH (file
,
2799 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2800 reg_names
[REGNO (ireg
)]);
2801 fprintf (file
, "l");
2806 fprintf (file
, "*%d", scale
);
2808 fprintf (file
, ":%d", scale
);
2814 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
2815 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
2817 ASM_OUTPUT_CASE_FETCH (file
,
2818 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2819 reg_names
[REGNO (breg
)]);
2820 fprintf (file
, "l)");
2823 if (ireg
!= 0 || breg
!= 0)
2830 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
2837 output_addr_const (file
, addr
);
2838 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
2839 fprintf (file
, "@GOT");
2841 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
2847 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
2850 output_addr_const (file
, addr
);
2851 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
2852 fprintf (file
, ":w");
2853 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
2854 fprintf (file
, ":l");
2856 if (addr
!= 0 && ireg
!= 0)
2861 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
2863 scale
= INTVAL (XEXP (ireg
, 1));
2864 ireg
= XEXP (ireg
, 0);
2866 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
2869 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2871 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
2877 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
2879 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
2885 fprintf (file
, "*%d", scale
);
2887 fprintf (file
, ":%d", scale
);
2893 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
2894 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
2896 ASM_OUTPUT_CASE_FETCH (file
,
2897 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
2898 reg_names
[REGNO (reg1
)]);
2899 fprintf (file
, "l)");
2902 /* FALL-THROUGH (is this really what we want? */
2904 if (GET_CODE (addr
) == CONST_INT
2905 && INTVAL (addr
) < 0x8000
2906 && INTVAL (addr
) >= -0x8000)
2910 /* Many SGS assemblers croak on size specifiers for constants. */
2911 fprintf (file
, "%d", INTVAL (addr
));
2913 fprintf (file
, "%d.w", INTVAL (addr
));
2916 fprintf (file
, "%d:w", INTVAL (addr
));
2921 output_addr_const (file
, addr
);
2927 /* Check for cases where a clr insns can be omitted from code using
2928 strict_low_part sets. For example, the second clrl here is not needed:
2929 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
2931 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
2932 insn we are checking for redundancy. TARGET is the register set by the
2936 strict_low_part_peephole_ok (mode
, first_insn
, target
)
2937 enum machine_mode mode
;
2943 p
= prev_nonnote_insn (first_insn
);
2947 /* If it isn't an insn, then give up. */
2948 if (GET_CODE (p
) != INSN
)
2951 if (reg_set_p (target
, p
))
2953 rtx set
= single_set (p
);
2956 /* If it isn't an easy to recognize insn, then give up. */
2960 dest
= SET_DEST (set
);
2962 /* If this sets the entire target register to zero, then our
2963 first_insn is redundant. */
2964 if (rtx_equal_p (dest
, target
)
2965 && SET_SRC (set
) == const0_rtx
)
2967 else if (GET_CODE (dest
) == STRICT_LOW_PART
2968 && GET_CODE (XEXP (dest
, 0)) == REG
2969 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
2970 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
2971 <= GET_MODE_SIZE (mode
)))
2972 /* This is a strict low part set which modifies less than
2973 we are using, so it is safe. */
2979 p
= prev_nonnote_insn (p
);
2986 /* Accept integer operands in the range 0..0xffffffff. We have to check the
2987 range carefully since this predicate is used in DImode contexts. Also, we
2988 need some extra crud to make it work when hosted on 64-bit machines. */
2991 const_uint32_operand (op
, mode
)
2993 enum machine_mode mode
;
2995 #if HOST_BITS_PER_WIDE_INT > 32
2996 /* All allowed constants will fit a CONST_INT. */
2997 return (GET_CODE (op
) == CONST_INT
2998 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3000 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3001 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3005 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3006 to check the range carefully since this predicate is used in DImode
3010 const_sint32_operand (op
, mode
)
3012 enum machine_mode mode
;
3014 /* All allowed constants will fit a CONST_INT. */
3015 return (GET_CODE (op
) == CONST_INT
3016 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));