1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* The minimum number of integer registers that we want to save with the
74 movem instruction. Using two movel instructions instead of a single
75 moveml is about 15% faster for the 68020 and 68030 at no expense in
77 #define MIN_MOVEM_REGS 3
79 /* The minimum number of floating point registers that we want to save
80 with the fmovem instruction. */
81 #define MIN_FMOVEM_REGS 1
83 /* Structure describing stack frame layout. */
86 /* Stack pointer to frame pointer offset. */
89 /* Offset of FPU registers. */
90 HOST_WIDE_INT foffset
;
92 /* Frame size in bytes (rounded up). */
95 /* Data and address register. */
97 unsigned int reg_mask
;
101 unsigned int fpu_mask
;
103 /* Offsets relative to ARG_POINTER. */
104 HOST_WIDE_INT frame_pointer_offset
;
105 HOST_WIDE_INT stack_pointer_offset
;
107 /* Function which the above information refers to. */
111 /* Current frame information calculated by m68k_compute_frame_layout(). */
112 static struct m68k_frame current_frame
;
114 /* Structure describing an m68k address.
116 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
117 with null fields evaluating to 0. Here:
119 - BASE satisfies m68k_legitimate_base_reg_p
120 - INDEX satisfies m68k_legitimate_index_reg_p
121 - OFFSET satisfies m68k_legitimate_constant_address_p
123 INDEX is either HImode or SImode. The other fields are SImode.
125 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
126 the address is (BASE)+. */
127 struct m68k_address
{
135 static bool m68k_handle_option (size_t, const char *, int);
136 static rtx
find_addr_reg (rtx
);
137 static const char *singlemove_string (rtx
*);
138 #ifdef M68K_TARGET_COFF
139 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
140 #endif /* M68K_TARGET_COFF */
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_rtx_costs (rtx
, int, int, int *);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands
;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_DEFAULT_TARGET_FLAGS
200 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
201 #undef TARGET_HANDLE_OPTION
202 #define TARGET_HANDLE_OPTION m68k_handle_option
204 #undef TARGET_RTX_COSTS
205 #define TARGET_RTX_COSTS m68k_rtx_costs
207 #undef TARGET_ATTRIBUTE_TABLE
208 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
210 #undef TARGET_PROMOTE_PROTOTYPES
211 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
213 #undef TARGET_STRUCT_VALUE_RTX
214 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
216 #undef TARGET_CANNOT_FORCE_CONST_MEM
217 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
219 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
220 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
222 static const struct attribute_spec m68k_attribute_table
[] =
224 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
225 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
226 { NULL
, 0, 0, false, false, false, NULL
}
229 struct gcc_target targetm
= TARGET_INITIALIZER
;
231 /* Base flags for 68k ISAs. */
232 #define FL_FOR_isa_00 FL_ISA_68000
233 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
234 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
235 generated 68881 code for 68020 and 68030 targets unless explicitly told
237 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
238 | FL_BITFIELD | FL_68881)
239 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
240 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
242 /* Base flags for ColdFire ISAs. */
243 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
244 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
245 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
246 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
247 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
251 /* Traditional 68000 instruction sets. */
257 /* ColdFire instruction set variants. */
265 /* Information about one of the -march, -mcpu or -mtune arguments. */
266 struct m68k_target_selection
268 /* The argument being described. */
271 /* For -mcpu, this is the device selected by the option.
272 For -mtune and -march, it is a representative device
273 for the microarchitecture or ISA respectively. */
274 enum target_device device
;
276 /* The M68K_DEVICE fields associated with DEVICE. See the comment
277 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
279 enum uarch_type microarch
;
284 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
285 static const struct m68k_target_selection all_devices
[] =
287 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
288 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
289 #include "m68k-devices.def"
291 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
294 /* A list of all ISAs, mapping each one to a representative device.
295 Used for -march selection. */
296 static const struct m68k_target_selection all_isas
[] =
298 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
299 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
300 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
301 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
302 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
303 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
304 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
305 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
307 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
309 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
310 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
313 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
316 /* A list of all microarchitectures, mapping each one to a representative
317 device. Used for -mtune selection. */
318 static const struct m68k_target_selection all_microarchs
[] =
320 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
321 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
322 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
323 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
324 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
325 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
326 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
327 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
328 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
329 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
330 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
332 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
333 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
337 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
340 /* The entries associated with the -mcpu, -march and -mtune settings,
341 or null for options that have not been used. */
342 const struct m68k_target_selection
*m68k_cpu_entry
;
343 const struct m68k_target_selection
*m68k_arch_entry
;
344 const struct m68k_target_selection
*m68k_tune_entry
;
346 /* Which CPU we are generating code for. */
347 enum target_device m68k_cpu
;
349 /* Which microarchitecture to tune for. */
350 enum uarch_type m68k_tune
;
352 /* Which FPU to use. */
353 enum fpu_type m68k_fpu
;
355 /* The set of FL_* flags that apply to the target processor. */
356 unsigned int m68k_cpu_flags
;
358 /* Asm templates for calling or jumping to an arbitrary symbolic address,
359 or NULL if such calls or jumps are not supported. The address is held
361 const char *m68k_symbolic_call
;
362 const char *m68k_symbolic_jump
;
364 /* See whether TABLE has an entry with name NAME. Return true and
365 store the entry in *ENTRY if so, otherwise return false and
366 leave *ENTRY alone. */
369 m68k_find_selection (const struct m68k_target_selection
**entry
,
370 const struct m68k_target_selection
*table
,
375 for (i
= 0; table
[i
].name
; i
++)
376 if (strcmp (table
[i
].name
, name
) == 0)
384 /* Implement TARGET_HANDLE_OPTION. */
387 m68k_handle_option (size_t code
, const char *arg
, int value
)
392 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
395 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
398 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
401 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
404 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
407 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
410 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
413 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
420 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
423 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
427 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
430 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
432 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
435 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
437 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
440 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
443 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
446 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
449 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
453 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
455 case OPT_mshared_library_id_
:
456 if (value
> MAX_LIBRARY_ID
)
457 error ("-mshared-library-id=%s is not between 0 and %d",
458 arg
, MAX_LIBRARY_ID
);
460 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
468 /* Sometimes certain combinations of command options do not make
469 sense on a particular target machine. You can define a macro
470 `OVERRIDE_OPTIONS' to take account of this. This macro, if
471 defined, is executed once just after all the command options have
474 Don't use this macro to turn on various extra optimizations for
475 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
478 override_options (void)
480 const struct m68k_target_selection
*entry
;
481 unsigned long target_mask
;
489 -march=ARCH should generate code that runs any processor
490 implementing architecture ARCH. -mcpu=CPU should override -march
491 and should generate code that runs on processor CPU, making free
492 use of any instructions that CPU understands. -mtune=UARCH applies
493 on top of -mcpu or -march and optimizes the code for UARCH. It does
494 not change the target architecture. */
497 /* Complain if the -march setting is for a different microarchitecture,
498 or includes flags that the -mcpu setting doesn't. */
500 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
501 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
502 warning (0, "-mcpu=%s conflicts with -march=%s",
503 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
505 entry
= m68k_cpu_entry
;
508 entry
= m68k_arch_entry
;
511 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
513 m68k_cpu_flags
= entry
->flags
;
515 /* Use the architecture setting to derive default values for
518 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
519 target_mask
|= MASK_BITFIELD
;
520 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
521 target_mask
|= MASK_CF_HWDIV
;
522 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
523 target_mask
|= MASK_HARD_FLOAT
;
524 target_flags
|= target_mask
& ~target_flags_explicit
;
526 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
527 m68k_cpu
= entry
->device
;
529 m68k_tune
= m68k_tune_entry
->microarch
;
530 #ifdef M68K_DEFAULT_TUNE
531 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
532 m68k_tune
= M68K_DEFAULT_TUNE
;
535 m68k_tune
= entry
->microarch
;
537 /* Set the type of FPU. */
538 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
539 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
542 if (TARGET_COLDFIRE_FPU
)
544 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
545 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
548 /* Sanity check to ensure that msep-data and mid-sahred-library are not
549 * both specified together. Doing so simply doesn't make sense.
551 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
552 error ("cannot specify both -msep-data and -mid-shared-library");
554 /* If we're generating code for a separate A5 relative data segment,
555 * we've got to enable -fPIC as well. This might be relaxable to
556 * -fpic but it hasn't been tested properly.
558 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
561 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
562 error if the target does not support them. */
563 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
564 error ("-mpcrel -fPIC is not currently supported on selected cpu");
566 /* ??? A historic way of turning on pic, or is this intended to
567 be an embedded thing that doesn't have the same name binding
568 significance that it does on hosted ELF systems? */
569 if (TARGET_PCREL
&& flag_pic
== 0)
574 #if MOTOROLA && !defined (USE_GAS)
575 m68k_symbolic_call
= "jsr %a0";
576 m68k_symbolic_jump
= "jmp %a0";
578 m68k_symbolic_call
= "jbsr %a0";
579 m68k_symbolic_jump
= "jra %a0";
582 else if (TARGET_ID_SHARED_LIBRARY
)
583 /* All addresses must be loaded from the GOT. */
585 else if (TARGET_68020
|| TARGET_ISAB
)
589 m68k_symbolic_call
= "bsr.l %c0";
590 m68k_symbolic_jump
= "bra.l %c0";
595 m68k_symbolic_call
= "bsr.l %p0";
596 m68k_symbolic_jump
= "bra.l %p0";
598 m68k_symbolic_call
= "bsr %p0";
599 m68k_symbolic_jump
= "bra %p0";
602 /* Turn off function cse if we are doing PIC. We always want
603 function call to be done as `bsr foo@PLTPC'. */
604 /* ??? It's traditional to do this for -mpcrel too, but it isn't
605 clear how intentional that is. */
606 flag_no_function_cse
= 1;
609 SUBTARGET_OVERRIDE_OPTIONS
;
612 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
613 given argument and NAME is the argument passed to -mcpu. Return NULL
614 if -mcpu was not passed. */
617 m68k_cpp_cpu_ident (const char *prefix
)
621 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
624 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
625 given argument and NAME is the name of the representative device for
626 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
629 m68k_cpp_cpu_family (const char *prefix
)
633 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
636 /* Return nonzero if FUNC is an interrupt function as specified by the
637 "interrupt_handler" attribute. */
639 m68k_interrupt_function_p (tree func
)
643 if (TREE_CODE (func
) != FUNCTION_DECL
)
646 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
647 return (a
!= NULL_TREE
);
650 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
651 struct attribute_spec.handler. */
653 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
654 tree args ATTRIBUTE_UNUSED
,
655 int flags ATTRIBUTE_UNUSED
,
658 if (TREE_CODE (*node
) != FUNCTION_DECL
)
660 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
661 IDENTIFIER_POINTER (name
));
662 *no_add_attrs
= true;
669 m68k_compute_frame_layout (void)
673 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
675 /* Only compute the frame once per function.
676 Don't cache information until reload has been completed. */
677 if (current_frame
.funcdef_no
== current_function_funcdef_no
681 current_frame
.size
= (get_frame_size () + 3) & -4;
684 for (regno
= 0; regno
< 16; regno
++)
685 if (m68k_save_reg (regno
, interrupt_handler
))
687 mask
|= 1 << (regno
- D0_REG
);
690 current_frame
.offset
= saved
* 4;
691 current_frame
.reg_no
= saved
;
692 current_frame
.reg_mask
= mask
;
694 current_frame
.foffset
= 0;
696 if (TARGET_HARD_FLOAT
)
698 for (regno
= 16; regno
< 24; regno
++)
699 if (m68k_save_reg (regno
, interrupt_handler
))
701 mask
|= 1 << (regno
- FP0_REG
);
704 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
705 current_frame
.offset
+= current_frame
.foffset
;
707 current_frame
.fpu_no
= saved
;
708 current_frame
.fpu_mask
= mask
;
710 /* Remember what function this frame refers to. */
711 current_frame
.funcdef_no
= current_function_funcdef_no
;
715 m68k_initial_elimination_offset (int from
, int to
)
718 /* The arg pointer points 8 bytes before the start of the arguments,
719 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
720 frame pointer in most frames. */
721 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
722 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
723 return argptr_offset
;
725 m68k_compute_frame_layout ();
727 gcc_assert (to
== STACK_POINTER_REGNUM
);
730 case ARG_POINTER_REGNUM
:
731 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
732 case FRAME_POINTER_REGNUM
:
733 return current_frame
.offset
+ current_frame
.size
;
739 /* Refer to the array `regs_ever_live' to determine which registers
740 to save; `regs_ever_live[I]' is nonzero if register number I
741 is ever used in the function. This function is responsible for
742 knowing which registers should not be saved even if used.
743 Return true if we need to save REGNO. */
746 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
748 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
750 if (current_function_uses_pic_offset_table
)
752 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
756 if (current_function_calls_eh_return
)
761 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
762 if (test
== INVALID_REGNUM
)
769 /* Fixed regs we never touch. */
770 if (fixed_regs
[regno
])
773 /* The frame pointer (if it is such) is handled specially. */
774 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
777 /* Interrupt handlers must also save call_used_regs
778 if they are live or when calling nested functions. */
779 if (interrupt_handler
)
781 if (regs_ever_live
[regno
])
784 if (!current_function_is_leaf
&& call_used_regs
[regno
])
788 /* Never need to save registers that aren't touched. */
789 if (!regs_ever_live
[regno
])
792 /* Otherwise save everything that isn't call-clobbered. */
793 return !call_used_regs
[regno
];
796 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
797 the lowest memory address. COUNT is the number of registers to be
798 moved, with register REGNO + I being moved if bit I of MASK is set.
799 STORE_P specifies the direction of the move and ADJUST_STACK_P says
800 whether or not this is pre-decrement (if STORE_P) or post-increment
801 (if !STORE_P) operation. */
804 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
805 unsigned int count
, unsigned int regno
,
806 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
809 rtx body
, addr
, src
, operands
[2];
810 enum machine_mode mode
;
812 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
813 mode
= reg_raw_mode
[regno
];
818 src
= plus_constant (base
, (count
819 * GET_MODE_SIZE (mode
)
820 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
821 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
824 for (; mask
!= 0; mask
>>= 1, regno
++)
827 addr
= plus_constant (base
, offset
);
828 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
829 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
830 XVECEXP (body
, 0, i
++)
831 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
832 offset
+= GET_MODE_SIZE (mode
);
834 gcc_assert (i
== XVECLEN (body
, 0));
836 return emit_insn (body
);
839 /* Make INSN a frame-related instruction. */
842 m68k_set_frame_related (rtx insn
)
847 RTX_FRAME_RELATED_P (insn
) = 1;
848 body
= PATTERN (insn
);
849 if (GET_CODE (body
) == PARALLEL
)
850 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
851 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
854 /* Emit RTL for the "prologue" define_expand. */
857 m68k_expand_prologue (void)
859 HOST_WIDE_INT fsize_with_regs
;
860 rtx limit
, src
, dest
, insn
;
862 m68k_compute_frame_layout ();
864 /* If the stack limit is a symbol, we can check it here,
865 before actually allocating the space. */
866 if (current_function_limit_stack
867 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
869 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
870 if (!LEGITIMATE_CONSTANT_P (limit
))
872 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
873 limit
= gen_rtx_REG (Pmode
, D0_REG
);
875 emit_insn (gen_cmpsi (stack_pointer_rtx
, limit
));
876 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
877 cc0_rtx
, const0_rtx
),
881 fsize_with_regs
= current_frame
.size
;
884 /* ColdFire's move multiple instructions do not allow pre-decrement
885 addressing. Add the size of movem saves to the initial stack
886 allocation instead. */
887 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
888 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
889 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
890 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
893 if (frame_pointer_needed
)
895 if (fsize_with_regs
== 0 && TUNE_68040
)
897 /* On the 68040, two separate moves are faster than link.w 0. */
898 dest
= gen_frame_mem (Pmode
,
899 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
900 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
901 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
904 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
905 m68k_set_frame_related
906 (emit_insn (gen_link (frame_pointer_rtx
,
907 GEN_INT (-4 - fsize_with_regs
))));
910 m68k_set_frame_related
911 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
912 m68k_set_frame_related
913 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
915 GEN_INT (-fsize_with_regs
))));
918 else if (fsize_with_regs
!= 0)
919 m68k_set_frame_related
920 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
922 GEN_INT (-fsize_with_regs
))));
924 if (current_frame
.fpu_mask
)
926 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
928 m68k_set_frame_related
929 (m68k_emit_movem (stack_pointer_rtx
,
930 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
931 current_frame
.fpu_no
, FP0_REG
,
932 current_frame
.fpu_mask
, true, true));
937 /* If we're using moveml to save the integer registers,
938 the stack pointer will point to the bottom of the moveml
939 save area. Find the stack offset of the first FP register. */
940 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
943 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
944 m68k_set_frame_related
945 (m68k_emit_movem (stack_pointer_rtx
, offset
,
946 current_frame
.fpu_no
, FP0_REG
,
947 current_frame
.fpu_mask
, true, false));
951 /* If the stack limit is not a symbol, check it here.
952 This has the disadvantage that it may be too late... */
953 if (current_function_limit_stack
)
955 if (REG_P (stack_limit_rtx
))
957 emit_insn (gen_cmpsi (stack_pointer_rtx
, stack_limit_rtx
));
958 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode
,
959 cc0_rtx
, const0_rtx
),
962 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
963 warning (0, "stack limit expression is not supported");
966 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
968 /* Store each register separately in the same order moveml does. */
971 for (i
= 16; i
-- > 0; )
972 if (current_frame
.reg_mask
& (1 << i
))
974 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
975 dest
= gen_frame_mem (SImode
,
976 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
977 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
983 /* The required register save space has already been allocated.
984 The first register should be stored at (%sp). */
985 m68k_set_frame_related
986 (m68k_emit_movem (stack_pointer_rtx
, 0,
987 current_frame
.reg_no
, D0_REG
,
988 current_frame
.reg_mask
, true, false));
990 m68k_set_frame_related
991 (m68k_emit_movem (stack_pointer_rtx
,
992 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
993 current_frame
.reg_no
, D0_REG
,
994 current_frame
.reg_mask
, true, true));
999 && (current_function_uses_pic_offset_table
1000 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
1002 insn
= emit_insn (gen_load_got (pic_offset_table_rtx
));
1003 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
1009 /* Return true if a simple (return) instruction is sufficient for this
1010 instruction (i.e. if no epilogue is needed). */
1013 m68k_use_return_insn (void)
1015 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1018 m68k_compute_frame_layout ();
1019 return current_frame
.offset
== 0;
1022 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1023 SIBCALL_P says which.
1025 The function epilogue should not depend on the current stack pointer!
1026 It should use the frame pointer only, if there is a frame pointer.
1027 This is mandatory because of alloca; we also take advantage of it to
1028 omit stack adjustments before returning. */
1031 m68k_expand_epilogue (bool sibcall_p
)
1033 HOST_WIDE_INT fsize
, fsize_with_regs
;
1034 bool big
, restore_from_sp
;
1036 m68k_compute_frame_layout ();
1038 fsize
= current_frame
.size
;
1040 restore_from_sp
= false;
1042 /* FIXME : current_function_is_leaf below is too strong.
1043 What we really need to know there is if there could be pending
1044 stack adjustment needed at that point. */
1045 restore_from_sp
= (!frame_pointer_needed
1046 || (!current_function_calls_alloca
1047 && current_function_is_leaf
));
1049 /* fsize_with_regs is the size we need to adjust the sp when
1050 popping the frame. */
1051 fsize_with_regs
= fsize
;
1052 if (TARGET_COLDFIRE
&& restore_from_sp
)
1054 /* ColdFire's move multiple instructions do not allow post-increment
1055 addressing. Add the size of movem loads to the final deallocation
1057 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1058 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1059 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1060 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1063 if (current_frame
.offset
+ fsize
>= 0x8000
1065 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1068 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1069 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1071 /* ColdFire's move multiple instructions do not support the
1072 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1073 stack-based restore. */
1074 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1075 GEN_INT (-(current_frame
.offset
+ fsize
)));
1076 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1077 gen_rtx_REG (Pmode
, A1_REG
),
1078 frame_pointer_rtx
));
1079 restore_from_sp
= true;
1083 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1089 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1091 /* Restore each register separately in the same order moveml does. */
1093 HOST_WIDE_INT offset
;
1095 offset
= current_frame
.offset
+ fsize
;
1096 for (i
= 0; i
< 16; i
++)
1097 if (current_frame
.reg_mask
& (1 << i
))
1103 /* Generate the address -OFFSET(%fp,%a1.l). */
1104 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1105 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1106 addr
= plus_constant (addr
, -offset
);
1108 else if (restore_from_sp
)
1109 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1111 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1112 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1113 gen_frame_mem (SImode
, addr
));
1114 offset
-= GET_MODE_SIZE (SImode
);
1117 else if (current_frame
.reg_mask
)
1120 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1121 gen_rtx_REG (Pmode
, A1_REG
),
1123 -(current_frame
.offset
+ fsize
),
1124 current_frame
.reg_no
, D0_REG
,
1125 current_frame
.reg_mask
, false, false);
1126 else if (restore_from_sp
)
1127 m68k_emit_movem (stack_pointer_rtx
, 0,
1128 current_frame
.reg_no
, D0_REG
,
1129 current_frame
.reg_mask
, false,
1132 m68k_emit_movem (frame_pointer_rtx
,
1133 -(current_frame
.offset
+ fsize
),
1134 current_frame
.reg_no
, D0_REG
,
1135 current_frame
.reg_mask
, false, false);
1138 if (current_frame
.fpu_no
> 0)
1141 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1142 gen_rtx_REG (Pmode
, A1_REG
),
1144 -(current_frame
.foffset
+ fsize
),
1145 current_frame
.fpu_no
, FP0_REG
,
1146 current_frame
.fpu_mask
, false, false);
1147 else if (restore_from_sp
)
1149 if (TARGET_COLDFIRE
)
1153 /* If we used moveml to restore the integer registers, the
1154 stack pointer will still point to the bottom of the moveml
1155 save area. Find the stack offset of the first FP
1157 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1160 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1161 m68k_emit_movem (stack_pointer_rtx
, offset
,
1162 current_frame
.fpu_no
, FP0_REG
,
1163 current_frame
.fpu_mask
, false, false);
1166 m68k_emit_movem (stack_pointer_rtx
, 0,
1167 current_frame
.fpu_no
, FP0_REG
,
1168 current_frame
.fpu_mask
, false, true);
1171 m68k_emit_movem (frame_pointer_rtx
,
1172 -(current_frame
.foffset
+ fsize
),
1173 current_frame
.fpu_no
, FP0_REG
,
1174 current_frame
.fpu_mask
, false, false);
1177 if (frame_pointer_needed
)
1178 emit_insn (gen_unlink (frame_pointer_rtx
));
1179 else if (fsize_with_regs
)
1180 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1182 GEN_INT (fsize_with_regs
)));
1184 if (current_function_calls_eh_return
)
1185 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1187 EH_RETURN_STACKADJ_RTX
));
1190 emit_insn (gen_rtx_RETURN (VOIDmode
));
1193 /* Return true if X is a valid comparison operator for the dbcc
1196 Note it rejects floating point comparison operators.
1197 (In the future we could use Fdbcc).
1199 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1202 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1204 switch (GET_CODE (x
))
1206 case EQ
: case NE
: case GTU
: case LTU
:
1210 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1212 case GT
: case LT
: case GE
: case LE
:
1213 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1219 /* Return nonzero if flags are currently in the 68881 flag register. */
1221 flags_in_68881 (void)
1223 /* We could add support for these in the future */
1224 return cc_status
.flags
& CC_IN_68881
;
1227 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. We cannot use sibcalls
1228 for nested functions because we use the static chain register for
1232 m68k_ok_for_sibcall_p (tree decl ATTRIBUTE_UNUSED
, tree exp
)
1234 return TREE_OPERAND (exp
, 2) == NULL
;
1237 /* Convert X to a legitimate function call memory reference and return the
1241 m68k_legitimize_call_address (rtx x
)
1243 gcc_assert (MEM_P (x
));
1244 if (call_operand (XEXP (x
, 0), VOIDmode
))
1246 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1249 /* Likewise for sibling calls. */
1252 m68k_legitimize_sibcall_address (rtx x
)
1254 gcc_assert (MEM_P (x
));
1255 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1258 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1259 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1262 /* Output a dbCC; jCC sequence. Note we do not handle the
1263 floating point version of this sequence (Fdbcc). We also
1264 do not handle alternative conditions when CC_NO_OVERFLOW is
1265 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1266 kick those out before we get here. */
1269 output_dbcc_and_branch (rtx
*operands
)
1271 switch (GET_CODE (operands
[3]))
1274 output_asm_insn (MOTOROLA
1275 ? "dbeq %0,%l1\n\tjbeq %l2"
1276 : "dbeq %0,%l1\n\tjeq %l2",
1281 output_asm_insn (MOTOROLA
1282 ? "dbne %0,%l1\n\tjbne %l2"
1283 : "dbne %0,%l1\n\tjne %l2",
1288 output_asm_insn (MOTOROLA
1289 ? "dbgt %0,%l1\n\tjbgt %l2"
1290 : "dbgt %0,%l1\n\tjgt %l2",
1295 output_asm_insn (MOTOROLA
1296 ? "dbhi %0,%l1\n\tjbhi %l2"
1297 : "dbhi %0,%l1\n\tjhi %l2",
1302 output_asm_insn (MOTOROLA
1303 ? "dblt %0,%l1\n\tjblt %l2"
1304 : "dblt %0,%l1\n\tjlt %l2",
1309 output_asm_insn (MOTOROLA
1310 ? "dbcs %0,%l1\n\tjbcs %l2"
1311 : "dbcs %0,%l1\n\tjcs %l2",
1316 output_asm_insn (MOTOROLA
1317 ? "dbge %0,%l1\n\tjbge %l2"
1318 : "dbge %0,%l1\n\tjge %l2",
1323 output_asm_insn (MOTOROLA
1324 ? "dbcc %0,%l1\n\tjbcc %l2"
1325 : "dbcc %0,%l1\n\tjcc %l2",
1330 output_asm_insn (MOTOROLA
1331 ? "dble %0,%l1\n\tjble %l2"
1332 : "dble %0,%l1\n\tjle %l2",
1337 output_asm_insn (MOTOROLA
1338 ? "dbls %0,%l1\n\tjbls %l2"
1339 : "dbls %0,%l1\n\tjls %l2",
1347 /* If the decrement is to be done in SImode, then we have
1348 to compensate for the fact that dbcc decrements in HImode. */
1349 switch (GET_MODE (operands
[0]))
1352 output_asm_insn (MOTOROLA
1353 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1354 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1367 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1370 enum rtx_code op_code
= GET_CODE (op
);
1372 /* This does not produce a useful cc. */
1375 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1376 below. Swap the operands and change the op if these requirements
1377 are not fulfilled. */
1378 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1382 operand1
= operand2
;
1384 op_code
= swap_condition (op_code
);
1386 loperands
[0] = operand1
;
1387 if (GET_CODE (operand1
) == REG
)
1388 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1390 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1391 if (operand2
!= const0_rtx
)
1393 loperands
[2] = operand2
;
1394 if (GET_CODE (operand2
) == REG
)
1395 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1397 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1399 loperands
[4] = gen_label_rtx ();
1400 if (operand2
!= const0_rtx
)
1402 output_asm_insn (MOTOROLA
1403 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1404 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1409 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1410 output_asm_insn ("tst%.l %0", loperands
);
1412 output_asm_insn ("cmp%.w #0,%0", loperands
);
1414 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1416 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1417 output_asm_insn ("tst%.l %1", loperands
);
1419 output_asm_insn ("cmp%.w #0,%1", loperands
);
1422 loperands
[5] = dest
;
1427 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1428 CODE_LABEL_NUMBER (loperands
[4]));
1429 output_asm_insn ("seq %5", loperands
);
1433 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1434 CODE_LABEL_NUMBER (loperands
[4]));
1435 output_asm_insn ("sne %5", loperands
);
1439 loperands
[6] = gen_label_rtx ();
1440 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1442 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1443 CODE_LABEL_NUMBER (loperands
[4]));
1444 output_asm_insn ("sgt %5", loperands
);
1445 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1446 CODE_LABEL_NUMBER (loperands
[6]));
1450 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1451 CODE_LABEL_NUMBER (loperands
[4]));
1452 output_asm_insn ("shi %5", loperands
);
1456 loperands
[6] = gen_label_rtx ();
1457 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1459 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1460 CODE_LABEL_NUMBER (loperands
[4]));
1461 output_asm_insn ("slt %5", loperands
);
1462 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1463 CODE_LABEL_NUMBER (loperands
[6]));
1467 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1468 CODE_LABEL_NUMBER (loperands
[4]));
1469 output_asm_insn ("scs %5", loperands
);
1473 loperands
[6] = gen_label_rtx ();
1474 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1476 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1477 CODE_LABEL_NUMBER (loperands
[4]));
1478 output_asm_insn ("sge %5", loperands
);
1479 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1480 CODE_LABEL_NUMBER (loperands
[6]));
1484 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1485 CODE_LABEL_NUMBER (loperands
[4]));
1486 output_asm_insn ("scc %5", loperands
);
1490 loperands
[6] = gen_label_rtx ();
1491 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1493 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1494 CODE_LABEL_NUMBER (loperands
[4]));
1495 output_asm_insn ("sle %5", loperands
);
1496 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1497 CODE_LABEL_NUMBER (loperands
[6]));
1501 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1502 CODE_LABEL_NUMBER (loperands
[4]));
1503 output_asm_insn ("sls %5", loperands
);
1513 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1515 operands
[0] = countop
;
1516 operands
[1] = dataop
;
1518 if (GET_CODE (countop
) == CONST_INT
)
1520 register int count
= INTVAL (countop
);
1521 /* If COUNT is bigger than size of storage unit in use,
1522 advance to the containing unit of same size. */
1523 if (count
> signpos
)
1525 int offset
= (count
& ~signpos
) / 8;
1526 count
= count
& signpos
;
1527 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1529 if (count
== signpos
)
1530 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1532 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1534 /* These three statements used to use next_insns_test_no...
1535 but it appears that this should do the same job. */
1537 && next_insn_tests_no_inequality (insn
))
1540 && next_insn_tests_no_inequality (insn
))
1543 && next_insn_tests_no_inequality (insn
))
1546 cc_status
.flags
= CC_NOT_NEGATIVE
;
1548 return "btst %0,%1";
1551 /* Return true if X is a legitimate base register. STRICT_P says
1552 whether we need strict checking. */
1555 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1557 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1558 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1563 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1564 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1567 /* Return true if X is a legitimate index register. STRICT_P says
1568 whether we need strict checking. */
1571 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1573 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1578 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1579 : !FP_REGNO_P (REGNO (x
))));
1582 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1583 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1584 ADDRESS if so. STRICT_P says whether we need strict checking. */
1587 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1591 /* Check for a scale factor. */
1593 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1594 && GET_CODE (x
) == MULT
1595 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1596 && (INTVAL (XEXP (x
, 1)) == 2
1597 || INTVAL (XEXP (x
, 1)) == 4
1598 || (INTVAL (XEXP (x
, 1)) == 8
1599 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1601 scale
= INTVAL (XEXP (x
, 1));
1605 /* Check for a word extension. */
1606 if (!TARGET_COLDFIRE
1607 && GET_CODE (x
) == SIGN_EXTEND
1608 && GET_MODE (XEXP (x
, 0)) == HImode
)
1611 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1613 address
->scale
= scale
;
1621 /* Return true if X is an illegitimate symbolic constant. */
1624 m68k_illegitimate_symbolic_constant_p (rtx x
)
1628 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1630 split_const (x
, &base
, &offset
);
1631 if (GET_CODE (base
) == SYMBOL_REF
1632 && !offset_within_block_p (base
, INTVAL (offset
)))
1638 /* Return true if X is a legitimate constant address that can reach
1639 bytes in the range [X, X + REACH). STRICT_P says whether we need
1643 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1647 if (!CONSTANT_ADDRESS_P (x
))
1651 && !(strict_p
&& TARGET_PCREL
)
1652 && symbolic_operand (x
, VOIDmode
))
1655 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1657 split_const (x
, &base
, &offset
);
1658 if (GET_CODE (base
) == SYMBOL_REF
1659 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1666 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1667 labels will become jump tables. */
1670 m68k_jump_table_ref_p (rtx x
)
1672 if (GET_CODE (x
) != LABEL_REF
)
1676 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1679 x
= next_nonnote_insn (x
);
1680 return x
&& JUMP_TABLE_DATA_P (x
);
1683 /* Return true if X is a legitimate address for values of mode MODE.
1684 STRICT_P says whether strict checking is needed. If the address
1685 is valid, describe its components in *ADDRESS. */
1688 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1689 bool strict_p
, struct m68k_address
*address
)
1693 memset (address
, 0, sizeof (*address
));
1695 if (mode
== BLKmode
)
1698 reach
= GET_MODE_SIZE (mode
);
1700 /* Check for (An) (mode 2). */
1701 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1707 /* Check for -(An) and (An)+ (modes 3 and 4). */
1708 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1709 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1711 address
->code
= GET_CODE (x
);
1712 address
->base
= XEXP (x
, 0);
1716 /* Check for (d16,An) (mode 5). */
1717 if (GET_CODE (x
) == PLUS
1718 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1719 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1720 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1722 address
->base
= XEXP (x
, 0);
1723 address
->offset
= XEXP (x
, 1);
1727 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1728 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1731 && GET_CODE (x
) == PLUS
1732 && XEXP (x
, 0) == pic_offset_table_rtx
1733 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1734 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1736 address
->base
= XEXP (x
, 0);
1737 address
->offset
= XEXP (x
, 1);
1741 /* The ColdFire FPU only accepts addressing modes 2-5. */
1742 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1745 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1746 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1747 All these modes are variations of mode 7. */
1748 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1750 address
->offset
= x
;
1754 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1757 ??? do_tablejump creates these addresses before placing the target
1758 label, so we have to assume that unplaced labels are jump table
1759 references. It seems unlikely that we would ever generate indexed
1760 accesses to unplaced labels in other cases. */
1761 if (GET_CODE (x
) == PLUS
1762 && m68k_jump_table_ref_p (XEXP (x
, 1))
1763 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1765 address
->offset
= XEXP (x
, 1);
1769 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1770 (bd,An,Xn.SIZE*SCALE) addresses. */
1774 /* Check for a nonzero base displacement. */
1775 if (GET_CODE (x
) == PLUS
1776 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1778 address
->offset
= XEXP (x
, 1);
1782 /* Check for a suppressed index register. */
1783 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1789 /* Check for a suppressed base register. Do not allow this case
1790 for non-symbolic offsets as it effectively gives gcc freedom
1791 to treat data registers as base registers, which can generate
1794 && symbolic_operand (address
->offset
, VOIDmode
)
1795 && m68k_decompose_index (x
, strict_p
, address
))
1800 /* Check for a nonzero base displacement. */
1801 if (GET_CODE (x
) == PLUS
1802 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1803 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1805 address
->offset
= XEXP (x
, 1);
1810 /* We now expect the sum of a base and an index. */
1811 if (GET_CODE (x
) == PLUS
)
1813 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1814 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1816 address
->base
= XEXP (x
, 0);
1820 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1821 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1823 address
->base
= XEXP (x
, 1);
1830 /* Return true if X is a legitimate address for values of mode MODE.
1831 STRICT_P says whether strict checking is needed. */
1834 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1836 struct m68k_address address
;
1838 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1841 /* Return true if X is a memory, describing its address in ADDRESS if so.
1842 Apply strict checking if called during or after reload. */
1845 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1848 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1849 reload_in_progress
|| reload_completed
,
1853 /* Return true if X matches the 'Q' constraint. It must be a memory
1854 with a base address and no constant offset or index. */
1857 m68k_matches_q_p (rtx x
)
1859 struct m68k_address address
;
1861 return (m68k_legitimate_mem_p (x
, &address
)
1862 && address
.code
== UNKNOWN
1868 /* Return true if X matches the 'U' constraint. It must be a base address
1869 with a constant offset and no index. */
1872 m68k_matches_u_p (rtx x
)
1874 struct m68k_address address
;
1876 return (m68k_legitimate_mem_p (x
, &address
)
1877 && address
.code
== UNKNOWN
1883 /* Legitimize PIC addresses. If the address is already
1884 position-independent, we return ORIG. Newly generated
1885 position-independent addresses go to REG. If we need more
1886 than one register, we lose.
1888 An address is legitimized by making an indirect reference
1889 through the Global Offset Table with the name of the symbol
1892 The assembler and linker are responsible for placing the
1893 address of the symbol in the GOT. The function prologue
1894 is responsible for initializing a5 to the starting address
1897 The assembler is also responsible for translating a symbol name
1898 into a constant displacement from the start of the GOT.
1900 A quick example may make things a little clearer:
1902 When not generating PIC code to store the value 12345 into _foo
1903 we would generate the following code:
1907 When generating PIC two transformations are made. First, the compiler
1908 loads the address of foo into a register. So the first transformation makes:
1913 The code in movsi will intercept the lea instruction and call this
1914 routine which will transform the instructions into:
1916 movel a5@(_foo:w), a0
1920 That (in a nutshell) is how *all* symbol and label references are
1924 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
1929 /* First handle a simple SYMBOL_REF or LABEL_REF */
1930 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1934 pic_ref
= gen_rtx_MEM (Pmode
,
1935 gen_rtx_PLUS (Pmode
,
1936 pic_offset_table_rtx
, orig
));
1937 current_function_uses_pic_offset_table
= 1;
1938 MEM_READONLY_P (pic_ref
) = 1;
1939 emit_move_insn (reg
, pic_ref
);
1942 else if (GET_CODE (orig
) == CONST
)
1946 /* Make sure this has not already been legitimized. */
1947 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1948 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1953 /* legitimize both operands of the PLUS */
1954 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
1956 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1957 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1958 base
== reg
? 0 : reg
);
1960 if (GET_CODE (orig
) == CONST_INT
)
1961 return plus_constant (base
, INTVAL (orig
));
1962 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1963 /* Likewise, should we set special REG_NOTEs here? */
1969 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
1971 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
1973 /* Return the type of move that should be used for integer I. */
1976 const_method (HOST_WIDE_INT i
)
1983 /* The ColdFire doesn't have byte or word operations. */
1984 /* FIXME: This may not be useful for the m68060 either. */
1985 if (!TARGET_COLDFIRE
)
1987 /* if -256 < N < 256 but N is not in range for a moveq
1988 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1989 if (USE_MOVQ (i
^ 0xff))
1991 /* Likewise, try with not.w */
1992 if (USE_MOVQ (i
^ 0xffff))
1994 /* This is the only value where neg.w is useful */
1999 /* Try also with swap. */
2001 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2006 /* Try using MVZ/MVS with an immediate value to load constants. */
2007 if (i
>= 0 && i
<= 65535)
2009 if (i
>= -32768 && i
<= 32767)
2013 /* Otherwise, use move.l */
2017 /* Return the cost of moving constant I into a data register. */
2020 const_int_cost (HOST_WIDE_INT i
)
2022 switch (const_method (i
))
2025 /* Constants between -128 and 127 are cheap due to moveq. */
2033 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2043 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2048 /* Constant zero is super cheap due to clr instruction. */
2049 if (x
== const0_rtx
)
2052 *total
= const_int_cost (INTVAL (x
));
2062 /* Make 0.0 cheaper than other floating constants to
2063 encourage creating tstsf and tstdf insns. */
2064 if (outer_code
== COMPARE
2065 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2071 /* These are vaguely right for a 68020. */
2072 /* The costs for long multiply have been adjusted to work properly
2073 in synth_mult on the 68020, relative to an average of the time
2074 for add and the time for shift, taking away a little more because
2075 sometimes move insns are needed. */
2076 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2082 : TARGET_COLDFIRE ? 3 : 13)
2087 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2088 : TARGET_COLDFIRE ? 2 : 8)
2091 (TARGET_CF_HWDIV ? 11 \
2092 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2095 /* An lea costs about three times as much as a simple add. */
2096 if (GET_MODE (x
) == SImode
2097 && GET_CODE (XEXP (x
, 1)) == REG
2098 && GET_CODE (XEXP (x
, 0)) == MULT
2099 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2100 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2101 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2102 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2103 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2105 /* lea an@(dx:l:i),am */
2106 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2116 *total
= COSTS_N_INSNS(1);
2121 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2123 if (INTVAL (XEXP (x
, 1)) < 16)
2124 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2126 /* We're using clrw + swap for these cases. */
2127 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2130 *total
= COSTS_N_INSNS (10); /* Worst case. */
2133 /* A shift by a big integer takes an extra instruction. */
2134 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2135 && (INTVAL (XEXP (x
, 1)) == 16))
2137 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2140 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2141 && !(INTVAL (XEXP (x
, 1)) > 0
2142 && INTVAL (XEXP (x
, 1)) <= 8))
2144 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2150 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2151 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2152 && GET_MODE (x
) == SImode
)
2153 *total
= COSTS_N_INSNS (MULW_COST
);
2154 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2155 *total
= COSTS_N_INSNS (MULW_COST
);
2157 *total
= COSTS_N_INSNS (MULL_COST
);
2164 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2165 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2166 else if (TARGET_CF_HWDIV
)
2167 *total
= COSTS_N_INSNS (18);
2169 *total
= COSTS_N_INSNS (43); /* div.l */
2177 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2181 output_move_const_into_data_reg (rtx
*operands
)
2185 i
= INTVAL (operands
[1]);
2186 switch (const_method (i
))
2189 return "mvzw %1,%0";
2191 return "mvsw %1,%0";
2193 return "moveq %1,%0";
2196 operands
[1] = GEN_INT (i
^ 0xff);
2197 return "moveq %1,%0\n\tnot%.b %0";
2200 operands
[1] = GEN_INT (i
^ 0xffff);
2201 return "moveq %1,%0\n\tnot%.w %0";
2204 return "moveq #-128,%0\n\tneg%.w %0";
2209 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2210 return "moveq %1,%0\n\tswap %0";
2213 return "move%.l %1,%0";
2219 /* Return true if I can be handled by ISA B's mov3q instruction. */
2222 valid_mov3q_const (HOST_WIDE_INT i
)
2224 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2227 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2228 I is the value of OPERANDS[1]. */
2231 output_move_simode_const (rtx
*operands
)
2237 src
= INTVAL (operands
[1]);
2239 && (DATA_REG_P (dest
) || MEM_P (dest
))
2240 /* clr insns on 68000 read before writing. */
2241 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2242 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2244 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2245 return "mov3q%.l %1,%0";
2246 else if (src
== 0 && ADDRESS_REG_P (dest
))
2247 return "sub%.l %0,%0";
2248 else if (DATA_REG_P (dest
))
2249 return output_move_const_into_data_reg (operands
);
2250 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2252 if (valid_mov3q_const (src
))
2253 return "mov3q%.l %1,%0";
2254 return "move%.w %1,%0";
2256 else if (MEM_P (dest
)
2257 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2258 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2259 && IN_RANGE (src
, -0x8000, 0x7fff))
2261 if (valid_mov3q_const (src
))
2262 return "mov3q%.l %1,%-";
2265 return "move%.l %1,%0";
2269 output_move_simode (rtx
*operands
)
2271 if (GET_CODE (operands
[1]) == CONST_INT
)
2272 return output_move_simode_const (operands
);
2273 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2274 || GET_CODE (operands
[1]) == CONST
)
2275 && push_operand (operands
[0], SImode
))
2277 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2278 || GET_CODE (operands
[1]) == CONST
)
2279 && ADDRESS_REG_P (operands
[0]))
2280 return "lea %a1,%0";
2281 return "move%.l %1,%0";
2285 output_move_himode (rtx
*operands
)
2287 if (GET_CODE (operands
[1]) == CONST_INT
)
2289 if (operands
[1] == const0_rtx
2290 && (DATA_REG_P (operands
[0])
2291 || GET_CODE (operands
[0]) == MEM
)
2292 /* clr insns on 68000 read before writing. */
2293 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2294 || !(GET_CODE (operands
[0]) == MEM
2295 && MEM_VOLATILE_P (operands
[0]))))
2297 else if (operands
[1] == const0_rtx
2298 && ADDRESS_REG_P (operands
[0]))
2299 return "sub%.l %0,%0";
2300 else if (DATA_REG_P (operands
[0])
2301 && INTVAL (operands
[1]) < 128
2302 && INTVAL (operands
[1]) >= -128)
2303 return "moveq %1,%0";
2304 else if (INTVAL (operands
[1]) < 0x8000
2305 && INTVAL (operands
[1]) >= -0x8000)
2306 return "move%.w %1,%0";
2308 else if (CONSTANT_P (operands
[1]))
2309 return "move%.l %1,%0";
2310 /* Recognize the insn before a tablejump, one that refers
2311 to a table of offsets. Such an insn will need to refer
2312 to a label on the insn. So output one. Use the label-number
2313 of the table of offsets to generate this label. This code,
2314 and similar code below, assumes that there will be at most one
2315 reference to each table. */
2316 if (GET_CODE (operands
[1]) == MEM
2317 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2318 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2319 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2321 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2323 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2324 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2326 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2327 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2329 return "move%.w %1,%0";
2333 output_move_qimode (rtx
*operands
)
2335 /* 68k family always modifies the stack pointer by at least 2, even for
2336 byte pushes. The 5200 (ColdFire) does not do this. */
2338 /* This case is generated by pushqi1 pattern now. */
2339 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2340 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2341 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2342 && ! ADDRESS_REG_P (operands
[1])
2343 && ! TARGET_COLDFIRE
));
2345 /* clr and st insns on 68000 read before writing. */
2346 if (!ADDRESS_REG_P (operands
[0])
2347 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2348 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2350 if (operands
[1] == const0_rtx
)
2352 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2353 && GET_CODE (operands
[1]) == CONST_INT
2354 && (INTVAL (operands
[1]) & 255) == 255)
2360 if (GET_CODE (operands
[1]) == CONST_INT
2361 && DATA_REG_P (operands
[0])
2362 && INTVAL (operands
[1]) < 128
2363 && INTVAL (operands
[1]) >= -128)
2364 return "moveq %1,%0";
2365 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2366 return "sub%.l %0,%0";
2367 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2368 return "move%.l %1,%0";
2369 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2370 from address registers. */
2371 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2372 return "move%.w %1,%0";
2373 return "move%.b %1,%0";
2377 output_move_stricthi (rtx
*operands
)
2379 if (operands
[1] == const0_rtx
2380 /* clr insns on 68000 read before writing. */
2381 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2382 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2384 return "move%.w %1,%0";
2388 output_move_strictqi (rtx
*operands
)
2390 if (operands
[1] == const0_rtx
2391 /* clr insns on 68000 read before writing. */
2392 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2393 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2395 return "move%.b %1,%0";
2398 /* Return the best assembler insn template
2399 for moving operands[1] into operands[0] as a fullword. */
2402 singlemove_string (rtx
*operands
)
2404 if (GET_CODE (operands
[1]) == CONST_INT
)
2405 return output_move_simode_const (operands
);
2406 return "move%.l %1,%0";
2410 /* Output assembler code to perform a doubleword move insn
2411 with operands OPERANDS. */
2414 output_move_double (rtx
*operands
)
2418 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2423 rtx addreg0
= 0, addreg1
= 0;
2424 int dest_overlapped_low
= 0;
2425 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2430 /* First classify both operands. */
2432 if (REG_P (operands
[0]))
2434 else if (offsettable_memref_p (operands
[0]))
2436 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2438 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2440 else if (GET_CODE (operands
[0]) == MEM
)
2445 if (REG_P (operands
[1]))
2447 else if (CONSTANT_P (operands
[1]))
2449 else if (offsettable_memref_p (operands
[1]))
2451 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2453 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2455 else if (GET_CODE (operands
[1]) == MEM
)
2460 /* Check for the cases that the operand constraints are not supposed
2461 to allow to happen. Generating code for these cases is
2463 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2465 /* If one operand is decrementing and one is incrementing
2466 decrement the former register explicitly
2467 and change that operand into ordinary indexing. */
2469 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2471 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2473 output_asm_insn ("sub%.l #12,%0", operands
);
2475 output_asm_insn ("subq%.l #8,%0", operands
);
2476 if (GET_MODE (operands
[1]) == XFmode
)
2477 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2478 else if (GET_MODE (operands
[0]) == DFmode
)
2479 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2481 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2484 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2486 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2488 output_asm_insn ("sub%.l #12,%1", operands
);
2490 output_asm_insn ("subq%.l #8,%1", operands
);
2491 if (GET_MODE (operands
[1]) == XFmode
)
2492 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2493 else if (GET_MODE (operands
[1]) == DFmode
)
2494 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2496 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2500 /* If an operand is an unoffsettable memory ref, find a register
2501 we can increment temporarily to make it refer to the second word. */
2503 if (optype0
== MEMOP
)
2504 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2506 if (optype1
== MEMOP
)
2507 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2509 /* Ok, we can do one word at a time.
2510 Normally we do the low-numbered word first,
2511 but if either operand is autodecrementing then we
2512 do the high-numbered word first.
2514 In either case, set up in LATEHALF the operands to use
2515 for the high-numbered word and in some cases alter the
2516 operands in OPERANDS to be suitable for the low-numbered word. */
2520 if (optype0
== REGOP
)
2522 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2523 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2525 else if (optype0
== OFFSOP
)
2527 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2528 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2532 middlehalf
[0] = operands
[0];
2533 latehalf
[0] = operands
[0];
2536 if (optype1
== REGOP
)
2538 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2539 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2541 else if (optype1
== OFFSOP
)
2543 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2544 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2546 else if (optype1
== CNSTOP
)
2548 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2553 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2554 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2555 operands
[1] = GEN_INT (l
[0]);
2556 middlehalf
[1] = GEN_INT (l
[1]);
2557 latehalf
[1] = GEN_INT (l
[2]);
2561 /* No non-CONST_DOUBLE constant should ever appear
2563 gcc_assert (!CONSTANT_P (operands
[1]));
2568 middlehalf
[1] = operands
[1];
2569 latehalf
[1] = operands
[1];
2573 /* size is not 12: */
2575 if (optype0
== REGOP
)
2576 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2577 else if (optype0
== OFFSOP
)
2578 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2580 latehalf
[0] = operands
[0];
2582 if (optype1
== REGOP
)
2583 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2584 else if (optype1
== OFFSOP
)
2585 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2586 else if (optype1
== CNSTOP
)
2587 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2589 latehalf
[1] = operands
[1];
2592 /* If insn is effectively movd N(sp),-(sp) then we will do the
2593 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2594 for the low word as well, to compensate for the first decrement of sp. */
2595 if (optype0
== PUSHOP
2596 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2597 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2598 operands
[1] = middlehalf
[1] = latehalf
[1];
2600 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2601 if the upper part of reg N does not appear in the MEM, arrange to
2602 emit the move late-half first. Otherwise, compute the MEM address
2603 into the upper part of N and use that as a pointer to the memory
2605 if (optype0
== REGOP
2606 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2608 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2610 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2611 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2613 /* If both halves of dest are used in the src memory address,
2614 compute the address into latehalf of dest.
2615 Note that this can't happen if the dest is two data regs. */
2617 xops
[0] = latehalf
[0];
2618 xops
[1] = XEXP (operands
[1], 0);
2619 output_asm_insn ("lea %a1,%0", xops
);
2620 if (GET_MODE (operands
[1]) == XFmode
)
2622 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2623 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2624 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2628 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2629 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2633 && reg_overlap_mentioned_p (middlehalf
[0],
2634 XEXP (operands
[1], 0)))
2636 /* Check for two regs used by both source and dest.
2637 Note that this can't happen if the dest is all data regs.
2638 It can happen if the dest is d6, d7, a0.
2639 But in that case, latehalf is an addr reg, so
2640 the code at compadr does ok. */
2642 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2643 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2646 /* JRV says this can't happen: */
2647 gcc_assert (!addreg0
&& !addreg1
);
2649 /* Only the middle reg conflicts; simply put it last. */
2650 output_asm_insn (singlemove_string (operands
), operands
);
2651 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2652 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2655 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2656 /* If the low half of dest is mentioned in the source memory
2657 address, the arrange to emit the move late half first. */
2658 dest_overlapped_low
= 1;
2661 /* If one or both operands autodecrementing,
2662 do the two words, high-numbered first. */
2664 /* Likewise, the first move would clobber the source of the second one,
2665 do them in the other order. This happens only for registers;
2666 such overlap can't happen in memory unless the user explicitly
2667 sets it up, and that is an undefined circumstance. */
2669 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2670 || (optype0
== REGOP
&& optype1
== REGOP
2671 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2672 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2673 || dest_overlapped_low
)
2675 /* Make any unoffsettable addresses point at high-numbered word. */
2679 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2681 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2686 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2688 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2692 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2694 /* Undo the adds we just did. */
2696 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2698 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2702 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2704 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2706 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2709 /* Do low-numbered word. */
2710 return singlemove_string (operands
);
2713 /* Normal case: do the two words, low-numbered first. */
2715 output_asm_insn (singlemove_string (operands
), operands
);
2717 /* Do the middle one of the three words for long double */
2721 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2723 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2725 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2728 /* Make any unoffsettable addresses point at high-numbered word. */
2730 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2732 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2735 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2737 /* Undo the adds we just did. */
2741 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2743 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2748 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2750 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2757 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2758 new rtx with the correct mode. */
2761 force_mode (enum machine_mode mode
, rtx orig
)
2763 if (mode
== GET_MODE (orig
))
2766 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2769 return gen_rtx_REG (mode
, REGNO (orig
));
2773 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2775 return reg_renumber
&& FP_REG_P (op
);
2778 /* Emit insns to move operands[1] into operands[0].
2780 Return 1 if we have written out everything that needs to be done to
2781 do the move. Otherwise, return 0 and the caller will emit the move
2784 Note SCRATCH_REG may not be in the proper mode depending on how it
2785 will be used. This routine is responsible for creating a new copy
2786 of SCRATCH_REG in the proper mode. */
2789 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2791 register rtx operand0
= operands
[0];
2792 register rtx operand1
= operands
[1];
2796 && reload_in_progress
&& GET_CODE (operand0
) == REG
2797 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2798 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2799 else if (scratch_reg
2800 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2801 && GET_CODE (SUBREG_REG (operand0
)) == REG
2802 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2804 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2805 the code which tracks sets/uses for delete_output_reload. */
2806 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2807 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2808 SUBREG_BYTE (operand0
));
2809 operand0
= alter_subreg (&temp
);
2813 && reload_in_progress
&& GET_CODE (operand1
) == REG
2814 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2815 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2816 else if (scratch_reg
2817 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2818 && GET_CODE (SUBREG_REG (operand1
)) == REG
2819 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2821 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2822 the code which tracks sets/uses for delete_output_reload. */
2823 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2824 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2825 SUBREG_BYTE (operand1
));
2826 operand1
= alter_subreg (&temp
);
2829 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2830 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2831 != XEXP (operand0
, 0)))
2832 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2833 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2834 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2835 != XEXP (operand1
, 0)))
2836 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2838 /* Handle secondary reloads for loads/stores of FP registers where
2839 the address is symbolic by using the scratch register */
2840 if (fp_reg_operand (operand0
, mode
)
2841 && ((GET_CODE (operand1
) == MEM
2842 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2843 || ((GET_CODE (operand1
) == SUBREG
2844 && GET_CODE (XEXP (operand1
, 0)) == MEM
2845 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2848 if (GET_CODE (operand1
) == SUBREG
)
2849 operand1
= XEXP (operand1
, 0);
2851 /* SCRATCH_REG will hold an address. We want
2852 it in SImode regardless of what mode it was originally given
2854 scratch_reg
= force_mode (SImode
, scratch_reg
);
2856 /* D might not fit in 14 bits either; for such cases load D into
2858 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2860 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
2861 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
2863 XEXP (XEXP (operand1
, 0), 0),
2867 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
2868 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
2869 gen_rtx_MEM (mode
, scratch_reg
)));
2872 else if (fp_reg_operand (operand1
, mode
)
2873 && ((GET_CODE (operand0
) == MEM
2874 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
2875 || ((GET_CODE (operand0
) == SUBREG
)
2876 && GET_CODE (XEXP (operand0
, 0)) == MEM
2877 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
2880 if (GET_CODE (operand0
) == SUBREG
)
2881 operand0
= XEXP (operand0
, 0);
2883 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2884 it in SIMODE regardless of what mode it was originally given
2886 scratch_reg
= force_mode (SImode
, scratch_reg
);
2888 /* D might not fit in 14 bits either; for such cases load D into
2890 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
2892 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
2893 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
2896 XEXP (XEXP (operand0
, 0),
2901 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
2902 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
2906 /* Handle secondary reloads for loads of FP registers from constant
2907 expressions by forcing the constant into memory.
2909 use scratch_reg to hold the address of the memory location.
2911 The proper fix is to change PREFERRED_RELOAD_CLASS to return
2912 NO_REGS when presented with a const_int and an register class
2913 containing only FP registers. Doing so unfortunately creates
2914 more problems than it solves. Fix this for 2.5. */
2915 else if (fp_reg_operand (operand0
, mode
)
2916 && CONSTANT_P (operand1
)
2921 /* SCRATCH_REG will hold an address and maybe the actual data. We want
2922 it in SIMODE regardless of what mode it was originally given
2924 scratch_reg
= force_mode (SImode
, scratch_reg
);
2926 /* Force the constant into memory and put the address of the
2927 memory location into scratch_reg. */
2928 xoperands
[0] = scratch_reg
;
2929 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
2930 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
2932 /* Now load the destination register. */
2933 emit_insn (gen_rtx_SET (mode
, operand0
,
2934 gen_rtx_MEM (mode
, scratch_reg
)));
2938 /* Now have insn-emit do whatever it normally does. */
2942 /* Split one or more DImode RTL references into pairs of SImode
2943 references. The RTL can be REG, offsettable MEM, integer constant, or
2944 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2945 split and "num" is its length. lo_half and hi_half are output arrays
2946 that parallel "operands". */
2949 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2953 rtx op
= operands
[num
];
2955 /* simplify_subreg refuses to split volatile memory addresses,
2956 but we still have to handle it. */
2957 if (GET_CODE (op
) == MEM
)
2959 lo_half
[num
] = adjust_address (op
, SImode
, 4);
2960 hi_half
[num
] = adjust_address (op
, SImode
, 0);
2964 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2965 GET_MODE (op
) == VOIDmode
2966 ? DImode
: GET_MODE (op
), 4);
2967 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2968 GET_MODE (op
) == VOIDmode
2969 ? DImode
: GET_MODE (op
), 0);
2974 /* Split X into a base and a constant offset, storing them in *BASE
2975 and *OFFSET respectively. */
2978 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
2981 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2983 *offset
+= INTVAL (XEXP (x
, 1));
2989 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
2990 instruction. STORE_P says whether the move is a load or store.
2992 If the instruction uses post-increment or pre-decrement addressing,
2993 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
2994 adjustment. This adjustment will be made by the first element of
2995 PARALLEL, with the loads or stores starting at element 1. If the
2996 instruction does not use post-increment or pre-decrement addressing,
2997 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
2998 start at element 0. */
3001 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3002 HOST_WIDE_INT automod_offset
, bool store_p
)
3004 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3005 HOST_WIDE_INT offset
, mem_offset
;
3007 enum reg_class rclass
;
3009 len
= XVECLEN (pattern
, 0);
3010 first
= (automod_base
!= NULL
);
3014 /* Stores must be pre-decrement and loads must be post-increment. */
3015 if (store_p
!= (automod_offset
< 0))
3018 /* Work out the base and offset for lowest memory location. */
3019 base
= automod_base
;
3020 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3024 /* Allow any valid base and offset in the first access. */
3031 for (i
= first
; i
< len
; i
++)
3033 /* We need a plain SET. */
3034 set
= XVECEXP (pattern
, 0, i
);
3035 if (GET_CODE (set
) != SET
)
3038 /* Check that we have a memory location... */
3039 mem
= XEXP (set
, !store_p
);
3040 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3043 /* ...with the right address. */
3046 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3047 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3048 There are no mode restrictions for 680x0 besides the
3049 automodification rules enforced above. */
3051 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3056 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3057 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3061 /* Check that we have a register of the required mode and class. */
3062 reg
= XEXP (set
, store_p
);
3064 || !HARD_REGISTER_P (reg
)
3065 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3070 /* The register must belong to RCLASS and have a higher number
3071 than the register in the previous SET. */
3072 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3073 || REGNO (last_reg
) >= REGNO (reg
))
3078 /* Work out which register class we need. */
3079 if (INT_REGNO_P (REGNO (reg
)))
3080 rclass
= GENERAL_REGS
;
3081 else if (FP_REGNO_P (REGNO (reg
)))
3088 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3091 /* If we have an automodification, check whether the final offset is OK. */
3092 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3095 /* Reject unprofitable cases. */
3096 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3102 /* Return the assembly code template for a movem or fmovem instruction
3103 whose pattern is given by PATTERN. Store the template's operands
3106 If the instruction uses post-increment or pre-decrement addressing,
3107 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3108 is true if this is a store instruction. */
3111 m68k_output_movem (rtx
*operands
, rtx pattern
,
3112 HOST_WIDE_INT automod_offset
, bool store_p
)
3117 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3119 first
= (automod_offset
!= 0);
3120 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3122 /* When using movem with pre-decrement addressing, register X + D0_REG
3123 is controlled by bit 15 - X. For all other addressing modes,
3124 register X + D0_REG is controlled by bit X. Confusingly, the
3125 register mask for fmovem is in the opposite order to that for
3129 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3130 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3131 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3132 if (automod_offset
< 0)
3134 if (FP_REGNO_P (regno
))
3135 mask
|= 1 << (regno
- FP0_REG
);
3137 mask
|= 1 << (15 - (regno
- D0_REG
));
3141 if (FP_REGNO_P (regno
))
3142 mask
|= 1 << (7 - (regno
- FP0_REG
));
3144 mask
|= 1 << (regno
- D0_REG
);
3149 if (automod_offset
== 0)
3150 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3151 else if (automod_offset
< 0)
3152 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3154 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3155 operands
[1] = GEN_INT (mask
);
3156 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3159 return MOTOROLA
? "fmovm %1,%a0" : "fmovem %1,%a0";
3161 return MOTOROLA
? "fmovm %a0,%1" : "fmovem %a0,%1";
3166 return MOTOROLA
? "movm.l %1,%a0" : "moveml %1,%a0";
3168 return MOTOROLA
? "movm.l %a0,%1" : "moveml %a0,%1";
3172 /* Return a REG that occurs in ADDR with coefficient 1.
3173 ADDR can be effectively incremented by incrementing REG. */
3176 find_addr_reg (rtx addr
)
3178 while (GET_CODE (addr
) == PLUS
)
3180 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3181 addr
= XEXP (addr
, 0);
3182 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3183 addr
= XEXP (addr
, 1);
3184 else if (CONSTANT_P (XEXP (addr
, 0)))
3185 addr
= XEXP (addr
, 1);
3186 else if (CONSTANT_P (XEXP (addr
, 1)))
3187 addr
= XEXP (addr
, 0);
3191 gcc_assert (GET_CODE (addr
) == REG
);
3195 /* Output assembler code to perform a 32-bit 3-operand add. */
3198 output_addsi3 (rtx
*operands
)
3200 if (! operands_match_p (operands
[0], operands
[1]))
3202 if (!ADDRESS_REG_P (operands
[1]))
3204 rtx tmp
= operands
[1];
3206 operands
[1] = operands
[2];
3210 /* These insns can result from reloads to access
3211 stack slots over 64k from the frame pointer. */
3212 if (GET_CODE (operands
[2]) == CONST_INT
3213 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3214 return "move%.l %2,%0\n\tadd%.l %1,%0";
3215 if (GET_CODE (operands
[2]) == REG
)
3216 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3217 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3219 if (GET_CODE (operands
[2]) == CONST_INT
)
3221 if (INTVAL (operands
[2]) > 0
3222 && INTVAL (operands
[2]) <= 8)
3223 return "addq%.l %2,%0";
3224 if (INTVAL (operands
[2]) < 0
3225 && INTVAL (operands
[2]) >= -8)
3227 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3228 return "subq%.l %2,%0";
3230 /* On the CPU32 it is faster to use two addql instructions to
3231 add a small integer (8 < N <= 16) to a register.
3232 Likewise for subql. */
3233 if (TUNE_CPU32
&& REG_P (operands
[0]))
3235 if (INTVAL (operands
[2]) > 8
3236 && INTVAL (operands
[2]) <= 16)
3238 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3239 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3241 if (INTVAL (operands
[2]) < -8
3242 && INTVAL (operands
[2]) >= -16)
3244 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3245 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3248 if (ADDRESS_REG_P (operands
[0])
3249 && INTVAL (operands
[2]) >= -0x8000
3250 && INTVAL (operands
[2]) < 0x8000)
3253 return "add%.w %2,%0";
3255 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3258 return "add%.l %2,%0";
3261 /* Store in cc_status the expressions that the condition codes will
3262 describe after execution of an instruction whose pattern is EXP.
3263 Do not alter them if the instruction would not alter the cc's. */
3265 /* On the 68000, all the insns to store in an address register fail to
3266 set the cc's. However, in some cases these instructions can make it
3267 possibly invalid to use the saved cc's. In those cases we clear out
3268 some or all of the saved cc's so they won't be used. */
3271 notice_update_cc (rtx exp
, rtx insn
)
3273 if (GET_CODE (exp
) == SET
)
3275 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3277 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3279 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3280 cc_status
.value1
= 0;
3281 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3282 cc_status
.value2
= 0;
3284 /* fmoves to memory or data registers do not set the condition
3285 codes. Normal moves _do_ set the condition codes, but not in
3286 a way that is appropriate for comparison with 0, because -0.0
3287 would be treated as a negative nonzero number. Note that it
3288 isn't appropriate to conditionalize this restriction on
3289 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3290 we care about the difference between -0.0 and +0.0. */
3291 else if (!FP_REG_P (SET_DEST (exp
))
3292 && SET_DEST (exp
) != cc0_rtx
3293 && (FP_REG_P (SET_SRC (exp
))
3294 || GET_CODE (SET_SRC (exp
)) == FIX
3295 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3297 /* A pair of move insns doesn't produce a useful overall cc. */
3298 else if (!FP_REG_P (SET_DEST (exp
))
3299 && !FP_REG_P (SET_SRC (exp
))
3300 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3301 && (GET_CODE (SET_SRC (exp
)) == REG
3302 || GET_CODE (SET_SRC (exp
)) == MEM
3303 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3305 else if (SET_DEST (exp
) != pc_rtx
)
3307 cc_status
.flags
= 0;
3308 cc_status
.value1
= SET_DEST (exp
);
3309 cc_status
.value2
= SET_SRC (exp
);
3312 else if (GET_CODE (exp
) == PARALLEL
3313 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3315 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3316 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3318 if (ADDRESS_REG_P (dest
))
3320 else if (dest
!= pc_rtx
)
3322 cc_status
.flags
= 0;
3323 cc_status
.value1
= dest
;
3324 cc_status
.value2
= src
;
3329 if (cc_status
.value2
!= 0
3330 && ADDRESS_REG_P (cc_status
.value2
)
3331 && GET_MODE (cc_status
.value2
) == QImode
)
3333 if (cc_status
.value2
!= 0)
3334 switch (GET_CODE (cc_status
.value2
))
3336 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3337 case ROTATE
: case ROTATERT
:
3338 /* These instructions always clear the overflow bit, and set
3339 the carry to the bit shifted out. */
3340 /* ??? We don't currently have a way to signal carry not valid,
3341 nor do we check for it in the branch insns. */
3345 case PLUS
: case MINUS
: case MULT
:
3346 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3347 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3348 cc_status
.flags
|= CC_NO_OVERFLOW
;
3351 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3352 ends with a move insn moving r2 in r2's mode.
3353 Thus, the cc's are set for r2.
3354 This can set N bit spuriously. */
3355 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3360 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3362 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3363 cc_status
.value2
= 0;
3364 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3365 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3366 cc_status
.flags
= CC_IN_68881
;
3370 output_move_const_double (rtx
*operands
)
3372 int code
= standard_68881_constant_p (operands
[1]);
3376 static char buf
[40];
3378 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3381 return "fmove%.d %1,%0";
3385 output_move_const_single (rtx
*operands
)
3387 int code
= standard_68881_constant_p (operands
[1]);
3391 static char buf
[40];
3393 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3396 return "fmove%.s %f1,%0";
3399 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3400 from the "fmovecr" instruction.
3401 The value, anded with 0xff, gives the code to use in fmovecr
3402 to get the desired constant. */
3404 /* This code has been fixed for cross-compilation. */
3406 static int inited_68881_table
= 0;
3408 static const char *const strings_68881
[7] = {
3418 static const int codes_68881
[7] = {
3428 REAL_VALUE_TYPE values_68881
[7];
3430 /* Set up values_68881 array by converting the decimal values
3431 strings_68881 to binary. */
3434 init_68881_table (void)
3438 enum machine_mode mode
;
3441 for (i
= 0; i
< 7; i
++)
3445 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3446 values_68881
[i
] = r
;
3448 inited_68881_table
= 1;
3452 standard_68881_constant_p (rtx x
)
3457 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3458 used at all on those chips. */
3462 if (! inited_68881_table
)
3463 init_68881_table ();
3465 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3467 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3469 for (i
= 0; i
< 6; i
++)
3471 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3472 return (codes_68881
[i
]);
3475 if (GET_MODE (x
) == SFmode
)
3478 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3479 return (codes_68881
[6]);
3481 /* larger powers of ten in the constants ram are not used
3482 because they are not equal to a `double' C constant. */
3486 /* If X is a floating-point constant, return the logarithm of X base 2,
3487 or 0 if X is not a power of 2. */
3490 floating_exact_log2 (rtx x
)
3492 REAL_VALUE_TYPE r
, r1
;
3495 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3497 if (REAL_VALUES_LESS (r
, dconst1
))
3500 exp
= real_exponent (&r
);
3501 real_2expN (&r1
, exp
);
3502 if (REAL_VALUES_EQUAL (r1
, r
))
3508 /* A C compound statement to output to stdio stream STREAM the
3509 assembler syntax for an instruction operand X. X is an RTL
3512 CODE is a value that can be used to specify one of several ways
3513 of printing the operand. It is used when identical operands
3514 must be printed differently depending on the context. CODE
3515 comes from the `%' specification that was used to request
3516 printing of the operand. If the specification was just `%DIGIT'
3517 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3518 is the ASCII code for LTR.
3520 If X is a register, this macro should print the register's name.
3521 The names can be found in an array `reg_names' whose type is
3522 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3524 When the machine description has a specification `%PUNCT' (a `%'
3525 followed by a punctuation character), this macro is called with
3526 a null pointer for X and the punctuation character for CODE.
3528 The m68k specific codes are:
3530 '.' for dot needed in Motorola-style opcode names.
3531 '-' for an operand pushing on the stack:
3532 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3533 '+' for an operand pushing on the stack:
3534 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3535 '@' for a reference to the top word on the stack:
3536 sp@, (sp) or (%sp) depending on the style of syntax.
3537 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3538 but & in SGS syntax).
3539 '!' for the cc register (used in an `and to cc' insn).
3540 '$' for the letter `s' in an op code, but only on the 68040.
3541 '&' for the letter `d' in an op code, but only on the 68040.
3542 '/' for register prefix needed by longlong.h.
3543 '?' for m68k_library_id_string
3545 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3546 'd' to force memory addressing to be absolute, not relative.
3547 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3548 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3549 or print pair of registers as rx:ry.
3550 'p' print an address with @PLTPC attached, but only if the operand
3551 is not locally-bound. */
3554 print_operand (FILE *file
, rtx op
, int letter
)
3559 fprintf (file
, ".");
3561 else if (letter
== '#')
3562 asm_fprintf (file
, "%I");
3563 else if (letter
== '-')
3564 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3565 else if (letter
== '+')
3566 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3567 else if (letter
== '@')
3568 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3569 else if (letter
== '!')
3570 asm_fprintf (file
, "%Rfpcr");
3571 else if (letter
== '$')
3574 fprintf (file
, "s");
3576 else if (letter
== '&')
3579 fprintf (file
, "d");
3581 else if (letter
== '/')
3582 asm_fprintf (file
, "%R");
3583 else if (letter
== '?')
3584 asm_fprintf (file
, m68k_library_id_string
);
3585 else if (letter
== 'p')
3587 output_addr_const (file
, op
);
3588 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3589 fprintf (file
, "@PLTPC");
3591 else if (GET_CODE (op
) == REG
)
3594 /* Print out the second register name of a register pair.
3595 I.e., R (6) => 7. */
3596 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3598 fputs (M68K_REGNAME(REGNO (op
)), file
);
3600 else if (GET_CODE (op
) == MEM
)
3602 output_address (XEXP (op
, 0));
3603 if (letter
== 'd' && ! TARGET_68020
3604 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3605 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3606 && INTVAL (XEXP (op
, 0)) < 0x8000
3607 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3608 fprintf (file
, MOTOROLA
? ".l" : ":l");
3610 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3613 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3614 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3616 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3619 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3620 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3622 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3625 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3626 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3630 /* Use `print_operand_address' instead of `output_addr_const'
3631 to ensure that we print relevant PIC stuff. */
3632 asm_fprintf (file
, "%I");
3634 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3635 print_operand_address (file
, op
);
3637 output_addr_const (file
, op
);
3642 /* A C compound statement to output to stdio stream STREAM the
3643 assembler syntax for an instruction operand that is a memory
3644 reference whose address is ADDR. ADDR is an RTL expression.
3646 Note that this contains a kludge that knows that the only reason
3647 we have an address (plus (label_ref...) (reg...)) when not generating
3648 PIC code is in the insn before a tablejump, and we know that m68k.md
3649 generates a label LInnn: on such an insn.
3651 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3652 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3654 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3655 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3656 we want. This difference can be accommodated by using an assembler
3657 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3658 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3659 macro. See m68k/sgs.h for an example; for versions without the bug.
3660 Some assemblers refuse all the above solutions. The workaround is to
3661 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3664 They also do not like things like "pea 1.w", so we simple leave off
3665 the .w on small constants.
3667 This routine is responsible for distinguishing between -fpic and -fPIC
3668 style relocations in an address. When generating -fpic code the
3669 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3670 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3673 print_operand_address (FILE *file
, rtx addr
)
3675 struct m68k_address address
;
3677 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3680 if (address
.code
== PRE_DEC
)
3681 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3682 M68K_REGNAME (REGNO (address
.base
)));
3683 else if (address
.code
== POST_INC
)
3684 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3685 M68K_REGNAME (REGNO (address
.base
)));
3686 else if (!address
.base
&& !address
.index
)
3688 /* A constant address. */
3689 gcc_assert (address
.offset
== addr
);
3690 if (GET_CODE (addr
) == CONST_INT
)
3692 /* (xxx).w or (xxx).l. */
3693 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3694 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3696 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3698 else if (TARGET_PCREL
)
3700 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3702 output_addr_const (file
, addr
);
3703 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3707 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3708 name ends in `.<letter>', as the last 2 characters can be
3709 mistaken as a size suffix. Put the name in parentheses. */
3710 if (GET_CODE (addr
) == SYMBOL_REF
3711 && strlen (XSTR (addr
, 0)) > 2
3712 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3715 output_addr_const (file
, addr
);
3719 output_addr_const (file
, addr
);
3726 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3727 label being acceesed, otherwise it is -1. */
3728 labelno
= (address
.offset
3730 && GET_CODE (address
.offset
) == LABEL_REF
3731 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3735 /* Print the "offset(base" component. */
3737 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3742 output_addr_const (file
, address
.offset
);
3743 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3745 fprintf (file
, "@GOT");
3746 if (flag_pic
== 1 && TARGET_68020
)
3747 fprintf (file
, ".w");
3752 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3754 /* Print the ",index" component, if any. */
3759 fprintf (file
, "%s.%c",
3760 M68K_REGNAME (REGNO (address
.index
)),
3761 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3762 if (address
.scale
!= 1)
3763 fprintf (file
, "*%d", address
.scale
);
3767 else /* !MOTOROLA */
3769 if (!address
.offset
&& !address
.index
)
3770 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3773 /* Print the "base@(offset" component. */
3775 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3779 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3780 fprintf (file
, "@(");
3783 output_addr_const (file
, address
.offset
);
3784 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3788 fprintf (file
, ":w"); break;
3790 fprintf (file
, ":l"); break;
3796 /* Print the ",index" component, if any. */
3799 fprintf (file
, ",%s:%c",
3800 M68K_REGNAME (REGNO (address
.index
)),
3801 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3802 if (address
.scale
!= 1)
3803 fprintf (file
, ":%d", address
.scale
);
3811 /* Check for cases where a clr insns can be omitted from code using
3812 strict_low_part sets. For example, the second clrl here is not needed:
3813 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3815 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3816 insn we are checking for redundancy. TARGET is the register set by the
3820 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3825 p
= prev_nonnote_insn (first_insn
);
3829 /* If it isn't an insn, then give up. */
3830 if (GET_CODE (p
) != INSN
)
3833 if (reg_set_p (target
, p
))
3835 rtx set
= single_set (p
);
3838 /* If it isn't an easy to recognize insn, then give up. */
3842 dest
= SET_DEST (set
);
3844 /* If this sets the entire target register to zero, then our
3845 first_insn is redundant. */
3846 if (rtx_equal_p (dest
, target
)
3847 && SET_SRC (set
) == const0_rtx
)
3849 else if (GET_CODE (dest
) == STRICT_LOW_PART
3850 && GET_CODE (XEXP (dest
, 0)) == REG
3851 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3852 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3853 <= GET_MODE_SIZE (mode
)))
3854 /* This is a strict low part set which modifies less than
3855 we are using, so it is safe. */
3861 p
= prev_nonnote_insn (p
);
3867 /* Operand predicates for implementing asymmetric pc-relative addressing
3868 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3869 when used as a source operand, but not as a destination operand.
3871 We model this by restricting the meaning of the basic predicates
3872 (general_operand, memory_operand, etc) to forbid the use of this
3873 addressing mode, and then define the following predicates that permit
3874 this addressing mode. These predicates can then be used for the
3875 source operands of the appropriate instructions.
3877 n.b. While it is theoretically possible to change all machine patterns
3878 to use this addressing more where permitted by the architecture,
3879 it has only been implemented for "common" cases: SImode, HImode, and
3880 QImode operands, and only for the principle operations that would
3881 require this addressing mode: data movement and simple integer operations.
3883 In parallel with these new predicates, two new constraint letters
3884 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3885 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3886 In the pcrel case 's' is only valid in combination with 'a' registers.
3887 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3888 of how these constraints are used.
3890 The use of these predicates is strictly optional, though patterns that
3891 don't will cause an extra reload register to be allocated where one
3894 lea (abc:w,%pc),%a0 ; need to reload address
3895 moveq &1,%d1 ; since write to pc-relative space
3896 movel %d1,%a0@ ; is not allowed
3898 lea (abc:w,%pc),%a1 ; no need to reload address here
3899 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3901 For more info, consult tiemann@cygnus.com.
3904 All of the ugliness with predicates and constraints is due to the
3905 simple fact that the m68k does not allow a pc-relative addressing
3906 mode as a destination. gcc does not distinguish between source and
3907 destination addresses. Hence, if we claim that pc-relative address
3908 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3909 end up with invalid code. To get around this problem, we left
3910 pc-relative modes as invalid addresses, and then added special
3911 predicates and constraints to accept them.
3913 A cleaner way to handle this is to modify gcc to distinguish
3914 between source and destination addresses. We can then say that
3915 pc-relative is a valid source address but not a valid destination
3916 address, and hopefully avoid a lot of the predicate and constraint
3917 hackery. Unfortunately, this would be a pretty big change. It would
3918 be a useful change for a number of ports, but there aren't any current
3919 plans to undertake this.
3921 ***************************************************************************/
3925 output_andsi3 (rtx
*operands
)
3928 if (GET_CODE (operands
[2]) == CONST_INT
3929 && (INTVAL (operands
[2]) | 0xffff) == -1
3930 && (DATA_REG_P (operands
[0])
3931 || offsettable_memref_p (operands
[0]))
3932 && !TARGET_COLDFIRE
)
3934 if (GET_CODE (operands
[0]) != REG
)
3935 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3936 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3937 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3939 if (operands
[2] == const0_rtx
)
3941 return "and%.w %2,%0";
3943 if (GET_CODE (operands
[2]) == CONST_INT
3944 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3945 && (DATA_REG_P (operands
[0])
3946 || offsettable_memref_p (operands
[0])))
3948 if (DATA_REG_P (operands
[0]))
3949 operands
[1] = GEN_INT (logval
);
3952 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3953 operands
[1] = GEN_INT (logval
% 8);
3955 /* This does not set condition codes in a standard way. */
3957 return "bclr %1,%0";
3959 return "and%.l %2,%0";
3963 output_iorsi3 (rtx
*operands
)
3965 register int logval
;
3966 if (GET_CODE (operands
[2]) == CONST_INT
3967 && INTVAL (operands
[2]) >> 16 == 0
3968 && (DATA_REG_P (operands
[0])
3969 || offsettable_memref_p (operands
[0]))
3970 && !TARGET_COLDFIRE
)
3972 if (GET_CODE (operands
[0]) != REG
)
3973 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3974 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3976 if (INTVAL (operands
[2]) == 0xffff)
3977 return "mov%.w %2,%0";
3978 return "or%.w %2,%0";
3980 if (GET_CODE (operands
[2]) == CONST_INT
3981 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3982 && (DATA_REG_P (operands
[0])
3983 || offsettable_memref_p (operands
[0])))
3985 if (DATA_REG_P (operands
[0]))
3986 operands
[1] = GEN_INT (logval
);
3989 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3990 operands
[1] = GEN_INT (logval
% 8);
3993 return "bset %1,%0";
3995 return "or%.l %2,%0";
3999 output_xorsi3 (rtx
*operands
)
4001 register int logval
;
4002 if (GET_CODE (operands
[2]) == CONST_INT
4003 && INTVAL (operands
[2]) >> 16 == 0
4004 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4005 && !TARGET_COLDFIRE
)
4007 if (! DATA_REG_P (operands
[0]))
4008 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4009 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4011 if (INTVAL (operands
[2]) == 0xffff)
4013 return "eor%.w %2,%0";
4015 if (GET_CODE (operands
[2]) == CONST_INT
4016 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
4017 && (DATA_REG_P (operands
[0])
4018 || offsettable_memref_p (operands
[0])))
4020 if (DATA_REG_P (operands
[0]))
4021 operands
[1] = GEN_INT (logval
);
4024 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4025 operands
[1] = GEN_INT (logval
% 8);
4028 return "bchg %1,%0";
4030 return "eor%.l %2,%0";
4033 /* Return the instruction that should be used for a call to address X,
4034 which is known to be in operand 0. */
4039 if (symbolic_operand (x
, VOIDmode
))
4040 return m68k_symbolic_call
;
4045 /* Likewise sibling calls. */
4048 output_sibcall (rtx x
)
4050 if (symbolic_operand (x
, VOIDmode
))
4051 return m68k_symbolic_jump
;
4056 #ifdef M68K_TARGET_COFF
4058 /* Output assembly to switch to section NAME with attribute FLAGS. */
4061 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
4062 tree decl ATTRIBUTE_UNUSED
)
4066 if (flags
& SECTION_WRITE
)
4071 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4074 #endif /* M68K_TARGET_COFF */
4077 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4078 HOST_WIDE_INT delta
,
4079 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
4085 if (delta
> 0 && delta
<= 8)
4086 asm_fprintf (file
, (MOTOROLA
4087 ? "\taddq.l %I%d,4(%Rsp)\n"
4088 : "\taddql %I%d,%Rsp@(4)\n"),
4090 else if (delta
< 0 && delta
>= -8)
4091 asm_fprintf (file
, (MOTOROLA
4092 ? "\tsubq.l %I%d,4(%Rsp)\n"
4093 : "\tsubql %I%d,%Rsp@(4)\n"),
4095 else if (TARGET_COLDFIRE
)
4097 /* ColdFire can't add/sub a constant to memory unless it is in
4098 the range of addq/subq. So load the value into %d0 and
4099 then add it to 4(%sp). */
4100 if (delta
>= -128 && delta
<= 127)
4101 asm_fprintf (file
, (MOTOROLA
4102 ? "\tmoveq.l %I%wd,%Rd0\n"
4103 : "\tmoveql %I%wd,%Rd0\n"),
4106 asm_fprintf (file
, (MOTOROLA
4107 ? "\tmove.l %I%wd,%Rd0\n"
4108 : "\tmovel %I%wd,%Rd0\n"),
4110 asm_fprintf (file
, (MOTOROLA
4111 ? "\tadd.l %Rd0,4(%Rsp)\n"
4112 : "\taddl %Rd0,%Rsp@(4)\n"));
4115 asm_fprintf (file
, (MOTOROLA
4116 ? "\tadd.l %I%wd,4(%Rsp)\n"
4117 : "\taddl %I%wd,%Rsp@(4)\n"),
4120 xops
[0] = DECL_RTL (function
);
4122 gcc_assert (MEM_P (xops
[0])
4123 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
4124 xops
[0] = XEXP (xops
[0], 0);
4126 fmt
= m68k_symbolic_jump
;
4127 if (m68k_symbolic_jump
== NULL
)
4128 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
4130 output_asm_insn (fmt
, xops
);
4133 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4136 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4137 int incoming ATTRIBUTE_UNUSED
)
4139 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4142 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4144 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4145 unsigned int new_reg
)
4148 /* Interrupt functions can only use registers that have already been
4149 saved by the prologue, even if they would normally be
4152 if (m68k_interrupt_function_p (current_function_decl
)
4153 && !regs_ever_live
[new_reg
])
4159 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
4160 On the 68000, the cpu registers can hold any mode except bytes in address
4161 registers, but the 68881 registers can hold only SFmode or DFmode. */
4163 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4165 if (DATA_REGNO_P (regno
))
4167 /* Data Registers, can hold aggregate if fits in. */
4168 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4171 else if (ADDRESS_REGNO_P (regno
))
4173 /* Address Registers, can't hold bytes, can hold aggregate if
4175 if (GET_MODE_SIZE (mode
) == 1)
4177 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4180 else if (FP_REGNO_P (regno
))
4182 /* FPU registers, hold float or complex float of long double or
4184 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4185 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4186 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4192 /* Return floating point values in a 68881 register. This makes 68881 code
4193 a little bit faster. It also makes -msoft-float code incompatible with
4194 hard-float code, so people have to be careful not to mix the two.
4195 For ColdFire it was decided the ABI incompatibility is undesirable.
4196 If there is need for a hard-float ABI it is probably worth doing it
4197 properly and also passing function arguments in FP registers. */
4199 m68k_libcall_value (enum machine_mode mode
)
4206 return gen_rtx_REG (mode
, 16);
4211 return gen_rtx_REG (mode
, 0);
4215 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4217 enum machine_mode mode
;
4219 mode
= TYPE_MODE (valtype
);
4225 return gen_rtx_REG (mode
, 16);
4231 /* If the function returns a pointer, push that into %a0. */
4232 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4233 /* For compatibility with the large body of existing code which
4234 does not always properly declare external functions returning
4235 pointer types, the m68k/SVR4 convention is to copy the value
4236 returned for pointer functions from a0 to d0 in the function
4237 epilogue, so that callers that have neglected to properly
4238 declare the callee can still find the correct return value in
4240 return gen_rtx_PARALLEL
4243 gen_rtx_EXPR_LIST (VOIDmode
,
4244 gen_rtx_REG (mode
, A0_REG
),
4246 gen_rtx_EXPR_LIST (VOIDmode
,
4247 gen_rtx_REG (mode
, D0_REG
),
4249 else if (POINTER_TYPE_P (valtype
))
4250 return gen_rtx_REG (mode
, A0_REG
);
4252 return gen_rtx_REG (mode
, D0_REG
);