1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "target-def.h"
47 enum reg_class regno_reg_class
[] =
49 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
50 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
51 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
52 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
53 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
54 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 /* The ASM_DOT macro allows easy string pasting to handle the differences
60 between MOTOROLA and MIT syntaxes in asm_fprintf(), which doesn't
61 support the %. option. */
64 # define ASM_DOTW ".w"
65 # define ASM_DOTL ".l"
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
88 unsigned int reg_rev_mask
;
92 unsigned int fpu_mask
;
93 unsigned int fpu_rev_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 /* Structure describing an m68k address.
108 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
109 with null fields evaluating to 0. Here:
111 - BASE satisfies m68k_legitimate_base_reg_p
112 - INDEX satisfies m68k_legitimate_index_reg_p
113 - OFFSET satisfies m68k_legitimate_constant_address_p
115 INDEX is either HImode or SImode. The other fields are SImode.
117 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
118 the address is (BASE)+. */
119 struct m68k_address
{
127 static bool m68k_handle_option (size_t, const char *, int);
128 static rtx
find_addr_reg (rtx
);
129 static const char *singlemove_string (rtx
*);
130 static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT
);
131 static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT
);
132 #ifdef M68K_TARGET_COFF
133 static void m68k_coff_asm_named_section (const char *, unsigned int, tree
);
134 #endif /* M68K_TARGET_COFF */
135 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
136 HOST_WIDE_INT
, tree
);
137 static rtx
m68k_struct_value_rtx (tree
, int);
138 static bool m68k_interrupt_function_p (tree func
);
139 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
140 tree args
, int flags
,
142 static void m68k_compute_frame_layout (void);
143 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
144 static bool m68k_rtx_costs (rtx
, int, int, int *);
147 /* Specify the identification number of the library being built */
148 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
150 /* Nonzero if the last compare/test insn had FP operands. The
151 sCC expanders peek at this to determine what to do for the
152 68060, which has no fsCC instructions. */
153 int m68k_last_compare_had_fp_operands
;
155 /* Initialize the GCC target structure. */
157 #if INT_OP_GROUP == INT_OP_DOT_WORD
158 #undef TARGET_ASM_ALIGNED_HI_OP
159 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
162 #if INT_OP_GROUP == INT_OP_NO_DOT
163 #undef TARGET_ASM_BYTE_OP
164 #define TARGET_ASM_BYTE_OP "\tbyte\t"
165 #undef TARGET_ASM_ALIGNED_HI_OP
166 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
167 #undef TARGET_ASM_ALIGNED_SI_OP
168 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
171 #if INT_OP_GROUP == INT_OP_DC
172 #undef TARGET_ASM_BYTE_OP
173 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
180 #undef TARGET_ASM_UNALIGNED_HI_OP
181 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
182 #undef TARGET_ASM_UNALIGNED_SI_OP
183 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
185 #undef TARGET_ASM_FUNCTION_PROLOGUE
186 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
190 #undef TARGET_ASM_OUTPUT_MI_THUNK
191 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
192 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
193 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
195 #undef TARGET_ASM_FILE_START_APP_OFF
196 #define TARGET_ASM_FILE_START_APP_OFF true
198 #undef TARGET_DEFAULT_TARGET_FLAGS
199 #define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT
200 #undef TARGET_HANDLE_OPTION
201 #define TARGET_HANDLE_OPTION m68k_handle_option
203 #undef TARGET_RTX_COSTS
204 #define TARGET_RTX_COSTS m68k_rtx_costs
206 #undef TARGET_ATTRIBUTE_TABLE
207 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
209 #undef TARGET_PROMOTE_PROTOTYPES
210 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
212 #undef TARGET_STRUCT_VALUE_RTX
213 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
215 #undef TARGET_CANNOT_FORCE_CONST_MEM
216 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
218 static const struct attribute_spec m68k_attribute_table
[] =
220 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
221 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute
},
222 { NULL
, 0, 0, false, false, false, NULL
}
225 struct gcc_target targetm
= TARGET_INITIALIZER
;
227 /* Base flags for 68k ISAs. */
228 #define FL_FOR_isa_00 FL_ISA_68000
229 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
230 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
231 generated 68881 code for 68020 and 68030 targets unless explicitly told
233 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
234 | FL_BITFIELD | FL_68881)
235 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
236 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
238 /* Base flags for ColdFire ISAs. */
239 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
240 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
241 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
242 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
243 #define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP)
247 /* Traditional 68000 instruction sets. */
253 /* ColdFire instruction set variants. */
261 /* Information about one of the -march, -mcpu or -mtune arguments. */
262 struct m68k_target_selection
264 /* The argument being described. */
267 /* For -mcpu, this is the device selected by the option.
268 For -mtune and -march, it is a representative device
269 for the microarchitecture or ISA respectively. */
270 enum target_device device
;
272 /* The M68K_DEVICE fields associated with DEVICE. See the comment
273 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
275 enum uarch_type microarch
;
280 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
281 static const struct m68k_target_selection all_devices
[] =
283 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
284 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
285 #include "m68k-devices.def"
287 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
290 /* A list of all ISAs, mapping each one to a representative device.
291 Used for -march selection. */
292 static const struct m68k_target_selection all_isas
[] =
294 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
295 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
296 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
297 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
298 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
299 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
300 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
301 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
303 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
305 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
306 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
309 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
312 /* A list of all microarchitectures, mapping each one to a representative
313 device. Used for -mtune selection. */
314 static const struct m68k_target_selection all_microarchs
[] =
316 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
317 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
318 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
319 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
320 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
321 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
322 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
323 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
324 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
325 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
326 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
328 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
329 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
333 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
336 /* The entries associated with the -mcpu, -march and -mtune settings,
337 or null for options that have not been used. */
338 const struct m68k_target_selection
*m68k_cpu_entry
;
339 const struct m68k_target_selection
*m68k_arch_entry
;
340 const struct m68k_target_selection
*m68k_tune_entry
;
342 /* Which CPU we are generating code for. */
343 enum target_device m68k_cpu
;
345 /* Which microarchitecture to tune for. */
346 enum uarch_type m68k_tune
;
348 /* Which FPU to use. */
349 enum fpu_type m68k_fpu
;
351 /* The set of FL_* flags that apply to the target processor. */
352 unsigned int m68k_cpu_flags
;
354 /* Asm templates for calling or jumping to an arbitrary symbolic address,
355 or NULL if such calls or jumps are not supported. The address is held
357 const char *m68k_symbolic_call
;
358 const char *m68k_symbolic_jump
;
360 /* See whether TABLE has an entry with name NAME. Return true and
361 store the entry in *ENTRY if so, otherwise return false and
362 leave *ENTRY alone. */
365 m68k_find_selection (const struct m68k_target_selection
**entry
,
366 const struct m68k_target_selection
*table
,
371 for (i
= 0; table
[i
].name
; i
++)
372 if (strcmp (table
[i
].name
, name
) == 0)
380 /* Implement TARGET_HANDLE_OPTION. */
383 m68k_handle_option (size_t code
, const char *arg
, int value
)
388 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
391 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
394 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
397 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206");
400 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5206e");
403 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "528x");
406 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5307");
409 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "5407");
412 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "547x");
416 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68000");
419 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68010");
423 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020");
426 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
428 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
431 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
433 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
436 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68030");
439 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68040");
442 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68060");
445 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68302");
449 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68332");
451 case OPT_mshared_library_id_
:
452 if (value
> MAX_LIBRARY_ID
)
453 error ("-mshared-library-id=%s is not between 0 and %d",
454 arg
, MAX_LIBRARY_ID
);
456 asprintf ((char **) &m68k_library_id_string
, "%d", (value
* -4) - 4);
464 /* Sometimes certain combinations of command options do not make
465 sense on a particular target machine. You can define a macro
466 `OVERRIDE_OPTIONS' to take account of this. This macro, if
467 defined, is executed once just after all the command options have
470 Don't use this macro to turn on various extra optimizations for
471 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
474 override_options (void)
476 const struct m68k_target_selection
*entry
;
477 unsigned long target_mask
;
485 -march=ARCH should generate code that runs any processor
486 implementing architecture ARCH. -mcpu=CPU should override -march
487 and should generate code that runs on processor CPU, making free
488 use of any instructions that CPU understands. -mtune=UARCH applies
489 on top of -mcpu or -march and optimizes the code for UARCH. It does
490 not change the target architecture. */
493 /* Complain if the -march setting is for a different microarchitecture,
494 or includes flags that the -mcpu setting doesn't. */
496 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
497 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
498 warning (0, "-mcpu=%s conflicts with -march=%s",
499 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
501 entry
= m68k_cpu_entry
;
504 entry
= m68k_arch_entry
;
507 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
509 m68k_cpu_flags
= entry
->flags
;
511 /* Use the architecture setting to derive default values for
514 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
515 target_mask
|= MASK_BITFIELD
;
516 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
517 target_mask
|= MASK_CF_HWDIV
;
518 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
519 target_mask
|= MASK_HARD_FLOAT
;
520 target_flags
|= target_mask
& ~target_flags_explicit
;
522 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
523 m68k_cpu
= entry
->device
;
525 m68k_tune
= m68k_tune_entry
->microarch
;
526 #ifdef M68K_DEFAULT_TUNE
527 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
528 m68k_tune
= M68K_DEFAULT_TUNE
;
531 m68k_tune
= entry
->microarch
;
533 /* Set the type of FPU. */
534 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
535 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
538 if (TARGET_COLDFIRE_FPU
)
540 REAL_MODE_FORMAT (SFmode
) = &coldfire_single_format
;
541 REAL_MODE_FORMAT (DFmode
) = &coldfire_double_format
;
544 /* Sanity check to ensure that msep-data and mid-sahred-library are not
545 * both specified together. Doing so simply doesn't make sense.
547 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
548 error ("cannot specify both -msep-data and -mid-shared-library");
550 /* If we're generating code for a separate A5 relative data segment,
551 * we've got to enable -fPIC as well. This might be relaxable to
552 * -fpic but it hasn't been tested properly.
554 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
557 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
558 error if the target does not support them. */
559 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
560 error ("-mpcrel -fPIC is not currently supported on selected cpu");
562 /* ??? A historic way of turning on pic, or is this intended to
563 be an embedded thing that doesn't have the same name binding
564 significance that it does on hosted ELF systems? */
565 if (TARGET_PCREL
&& flag_pic
== 0)
570 #if MOTOROLA && !defined (USE_GAS)
571 m68k_symbolic_call
= "jsr %a0";
572 m68k_symbolic_jump
= "jmp %a0";
574 m68k_symbolic_call
= "jbsr %a0";
575 m68k_symbolic_jump
= "jra %a0";
578 else if (TARGET_ID_SHARED_LIBRARY
)
579 /* All addresses must be loaded from the GOT. */
581 else if (TARGET_68020
|| TARGET_ISAB
)
585 m68k_symbolic_call
= "bsr.l %c0";
586 m68k_symbolic_jump
= "bra.l %c0";
591 m68k_symbolic_call
= "bsr.l %p0";
592 m68k_symbolic_jump
= "bra.l %p0";
594 m68k_symbolic_call
= "bsr %p0";
595 m68k_symbolic_jump
= "bra %p0";
598 /* Turn off function cse if we are doing PIC. We always want
599 function call to be done as `bsr foo@PLTPC'. */
600 /* ??? It's traditional to do this for -mpcrel too, but it isn't
601 clear how intentional that is. */
602 flag_no_function_cse
= 1;
605 SUBTARGET_OVERRIDE_OPTIONS
;
608 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
609 given argument and NAME is the argument passed to -mcpu. Return NULL
610 if -mcpu was not passed. */
613 m68k_cpp_cpu_ident (const char *prefix
)
617 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
620 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
621 given argument and NAME is the name of the representative device for
622 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
625 m68k_cpp_cpu_family (const char *prefix
)
629 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
632 /* Return nonzero if FUNC is an interrupt function as specified by the
633 "interrupt_handler" attribute. */
635 m68k_interrupt_function_p(tree func
)
639 if (TREE_CODE (func
) != FUNCTION_DECL
)
642 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
643 return (a
!= NULL_TREE
);
646 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
647 struct attribute_spec.handler. */
649 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
650 tree args ATTRIBUTE_UNUSED
,
651 int flags ATTRIBUTE_UNUSED
,
654 if (TREE_CODE (*node
) != FUNCTION_DECL
)
656 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
657 IDENTIFIER_POINTER (name
));
658 *no_add_attrs
= true;
665 m68k_compute_frame_layout (void)
668 unsigned int mask
, rmask
;
669 bool interrupt_handler
= m68k_interrupt_function_p (current_function_decl
);
671 /* Only compute the frame once per function.
672 Don't cache information until reload has been completed. */
673 if (current_frame
.funcdef_no
== current_function_funcdef_no
677 current_frame
.size
= (get_frame_size () + 3) & -4;
679 mask
= rmask
= saved
= 0;
680 for (regno
= 0; regno
< 16; regno
++)
681 if (m68k_save_reg (regno
, interrupt_handler
))
684 rmask
|= 1 << (15 - regno
);
687 current_frame
.offset
= saved
* 4;
688 current_frame
.reg_no
= saved
;
689 current_frame
.reg_mask
= mask
;
690 current_frame
.reg_rev_mask
= rmask
;
692 current_frame
.foffset
= 0;
693 mask
= rmask
= saved
= 0;
694 if (TARGET_HARD_FLOAT
)
696 for (regno
= 16; regno
< 24; regno
++)
697 if (m68k_save_reg (regno
, interrupt_handler
))
699 mask
|= 1 << (regno
- 16);
700 rmask
|= 1 << (23 - regno
);
703 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
704 current_frame
.offset
+= current_frame
.foffset
;
706 current_frame
.fpu_no
= saved
;
707 current_frame
.fpu_mask
= mask
;
708 current_frame
.fpu_rev_mask
= rmask
;
710 /* Remember what function this frame refers to. */
711 current_frame
.funcdef_no
= current_function_funcdef_no
;
715 m68k_initial_elimination_offset (int from
, int to
)
718 /* The arg pointer points 8 bytes before the start of the arguments,
719 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
720 frame pointer in most frames. */
721 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
722 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
723 return argptr_offset
;
725 m68k_compute_frame_layout ();
727 gcc_assert (to
== STACK_POINTER_REGNUM
);
730 case ARG_POINTER_REGNUM
:
731 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
732 case FRAME_POINTER_REGNUM
:
733 return current_frame
.offset
+ current_frame
.size
;
739 /* Refer to the array `regs_ever_live' to determine which registers
740 to save; `regs_ever_live[I]' is nonzero if register number I
741 is ever used in the function. This function is responsible for
742 knowing which registers should not be saved even if used.
743 Return true if we need to save REGNO. */
746 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
748 if (flag_pic
&& regno
== PIC_OFFSET_TABLE_REGNUM
)
750 if (current_function_uses_pic_offset_table
)
752 if (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)
756 if (current_function_calls_eh_return
)
761 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
762 if (test
== INVALID_REGNUM
)
769 /* Fixed regs we never touch. */
770 if (fixed_regs
[regno
])
773 /* The frame pointer (if it is such) is handled specially. */
774 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
777 /* Interrupt handlers must also save call_used_regs
778 if they are live or when calling nested functions. */
779 if (interrupt_handler
)
781 if (regs_ever_live
[regno
])
784 if (!current_function_is_leaf
&& call_used_regs
[regno
])
788 /* Never need to save registers that aren't touched. */
789 if (!regs_ever_live
[regno
])
792 /* Otherwise save everything that isn't call-clobbered. */
793 return !call_used_regs
[regno
];
796 /* This function generates the assembly code for function entry.
797 STREAM is a stdio stream to output the code to.
798 SIZE is an int: how many units of temporary storage to allocate. */
801 m68k_output_function_prologue (FILE *stream
,
802 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
804 HOST_WIDE_INT fsize_with_regs
;
805 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
807 m68k_compute_frame_layout();
809 /* If the stack limit is a symbol, we can check it here,
810 before actually allocating the space. */
811 if (current_function_limit_stack
812 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
813 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %I%s+%wd,%Rsp\n\ttrapcs\n",
814 XSTR (stack_limit_rtx
, 0), current_frame
.size
+ 4);
816 /* On ColdFire add register save into initial stack frame setup, if possible. */
817 fsize_with_regs
= current_frame
.size
;
820 if (current_frame
.reg_no
> 2)
821 fsize_with_regs
+= current_frame
.reg_no
* 4;
822 if (current_frame
.fpu_no
)
823 fsize_with_regs
+= current_frame
.fpu_no
* 8;
826 if (frame_pointer_needed
)
828 if (current_frame
.size
== 0 && TUNE_68040
)
829 /* on the 68040, pea + move is faster than link.w 0 */
830 fprintf (stream
, (MOTOROLA
831 ? "\tpea (%s)\n\tmove.l %s,%s\n"
832 : "\tpea %s@\n\tmovel %s,%s\n"),
833 M68K_REGNAME (FRAME_POINTER_REGNUM
),
834 M68K_REGNAME (STACK_POINTER_REGNUM
),
835 M68K_REGNAME (FRAME_POINTER_REGNUM
));
836 else if (fsize_with_regs
< 0x8000)
837 asm_fprintf (stream
, "\tlink" ASM_DOTW
" %s,%I%wd\n",
838 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
839 else if (TARGET_68020
)
840 asm_fprintf (stream
, "\tlink" ASM_DOTL
" %s,%I%wd\n",
841 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
843 /* Adding negative number is faster on the 68040. */
845 "\tlink" ASM_DOTW
" %s,%I0\n"
846 "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
847 M68K_REGNAME (FRAME_POINTER_REGNUM
), -fsize_with_regs
);
849 else if (fsize_with_regs
) /* !frame_pointer_needed */
851 if (fsize_with_regs
< 0x8000)
853 if (fsize_with_regs
<= 8)
855 if (!TARGET_COLDFIRE
)
856 asm_fprintf (stream
, "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
859 asm_fprintf (stream
, "\tsubq" ASM_DOT
"l %I%wd,%Rsp\n",
862 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
863 /* On the CPU32 it is faster to use two subqw instructions to
864 subtract a small integer (8 < N <= 16) to a register. */
866 "\tsubq" ASM_DOT
"w %I8,%Rsp\n"
867 "\tsubq" ASM_DOT
"w %I%wd,%Rsp\n",
868 fsize_with_regs
- 8);
870 /* Adding negative number is faster on the 68040. */
871 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
874 asm_fprintf (stream
, (MOTOROLA
875 ? "\tlea (%wd,%Rsp),%Rsp\n"
876 : "\tlea %Rsp@(%wd),%Rsp\n"),
879 else /* fsize_with_regs >= 0x8000 */
880 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n",
882 } /* !frame_pointer_needed */
884 if (dwarf2out_do_frame ())
886 if (frame_pointer_needed
)
889 l
= (char *) dwarf2out_cfi_label ();
891 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_offset
);
892 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
893 cfa_offset
+= current_frame
.size
;
897 cfa_offset
+= current_frame
.size
;
898 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
902 if (current_frame
.fpu_mask
)
906 asm_fprintf (stream
, (MOTOROLA
907 ? "\tfmovm %I0x%x,-(%Rsp)\n"
908 : "\tfmovem %I0x%x,%Rsp@-\n"),
909 current_frame
.fpu_mask
);
915 /* stack already has registers in it. Find the offset from
916 the bottom of stack to where the FP registers go */
917 if (current_frame
.reg_no
<= 2)
920 offset
= current_frame
.reg_no
* 4;
923 "\tfmovem %I0x%x,%d(%Rsp)\n",
924 current_frame
.fpu_rev_mask
,
928 "\tfmovem %I0x%x,(%Rsp)\n",
929 current_frame
.fpu_rev_mask
);
932 if (dwarf2out_do_frame ())
934 char *l
= (char *) dwarf2out_cfi_label ();
937 cfa_offset
+= current_frame
.fpu_no
* TARGET_FP_REG_SIZE
;
938 if (! frame_pointer_needed
)
939 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
940 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
941 if (current_frame
.fpu_mask
& (1 << (regno
- 16)))
942 dwarf2out_reg_save (l
, regno
, -cfa_offset
943 + n_regs
++ * TARGET_FP_REG_SIZE
);
947 /* If the stack limit is not a symbol, check it here.
948 This has the disadvantage that it may be too late... */
949 if (current_function_limit_stack
)
951 if (REG_P (stack_limit_rtx
))
952 asm_fprintf (stream
, "\tcmp" ASM_DOT
"l %s,%Rsp\n\ttrapcs\n",
953 M68K_REGNAME (REGNO (stack_limit_rtx
)));
954 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
955 warning (0, "stack limit expression is not supported");
958 if (current_frame
.reg_no
<= 2)
960 /* Store each separately in the same order moveml uses.
961 Using two movel instructions instead of a single moveml
962 is about 15% faster for the 68020 and 68030 at no expense
967 for (i
= 0; i
< 16; i
++)
968 if (current_frame
.reg_rev_mask
& (1 << i
))
970 asm_fprintf (stream
, (MOTOROLA
971 ? "\t%Omove.l %s,-(%Rsp)\n"
972 : "\tmovel %s,%Rsp@-\n"),
973 M68K_REGNAME (15 - i
));
974 if (dwarf2out_do_frame ())
976 char *l
= (char *) dwarf2out_cfi_label ();
979 if (! frame_pointer_needed
)
980 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
981 dwarf2out_reg_save (l
, 15 - i
, -cfa_offset
);
985 else if (current_frame
.reg_rev_mask
)
988 /* The ColdFire does not support the predecrement form of the
989 MOVEM instruction, so we must adjust the stack pointer and
990 then use the plain address register indirect mode.
991 The required register save space was combined earlier with
992 the fsize_with_regs amount. */
994 asm_fprintf (stream
, (MOTOROLA
995 ? "\tmovm.l %I0x%x,(%Rsp)\n"
996 : "\tmoveml %I0x%x,%Rsp@\n"),
997 current_frame
.reg_mask
);
999 asm_fprintf (stream
, (MOTOROLA
1000 ? "\tmovm.l %I0x%x,-(%Rsp)\n"
1001 : "\tmoveml %I0x%x,%Rsp@-\n"),
1002 current_frame
.reg_rev_mask
);
1003 if (dwarf2out_do_frame ())
1005 char *l
= (char *) dwarf2out_cfi_label ();
1008 cfa_offset
+= current_frame
.reg_no
* 4;
1009 if (! frame_pointer_needed
)
1010 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
1011 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
1012 if (current_frame
.reg_mask
& (1 << regno
))
1013 dwarf2out_reg_save (l
, regno
, -cfa_offset
+ n_regs
++ * 4);
1016 if (!TARGET_SEP_DATA
&& flag_pic
1017 && (current_function_uses_pic_offset_table
1018 || (!current_function_is_leaf
&& TARGET_ID_SHARED_LIBRARY
)))
1020 if (TARGET_ID_SHARED_LIBRARY
)
1022 asm_fprintf (stream
, "\tmovel %s@(%s), %s\n",
1023 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1024 m68k_library_id_string
,
1025 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1030 asm_fprintf (stream
,
1031 "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
1032 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1035 asm_fprintf (stream
, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
1036 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1037 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
1038 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
),
1039 M68K_REGNAME (PIC_OFFSET_TABLE_REGNUM
));
1045 /* Return true if a simple (return) instruction is sufficient for this
1046 instruction (i.e. if no epilogue is needed). */
1049 m68k_use_return_insn (void)
1051 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1054 m68k_compute_frame_layout ();
1055 return current_frame
.offset
== 0;
1058 /* This function generates the assembly code for function exit,
1059 on machines that need it.
1061 The function epilogue should not depend on the current stack pointer!
1062 It should use the frame pointer only, if there is a frame pointer.
1063 This is mandatory because of alloca; we also take advantage of it to
1064 omit stack adjustments before returning. */
1067 m68k_output_function_epilogue (FILE *stream
,
1068 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1070 HOST_WIDE_INT fsize
, fsize_with_regs
;
1072 bool restore_from_sp
= false;
1073 rtx insn
= get_last_insn ();
1075 m68k_compute_frame_layout ();
1077 /* If the last insn was a BARRIER, we don't have to write any code. */
1078 if (GET_CODE (insn
) == NOTE
)
1079 insn
= prev_nonnote_insn (insn
);
1080 if (insn
&& GET_CODE (insn
) == BARRIER
)
1083 fsize
= current_frame
.size
;
1085 /* FIXME: leaf_function_p below is too strong.
1086 What we really need to know there is if there could be pending
1087 stack adjustment needed at that point. */
1089 = (! frame_pointer_needed
1090 || (! current_function_calls_alloca
&& leaf_function_p ()));
1092 /* fsize_with_regs is the size we need to adjust the sp when
1093 popping the frame. */
1094 fsize_with_regs
= fsize
;
1096 /* Because the ColdFire doesn't support moveml with
1097 complex address modes, we must adjust the stack manually
1098 after restoring registers. When the frame pointer isn't used,
1099 we can merge movem adjustment into frame unlinking
1100 made immediately after it. */
1101 if (TARGET_COLDFIRE
&& restore_from_sp
)
1103 if (current_frame
.reg_no
> 2)
1104 fsize_with_regs
+= current_frame
.reg_no
* 4;
1105 if (current_frame
.fpu_no
)
1106 fsize_with_regs
+= current_frame
.fpu_no
* 8;
1109 if (current_frame
.offset
+ fsize
>= 0x8000
1110 && ! restore_from_sp
1111 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1113 /* Because the ColdFire doesn't support moveml with
1114 complex address modes we make an extra correction here. */
1115 if (TARGET_COLDFIRE
)
1116 fsize
+= current_frame
.offset
;
1118 asm_fprintf (stream
, "\t%Omove" ASM_DOT
"l %I%wd,%Ra1\n", -fsize
);
1119 fsize
= 0, big
= true;
1121 if (current_frame
.reg_no
<= 2)
1123 /* Restore each separately in the same order moveml does.
1124 Using two movel instructions instead of a single moveml
1125 is about 15% faster for the 68020 and 68030 at no expense
1129 HOST_WIDE_INT offset
= current_frame
.offset
+ fsize
;
1131 for (i
= 0; i
< 16; i
++)
1132 if (current_frame
.reg_mask
& (1 << i
))
1137 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
1139 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1142 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
1143 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1147 else if (restore_from_sp
)
1148 asm_fprintf (stream
, (MOTOROLA
1149 ? "\t%Omove.l (%Rsp)+,%s\n"
1150 : "\tmovel %Rsp@+,%s\n"),
1155 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
1157 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1160 asm_fprintf (stream
, "\tmovel %s@(-%wd),%s\n",
1161 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1168 else if (current_frame
.reg_mask
)
1170 /* The ColdFire requires special handling due to its limited moveml
1172 if (TARGET_COLDFIRE
)
1176 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %s,%Ra1\n",
1177 M68K_REGNAME (FRAME_POINTER_REGNUM
));
1178 asm_fprintf (stream
, (MOTOROLA
1179 ? "\tmovm.l (%Ra1),%I0x%x\n"
1180 : "\tmoveml %Ra1@,%I0x%x\n"),
1181 current_frame
.reg_mask
);
1183 else if (restore_from_sp
)
1184 asm_fprintf (stream
, (MOTOROLA
1185 ? "\tmovm.l (%Rsp),%I0x%x\n"
1186 : "\tmoveml %Rsp@,%I0x%x\n"),
1187 current_frame
.reg_mask
);
1191 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1192 current_frame
.offset
+ fsize
,
1193 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1194 current_frame
.reg_mask
);
1196 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1197 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1198 current_frame
.offset
+ fsize
,
1199 current_frame
.reg_mask
);
1202 else /* !TARGET_COLDFIRE */
1207 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
1208 current_frame
.offset
+ fsize
,
1209 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1210 current_frame
.reg_mask
);
1212 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
1213 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1214 current_frame
.offset
+ fsize
,
1215 current_frame
.reg_mask
);
1217 else if (restore_from_sp
)
1219 asm_fprintf (stream
, (MOTOROLA
1220 ? "\tmovm.l (%Rsp)+,%I0x%x\n"
1221 : "\tmoveml %Rsp@+,%I0x%x\n"),
1222 current_frame
.reg_mask
);
1227 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
1228 current_frame
.offset
+ fsize
,
1229 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1230 current_frame
.reg_mask
);
1232 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
1233 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1234 current_frame
.offset
+ fsize
,
1235 current_frame
.reg_mask
);
1239 if (current_frame
.fpu_rev_mask
)
1243 if (TARGET_COLDFIRE
)
1245 if (current_frame
.reg_no
)
1246 asm_fprintf (stream
, MOTOROLA
?
1247 "\tfmovem.d %d(%Ra1),%I0x%x\n" :
1248 "\tfmovmd (%d,%Ra1),%I0x%x\n",
1249 current_frame
.reg_no
* 4,
1250 current_frame
.fpu_rev_mask
);
1252 asm_fprintf (stream
, MOTOROLA
?
1253 "\tfmovem.d (%Ra1),%I0x%x\n" :
1254 "\tfmovmd (%Ra1),%I0x%x\n",
1255 current_frame
.fpu_rev_mask
);
1258 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
1259 current_frame
.foffset
+ fsize
,
1260 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1261 current_frame
.fpu_rev_mask
);
1263 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
1264 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1265 current_frame
.foffset
+ fsize
,
1266 current_frame
.fpu_rev_mask
);
1268 else if (restore_from_sp
)
1270 if (TARGET_COLDFIRE
)
1274 /* Stack already has registers in it. Find the offset from
1275 the bottom of stack to where the FP registers go. */
1276 if (current_frame
.reg_no
<= 2)
1279 offset
= current_frame
.reg_no
* 4;
1281 asm_fprintf (stream
,
1282 "\tfmovem %Rsp@(%d), %I0x%x\n",
1283 offset
, current_frame
.fpu_rev_mask
);
1285 asm_fprintf (stream
,
1286 "\tfmovem %Rsp@, %I0x%x\n",
1287 current_frame
.fpu_rev_mask
);
1290 asm_fprintf (stream
, MOTOROLA
?
1291 "\tfmovm (%Rsp)+,%I0x%x\n" :
1292 "\tfmovem %Rsp@+,%I0x%x\n",
1293 current_frame
.fpu_rev_mask
);
1297 if (MOTOROLA
&& !TARGET_COLDFIRE
)
1298 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
1299 current_frame
.foffset
+ fsize
,
1300 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1301 current_frame
.fpu_rev_mask
);
1303 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
1304 M68K_REGNAME (FRAME_POINTER_REGNUM
),
1305 current_frame
.foffset
+ fsize
,
1306 current_frame
.fpu_rev_mask
);
1309 if (frame_pointer_needed
)
1310 fprintf (stream
, "\tunlk %s\n", M68K_REGNAME (FRAME_POINTER_REGNUM
));
1311 else if (fsize_with_regs
)
1313 if (fsize_with_regs
<= 8)
1315 if (!TARGET_COLDFIRE
)
1316 asm_fprintf (stream
, "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1319 asm_fprintf (stream
, "\taddq" ASM_DOT
"l %I%wd,%Rsp\n",
1322 else if (fsize_with_regs
<= 16 && TUNE_CPU32
)
1324 /* On the CPU32 it is faster to use two addqw instructions to
1325 add a small integer (8 < N <= 16) to a register. */
1326 asm_fprintf (stream
,
1327 "\taddq" ASM_DOT
"w %I8,%Rsp\n"
1328 "\taddq" ASM_DOT
"w %I%wd,%Rsp\n",
1329 fsize_with_regs
- 8);
1331 else if (fsize_with_regs
< 0x8000)
1334 asm_fprintf (stream
, "\tadd" ASM_DOT
"w %I%wd,%Rsp\n",
1337 asm_fprintf (stream
, (MOTOROLA
1338 ? "\tlea (%wd,%Rsp),%Rsp\n"
1339 : "\tlea %Rsp@(%wd),%Rsp\n"),
1343 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %I%wd,%Rsp\n", fsize_with_regs
);
1345 if (current_function_calls_eh_return
)
1346 asm_fprintf (stream
, "\tadd" ASM_DOT
"l %Ra0,%Rsp\n");
1347 if (m68k_interrupt_function_p (current_function_decl
))
1348 fprintf (stream
, "\trte\n");
1349 else if (current_function_pops_args
)
1350 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1352 fprintf (stream
, "\trts\n");
1355 /* Return true if X is a valid comparison operator for the dbcc
1358 Note it rejects floating point comparison operators.
1359 (In the future we could use Fdbcc).
1361 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1364 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1366 switch (GET_CODE (x
))
1368 case EQ
: case NE
: case GTU
: case LTU
:
1372 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1374 case GT
: case LT
: case GE
: case LE
:
1375 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1381 /* Return nonzero if flags are currently in the 68881 flag register. */
1383 flags_in_68881 (void)
1385 /* We could add support for these in the future */
1386 return cc_status
.flags
& CC_IN_68881
;
1389 /* Convert X to a legitimate function call memory reference and return the
1393 m68k_legitimize_call_address (rtx x
)
1395 gcc_assert (MEM_P (x
));
1396 if (call_operand (XEXP (x
, 0), VOIDmode
))
1398 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1401 /* Output a dbCC; jCC sequence. Note we do not handle the
1402 floating point version of this sequence (Fdbcc). We also
1403 do not handle alternative conditions when CC_NO_OVERFLOW is
1404 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1405 kick those out before we get here. */
1408 output_dbcc_and_branch (rtx
*operands
)
1410 switch (GET_CODE (operands
[3]))
1413 output_asm_insn (MOTOROLA
1414 ? "dbeq %0,%l1\n\tjbeq %l2"
1415 : "dbeq %0,%l1\n\tjeq %l2",
1420 output_asm_insn (MOTOROLA
1421 ? "dbne %0,%l1\n\tjbne %l2"
1422 : "dbne %0,%l1\n\tjne %l2",
1427 output_asm_insn (MOTOROLA
1428 ? "dbgt %0,%l1\n\tjbgt %l2"
1429 : "dbgt %0,%l1\n\tjgt %l2",
1434 output_asm_insn (MOTOROLA
1435 ? "dbhi %0,%l1\n\tjbhi %l2"
1436 : "dbhi %0,%l1\n\tjhi %l2",
1441 output_asm_insn (MOTOROLA
1442 ? "dblt %0,%l1\n\tjblt %l2"
1443 : "dblt %0,%l1\n\tjlt %l2",
1448 output_asm_insn (MOTOROLA
1449 ? "dbcs %0,%l1\n\tjbcs %l2"
1450 : "dbcs %0,%l1\n\tjcs %l2",
1455 output_asm_insn (MOTOROLA
1456 ? "dbge %0,%l1\n\tjbge %l2"
1457 : "dbge %0,%l1\n\tjge %l2",
1462 output_asm_insn (MOTOROLA
1463 ? "dbcc %0,%l1\n\tjbcc %l2"
1464 : "dbcc %0,%l1\n\tjcc %l2",
1469 output_asm_insn (MOTOROLA
1470 ? "dble %0,%l1\n\tjble %l2"
1471 : "dble %0,%l1\n\tjle %l2",
1476 output_asm_insn (MOTOROLA
1477 ? "dbls %0,%l1\n\tjbls %l2"
1478 : "dbls %0,%l1\n\tjls %l2",
1486 /* If the decrement is to be done in SImode, then we have
1487 to compensate for the fact that dbcc decrements in HImode. */
1488 switch (GET_MODE (operands
[0]))
1491 output_asm_insn (MOTOROLA
1492 ? "clr%.w %0\n\tsubq%.l #1,%0\n\tjbpl %l1"
1493 : "clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1",
1506 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1509 enum rtx_code op_code
= GET_CODE (op
);
1511 /* This does not produce a useful cc. */
1514 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1515 below. Swap the operands and change the op if these requirements
1516 are not fulfilled. */
1517 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1521 operand1
= operand2
;
1523 op_code
= swap_condition (op_code
);
1525 loperands
[0] = operand1
;
1526 if (GET_CODE (operand1
) == REG
)
1527 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1529 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1530 if (operand2
!= const0_rtx
)
1532 loperands
[2] = operand2
;
1533 if (GET_CODE (operand2
) == REG
)
1534 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1536 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1538 loperands
[4] = gen_label_rtx ();
1539 if (operand2
!= const0_rtx
)
1541 output_asm_insn (MOTOROLA
1542 ? "cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1"
1543 : "cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1",
1548 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1549 output_asm_insn ("tst%.l %0", loperands
);
1551 output_asm_insn ("cmp%.w #0,%0", loperands
);
1553 output_asm_insn (MOTOROLA
? "jbne %l4" : "jne %l4", loperands
);
1555 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1556 output_asm_insn ("tst%.l %1", loperands
);
1558 output_asm_insn ("cmp%.w #0,%1", loperands
);
1561 loperands
[5] = dest
;
1566 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1567 CODE_LABEL_NUMBER (loperands
[4]));
1568 output_asm_insn ("seq %5", loperands
);
1572 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1573 CODE_LABEL_NUMBER (loperands
[4]));
1574 output_asm_insn ("sne %5", loperands
);
1578 loperands
[6] = gen_label_rtx ();
1579 output_asm_insn (MOTOROLA
? "shi %5\n\tjbra %l6" : "shi %5\n\tjra %l6",
1581 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1582 CODE_LABEL_NUMBER (loperands
[4]));
1583 output_asm_insn ("sgt %5", loperands
);
1584 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1585 CODE_LABEL_NUMBER (loperands
[6]));
1589 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1590 CODE_LABEL_NUMBER (loperands
[4]));
1591 output_asm_insn ("shi %5", loperands
);
1595 loperands
[6] = gen_label_rtx ();
1596 output_asm_insn (MOTOROLA
? "scs %5\n\tjbra %l6" : "scs %5\n\tjra %l6",
1598 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1599 CODE_LABEL_NUMBER (loperands
[4]));
1600 output_asm_insn ("slt %5", loperands
);
1601 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1602 CODE_LABEL_NUMBER (loperands
[6]));
1606 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1607 CODE_LABEL_NUMBER (loperands
[4]));
1608 output_asm_insn ("scs %5", loperands
);
1612 loperands
[6] = gen_label_rtx ();
1613 output_asm_insn (MOTOROLA
? "scc %5\n\tjbra %l6" : "scc %5\n\tjra %l6",
1615 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1616 CODE_LABEL_NUMBER (loperands
[4]));
1617 output_asm_insn ("sge %5", loperands
);
1618 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1619 CODE_LABEL_NUMBER (loperands
[6]));
1623 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1624 CODE_LABEL_NUMBER (loperands
[4]));
1625 output_asm_insn ("scc %5", loperands
);
1629 loperands
[6] = gen_label_rtx ();
1630 output_asm_insn (MOTOROLA
? "sls %5\n\tjbra %l6" : "sls %5\n\tjra %l6",
1632 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1633 CODE_LABEL_NUMBER (loperands
[4]));
1634 output_asm_insn ("sle %5", loperands
);
1635 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1636 CODE_LABEL_NUMBER (loperands
[6]));
1640 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1641 CODE_LABEL_NUMBER (loperands
[4]));
1642 output_asm_insn ("sls %5", loperands
);
1652 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1654 operands
[0] = countop
;
1655 operands
[1] = dataop
;
1657 if (GET_CODE (countop
) == CONST_INT
)
1659 register int count
= INTVAL (countop
);
1660 /* If COUNT is bigger than size of storage unit in use,
1661 advance to the containing unit of same size. */
1662 if (count
> signpos
)
1664 int offset
= (count
& ~signpos
) / 8;
1665 count
= count
& signpos
;
1666 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1668 if (count
== signpos
)
1669 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1671 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1673 /* These three statements used to use next_insns_test_no...
1674 but it appears that this should do the same job. */
1676 && next_insn_tests_no_inequality (insn
))
1679 && next_insn_tests_no_inequality (insn
))
1682 && next_insn_tests_no_inequality (insn
))
1685 cc_status
.flags
= CC_NOT_NEGATIVE
;
1687 return "btst %0,%1";
1690 /* Return true if X is a legitimate base register. STRICT_P says
1691 whether we need strict checking. */
1694 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1696 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1697 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1702 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1703 : !DATA_REGNO_P (REGNO (x
)) && !FP_REGNO_P (REGNO (x
))));
1706 /* Return true if X is a legitimate index register. STRICT_P says
1707 whether we need strict checking. */
1710 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1712 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1717 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1718 : !FP_REGNO_P (REGNO (x
))));
1721 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1722 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1723 ADDRESS if so. STRICT_P says whether we need strict checking. */
1726 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1730 /* Check for a scale factor. */
1732 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1733 && GET_CODE (x
) == MULT
1734 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1735 && (INTVAL (XEXP (x
, 1)) == 2
1736 || INTVAL (XEXP (x
, 1)) == 4
1737 || (INTVAL (XEXP (x
, 1)) == 8
1738 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1740 scale
= INTVAL (XEXP (x
, 1));
1744 /* Check for a word extension. */
1745 if (!TARGET_COLDFIRE
1746 && GET_CODE (x
) == SIGN_EXTEND
1747 && GET_MODE (XEXP (x
, 0)) == HImode
)
1750 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1752 address
->scale
= scale
;
1760 /* Return true if X is an illegitimate symbolic constant. */
1763 m68k_illegitimate_symbolic_constant_p (rtx x
)
1767 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1769 split_const (x
, &base
, &offset
);
1770 if (GET_CODE (base
) == SYMBOL_REF
1771 && !offset_within_block_p (base
, INTVAL (offset
)))
1777 /* Return true if X is a legitimate constant address that can reach
1778 bytes in the range [X, X + REACH). STRICT_P says whether we need
1782 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1786 if (!CONSTANT_ADDRESS_P (x
))
1790 && !(strict_p
&& TARGET_PCREL
)
1791 && symbolic_operand (x
, VOIDmode
))
1794 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1796 split_const (x
, &base
, &offset
);
1797 if (GET_CODE (base
) == SYMBOL_REF
1798 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1805 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1806 labels will become jump tables. */
1809 m68k_jump_table_ref_p (rtx x
)
1811 if (GET_CODE (x
) != LABEL_REF
)
1815 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1818 x
= next_nonnote_insn (x
);
1819 return x
&& JUMP_TABLE_DATA_P (x
);
1822 /* Return true if X is a legitimate address for values of mode MODE.
1823 STRICT_P says whether strict checking is needed. If the address
1824 is valid, describe its components in *ADDRESS. */
1827 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1828 bool strict_p
, struct m68k_address
*address
)
1832 memset (address
, 0, sizeof (*address
));
1834 if (mode
== BLKmode
)
1837 reach
= GET_MODE_SIZE (mode
);
1839 /* Check for (An) (mode 2). */
1840 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1846 /* Check for -(An) and (An)+ (modes 3 and 4). */
1847 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1848 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1850 address
->code
= GET_CODE (x
);
1851 address
->base
= XEXP (x
, 0);
1855 /* Check for (d16,An) (mode 5). */
1856 if (GET_CODE (x
) == PLUS
1857 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1858 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1859 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1861 address
->base
= XEXP (x
, 0);
1862 address
->offset
= XEXP (x
, 1);
1866 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1867 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1870 && GET_CODE (x
) == PLUS
1871 && XEXP (x
, 0) == pic_offset_table_rtx
1872 && (GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
1873 || GET_CODE (XEXP (x
, 1)) == LABEL_REF
))
1875 address
->base
= XEXP (x
, 0);
1876 address
->offset
= XEXP (x
, 1);
1880 /* The ColdFire FPU only accepts addressing modes 2-5. */
1881 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1884 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1885 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1886 All these modes are variations of mode 7. */
1887 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1889 address
->offset
= x
;
1893 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1896 ??? do_tablejump creates these addresses before placing the target
1897 label, so we have to assume that unplaced labels are jump table
1898 references. It seems unlikely that we would ever generate indexed
1899 accesses to unplaced labels in other cases. */
1900 if (GET_CODE (x
) == PLUS
1901 && m68k_jump_table_ref_p (XEXP (x
, 1))
1902 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1904 address
->offset
= XEXP (x
, 1);
1908 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1909 (bd,An,Xn.SIZE*SCALE) addresses. */
1913 /* Check for a nonzero base displacement. */
1914 if (GET_CODE (x
) == PLUS
1915 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
1917 address
->offset
= XEXP (x
, 1);
1921 /* Check for a suppressed index register. */
1922 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1928 /* Check for a suppressed base register. Do not allow this case
1929 for non-symbolic offsets as it effectively gives gcc freedom
1930 to treat data registers as base registers, which can generate
1933 && symbolic_operand (address
->offset
, VOIDmode
)
1934 && m68k_decompose_index (x
, strict_p
, address
))
1939 /* Check for a nonzero base displacement. */
1940 if (GET_CODE (x
) == PLUS
1941 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1942 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
1944 address
->offset
= XEXP (x
, 1);
1949 /* We now expect the sum of a base and an index. */
1950 if (GET_CODE (x
) == PLUS
)
1952 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
1953 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
1955 address
->base
= XEXP (x
, 0);
1959 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
1960 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1962 address
->base
= XEXP (x
, 1);
1969 /* Return true if X is a legitimate address for values of mode MODE.
1970 STRICT_P says whether strict checking is needed. */
1973 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1975 struct m68k_address address
;
1977 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
1980 /* Return true if X is a memory, describing its address in ADDRESS if so.
1981 Apply strict checking if called during or after reload. */
1984 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
1987 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
1988 reload_in_progress
|| reload_completed
,
1992 /* Return true if X matches the 'Q' constraint. It must be a memory
1993 with a base address and no constant offset or index. */
1996 m68k_matches_q_p (rtx x
)
1998 struct m68k_address address
;
2000 return (m68k_legitimate_mem_p (x
, &address
)
2001 && address
.code
== UNKNOWN
2007 /* Return true if X matches the 'U' constraint. It must be a base address
2008 with a constant offset and no index. */
2011 m68k_matches_u_p (rtx x
)
2013 struct m68k_address address
;
2015 return (m68k_legitimate_mem_p (x
, &address
)
2016 && address
.code
== UNKNOWN
2022 /* Legitimize PIC addresses. If the address is already
2023 position-independent, we return ORIG. Newly generated
2024 position-independent addresses go to REG. If we need more
2025 than one register, we lose.
2027 An address is legitimized by making an indirect reference
2028 through the Global Offset Table with the name of the symbol
2031 The assembler and linker are responsible for placing the
2032 address of the symbol in the GOT. The function prologue
2033 is responsible for initializing a5 to the starting address
2036 The assembler is also responsible for translating a symbol name
2037 into a constant displacement from the start of the GOT.
2039 A quick example may make things a little clearer:
2041 When not generating PIC code to store the value 12345 into _foo
2042 we would generate the following code:
2046 When generating PIC two transformations are made. First, the compiler
2047 loads the address of foo into a register. So the first transformation makes:
2052 The code in movsi will intercept the lea instruction and call this
2053 routine which will transform the instructions into:
2055 movel a5@(_foo:w), a0
2059 That (in a nutshell) is how *all* symbol and label references are
2063 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2068 /* First handle a simple SYMBOL_REF or LABEL_REF */
2069 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2073 pic_ref
= gen_rtx_MEM (Pmode
,
2074 gen_rtx_PLUS (Pmode
,
2075 pic_offset_table_rtx
, orig
));
2076 current_function_uses_pic_offset_table
= 1;
2077 MEM_READONLY_P (pic_ref
) = 1;
2078 emit_move_insn (reg
, pic_ref
);
2081 else if (GET_CODE (orig
) == CONST
)
2085 /* Make sure this has not already been legitimized. */
2086 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2087 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2092 /* legitimize both operands of the PLUS */
2093 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2095 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2096 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2097 base
== reg
? 0 : reg
);
2099 if (GET_CODE (orig
) == CONST_INT
)
2100 return plus_constant (base
, INTVAL (orig
));
2101 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2102 /* Likewise, should we set special REG_NOTEs here? */
2108 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
, MVS
, MVZ
} CONST_METHOD
;
2110 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2112 /* Return the type of move that should be used for integer I. */
2115 const_method (HOST_WIDE_INT i
)
2122 /* The ColdFire doesn't have byte or word operations. */
2123 /* FIXME: This may not be useful for the m68060 either. */
2124 if (!TARGET_COLDFIRE
)
2126 /* if -256 < N < 256 but N is not in range for a moveq
2127 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2128 if (USE_MOVQ (i
^ 0xff))
2130 /* Likewise, try with not.w */
2131 if (USE_MOVQ (i
^ 0xffff))
2133 /* This is the only value where neg.w is useful */
2138 /* Try also with swap. */
2140 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2145 /* Try using MVZ/MVS with an immediate value to load constants. */
2146 if (i
>= 0 && i
<= 65535)
2148 if (i
>= -32768 && i
<= 32767)
2152 /* Otherwise, use move.l */
2156 /* Return the cost of moving constant I into a data register. */
2159 const_int_cost (HOST_WIDE_INT i
)
2161 switch (const_method (i
))
2164 /* Constants between -128 and 127 are cheap due to moveq. */
2172 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2182 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2187 /* Constant zero is super cheap due to clr instruction. */
2188 if (x
== const0_rtx
)
2191 *total
= const_int_cost (INTVAL (x
));
2201 /* Make 0.0 cheaper than other floating constants to
2202 encourage creating tstsf and tstdf insns. */
2203 if (outer_code
== COMPARE
2204 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2210 /* These are vaguely right for a 68020. */
2211 /* The costs for long multiply have been adjusted to work properly
2212 in synth_mult on the 68020, relative to an average of the time
2213 for add and the time for shift, taking away a little more because
2214 sometimes move insns are needed. */
2215 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2221 : TARGET_COLDFIRE ? 3 : 13)
2226 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2227 : TARGET_COLDFIRE ? 2 : 8)
2230 (TARGET_CF_HWDIV ? 11 \
2231 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2234 /* An lea costs about three times as much as a simple add. */
2235 if (GET_MODE (x
) == SImode
2236 && GET_CODE (XEXP (x
, 1)) == REG
2237 && GET_CODE (XEXP (x
, 0)) == MULT
2238 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2239 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2240 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2241 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2242 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2244 /* lea an@(dx:l:i),am */
2245 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2255 *total
= COSTS_N_INSNS(1);
2260 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2262 if (INTVAL (XEXP (x
, 1)) < 16)
2263 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2265 /* We're using clrw + swap for these cases. */
2266 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2269 *total
= COSTS_N_INSNS (10); /* Worst case. */
2272 /* A shift by a big integer takes an extra instruction. */
2273 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2274 && (INTVAL (XEXP (x
, 1)) == 16))
2276 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2279 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2280 && !(INTVAL (XEXP (x
, 1)) > 0
2281 && INTVAL (XEXP (x
, 1)) <= 8))
2283 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2289 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2290 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2291 && GET_MODE (x
) == SImode
)
2292 *total
= COSTS_N_INSNS (MULW_COST
);
2293 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2294 *total
= COSTS_N_INSNS (MULW_COST
);
2296 *total
= COSTS_N_INSNS (MULL_COST
);
2303 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2304 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2305 else if (TARGET_CF_HWDIV
)
2306 *total
= COSTS_N_INSNS (18);
2308 *total
= COSTS_N_INSNS (43); /* div.l */
2316 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2320 output_move_const_into_data_reg (rtx
*operands
)
2324 i
= INTVAL (operands
[1]);
2325 switch (const_method (i
))
2328 return "mvzw %1,%0";
2330 return "mvsw %1,%0";
2332 return "moveq %1,%0";
2335 operands
[1] = GEN_INT (i
^ 0xff);
2336 return "moveq %1,%0\n\tnot%.b %0";
2339 operands
[1] = GEN_INT (i
^ 0xffff);
2340 return "moveq %1,%0\n\tnot%.w %0";
2343 return "moveq #-128,%0\n\tneg%.w %0";
2348 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2349 return "moveq %1,%0\n\tswap %0";
2352 return "move%.l %1,%0";
2358 /* Return true if I can be handled by ISA B's mov3q instruction. */
2361 valid_mov3q_const (HOST_WIDE_INT i
)
2363 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2366 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2367 I is the value of OPERANDS[1]. */
2370 output_move_simode_const (rtx
*operands
)
2376 src
= INTVAL (operands
[1]);
2378 && (DATA_REG_P (dest
) || MEM_P (dest
))
2379 /* clr insns on 68000 read before writing. */
2380 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2381 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2383 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2384 return "mov3q%.l %1,%0";
2385 else if (src
== 0 && ADDRESS_REG_P (dest
))
2386 return "sub%.l %0,%0";
2387 else if (DATA_REG_P (dest
))
2388 return output_move_const_into_data_reg (operands
);
2389 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2391 if (valid_mov3q_const (src
))
2392 return "mov3q%.l %1,%0";
2393 return "move%.w %1,%0";
2395 else if (MEM_P (dest
)
2396 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2397 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2398 && IN_RANGE (src
, -0x8000, 0x7fff))
2400 if (valid_mov3q_const (src
))
2401 return "mov3q%.l %1,%-";
2404 return "move%.l %1,%0";
2408 output_move_simode (rtx
*operands
)
2410 if (GET_CODE (operands
[1]) == CONST_INT
)
2411 return output_move_simode_const (operands
);
2412 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2413 || GET_CODE (operands
[1]) == CONST
)
2414 && push_operand (operands
[0], SImode
))
2416 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2417 || GET_CODE (operands
[1]) == CONST
)
2418 && ADDRESS_REG_P (operands
[0]))
2419 return "lea %a1,%0";
2420 return "move%.l %1,%0";
2424 output_move_himode (rtx
*operands
)
2426 if (GET_CODE (operands
[1]) == CONST_INT
)
2428 if (operands
[1] == const0_rtx
2429 && (DATA_REG_P (operands
[0])
2430 || GET_CODE (operands
[0]) == MEM
)
2431 /* clr insns on 68000 read before writing. */
2432 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2433 || !(GET_CODE (operands
[0]) == MEM
2434 && MEM_VOLATILE_P (operands
[0]))))
2436 else if (operands
[1] == const0_rtx
2437 && ADDRESS_REG_P (operands
[0]))
2438 return "sub%.l %0,%0";
2439 else if (DATA_REG_P (operands
[0])
2440 && INTVAL (operands
[1]) < 128
2441 && INTVAL (operands
[1]) >= -128)
2442 return "moveq %1,%0";
2443 else if (INTVAL (operands
[1]) < 0x8000
2444 && INTVAL (operands
[1]) >= -0x8000)
2445 return "move%.w %1,%0";
2447 else if (CONSTANT_P (operands
[1]))
2448 return "move%.l %1,%0";
2449 /* Recognize the insn before a tablejump, one that refers
2450 to a table of offsets. Such an insn will need to refer
2451 to a label on the insn. So output one. Use the label-number
2452 of the table of offsets to generate this label. This code,
2453 and similar code below, assumes that there will be at most one
2454 reference to each table. */
2455 if (GET_CODE (operands
[1]) == MEM
2456 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2457 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
2458 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
2460 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
2462 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
2463 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2465 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
2466 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
2468 return "move%.w %1,%0";
2472 output_move_qimode (rtx
*operands
)
2474 /* 68k family always modifies the stack pointer by at least 2, even for
2475 byte pushes. The 5200 (ColdFire) does not do this. */
2477 /* This case is generated by pushqi1 pattern now. */
2478 gcc_assert (!(GET_CODE (operands
[0]) == MEM
2479 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
2480 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
2481 && ! ADDRESS_REG_P (operands
[1])
2482 && ! TARGET_COLDFIRE
));
2484 /* clr and st insns on 68000 read before writing. */
2485 if (!ADDRESS_REG_P (operands
[0])
2486 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2487 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2489 if (operands
[1] == const0_rtx
)
2491 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
2492 && GET_CODE (operands
[1]) == CONST_INT
2493 && (INTVAL (operands
[1]) & 255) == 255)
2499 if (GET_CODE (operands
[1]) == CONST_INT
2500 && DATA_REG_P (operands
[0])
2501 && INTVAL (operands
[1]) < 128
2502 && INTVAL (operands
[1]) >= -128)
2503 return "moveq %1,%0";
2504 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
2505 return "sub%.l %0,%0";
2506 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2507 return "move%.l %1,%0";
2508 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2509 from address registers. */
2510 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2511 return "move%.w %1,%0";
2512 return "move%.b %1,%0";
2516 output_move_stricthi (rtx
*operands
)
2518 if (operands
[1] == const0_rtx
2519 /* clr insns on 68000 read before writing. */
2520 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2521 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2523 return "move%.w %1,%0";
2527 output_move_strictqi (rtx
*operands
)
2529 if (operands
[1] == const0_rtx
2530 /* clr insns on 68000 read before writing. */
2531 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2532 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2534 return "move%.b %1,%0";
2537 /* Return the best assembler insn template
2538 for moving operands[1] into operands[0] as a fullword. */
2541 singlemove_string (rtx
*operands
)
2543 if (GET_CODE (operands
[1]) == CONST_INT
)
2544 return output_move_simode_const (operands
);
2545 return "move%.l %1,%0";
2549 /* Output assembler code to perform a doubleword move insn
2550 with operands OPERANDS. */
2553 output_move_double (rtx
*operands
)
2557 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2562 rtx addreg0
= 0, addreg1
= 0;
2563 int dest_overlapped_low
= 0;
2564 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2569 /* First classify both operands. */
2571 if (REG_P (operands
[0]))
2573 else if (offsettable_memref_p (operands
[0]))
2575 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2577 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2579 else if (GET_CODE (operands
[0]) == MEM
)
2584 if (REG_P (operands
[1]))
2586 else if (CONSTANT_P (operands
[1]))
2588 else if (offsettable_memref_p (operands
[1]))
2590 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2592 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2594 else if (GET_CODE (operands
[1]) == MEM
)
2599 /* Check for the cases that the operand constraints are not supposed
2600 to allow to happen. Generating code for these cases is
2602 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
2604 /* If one operand is decrementing and one is incrementing
2605 decrement the former register explicitly
2606 and change that operand into ordinary indexing. */
2608 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2610 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2612 output_asm_insn ("sub%.l #12,%0", operands
);
2614 output_asm_insn ("subq%.l #8,%0", operands
);
2615 if (GET_MODE (operands
[1]) == XFmode
)
2616 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2617 else if (GET_MODE (operands
[0]) == DFmode
)
2618 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2620 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2623 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2625 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2627 output_asm_insn ("sub%.l #12,%1", operands
);
2629 output_asm_insn ("subq%.l #8,%1", operands
);
2630 if (GET_MODE (operands
[1]) == XFmode
)
2631 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2632 else if (GET_MODE (operands
[1]) == DFmode
)
2633 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2635 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2639 /* If an operand is an unoffsettable memory ref, find a register
2640 we can increment temporarily to make it refer to the second word. */
2642 if (optype0
== MEMOP
)
2643 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2645 if (optype1
== MEMOP
)
2646 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2648 /* Ok, we can do one word at a time.
2649 Normally we do the low-numbered word first,
2650 but if either operand is autodecrementing then we
2651 do the high-numbered word first.
2653 In either case, set up in LATEHALF the operands to use
2654 for the high-numbered word and in some cases alter the
2655 operands in OPERANDS to be suitable for the low-numbered word. */
2659 if (optype0
== REGOP
)
2661 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2662 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2664 else if (optype0
== OFFSOP
)
2666 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2667 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2671 middlehalf
[0] = operands
[0];
2672 latehalf
[0] = operands
[0];
2675 if (optype1
== REGOP
)
2677 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2678 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2680 else if (optype1
== OFFSOP
)
2682 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2683 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2685 else if (optype1
== CNSTOP
)
2687 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2692 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2693 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2694 operands
[1] = GEN_INT (l
[0]);
2695 middlehalf
[1] = GEN_INT (l
[1]);
2696 latehalf
[1] = GEN_INT (l
[2]);
2700 /* No non-CONST_DOUBLE constant should ever appear
2702 gcc_assert (!CONSTANT_P (operands
[1]));
2707 middlehalf
[1] = operands
[1];
2708 latehalf
[1] = operands
[1];
2712 /* size is not 12: */
2714 if (optype0
== REGOP
)
2715 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2716 else if (optype0
== OFFSOP
)
2717 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2719 latehalf
[0] = operands
[0];
2721 if (optype1
== REGOP
)
2722 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2723 else if (optype1
== OFFSOP
)
2724 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2725 else if (optype1
== CNSTOP
)
2726 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2728 latehalf
[1] = operands
[1];
2731 /* If insn is effectively movd N(sp),-(sp) then we will do the
2732 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2733 for the low word as well, to compensate for the first decrement of sp. */
2734 if (optype0
== PUSHOP
2735 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2736 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2737 operands
[1] = middlehalf
[1] = latehalf
[1];
2739 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2740 if the upper part of reg N does not appear in the MEM, arrange to
2741 emit the move late-half first. Otherwise, compute the MEM address
2742 into the upper part of N and use that as a pointer to the memory
2744 if (optype0
== REGOP
2745 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2747 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2749 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2750 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2752 /* If both halves of dest are used in the src memory address,
2753 compute the address into latehalf of dest.
2754 Note that this can't happen if the dest is two data regs. */
2756 xops
[0] = latehalf
[0];
2757 xops
[1] = XEXP (operands
[1], 0);
2758 output_asm_insn ("lea %a1,%0", xops
);
2759 if (GET_MODE (operands
[1]) == XFmode
)
2761 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2762 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2763 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2767 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2768 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2772 && reg_overlap_mentioned_p (middlehalf
[0],
2773 XEXP (operands
[1], 0)))
2775 /* Check for two regs used by both source and dest.
2776 Note that this can't happen if the dest is all data regs.
2777 It can happen if the dest is d6, d7, a0.
2778 But in that case, latehalf is an addr reg, so
2779 the code at compadr does ok. */
2781 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2782 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2785 /* JRV says this can't happen: */
2786 gcc_assert (!addreg0
&& !addreg1
);
2788 /* Only the middle reg conflicts; simply put it last. */
2789 output_asm_insn (singlemove_string (operands
), operands
);
2790 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2791 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2794 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2795 /* If the low half of dest is mentioned in the source memory
2796 address, the arrange to emit the move late half first. */
2797 dest_overlapped_low
= 1;
2800 /* If one or both operands autodecrementing,
2801 do the two words, high-numbered first. */
2803 /* Likewise, the first move would clobber the source of the second one,
2804 do them in the other order. This happens only for registers;
2805 such overlap can't happen in memory unless the user explicitly
2806 sets it up, and that is an undefined circumstance. */
2808 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2809 || (optype0
== REGOP
&& optype1
== REGOP
2810 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2811 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2812 || dest_overlapped_low
)
2814 /* Make any unoffsettable addresses point at high-numbered word. */
2818 output_asm_insn ("addq%.l #8,%0", &addreg0
);
2820 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2825 output_asm_insn ("addq%.l #8,%0", &addreg1
);
2827 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2831 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2833 /* Undo the adds we just did. */
2835 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2837 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2841 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2843 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2845 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2848 /* Do low-numbered word. */
2849 return singlemove_string (operands
);
2852 /* Normal case: do the two words, low-numbered first. */
2854 output_asm_insn (singlemove_string (operands
), operands
);
2856 /* Do the middle one of the three words for long double */
2860 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2862 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2864 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2867 /* Make any unoffsettable addresses point at high-numbered word. */
2869 output_asm_insn ("addq%.l #4,%0", &addreg0
);
2871 output_asm_insn ("addq%.l #4,%0", &addreg1
);
2874 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2876 /* Undo the adds we just did. */
2880 output_asm_insn ("subq%.l #8,%0", &addreg0
);
2882 output_asm_insn ("subq%.l #4,%0", &addreg0
);
2887 output_asm_insn ("subq%.l #8,%0", &addreg1
);
2889 output_asm_insn ("subq%.l #4,%0", &addreg1
);
2896 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2897 new rtx with the correct mode. */
2900 force_mode (enum machine_mode mode
, rtx orig
)
2902 if (mode
== GET_MODE (orig
))
2905 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
2908 return gen_rtx_REG (mode
, REGNO (orig
));
2912 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2914 return reg_renumber
&& FP_REG_P (op
);
2917 /* Emit insns to move operands[1] into operands[0].
2919 Return 1 if we have written out everything that needs to be done to
2920 do the move. Otherwise, return 0 and the caller will emit the move
2923 Note SCRATCH_REG may not be in the proper mode depending on how it
2924 will be used. This routine is responsible for creating a new copy
2925 of SCRATCH_REG in the proper mode. */
2928 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
2930 register rtx operand0
= operands
[0];
2931 register rtx operand1
= operands
[1];
2935 && reload_in_progress
&& GET_CODE (operand0
) == REG
2936 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
2937 operand0
= reg_equiv_mem
[REGNO (operand0
)];
2938 else if (scratch_reg
2939 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
2940 && GET_CODE (SUBREG_REG (operand0
)) == REG
2941 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
2943 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2944 the code which tracks sets/uses for delete_output_reload. */
2945 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
2946 reg_equiv_mem
[REGNO (SUBREG_REG (operand0
))],
2947 SUBREG_BYTE (operand0
));
2948 operand0
= alter_subreg (&temp
);
2952 && reload_in_progress
&& GET_CODE (operand1
) == REG
2953 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
2954 operand1
= reg_equiv_mem
[REGNO (operand1
)];
2955 else if (scratch_reg
2956 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
2957 && GET_CODE (SUBREG_REG (operand1
)) == REG
2958 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
2960 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2961 the code which tracks sets/uses for delete_output_reload. */
2962 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
2963 reg_equiv_mem
[REGNO (SUBREG_REG (operand1
))],
2964 SUBREG_BYTE (operand1
));
2965 operand1
= alter_subreg (&temp
);
2968 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
2969 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
2970 != XEXP (operand0
, 0)))
2971 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
2972 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
2973 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
2974 != XEXP (operand1
, 0)))
2975 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
2977 /* Handle secondary reloads for loads/stores of FP registers where
2978 the address is symbolic by using the scratch register */
2979 if (fp_reg_operand (operand0
, mode
)
2980 && ((GET_CODE (operand1
) == MEM
2981 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
2982 || ((GET_CODE (operand1
) == SUBREG
2983 && GET_CODE (XEXP (operand1
, 0)) == MEM
2984 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
2987 if (GET_CODE (operand1
) == SUBREG
)
2988 operand1
= XEXP (operand1
, 0);
2990 /* SCRATCH_REG will hold an address. We want
2991 it in SImode regardless of what mode it was originally given
2993 scratch_reg
= force_mode (SImode
, scratch_reg
);
2995 /* D might not fit in 14 bits either; for such cases load D into
2997 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
2999 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3000 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3002 XEXP (XEXP (operand1
, 0), 0),
3006 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3007 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3008 gen_rtx_MEM (mode
, scratch_reg
)));
3011 else if (fp_reg_operand (operand1
, mode
)
3012 && ((GET_CODE (operand0
) == MEM
3013 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3014 || ((GET_CODE (operand0
) == SUBREG
)
3015 && GET_CODE (XEXP (operand0
, 0)) == MEM
3016 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3019 if (GET_CODE (operand0
) == SUBREG
)
3020 operand0
= XEXP (operand0
, 0);
3022 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3023 it in SIMODE regardless of what mode it was originally given
3025 scratch_reg
= force_mode (SImode
, scratch_reg
);
3027 /* D might not fit in 14 bits either; for such cases load D into
3029 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3031 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3032 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3035 XEXP (XEXP (operand0
, 0),
3040 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3041 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3045 /* Handle secondary reloads for loads of FP registers from constant
3046 expressions by forcing the constant into memory.
3048 use scratch_reg to hold the address of the memory location.
3050 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3051 NO_REGS when presented with a const_int and an register class
3052 containing only FP registers. Doing so unfortunately creates
3053 more problems than it solves. Fix this for 2.5. */
3054 else if (fp_reg_operand (operand0
, mode
)
3055 && CONSTANT_P (operand1
)
3060 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3061 it in SIMODE regardless of what mode it was originally given
3063 scratch_reg
= force_mode (SImode
, scratch_reg
);
3065 /* Force the constant into memory and put the address of the
3066 memory location into scratch_reg. */
3067 xoperands
[0] = scratch_reg
;
3068 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3069 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3071 /* Now load the destination register. */
3072 emit_insn (gen_rtx_SET (mode
, operand0
,
3073 gen_rtx_MEM (mode
, scratch_reg
)));
3077 /* Now have insn-emit do whatever it normally does. */
3081 /* Split one or more DImode RTL references into pairs of SImode
3082 references. The RTL can be REG, offsettable MEM, integer constant, or
3083 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3084 split and "num" is its length. lo_half and hi_half are output arrays
3085 that parallel "operands". */
3088 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3092 rtx op
= operands
[num
];
3094 /* simplify_subreg refuses to split volatile memory addresses,
3095 but we still have to handle it. */
3096 if (GET_CODE (op
) == MEM
)
3098 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3099 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3103 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3104 GET_MODE (op
) == VOIDmode
3105 ? DImode
: GET_MODE (op
), 4);
3106 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3107 GET_MODE (op
) == VOIDmode
3108 ? DImode
: GET_MODE (op
), 0);
3113 /* Return a REG that occurs in ADDR with coefficient 1.
3114 ADDR can be effectively incremented by incrementing REG. */
3117 find_addr_reg (rtx addr
)
3119 while (GET_CODE (addr
) == PLUS
)
3121 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3122 addr
= XEXP (addr
, 0);
3123 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3124 addr
= XEXP (addr
, 1);
3125 else if (CONSTANT_P (XEXP (addr
, 0)))
3126 addr
= XEXP (addr
, 1);
3127 else if (CONSTANT_P (XEXP (addr
, 1)))
3128 addr
= XEXP (addr
, 0);
3132 gcc_assert (GET_CODE (addr
) == REG
);
3136 /* Output assembler code to perform a 32-bit 3-operand add. */
3139 output_addsi3 (rtx
*operands
)
3141 if (! operands_match_p (operands
[0], operands
[1]))
3143 if (!ADDRESS_REG_P (operands
[1]))
3145 rtx tmp
= operands
[1];
3147 operands
[1] = operands
[2];
3151 /* These insns can result from reloads to access
3152 stack slots over 64k from the frame pointer. */
3153 if (GET_CODE (operands
[2]) == CONST_INT
3154 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
3155 return "move%.l %2,%0\n\tadd%.l %1,%0";
3156 if (GET_CODE (operands
[2]) == REG
)
3157 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3158 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3160 if (GET_CODE (operands
[2]) == CONST_INT
)
3162 if (INTVAL (operands
[2]) > 0
3163 && INTVAL (operands
[2]) <= 8)
3164 return "addq%.l %2,%0";
3165 if (INTVAL (operands
[2]) < 0
3166 && INTVAL (operands
[2]) >= -8)
3168 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
3169 return "subq%.l %2,%0";
3171 /* On the CPU32 it is faster to use two addql instructions to
3172 add a small integer (8 < N <= 16) to a register.
3173 Likewise for subql. */
3174 if (TUNE_CPU32
&& REG_P (operands
[0]))
3176 if (INTVAL (operands
[2]) > 8
3177 && INTVAL (operands
[2]) <= 16)
3179 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
3180 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3182 if (INTVAL (operands
[2]) < -8
3183 && INTVAL (operands
[2]) >= -16)
3185 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
3186 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3189 if (ADDRESS_REG_P (operands
[0])
3190 && INTVAL (operands
[2]) >= -0x8000
3191 && INTVAL (operands
[2]) < 0x8000)
3194 return "add%.w %2,%0";
3196 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3199 return "add%.l %2,%0";
3202 /* Store in cc_status the expressions that the condition codes will
3203 describe after execution of an instruction whose pattern is EXP.
3204 Do not alter them if the instruction would not alter the cc's. */
3206 /* On the 68000, all the insns to store in an address register fail to
3207 set the cc's. However, in some cases these instructions can make it
3208 possibly invalid to use the saved cc's. In those cases we clear out
3209 some or all of the saved cc's so they won't be used. */
3212 notice_update_cc (rtx exp
, rtx insn
)
3214 if (GET_CODE (exp
) == SET
)
3216 if (GET_CODE (SET_SRC (exp
)) == CALL
)
3218 else if (ADDRESS_REG_P (SET_DEST (exp
)))
3220 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
3221 cc_status
.value1
= 0;
3222 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
3223 cc_status
.value2
= 0;
3225 /* fmoves to memory or data registers do not set the condition
3226 codes. Normal moves _do_ set the condition codes, but not in
3227 a way that is appropriate for comparison with 0, because -0.0
3228 would be treated as a negative nonzero number. Note that it
3229 isn't appropriate to conditionalize this restriction on
3230 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3231 we care about the difference between -0.0 and +0.0. */
3232 else if (!FP_REG_P (SET_DEST (exp
))
3233 && SET_DEST (exp
) != cc0_rtx
3234 && (FP_REG_P (SET_SRC (exp
))
3235 || GET_CODE (SET_SRC (exp
)) == FIX
3236 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
3238 /* A pair of move insns doesn't produce a useful overall cc. */
3239 else if (!FP_REG_P (SET_DEST (exp
))
3240 && !FP_REG_P (SET_SRC (exp
))
3241 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
3242 && (GET_CODE (SET_SRC (exp
)) == REG
3243 || GET_CODE (SET_SRC (exp
)) == MEM
3244 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
3246 else if (SET_DEST (exp
) != pc_rtx
)
3248 cc_status
.flags
= 0;
3249 cc_status
.value1
= SET_DEST (exp
);
3250 cc_status
.value2
= SET_SRC (exp
);
3253 else if (GET_CODE (exp
) == PARALLEL
3254 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
3256 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
3257 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
3259 if (ADDRESS_REG_P (dest
))
3261 else if (dest
!= pc_rtx
)
3263 cc_status
.flags
= 0;
3264 cc_status
.value1
= dest
;
3265 cc_status
.value2
= src
;
3270 if (cc_status
.value2
!= 0
3271 && ADDRESS_REG_P (cc_status
.value2
)
3272 && GET_MODE (cc_status
.value2
) == QImode
)
3274 if (cc_status
.value2
!= 0)
3275 switch (GET_CODE (cc_status
.value2
))
3277 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
3278 case ROTATE
: case ROTATERT
:
3279 /* These instructions always clear the overflow bit, and set
3280 the carry to the bit shifted out. */
3281 /* ??? We don't currently have a way to signal carry not valid,
3282 nor do we check for it in the branch insns. */
3286 case PLUS
: case MINUS
: case MULT
:
3287 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
3288 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
3289 cc_status
.flags
|= CC_NO_OVERFLOW
;
3292 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3293 ends with a move insn moving r2 in r2's mode.
3294 Thus, the cc's are set for r2.
3295 This can set N bit spuriously. */
3296 cc_status
.flags
|= CC_NOT_NEGATIVE
;
3301 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
3303 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
3304 cc_status
.value2
= 0;
3305 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
3306 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
3307 cc_status
.flags
= CC_IN_68881
;
3311 output_move_const_double (rtx
*operands
)
3313 int code
= standard_68881_constant_p (operands
[1]);
3317 static char buf
[40];
3319 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3322 return "fmove%.d %1,%0";
3326 output_move_const_single (rtx
*operands
)
3328 int code
= standard_68881_constant_p (operands
[1]);
3332 static char buf
[40];
3334 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
3337 return "fmove%.s %f1,%0";
3340 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3341 from the "fmovecr" instruction.
3342 The value, anded with 0xff, gives the code to use in fmovecr
3343 to get the desired constant. */
3345 /* This code has been fixed for cross-compilation. */
3347 static int inited_68881_table
= 0;
3349 static const char *const strings_68881
[7] = {
3359 static const int codes_68881
[7] = {
3369 REAL_VALUE_TYPE values_68881
[7];
3371 /* Set up values_68881 array by converting the decimal values
3372 strings_68881 to binary. */
3375 init_68881_table (void)
3379 enum machine_mode mode
;
3382 for (i
= 0; i
< 7; i
++)
3386 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
3387 values_68881
[i
] = r
;
3389 inited_68881_table
= 1;
3393 standard_68881_constant_p (rtx x
)
3398 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3399 used at all on those chips. */
3403 if (! inited_68881_table
)
3404 init_68881_table ();
3406 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3408 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3410 for (i
= 0; i
< 6; i
++)
3412 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
3413 return (codes_68881
[i
]);
3416 if (GET_MODE (x
) == SFmode
)
3419 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
3420 return (codes_68881
[6]);
3422 /* larger powers of ten in the constants ram are not used
3423 because they are not equal to a `double' C constant. */
3427 /* If X is a floating-point constant, return the logarithm of X base 2,
3428 or 0 if X is not a power of 2. */
3431 floating_exact_log2 (rtx x
)
3433 REAL_VALUE_TYPE r
, r1
;
3436 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3438 if (REAL_VALUES_LESS (r
, dconst1
))
3441 exp
= real_exponent (&r
);
3442 real_2expN (&r1
, exp
);
3443 if (REAL_VALUES_EQUAL (r1
, r
))
3449 /* A C compound statement to output to stdio stream STREAM the
3450 assembler syntax for an instruction operand X. X is an RTL
3453 CODE is a value that can be used to specify one of several ways
3454 of printing the operand. It is used when identical operands
3455 must be printed differently depending on the context. CODE
3456 comes from the `%' specification that was used to request
3457 printing of the operand. If the specification was just `%DIGIT'
3458 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3459 is the ASCII code for LTR.
3461 If X is a register, this macro should print the register's name.
3462 The names can be found in an array `reg_names' whose type is
3463 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3465 When the machine description has a specification `%PUNCT' (a `%'
3466 followed by a punctuation character), this macro is called with
3467 a null pointer for X and the punctuation character for CODE.
3469 The m68k specific codes are:
3471 '.' for dot needed in Motorola-style opcode names.
3472 '-' for an operand pushing on the stack:
3473 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3474 '+' for an operand pushing on the stack:
3475 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3476 '@' for a reference to the top word on the stack:
3477 sp@, (sp) or (%sp) depending on the style of syntax.
3478 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3479 but & in SGS syntax).
3480 '!' for the cc register (used in an `and to cc' insn).
3481 '$' for the letter `s' in an op code, but only on the 68040.
3482 '&' for the letter `d' in an op code, but only on the 68040.
3483 '/' for register prefix needed by longlong.h.
3485 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3486 'd' to force memory addressing to be absolute, not relative.
3487 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3488 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3489 or print pair of registers as rx:ry.
3490 'p' print an address with @PLTPC attached, but only if the operand
3491 is not locally-bound. */
3494 print_operand (FILE *file
, rtx op
, int letter
)
3499 fprintf (file
, ".");
3501 else if (letter
== '#')
3502 asm_fprintf (file
, "%I");
3503 else if (letter
== '-')
3504 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
3505 else if (letter
== '+')
3506 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
3507 else if (letter
== '@')
3508 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
3509 else if (letter
== '!')
3510 asm_fprintf (file
, "%Rfpcr");
3511 else if (letter
== '$')
3514 fprintf (file
, "s");
3516 else if (letter
== '&')
3519 fprintf (file
, "d");
3521 else if (letter
== '/')
3522 asm_fprintf (file
, "%R");
3523 else if (letter
== 'p')
3525 output_addr_const (file
, op
);
3526 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
3527 fprintf (file
, "@PLTPC");
3529 else if (GET_CODE (op
) == REG
)
3532 /* Print out the second register name of a register pair.
3533 I.e., R (6) => 7. */
3534 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
3536 fputs (M68K_REGNAME(REGNO (op
)), file
);
3538 else if (GET_CODE (op
) == MEM
)
3540 output_address (XEXP (op
, 0));
3541 if (letter
== 'd' && ! TARGET_68020
3542 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
3543 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
3544 && INTVAL (XEXP (op
, 0)) < 0x8000
3545 && INTVAL (XEXP (op
, 0)) >= -0x8000))
3546 fprintf (file
, MOTOROLA
? ".l" : ":l");
3548 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
3551 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3552 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
3554 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
3557 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3558 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
3560 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
3563 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
3564 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
3568 /* Use `print_operand_address' instead of `output_addr_const'
3569 to ensure that we print relevant PIC stuff. */
3570 asm_fprintf (file
, "%I");
3572 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
3573 print_operand_address (file
, op
);
3575 output_addr_const (file
, op
);
3580 /* A C compound statement to output to stdio stream STREAM the
3581 assembler syntax for an instruction operand that is a memory
3582 reference whose address is ADDR. ADDR is an RTL expression.
3584 Note that this contains a kludge that knows that the only reason
3585 we have an address (plus (label_ref...) (reg...)) when not generating
3586 PIC code is in the insn before a tablejump, and we know that m68k.md
3587 generates a label LInnn: on such an insn.
3589 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3590 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3592 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3593 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3594 we want. This difference can be accommodated by using an assembler
3595 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3596 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3597 macro. See m68k/sgs.h for an example; for versions without the bug.
3598 Some assemblers refuse all the above solutions. The workaround is to
3599 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3602 They also do not like things like "pea 1.w", so we simple leave off
3603 the .w on small constants.
3605 This routine is responsible for distinguishing between -fpic and -fPIC
3606 style relocations in an address. When generating -fpic code the
3607 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3608 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3611 print_operand_address (FILE *file
, rtx addr
)
3613 struct m68k_address address
;
3615 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
3618 if (address
.code
== PRE_DEC
)
3619 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
3620 M68K_REGNAME (REGNO (address
.base
)));
3621 else if (address
.code
== POST_INC
)
3622 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
3623 M68K_REGNAME (REGNO (address
.base
)));
3624 else if (!address
.base
&& !address
.index
)
3626 /* A constant address. */
3627 gcc_assert (address
.offset
== addr
);
3628 if (GET_CODE (addr
) == CONST_INT
)
3630 /* (xxx).w or (xxx).l. */
3631 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
3632 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
3634 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3636 else if (TARGET_PCREL
)
3638 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3640 output_addr_const (file
, addr
);
3641 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3645 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3646 name ends in `.<letter>', as the last 2 characters can be
3647 mistaken as a size suffix. Put the name in parentheses. */
3648 if (GET_CODE (addr
) == SYMBOL_REF
3649 && strlen (XSTR (addr
, 0)) > 2
3650 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3653 output_addr_const (file
, addr
);
3657 output_addr_const (file
, addr
);
3664 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3665 label being acceesed, otherwise it is -1. */
3666 labelno
= (address
.offset
3668 && GET_CODE (address
.offset
) == LABEL_REF
3669 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
3673 /* Print the "offset(base" component. */
3675 asm_fprintf (file
, "%LL%d-%LLI%d.b(%Rpc,", labelno
, labelno
);
3680 output_addr_const (file
, address
.offset
);
3681 if (flag_pic
&& address
.base
== pic_offset_table_rtx
)
3683 fprintf (file
, "@GOT");
3684 if (flag_pic
== 1 && TARGET_68020
)
3685 fprintf (file
, ".w");
3690 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3692 /* Print the ",index" component, if any. */
3697 fprintf (file
, "%s.%c",
3698 M68K_REGNAME (REGNO (address
.index
)),
3699 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3700 if (address
.scale
!= 1)
3701 fprintf (file
, "*%d", address
.scale
);
3705 else /* !MOTOROLA */
3707 if (!address
.offset
&& !address
.index
)
3708 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
3711 /* Print the "base@(offset" component. */
3713 asm_fprintf (file
, "%Rpc@(%LL%d-%LLI%d-2:b", labelno
, labelno
);
3717 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
3718 fprintf (file
, "@(");
3721 output_addr_const (file
, address
.offset
);
3722 if (address
.base
== pic_offset_table_rtx
&& TARGET_68020
)
3726 fprintf (file
, ":w"); break;
3728 fprintf (file
, ":l"); break;
3734 /* Print the ",index" component, if any. */
3737 fprintf (file
, ",%s:%c",
3738 M68K_REGNAME (REGNO (address
.index
)),
3739 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
3740 if (address
.scale
!= 1)
3741 fprintf (file
, ":%d", address
.scale
);
3749 /* Check for cases where a clr insns can be omitted from code using
3750 strict_low_part sets. For example, the second clrl here is not needed:
3751 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3753 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3754 insn we are checking for redundancy. TARGET is the register set by the
3758 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
3763 p
= prev_nonnote_insn (first_insn
);
3767 /* If it isn't an insn, then give up. */
3768 if (GET_CODE (p
) != INSN
)
3771 if (reg_set_p (target
, p
))
3773 rtx set
= single_set (p
);
3776 /* If it isn't an easy to recognize insn, then give up. */
3780 dest
= SET_DEST (set
);
3782 /* If this sets the entire target register to zero, then our
3783 first_insn is redundant. */
3784 if (rtx_equal_p (dest
, target
)
3785 && SET_SRC (set
) == const0_rtx
)
3787 else if (GET_CODE (dest
) == STRICT_LOW_PART
3788 && GET_CODE (XEXP (dest
, 0)) == REG
3789 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3790 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3791 <= GET_MODE_SIZE (mode
)))
3792 /* This is a strict low part set which modifies less than
3793 we are using, so it is safe. */
3799 p
= prev_nonnote_insn (p
);
3805 /* Operand predicates for implementing asymmetric pc-relative addressing
3806 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3807 when used as a source operand, but not as a destination operand.
3809 We model this by restricting the meaning of the basic predicates
3810 (general_operand, memory_operand, etc) to forbid the use of this
3811 addressing mode, and then define the following predicates that permit
3812 this addressing mode. These predicates can then be used for the
3813 source operands of the appropriate instructions.
3815 n.b. While it is theoretically possible to change all machine patterns
3816 to use this addressing more where permitted by the architecture,
3817 it has only been implemented for "common" cases: SImode, HImode, and
3818 QImode operands, and only for the principle operations that would
3819 require this addressing mode: data movement and simple integer operations.
3821 In parallel with these new predicates, two new constraint letters
3822 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3823 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3824 In the pcrel case 's' is only valid in combination with 'a' registers.
3825 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3826 of how these constraints are used.
3828 The use of these predicates is strictly optional, though patterns that
3829 don't will cause an extra reload register to be allocated where one
3832 lea (abc:w,%pc),%a0 ; need to reload address
3833 moveq &1,%d1 ; since write to pc-relative space
3834 movel %d1,%a0@ ; is not allowed
3836 lea (abc:w,%pc),%a1 ; no need to reload address here
3837 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3839 For more info, consult tiemann@cygnus.com.
3842 All of the ugliness with predicates and constraints is due to the
3843 simple fact that the m68k does not allow a pc-relative addressing
3844 mode as a destination. gcc does not distinguish between source and
3845 destination addresses. Hence, if we claim that pc-relative address
3846 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3847 end up with invalid code. To get around this problem, we left
3848 pc-relative modes as invalid addresses, and then added special
3849 predicates and constraints to accept them.
3851 A cleaner way to handle this is to modify gcc to distinguish
3852 between source and destination addresses. We can then say that
3853 pc-relative is a valid source address but not a valid destination
3854 address, and hopefully avoid a lot of the predicate and constraint
3855 hackery. Unfortunately, this would be a pretty big change. It would
3856 be a useful change for a number of ports, but there aren't any current
3857 plans to undertake this.
3859 ***************************************************************************/
3863 output_andsi3 (rtx
*operands
)
3866 if (GET_CODE (operands
[2]) == CONST_INT
3867 && (INTVAL (operands
[2]) | 0xffff) == -1
3868 && (DATA_REG_P (operands
[0])
3869 || offsettable_memref_p (operands
[0]))
3870 && !TARGET_COLDFIRE
)
3872 if (GET_CODE (operands
[0]) != REG
)
3873 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3874 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3875 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3877 if (operands
[2] == const0_rtx
)
3879 return "and%.w %2,%0";
3881 if (GET_CODE (operands
[2]) == CONST_INT
3882 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3883 && (DATA_REG_P (operands
[0])
3884 || offsettable_memref_p (operands
[0])))
3886 if (DATA_REG_P (operands
[0]))
3887 operands
[1] = GEN_INT (logval
);
3890 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3891 operands
[1] = GEN_INT (logval
% 8);
3893 /* This does not set condition codes in a standard way. */
3895 return "bclr %1,%0";
3897 return "and%.l %2,%0";
3901 output_iorsi3 (rtx
*operands
)
3903 register int logval
;
3904 if (GET_CODE (operands
[2]) == CONST_INT
3905 && INTVAL (operands
[2]) >> 16 == 0
3906 && (DATA_REG_P (operands
[0])
3907 || offsettable_memref_p (operands
[0]))
3908 && !TARGET_COLDFIRE
)
3910 if (GET_CODE (operands
[0]) != REG
)
3911 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3912 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3914 if (INTVAL (operands
[2]) == 0xffff)
3915 return "mov%.w %2,%0";
3916 return "or%.w %2,%0";
3918 if (GET_CODE (operands
[2]) == CONST_INT
3919 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3920 && (DATA_REG_P (operands
[0])
3921 || offsettable_memref_p (operands
[0])))
3923 if (DATA_REG_P (operands
[0]))
3924 operands
[1] = GEN_INT (logval
);
3927 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3928 operands
[1] = GEN_INT (logval
% 8);
3931 return "bset %1,%0";
3933 return "or%.l %2,%0";
3937 output_xorsi3 (rtx
*operands
)
3939 register int logval
;
3940 if (GET_CODE (operands
[2]) == CONST_INT
3941 && INTVAL (operands
[2]) >> 16 == 0
3942 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3943 && !TARGET_COLDFIRE
)
3945 if (! DATA_REG_P (operands
[0]))
3946 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3947 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3949 if (INTVAL (operands
[2]) == 0xffff)
3951 return "eor%.w %2,%0";
3953 if (GET_CODE (operands
[2]) == CONST_INT
3954 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3955 && (DATA_REG_P (operands
[0])
3956 || offsettable_memref_p (operands
[0])))
3958 if (DATA_REG_P (operands
[0]))
3959 operands
[1] = GEN_INT (logval
);
3962 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3963 operands
[1] = GEN_INT (logval
% 8);
3966 return "bchg %1,%0";
3968 return "eor%.l %2,%0";
3971 /* Return the instruction that should be used for a call to address X,
3972 which is known to be in operand 0. */
3977 if (symbolic_operand (x
, VOIDmode
))
3978 return m68k_symbolic_call
;
3983 #ifdef M68K_TARGET_COFF
3985 /* Output assembly to switch to section NAME with attribute FLAGS. */
3988 m68k_coff_asm_named_section (const char *name
, unsigned int flags
,
3989 tree decl ATTRIBUTE_UNUSED
)
3993 if (flags
& SECTION_WRITE
)
3998 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
4001 #endif /* M68K_TARGET_COFF */
4004 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4005 HOST_WIDE_INT delta
,
4006 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
4012 if (delta
> 0 && delta
<= 8)
4013 asm_fprintf (file
, (MOTOROLA
4014 ? "\taddq.l %I%d,4(%Rsp)\n"
4015 : "\taddql %I%d,%Rsp@(4)\n"),
4017 else if (delta
< 0 && delta
>= -8)
4018 asm_fprintf (file
, (MOTOROLA
4019 ? "\tsubq.l %I%d,4(%Rsp)\n"
4020 : "\tsubql %I%d,%Rsp@(4)\n"),
4022 else if (TARGET_COLDFIRE
)
4024 /* ColdFire can't add/sub a constant to memory unless it is in
4025 the range of addq/subq. So load the value into %d0 and
4026 then add it to 4(%sp). */
4027 if (delta
>= -128 && delta
<= 127)
4028 asm_fprintf (file
, (MOTOROLA
4029 ? "\tmoveq.l %I%wd,%Rd0\n"
4030 : "\tmoveql %I%wd,%Rd0\n"),
4033 asm_fprintf (file
, (MOTOROLA
4034 ? "\tmove.l %I%wd,%Rd0\n"
4035 : "\tmovel %I%wd,%Rd0\n"),
4037 asm_fprintf (file
, (MOTOROLA
4038 ? "\tadd.l %Rd0,4(%Rsp)\n"
4039 : "\taddl %Rd0,%Rsp@(4)\n"));
4042 asm_fprintf (file
, (MOTOROLA
4043 ? "\tadd.l %I%wd,4(%Rsp)\n"
4044 : "\taddl %I%wd,%Rsp@(4)\n"),
4047 xops
[0] = DECL_RTL (function
);
4049 gcc_assert (MEM_P (xops
[0])
4050 && symbolic_operand (XEXP (xops
[0], 0), VOIDmode
));
4051 xops
[0] = XEXP (xops
[0], 0);
4053 fmt
= m68k_symbolic_jump
;
4054 if (m68k_symbolic_jump
== NULL
)
4055 fmt
= "move.l %%a1@GOT(%%a5), %%a1\n\tjmp (%%a1)";
4057 output_asm_insn (fmt
, xops
);
4060 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4063 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4064 int incoming ATTRIBUTE_UNUSED
)
4066 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
4069 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4071 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
4072 unsigned int new_reg
)
4075 /* Interrupt functions can only use registers that have already been
4076 saved by the prologue, even if they would normally be
4079 if (m68k_interrupt_function_p (current_function_decl
)
4080 && !regs_ever_live
[new_reg
])
4086 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
4087 On the 68000, the cpu registers can hold any mode except bytes in address
4088 registers, but the 68881 registers can hold only SFmode or DFmode. */
4090 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
4092 if (DATA_REGNO_P (regno
))
4094 /* Data Registers, can hold aggregate if fits in. */
4095 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
4098 else if (ADDRESS_REGNO_P (regno
))
4100 /* Address Registers, can't hold bytes, can hold aggregate if
4102 if (GET_MODE_SIZE (mode
) == 1)
4104 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
4107 else if (FP_REGNO_P (regno
))
4109 /* FPU registers, hold float or complex float of long double or
4111 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4112 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4113 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
4119 /* Return floating point values in a 68881 register. This makes 68881 code
4120 a little bit faster. It also makes -msoft-float code incompatible with
4121 hard-float code, so people have to be careful not to mix the two.
4122 For ColdFire it was decided the ABI incompatibility is undesirable.
4123 If there is need for a hard-float ABI it is probably worth doing it
4124 properly and also passing function arguments in FP registers. */
4126 m68k_libcall_value (enum machine_mode mode
)
4133 return gen_rtx_REG (mode
, 16);
4138 return gen_rtx_REG (mode
, 0);
4142 m68k_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4144 enum machine_mode mode
;
4146 mode
= TYPE_MODE (valtype
);
4152 return gen_rtx_REG (mode
, 16);
4158 /* If the function returns a pointer, push that into %a0. */
4159 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
4160 /* For compatibility with the large body of existing code which
4161 does not always properly declare external functions returning
4162 pointer types, the m68k/SVR4 convention is to copy the value
4163 returned for pointer functions from a0 to d0 in the function
4164 epilogue, so that callers that have neglected to properly
4165 declare the callee can still find the correct return value in
4167 return gen_rtx_PARALLEL
4170 gen_rtx_EXPR_LIST (VOIDmode
,
4171 gen_rtx_REG (mode
, A0_REG
),
4173 gen_rtx_EXPR_LIST (VOIDmode
,
4174 gen_rtx_REG (mode
, D0_REG
),
4176 else if (POINTER_TYPE_P (valtype
))
4177 return gen_rtx_REG (mode
, A0_REG
);
4179 return gen_rtx_REG (mode
, D0_REG
);