gcc/config/m68k/m68k.h

   1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
   2    Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to
  19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  20 Boston, MA 02110-1301, USA.  */
  21
  22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
  23    if-statements and ?: on it.  This way we have compile-time error checking
  24    for both the MOTOROLA and MIT code paths.  We do rely on the host compiler
  25    to optimize away all constant tests.  */
  26 #if MOTOROLA  /* Use the Motorola assembly syntax.  */
  27 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
  28 #else
  29 # define MOTOROLA 0  /* Use the MIT assembly syntax.  */
  30 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
  31 #endif
  32
  33 /* Handle --with-cpu default option from configure script.  */
  34 #define OPTION_DEFAULT_SPECS                                            \
  35   { "cpu",   "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
  36 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
  37 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
  38 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
  39
  40 /* Pass flags to gas indicating which type of processor we have.  This
  41    can be simplified when we can rely on the assembler supporting .cpu
  42    and .arch directives.  */
  43
  44 #define ASM_CPU_SPEC "\
  45 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
  46 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
  47 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
  48 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
  49 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
  50 "
  51
  52 #define ASM_SPEC "%(asm_cpu_spec)"
  53
  54 #define EXTRA_SPECS                                     \
  55   { "asm_cpu_spec", ASM_CPU_SPEC },                     \
  56   SUBTARGET_EXTRA_SPECS
  57
  58 #define SUBTARGET_EXTRA_SPECS
  59
  60 /* Note that some other tm.h files include this one and then override
  61    many of the definitions that relate to assembler syntax.  */
  62
  63 #define TARGET_CPU_CPP_BUILTINS()                                       \
  64   do                                                                    \
  65     {                                                                   \
  66       builtin_define ("__m68k__");                                      \
  67       builtin_define_std ("mc68000");                                   \
  68       /* The other mc680x0 macros have traditionally been derived       \
  69          from the tuning setting.  For example, -m68020-60 defines      \
  70          m68060, even though it generates pure 68020 code.  */          \
  71       switch (m68k_tune)                                                \
  72         {                                                               \
  73         case u68010:                                                    \
  74           builtin_define_std ("mc68010");                               \
  75           break;                                                        \
  76                                                                         \
  77         case u68020:                                                    \
  78           builtin_define_std ("mc68020");                               \
  79           break;                                                        \
  80                                                                         \
  81         case u68030:                                                    \
  82           builtin_define_std ("mc68030");                               \
  83           break;                                                        \
  84                                                                         \
  85         case u68040:                                                    \
  86           builtin_define_std ("mc68040");                               \
  87           break;                                                        \
  88                                                                         \
  89         case u68060:                                                    \
  90           builtin_define_std ("mc68060");                               \
  91           break;                                                        \
  92                                                                         \
  93         case u68020_60:                                                 \
  94           builtin_define_std ("mc68060");                               \
  95           /* Fall through.  */                                          \
  96         case u68020_40:                                                 \
  97           builtin_define_std ("mc68040");                               \
  98           builtin_define_std ("mc68030");                               \
  99           builtin_define_std ("mc68020");                               \
 100           break;                                                        \
 101                                                                         \
 102         case ucpu32:                                                    \
 103           builtin_define_std ("mc68332");                               \
 104           builtin_define_std ("mcpu32");                                \
 105           builtin_define_std ("mc68020");                               \
 106           break;                                                        \
 107                                                                         \
 108         case ucfv2:                                                     \
 109           builtin_define ("__mcfv2__");                                 \
 110           break;                                                        \
 111                                                                         \
 112         case ucfv3:                                                     \
 113           builtin_define ("__mcfv3__");                                 \
 114           break;                                                        \
 115                                                                         \
 116         case ucfv4:                                                     \
 117           builtin_define ("__mcfv4__");                                 \
 118           break;                                                        \
 119                                                                         \
 120         case ucfv4e:                                                    \
 121           builtin_define ("__mcfv4e__");                                \
 122           break;                                                        \
 123                                                                         \
 124         case ucfv5:                                                     \
 125           builtin_define ("__mcfv5__");                                 \
 126           break;                                                        \
 127                                                                         \
 128         default:                                                        \
 129           break;                                                        \
 130         }                                                               \
 131                                                                         \
 132       if (TARGET_68881)                                                 \
 133         builtin_define ("__HAVE_68881__");                              \
 134                                                                         \
 135       if (TARGET_COLDFIRE)                                              \
 136         {                                                               \
 137           const char *tmp;                                              \
 138                                                                         \
 139           tmp = m68k_cpp_cpu_ident ("cf");                              \
 140           if (tmp)                                                      \
 141             builtin_define (tmp);                                       \
 142           tmp = m68k_cpp_cpu_family ("cf");                             \
 143           if (tmp)                                                      \
 144             builtin_define (tmp);                                       \
 145           builtin_define ("__mcoldfire__");                             \
 146                                                                         \
 147           if (TARGET_ISAC)                                              \
 148             builtin_define ("__mcfisac__");                             \
 149           else if (TARGET_ISAB)                                         \
 150             {                                                           \
 151               builtin_define ("__mcfisab__");                           \
 152               /* ISA_B: Legacy 5407 defines.  */                        \
 153               builtin_define ("__mcf5400__");                           \
 154               builtin_define ("__mcf5407__");                           \
 155             }                                                           \
 156           else if (TARGET_ISAAPLUS)                                     \
 157             {                                                           \
 158               builtin_define ("__mcfisaaplus__");                       \
 159               /* ISA_A+: legacy defines.  */                            \
 160               builtin_define ("__mcf528x__");                           \
 161               builtin_define ("__mcf5200__");                           \
 162             }                                                           \
 163           else                                                          \
 164             {                                                           \
 165               builtin_define ("__mcfisaa__");                           \
 166               /* ISA_A: legacy defines.  */                             \
 167               switch (m68k_tune)                                        \
 168                 {                                                       \
 169                 case ucfv2:                                             \
 170                   builtin_define ("__mcf5200__");                       \
 171                   break;                                                \
 172                                                                         \
 173                 case ucfv3:                                             \
 174                   builtin_define ("__mcf5307__");                       \
 175                   builtin_define ("__mcf5300__");                       \
 176                   break;                                                \
 177                                                                         \
 178                 default:                                                \
 179                   break;                                                \
 180                 }                                                       \
 181             }                                                           \
 182         }                                                               \
 183                                                                         \
 184       if (TARGET_COLDFIRE_FPU)                                          \
 185         builtin_define ("__mcffpu__");                                  \
 186                                                                         \
 187       if (TARGET_CF_HWDIV)                                              \
 188         builtin_define ("__mcfhwdiv__");                                \
 189                                                                         \
 190       if (TARGET_FIDOA)                                                 \
 191         builtin_define ("__mfido__");                                   \
 192                                                                         \
 193       builtin_assert ("cpu=m68k");                                      \
 194       builtin_assert ("machine=m68k");                                  \
 195     }                                                                   \
 196   while (0)
 197
 198 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
 199    quantities.  */
 200 #define INT_OP_STANDARD 0       /* .byte, .short, .long */
 201 #define INT_OP_DOT_WORD 1       /* .byte, .word, .long */
 202 #define INT_OP_NO_DOT   2       /* byte, short, long */
 203 #define INT_OP_DC       3       /* dc.b, dc.w, dc.l */
 204
 205 /* Set the default.  */
 206 #define INT_OP_GROUP INT_OP_DOT_WORD
 207
 208 /* Bit values used by m68k-devices.def to identify processor capabilities.  */
 209 #define FL_BITFIELD  (1 << 0)    /* Support bitfield instructions.  */
 210 #define FL_68881     (1 << 1)    /* (Default) support for 68881/2.  */
 211 #define FL_COLDFIRE  (1 << 2)    /* ColdFire processor.  */
 212 #define FL_CF_HWDIV  (1 << 3)    /* ColdFire hardware divide supported.  */
 213 #define FL_CF_MAC    (1 << 4)    /* ColdFire MAC unit supported.  */
 214 #define FL_CF_EMAC   (1 << 5)    /* ColdFire eMAC unit supported.  */
 215 #define FL_CF_EMAC_B (1 << 6)    /* ColdFire eMAC-B unit supported.  */
 216 #define FL_CF_USP    (1 << 7)    /* ColdFire User Stack Pointer supported.  */
 217 #define FL_CF_FPU    (1 << 8)    /* ColdFire FPU supported.  */
 218 #define FL_ISA_68000 (1 << 9)
 219 #define FL_ISA_68010 (1 << 10)
 220 #define FL_ISA_68020 (1 << 11)
 221 #define FL_ISA_68040 (1 << 12)
 222 #define FL_ISA_A     (1 << 13)
 223 #define FL_ISA_APLUS (1 << 14)
 224 #define FL_ISA_B     (1 << 15)
 225 #define FL_ISA_C     (1 << 16)
 226 #define FL_FIDOA     (1 << 17)
 227 #define FL_MMU       0   /* Used by multilib machinery.  */
 228
 229 #define TARGET_68010            ((m68k_cpu_flags & FL_ISA_68010) != 0)
 230 #define TARGET_68020            ((m68k_cpu_flags & FL_ISA_68020) != 0)
 231 #define TARGET_68040            ((m68k_cpu_flags & FL_ISA_68040) != 0)
 232 #define TARGET_COLDFIRE         ((m68k_cpu_flags & FL_COLDFIRE) != 0)
 233 #define TARGET_COLDFIRE_FPU     (m68k_fpu == FPUTYPE_COLDFIRE)
 234 #define TARGET_68881            (m68k_fpu == FPUTYPE_68881)
 235 #define TARGET_FIDOA            ((m68k_cpu_flags & FL_FIDOA) != 0)
 236
 237 /* Size (in bytes) of FPU registers.  */
 238 #define TARGET_FP_REG_SIZE      (TARGET_COLDFIRE ? 8 : 12)
 239
 240 #define TARGET_ISAAPLUS         ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
 241 #define TARGET_ISAB             ((m68k_cpu_flags & FL_ISA_B) != 0)
 242 #define TARGET_ISAC             ((m68k_cpu_flags & FL_ISA_C) != 0)
 243
 244 #define TUNE_68000      (m68k_tune == u68000)
 245 #define TUNE_68010      (m68k_tune == u68010)
 246 #define TUNE_68000_10   (TUNE_68000 || TUNE_68010)
 247 #define TUNE_68030      (m68k_tune == u68030 \
 248                          || m68k_tune == u68020_40 \
 249                          || m68k_tune == u68020_60)
 250 #define TUNE_68040      (m68k_tune == u68040 \
 251                          || m68k_tune == u68020_40 \
 252                          || m68k_tune == u68020_60)
 253 #define TUNE_68060      (m68k_tune == u68060 || m68k_tune == u68020_60)
 254 #define TUNE_68040_60   (TUNE_68040 || TUNE_68060)
 255 #define TUNE_CPU32      (m68k_tune == ucpu32)
 256 #define TUNE_CFV2       (m68k_tune == ucfv2)
 257
 258 #define OVERRIDE_OPTIONS   override_options()
 259
 260 /* These are meant to be redefined in the host dependent files */
 261 #define SUBTARGET_OVERRIDE_OPTIONS
 262 \f
 263 /* target machine storage layout */
 264
 265 /* "long double" is the same as "double" on ColdFire and fido
 266    targets.  */
 267
 268 #define LONG_DOUBLE_TYPE_SIZE                   \
 269   ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
 270
 271 /* We need to know the size of long double at compile-time in libgcc2.  */
 272
 273 #if defined(__mcoldfire__) || defined(__mfido__)
 274 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
 275 #else
 276 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
 277 #endif
 278
 279 /* Set the value of FLT_EVAL_METHOD in float.h.  When using 68040 fp
 280    instructions, we get proper intermediate rounding, otherwise we
 281    get extended precision results.  */
 282 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
 283
 284 #define BITS_BIG_ENDIAN 1
 285 #define BYTES_BIG_ENDIAN 1
 286 #define WORDS_BIG_ENDIAN 1
 287
 288 #define UNITS_PER_WORD 4
 289
 290 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
 291 #define STACK_BOUNDARY 16
 292 #define FUNCTION_BOUNDARY 16
 293 #define EMPTY_FIELD_BOUNDARY 16
 294 /* ColdFire and fido strongly prefer a 32-bit aligned stack.  */
 295 #define PREFERRED_STACK_BOUNDARY \
 296   ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
 297
 298 /* No data type wants to be aligned rounder than this.
 299    Most published ABIs say that ints should be aligned on 16-bit
 300    boundaries, but CPUs with 32-bit busses get better performance
 301    aligned on 32-bit boundaries.  ColdFires without a misalignment
 302    module require 32-bit alignment.  */
 303 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
 304
 305 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
 306
 307 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
 308
 309 /* Define these to avoid dependence on meaning of `int'.  */
 310 #define WCHAR_TYPE "long int"
 311 #define WCHAR_TYPE_SIZE 32
 312
 313 /* Maximum number of library IDs we permit with -mid-shared-library.  */
 314 #define MAX_LIBRARY_ID 255
 315
 316 \f
 317 /* Standard register usage.  */
 318
 319 /* For the m68k, we give the data registers numbers 0-7,
 320    the address registers numbers 010-017 (8-15),
 321    and the 68881 floating point registers numbers 020-027 (16-23).
 322    We also have a fake `arg-pointer' register 030 (24) used for
 323    register elimination.  */
 324 #define FIRST_PSEUDO_REGISTER 25
 325
 326 /* All m68k targets (except AmigaOS) use %a5 as the PIC register  */
 327 #define PIC_OFFSET_TABLE_REGNUM                         \
 328   (!flag_pic ? INVALID_REGNUM                           \
 329    : reload_completed ? REGNO (pic_offset_table_rtx)    \
 330    : PIC_REG)
 331
 332 /* 1 for registers that have pervasive standard uses
 333    and are not available for the register allocator.
 334    On the m68k, only the stack pointer is such.
 335    Our fake arg-pointer is obviously fixed as well.  */
 336 #define FIXED_REGISTERS        \
 337  {/* Data registers.  */       \
 338   0, 0, 0, 0, 0, 0, 0, 0,      \
 339                                \
 340   /* Address registers.  */    \
 341   0, 0, 0, 0, 0, 0, 0, 1,      \
 342                                \
 343   /* Floating point registers  \
 344      (if available).  */       \
 345   0, 0, 0, 0, 0, 0, 0, 0,      \
 346                                \
 347   /* Arg pointer.  */          \
 348   1 }
 349
 350 /* 1 for registers not available across function calls.
 351    These must include the FIXED_REGISTERS and also any
 352    registers that can be used without being saved.
 353    The latter must include the registers where values are returned
 354    and the register where structure-value addresses are passed.
 355    Aside from that, you can include as many other registers as you like.  */
 356 #define CALL_USED_REGISTERS     \
 357  {/* Data registers.  */        \
 358   1, 1, 0, 0, 0, 0, 0, 0,       \
 359                                 \
 360   /* Address registers.  */     \
 361   1, 1, 0, 0, 0, 0, 0, 1,       \
 362                                 \
 363   /* Floating point registers   \
 364      (if available).  */        \
 365   1, 1, 0, 0, 0, 0, 0, 0,       \
 366                                 \
 367   /* Arg pointer.  */           \
 368   1 }
 369
 370 #define REG_ALLOC_ORDER         \
 371 { /* d0/d1/a0/a1 */             \
 372   0, 1, 8, 9,                   \
 373   /* d2-d7 */                   \
 374   2, 3, 4, 5, 6, 7,             \
 375   /* a2-a7/arg */               \
 376   10, 11, 12, 13, 14, 15, 24,   \
 377   /* fp0-fp7 */                 \
 378   16, 17, 18, 19, 20, 21, 22, 23\
 379 }
 380
 381
 382 /* Make sure everything's fine if we *don't* have a given processor.
 383    This assumes that putting a register in fixed_regs will keep the
 384    compiler's mitts completely off it.  We don't bother to zero it out
 385    of register classes.  */
 386 #define CONDITIONAL_REGISTER_USAGE                              \
 387 {                                                               \
 388   int i;                                                        \
 389   HARD_REG_SET x;                                               \
 390   if (!TARGET_HARD_FLOAT)                                       \
 391     {                                                           \
 392       COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);  \
 393       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)               \
 394         if (TEST_HARD_REG_BIT (x, i))                           \
 395           fixed_regs[i] = call_used_regs[i] = 1;                \
 396     }                                                           \
 397   if (flag_pic)                                                 \
 398     fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;          \
 399 }
 400
 401 /* On the m68k, ordinary registers hold 32 bits worth;
 402    for the 68881 registers, a single register is always enough for
 403    anything that can be stored in them at all.  */
 404 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 405   ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE)       \
 406    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 407
 408 /* A C expression that is nonzero if hard register NEW_REG can be
 409    considered for use as a rename register for OLD_REG register.  */
 410
 411 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
 412   m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
 413
 414 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
 415   m68k_regno_mode_ok ((REGNO), (MODE))
 416
 417 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
 418   m68k_secondary_reload_class (CLASS, MODE, X)
 419
 420 #define MODES_TIEABLE_P(MODE1, MODE2)                   \
 421   (! TARGET_HARD_FLOAT                                  \
 422    || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT            \
 423         || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)        \
 424        == (GET_MODE_CLASS (MODE2) == MODE_FLOAT         \
 425            || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
 426
 427 /* Specify the registers used for certain standard purposes.
 428    The values of these macros are register numbers.  */
 429
 430 #define STACK_POINTER_REGNUM SP_REG
 431
 432 /* Most m68k targets use %a6 as a frame pointer.  The AmigaOS
 433    ABI uses %a6 for shared library calls, therefore the frame
 434    pointer is shifted to %a5 on this target.  */
 435 #define FRAME_POINTER_REGNUM A6_REG
 436
 437 #define FRAME_POINTER_REQUIRED 0
 438
 439 /* Base register for access to arguments of the function.
 440  * This isn't a hardware register. It will be eliminated to the
 441  * stack pointer or frame pointer.
 442  */
 443 #define ARG_POINTER_REGNUM 24
 444
 445 #define STATIC_CHAIN_REGNUM A0_REG
 446 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
 447
 448 /* Register in which address to store a structure value
 449    is passed to a function.  */
 450 #define M68K_STRUCT_VALUE_REGNUM A1_REG
 451
 452 \f
 453
 454 /* The m68k has three kinds of registers, so eight classes would be
 455    a complete set.  One of them is not needed.  */
 456 enum reg_class {
 457   NO_REGS, DATA_REGS,
 458   ADDR_REGS, FP_REGS,
 459   GENERAL_REGS, DATA_OR_FP_REGS,
 460   ADDR_OR_FP_REGS, ALL_REGS,
 461   LIM_REG_CLASSES };
 462
 463 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 464
 465 #define REG_CLASS_NAMES \
 466  { "NO_REGS", "DATA_REGS",              \
 467    "ADDR_REGS", "FP_REGS",              \
 468    "GENERAL_REGS", "DATA_OR_FP_REGS",   \
 469    "ADDR_OR_FP_REGS", "ALL_REGS" }
 470
 471 #define REG_CLASS_CONTENTS \
 472 {                                       \
 473   {0x00000000},  /* NO_REGS */          \
 474   {0x000000ff},  /* DATA_REGS */        \
 475   {0x0100ff00},  /* ADDR_REGS */        \
 476   {0x00ff0000},  /* FP_REGS */          \
 477   {0x0100ffff},  /* GENERAL_REGS */     \
 478   {0x00ff00ff},  /* DATA_OR_FP_REGS */  \
 479   {0x01ffff00},  /* ADDR_OR_FP_REGS */  \
 480   {0x01ffffff},  /* ALL_REGS */         \
 481 }
 482
 483 extern enum reg_class regno_reg_class[];
 484 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
 485 #define INDEX_REG_CLASS GENERAL_REGS
 486 #define BASE_REG_CLASS ADDR_REGS
 487
 488 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
 489   m68k_preferred_reload_class (X, CLASS)
 490
 491 /* On the m68k, this is the size of MODE in words,
 492    except in the FP regs, where a single reg is always enough.  */
 493 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 494  ((CLASS) == FP_REGS ? 1 \
 495   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 496
 497 /* Moves between fp regs and other regs are two insns.  */
 498 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)        \
 499   ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
 500 \f
 501 /* Stack layout; function entry, exit and calling.  */
 502
 503 #define STACK_GROWS_DOWNWARD 1
 504 #define FRAME_GROWS_DOWNWARD 1
 505 #define STARTING_FRAME_OFFSET 0
 506
 507 /* On the 680x0, sp@- in a byte insn really pushes a word.
 508    On the ColdFire, sp@- in a byte insn pushes just a byte.  */
 509 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
 510
 511 #define FIRST_PARM_OFFSET(FNDECL) 8
 512
 513 /* On the 68000, the RTS insn cannot pop anything.
 514    On the 68010, the RTD insn may be used to pop them if the number
 515      of args is fixed, but if the number is variable then the caller
 516      must pop them all.  RTD can't be used for library calls now
 517      because the library is compiled with the Unix compiler.
 518    Use of RTD is a selectable option, since it is incompatible with
 519    standard Unix calling sequences.  If the option is not selected,
 520    the caller must always pop the args.  */
 521 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
 522   ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE)        \
 523     && (TYPE_ARG_TYPES (FUNTYPE) == 0                           \
 524         || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))   \
 525             == void_type_node)))                                \
 526    ? (SIZE) : 0)
 527
 528 /* On the m68k the return value defaults to D0.  */
 529 #define FUNCTION_VALUE(VALTYPE, FUNC)  \
 530   gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
 531
 532 /* On the m68k the return value defaults to D0.  */
 533 #define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, D0_REG)
 534
 535 /* On the m68k, D0 is usually the only register used.  */
 536 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
 537
 538 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
 539    more than one register.
 540    XXX This macro is m68k specific and used only for m68kemb.h.  */
 541 #define NEEDS_UNTYPED_CALL 0
 542
 543 /* On the m68k, all arguments are usually pushed on the stack.  */
 544 #define FUNCTION_ARG_REGNO_P(N) 0
 545 \f
 546 /* On the m68k, this is a single integer, which is a number of bytes
 547    of arguments scanned so far.  */
 548 #define CUMULATIVE_ARGS int
 549
 550 /* On the m68k, the offset starts at 0.  */
 551 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 552  ((CUM) = 0)
 553
 554 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)    \
 555  ((CUM) += ((MODE) != BLKmode                   \
 556             ? (GET_MODE_SIZE (MODE) + 3) & ~3   \
 557             : (int_size_in_bytes (TYPE) + 3) & ~3))
 558
 559 /* On the m68k all args are always pushed.  */
 560 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
 561
 562 #define FUNCTION_PROFILER(FILE, LABELNO)  \
 563   asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
 564
 565 #define EXIT_IGNORE_STACK 1
 566
 567 /* Output assembler code for a block containing the constant parts
 568    of a trampoline, leaving space for the variable parts.
 569
 570    On the m68k, the trampoline looks like this:
 571      movl #STATIC,a0
 572      jmp  FUNCTION
 573
 574    WARNING: Targets that may run on 68040+ cpus must arrange for
 575    the instruction cache to be flushed.  Previous incarnations of
 576    the m68k trampoline code attempted to get around this by either
 577    using an out-of-line transfer function or pc-relative data, but
 578    the fact remains that the code to jump to the transfer function
 579    or the code to load the pc-relative data needs to be flushed
 580    just as much as the "variable" portion of the trampoline.
 581    Recognizing that a cache flush is going to be required anyway,
 582    dispense with such notions and build a smaller trampoline.
 583
 584    Since more instructions are required to move a template into
 585    place than to create it on the spot, don't use a template.  */
 586
 587 #define TRAMPOLINE_SIZE 12
 588 #define TRAMPOLINE_ALIGNMENT 16
 589
 590 /* Targets redefine this to invoke code to either flush the cache,
 591    or enable stack execution (or both).  */
 592 #ifndef FINALIZE_TRAMPOLINE
 593 #define FINALIZE_TRAMPOLINE(TRAMP)
 594 #endif
 595
 596 /* We generate a two-instructions program at address TRAMP :
 597         movea.l &CXT,%a0
 598         jmp FNADDR  */
 599 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                       \
 600 {                                                                       \
 601   emit_move_insn (gen_rtx_MEM (HImode, TRAMP),                          \
 602                   GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));    \
 603   emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
 604   emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)),       \
 605                   GEN_INT(0x4EF9));                                     \
 606   emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
 607   FINALIZE_TRAMPOLINE(TRAMP);                                           \
 608 }
 609
 610 /* This is the library routine that is used to transfer control from the
 611    trampoline to the actual nested function.  It is defined for backward
 612    compatibility, for linking with object code that used the old trampoline
 613    definition.
 614
 615    A colon is used with no explicit operands to cause the template string
 616    to be scanned for %-constructs.
 617
 618    The function name __transfer_from_trampoline is not actually used.
 619    The function definition just permits use of "asm with operands"
 620    (though the operand list is empty).  */
 621 #define TRANSFER_FROM_TRAMPOLINE                                \
 622 void                                                            \
 623 __transfer_from_trampoline ()                                   \
 624 {                                                               \
 625   register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME);           \
 626   asm (GLOBAL_ASM_OP "___trampoline");                          \
 627   asm ("___trampoline:");                                       \
 628   asm volatile ("move%.l %0,%@" : : "m" (a0[22]));              \
 629   asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18]));    \
 630   asm ("rts":);                                                 \
 631 }
 632 \f
 633 /* There are two registers that can always be eliminated on the m68k.
 634    The frame pointer and the arg pointer can be replaced by either the
 635    hard frame pointer or to the stack pointer, depending upon the
 636    circumstances.  The hard frame pointer is not used before reload and
 637    so it is not eligible for elimination.  */
 638 #define ELIMINABLE_REGS                                 \
 639 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },          \
 640  { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },          \
 641  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
 642
 643 #define CAN_ELIMINATE(FROM, TO) \
 644   ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
 645
 646 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                    \
 647   (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
 648 \f
 649 /* Addressing modes, and classification of registers for them.  */
 650
 651 #define HAVE_POST_INCREMENT 1
 652 #define HAVE_PRE_DECREMENT 1
 653
 654 /* Macros to check register numbers against specific register classes.  */
 655
 656 /* True for data registers, D0 through D7.  */
 657 #define DATA_REGNO_P(REGNO) ((unsigned int) (REGNO) < 8)
 658
 659 /* True for address registers, A0 through A7.  */
 660 #define ADDRESS_REGNO_P(REGNO) (((unsigned int) (REGNO) - 8) < 8)
 661
 662 /* True for integer registers, D0 through D7 and A0 through A7.  */
 663 #define INT_REGNO_P(REGNO) ((unsigned int) (REGNO) < 16)
 664
 665 /* True for floating point registers, FP0 through FP7.  */
 666 #define FP_REGNO_P(REGNO) (((unsigned int) (REGNO) - 16) < 8)
 667
 668 #define REGNO_OK_FOR_INDEX_P(REGNO)                     \
 669   (INT_REGNO_P (REGNO)                                  \
 670    || INT_REGNO_P (reg_renumber[REGNO]))
 671
 672 #define REGNO_OK_FOR_BASE_P(REGNO)                      \
 673   (ADDRESS_REGNO_P (REGNO)                              \
 674    || ADDRESS_REGNO_P (reg_renumber[REGNO]))
 675
 676 #define REGNO_OK_FOR_DATA_P(REGNO)                      \
 677   (DATA_REGNO_P (REGNO)                                 \
 678    || DATA_REGNO_P (reg_renumber[REGNO]))
 679
 680 #define REGNO_OK_FOR_FP_P(REGNO)                        \
 681   (FP_REGNO_P (REGNO)                                   \
 682    || FP_REGNO_P (reg_renumber[REGNO]))
 683
 684 /* Now macros that check whether X is a register and also,
 685    strictly, whether it is in a specified class.
 686
 687    These macros are specific to the m68k, and may be used only
 688    in code for printing assembler insns and in conditions for
 689    define_optimization.  */
 690
 691 /* 1 if X is a data register.  */
 692 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
 693
 694 /* 1 if X is an fp register.  */
 695 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
 696
 697 /* 1 if X is an address register  */
 698 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
 699 \f
 700 /* True if SYMBOL + OFFSET constants must refer to something within
 701    SYMBOL's section.  */
 702 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
 703 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
 704 #endif
 705
 706 #define MAX_REGS_PER_ADDRESS 2
 707
 708 #define CONSTANT_ADDRESS_P(X)                                           \
 709   ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF             \
 710     || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST               \
 711     || GET_CODE (X) == HIGH)                                            \
 712    && LEGITIMATE_CONSTANT_P (X))
 713
 714 /* Nonzero if the constant value X is a legitimate general operand.
 715    It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 716 #define LEGITIMATE_CONSTANT_P(X)                                \
 717   (GET_MODE (X) != XFmode                                       \
 718    && !m68k_illegitimate_symbolic_constant_p (X))
 719
 720 #ifndef REG_OK_STRICT
 721 #define REG_STRICT_P 0
 722 #else
 723 #define REG_STRICT_P 1
 724 #endif
 725
 726 #define LEGITIMATE_PIC_OPERAND_P(X)                             \
 727   (!symbolic_operand (X, VOIDmode)                              \
 728    || (TARGET_PCREL && REG_STRICT_P))
 729
 730 #define REG_OK_FOR_BASE_P(X) \
 731   m68k_legitimate_base_reg_p (X, REG_STRICT_P)
 732
 733 #define REG_OK_FOR_INDEX_P(X) \
 734   m68k_legitimate_index_reg_p (X, REG_STRICT_P)
 735
 736 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)                         \
 737   do                                                                    \
 738     {                                                                   \
 739       if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P))            \
 740         goto ADDR;                                                      \
 741     }                                                                   \
 742   while (0)
 743
 744 /* Don't call memory_address_noforce for the address to fetch
 745    the switch offset.  This address is ok as it stands,
 746    but memory_address_noforce would alter it.  */
 747 #define PIC_CASE_VECTOR_ADDRESS(index) index
 748 \f
 749 /* For the 68000, we handle X+REG by loading X into a register R and
 750    using R+REG.  R will go in an address reg and indexing will be used.
 751    However, if REG is a broken-out memory address or multiplication,
 752    nothing needs to be done because REG can certainly go in an address reg.  */
 753 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
 754 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)   \
 755 { register int ch = (X) != (OLDX);                                      \
 756   if (GET_CODE (X) == PLUS)                                             \
 757     { int copied = 0;                                                   \
 758       if (GET_CODE (XEXP (X, 0)) == MULT)                               \
 759         { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
 760       if (GET_CODE (XEXP (X, 1)) == MULT)                               \
 761         { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
 762       if (ch && GET_CODE (XEXP (X, 1)) == REG                           \
 763           && GET_CODE (XEXP (X, 0)) == REG)                             \
 764         { if (TARGET_COLDFIRE_FPU                                       \
 765               && GET_MODE_CLASS (MODE) == MODE_FLOAT)                   \
 766             { COPY_ONCE (X); X = force_operand (X, 0);}                 \
 767           goto WIN; }                                                   \
 768       if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); }              \
 769       if (GET_CODE (XEXP (X, 0)) == REG                                 \
 770                || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND                \
 771                    && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG           \
 772                    && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode))      \
 773         { register rtx temp = gen_reg_rtx (Pmode);                      \
 774           register rtx val = force_operand (XEXP (X, 1), 0);            \
 775           emit_move_insn (temp, val);                                   \
 776           COPY_ONCE (X);                                                \
 777           XEXP (X, 1) = temp;                                           \
 778           if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
 779               && GET_CODE (XEXP (X, 0)) == REG)                         \
 780             X = force_operand (X, 0);                                   \
 781           goto WIN; }                                                   \
 782       else if (GET_CODE (XEXP (X, 1)) == REG                            \
 783                || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND                \
 784                    && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG           \
 785                    && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode))      \
 786         { register rtx temp = gen_reg_rtx (Pmode);                      \
 787           register rtx val = force_operand (XEXP (X, 0), 0);            \
 788           emit_move_insn (temp, val);                                   \
 789           COPY_ONCE (X);                                                \
 790           XEXP (X, 0) = temp;                                           \
 791           if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
 792               && GET_CODE (XEXP (X, 1)) == REG)                         \
 793             X = force_operand (X, 0);                                   \
 794           goto WIN; }}}
 795
 796 /* On the 68000, only predecrement and postincrement address depend thus
 797    (the amount of decrement or increment being the length of the operand).
 798    These are now treated generically in recog.c.  */
 799 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
 800 \f
 801 #define CASE_VECTOR_MODE HImode
 802 #define CASE_VECTOR_PC_RELATIVE 1
 803
 804 #define DEFAULT_SIGNED_CHAR 1
 805 #define MOVE_MAX 4
 806 #define SLOW_BYTE_ACCESS 0
 807
 808 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 809
 810 /* The ColdFire FF1 instruction returns 32 for zero. */
 811 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
 812
 813 #define STORE_FLAG_VALUE (-1)
 814
 815 #define Pmode SImode
 816 #define FUNCTION_MODE QImode
 817
 818 \f
 819 /* Tell final.c how to eliminate redundant test instructions.  */
 820
 821 /* Here we define machine-dependent flags and fields in cc_status
 822    (see `conditions.h').  */
 823
 824 /* Set if the cc value is actually in the 68881, so a floating point
 825    conditional branch must be output.  */
 826 #define CC_IN_68881 04000
 827
 828 /* On the 68000, all the insns to store in an address register fail to
 829    set the cc's.  However, in some cases these instructions can make it
 830    possibly invalid to use the saved cc's.  In those cases we clear out
 831    some or all of the saved cc's so they won't be used.  */
 832 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
 833
 834 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV)  \
 835 do { if (cc_prev_status.flags & CC_IN_68881)                    \
 836     return FLOAT;                                               \
 837   if (cc_prev_status.flags & CC_NO_OVERFLOW)                    \
 838     return NO_OV;                                               \
 839   return NORMAL; } while (0)
 840 \f
 841 /* Control the assembler format that we output.  */
 842
 843 #define ASM_APP_ON "#APP\n"
 844 #define ASM_APP_OFF "#NO_APP\n"
 845 #define TEXT_SECTION_ASM_OP "\t.text"
 846 #define DATA_SECTION_ASM_OP "\t.data"
 847 #define GLOBAL_ASM_OP "\t.globl\t"
 848 #define REGISTER_PREFIX ""
 849 #define LOCAL_LABEL_PREFIX ""
 850 #define USER_LABEL_PREFIX "_"
 851 #define IMMEDIATE_PREFIX "#"
 852
 853 #define REGISTER_NAMES \
 854 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
 855  REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
 856  REGISTER_PREFIX"d6", REGISTER_PREFIX"d7",                      \
 857  REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
 858  REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
 859  REGISTER_PREFIX"a6", REGISTER_PREFIX"sp",                      \
 860  REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
 861  REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
 862  REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
 863
 864 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
 865
 866 /* Return a register name by index, handling %fp nicely.
 867    We don't replace %fp for targets that don't map it to %a6
 868    since it may confuse GAS.  */
 869 #define M68K_REGNAME(r) ( \
 870   ((FRAME_POINTER_REGNUM == A6_REG) \
 871     && ((r) == FRAME_POINTER_REGNUM) \
 872     && frame_pointer_needed) ? \
 873     M68K_FP_REG_NAME : reg_names[(r)])
 874
 875 /* On the Sun-3, the floating point registers have numbers
 876    18 to 25, not 16 to 23 as they do in the compiler.  */
 877 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
 878
 879 /* Before the prologue, RA is at 0(%sp).  */
 880 #define INCOMING_RETURN_ADDR_RTX \
 881   gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
 882
 883 /* After the prologue, RA is at 4(AP) in the current frame.  */
 884 #define RETURN_ADDR_RTX(COUNT, FRAME)                                      \
 885   ((COUNT) == 0                                                            \
 886    ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
 887    : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
 888
 889 /* We must not use the DBX register numbers for the DWARF 2 CFA column
 890    numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
 891    Instead use the identity mapping.  */
 892 #define DWARF_FRAME_REGNUM(REG) \
 893   (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
 894
 895 /* The return column was originally 24, but gcc used 25 for a while too.
 896    Define both registers 24 and 25 as Pmode ones and use 24 in our own
 897    unwind information.  */
 898 #define DWARF_FRAME_REGISTERS 25
 899 #define DWARF_FRAME_RETURN_COLUMN 24
 900 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
 901
 902 /* Before the prologue, the top of the frame is at 4(%sp).  */
 903 #define INCOMING_FRAME_SP_OFFSET 4
 904
 905 /* All registers are live on exit from an interrupt routine.  */
 906 #define EPILOGUE_USES(REGNO)                                    \
 907   (reload_completed                                             \
 908    && (m68k_get_function_kind (current_function_decl)   \
 909        == m68k_fk_interrupt_handler))
 910
 911 /* Describe how we implement __builtin_eh_return.  */
 912 #define EH_RETURN_DATA_REGNO(N) \
 913   ((N) < 2 ? (N) : INVALID_REGNUM)
 914 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, A0_REG)
 915 #define EH_RETURN_HANDLER_RTX                                       \
 916   gen_rtx_MEM (Pmode,                                               \
 917                gen_rtx_PLUS (Pmode, arg_pointer_rtx,                \
 918                              plus_constant (EH_RETURN_STACKADJ_RTX, \
 919                                             UNITS_PER_WORD)))
 920
 921 /* Select a format to encode pointers in exception handling data.  CODE
 922    is 0 for data, 1 for code labels, 2 for function pointers.  GLOBAL is
 923    true if the symbol may be affected by dynamic relocations.
 924
 925    TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
 926    a read-only text segment without imposing a fixed gap between the
 927    text and data segments.  As a result, the text segment cannot refer
 928    to anything in the data segment, even in PC-relative form.  Because
 929    .eh_frame refers to both code and data, it follows that .eh_frame
 930    must be in the data segment itself, and that the offset between
 931    .eh_frame and code will not be a link-time constant.
 932
 933    In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
 934    | DW_EH_PE_indirect for all code references.  However, gcc currently
 935    handles indirect references using a per-TU constant pool.  This means
 936    that if a function and its eh_frame are removed by the linker, the
 937    eh_frame's indirect references to the removed function will not be
 938    removed, leading to an unresolved symbol error.
 939
 940    It isn't clear that any -msep-data or -mid-shared-library target
 941    would benefit from a read-only .eh_frame anyway.  In particular,
 942    no known target that supports these options has a feature like
 943    PT_GNU_RELRO.  Without any such feature to motivate them, indirect
 944    references would be unnecessary bloat, so we simply use an absolute
 945    pointer for code and global references.  We still use pc-relative
 946    references to data, as this avoids a relocation.  */
 947 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                         \
 948   (flag_pic                                                                \
 949    && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA)                      \
 950         && ((GLOBAL) || (CODE)))                                           \
 951    ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
 952    : DW_EH_PE_absptr)
 953
 954 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
 955   asm_fprintf (FILE, "%U%s", NAME)
 956
 957 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)   \
 958   sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
 959
 960 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO)                 \
 961   asm_fprintf (FILE, (MOTOROLA                          \
 962                       ? "\tmove.l %s,-(%Rsp)\n"         \
 963                       : "\tmovel %s,%Rsp@-\n"),         \
 964                reg_names[REGNO])
 965
 966 #define ASM_OUTPUT_REG_POP(FILE,REGNO)                  \
 967   asm_fprintf (FILE, (MOTOROLA                          \
 968                       ? "\tmove.l (%Rsp)+,%s\n"         \
 969                       : "\tmovel %Rsp@+,%s\n"),         \
 970                reg_names[REGNO])
 971
 972 /* The m68k does not use absolute case-vectors, but we must define this macro
 973    anyway.  */
 974 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
 975   asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
 976
 977 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
 978   asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
 979
 980 /* We don't have a way to align to more than a two-byte boundary, so do the
 981    best we can and don't complain.  */
 982 #define ASM_OUTPUT_ALIGN(FILE,LOG)      \
 983   if ((LOG) >= 1)                       \
 984     fprintf (FILE, "\t.even\n");
 985
 986 #define ASM_OUTPUT_SKIP(FILE,SIZE)  \
 987   fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
 988
 989 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
 990 ( fputs (".comm ", (FILE)),                     \
 991   assemble_name ((FILE), (NAME)),               \
 992   fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
 993
 994 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)  \
 995 ( fputs (".lcomm ", (FILE)),                    \
 996   assemble_name ((FILE), (NAME)),               \
 997   fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
 998
 999 /* Output a float value (represented as a C double) as an immediate operand.
1000    This macro is m68k-specific.  */
1001 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE)               \
1002  do {                                                           \
1003       if (CODE == 'f')                                          \
1004         {                                                       \
1005           char dstr[30];                                        \
1006           real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1007           asm_fprintf ((FILE), "%I0r%s", dstr);                 \
1008         }                                                       \
1009       else                                                      \
1010         {                                                       \
1011           long l;                                               \
1012           REAL_VALUE_TO_TARGET_SINGLE (VALUE, l);               \
1013           asm_fprintf ((FILE), "%I0x%lx", l);                   \
1014         }                                                       \
1015      } while (0)
1016
1017 /* Output a double value (represented as a C double) as an immediate operand.
1018    This macro is m68k-specific.  */
1019 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE)                           \
1020  do { char dstr[30];                                                    \
1021       real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1);            \
1022       asm_fprintf (FILE, "%I0r%s", dstr);                               \
1023     } while (0)
1024
1025 /* Note, long double immediate operands are not actually
1026    generated by m68k.md.  */
1027 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE)                      \
1028  do { char dstr[30];                                                    \
1029       real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1);            \
1030       asm_fprintf (FILE, "%I0r%s", dstr);                               \
1031     } while (0)
1032
1033 /* On the 68000, we use several CODE characters:
1034    '.' for dot needed in Motorola-style opcode names.
1035    '-' for an operand pushing on the stack:
1036        sp@-, -(sp) or -(%sp) depending on the style of syntax.
1037    '+' for an operand pushing on the stack:
1038        sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1039    '@' for a reference to the top word on the stack:
1040        sp@, (sp) or (%sp) depending on the style of syntax.
1041    '#' for an immediate operand prefix (# in MIT and Motorola syntax
1042        but & in SGS syntax).
1043    '!' for the fpcr register (used in some float-to-fixed conversions).
1044    '$' for the letter `s' in an op code, but only on the 68040.
1045    '&' for the letter `d' in an op code, but only on the 68040.
1046    '/' for register prefix needed by longlong.h.
1047    '?' for m68k_library_id_string
1048
1049    'b' for byte insn (no effect, on the Sun; this is for the ISI).
1050    'd' to force memory addressing to be absolute, not relative.
1051    'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1052    'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1053        or print pair of registers as rx:ry.  */
1054
1055 #define PRINT_OPERAND_PUNCT_VALID_P(CODE)                               \
1056   ((CODE) == '.' || (CODE) == '#' || (CODE) == '-'                      \
1057    || (CODE) == '+' || (CODE) == '@' || (CODE) == '!'                   \
1058    || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
1059
1060
1061 /* See m68k.c for the m68k specific codes.  */
1062 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1063
1064 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1065
1066 /* Values used in the MICROARCH argument to M68K_DEVICE.  */
1067 enum uarch_type
1068 {
1069   u68000,
1070   u68010,
1071   u68020,
1072   u68020_40,
1073   u68020_60,
1074   u68030,
1075   u68040,
1076   u68060,
1077   ucpu32,
1078   ucfv2,
1079   ucfv3,
1080   ucfv4,
1081   ucfv4e,
1082   ucfv5,
1083   unk_arch
1084 };
1085
1086 /* An enumeration of all supported target devices.  */
1087 enum target_device
1088 {
1089 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1090   ENUM_VALUE,
1091 #include "m68k-devices.def"
1092 #undef M68K_DEVICE
1093   unk_device
1094 };
1095
1096 enum fpu_type
1097 {
1098   FPUTYPE_NONE,
1099   FPUTYPE_68881,
1100   FPUTYPE_COLDFIRE
1101 };
1102
1103 enum m68k_function_kind
1104 {
1105   m68k_fk_normal_function,
1106   m68k_fk_interrupt_handler,
1107   m68k_fk_interrupt_thread
1108 };
1109
1110 /* Variables in m68k.c; see there for details.  */
1111 extern const char *m68k_library_id_string;
1112 extern int m68k_last_compare_had_fp_operands;
1113 extern enum target_device m68k_cpu;
1114 extern enum uarch_type m68k_tune;
1115 extern enum fpu_type m68k_fpu;
1116 extern unsigned int m68k_cpu_flags;
1117 extern const char *m68k_symbolic_call;
1118 extern const char *m68k_symbolic_jump;