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[gcc.git] / gcc / config / m68k / m68k.h
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
26 #if MOTOROLA /* Use the Motorola assembly syntax. */
27 #else
28 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
29 #endif
30
31 /* Handle --with-cpu default option from configure script. */
32 #define OPTION_DEFAULT_SPECS \
33 { "cpu", "%{!m68020-40:%{!m68020-60:\
34 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}" },
35
36 /* Pass flags to gas indicating which type of processor we have. This
37 can be simplified when we can rely on the assembler supporting .cpu
38 and .arch directives. */
39
40 #define ASM_CPU_SPEC "\
41 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
42 %{m68020-40:-m68040}%{m68020-60:-m68040}\
43 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
44 "
45 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
46 %{msep-data|mid-shared-library:--pcrel} \
47 "
48
49 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
50
51 #define EXTRA_SPECS \
52 { "asm_cpu_spec", ASM_CPU_SPEC }, \
53 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
54 SUBTARGET_EXTRA_SPECS
55
56 #define SUBTARGET_EXTRA_SPECS
57
58 /* Note that some other tm.h files include this one and then override
59 many of the definitions that relate to assembler syntax. */
60
61 #define TARGET_CPU_CPP_BUILTINS() \
62 do \
63 { \
64 builtin_define ("__m68k__"); \
65 builtin_define_std ("mc68000"); \
66 /* The other mc680x0 macros have traditionally been derived \
67 from the tuning setting. For example, -m68020-60 defines \
68 m68060, even though it generates pure 68020 code. */ \
69 switch (m68k_tune) \
70 { \
71 case u68010: \
72 builtin_define_std ("mc68010"); \
73 break; \
74 \
75 case u68020: \
76 builtin_define_std ("mc68020"); \
77 break; \
78 \
79 case u68030: \
80 builtin_define_std ("mc68030"); \
81 break; \
82 \
83 case u68040: \
84 builtin_define_std ("mc68040"); \
85 break; \
86 \
87 case u68060: \
88 builtin_define_std ("mc68060"); \
89 break; \
90 \
91 case u68020_60: \
92 builtin_define_std ("mc68060"); \
93 /* Fall through. */ \
94 case u68020_40: \
95 builtin_define_std ("mc68040"); \
96 builtin_define_std ("mc68030"); \
97 builtin_define_std ("mc68020"); \
98 break; \
99 \
100 case ucpu32: \
101 builtin_define_std ("mc68332"); \
102 builtin_define_std ("mcpu32"); \
103 builtin_define_std ("mc68020"); \
104 break; \
105 \
106 case ucfv1: \
107 builtin_define ("__mcfv1__"); \
108 break; \
109 \
110 case ucfv2: \
111 builtin_define ("__mcfv2__"); \
112 break; \
113 \
114 case ucfv3: \
115 builtin_define ("__mcfv3__"); \
116 break; \
117 \
118 case ucfv4: \
119 builtin_define ("__mcfv4__"); \
120 break; \
121 \
122 case ucfv4e: \
123 builtin_define ("__mcfv4e__"); \
124 break; \
125 \
126 case ucfv5: \
127 builtin_define ("__mcfv5__"); \
128 break; \
129 \
130 default: \
131 break; \
132 } \
133 \
134 if (TARGET_68881) \
135 builtin_define ("__HAVE_68881__"); \
136 \
137 if (TARGET_COLDFIRE) \
138 { \
139 const char *tmp; \
140 \
141 tmp = m68k_cpp_cpu_ident ("cf"); \
142 if (tmp) \
143 builtin_define (tmp); \
144 tmp = m68k_cpp_cpu_family ("cf"); \
145 if (tmp) \
146 builtin_define (tmp); \
147 builtin_define ("__mcoldfire__"); \
148 \
149 if (TARGET_ISAC) \
150 builtin_define ("__mcfisac__"); \
151 else if (TARGET_ISAB) \
152 { \
153 builtin_define ("__mcfisab__"); \
154 /* ISA_B: Legacy 5407 defines. */ \
155 builtin_define ("__mcf5400__"); \
156 builtin_define ("__mcf5407__"); \
157 } \
158 else if (TARGET_ISAAPLUS) \
159 { \
160 builtin_define ("__mcfisaaplus__"); \
161 /* ISA_A+: legacy defines. */ \
162 builtin_define ("__mcf528x__"); \
163 builtin_define ("__mcf5200__"); \
164 } \
165 else \
166 { \
167 builtin_define ("__mcfisaa__"); \
168 /* ISA_A: legacy defines. */ \
169 switch (m68k_tune) \
170 { \
171 case ucfv2: \
172 builtin_define ("__mcf5200__"); \
173 break; \
174 \
175 case ucfv3: \
176 builtin_define ("__mcf5307__"); \
177 builtin_define ("__mcf5300__"); \
178 break; \
179 \
180 default: \
181 break; \
182 } \
183 } \
184 } \
185 \
186 if (TARGET_COLDFIRE_FPU) \
187 builtin_define ("__mcffpu__"); \
188 \
189 if (TARGET_CF_HWDIV) \
190 builtin_define ("__mcfhwdiv__"); \
191 \
192 if (TARGET_FIDOA) \
193 builtin_define ("__mfido__"); \
194 \
195 builtin_assert ("cpu=m68k"); \
196 builtin_assert ("machine=m68k"); \
197 } \
198 while (0)
199
200 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
201 quantities. */
202 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
203 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
204 #define INT_OP_NO_DOT 2 /* byte, short, long */
205 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
206
207 /* Set the default. */
208 #define INT_OP_GROUP INT_OP_DOT_WORD
209
210 /* Bit values used by m68k-devices.def to identify processor capabilities. */
211 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
212 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
213 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
214 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
215 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
216 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
217 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
218 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
219 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
220 #define FL_ISA_68000 (1 << 9)
221 #define FL_ISA_68010 (1 << 10)
222 #define FL_ISA_68020 (1 << 11)
223 #define FL_ISA_68040 (1 << 12)
224 #define FL_ISA_A (1 << 13)
225 #define FL_ISA_APLUS (1 << 14)
226 #define FL_ISA_B (1 << 15)
227 #define FL_ISA_C (1 << 16)
228 #define FL_FIDOA (1 << 17)
229 #define FL_MMU 0 /* Used by multilib machinery. */
230 #define FL_UCLINUX 0 /* Used by multilib machinery. */
231
232 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
233 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
234 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
235 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
236 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
237 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
238 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
239
240 /* Size (in bytes) of FPU registers. */
241 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
242
243 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
244 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
245 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
246
247 /* Some instructions are common to more than one ISA. */
248 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
249 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
250
251 #define TUNE_68000 (m68k_tune == u68000)
252 #define TUNE_68010 (m68k_tune == u68010)
253 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
254 #define TUNE_68030 (m68k_tune == u68030 \
255 || m68k_tune == u68020_40 \
256 || m68k_tune == u68020_60)
257 #define TUNE_68040 (m68k_tune == u68040 \
258 || m68k_tune == u68020_40 \
259 || m68k_tune == u68020_60)
260 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
261 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
262 #define TUNE_CPU32 (m68k_tune == ucpu32)
263 #define TUNE_CFV1 (m68k_tune == ucfv1)
264 #define TUNE_CFV2 (m68k_tune == ucfv2)
265 #define TUNE_CFV3 (m68k_tune == ucfv3)
266 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e)
267
268 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0)
269 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0)
270
271 /* These are meant to be redefined in the host dependent files */
272 #define SUBTARGET_OVERRIDE_OPTIONS
273 \f
274 /* target machine storage layout */
275
276 /* "long double" is the same as "double" on ColdFire and fido
277 targets. */
278
279 #define LONG_DOUBLE_TYPE_SIZE \
280 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
281
282 /* We need to know the size of long double at compile-time in libgcc2. */
283
284 #if defined(__mcoldfire__) || defined(__mfido__)
285 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
286 #else
287 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
288 #endif
289
290 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
291 instructions, we get proper intermediate rounding, otherwise we
292 get extended precision results. */
293 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
294
295 #define BITS_BIG_ENDIAN 1
296 #define BYTES_BIG_ENDIAN 1
297 #define WORDS_BIG_ENDIAN 1
298
299 #define UNITS_PER_WORD 4
300
301 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
302 #define STACK_BOUNDARY 16
303 #define FUNCTION_BOUNDARY 16
304 #define EMPTY_FIELD_BOUNDARY 16
305 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
306 #define PREFERRED_STACK_BOUNDARY \
307 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
308
309 /* No data type wants to be aligned rounder than this.
310 Most published ABIs say that ints should be aligned on 16-bit
311 boundaries, but CPUs with 32-bit busses get better performance
312 aligned on 32-bit boundaries. */
313 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
314
315 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
316 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
317
318 #define DWARF_CIE_DATA_ALIGNMENT -2
319
320 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
321
322 /* Define these to avoid dependence on meaning of `int'. */
323 #define WCHAR_TYPE "long int"
324 #define WCHAR_TYPE_SIZE 32
325
326 /* Maximum number of library IDs we permit with -mid-shared-library. */
327 #define MAX_LIBRARY_ID 255
328
329 \f
330 /* Standard register usage. */
331
332 /* For the m68k, we give the data registers numbers 0-7,
333 the address registers numbers 010-017 (8-15),
334 and the 68881 floating point registers numbers 020-027 (16-23).
335 We also have a fake `arg-pointer' register 030 (24) used for
336 register elimination. */
337 #define FIRST_PSEUDO_REGISTER 25
338
339 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
340 #define PIC_OFFSET_TABLE_REGNUM \
341 (!flag_pic ? INVALID_REGNUM \
342 : reload_completed ? REGNO (pic_offset_table_rtx) \
343 : PIC_REG)
344
345 /* 1 for registers that have pervasive standard uses
346 and are not available for the register allocator.
347 On the m68k, only the stack pointer is such.
348 Our fake arg-pointer is obviously fixed as well. */
349 #define FIXED_REGISTERS \
350 {/* Data registers. */ \
351 0, 0, 0, 0, 0, 0, 0, 0, \
352 \
353 /* Address registers. */ \
354 0, 0, 0, 0, 0, 0, 0, 1, \
355 \
356 /* Floating point registers \
357 (if available). */ \
358 0, 0, 0, 0, 0, 0, 0, 0, \
359 \
360 /* Arg pointer. */ \
361 1 }
362
363 /* 1 for registers not available across function calls.
364 These must include the FIXED_REGISTERS and also any
365 registers that can be used without being saved.
366 The latter must include the registers where values are returned
367 and the register where structure-value addresses are passed.
368 Aside from that, you can include as many other registers as you like. */
369 #define CALL_USED_REGISTERS \
370 {/* Data registers. */ \
371 1, 1, 0, 0, 0, 0, 0, 0, \
372 \
373 /* Address registers. */ \
374 1, 1, 0, 0, 0, 0, 0, 1, \
375 \
376 /* Floating point registers \
377 (if available). */ \
378 1, 1, 0, 0, 0, 0, 0, 0, \
379 \
380 /* Arg pointer. */ \
381 1 }
382
383 #define REG_ALLOC_ORDER \
384 { /* d0/d1/a0/a1 */ \
385 0, 1, 8, 9, \
386 /* d2-d7 */ \
387 2, 3, 4, 5, 6, 7, \
388 /* a2-a7/arg */ \
389 10, 11, 12, 13, 14, 15, 24, \
390 /* fp0-fp7 */ \
391 16, 17, 18, 19, 20, 21, 22, 23\
392 }
393
394
395 /* On the m68k, ordinary registers hold 32 bits worth;
396 for the 68881 registers, a single register is always enough for
397 anything that can be stored in them at all. */
398 #define HARD_REGNO_NREGS(REGNO, MODE) \
399 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
400 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
401
402 /* A C expression that is nonzero if hard register NEW_REG can be
403 considered for use as a rename register for OLD_REG register. */
404
405 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
406 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
407
408 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
409 m68k_regno_mode_ok ((REGNO), (MODE))
410
411 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
412 m68k_secondary_reload_class (CLASS, MODE, X)
413
414 #define MODES_TIEABLE_P(MODE1, MODE2) \
415 (! TARGET_HARD_FLOAT \
416 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
417 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
418 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
419 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
420
421 /* Specify the registers used for certain standard purposes.
422 The values of these macros are register numbers. */
423
424 #define STACK_POINTER_REGNUM SP_REG
425
426 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
427 ABI uses %a6 for shared library calls, therefore the frame
428 pointer is shifted to %a5 on this target. */
429 #define FRAME_POINTER_REGNUM A6_REG
430
431 /* Base register for access to arguments of the function.
432 * This isn't a hardware register. It will be eliminated to the
433 * stack pointer or frame pointer.
434 */
435 #define ARG_POINTER_REGNUM 24
436
437 #define STATIC_CHAIN_REGNUM A0_REG
438 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
439
440 /* Register in which address to store a structure value
441 is passed to a function. */
442 #define M68K_STRUCT_VALUE_REGNUM A1_REG
443
444 \f
445
446 /* The m68k has three kinds of registers, so eight classes would be
447 a complete set. One of them is not needed. */
448 enum reg_class {
449 NO_REGS, DATA_REGS,
450 ADDR_REGS, FP_REGS,
451 GENERAL_REGS, DATA_OR_FP_REGS,
452 ADDR_OR_FP_REGS, ALL_REGS,
453 LIM_REG_CLASSES };
454
455 #define N_REG_CLASSES (int) LIM_REG_CLASSES
456
457 #define REG_CLASS_NAMES \
458 { "NO_REGS", "DATA_REGS", \
459 "ADDR_REGS", "FP_REGS", \
460 "GENERAL_REGS", "DATA_OR_FP_REGS", \
461 "ADDR_OR_FP_REGS", "ALL_REGS" }
462
463 #define REG_CLASS_CONTENTS \
464 { \
465 {0x00000000}, /* NO_REGS */ \
466 {0x000000ff}, /* DATA_REGS */ \
467 {0x0100ff00}, /* ADDR_REGS */ \
468 {0x00ff0000}, /* FP_REGS */ \
469 {0x0100ffff}, /* GENERAL_REGS */ \
470 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
471 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
472 {0x01ffffff}, /* ALL_REGS */ \
473 }
474
475 extern enum reg_class regno_reg_class[];
476 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
477 #define INDEX_REG_CLASS GENERAL_REGS
478 #define BASE_REG_CLASS ADDR_REGS
479
480 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
481 m68k_preferred_reload_class (X, CLASS)
482
483 /* On the m68k, this is the size of MODE in words,
484 except in the FP regs, where a single reg is always enough. */
485 #define CLASS_MAX_NREGS(CLASS, MODE) \
486 ((CLASS) == FP_REGS ? 1 \
487 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
488
489 /* Moves between fp regs and other regs are two insns. */
490 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
491 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
492
493 \f
494 /* Stack layout; function entry, exit and calling. */
495
496 #define STACK_GROWS_DOWNWARD 1
497 #define FRAME_GROWS_DOWNWARD 1
498 #define STARTING_FRAME_OFFSET 0
499
500 /* On the 680x0, sp@- in a byte insn really pushes a word.
501 On the ColdFire, sp@- in a byte insn pushes just a byte. */
502 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
503
504 #define FIRST_PARM_OFFSET(FNDECL) 8
505
506 /* On the m68k the return value defaults to D0. */
507 #define FUNCTION_VALUE(VALTYPE, FUNC) \
508 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
509
510 /* On the m68k the return value defaults to D0. */
511 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
512
513 /* On the m68k, D0 is usually the only register used. */
514 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
515
516 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
517 more than one register.
518 XXX This macro is m68k specific and used only for m68kemb.h. */
519 #define NEEDS_UNTYPED_CALL 0
520
521 /* On the m68k, all arguments are usually pushed on the stack. */
522 #define FUNCTION_ARG_REGNO_P(N) 0
523 \f
524 /* On the m68k, this is a single integer, which is a number of bytes
525 of arguments scanned so far. */
526 #define CUMULATIVE_ARGS int
527
528 /* On the m68k, the offset starts at 0. */
529 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
530 ((CUM) = 0)
531
532 #define FUNCTION_PROFILER(FILE, LABELNO) \
533 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
534
535 #define EXIT_IGNORE_STACK 1
536
537 /* Output assembler code for a block containing the constant parts
538 of a trampoline, leaving space for the variable parts.
539
540 On the m68k, the trampoline looks like this:
541 movl #STATIC,a0
542 jmp FUNCTION
543
544 WARNING: Targets that may run on 68040+ cpus must arrange for
545 the instruction cache to be flushed. Previous incarnations of
546 the m68k trampoline code attempted to get around this by either
547 using an out-of-line transfer function or pc-relative data, but
548 the fact remains that the code to jump to the transfer function
549 or the code to load the pc-relative data needs to be flushed
550 just as much as the "variable" portion of the trampoline.
551 Recognizing that a cache flush is going to be required anyway,
552 dispense with such notions and build a smaller trampoline.
553
554 Since more instructions are required to move a template into
555 place than to create it on the spot, don't use a template. */
556
557 #define TRAMPOLINE_SIZE 12
558 #define TRAMPOLINE_ALIGNMENT 16
559
560 /* Targets redefine this to invoke code to either flush the cache,
561 or enable stack execution (or both). */
562 #ifndef FINALIZE_TRAMPOLINE
563 #define FINALIZE_TRAMPOLINE(TRAMP)
564 #endif
565
566 /* This is the library routine that is used to transfer control from the
567 trampoline to the actual nested function. It is defined for backward
568 compatibility, for linking with object code that used the old trampoline
569 definition.
570
571 A colon is used with no explicit operands to cause the template string
572 to be scanned for %-constructs.
573
574 The function name __transfer_from_trampoline is not actually used.
575 The function definition just permits use of "asm with operands"
576 (though the operand list is empty). */
577 #define TRANSFER_FROM_TRAMPOLINE \
578 void \
579 __transfer_from_trampoline () \
580 { \
581 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
582 asm (GLOBAL_ASM_OP "___trampoline"); \
583 asm ("___trampoline:"); \
584 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
585 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
586 asm ("rts":); \
587 }
588 \f
589 /* There are two registers that can always be eliminated on the m68k.
590 The frame pointer and the arg pointer can be replaced by either the
591 hard frame pointer or to the stack pointer, depending upon the
592 circumstances. The hard frame pointer is not used before reload and
593 so it is not eligible for elimination. */
594 #define ELIMINABLE_REGS \
595 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
596 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
597 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
598
599 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
600 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
601 \f
602 /* Addressing modes, and classification of registers for them. */
603
604 #define HAVE_POST_INCREMENT 1
605 #define HAVE_PRE_DECREMENT 1
606
607 /* Macros to check register numbers against specific register classes. */
608
609 /* True for data registers, D0 through D7. */
610 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
611
612 /* True for address registers, A0 through A7. */
613 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
614
615 /* True for integer registers, D0 through D7 and A0 through A7. */
616 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
617
618 /* True for floating point registers, FP0 through FP7. */
619 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
620
621 #define REGNO_OK_FOR_INDEX_P(REGNO) \
622 (INT_REGNO_P (REGNO) \
623 || INT_REGNO_P (reg_renumber[REGNO]))
624
625 #define REGNO_OK_FOR_BASE_P(REGNO) \
626 (ADDRESS_REGNO_P (REGNO) \
627 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
628
629 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
630 (INT_REGNO_P (REGNO) \
631 || REGNO == ARG_POINTER_REGNUM \
632 || REGNO >= FIRST_PSEUDO_REGISTER)
633
634 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
635 (ADDRESS_REGNO_P (REGNO) \
636 || REGNO == ARG_POINTER_REGNUM \
637 || REGNO >= FIRST_PSEUDO_REGISTER)
638
639 /* Now macros that check whether X is a register and also,
640 strictly, whether it is in a specified class.
641
642 These macros are specific to the m68k, and may be used only
643 in code for printing assembler insns and in conditions for
644 define_optimization. */
645
646 /* 1 if X is a data register. */
647 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
648
649 /* 1 if X is an fp register. */
650 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
651
652 /* 1 if X is an address register */
653 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
654 \f
655 /* True if SYMBOL + OFFSET constants must refer to something within
656 SYMBOL's section. */
657 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
658 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
659 #endif
660
661 #define MAX_REGS_PER_ADDRESS 2
662
663 #define CONSTANT_ADDRESS_P(X) \
664 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
665 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
666 || GET_CODE (X) == HIGH) \
667 && m68k_legitimate_constant_p (Pmode, X))
668
669 #ifndef REG_OK_STRICT
670 #define REG_STRICT_P 0
671 #else
672 #define REG_STRICT_P 1
673 #endif
674
675 #define LEGITIMATE_PIC_OPERAND_P(X) \
676 (!symbolic_operand (X, VOIDmode) \
677 || (TARGET_PCREL && REG_STRICT_P) \
678 || m68k_tls_reference_p (X, true))
679
680 #define REG_OK_FOR_BASE_P(X) \
681 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
682
683 #define REG_OK_FOR_INDEX_P(X) \
684 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
685
686 \f
687 /* This address is OK as it stands. */
688 #define PIC_CASE_VECTOR_ADDRESS(index) index
689 #define CASE_VECTOR_MODE HImode
690 #define CASE_VECTOR_PC_RELATIVE 1
691
692 #define DEFAULT_SIGNED_CHAR 1
693 #define MOVE_MAX 4
694 #define SLOW_BYTE_ACCESS 0
695
696 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
697
698 /* The ColdFire FF1 instruction returns 32 for zero. */
699 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
700
701 #define STORE_FLAG_VALUE (-1)
702
703 #define Pmode SImode
704 #define FUNCTION_MODE QImode
705
706 \f
707 /* Tell final.c how to eliminate redundant test instructions. */
708
709 /* Here we define machine-dependent flags and fields in cc_status
710 (see `conditions.h'). */
711
712 /* Set if the cc value is actually in the 68881, so a floating point
713 conditional branch must be output. */
714 #define CC_IN_68881 04000
715
716 /* On the 68000, all the insns to store in an address register fail to
717 set the cc's. However, in some cases these instructions can make it
718 possibly invalid to use the saved cc's. In those cases we clear out
719 some or all of the saved cc's so they won't be used. */
720 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
721
722 /* The shift instructions always clear the overflow bit. */
723 #define CC_OVERFLOW_UNUSABLE 01000
724
725 /* The shift instructions use the carry bit in a way not compatible with
726 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose.
727 Rename it to something more understandable. */
728 #define CC_NO_CARRY CC_NO_OVERFLOW
729
730 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
731 do { if (cc_prev_status.flags & CC_IN_68881) \
732 return FLOAT; \
733 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
734 return NO_OV; \
735 return NORMAL; } while (0)
736 \f
737 /* Control the assembler format that we output. */
738
739 #define ASM_APP_ON "#APP\n"
740 #define ASM_APP_OFF "#NO_APP\n"
741 #define TEXT_SECTION_ASM_OP "\t.text"
742 #define DATA_SECTION_ASM_OP "\t.data"
743 #define GLOBAL_ASM_OP "\t.globl\t"
744 #define REGISTER_PREFIX ""
745 #define LOCAL_LABEL_PREFIX ""
746 #define USER_LABEL_PREFIX "_"
747 #define IMMEDIATE_PREFIX "#"
748
749 #define REGISTER_NAMES \
750 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
751 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
752 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
753 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
754 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
755 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
756 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
757 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
758 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
759
760 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
761
762 /* Return a register name by index, handling %fp nicely.
763 We don't replace %fp for targets that don't map it to %a6
764 since it may confuse GAS. */
765 #define M68K_REGNAME(r) ( \
766 ((FRAME_POINTER_REGNUM == A6_REG) \
767 && ((r) == FRAME_POINTER_REGNUM) \
768 && frame_pointer_needed) ? \
769 M68K_FP_REG_NAME : reg_names[(r)])
770
771 /* On the Sun-3, the floating point registers have numbers
772 18 to 25, not 16 to 23 as they do in the compiler. */
773 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
774
775 /* Before the prologue, RA is at 0(%sp). */
776 #define INCOMING_RETURN_ADDR_RTX \
777 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
778
779 /* After the prologue, RA is at 4(AP) in the current frame. */
780 #define RETURN_ADDR_RTX(COUNT, FRAME) \
781 ((COUNT) == 0 \
782 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
783 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
784
785 /* We must not use the DBX register numbers for the DWARF 2 CFA column
786 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
787 Instead use the identity mapping. */
788 #define DWARF_FRAME_REGNUM(REG) \
789 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
790
791 /* The return column was originally 24, but gcc used 25 for a while too.
792 Define both registers 24 and 25 as Pmode ones and use 24 in our own
793 unwind information. */
794 #define DWARF_FRAME_REGISTERS 25
795 #define DWARF_FRAME_RETURN_COLUMN 24
796 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
797
798 /* Before the prologue, the top of the frame is at 4(%sp). */
799 #define INCOMING_FRAME_SP_OFFSET 4
800
801 /* All registers are live on exit from an interrupt routine. */
802 #define EPILOGUE_USES(REGNO) \
803 (reload_completed \
804 && (m68k_get_function_kind (current_function_decl) \
805 == m68k_fk_interrupt_handler))
806
807 /* Describe how we implement __builtin_eh_return. */
808 #define EH_RETURN_DATA_REGNO(N) \
809 ((N) < 2 ? (N) : INVALID_REGNUM)
810 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
811 #define EH_RETURN_HANDLER_RTX \
812 gen_rtx_MEM (Pmode, \
813 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
814 plus_constant (EH_RETURN_STACKADJ_RTX, \
815 UNITS_PER_WORD)))
816
817 /* Select a format to encode pointers in exception handling data. CODE
818 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
819 true if the symbol may be affected by dynamic relocations.
820
821 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
822 a read-only text segment without imposing a fixed gap between the
823 text and data segments. As a result, the text segment cannot refer
824 to anything in the data segment, even in PC-relative form. Because
825 .eh_frame refers to both code and data, it follows that .eh_frame
826 must be in the data segment itself, and that the offset between
827 .eh_frame and code will not be a link-time constant.
828
829 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
830 | DW_EH_PE_indirect for all code references. However, gcc currently
831 handles indirect references using a per-TU constant pool. This means
832 that if a function and its eh_frame are removed by the linker, the
833 eh_frame's indirect references to the removed function will not be
834 removed, leading to an unresolved symbol error.
835
836 It isn't clear that any -msep-data or -mid-shared-library target
837 would benefit from a read-only .eh_frame anyway. In particular,
838 no known target that supports these options has a feature like
839 PT_GNU_RELRO. Without any such feature to motivate them, indirect
840 references would be unnecessary bloat, so we simply use an absolute
841 pointer for code and global references. We still use pc-relative
842 references to data, as this avoids a relocation. */
843 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
844 (flag_pic \
845 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
846 && ((GLOBAL) || (CODE))) \
847 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
848 : DW_EH_PE_absptr)
849
850 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
851 asm_fprintf (FILE, "%U%s", NAME)
852
853 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
854 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
855
856 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
857 asm_fprintf (FILE, (MOTOROLA \
858 ? "\tmove.l %s,-(%Rsp)\n" \
859 : "\tmovel %s,%Rsp@-\n"), \
860 reg_names[REGNO])
861
862 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
863 asm_fprintf (FILE, (MOTOROLA \
864 ? "\tmove.l (%Rsp)+,%s\n" \
865 : "\tmovel %Rsp@+,%s\n"), \
866 reg_names[REGNO])
867
868 /* The m68k does not use absolute case-vectors, but we must define this macro
869 anyway. */
870 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
871 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
872
873 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
874 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
875
876 /* We don't have a way to align to more than a two-byte boundary, so do the
877 best we can and don't complain. */
878 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
879 if ((LOG) >= 1) \
880 fprintf (FILE, "\t.even\n");
881
882 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN
883 /* Use "move.l %a4,%a4" to advance within code. */
884 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
885 if ((LOG) > 0) \
886 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG));
887 #endif
888
889 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
890 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
891
892 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
893 ( fputs (".comm ", (FILE)), \
894 assemble_name ((FILE), (NAME)), \
895 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
896
897 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
898 ( fputs (".lcomm ", (FILE)), \
899 assemble_name ((FILE), (NAME)), \
900 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
901
902 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
903 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS)
904
905 /* On the 68000, we use several CODE characters:
906 '.' for dot needed in Motorola-style opcode names.
907 '-' for an operand pushing on the stack:
908 sp@-, -(sp) or -(%sp) depending on the style of syntax.
909 '+' for an operand pushing on the stack:
910 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
911 '@' for a reference to the top word on the stack:
912 sp@, (sp) or (%sp) depending on the style of syntax.
913 '#' for an immediate operand prefix (# in MIT and Motorola syntax
914 but & in SGS syntax).
915 '!' for the fpcr register (used in some float-to-fixed conversions).
916 '$' for the letter `s' in an op code, but only on the 68040.
917 '&' for the letter `d' in an op code, but only on the 68040.
918 '/' for register prefix needed by longlong.h.
919 '?' for m68k_library_id_string
920
921 'b' for byte insn (no effect, on the Sun; this is for the ISI).
922 'd' to force memory addressing to be absolute, not relative.
923 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
924 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
925 or print pair of registers as rx:ry. */
926
927 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
928 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
929 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
930 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
931
932
933 /* See m68k.c for the m68k specific codes. */
934 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
935
936 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
937
938 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
939 do { \
940 if (! m68k_output_addr_const_extra (FILE, (X))) \
941 goto FAIL; \
942 } while (0);
943
944 #include "config/m68k/m68k-opts.h"
945
946 enum fpu_type
947 {
948 FPUTYPE_NONE,
949 FPUTYPE_68881,
950 FPUTYPE_COLDFIRE
951 };
952
953 enum m68k_function_kind
954 {
955 m68k_fk_normal_function,
956 m68k_fk_interrupt_handler,
957 m68k_fk_interrupt_thread
958 };
959
960 /* Variables in m68k.c; see there for details. */
961 extern enum target_device m68k_cpu;
962 extern enum uarch_type m68k_tune;
963 extern enum fpu_type m68k_fpu;
964 extern unsigned int m68k_cpu_flags;
965 extern unsigned int m68k_tune_flags;
966 extern const char *m68k_symbolic_call;
967 extern const char *m68k_symbolic_jump;
968
969 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
970 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
971
972 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
973
974 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
975 Workaround that. */
976 #ifdef HOST_WIDE_INT
977 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
978 M68K_CONST_METHOD;
979
980 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
981 #endif
982
983 extern void m68k_emit_move_double (rtx [2]);
984
985 extern int m68k_sched_address_bypass_p (rtx, rtx);
986 extern int m68k_sched_indexed_address_bypass_p (rtx, rtx);
987
988 #define CPU_UNITS_QUERY 1