1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 97, 98 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
832 return output_btst (operands, operands[1], operands[0], insn, 7);
834 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
835 return output_btst (operands, operands[1], operands[0], insn, 31);
838 ;; This is the same as the above pattern except for the constraints.
839 ;; The 'o' has been replaced with 'Q'.
842 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
844 (match_operand:SI 1 "const_int_operand" "n")))]
848 if (GET_CODE (operands[0]) == MEM)
850 operands[0] = adj_offsettable_operand (operands[0],
851 INTVAL (operands[1]) / 8);
852 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
853 return output_btst (operands, operands[1], operands[0], insn, 7);
855 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
856 return output_btst (operands, operands[1], operands[0], insn, 31);
862 ;; A special case in which it is not desirable
863 ;; to reload the constant into a data register.
864 (define_insn "pushexthisi_const"
865 [(set (match_operand:SI 0 "push_operand" "=m")
866 (match_operand:SI 1 "const_int_operand" "J"))]
867 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
870 if (operands[1] == const0_rtx)
871 return \"clr%.l %0\";
876 ;(define_insn "swapsi"
877 ; [(set (match_operand:SI 0 "general_operand" "+r")
878 ; (match_operand:SI 1 "general_operand" "+r"))
879 ; (set (match_dup 1) (match_dup 0))]
883 ;; Special case of fullword move when source is zero.
884 ;; The reason this is special is to avoid loading a zero
885 ;; into a data reg with moveq in order to store it elsewhere.
887 (define_insn "movsi_const0"
888 [(set (match_operand:SI 0 "general_operand" "=g")
890 ;; clr insns on 68000 read before writing.
891 ;; This isn't so on the 68010, but we have no TARGET_68010.
892 "((TARGET_68020 || TARGET_5200)
893 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
896 if (ADDRESS_REG_P (operands[0]))
898 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
899 if (!TARGET_68040 && !TARGET_68060)
900 return \"sub%.l %0,%0\";
905 /* Many SGS assemblers croak on size specifiers for constants. */
908 return \"lea 0.w,%0\";
911 return \"lea 0:w,%0\";
915 /* moveq is faster on the 68000. */
916 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
917 #if defined(MOTOROLA) && !defined(CRDS)
918 return \"moveq%.l %#0,%0\";
920 return \"moveq %#0,%0\";
922 return \"clr%.l %0\";
925 ;; General case of fullword move.
927 ;; This is the main "hook" for PIC code. When generating
928 ;; PIC, movsi is responsible for determining when the source address
929 ;; needs PIC relocation and appropriately calling legitimize_pic_address
930 ;; to perform the actual relocation.
932 ;; In both the PIC and non-PIC cases the patterns generated will
933 ;; matched by the next define_insn.
934 (define_expand "movsi"
935 [(set (match_operand:SI 0 "general_operand" "")
936 (match_operand:SI 1 "general_operand" ""))]
940 if (flag_pic && symbolic_operand (operands[1], SImode))
942 /* The source is an address which requires PIC relocation.
943 Call legitimize_pic_address with the source, mode, and a relocation
944 register (a new pseudo, or the final destination if reload_in_progress
945 is set). Then fall through normally */
946 extern rtx legitimize_pic_address();
947 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
948 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
952 ;; General case of fullword move. The register constraints
953 ;; force integer constants in range for a moveq to be reloaded
954 ;; if they are headed for memory.
956 ;; Notes: make sure no alternative allows g vs g.
957 ;; We don't allow f-regs since fixed point cannot go in them.
958 ;; We do allow y and x regs since fixed point is allowed in them.
959 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
960 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
964 if (which_alternative == 3)
965 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
966 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
967 return \"fpmove%.l %x1,%x0\";
968 return output_move_simode (operands);
972 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
973 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
975 "* return output_move_simode (operands);")
977 (define_expand "movhi"
978 [(set (match_operand:HI 0 "general_operand" "")
979 (match_operand:HI 1 "general_operand" ""))]
984 [(set (match_operand:HI 0 "general_operand" "=g")
985 (match_operand:HI 1 "general_operand" "g"))]
987 "* return output_move_himode (operands);")
990 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
991 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
993 "* return output_move_himode (operands);")
995 (define_expand "movstricthi"
996 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
997 (match_operand:HI 1 "general_operand" ""))]
1002 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1003 (match_operand:HI 1 "general_operand" "rmn"))]
1005 "* return output_move_stricthi (operands);")
1008 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1009 (match_operand:HI 1 "general_operand" "rmn,r"))]
1011 "* return output_move_stricthi (operands);")
1013 (define_expand "movqi"
1014 [(set (match_operand:QI 0 "general_operand" "")
1015 (match_operand:QI 1 "general_operand" ""))]
1020 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1021 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1023 "* return output_move_qimode (operands);")
1026 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
1027 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
1029 "* return output_move_qimode (operands);")
1031 (define_expand "movstrictqi"
1032 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1033 (match_operand:QI 1 "general_operand" ""))]
1038 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1039 (match_operand:QI 1 "general_operand" "dmn"))]
1041 "* return output_move_strictqi (operands);")
1044 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1045 (match_operand:QI 1 "general_operand" "dmn,d"))]
1047 "* return output_move_strictqi (operands);")
1049 (define_expand "movsf"
1050 [(set (match_operand:SF 0 "general_operand" "")
1051 (match_operand:SF 1 "general_operand" ""))]
1056 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1057 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1058 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1059 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1063 if (which_alternative >= 4)
1064 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1065 if (FPA_REG_P (operands[0]))
1067 if (FPA_REG_P (operands[1]))
1068 return \"fpmove%.s %x1,%x0\";
1069 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1070 return output_move_const_single (operands);
1071 else if (FP_REG_P (operands[1]))
1072 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1073 return \"fpmove%.s %x1,%x0\";
1075 if (FPA_REG_P (operands[1]))
1077 if (FP_REG_P (operands[0]))
1078 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1080 return \"fpmove%.s %x1,%x0\";
1082 if (FP_REG_P (operands[0]))
1084 if (FP_REG_P (operands[1]))
1085 return \"f%$move%.x %1,%0\";
1086 else if (ADDRESS_REG_P (operands[1]))
1087 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1088 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1089 return output_move_const_single (operands);
1090 return \"f%$move%.s %f1,%0\";
1092 if (FP_REG_P (operands[1]))
1094 if (ADDRESS_REG_P (operands[0]))
1095 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1096 return \"fmove%.s %f1,%0\";
1098 if (operands[1] == CONST0_RTX (SFmode)
1099 /* clr insns on 68000 read before writing.
1100 This isn't so on the 68010, but we have no TARGET_68010. */
1101 && ((TARGET_68020 || TARGET_5200)
1102 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1104 if (ADDRESS_REG_P (operands[0]))
1106 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1107 if (!TARGET_68040 && !TARGET_68060)
1108 return \"sub%.l %0,%0\";
1113 /* Many SGS assemblers croak on size specifiers for constants. */
1114 return \"lea 0,%0\";
1116 return \"lea 0.w,%0\";
1119 return \"lea 0:w,%0\";
1123 /* moveq is faster on the 68000. */
1124 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1126 #if defined(MOTOROLA) && !defined(CRDS)
1127 return \"moveq%.l %#0,%0\";
1129 return \"moveq %#0,%0\";
1132 return \"clr%.l %0\";
1134 return \"move%.l %1,%0\";
1138 [(set (match_operand:SF 0 "general_operand" "=r,g")
1139 (match_operand:SF 1 "general_operand" "g,r"))]
1141 "* return \"move%.l %1,%0\";")
1143 (define_expand "movdf"
1144 [(set (match_operand:DF 0 "general_operand" "")
1145 (match_operand:DF 1 "general_operand" ""))]
1150 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1151 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1152 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1153 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1157 if (which_alternative == 7)
1158 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1159 if (FPA_REG_P (operands[0]))
1161 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1162 return output_move_const_double (operands);
1163 if (FP_REG_P (operands[1]))
1164 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1165 return \"fpmove%.d %x1,%x0\";
1167 else if (FPA_REG_P (operands[1]))
1169 if (FP_REG_P(operands[0]))
1170 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1172 return \"fpmove%.d %x1,%x0\";
1174 if (FP_REG_P (operands[0]))
1176 if (FP_REG_P (operands[1]))
1177 return \"f%&move%.x %1,%0\";
1178 if (REG_P (operands[1]))
1181 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1182 output_asm_insn (\"move%.l %1,%-\", xoperands);
1183 output_asm_insn (\"move%.l %1,%-\", operands);
1184 return \"f%&move%.d %+,%0\";
1186 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1187 return output_move_const_double (operands);
1188 return \"f%&move%.d %f1,%0\";
1190 else if (FP_REG_P (operands[1]))
1192 if (REG_P (operands[0]))
1194 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1195 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1196 return \"move%.l %+,%0\";
1199 return \"fmove%.d %f1,%0\";
1201 return output_move_double (operands);
1205 [(set (match_operand:DF 0 "general_operand" "=r,g")
1206 (match_operand:DF 1 "general_operand" "g,r"))]
1208 "* return output_move_double (operands);")
1210 (define_expand "movxf"
1211 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1212 (match_operand:XF 1 "general_operand" ""))]
1216 if (CONSTANT_P (operands[1]))
1218 operands[1] = force_const_mem (XFmode, operands[1]);
1219 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1220 && ! reload_in_progress)
1221 operands[1] = change_address (operands[1], XFmode,
1222 XEXP (operands[1], 0));
1227 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1228 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1232 if (FP_REG_P (operands[0]))
1234 if (FP_REG_P (operands[1]))
1235 return \"fmove%.x %1,%0\";
1236 if (REG_P (operands[1]))
1239 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1240 output_asm_insn (\"move%.l %1,%-\", xoperands);
1241 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1242 output_asm_insn (\"move%.l %1,%-\", xoperands);
1243 output_asm_insn (\"move%.l %1,%-\", operands);
1244 return \"fmove%.x %+,%0\";
1246 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1247 return \"fmove%.x %1,%0\";
1248 return \"fmove%.x %f1,%0\";
1250 if (REG_P (operands[0]))
1252 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1253 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1254 output_asm_insn (\"move%.l %+,%0\", operands);
1255 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1256 return \"move%.l %+,%0\";
1258 return \"fmove%.x %f1,%0\";
1263 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1264 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1265 "! TARGET_68881 && ! TARGET_5200"
1268 if (FP_REG_P (operands[0]))
1270 if (FP_REG_P (operands[1]))
1271 return \"fmove%.x %1,%0\";
1272 if (REG_P (operands[1]))
1275 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1276 output_asm_insn (\"move%.l %1,%-\", xoperands);
1277 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1278 output_asm_insn (\"move%.l %1,%-\", xoperands);
1279 output_asm_insn (\"move%.l %1,%-\", operands);
1280 return \"fmove%.x %+,%0\";
1282 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1283 return \"fmove%.x %1,%0\";
1284 return \"fmove%.x %f1,%0\";
1286 if (FP_REG_P (operands[1]))
1288 if (REG_P (operands[0]))
1290 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1291 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1292 output_asm_insn (\"move%.l %+,%0\", operands);
1293 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1294 return \"move%.l %+,%0\";
1297 return \"fmove%.x %f1,%0\";
1299 return output_move_double (operands);
1304 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1305 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1306 "! TARGET_68881 && TARGET_5200"
1307 "* return output_move_double (operands);")
1309 (define_expand "movdi"
1310 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1311 [(set (match_operand:DI 0 "general_operand" "")
1312 (match_operand:DI 1 "general_operand" ""))]
1316 ;; movdi can apply to fp regs in some cases
1318 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1319 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1320 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1321 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1322 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1323 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1324 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1328 if (which_alternative == 8)
1329 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1330 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1331 return \"fpmove%.d %x1,%x0\";
1332 if (FP_REG_P (operands[0]))
1334 if (FP_REG_P (operands[1]))
1335 return \"fmove%.x %1,%0\";
1336 if (REG_P (operands[1]))
1339 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1340 output_asm_insn (\"move%.l %1,%-\", xoperands);
1341 output_asm_insn (\"move%.l %1,%-\", operands);
1342 return \"fmove%.d %+,%0\";
1344 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1345 return output_move_const_double (operands);
1346 return \"fmove%.d %f1,%0\";
1348 else if (FP_REG_P (operands[1]))
1350 if (REG_P (operands[0]))
1352 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1353 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1354 return \"move%.l %+,%0\";
1357 return \"fmove%.d %f1,%0\";
1359 return output_move_double (operands);
1363 [(set (match_operand:DI 0 "general_operand" "=r,g")
1364 (match_operand:DI 1 "general_operand" "g,r"))]
1366 "* return output_move_double (operands);")
1368 ;; Thus goes after the move instructions
1369 ;; because the move instructions are better (require no spilling)
1370 ;; when they can apply. It goes before the add/sub insns
1371 ;; so we will prefer it to them.
1373 (define_insn "pushasi"
1374 [(set (match_operand:SI 0 "push_operand" "=m")
1375 (match_operand:SI 1 "address_operand" "p"))]
1379 ;; truncation instructions
1380 (define_insn "truncsiqi2"
1381 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1383 (match_operand:SI 1 "general_operand" "doJ,i")))]
1387 if (GET_CODE (operands[0]) == REG)
1389 /* Must clear condition codes, since the move.l bases them on
1390 the entire 32 bits, not just the desired 8 bits. */
1392 return \"move%.l %1,%0\";
1394 if (GET_CODE (operands[1]) == MEM)
1395 operands[1] = adj_offsettable_operand (operands[1], 3);
1396 return \"move%.b %1,%0\";
1399 (define_insn "trunchiqi2"
1400 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1402 (match_operand:HI 1 "general_operand" "doJ,i")))]
1406 if (GET_CODE (operands[0]) == REG
1407 && (GET_CODE (operands[1]) == MEM
1408 || GET_CODE (operands[1]) == CONST_INT))
1410 /* Must clear condition codes, since the move.w bases them on
1411 the entire 16 bits, not just the desired 8 bits. */
1413 return \"move%.w %1,%0\";
1415 if (GET_CODE (operands[0]) == REG)
1417 /* Must clear condition codes, since the move.l bases them on
1418 the entire 32 bits, not just the desired 8 bits. */
1420 return \"move%.l %1,%0\";
1422 if (GET_CODE (operands[1]) == MEM)
1423 operands[1] = adj_offsettable_operand (operands[1], 1);
1424 return \"move%.b %1,%0\";
1427 (define_insn "truncsihi2"
1428 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1430 (match_operand:SI 1 "general_operand" "roJ,i")))]
1434 if (GET_CODE (operands[0]) == REG)
1436 /* Must clear condition codes, since the move.l bases them on
1437 the entire 32 bits, not just the desired 8 bits. */
1439 return \"move%.l %1,%0\";
1441 if (GET_CODE (operands[1]) == MEM)
1442 operands[1] = adj_offsettable_operand (operands[1], 2);
1443 return \"move%.w %1,%0\";
1446 ;; zero extension instructions
1448 (define_insn "zero_extendqidi2"
1449 [(set (match_operand:DI 0 "general_operand" "=&d")
1450 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1455 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1456 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1459 (define_insn "zero_extendhidi2"
1460 [(set (match_operand:DI 0 "general_operand" "=&d")
1461 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1466 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1467 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1470 ;; this is the canonical form for (lshiftrt:DI x 32)
1471 (define_insn "zero_extendsidi2"
1472 [(set (match_operand:DI 0 "general_operand" "rm")
1473 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1478 if (GET_CODE (operands[0]) == REG)
1479 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1480 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1481 return \"move%.l %1,%0\;clr%.l %0\";
1482 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1483 return \"clr%.l %0\;move%.l %1,%0\";
1485 operands[2] = adj_offsettable_operand (operands[0], 4);
1486 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[1]) != REG
1487 || REGNO (operands[1]) != REGNO (operands[2]))
1488 output_asm_insn (\"move%.l %1,%2\", operands);
1489 if (ADDRESS_REG_P (operands[0]))
1490 return \"sub%.l %0,%0\";
1492 return \"clr%.l %0\";
1495 (define_expand "zero_extendhisi2"
1496 [(set (match_operand:SI 0 "register_operand" "")
1498 (set (strict_low_part (match_dup 2))
1499 (match_operand:HI 1 "general_operand" ""))]
1503 operands[1] = make_safe_from (operands[1], operands[0]);
1504 if (GET_CODE (operands[0]) == SUBREG)
1505 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1506 SUBREG_WORD (operands[0]));
1508 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1511 (define_expand "zero_extendqihi2"
1512 [(set (match_operand:HI 0 "register_operand" "")
1514 (set (strict_low_part (match_dup 2))
1515 (match_operand:QI 1 "general_operand" ""))]
1519 operands[1] = make_safe_from (operands[1], operands[0]);
1520 if (GET_CODE (operands[0]) == SUBREG)
1521 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1522 SUBREG_WORD (operands[0]));
1524 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1527 (define_expand "zero_extendqisi2"
1528 [(set (match_operand:SI 0 "register_operand" "")
1530 (set (strict_low_part (match_dup 2))
1531 (match_operand:QI 1 "general_operand" ""))]
1535 operands[1] = make_safe_from (operands[1], operands[0]);
1536 if (GET_CODE (operands[0]) == SUBREG)
1537 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1538 SUBREG_WORD (operands[0]));
1540 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1543 ;; Patterns to recognize zero-extend insns produced by the combiner.
1544 ;; We don't allow both operands in memory, because of aliasing problems.
1545 ;; Explicitly disallow two memory operands via the condition since reloading
1546 ;; of this case will result in worse code than the uncombined patterns.
1549 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1550 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1551 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1554 if (DATA_REG_P (operands[0]))
1556 if (GET_CODE (operands[1]) == REG
1557 && REGNO (operands[0]) == REGNO (operands[1]))
1558 return \"and%.l %#0xFFFF,%0\";
1559 if (reg_mentioned_p (operands[0], operands[1]))
1560 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1561 return \"clr%.l %0\;move%.w %1,%0\";
1563 else if (GET_CODE (operands[0]) == MEM
1564 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1565 return \"move%.w %1,%0\;clr%.w %0\";
1566 else if (GET_CODE (operands[0]) == MEM
1567 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1568 return \"clr%.w %0\;move%.w %1,%0\";
1571 output_asm_insn (\"clr%.w %0\", operands);
1572 operands[0] = adj_offsettable_operand (operands[0], 2);
1573 return \"move%.w %1,%0\";
1578 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1579 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1580 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1583 if (DATA_REG_P (operands[0]))
1585 if (GET_CODE (operands[1]) == REG
1586 && REGNO (operands[0]) == REGNO (operands[1]))
1587 return \"and%.w %#0xFF,%0\";
1588 if (reg_mentioned_p (operands[0], operands[1]))
1589 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1590 return \"clr%.w %0\;move%.b %1,%0\";
1592 else if (GET_CODE (operands[0]) == MEM
1593 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1595 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1596 == STACK_POINTER_REGNUM)
1598 output_asm_insn (\"clr%.w %-\", operands);
1599 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1600 plus_constant (stack_pointer_rtx, 1));
1601 return \"move%.b %1,%0\";
1604 return \"move%.b %1,%0\;clr%.b %0\";
1606 else if (GET_CODE (operands[0]) == MEM
1607 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1608 return \"clr%.b %0\;move%.b %1,%0\";
1611 output_asm_insn (\"clr%.b %0\", operands);
1612 operands[0] = adj_offsettable_operand (operands[0], 1);
1613 return \"move%.b %1,%0\";
1618 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1619 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1620 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1623 if (DATA_REG_P (operands[0]))
1625 if (GET_CODE (operands[1]) == REG
1626 && REGNO (operands[0]) == REGNO (operands[1]))
1627 return \"and%.l %#0xFF,%0\";
1628 if (reg_mentioned_p (operands[0], operands[1]))
1629 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1630 return \"clr%.l %0\;move%.b %1,%0\";
1632 else if (GET_CODE (operands[0]) == MEM
1633 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1635 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1638 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1640 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1643 return \"clrl %0@-\;moveb %1,%0@(3)\";
1646 else if (GET_CODE (operands[0]) == MEM
1647 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1649 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1652 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1654 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1657 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1662 output_asm_insn (\"clr%.l %0\", operands);
1663 operands[0] = adj_offsettable_operand (operands[0], 3);
1664 return \"move%.b %1,%0\";
1668 ;; sign extension instructions
1670 (define_insn "extendqidi2"
1671 [(set (match_operand:DI 0 "general_operand" "=d")
1673 (match_operand:QI 1 "general_operand" "rm")))]
1678 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1679 if (TARGET_68020 || TARGET_5200)
1680 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1682 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1685 (define_insn "extendhidi2"
1686 [(set (match_operand:DI 0 "general_operand" "=d")
1688 (match_operand:HI 1 "general_operand" "rm")))]
1693 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1694 if (TARGET_68020 || TARGET_5200)
1695 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1697 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1700 (define_insn "extendsidi2"
1701 [(set (match_operand:DI 0 "general_operand" "=d")
1703 (match_operand:SI 1 "general_operand" "rm")))]
1708 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1709 if (TARGET_68020 || TARGET_5200)
1710 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1712 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1715 ;; Special case when one can avoid register clobbering, copy and test
1716 ;; Maybe there is a way to make that the general case, by forcing the
1717 ;; result of the SI tree to be in the lower register of the DI target
1719 (define_insn "extendplussidi"
1720 [(set (match_operand:DI 0 "register_operand" "=d")
1721 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1722 (match_operand:SI 2 "general_operand" "rmn"))))]
1727 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1728 if (GET_CODE (operands[1]) == CONST_INT
1729 && (unsigned) INTVAL (operands[1]) > 8)
1731 rtx tmp = operands[1];
1733 operands[1] = operands[2];
1736 if (GET_CODE (operands[1]) == REG
1737 && REGNO (operands[1]) == REGNO (operands[3]))
1738 output_asm_insn (\"add%.l %2,%3\", operands);
1740 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1741 if (TARGET_68020 || TARGET_5200)
1742 return \"smi %0\;extb%.l %0\";
1744 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1747 (define_insn "extendhisi2"
1748 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1750 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1754 if (ADDRESS_REG_P (operands[0]))
1755 return \"move%.w %1,%0\";
1756 return \"ext%.l %0\";
1759 (define_insn "extendqihi2"
1760 [(set (match_operand:HI 0 "general_operand" "=d")
1761 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1765 (define_insn "extendqisi2"
1766 [(set (match_operand:SI 0 "general_operand" "=d")
1767 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1768 "TARGET_68020 || TARGET_5200"
1771 ;; Conversions between float and double.
1773 (define_expand "extendsfdf2"
1774 [(set (match_operand:DF 0 "general_operand" "")
1776 (match_operand:SF 1 "general_operand" "")))]
1777 "TARGET_68881 || TARGET_FPA"
1781 [(set (match_operand:DF 0 "general_operand" "=x,y")
1783 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1788 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1790 (match_operand:SF 1 "general_operand" "f,dmF")))]
1794 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1796 if (REGNO (operands[0]) == REGNO (operands[1]))
1798 /* Extending float to double in an fp-reg is a no-op.
1799 NOTICE_UPDATE_CC has already assumed that the
1800 cc will be set. So cancel what it did. */
1801 cc_status = cc_prev_status;
1804 return \"f%&move%.x %1,%0\";
1806 if (FP_REG_P (operands[0]))
1807 return \"f%&move%.s %f1,%0\";
1808 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1810 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1811 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1812 return \"move%.l %+,%0\";
1814 return \"fmove%.d %f1,%0\";
1817 ;; This cannot output into an f-reg because there is no way to be
1818 ;; sure of truncating in that case.
1819 ;; But on the Sun FPA, we can be sure.
1820 (define_expand "truncdfsf2"
1821 [(set (match_operand:SF 0 "general_operand" "")
1823 (match_operand:DF 1 "general_operand" "")))]
1824 "TARGET_68881 || TARGET_FPA"
1828 [(set (match_operand:SF 0 "general_operand" "=x,y")
1830 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1834 ;; On the '040 we can truncate in a register accurately and easily.
1836 [(set (match_operand:SF 0 "general_operand" "=f")
1838 (match_operand:DF 1 "general_operand" "fmG")))]
1842 if (FP_REG_P (operands[1]))
1843 return \"f%$move%.x %1,%0\";
1844 return \"f%$move%.d %f1,%0\";
1848 [(set (match_operand:SF 0 "general_operand" "=dm")
1850 (match_operand:DF 1 "general_operand" "f")))]
1854 ;; Conversion between fixed point and floating point.
1855 ;; Note that among the fix-to-float insns
1856 ;; the ones that start with SImode come first.
1857 ;; That is so that an operand that is a CONST_INT
1858 ;; (and therefore lacks a specific machine mode).
1859 ;; will be recognized as SImode (which is always valid)
1860 ;; rather than as QImode or HImode.
1862 (define_expand "floatsisf2"
1863 [(set (match_operand:SF 0 "general_operand" "")
1864 (float:SF (match_operand:SI 1 "general_operand" "")))]
1865 "TARGET_68881 || TARGET_FPA"
1869 [(set (match_operand:SF 0 "general_operand" "=y,x")
1870 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1875 [(set (match_operand:SF 0 "general_operand" "=f")
1876 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1880 (define_expand "floatsidf2"
1881 [(set (match_operand:DF 0 "general_operand" "")
1882 (float:DF (match_operand:SI 1 "general_operand" "")))]
1883 "TARGET_68881 || TARGET_FPA"
1887 [(set (match_operand:DF 0 "general_operand" "=y,x")
1888 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1893 [(set (match_operand:DF 0 "general_operand" "=f")
1894 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1898 (define_insn "floathisf2"
1899 [(set (match_operand:SF 0 "general_operand" "=f")
1900 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1904 (define_insn "floathidf2"
1905 [(set (match_operand:DF 0 "general_operand" "=f")
1906 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1910 (define_insn "floatqisf2"
1911 [(set (match_operand:SF 0 "general_operand" "=f")
1912 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1916 (define_insn "floatqidf2"
1917 [(set (match_operand:DF 0 "general_operand" "=f")
1918 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1922 ;; New routines to convert floating-point values to integers
1923 ;; to be used on the '040. These should be faster than trapping
1924 ;; into the kernel to emulate fintrz. They should also be faster
1925 ;; than calling the subroutines fixsfsi or fixdfsi.
1927 (define_insn "fix_truncdfsi2"
1928 [(set (match_operand:SI 0 "general_operand" "=dm")
1929 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1930 (clobber (match_scratch:SI 2 "=d"))
1931 (clobber (match_scratch:SI 3 "=d"))]
1932 "TARGET_68881 && TARGET_68040"
1936 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1939 (define_insn "fix_truncdfhi2"
1940 [(set (match_operand:HI 0 "general_operand" "=dm")
1941 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1942 (clobber (match_scratch:SI 2 "=d"))
1943 (clobber (match_scratch:SI 3 "=d"))]
1944 "TARGET_68881 && TARGET_68040"
1948 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1951 (define_insn "fix_truncdfqi2"
1952 [(set (match_operand:QI 0 "general_operand" "=dm")
1953 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1954 (clobber (match_scratch:SI 2 "=d"))
1955 (clobber (match_scratch:SI 3 "=d"))]
1956 "TARGET_68881 && TARGET_68040"
1960 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1963 ;; Convert a float to a float whose value is an integer.
1964 ;; This is the first stage of converting it to an integer type.
1966 (define_insn "ftruncdf2"
1967 [(set (match_operand:DF 0 "general_operand" "=f")
1968 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1969 "TARGET_68881 && !TARGET_68040"
1972 if (FP_REG_P (operands[1]))
1973 return \"fintrz%.x %f1,%0\";
1974 return \"fintrz%.d %f1,%0\";
1977 (define_insn "ftruncsf2"
1978 [(set (match_operand:SF 0 "general_operand" "=f")
1979 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1980 "TARGET_68881 && !TARGET_68040"
1983 if (FP_REG_P (operands[1]))
1984 return \"fintrz%.x %f1,%0\";
1985 return \"fintrz%.s %f1,%0\";
1988 ;; Convert a float whose value is an integer
1989 ;; to an actual integer. Second stage of converting float to integer type.
1990 (define_insn "fixsfqi2"
1991 [(set (match_operand:QI 0 "general_operand" "=dm")
1992 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1996 (define_insn "fixsfhi2"
1997 [(set (match_operand:HI 0 "general_operand" "=dm")
1998 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2002 (define_insn "fixsfsi2"
2003 [(set (match_operand:SI 0 "general_operand" "=dm")
2004 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2008 (define_insn "fixdfqi2"
2009 [(set (match_operand:QI 0 "general_operand" "=dm")
2010 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2014 (define_insn "fixdfhi2"
2015 [(set (match_operand:HI 0 "general_operand" "=dm")
2016 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2020 (define_insn "fixdfsi2"
2021 [(set (match_operand:SI 0 "general_operand" "=dm")
2022 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2026 ;; Convert a float to an integer.
2027 ;; On the Sun FPA, this is done in one step.
2030 [(set (match_operand:SI 0 "general_operand" "=x,y")
2031 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2036 [(set (match_operand:SI 0 "general_operand" "=x,y")
2037 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2043 (define_insn "adddi_lshrdi_63"
2044 [(set (match_operand:DI 0 "general_operand" "=d")
2045 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2048 (clobber (match_scratch:SI 2 "=d"))]
2052 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2053 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2055 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2056 if (GET_CODE (operands[1]) == REG)
2057 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2058 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2059 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2060 operands[4] = operands[1];
2062 operands[4] = adj_offsettable_operand (operands[1], 4);
2063 if (GET_CODE (operands[1]) == MEM
2064 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2065 output_asm_insn (\"move%.l %4,%3\", operands);
2066 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2067 if (TARGET_68020 || TARGET_5200)
2068 output_asm_insn (\"extb%.l %2\", operands);
2070 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2071 if (GET_CODE (operands[1]) != MEM
2072 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2073 output_asm_insn (\"move%.l %4,%3\", operands);
2074 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2077 (define_insn "adddi_sexthishl32"
2078 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2079 (plus:DI (ashift:DI (sign_extend:DI
2080 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2082 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2083 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2088 if (ADDRESS_REG_P (operands[0]))
2089 return \"add%.w %1,%0\";
2090 else if (ADDRESS_REG_P (operands[3]))
2091 return \"move%.w %1,%3\;add%.l %3,%0\";
2093 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2096 (define_insn "adddi_dilshr32"
2097 [(set (match_operand:DI 0 "general_operand" "=do")
2098 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2099 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2100 ;; (const_int 32))))]
2101 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2103 (match_operand:DI 2 "general_operand" "0")))]
2108 if (GET_CODE (operands[0]) == REG)
2109 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2111 operands[2] = adj_offsettable_operand (operands[0], 4);
2112 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2115 (define_insn "adddi_dishl32"
2116 [(set (match_operand:DI 0 "general_operand" "=ro")
2117 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2118 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2119 ;; (const_int 32))))]
2120 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2122 (match_operand:DI 2 "general_operand" "0")))]
2127 if (GET_CODE (operands[1]) == REG)
2128 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2130 operands[1] = adj_offsettable_operand (operands[1], 4);
2131 return \"add%.l %1,%0\";
2134 (define_insn "adddi3"
2135 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2136 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2137 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2138 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2142 if (DATA_REG_P (operands[0]))
2144 if (DATA_REG_P (operands[2]))
2145 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2146 else if (GET_CODE (operands[2]) == MEM
2147 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2149 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2153 if (GET_CODE (operands[2]) == REG)
2154 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2155 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2157 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2158 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2160 else if (GET_CODE (operands[2]) == CONST_INT)
2162 operands[1] = operands[2];
2163 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2166 operands[1] = adj_offsettable_operand (operands[2], 4);
2167 /* TODO : for consts, optimize move and add */
2168 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2171 else if (GET_CODE (operands[0]) == MEM)
2173 if (GET_CODE (operands[2]) == MEM
2174 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2175 return \"add%.l %2,%0\;addx%.l %2,%0\";
2177 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2180 = gen_rtx_MEM (SImode,
2181 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2183 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2185 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2187 operands[1] = XEXP(operands[0], 0);
2188 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2192 operands[1] = adj_offsettable_operand (operands[0], 4);
2193 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2198 (define_insn "addsi_lshrsi_31"
2199 [(set (match_operand:SI 0 "general_operand" "=dm")
2200 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2206 operands[2] = operands[0];
2207 operands[3] = gen_label_rtx();
2208 if (GET_CODE (operands[0]) == MEM)
2210 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2211 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2212 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2213 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2215 output_asm_insn (\"move%.l %1,%0\", operands);
2217 output_asm_insn (\"jbpl %l3\", operands);
2219 output_asm_insn (\"jpl %l3\", operands);
2222 output_asm_insn (\"addq%.l %#1,%2\", operands);
2224 output_asm_insn (\"add%.l %#1,%2\", operands);
2226 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2227 CODE_LABEL_NUMBER (operands[3]));
2231 (define_expand "addsi3"
2232 [(set (match_operand:SI 0 "general_operand" "")
2233 (plus:SI (match_operand:SI 1 "general_operand" "")
2234 (match_operand:SI 2 "general_operand" "")))]
2238 ;; Note that the middle two alternatives are near-duplicates
2239 ;; in order to handle insns generated by reload.
2240 ;; This is needed since they are not themselves reloaded,
2241 ;; so commutativity won't apply to them.
2242 (define_insn "*addsi3_internal"
2243 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2244 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2245 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2247 "* return output_addsi3 (operands);")
2249 (define_insn "*addsi3_5200"
2250 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2251 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2252 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2254 "* return output_addsi3 (operands);")
2257 [(set (match_operand:SI 0 "general_operand" "=a")
2258 (plus:SI (match_operand:SI 1 "general_operand" "0")
2260 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2264 (define_insn "addhi3"
2265 [(set (match_operand:HI 0 "general_operand" "=m,r")
2266 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2267 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2271 if (GET_CODE (operands[2]) == CONST_INT)
2274 /* If the constant would be a negative number when interpreted as
2275 HImode, make it negative. This is usually, but not always, done
2276 elsewhere in the compiler. First check for constants out of range,
2277 which could confuse us. */
2279 if (INTVAL (operands[2]) >= 32768)
2280 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2282 if (INTVAL (operands[2]) > 0
2283 && INTVAL (operands[2]) <= 8)
2284 return \"addq%.w %2,%0\";
2285 if (INTVAL (operands[2]) < 0
2286 && INTVAL (operands[2]) >= -8)
2288 operands[2] = GEN_INT (-INTVAL (operands[2]));
2289 return \"subq%.w %2,%0\";
2291 /* On the CPU32 it is faster to use two addqw instructions to
2292 add a small integer (8 < N <= 16) to a register.
2293 Likewise for subqw. */
2294 if (TARGET_CPU32 && REG_P (operands[0]))
2296 if (INTVAL (operands[2]) > 8
2297 && INTVAL (operands[2]) <= 16)
2299 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2300 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2302 if (INTVAL (operands[2]) < -8
2303 && INTVAL (operands[2]) >= -16)
2305 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2306 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2310 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2312 return \"lea (%c2,%0),%0\";
2314 return \"lea %0@(%c2),%0\";
2317 return \"add%.w %2,%0\";
2320 ;; These insns must use MATCH_DUP instead of the more expected
2321 ;; use of a matching constraint because the "output" here is also
2322 ;; an input, so you can't use the matching constraint. That also means
2323 ;; that you can't use the "%", so you need patterns with the matched
2324 ;; operand in both positions.
2327 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2328 (plus:HI (match_dup 0)
2329 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2333 if (GET_CODE (operands[1]) == CONST_INT)
2336 /* If the constant would be a negative number when interpreted as
2337 HImode, make it negative. This is usually, but not always, done
2338 elsewhere in the compiler. First check for constants out of range,
2339 which could confuse us. */
2341 if (INTVAL (operands[1]) >= 32768)
2342 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2344 if (INTVAL (operands[1]) > 0
2345 && INTVAL (operands[1]) <= 8)
2346 return \"addq%.w %1,%0\";
2347 if (INTVAL (operands[1]) < 0
2348 && INTVAL (operands[1]) >= -8)
2350 operands[1] = GEN_INT (-INTVAL (operands[1]));
2351 return \"subq%.w %1,%0\";
2353 /* On the CPU32 it is faster to use two addqw instructions to
2354 add a small integer (8 < N <= 16) to a register.
2355 Likewise for subqw. */
2356 if (TARGET_CPU32 && REG_P (operands[0]))
2358 if (INTVAL (operands[1]) > 8
2359 && INTVAL (operands[1]) <= 16)
2361 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2362 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2364 if (INTVAL (operands[1]) < -8
2365 && INTVAL (operands[1]) >= -16)
2367 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2368 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2372 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2374 return \"lea (%c1,%0),%0\";
2376 return \"lea %0@(%c1),%0\";
2379 return \"add%.w %1,%0\";
2383 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2384 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2389 if (GET_CODE (operands[1]) == CONST_INT)
2392 /* If the constant would be a negative number when interpreted as
2393 HImode, make it negative. This is usually, but not always, done
2394 elsewhere in the compiler. First check for constants out of range,
2395 which could confuse us. */
2397 if (INTVAL (operands[1]) >= 32768)
2398 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2400 if (INTVAL (operands[1]) > 0
2401 && INTVAL (operands[1]) <= 8)
2402 return \"addq%.w %1,%0\";
2403 if (INTVAL (operands[1]) < 0
2404 && INTVAL (operands[1]) >= -8)
2406 operands[1] = GEN_INT (-INTVAL (operands[1]));
2407 return \"subq%.w %1,%0\";
2409 /* On the CPU32 it is faster to use two addqw instructions to
2410 add a small integer (8 < N <= 16) to a register.
2411 Likewise for subqw. */
2412 if (TARGET_CPU32 && REG_P (operands[0]))
2414 if (INTVAL (operands[1]) > 8
2415 && INTVAL (operands[1]) <= 16)
2417 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2418 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2420 if (INTVAL (operands[1]) < -8
2421 && INTVAL (operands[1]) >= -16)
2423 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2424 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2428 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2430 return \"lea (%c1,%0),%0\";
2432 return \"lea %0@(%c1),%0\";
2435 return \"add%.w %1,%0\";
2438 (define_insn "addqi3"
2439 [(set (match_operand:QI 0 "general_operand" "=m,d")
2440 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2441 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2446 if (GET_CODE (operands[2]) == CONST_INT)
2448 if (INTVAL (operands[2]) >= 128)
2449 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2451 if (INTVAL (operands[2]) > 0
2452 && INTVAL (operands[2]) <= 8)
2453 return \"addq%.b %2,%0\";
2454 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2456 operands[2] = GEN_INT (-INTVAL (operands[2]));
2457 return \"subq%.b %2,%0\";
2461 return \"add%.b %2,%0\";
2465 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2466 (plus:QI (match_dup 0)
2467 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2472 if (GET_CODE (operands[1]) == CONST_INT)
2474 if (INTVAL (operands[1]) >= 128)
2475 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2477 if (INTVAL (operands[1]) > 0
2478 && INTVAL (operands[1]) <= 8)
2479 return \"addq%.b %1,%0\";
2480 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2482 operands[1] = GEN_INT (-INTVAL (operands[1]));
2483 return \"subq%.b %1,%0\";
2487 return \"add%.b %1,%0\";
2491 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2492 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2498 if (GET_CODE (operands[1]) == CONST_INT)
2500 if (INTVAL (operands[1]) >= 128)
2501 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2503 if (INTVAL (operands[1]) > 0
2504 && INTVAL (operands[1]) <= 8)
2505 return \"addq%.b %1,%0\";
2506 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2508 operands[1] = GEN_INT (-INTVAL (operands[1]));
2509 return \"subq%.b %1,%0\";
2513 return \"add%.b %1,%0\";
2516 (define_expand "adddf3"
2517 [(set (match_operand:DF 0 "general_operand" "")
2518 (plus:DF (match_operand:DF 1 "general_operand" "")
2519 (match_operand:DF 2 "general_operand" "")))]
2520 "TARGET_68881 || TARGET_FPA"
2524 [(set (match_operand:DF 0 "general_operand" "=x,y")
2525 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2526 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2530 if (rtx_equal_p (operands[0], operands[1]))
2531 return \"fpadd%.d %y2,%0\";
2532 if (rtx_equal_p (operands[0], operands[2]))
2533 return \"fpadd%.d %y1,%0\";
2534 if (which_alternative == 0)
2535 return \"fpadd3%.d %w2,%w1,%0\";
2536 return \"fpadd3%.d %x2,%x1,%0\";
2540 [(set (match_operand:DF 0 "general_operand" "=f")
2541 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2542 (match_operand:DF 1 "general_operand" "0")))]
2547 [(set (match_operand:DF 0 "general_operand" "=f")
2548 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2549 (match_operand:DF 1 "general_operand" "0")))]
2554 [(set (match_operand:DF 0 "general_operand" "=f")
2555 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2556 (match_operand:DF 1 "general_operand" "0")))]
2561 [(set (match_operand:DF 0 "general_operand" "=f")
2562 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2563 (match_operand:DF 2 "general_operand" "fmG")))]
2567 if (REG_P (operands[2]))
2568 return \"f%&add%.x %2,%0\";
2569 return \"f%&add%.d %f2,%0\";
2572 (define_expand "addsf3"
2573 [(set (match_operand:SF 0 "general_operand" "")
2574 (plus:SF (match_operand:SF 1 "general_operand" "")
2575 (match_operand:SF 2 "general_operand" "")))]
2576 "TARGET_68881 || TARGET_FPA"
2580 [(set (match_operand:SF 0 "general_operand" "=x,y")
2581 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2582 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2586 if (rtx_equal_p (operands[0], operands[1]))
2587 return \"fpadd%.s %w2,%0\";
2588 if (rtx_equal_p (operands[0], operands[2]))
2589 return \"fpadd%.s %w1,%0\";
2590 if (which_alternative == 0)
2591 return \"fpadd3%.s %w2,%w1,%0\";
2592 return \"fpadd3%.s %2,%1,%0\";
2596 [(set (match_operand:SF 0 "general_operand" "=f")
2597 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2598 (match_operand:SF 1 "general_operand" "0")))]
2603 [(set (match_operand:SF 0 "general_operand" "=f")
2604 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2605 (match_operand:SF 1 "general_operand" "0")))]
2610 [(set (match_operand:SF 0 "general_operand" "=f")
2611 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2612 (match_operand:SF 1 "general_operand" "0")))]
2617 [(set (match_operand:SF 0 "general_operand" "=f")
2618 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2619 (match_operand:SF 2 "general_operand" "fdmF")))]
2623 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2624 return \"f%$add%.x %2,%0\";
2625 return \"f%$add%.s %f2,%0\";
2628 ;; subtract instructions
2630 (define_insn "subdi_sexthishl32"
2631 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2632 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2633 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2635 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2640 if (ADDRESS_REG_P (operands[0]))
2641 return \"sub%.w %2,%0\";
2642 else if (ADDRESS_REG_P (operands[3]))
2643 return \"move%.w %2,%3\;sub%.l %3,%0\";
2645 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2648 (define_insn "subdi_dishl32"
2649 [(set (match_operand:DI 0 "general_operand" "+ro")
2650 (minus:DI (match_dup 0)
2651 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2657 if (GET_CODE (operands[1]) == REG)
2658 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2660 operands[1] = adj_offsettable_operand (operands[1], 4);
2661 return \"sub%.l %1,%0\";
2664 (define_insn "subdi3"
2665 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2666 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2667 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2668 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2672 if (DATA_REG_P (operands[0]))
2674 if (DATA_REG_P (operands[2]))
2675 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2676 else if (GET_CODE (operands[2]) == MEM
2677 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2679 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2683 if (GET_CODE (operands[2]) == REG)
2684 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2685 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2687 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2688 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2690 else if (GET_CODE (operands[2]) == CONST_INT)
2692 operands[1] = operands[2];
2693 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2696 operands[1] = adj_offsettable_operand (operands[2], 4);
2697 /* TODO : for consts, optimize move and sub */
2698 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2701 else if (GET_CODE (operands[0]) == MEM)
2703 if (GET_CODE (operands[2]) == MEM
2704 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2705 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2707 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2710 = gen_rtx_MEM (SImode,
2711 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2713 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2715 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2717 operands[1] = XEXP(operands[0], 0);
2718 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2722 operands[1] = adj_offsettable_operand (operands[0], 4);
2723 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2728 (define_insn "subsi3"
2729 [(set (match_operand:SI 0 "general_operand" "=m,r")
2730 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2731 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2736 [(set (match_operand:SI 0 "general_operand" "=a")
2737 (minus:SI (match_operand:SI 1 "general_operand" "0")
2739 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2743 (define_insn "subhi3"
2744 [(set (match_operand:HI 0 "general_operand" "=m,r")
2745 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2746 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2751 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2752 (minus:HI (match_dup 0)
2753 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2757 (define_insn "subqi3"
2758 [(set (match_operand:QI 0 "general_operand" "=m,d")
2759 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2760 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2765 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2766 (minus:QI (match_dup 0)
2767 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2771 (define_expand "subdf3"
2772 [(set (match_operand:DF 0 "general_operand" "")
2773 (minus:DF (match_operand:DF 1 "general_operand" "")
2774 (match_operand:DF 2 "general_operand" "")))]
2775 "TARGET_68881 || TARGET_FPA"
2779 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2780 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2781 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2785 if (rtx_equal_p (operands[0], operands[2]))
2786 return \"fprsub%.d %y1,%0\";
2787 if (rtx_equal_p (operands[0], operands[1]))
2788 return \"fpsub%.d %y2,%0\";
2789 if (which_alternative == 0)
2790 return \"fpsub3%.d %w2,%w1,%0\";
2791 return \"fpsub3%.d %x2,%x1,%0\";
2795 [(set (match_operand:DF 0 "general_operand" "=f")
2796 (minus:DF (match_operand:DF 1 "general_operand" "0")
2797 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2802 [(set (match_operand:DF 0 "general_operand" "=f")
2803 (minus:DF (match_operand:DF 1 "general_operand" "0")
2804 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2809 [(set (match_operand:DF 0 "general_operand" "=f")
2810 (minus:DF (match_operand:DF 1 "general_operand" "0")
2811 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2816 [(set (match_operand:DF 0 "general_operand" "=f")
2817 (minus:DF (match_operand:DF 1 "general_operand" "0")
2818 (match_operand:DF 2 "general_operand" "fmG")))]
2822 if (REG_P (operands[2]))
2823 return \"f%&sub%.x %2,%0\";
2824 return \"f%&sub%.d %f2,%0\";
2827 (define_expand "subsf3"
2828 [(set (match_operand:SF 0 "general_operand" "")
2829 (minus:SF (match_operand:SF 1 "general_operand" "")
2830 (match_operand:SF 2 "general_operand" "")))]
2831 "TARGET_68881 || TARGET_FPA"
2835 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2836 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2837 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2841 if (rtx_equal_p (operands[0], operands[2]))
2842 return \"fprsub%.s %w1,%0\";
2843 if (rtx_equal_p (operands[0], operands[1]))
2844 return \"fpsub%.s %w2,%0\";
2845 if (which_alternative == 0)
2846 return \"fpsub3%.s %w2,%w1,%0\";
2847 return \"fpsub3%.s %2,%1,%0\";
2851 [(set (match_operand:SF 0 "general_operand" "=f")
2852 (minus:SF (match_operand:SF 1 "general_operand" "0")
2853 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2858 [(set (match_operand:SF 0 "general_operand" "=f")
2859 (minus:SF (match_operand:SF 1 "general_operand" "0")
2860 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2865 [(set (match_operand:SF 0 "general_operand" "=f")
2866 (minus:SF (match_operand:SF 1 "general_operand" "0")
2867 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2872 [(set (match_operand:SF 0 "general_operand" "=f")
2873 (minus:SF (match_operand:SF 1 "general_operand" "0")
2874 (match_operand:SF 2 "general_operand" "fdmF")))]
2878 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2879 return \"f%$sub%.x %2,%0\";
2880 return \"f%$sub%.s %f2,%0\";
2883 ;; multiply instructions
2885 (define_insn "mulhi3"
2886 [(set (match_operand:HI 0 "general_operand" "=d")
2887 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2888 (match_operand:HI 2 "general_operand" "dmn")))]
2892 #if defined(MOTOROLA) && !defined(CRDS)
2893 return \"muls%.w %2,%0\";
2895 return \"muls %2,%0\";
2899 (define_insn "mulhisi3"
2900 [(set (match_operand:SI 0 "general_operand" "=d")
2901 (mult:SI (sign_extend:SI
2902 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2904 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2908 #if defined(MOTOROLA) && !defined(CRDS)
2909 return \"muls%.w %2,%0\";
2911 return \"muls %2,%0\";
2916 [(set (match_operand:SI 0 "general_operand" "=d")
2917 (mult:SI (sign_extend:SI
2918 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2919 (match_operand:SI 2 "const_int_operand" "n")))]
2920 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2923 #if defined(MOTOROLA) && !defined(CRDS)
2924 return \"muls%.w %2,%0\";
2926 return \"muls %2,%0\";
2930 (define_expand "mulsi3"
2931 [(set (match_operand:SI 0 "general_operand" "")
2932 (mult:SI (match_operand:SI 1 "general_operand" "")
2933 (match_operand:SI 2 "general_operand" "")))]
2934 "TARGET_68020 || TARGET_5200"
2938 [(set (match_operand:SI 0 "general_operand" "=d")
2939 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2940 (match_operand:SI 2 "general_operand" "dmsK")))]
2945 [(set (match_operand:SI 0 "general_operand" "=d")
2946 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2947 (match_operand:SI 2 "general_operand" "d<Q>")))]
2951 (define_insn "umulhisi3"
2952 [(set (match_operand:SI 0 "general_operand" "=d")
2953 (mult:SI (zero_extend:SI
2954 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2956 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2960 #if defined(MOTOROLA) && !defined(CRDS)
2961 return \"mulu%.w %2,%0\";
2963 return \"mulu %2,%0\";
2968 [(set (match_operand:SI 0 "general_operand" "=d")
2969 (mult:SI (zero_extend:SI
2970 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2971 (match_operand:SI 2 "const_int_operand" "n")))]
2972 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2975 #if defined(MOTOROLA) && !defined(CRDS)
2976 return \"mulu%.w %2,%0\";
2978 return \"mulu %2,%0\";
2982 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2983 ;; proper matching constraint. This is because the matching is between
2984 ;; the high-numbered word of the DImode operand[0] and operand[1].
2985 (define_expand "umulsidi3"
2987 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2988 (mult:SI (match_operand:SI 1 "register_operand" "")
2989 (match_operand:SI 2 "nonimmediate_operand" "")))
2990 (set (subreg:SI (match_dup 0) 0)
2991 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2992 (zero_extend:DI (match_dup 2)))
2993 (const_int 32))))])]
2994 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2998 [(set (match_operand:SI 0 "register_operand" "=d")
2999 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3000 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3001 (set (match_operand:SI 3 "register_operand" "=d")
3002 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3003 (zero_extend:DI (match_dup 2)))
3005 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3008 ; Match immediate case. For 2.4 only match things < 2^31.
3009 ; It's tricky with larger values in these patterns since we need to match
3010 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3013 [(set (match_operand:SI 0 "register_operand" "=d")
3014 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3015 (match_operand:SI 2 "const_int_operand" "n")))
3016 (set (match_operand:SI 3 "register_operand" "=d")
3017 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3020 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3021 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3024 (define_expand "mulsidi3"
3026 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3027 (mult:SI (match_operand:SI 1 "register_operand" "")
3028 (match_operand:SI 2 "nonimmediate_operand" "")))
3029 (set (subreg:SI (match_dup 0) 0)
3030 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3031 (sign_extend:DI (match_dup 2)))
3032 (const_int 32))))])]
3033 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3037 [(set (match_operand:SI 0 "register_operand" "=d")
3038 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3039 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3040 (set (match_operand:SI 3 "register_operand" "=d")
3041 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3042 (sign_extend:DI (match_dup 2)))
3044 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3048 [(set (match_operand:SI 0 "register_operand" "=d")
3049 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3050 (match_operand:SI 2 "const_sint32_operand" "")))
3051 (set (match_operand:SI 3 "register_operand" "=d")
3052 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3055 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3058 (define_expand "umulsi3_highpart"
3060 [(set (match_operand:SI 0 "register_operand" "")
3063 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3064 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3066 (clobber (match_dup 3))])]
3067 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3070 operands[3] = gen_reg_rtx (SImode);
3071 if (GET_CODE (operands[2]) == CONST_INT
3072 || GET_CODE (operands[2]) == CONST_DOUBLE)
3074 if (! const_uint32_operand (operands[2], VOIDmode))
3076 /* We have to adjust the operand order for the matching constraints. */
3077 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3078 operands[1], operands[2]));
3084 [(set (match_operand:SI 0 "register_operand" "=d")
3087 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3088 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3090 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3091 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3094 (define_insn "const_umulsi3_highpart"
3095 [(set (match_operand:SI 0 "register_operand" "=d")
3098 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3099 (match_operand 3 "const_uint32_operand" ""))
3101 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3102 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3105 (define_expand "smulsi3_highpart"
3107 [(set (match_operand:SI 0 "register_operand" "")
3110 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3111 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3113 (clobber (match_dup 3))])]
3114 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3117 operands[3] = gen_reg_rtx (SImode);
3118 if (GET_CODE (operands[2]) == CONST_INT
3119 || GET_CODE (operands[2]) == CONST_DOUBLE)
3121 if (! const_sint32_operand (operands[2], VOIDmode))
3123 /* We have to adjust the operand order for the matching constraints. */
3124 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3125 operands[1], operands[2]));
3131 [(set (match_operand:SI 0 "register_operand" "=d")
3134 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3135 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3137 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3138 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3141 (define_insn "const_smulsi3_highpart"
3142 [(set (match_operand:SI 0 "register_operand" "=d")
3145 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3146 (match_operand 3 "const_sint32_operand" ""))
3148 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3149 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3152 (define_expand "muldf3"
3153 [(set (match_operand:DF 0 "general_operand" "")
3154 (mult:DF (match_operand:DF 1 "general_operand" "")
3155 (match_operand:DF 2 "general_operand" "")))]
3156 "TARGET_68881 || TARGET_FPA"
3160 [(set (match_operand:DF 0 "general_operand" "=x,y")
3161 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3162 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3166 if (rtx_equal_p (operands[1], operands[2]))
3167 return \"fpsqr%.d %y1,%0\";
3168 if (rtx_equal_p (operands[0], operands[1]))
3169 return \"fpmul%.d %y2,%0\";
3170 if (rtx_equal_p (operands[0], operands[2]))
3171 return \"fpmul%.d %y1,%0\";
3172 if (which_alternative == 0)
3173 return \"fpmul3%.d %w2,%w1,%0\";
3174 return \"fpmul3%.d %x2,%x1,%0\";
3178 [(set (match_operand:DF 0 "general_operand" "=f")
3179 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3180 (match_operand:DF 1 "general_operand" "0")))]
3185 [(set (match_operand:DF 0 "general_operand" "=f")
3186 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3187 (match_operand:DF 1 "general_operand" "0")))]
3192 [(set (match_operand:DF 0 "general_operand" "=f")
3193 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3194 (match_operand:DF 1 "general_operand" "0")))]
3199 [(set (match_operand:DF 0 "general_operand" "=f")
3200 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3201 (match_operand:DF 2 "general_operand" "fmG")))]
3205 if (GET_CODE (operands[2]) == CONST_DOUBLE
3206 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3208 int i = floating_exact_log2 (operands[2]);
3209 operands[2] = GEN_INT (i);
3210 return \"fscale%.l %2,%0\";
3212 if (REG_P (operands[2]))
3213 return \"f%&mul%.x %2,%0\";
3214 return \"f%&mul%.d %f2,%0\";
3217 (define_expand "mulsf3"
3218 [(set (match_operand:SF 0 "general_operand" "")
3219 (mult:SF (match_operand:SF 1 "general_operand" "")
3220 (match_operand:SF 2 "general_operand" "")))]
3221 "TARGET_68881 || TARGET_FPA"
3225 [(set (match_operand:SF 0 "general_operand" "=x,y")
3226 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3227 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3231 if (rtx_equal_p (operands[1], operands[2]))
3232 return \"fpsqr%.s %w1,%0\";
3233 if (rtx_equal_p (operands[0], operands[1]))
3234 return \"fpmul%.s %w2,%0\";
3235 if (rtx_equal_p (operands[0], operands[2]))
3236 return \"fpmul%.s %w1,%0\";
3237 if (which_alternative == 0)
3238 return \"fpmul3%.s %w2,%w1,%0\";
3239 return \"fpmul3%.s %2,%1,%0\";
3243 [(set (match_operand:SF 0 "general_operand" "=f")
3244 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3245 (match_operand:SF 1 "general_operand" "0")))]
3249 return (TARGET_68040_ONLY
3250 ? \"fsmul%.l %2,%0\"
3251 : \"fsglmul%.l %2,%0\");
3255 [(set (match_operand:SF 0 "general_operand" "=f")
3256 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3257 (match_operand:SF 1 "general_operand" "0")))]
3261 return (TARGET_68040_ONLY
3262 ? \"fsmul%.w %2,%0\"
3263 : \"fsglmul%.w %2,%0\");
3267 [(set (match_operand:SF 0 "general_operand" "=f")
3268 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3269 (match_operand:SF 1 "general_operand" "0")))]
3273 return (TARGET_68040_ONLY
3274 ? \"fsmul%.b %2,%0\"
3275 : \"fsglmul%.b %2,%0\");
3279 [(set (match_operand:SF 0 "general_operand" "=f")
3280 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3281 (match_operand:SF 2 "general_operand" "fdmF")))]
3285 #ifdef FSGLMUL_USE_S
3286 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3287 return (TARGET_68040_ONLY
3288 ? \"fsmul%.s %2,%0\"
3289 : \"fsglmul%.s %2,%0\");
3291 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3292 return (TARGET_68040_ONLY
3293 ? \"fsmul%.x %2,%0\"
3294 : \"fsglmul%.x %2,%0\");
3296 return (TARGET_68040_ONLY
3297 ? \"fsmul%.s %f2,%0\"
3298 : \"fsglmul%.s %f2,%0\");
3301 ;; divide instructions
3303 (define_expand "divdf3"
3304 [(set (match_operand:DF 0 "general_operand" "")
3305 (div:DF (match_operand:DF 1 "general_operand" "")
3306 (match_operand:DF 2 "general_operand" "")))]
3307 "TARGET_68881 || TARGET_FPA"
3311 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3312 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3313 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3317 if (rtx_equal_p (operands[0], operands[2]))
3318 return \"fprdiv%.d %y1,%0\";
3319 if (rtx_equal_p (operands[0], operands[1]))
3320 return \"fpdiv%.d %y2,%0\";
3321 if (which_alternative == 0)
3322 return \"fpdiv3%.d %w2,%w1,%0\";
3323 return \"fpdiv3%.d %x2,%x1,%x0\";
3327 [(set (match_operand:DF 0 "general_operand" "=f")
3328 (div:DF (match_operand:DF 1 "general_operand" "0")
3329 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3334 [(set (match_operand:DF 0 "general_operand" "=f")
3335 (div:DF (match_operand:DF 1 "general_operand" "0")
3336 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3341 [(set (match_operand:DF 0 "general_operand" "=f")
3342 (div:DF (match_operand:DF 1 "general_operand" "0")
3343 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3348 [(set (match_operand:DF 0 "general_operand" "=f")
3349 (div:DF (match_operand:DF 1 "general_operand" "0")
3350 (match_operand:DF 2 "general_operand" "fmG")))]
3354 if (REG_P (operands[2]))
3355 return \"f%&div%.x %2,%0\";
3356 return \"f%&div%.d %f2,%0\";
3359 (define_expand "divsf3"
3360 [(set (match_operand:SF 0 "general_operand" "")
3361 (div:SF (match_operand:SF 1 "general_operand" "")
3362 (match_operand:SF 2 "general_operand" "")))]
3363 "TARGET_68881 || TARGET_FPA"
3367 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3368 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3369 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3373 if (rtx_equal_p (operands[0], operands[1]))
3374 return \"fpdiv%.s %w2,%0\";
3375 if (rtx_equal_p (operands[0], operands[2]))
3376 return \"fprdiv%.s %w1,%0\";
3377 if (which_alternative == 0)
3378 return \"fpdiv3%.s %w2,%w1,%0\";
3379 return \"fpdiv3%.s %2,%1,%0\";
3383 [(set (match_operand:SF 0 "general_operand" "=f")
3384 (div:SF (match_operand:SF 1 "general_operand" "0")
3385 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3389 return (TARGET_68040_ONLY
3390 ? \"fsdiv%.l %2,%0\"
3391 : \"fsgldiv%.l %2,%0\");
3395 [(set (match_operand:SF 0 "general_operand" "=f")
3396 (div:SF (match_operand:SF 1 "general_operand" "0")
3397 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3401 return (TARGET_68040_ONLY
3402 ? \"fsdiv%.w %2,%0\"
3403 : \"fsgldiv%.w %2,%0\");
3407 [(set (match_operand:SF 0 "general_operand" "=f")
3408 (div:SF (match_operand:SF 1 "general_operand" "0")
3409 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3413 return (TARGET_68040_ONLY
3414 ? \"fsdiv%.b %2,%0\"
3415 : \"fsgldiv%.b %2,%0\");
3419 [(set (match_operand:SF 0 "general_operand" "=f")
3420 (div:SF (match_operand:SF 1 "general_operand" "0")
3421 (match_operand:SF 2 "general_operand" "fdmF")))]
3425 #ifdef FSGLDIV_USE_S
3426 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3427 return (TARGET_68040_ONLY
3428 ? \"fsdiv%.s %2,%0\"
3429 : \"fsgldiv%.s %2,%0\");
3431 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3432 return (TARGET_68040_ONLY
3433 ? \"fsdiv%.x %2,%0\"
3434 : \"fsgldiv%.x %2,%0\");
3436 return (TARGET_68040_ONLY
3437 ? \"fsdiv%.s %f2,%0\"
3438 : \"fsgldiv%.s %f2,%0\");
3441 ;; Remainder instructions.
3443 (define_insn "divmodsi4"
3444 [(set (match_operand:SI 0 "general_operand" "=d")
3445 (div:SI (match_operand:SI 1 "general_operand" "0")
3446 (match_operand:SI 2 "general_operand" "dmsK")))
3447 (set (match_operand:SI 3 "general_operand" "=d")
3448 (mod:SI (match_dup 1) (match_dup 2)))]
3449 "TARGET_68020 && !TARGET_5200"
3452 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3453 return \"divs%.l %2,%0\";
3455 return \"divsl%.l %2,%3:%0\";
3458 (define_insn "udivmodsi4"
3459 [(set (match_operand:SI 0 "general_operand" "=d")
3460 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3461 (match_operand:SI 2 "general_operand" "dmsK")))
3462 (set (match_operand:SI 3 "general_operand" "=d")
3463 (umod:SI (match_dup 1) (match_dup 2)))]
3464 "TARGET_68020 && !TARGET_5200"
3467 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3468 return \"divu%.l %2,%0\";
3470 return \"divul%.l %2,%3:%0\";
3473 (define_insn "divmodhi4"
3474 [(set (match_operand:HI 0 "general_operand" "=d")
3475 (div:HI (match_operand:HI 1 "general_operand" "0")
3476 (match_operand:HI 2 "general_operand" "dmsK")))
3477 (set (match_operand:HI 3 "general_operand" "=d")
3478 (mod:HI (match_dup 1) (match_dup 2)))]
3483 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3485 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3487 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3490 return \"move%.l %0,%3\;swap %3\";
3496 (define_insn "udivmodhi4"
3497 [(set (match_operand:HI 0 "general_operand" "=d")
3498 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3499 (match_operand:HI 2 "general_operand" "dmsK")))
3500 (set (match_operand:HI 3 "general_operand" "=d")
3501 (umod:HI (match_dup 1) (match_dup 2)))]
3506 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3508 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3510 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3513 return \"move%.l %0,%3\;swap %3\";
3519 ;; logical-and instructions
3521 ;; "anddi3" is mainly here to help combine().
3522 (define_insn "anddi3"
3523 [(set (match_operand:DI 0 "general_operand" "=o,d")
3524 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3525 (match_operand:DI 2 "general_operand" "dn,don")))]
3530 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3531 if (GET_CODE (operands[2]) == CONST_DOUBLE
3532 || GET_CODE (operands[2]) == CONST_INT)
3536 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3538 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3539 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3544 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3546 switch (INTVAL (hi))
3549 output_asm_insn (\"clr%.l %0\", operands);
3557 xoperands[0] = operands[0];
3559 output_asm_insn (output_andsi3 (xoperands), xoperands);
3562 if (GET_CODE (operands[0]) == REG)
3563 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3565 operands[0] = adj_offsettable_operand (operands[0], 4);
3566 switch (INTVAL (lo))
3569 output_asm_insn (\"clr%.l %0\", operands);
3577 xoperands[0] = operands[0];
3579 output_asm_insn (output_andsi3 (xoperands), xoperands);
3584 if (GET_CODE (operands[0]) != REG)
3586 operands[1] = adj_offsettable_operand (operands[0], 4);
3587 return \"and%.l %2,%0\;and%.l %R2,%1\";
3589 if (GET_CODE (operands[2]) != REG)
3591 operands[1] = adj_offsettable_operand (operands[2], 4);
3592 return \"and%.l %2,%0\;and%.l %1,%R0\";
3594 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3597 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3598 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3599 ;; can't allocate pseudos into it.
3601 (define_expand "andsi3"
3602 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3603 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3604 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3608 (define_insn "andsi3_internal"
3609 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3610 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3611 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3615 return output_andsi3 (operands);
3618 (define_insn "andsi3_5200"
3619 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3620 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3621 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3625 (define_insn "andhi3"
3626 [(set (match_operand:HI 0 "general_operand" "=m,d")
3627 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3628 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3633 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3634 (and:HI (match_dup 0)
3635 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3640 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3641 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3646 (define_insn "andqi3"
3647 [(set (match_operand:QI 0 "general_operand" "=m,d")
3648 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3649 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3654 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3655 (and:QI (match_dup 0)
3656 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3661 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3662 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3667 ;; inclusive-or instructions
3669 (define_insn "iordi_zext"
3670 [(set (match_operand:DI 0 "general_operand" "=o,d")
3671 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3672 (match_operand:DI 2 "general_operand" "0,0")))]
3679 if (GET_CODE (operands[0]) == REG)
3680 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3682 operands[0] = adj_offsettable_operand (operands[0], 4);
3683 if (GET_MODE (operands[1]) == SImode)
3684 return \"or%.l %1,%0\";
3685 byte_mode = (GET_MODE (operands[1]) == QImode);
3686 if (GET_CODE (operands[0]) == MEM)
3687 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3689 return \"or%.b %1,%0\";
3691 return \"or%.w %1,%0\";
3694 ;; "iordi3" is mainly here to help combine().
3695 (define_insn "iordi3"
3696 [(set (match_operand:DI 0 "general_operand" "=o,d")
3697 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3698 (match_operand:DI 2 "general_operand" "dn,don")))]
3703 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3704 if (GET_CODE (operands[2]) == CONST_DOUBLE
3705 || GET_CODE (operands[2]) == CONST_INT)
3709 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3711 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3712 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3717 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3719 switch (INTVAL (hi))
3724 /* FIXME : a scratch register would be welcome here if operand[0]
3725 is not a register */
3726 output_asm_insn (\"move%.l %#-1,%0\", operands);
3732 xoperands[0] = operands[0];
3734 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3737 if (GET_CODE (operands[0]) == REG)
3738 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3740 operands[0] = adj_offsettable_operand (operands[0], 4);
3741 switch (INTVAL (lo))
3746 /* FIXME : a scratch register would be welcome here if operand[0]
3747 is not a register */
3748 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3754 xoperands[0] = operands[0];
3756 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3761 if (GET_CODE (operands[0]) != REG)
3763 operands[1] = adj_offsettable_operand (operands[0], 4);
3764 return \"or%.l %2,%0\;or%.l %R2,%1\";
3766 if (GET_CODE (operands[2]) != REG)
3768 operands[1] = adj_offsettable_operand (operands[2], 4);
3769 return \"or%.l %2,%0\;or%.l %1,%R0\";
3771 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3774 (define_expand "iorsi3"
3775 [(set (match_operand:SI 0 "general_operand" "")
3776 (ior:SI (match_operand:SI 1 "general_operand" "")
3777 (match_operand:SI 2 "general_operand" "")))]
3781 (define_insn "iorsi3_internal"
3782 [(set (match_operand:SI 0 "general_operand" "=m,d")
3783 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3784 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3788 return output_iorsi3 (operands);
3791 (define_insn "iorsi3_5200"
3792 [(set (match_operand:SI 0 "general_operand" "=m,d")
3793 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3794 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3798 (define_insn "iorhi3"
3799 [(set (match_operand:HI 0 "general_operand" "=m,d")
3800 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3801 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3806 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3807 (ior:HI (match_dup 0)
3808 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3813 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3814 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3819 (define_insn "iorqi3"
3820 [(set (match_operand:QI 0 "general_operand" "=m,d")
3821 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3822 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3827 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3828 (ior:QI (match_dup 0)
3829 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3834 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3835 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3840 ;; On all 68k models, this makes faster code in a special case.
3841 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3843 (define_insn "iorsi_zexthi_ashl16"
3844 [(set (match_operand:SI 0 "general_operand" "=&d")
3845 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3846 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3852 if (GET_CODE (operands[2]) != REG)
3853 operands[2] = adj_offsettable_operand (operands[2], 2);
3854 if (GET_CODE (operands[2]) != REG
3855 || REGNO (operands[2]) != REGNO (operands[0]))
3856 output_asm_insn (\"move%.w %2,%0\", operands);
3857 return \"swap %0\;mov%.w %1,%0\";
3860 (define_insn "iorsi_zext"
3861 [(set (match_operand:SI 0 "general_operand" "=o,d")
3862 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3863 (match_operand:SI 2 "general_operand" "0,0")))]
3870 byte_mode = (GET_MODE (operands[1]) == QImode);
3871 if (GET_CODE (operands[0]) == MEM)
3872 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3874 return \"or%.b %1,%0\";
3876 return \"or%.w %1,%0\";
3881 ;; "xordi3" is mainly here to help combine().
3882 (define_insn "xordi3"
3883 [(set (match_operand:DI 0 "general_operand" "=od")
3884 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3885 (match_operand:DI 2 "general_operand" "dn")))]
3890 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3891 if (GET_CODE (operands[2]) == CONST_DOUBLE
3892 || GET_CODE (operands[2]) == CONST_INT)
3896 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3898 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3899 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3904 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3906 switch (INTVAL (hi))
3911 output_asm_insn (\"not%.l %0\", operands);
3914 /* FIXME : a scratch register would be welcome here if
3915 -128 <= INTVAL (hi) < -1 */
3919 xoperands[0] = operands[0];
3921 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3924 if (GET_CODE (operands[0]) == REG)
3925 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3927 operands[0] = adj_offsettable_operand (operands[0], 4);
3928 switch (INTVAL (lo))
3933 output_asm_insn (\"not%.l %0\", operands);
3936 /* FIXME : a scratch register would be welcome here if
3937 -128 <= INTVAL (lo) < -1 */
3939 /* FIXME : this should be merged with xorsi3 */
3943 xoperands[0] = operands[0];
3945 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3950 if (GET_CODE (operands[0]) != REG)
3952 operands[1] = adj_offsettable_operand (operands[0], 4);
3953 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3955 if (GET_CODE (operands[2]) != REG)
3957 operands[1] = adj_offsettable_operand (operands[2], 4);
3958 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3960 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3963 (define_expand "xorsi3"
3964 [(set (match_operand:SI 0 "general_operand" "")
3965 (xor:SI (match_operand:SI 1 "general_operand" "")
3966 (match_operand:SI 2 "general_operand" "")))]
3970 (define_insn "xorsi3_internal"
3971 [(set (match_operand:SI 0 "general_operand" "=do,m")
3972 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3973 (match_operand:SI 2 "general_operand" "di,dKs")))]
3977 return output_xorsi3 (operands);
3980 (define_insn "xorsi3_5200"
3981 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3982 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3983 (match_operand:SI 2 "general_operand" "d,Ks")))]
3987 (define_insn "xorhi3"
3988 [(set (match_operand:HI 0 "general_operand" "=dm")
3989 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3990 (match_operand:HI 2 "general_operand" "dn")))]
3995 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3996 (xor:HI (match_dup 0)
3997 (match_operand:HI 1 "general_operand" "dn")))]
4002 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4003 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4008 (define_insn "xorqi3"
4009 [(set (match_operand:QI 0 "general_operand" "=dm")
4010 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4011 (match_operand:QI 2 "general_operand" "dn")))]
4016 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4017 (xor:QI (match_dup 0)
4018 (match_operand:QI 1 "general_operand" "dn")))]
4023 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4024 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4029 ;; negation instructions
4031 (define_expand "negdi2"
4032 [(set (match_operand:DI 0 "general_operand" "")
4033 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4038 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4040 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4044 (define_insn "negdi2_internal"
4045 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4046 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4050 if (which_alternative == 0)
4051 return \"neg%.l %0\;negx%.l %0\";
4052 if (GET_CODE (operands[0]) == REG)
4053 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4055 operands[1] = adj_offsettable_operand (operands[0], 4);
4056 if (ADDRESS_REG_P (operands[0]))
4057 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4059 return \"neg%.l %1\;negx%.l %0\";
4062 (define_insn "negdi2_5200"
4063 [(set (match_operand:DI 0 "general_operand" "=d")
4064 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4068 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4069 return \"neg%.l %1\;negx%.l %0\";
4072 (define_expand "negsi2"
4073 [(set (match_operand:SI 0 "general_operand" "")
4074 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4079 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4081 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4085 (define_insn "negsi2_internal"
4086 [(set (match_operand:SI 0 "general_operand" "=dm")
4087 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4091 (define_insn "negsi2_5200"
4092 [(set (match_operand:SI 0 "general_operand" "=d")
4093 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4097 (define_insn "neghi2"
4098 [(set (match_operand:HI 0 "general_operand" "=dm")
4099 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4104 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4105 (neg:HI (match_dup 0)))]
4109 (define_insn "negqi2"
4110 [(set (match_operand:QI 0 "general_operand" "=dm")
4111 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4116 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4117 (neg:QI (match_dup 0)))]
4121 ;; If using software floating point, just flip the sign bit.
4123 (define_expand "negsf2"
4124 [(set (match_operand:SF 0 "general_operand" "")
4125 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4129 if (!TARGET_FPA && !TARGET_68881)
4134 target = operand_subword_force (operands[0], 0, SFmode);
4135 result = expand_binop (SImode, xor_optab,
4136 operand_subword_force (operands[1], 0, SFmode),
4137 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4141 if (result != target)
4142 emit_move_insn (result, target);
4144 /* Make a place for REG_EQUAL. */
4145 emit_move_insn (operands[0], operands[0]);
4151 [(set (match_operand:SF 0 "general_operand" "=x,y")
4152 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4157 [(set (match_operand:SF 0 "general_operand" "=f,d")
4158 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4162 if (DATA_REG_P (operands[0]))
4164 operands[1] = GEN_INT (31);
4165 return \"bchg %1,%0\";
4167 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4168 return \"f%$neg%.x %1,%0\";
4169 return \"f%$neg%.s %f1,%0\";
4172 (define_expand "negdf2"
4173 [(set (match_operand:DF 0 "general_operand" "")
4174 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4178 if (!TARGET_FPA && !TARGET_68881)
4185 target = operand_subword (operands[0], 0, 1, DFmode);
4186 result = expand_binop (SImode, xor_optab,
4187 operand_subword_force (operands[1], 0, DFmode),
4188 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4192 if (result != target)
4193 emit_move_insn (result, target);
4195 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4196 operand_subword_force (operands[1], 1, DFmode));
4198 insns = get_insns ();
4201 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4207 [(set (match_operand:DF 0 "general_operand" "=x,y")
4208 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4213 [(set (match_operand:DF 0 "general_operand" "=f,d")
4214 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4218 if (DATA_REG_P (operands[0]))
4220 operands[1] = GEN_INT (31);
4221 return \"bchg %1,%0\";
4223 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4224 return \"f%&neg%.x %1,%0\";
4225 return \"f%&neg%.d %f1,%0\";
4228 ;; Sqrt instruction for the 68881
4230 (define_insn "sqrtsf2"
4231 [(set (match_operand:SF 0 "general_operand" "=f")
4232 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4236 if (FP_REG_P (operands[1]))
4237 return \"f%$sqrt%.x %1,%0\";
4239 return \"f%$sqrt%.s %1,%0\";
4242 (define_insn "sqrtdf2"
4243 [(set (match_operand:DF 0 "general_operand" "=f")
4244 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4248 if (FP_REG_P (operands[1]))
4249 return \"f%&sqrt%.x %1,%0\";
4251 return \"f%&sqrt%.d %1,%0\";
4254 ;; Absolute value instructions
4255 ;; If using software floating point, just zero the sign bit.
4257 (define_expand "abssf2"
4258 [(set (match_operand:SF 0 "general_operand" "")
4259 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4263 if (!TARGET_FPA && !TARGET_68881)
4268 target = operand_subword_force (operands[0], 0, SFmode);
4269 result = expand_binop (SImode, and_optab,
4270 operand_subword_force (operands[1], 0, SFmode),
4271 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4275 if (result != target)
4276 emit_move_insn (result, target);
4278 /* Make a place for REG_EQUAL. */
4279 emit_move_insn (operands[0], operands[0]);
4285 [(set (match_operand:SF 0 "general_operand" "=x,y")
4286 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4291 [(set (match_operand:SF 0 "general_operand" "=f")
4292 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4296 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4297 return \"f%$abs%.x %1,%0\";
4298 return \"f%$abs%.s %f1,%0\";
4301 (define_expand "absdf2"
4302 [(set (match_operand:DF 0 "general_operand" "")
4303 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4307 if (!TARGET_FPA && !TARGET_68881)
4314 target = operand_subword (operands[0], 0, 1, DFmode);
4315 result = expand_binop (SImode, and_optab,
4316 operand_subword_force (operands[1], 0, DFmode),
4317 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4321 if (result != target)
4322 emit_move_insn (result, target);
4324 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4325 operand_subword_force (operands[1], 1, DFmode));
4327 insns = get_insns ();
4330 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4336 [(set (match_operand:DF 0 "general_operand" "=x,y")
4337 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4342 [(set (match_operand:DF 0 "general_operand" "=f")
4343 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4347 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4348 return \"f%&abs%.x %1,%0\";
4349 return \"f%&abs%.d %f1,%0\";
4352 ;; one complement instructions
4354 ;; "one_cmpldi2" is mainly here to help combine().
4355 (define_insn "one_cmpldi2"
4356 [(set (match_operand:DI 0 "general_operand" "=dm")
4357 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4362 if (GET_CODE (operands[0]) == REG)
4363 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4364 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4365 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4366 operands[1] = operands[0];
4368 operands[1] = adj_offsettable_operand (operands[0], 4);
4369 return \"not%.l %1\;not%.l %0\";
4372 (define_expand "one_cmplsi2"
4373 [(set (match_operand:SI 0 "general_operand" "")
4374 (not:SI (match_operand:SI 1 "general_operand" "")))]
4379 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4381 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4385 (define_insn "one_cmplsi2_internal"
4386 [(set (match_operand:SI 0 "general_operand" "=dm")
4387 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4391 (define_insn "one_cmplsi2_5200"
4392 [(set (match_operand:SI 0 "general_operand" "=d")
4393 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4397 (define_insn "one_cmplhi2"
4398 [(set (match_operand:HI 0 "general_operand" "=dm")
4399 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4404 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4405 (not:HI (match_dup 0)))]
4409 (define_insn "one_cmplqi2"
4410 [(set (match_operand:QI 0 "general_operand" "=dm")
4411 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4416 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4417 (not:QI (match_dup 0)))]
4421 ;; arithmetic shift instructions
4422 ;; We don't need the shift memory by 1 bit instruction
4424 (define_insn "ashldi_extsi"
4425 [(set (match_operand:DI 0 "general_operand" "=ro")
4427 (match_operator:DI 2 "extend_operator"
4428 [(match_operand:SI 1 "general_operand" "rm")])
4434 if (GET_CODE (operands[0]) == REG)
4435 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4437 operands[2] = adj_offsettable_operand (operands[0], 4);
4438 if (ADDRESS_REG_P (operands[0]))
4439 return \"move%.l %1,%0\;sub%.l %2,%2\";
4441 return \"move%.l %1,%0\;clr%.l %2\";
4444 (define_insn "ashldi_sexthi"
4445 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4446 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4448 (clobber (match_scratch:SI 2 "=a,X"))]
4453 if (GET_CODE (operands[0]) == MEM)
4455 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4456 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4457 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4458 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4461 operands[3] = adj_offsettable_operand (operands[0], 4);
4462 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4465 else if (DATA_REG_P (operands[0]))
4466 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4468 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4471 (define_insn "ashldi_const32"
4472 [(set (match_operand:DI 0 "general_operand" "=rm")
4473 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4479 if (GET_CODE (operands[1]) == REG)
4480 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4482 operands[3] = adj_offsettable_operand (operands[1], 4);
4483 if (GET_CODE (operands[0]) == REG)
4484 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4485 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4486 return \"clr%.l %0\;move%.l %3,%0\";
4487 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4488 return \"move%.l %3,%0\;clr%.l %0\";
4490 operands[2] = adj_offsettable_operand (operands[0], 4);
4491 if (ADDRESS_REG_P (operands[2]))
4492 return \"move%.l %3,%0\;sub%.l %2,%2\";
4494 return \"move%.l %3,%0\;clr%.l %2\";
4497 ;; The predicate below must be general_operand, because ashldi3 allows that
4498 (define_insn "ashldi_const"
4499 [(set (match_operand:DI 0 "general_operand" "=d")
4500 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4501 (match_operand 2 "const_int_operand" "n")))]
4502 "((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4503 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4504 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4507 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4508 if (INTVAL (operands[2]) == 1)
4509 return \"add%.l %1,%1\;addx%.l %0,%0\";
4510 else if (INTVAL (operands[2]) == 8)
4511 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4512 else if (INTVAL (operands[2]) == 16)
4513 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4514 else if (INTVAL (operands[2]) == 48)
4515 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4516 else if (INTVAL (operands[2]) == 2)
4517 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4518 else if (INTVAL (operands[2]) == 3)
4519 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4520 else /* 32 < INTVAL (operands[2]) <= 63 */
4522 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4523 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4524 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4525 return \"mov%.l %1,%0\;moveq %#0,%1\";
4529 (define_expand "ashldi3"
4530 [(set (match_operand:DI 0 "general_operand" "")
4531 (ashift:DI (match_operand:DI 1 "general_operand" "")
4532 (match_operand 2 "const_int_operand" "")))]
4536 if (GET_CODE (operands[2]) != CONST_INT
4537 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4538 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4539 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4543 ;; On most 68k models, this makes faster code in a special case.
4545 (define_insn "ashlsi_16"
4546 [(set (match_operand:SI 0 "register_operand" "=d")
4547 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4553 return \"swap %0\;clr%.w %0\";
4556 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4557 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4559 ;; On the 68000, this makes faster code in a special case.
4561 (define_insn "ashlsi_17_24"
4562 [(set (match_operand:SI 0 "register_operand" "=d")
4563 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4564 (match_operand:SI 2 "const_int_operand" "n")))]
4565 "(! TARGET_68020 && !TARGET_5200
4566 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4571 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4572 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4575 (define_insn "ashlsi3"
4576 [(set (match_operand:SI 0 "register_operand" "=d")
4577 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4578 (match_operand:SI 2 "general_operand" "dI")))]
4582 if (operands[2] == const1_rtx)
4584 cc_status.flags = CC_NO_OVERFLOW;
4585 return \"add%.l %0,%0\";
4587 return \"lsl%.l %2,%0\";
4590 (define_insn "ashlhi3"
4591 [(set (match_operand:HI 0 "register_operand" "=d")
4592 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4593 (match_operand:HI 2 "general_operand" "dI")))]
4598 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4599 (ashift:HI (match_dup 0)
4600 (match_operand:HI 1 "general_operand" "dI")))]
4604 (define_insn "ashlqi3"
4605 [(set (match_operand:QI 0 "register_operand" "=d")
4606 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4607 (match_operand:QI 2 "general_operand" "dI")))]
4612 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4613 (ashift:QI (match_dup 0)
4614 (match_operand:QI 1 "general_operand" "dI")))]
4618 ;; On most 68k models, this makes faster code in a special case.
4620 (define_insn "ashrsi_16"
4621 [(set (match_operand:SI 0 "register_operand" "=d")
4622 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4625 "swap %0\;ext%.l %0")
4627 ;; On the 68000, this makes faster code in a special case.
4630 [(set (match_operand:SI 0 "register_operand" "=d")
4631 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4632 (match_operand:SI 2 "const_int_operand" "n")))]
4633 "(! TARGET_68020 && !TARGET_5200
4634 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4637 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4638 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4641 (define_insn "subreghi1ashrdi_const32"
4642 [(set (match_operand:HI 0 "general_operand" "=rm")
4643 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4644 (const_int 32)) 1))]
4648 if (GET_CODE (operands[1]) != REG)
4649 operands[1] = adj_offsettable_operand (operands[1], 2);
4650 return \"move%.w %1,%0\";
4653 (define_insn "subregsi1ashrdi_const32"
4654 [(set (match_operand:SI 0 "general_operand" "=rm")
4655 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4656 (const_int 32)) 1))]
4660 return \"move%.l %1,%0\";
4663 (define_insn "ashrdi_const32"
4664 [(set (match_operand:DI 0 "register_operand" "=d")
4665 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4671 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4673 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4675 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4678 (define_insn "ashrdi_const32_mem"
4679 [(set (match_operand:DI 0 "general_operand" "=o,<")
4680 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4682 (clobber (match_scratch:SI 2 "=d,d"))]
4687 if (which_alternative == 1)
4688 operands[3] = operands[0];
4690 operands[3] = adj_offsettable_operand (operands[0], 4);
4692 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4694 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4697 ;; The predicate below must be general_operand, because ashrdi3 allows that
4698 (define_insn "ashrdi_const"
4699 [(set (match_operand:DI 0 "general_operand" "=d")
4700 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4701 (match_operand 2 "const_int_operand" "n")))]
4703 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4704 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4705 || INTVAL (operands[2]) == 31
4706 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4709 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4710 if (INTVAL (operands[2]) == 63)
4711 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4713 if (INTVAL (operands[2]) == 1)
4714 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4715 else if (INTVAL (operands[2]) == 8)
4716 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4717 else if (INTVAL (operands[2]) == 16)
4718 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4719 else if (INTVAL (operands[2]) == 48)
4720 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4721 else if (INTVAL (operands[2]) == 31)
4722 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4723 else if (INTVAL (operands[2]) == 2)
4724 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4725 else if (INTVAL (operands[2]) == 3)
4726 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4727 else /* 32 < INTVAL (operands[2]) <= 63 */
4729 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4730 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4731 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4732 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4733 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4734 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4738 (define_expand "ashrdi3"
4739 [(set (match_operand:DI 0 "general_operand" "")
4740 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4741 (match_operand 2 "const_int_operand" "")))]
4745 if (GET_CODE (operands[2]) != CONST_INT
4746 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4747 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4748 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4752 ;; On all 68k models, this makes faster code in a special case.
4754 (define_insn "ashrsi_31"
4755 [(set (match_operand:SI 0 "register_operand" "=d")
4756 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4761 return \"add%.l %0,%0\;subx%.l %0,%0\";
4764 (define_insn "ashrsi3"
4765 [(set (match_operand:SI 0 "register_operand" "=d")
4766 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4767 (match_operand:SI 2 "general_operand" "dI")))]
4771 (define_insn "ashrhi3"
4772 [(set (match_operand:HI 0 "register_operand" "=d")
4773 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4774 (match_operand:HI 2 "general_operand" "dI")))]
4779 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4780 (ashiftrt:HI (match_dup 0)
4781 (match_operand:HI 1 "general_operand" "dI")))]
4785 (define_insn "ashrqi3"
4786 [(set (match_operand:QI 0 "register_operand" "=d")
4787 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4788 (match_operand:QI 2 "general_operand" "dI")))]
4793 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4794 (ashiftrt:QI (match_dup 0)
4795 (match_operand:QI 1 "general_operand" "dI")))]
4799 ;; logical shift instructions
4801 ;; commented out because of reload problems in 950612-1.c
4804 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4805 ;; (const_int 32)) 1))
4806 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4807 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4808 ;; (const_int 32)) 1))]
4812 ;; return \"move%.l %0,%1\";
4817 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4818 ;; (const_int 32)) 0))
4819 ;; (set (match_operand:DI 1 "general_operand" "=do")
4820 ;; (lshiftrt:DI (match_dup 0)
4821 ;; (const_int 32)))]
4825 ;; if (GET_CODE (operands[1]) == REG)
4826 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4828 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4829 ;; return \"move%.l %0,%2\;clr%.l %1\";
4832 (define_insn "subreg1lshrdi_const32"
4833 [(set (match_operand:SI 0 "general_operand" "=rm")
4834 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4835 (const_int 32)) 1))]
4839 return \"move%.l %1,%0\";
4842 (define_insn "lshrdi_const32"
4843 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4844 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4850 if (which_alternative == 1)
4851 return \"move%.l %1,%0\;clr%.l %0\";
4852 if (which_alternative == 2)
4853 return \"clr%.l %0\;move%.l %1,%0\";
4854 if (GET_CODE (operands[0]) == REG)
4855 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4857 operands[2] = adj_offsettable_operand (operands[0], 4);
4858 if (GET_CODE (operands[1]) == REG)
4859 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4861 operands[3] = adj_offsettable_operand (operands[1], 4);
4862 if (ADDRESS_REG_P (operands[0]))
4863 return \"move%.l %1,%2\;sub%.l %0,%0\";
4865 return \"move%.l %1,%2\;clr%.l %0\";
4868 ;; The predicate below must be general_operand, because lshrdi3 allows that
4869 (define_insn "lshrdi_const"
4870 [(set (match_operand:DI 0 "general_operand" "=d")
4871 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4872 (match_operand 2 "const_int_operand" "n")))]
4874 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4875 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4876 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4879 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4880 if (INTVAL (operands[2]) == 63)
4881 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4883 if (INTVAL (operands[2]) == 1)
4884 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4885 else if (INTVAL (operands[2]) == 8)
4886 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4887 else if (INTVAL (operands[2]) == 16)
4888 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4889 else if (INTVAL (operands[2]) == 48)
4890 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4891 else if (INTVAL (operands[2]) == 2)
4892 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4893 else if (INTVAL (operands[2]) == 3)
4894 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4895 else /* 32 < INTVAL (operands[2]) <= 63 */
4897 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4898 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4899 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4900 return \"mov%.l %0,%1\;moveq %#0,%0\";
4904 (define_expand "lshrdi3"
4905 [(set (match_operand:DI 0 "general_operand" "")
4906 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4907 (match_operand 2 "const_int_operand" "")))]
4911 if (GET_CODE (operands[2]) != CONST_INT
4912 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4913 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4914 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4918 ;; On all 68k models, this makes faster code in a special case.
4920 (define_insn "lshrsi_31"
4921 [(set (match_operand:SI 0 "register_operand" "=d")
4922 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4927 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4930 ;; On most 68k models, this makes faster code in a special case.
4932 (define_insn "lshrsi_16"
4933 [(set (match_operand:SI 0 "register_operand" "=d")
4934 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4940 return \"clr%.w %0\;swap %0\";
4943 ;; On the 68000, this makes faster code in a special case.
4945 (define_insn "lshrsi_17_24"
4946 [(set (match_operand:SI 0 "register_operand" "=d")
4947 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4948 (match_operand:SI 2 "const_int_operand" "n")))]
4949 "(! TARGET_68020 && !TARGET_5200
4950 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4953 /* I think lsr%.w sets the CC properly. */
4954 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4955 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4958 (define_insn "lshrsi3"
4959 [(set (match_operand:SI 0 "register_operand" "=d")
4960 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4961 (match_operand:SI 2 "general_operand" "dI")))]
4965 (define_insn "lshrhi3"
4966 [(set (match_operand:HI 0 "register_operand" "=d")
4967 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4968 (match_operand:HI 2 "general_operand" "dI")))]
4973 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4974 (lshiftrt:HI (match_dup 0)
4975 (match_operand:HI 1 "general_operand" "dI")))]
4979 (define_insn "lshrqi3"
4980 [(set (match_operand:QI 0 "register_operand" "=d")
4981 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4982 (match_operand:QI 2 "general_operand" "dI")))]
4987 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4988 (lshiftrt:QI (match_dup 0)
4989 (match_operand:QI 1 "general_operand" "dI")))]
4993 ;; rotate instructions
4995 (define_insn "rotlsi3"
4996 [(set (match_operand:SI 0 "register_operand" "=d")
4997 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4998 (match_operand:SI 2 "general_operand" "dINO")))]
5002 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5004 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5006 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5007 return \"ror%.l %2,%0\";
5010 return \"rol%.l %2,%0\";
5013 (define_insn "rotlhi3"
5014 [(set (match_operand:HI 0 "register_operand" "=d")
5015 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5016 (match_operand:HI 2 "general_operand" "dIP")))]
5020 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5022 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5023 return \"ror%.w %2,%0\";
5026 return \"rol%.w %2,%0\";
5030 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5031 (rotate:HI (match_dup 0)
5032 (match_operand:HI 1 "general_operand" "dIP")))]
5036 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5038 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5039 return \"ror%.w %2,%0\";
5042 return \"rol%.w %2,%0\";
5045 (define_insn "rotlqi3"
5046 [(set (match_operand:QI 0 "register_operand" "=d")
5047 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5048 (match_operand:QI 2 "general_operand" "dI")))]
5052 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5054 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5055 return \"ror%.b %2,%0\";
5058 return \"rol%.b %2,%0\";
5062 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5063 (rotate:QI (match_dup 0)
5064 (match_operand:QI 1 "general_operand" "dI")))]
5068 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5070 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5071 return \"ror%.b %2,%0\";
5074 return \"rol%.b %2,%0\";
5077 (define_insn "rotrsi3"
5078 [(set (match_operand:SI 0 "register_operand" "=d")
5079 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5080 (match_operand:SI 2 "general_operand" "dI")))]
5084 (define_insn "rotrhi3"
5085 [(set (match_operand:HI 0 "register_operand" "=d")
5086 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5087 (match_operand:HI 2 "general_operand" "dI")))]
5092 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5093 (rotatert:HI (match_dup 0)
5094 (match_operand:HI 1 "general_operand" "dI")))]
5098 (define_insn "rotrqi3"
5099 [(set (match_operand:QI 0 "register_operand" "=d")
5100 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5101 (match_operand:QI 2 "general_operand" "dI")))]
5106 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5107 (rotatert:QI (match_dup 0)
5108 (match_operand:QI 1 "general_operand" "dI")))]
5113 ;; Bit set/clear in memory byte.
5115 ;; set bit, bit number is int
5116 (define_insn "bsetmemqi"
5117 [(set (match_operand:QI 0 "memory_operand" "+m")
5118 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5119 (match_operand:SI 1 "general_operand" "d")) 0)
5125 return \"bset %1,%0\";
5128 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5130 [(set (match_operand:QI 0 "memory_operand" "+m")
5131 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5132 (match_operator:SI 2 "extend_operator"
5133 [(match_operand 1 "general_operand" "d")])) 0)
5139 return \"bset %1,%0\";
5142 ;; clear bit, bit number is int
5143 (define_insn "bclrmemqi"
5144 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5146 (minus:SI (const_int 7)
5147 (match_operand:SI 1 "general_operand" "d")))
5153 return \"bclr %1,%0\";
5156 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5158 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5160 (minus:SI (const_int 7)
5161 (match_operator:SI 2 "extend_operator"
5162 [(match_operand 1 "general_operand" "d")])))
5168 return \"bclr %1,%0\";
5171 ;; Special cases of bit-field insns which we should
5172 ;; recognize in preference to the general case.
5173 ;; These handle aligned 8-bit and 16-bit fields,
5174 ;; which can usually be done with move instructions.
5177 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5178 ; alignment of structure members is specified.
5180 ; The move is allowed to be odd byte aligned, because that's still faster
5181 ; than an odd byte aligned bit field instruction.
5184 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5186 (match_operand:SI 2 "const_int_operand" "n"))
5187 (match_operand:SI 3 "general_operand" "rmi"))]
5188 "TARGET_68020 && TARGET_BITFIELD
5189 && (INTVAL (operands[2]) % 8) == 0
5190 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5194 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5196 return \"move%.l %3,%0\";
5200 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5201 (match_operand:SI 1 "const_int_operand" "n")
5202 (match_operand:SI 2 "const_int_operand" "n"))
5203 (match_operand:SI 3 "register_operand" "d"))]
5204 "TARGET_68020 && TARGET_BITFIELD
5205 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5206 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5207 && (GET_CODE (operands[0]) == REG
5208 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5211 if (REG_P (operands[0]))
5213 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5214 return \"bfins %3,%0{%b2:%b1}\";
5218 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5220 if (GET_CODE (operands[3]) == MEM)
5221 operands[3] = adj_offsettable_operand (operands[3],
5222 (32 - INTVAL (operands[1])) / 8);
5223 if (INTVAL (operands[1]) == 8)
5224 return \"move%.b %3,%0\";
5225 return \"move%.w %3,%0\";
5230 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5231 ; alignment of structure members is specified.
5233 ; The move is allowed to be odd byte aligned, because that's still faster
5234 ; than an odd byte aligned bit field instruction.
5237 [(set (match_operand:SI 0 "general_operand" "=rm")
5238 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5240 (match_operand:SI 3 "const_int_operand" "n")))]
5241 "TARGET_68020 && TARGET_BITFIELD
5242 && (INTVAL (operands[3]) % 8) == 0
5243 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5247 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5249 return \"move%.l %1,%0\";
5253 [(set (match_operand:SI 0 "general_operand" "=&d")
5254 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5255 (match_operand:SI 2 "const_int_operand" "n")
5256 (match_operand:SI 3 "const_int_operand" "n")))]
5257 "TARGET_68020 && TARGET_BITFIELD
5258 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5259 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5260 && (GET_CODE (operands[1]) == REG
5261 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5264 cc_status.flags |= CC_NOT_NEGATIVE;
5265 if (REG_P (operands[1]))
5267 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5268 return \"bfextu %1{%b3:%b2},%0\";
5272 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5274 output_asm_insn (\"clr%.l %0\", operands);
5275 if (GET_CODE (operands[0]) == MEM)
5276 operands[0] = adj_offsettable_operand (operands[0],
5277 (32 - INTVAL (operands[1])) / 8);
5278 if (INTVAL (operands[2]) == 8)
5279 return \"move%.b %1,%0\";
5280 return \"move%.w %1,%0\";
5284 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5285 ; alignment of structure members is specified.
5287 ; The move is allowed to be odd byte aligned, because that's still faster
5288 ; than an odd byte aligned bit field instruction.
5291 [(set (match_operand:SI 0 "general_operand" "=rm")
5292 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5294 (match_operand:SI 3 "const_int_operand" "n")))]
5295 "TARGET_68020 && TARGET_BITFIELD
5296 && (INTVAL (operands[3]) % 8) == 0
5297 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5301 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5303 return \"move%.l %1,%0\";
5307 [(set (match_operand:SI 0 "general_operand" "=d")
5308 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5309 (match_operand:SI 2 "const_int_operand" "n")
5310 (match_operand:SI 3 "const_int_operand" "n")))]
5311 "TARGET_68020 && TARGET_BITFIELD
5312 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5313 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5314 && (GET_CODE (operands[1]) == REG
5315 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5318 if (REG_P (operands[1]))
5320 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5321 return \"bfexts %1{%b3:%b2},%0\";
5325 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5327 if (INTVAL (operands[2]) == 8)
5328 return \"move%.b %1,%0\;extb%.l %0\";
5329 return \"move%.w %1,%0\;ext%.l %0\";
5332 ;; Bit field instructions, general cases.
5333 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5334 ;; so that its address is reloaded.
5336 (define_expand "extv"
5337 [(set (match_operand:SI 0 "general_operand" "")
5338 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5339 (match_operand:SI 2 "general_operand" "")
5340 (match_operand:SI 3 "general_operand" "")))]
5341 "TARGET_68020 && TARGET_BITFIELD"
5345 [(set (match_operand:SI 0 "general_operand" "=d")
5346 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5347 (match_operand:SI 2 "general_operand" "di")
5348 (match_operand:SI 3 "general_operand" "di")))]
5349 "TARGET_68020 && TARGET_BITFIELD"
5350 "bfexts %1{%b3:%b2},%0")
5352 (define_expand "extzv"
5353 [(set (match_operand:SI 0 "general_operand" "")
5354 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5355 (match_operand:SI 2 "general_operand" "")
5356 (match_operand:SI 3 "general_operand" "")))]
5357 "TARGET_68020 && TARGET_BITFIELD"
5361 [(set (match_operand:SI 0 "general_operand" "=d,d")
5362 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5363 (match_operand:SI 2 "general_operand" "di,di")
5364 (match_operand:SI 3 "general_operand" "di,di")))]
5365 "TARGET_68020 && TARGET_BITFIELD"
5368 if (GET_CODE (operands[2]) == CONST_INT)
5370 if (INTVAL (operands[2]) != 32)
5371 cc_status.flags |= CC_NOT_NEGATIVE;
5377 return \"bfextu %1{%b3:%b2},%0\";
5381 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5382 (match_operand:SI 1 "general_operand" "di")
5383 (match_operand:SI 2 "general_operand" "di"))
5384 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5385 (match_operand 3 "const_int_operand" "n")))]
5386 "TARGET_68020 && TARGET_BITFIELD
5387 && (INTVAL (operands[3]) == -1
5388 || (GET_CODE (operands[1]) == CONST_INT
5389 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5393 return \"bfchg %0{%b2:%b1}\";
5397 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5398 (match_operand:SI 1 "general_operand" "di")
5399 (match_operand:SI 2 "general_operand" "di"))
5401 "TARGET_68020 && TARGET_BITFIELD"
5405 return \"bfclr %0{%b2:%b1}\";
5409 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5410 (match_operand:SI 1 "general_operand" "di")
5411 (match_operand:SI 2 "general_operand" "di"))
5413 "TARGET_68020 && TARGET_BITFIELD"
5417 return \"bfset %0{%b2:%b1}\";
5420 (define_expand "insv"
5421 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5422 (match_operand:SI 1 "general_operand" "")
5423 (match_operand:SI 2 "general_operand" ""))
5424 (match_operand:SI 3 "register_operand" ""))]
5425 "TARGET_68020 && TARGET_BITFIELD"
5429 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5430 (match_operand:SI 1 "general_operand" "di")
5431 (match_operand:SI 2 "general_operand" "di"))
5432 (match_operand:SI 3 "register_operand" "d"))]
5433 "TARGET_68020 && TARGET_BITFIELD"
5434 "bfins %3,%0{%b2:%b1}")
5436 ;; Now recognize bit field insns that operate on registers
5437 ;; (or at least were intended to do so).
5440 [(set (match_operand:SI 0 "general_operand" "=d")
5441 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5442 (match_operand:SI 2 "general_operand" "di")
5443 (match_operand:SI 3 "general_operand" "di")))]
5444 "TARGET_68020 && TARGET_BITFIELD"
5445 "bfexts %1{%b3:%b2},%0")
5448 [(set (match_operand:SI 0 "general_operand" "=d")
5449 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5450 (match_operand:SI 2 "general_operand" "di")
5451 (match_operand:SI 3 "general_operand" "di")))]
5452 "TARGET_68020 && TARGET_BITFIELD"
5455 if (GET_CODE (operands[2]) == CONST_INT)
5457 if (INTVAL (operands[2]) != 32)
5458 cc_status.flags |= CC_NOT_NEGATIVE;
5464 return \"bfextu %1{%b3:%b2},%0\";
5468 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5469 (match_operand:SI 1 "general_operand" "di")
5470 (match_operand:SI 2 "general_operand" "di"))
5472 "TARGET_68020 && TARGET_BITFIELD"
5476 return \"bfclr %0{%b2:%b1}\";
5480 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5481 (match_operand:SI 1 "general_operand" "di")
5482 (match_operand:SI 2 "general_operand" "di"))
5484 "TARGET_68020 && TARGET_BITFIELD"
5488 return \"bfset %0{%b2:%b1}\";
5492 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5493 (match_operand:SI 1 "general_operand" "di")
5494 (match_operand:SI 2 "general_operand" "di"))
5495 (match_operand:SI 3 "register_operand" "d"))]
5496 "TARGET_68020 && TARGET_BITFIELD"
5500 /* These special cases are now recognized by a specific pattern. */
5501 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5502 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5503 return \"move%.w %3,%0\";
5504 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5505 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5506 return \"move%.b %3,%0\";
5508 return \"bfins %3,%0{%b2:%b1}\";
5511 ;; Special patterns for optimizing bit-field instructions.
5515 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5516 (match_operand:SI 1 "const_int_operand" "n")
5517 (match_operand:SI 2 "general_operand" "di")))]
5518 "TARGET_68020 && TARGET_BITFIELD"
5521 if (operands[1] == const1_rtx
5522 && GET_CODE (operands[2]) == CONST_INT)
5524 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5525 return output_btst (operands,
5526 GEN_INT (width - INTVAL (operands[2])),
5529 /* Pass 1000 as SIGNPOS argument so that btst will
5530 not think we are testing the sign bit for an `and'
5531 and assume that nonzero implies a negative result. */
5533 if (INTVAL (operands[1]) != 32)
5534 cc_status.flags = CC_NOT_NEGATIVE;
5535 return \"bftst %0{%b2:%b1}\";
5539 ;;; now handle the register cases
5542 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5543 (match_operand:SI 1 "const_int_operand" "n")
5544 (match_operand:SI 2 "general_operand" "di")))]
5545 "TARGET_68020 && TARGET_BITFIELD"
5548 if (operands[1] == const1_rtx
5549 && GET_CODE (operands[2]) == CONST_INT)
5551 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5552 return output_btst (operands,
5553 GEN_INT (width - INTVAL (operands[2])),
5556 /* Pass 1000 as SIGNPOS argument so that btst will
5557 not think we are testing the sign bit for an `and'
5558 and assume that nonzero implies a negative result. */
5560 if (INTVAL (operands[1]) != 32)
5561 cc_status.flags = CC_NOT_NEGATIVE;
5562 return \"bftst %0{%b2:%b1}\";
5565 (define_insn "scc0_di"
5566 [(set (match_operand:QI 0 "general_operand" "=dm")
5567 (match_operator 1 "valid_dbcc_comparison_p"
5568 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5572 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5575 (define_insn "scc0_di_5200"
5576 [(set (match_operand:QI 0 "general_operand" "=d")
5577 (match_operator 1 "valid_dbcc_comparison_p"
5578 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5582 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5585 (define_insn "scc_di"
5586 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5587 (match_operator 1 "valid_dbcc_comparison_p"
5588 [(match_operand:DI 2 "general_operand" "ro,r")
5589 (match_operand:DI 3 "general_operand" "r,ro")]))]
5593 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5596 (define_insn "scc_di_5200"
5597 [(set (match_operand:QI 0 "general_operand" "=d,d")
5598 (match_operator 1 "valid_dbcc_comparison_p"
5599 [(match_operand:DI 2 "general_operand" "ro,r")
5600 (match_operand:DI 3 "general_operand" "r,ro")]))]
5604 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5607 (define_expand "seq"
5608 [(set (match_operand:QI 0 "general_operand" "")
5609 (eq:QI (cc0) (const_int 0)))]
5613 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5615 m68k_last_compare_had_fp_operands = 0;
5621 [(set (match_operand:QI 0 "general_operand" "=dm")
5622 (eq:QI (cc0) (const_int 0)))]
5625 cc_status = cc_prev_status;
5626 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5630 [(set (match_operand:QI 0 "general_operand" "=d")
5631 (eq:QI (cc0) (const_int 0)))]
5634 cc_status = cc_prev_status;
5635 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5638 (define_expand "sne"
5639 [(set (match_operand:QI 0 "general_operand" "")
5640 (ne:QI (cc0) (const_int 0)))]
5644 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5646 m68k_last_compare_had_fp_operands = 0;
5652 [(set (match_operand:QI 0 "general_operand" "=dm")
5653 (ne:QI (cc0) (const_int 0)))]
5656 cc_status = cc_prev_status;
5657 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5661 [(set (match_operand:QI 0 "general_operand" "=d")
5662 (ne:QI (cc0) (const_int 0)))]
5665 cc_status = cc_prev_status;
5666 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5669 (define_expand "sgt"
5670 [(set (match_operand:QI 0 "general_operand" "")
5671 (gt:QI (cc0) (const_int 0)))]
5675 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5677 m68k_last_compare_had_fp_operands = 0;
5683 [(set (match_operand:QI 0 "general_operand" "=dm")
5684 (gt:QI (cc0) (const_int 0)))]
5687 cc_status = cc_prev_status;
5688 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5692 [(set (match_operand:QI 0 "general_operand" "=d")
5693 (gt:QI (cc0) (const_int 0)))]
5696 cc_status = cc_prev_status;
5697 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5700 (define_expand "sgtu"
5701 [(set (match_operand:QI 0 "general_operand" "")
5702 (gtu:QI (cc0) (const_int 0)))]
5707 [(set (match_operand:QI 0 "general_operand" "=dm")
5708 (gtu:QI (cc0) (const_int 0)))]
5710 "* cc_status = cc_prev_status;
5711 return \"shi %0\"; ")
5714 [(set (match_operand:QI 0 "general_operand" "=d")
5715 (gtu:QI (cc0) (const_int 0)))]
5717 "* cc_status = cc_prev_status;
5718 return \"shi %0\"; ")
5720 (define_expand "slt"
5721 [(set (match_operand:QI 0 "general_operand" "")
5722 (lt:QI (cc0) (const_int 0)))]
5726 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5728 m68k_last_compare_had_fp_operands = 0;
5734 [(set (match_operand:QI 0 "general_operand" "=dm")
5735 (lt:QI (cc0) (const_int 0)))]
5737 "* cc_status = cc_prev_status;
5738 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5741 [(set (match_operand:QI 0 "general_operand" "=d")
5742 (lt:QI (cc0) (const_int 0)))]
5744 "* cc_status = cc_prev_status;
5745 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5747 (define_expand "sltu"
5748 [(set (match_operand:QI 0 "general_operand" "")
5749 (ltu:QI (cc0) (const_int 0)))]
5754 [(set (match_operand:QI 0 "general_operand" "=dm")
5755 (ltu:QI (cc0) (const_int 0)))]
5757 "* cc_status = cc_prev_status;
5758 return \"scs %0\"; ")
5761 [(set (match_operand:QI 0 "general_operand" "=d")
5762 (ltu:QI (cc0) (const_int 0)))]
5764 "* cc_status = cc_prev_status;
5765 return \"scs %0\"; ")
5767 (define_expand "sge"
5768 [(set (match_operand:QI 0 "general_operand" "")
5769 (ge:QI (cc0) (const_int 0)))]
5773 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5775 m68k_last_compare_had_fp_operands = 0;
5781 [(set (match_operand:QI 0 "general_operand" "=dm")
5782 (ge:QI (cc0) (const_int 0)))]
5784 "* cc_status = cc_prev_status;
5785 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5788 [(set (match_operand:QI 0 "general_operand" "=d")
5789 (ge:QI (cc0) (const_int 0)))]
5791 "* cc_status = cc_prev_status;
5792 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5794 (define_expand "sgeu"
5795 [(set (match_operand:QI 0 "general_operand" "")
5796 (geu:QI (cc0) (const_int 0)))]
5801 [(set (match_operand:QI 0 "general_operand" "=dm")
5802 (geu:QI (cc0) (const_int 0)))]
5804 "* cc_status = cc_prev_status;
5805 return \"scc %0\"; ")
5808 [(set (match_operand:QI 0 "general_operand" "=d")
5809 (geu:QI (cc0) (const_int 0)))]
5811 "* cc_status = cc_prev_status;
5812 return \"scc %0\"; ")
5814 (define_expand "sle"
5815 [(set (match_operand:QI 0 "general_operand" "")
5816 (le:QI (cc0) (const_int 0)))]
5820 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5822 m68k_last_compare_had_fp_operands = 0;
5828 [(set (match_operand:QI 0 "general_operand" "=dm")
5829 (le:QI (cc0) (const_int 0)))]
5832 cc_status = cc_prev_status;
5833 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5837 [(set (match_operand:QI 0 "general_operand" "=d")
5838 (le:QI (cc0) (const_int 0)))]
5841 cc_status = cc_prev_status;
5842 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5845 (define_expand "sleu"
5846 [(set (match_operand:QI 0 "general_operand" "")
5847 (leu:QI (cc0) (const_int 0)))]
5852 [(set (match_operand:QI 0 "general_operand" "=dm")
5853 (leu:QI (cc0) (const_int 0)))]
5855 "* cc_status = cc_prev_status;
5856 return \"sls %0\"; ")
5859 [(set (match_operand:QI 0 "general_operand" "=d")
5860 (leu:QI (cc0) (const_int 0)))]
5862 "* cc_status = cc_prev_status;
5863 return \"sls %0\"; ")
5865 ;; Basic conditional jump instructions.
5867 (define_insn "beq0_di"
5869 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5871 (label_ref (match_operand 1 "" ","))
5873 (clobber (match_scratch:SI 2 "=d,d"))]
5878 if (which_alternative == 1)
5880 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5882 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5884 if ((cc_prev_status.value1
5885 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5886 || (cc_prev_status.value2
5887 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5889 cc_status = cc_prev_status;
5891 return \"jbeq %l1\";
5896 if (GET_CODE (operands[0]) == REG)
5897 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5899 operands[3] = adj_offsettable_operand (operands[0], 4);
5900 if (! ADDRESS_REG_P (operands[0]))
5903 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5905 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5908 operands[4] = gen_label_rtx();
5909 if (TARGET_68020 || TARGET_5200)
5912 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5914 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5920 #ifdef SGS_CMP_ORDER
5921 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5923 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5926 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5929 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5930 CODE_LABEL_NUMBER (operands[4]));
5934 (define_insn "bne0_di"
5936 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5938 (label_ref (match_operand 1 "" ","))
5940 (clobber (match_scratch:SI 2 "=d,X"))]
5944 if ((cc_prev_status.value1
5945 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5946 || (cc_prev_status.value2
5947 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5949 cc_status = cc_prev_status;
5951 return \"jbne %l1\";
5957 if (GET_CODE (operands[0]) == REG)
5958 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5960 operands[3] = adj_offsettable_operand (operands[0], 4);
5961 if (!ADDRESS_REG_P (operands[0]))
5964 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5966 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5969 if (TARGET_68020 || TARGET_5200)
5972 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5974 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5980 #ifdef SGS_CMP_ORDER
5981 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5983 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5986 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5991 (define_insn "bge0_di"
5993 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5995 (label_ref (match_operand 1 "" ""))
6000 if ((cc_prev_status.value1
6001 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6002 || (cc_prev_status.value2
6003 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6005 cc_status = cc_prev_status;
6006 if (cc_status.flags & CC_REVERSED)
6009 return \"jble %l1\";
6017 return \"jbpl %l1\";
6024 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6025 output_asm_insn(\"tst%.l %0\", operands);
6028 /* On an address reg, cmpw may replace cmpl. */
6029 #ifdef SGS_CMP_ORDER
6030 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6032 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6037 return \"jbpl %l1\";
6043 (define_insn "blt0_di"
6045 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6047 (label_ref (match_operand 1 "" ""))
6052 if ((cc_prev_status.value1
6053 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6054 || (cc_prev_status.value2
6055 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6057 cc_status = cc_prev_status;
6058 if (cc_status.flags & CC_REVERSED)
6061 return \"jbgt %l1\";
6069 return \"jbmi %l1\";
6076 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6077 output_asm_insn(\"tst%.l %0\", operands);
6080 /* On an address reg, cmpw may replace cmpl. */
6081 #ifdef SGS_CMP_ORDER
6082 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6084 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6089 return \"jbmi %l1\";
6097 (if_then_else (eq (cc0)
6099 (label_ref (match_operand 0 "" ""))
6105 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6107 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6113 (if_then_else (ne (cc0)
6115 (label_ref (match_operand 0 "" ""))
6121 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6123 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6129 (if_then_else (gt (cc0)
6131 (label_ref (match_operand 0 "" ""))
6136 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6138 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6144 (if_then_else (gtu (cc0)
6146 (label_ref (match_operand 0 "" ""))
6151 return \"jbhi %l0\";
6159 (if_then_else (lt (cc0)
6161 (label_ref (match_operand 0 "" ""))
6166 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6168 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6174 (if_then_else (ltu (cc0)
6176 (label_ref (match_operand 0 "" ""))
6181 return \"jbcs %l0\";
6189 (if_then_else (ge (cc0)
6191 (label_ref (match_operand 0 "" ""))
6196 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6198 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6204 (if_then_else (geu (cc0)
6206 (label_ref (match_operand 0 "" ""))
6211 return \"jbcc %l0\";
6219 (if_then_else (le (cc0)
6221 (label_ref (match_operand 0 "" ""))
6226 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6228 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6234 (if_then_else (leu (cc0)
6236 (label_ref (match_operand 0 "" ""))
6241 return \"jbls %l0\";
6247 ;; Negated conditional jump instructions.
6251 (if_then_else (eq (cc0)
6254 (label_ref (match_operand 0 "" ""))))]
6259 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6261 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6267 (if_then_else (ne (cc0)
6270 (label_ref (match_operand 0 "" ""))))]
6275 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6277 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6283 (if_then_else (gt (cc0)
6286 (label_ref (match_operand 0 "" ""))))]
6290 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6292 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6298 (if_then_else (gtu (cc0)
6301 (label_ref (match_operand 0 "" ""))))]
6305 return \"jbls %l0\";
6313 (if_then_else (lt (cc0)
6316 (label_ref (match_operand 0 "" ""))))]
6320 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6322 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6328 (if_then_else (ltu (cc0)
6331 (label_ref (match_operand 0 "" ""))))]
6335 return \"jbcc %l0\";
6343 (if_then_else (ge (cc0)
6346 (label_ref (match_operand 0 "" ""))))]
6350 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6352 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6358 (if_then_else (geu (cc0)
6361 (label_ref (match_operand 0 "" ""))))]
6365 return \"jbcs %l0\";
6373 (if_then_else (le (cc0)
6376 (label_ref (match_operand 0 "" ""))))]
6380 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6382 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6388 (if_then_else (leu (cc0)
6391 (label_ref (match_operand 0 "" ""))))]
6395 return \"jbhi %l0\";
6401 ;; Unconditional and other jump instructions
6404 (label_ref (match_operand 0 "" "")))]
6408 return \"jbra %l0\";
6414 ;; We support two different ways of handling dispatch tables.
6415 ;; The NeXT uses absolute tables, and other machines use relative.
6416 ;; This define_expand can generate either kind.
6417 (define_expand "tablejump"
6418 [(parallel [(set (pc) (match_operand 0 "" ""))
6419 (use (label_ref (match_operand 1 "" "")))])]
6423 #ifdef CASE_VECTOR_PC_RELATIVE
6424 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6425 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6429 ;; Jump to variable address from dispatch table of absolute addresses.
6431 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6432 (use (label_ref (match_operand 1 "" "")))]
6436 return \"jmp (%0)\";
6442 ;; Jump to variable address from dispatch table of relative addresses.
6446 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6447 (use (label_ref (match_operand 1 "" "")))]
6450 #ifdef ASM_RETURN_CASE_JUMP
6451 ASM_RETURN_CASE_JUMP;
6454 #ifdef ASM_OUTPUT_CASE_LABEL
6456 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6458 return \"jmp 6(%%pc,%0.w)\";
6463 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6465 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6466 #endif /* end !CRDS */
6471 return \"jmp 2(pc,%0.w)\";
6473 return \"jmp 2(%%pc,%0.w)\";
6474 #endif /* end !CRDS */
6481 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6483 return \"extl %0\;jmp pc@(2,%0:l)\";
6489 return \"jmp (2,pc,%0.w)\";
6491 return \"jmp pc@(2,%0:w)\";
6498 ;; Decrement-and-branch insns.
6502 (ne (match_operand:HI 0 "general_operand" "+d*g")
6504 (label_ref (match_operand 1 "" ""))
6507 (plus:HI (match_dup 0)
6513 if (DATA_REG_P (operands[0]))
6514 return \"dbra %0,%l1\";
6515 if (GET_CODE (operands[0]) == MEM)
6519 return \"sub%.w %#1,%0\;jbcc %l1\";
6521 return \"subq%.w %#1,%0\;jbcc %l1\";
6523 #else /* not MOTOROLA */
6524 return \"subqw %#1,%0\;jcc %l1\";
6528 #ifdef SGS_CMP_ORDER
6530 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6532 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6534 #else /* not SGS_CMP_ORDER */
6535 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6537 #else /* not MOTOROLA */
6538 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6545 (ne (match_operand:SI 0 "general_operand" "+d*g")
6547 (label_ref (match_operand 1 "" ""))
6550 (plus:SI (match_dup 0)
6558 if (DATA_REG_P (operands[0]))
6559 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6560 if (GET_CODE (operands[0]) == MEM)
6561 return \"sub%.l %#1,%0\;jbcc %l1\";
6563 if (DATA_REG_P (operands[0]))
6564 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6565 if (GET_CODE (operands[0]) == MEM)
6566 return \"subq%.l %#1,%0\;jbcc %l1\";
6567 #endif /* NO_ADDSUB_Q */
6568 #ifdef SGS_CMP_ORDER
6570 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6572 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6574 #else /* not SGS_CMP_ORDER */
6575 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6576 #endif /* not SGS_CMP_ORDER */
6577 #else /* not MOTOROLA */
6578 if (DATA_REG_P (operands[0]))
6579 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6580 if (GET_CODE (operands[0]) == MEM)
6581 return \"subql %#1,%0\;jcc %l1\";
6582 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6583 #endif /* not MOTOROLA */
6586 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6591 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6594 (label_ref (match_operand 1 "" ""))
6597 (plus:HI (match_dup 0)
6599 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6605 if (DATA_REG_P (operands[0]))
6606 return \"dbra %0,%l1\";
6607 if (GET_CODE (operands[0]) == MEM)
6608 return \"sub%.w %#1,%0\;jbcc %l1\";
6610 if (DATA_REG_P (operands[0]))
6611 return \"dbra %0,%l1\";
6612 if (GET_CODE (operands[0]) == MEM)
6613 return \"subq%.w %#1,%0\;jbcc %l1\";
6615 #ifdef SGS_CMP_ORDER
6617 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6619 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6621 #else /* not SGS_CMP_ORDER */
6622 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6623 #endif /* not SGS_CMP_ORDER */
6624 #else /* not MOTOROLA */
6625 if (DATA_REG_P (operands[0]))
6626 return \"dbra %0,%l1\";
6627 if (GET_CODE (operands[0]) == MEM)
6628 return \"subqw %#1,%0\;jcc %l1\";
6629 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6630 #endif /* not MOTOROLA */
6633 (define_expand "decrement_and_branch_until_zero"
6634 [(parallel [(set (pc)
6636 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6639 (label_ref (match_operand 1 "" ""))
6642 (plus:SI (match_dup 0)
6650 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6653 (label_ref (match_operand 1 "" ""))
6656 (plus:SI (match_dup 0)
6658 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6664 if (DATA_REG_P (operands[0]))
6665 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6666 if (GET_CODE (operands[0]) == MEM)
6667 return \"sub%.l %#1,%0\;jbcc %l1\";
6669 if (DATA_REG_P (operands[0]))
6670 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6671 if (GET_CODE (operands[0]) == MEM)
6672 return \"subq%.l %#1,%0\;jbcc %l1\";
6674 #ifdef SGS_CMP_ORDER
6676 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6678 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6680 #else /* not SGS_CMP_ORDER */
6681 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6682 #endif /* not SGS_CMP_ORDER */
6683 #else /* not MOTOROLA */
6684 if (DATA_REG_P (operands[0]))
6685 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6686 if (GET_CODE (operands[0]) == MEM)
6687 return \"subql %#1,%0\;jcc %l1\";
6688 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6689 #endif /* not MOTOROLA */
6693 ;; For PIC calls, in order to be able to support
6694 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6695 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6697 ;; PIC calls are handled by loading the address of the function into a
6698 ;; register (via movsi), then emitting a register indirect call using
6699 ;; the "jsr" function call syntax.
6701 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6702 ;; operand to the jbsr statement to indicate that this call should
6703 ;; go through the PLT (why? because this is the way that Sun does it).
6705 ;; We have different patterns for PIC calls and non-PIC calls. The
6706 ;; different patterns are only used to choose the right syntax.
6708 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6709 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6710 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6711 ;; section at link time. However, all global objects reference are still
6712 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6713 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6714 ;; We need to have a way to differentiate these two different operands.
6716 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6717 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6718 ;; to be changed to recognize function calls symbol_ref operand as a valid
6719 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6720 ;; avoid the compiler to load this symbol_ref operand into a register.
6721 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6722 ;; since the value is a PC relative offset, not a real address.
6724 ;; All global objects are treated in the similar way as in SUN3. The only
6725 ;; difference is: on m68k svr4, the reference of such global object needs
6726 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6727 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6730 ;; Call subroutine with no return value.
6731 (define_expand "call"
6732 [(call (match_operand:QI 0 "memory_operand" "")
6733 (match_operand:SI 1 "general_operand" ""))]
6734 ;; Operand 1 not really used on the m68000.
6739 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6740 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6743 ;; This is a normal call sequence.
6745 [(call (match_operand:QI 0 "memory_operand" "o")
6746 (match_operand:SI 1 "general_operand" "g"))]
6747 ;; Operand 1 not really used on the m68000.
6751 #if defined (MOTOROLA) && !defined (USE_GAS)
6753 if (GET_CODE (operands[0]) == MEM
6754 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6763 ;; This is a PIC call sequence.
6765 [(call (match_operand:QI 0 "memory_operand" "o")
6766 (match_operand:SI 1 "general_operand" "g"))]
6767 ;; Operand 1 not really used on the m68000.
6771 if (GET_CODE (operands[0]) == MEM
6772 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6775 return \"bsr.l %0\";
6778 return \"bsr.l %0@PLTPC\";
6780 return \"bsr %0@PLTPC\";
6784 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6785 GAS just plain ignores it. */
6786 return \"jbsr %0,a1\";
6791 ;; Call subroutine, returning value in operand 0
6792 ;; (which must be a hard register).
6793 ;; See comments before "call" regarding PIC calls.
6794 (define_expand "call_value"
6795 [(set (match_operand 0 "" "")
6796 (call (match_operand:QI 1 "memory_operand" "")
6797 (match_operand:SI 2 "general_operand" "")))]
6798 ;; Operand 2 not really used on the m68000.
6802 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6803 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6806 ;; This is a normal call_value
6808 [(set (match_operand 0 "" "=rf")
6809 (call (match_operand:QI 1 "memory_operand" "o")
6810 (match_operand:SI 2 "general_operand" "g")))]
6811 ;; Operand 2 not really used on the m68000.
6814 #if defined (MOTOROLA) && !defined (USE_GAS)
6816 if (GET_CODE (operands[1]) == MEM
6817 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6826 ;; This is a PIC call_value
6828 [(set (match_operand 0 "" "=rf")
6829 (call (match_operand:QI 1 "memory_operand" "o")
6830 (match_operand:SI 2 "general_operand" "g")))]
6831 ;; Operand 2 not really used on the m68000.
6834 if (GET_CODE (operands[1]) == MEM
6835 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6839 return \"bsr.l %1\";
6842 return \"bsr.l %1@PLTPC\";
6844 return \"bsr %1@PLTPC\";
6848 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6849 GAS just plain ignores it. */
6850 return \"jbsr %1,a1\";
6856 ;; Call subroutine returning any type.
6858 (define_expand "untyped_call"
6859 [(parallel [(call (match_operand 0 "" "")
6861 (match_operand 1 "" "")
6862 (match_operand 2 "" "")])]
6863 "NEEDS_UNTYPED_CALL"
6868 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6870 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6872 rtx set = XVECEXP (operands[2], 0, i);
6873 emit_move_insn (SET_DEST (set), SET_SRC (set));
6876 /* The optimizer does not know that the call sets the function value
6877 registers we stored in the result block. We avoid problems by
6878 claiming that all hard registers are used and clobbered at this
6880 emit_insn (gen_blockage ());
6885 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6886 ;; all of memory. This blocks insns from being moved across this point.
6888 (define_insn "blockage"
6889 [(unspec_volatile [(const_int 0)] 0)]
6898 (define_insn "probe"
6903 operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
6904 GEN_INT (NEED_PROBE));
6905 return \"tstl %a0\";
6908 ;; Used for frameless functions which save no regs and allocate no locals.
6909 (define_insn "return"
6914 if (current_function_pops_args == 0)
6916 operands[0] = GEN_INT (current_function_pops_args);
6920 (define_insn "indirect_jump"
6921 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6925 ;; This should not be used unless the add/sub insns can't be.
6928 [(set (match_operand:SI 0 "general_operand" "=a")
6929 (match_operand:QI 1 "address_operand" "p"))]
6934 /* Recognize an insn that refers to a table of offsets. Such an insn will
6935 need to refer to a label on the insn. So output one. Use the
6936 label-number of the table of offsets to generate this label. This code,
6937 and similar code above, assumes that there will be at most one reference
6939 if (GET_CODE (operands[1]) == PLUS
6940 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6941 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6943 rtx labelref = XEXP (operands[1], 1);
6944 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6946 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6947 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6949 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6950 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6951 #endif /* not SGS */
6952 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6953 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6954 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6955 #ifdef SGS_SWITCH_TABLES
6956 /* Set flag saying we need to define the symbol
6957 LD%n (with value L%n-LI%n) at the end of the switch table. */
6958 switch_table_difference_label_flag = 1;
6959 #endif /* SGS_SWITCH_TABLES */
6960 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6962 #endif /* SGS_NO_LI */
6964 return \"lea %a1,%0\";
6967 ;; This is the first machine-dependent peephole optimization.
6968 ;; It is useful when a floating value is returned from a function call
6969 ;; and then is moved into an FP register.
6970 ;; But it is mainly intended to test the support for these optimizations.
6973 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6974 (set (match_operand:DF 0 "register_operand" "=f")
6975 (match_operand:DF 1 "register_operand" "ad"))]
6976 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6980 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6981 output_asm_insn (\"move%.l %1,%@\", xoperands);
6982 output_asm_insn (\"move%.l %1,%-\", operands);
6983 return \"fmove%.d %+,%0\";
6987 ;; Optimize a stack-adjust followed by a push of an argument.
6988 ;; This is said to happen frequently with -msoft-float
6989 ;; when there are consecutive library calls.
6992 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6993 (match_operand:SI 0 "const_int_operand" "n")))
6994 (set (match_operand:SF 1 "push_operand" "=m")
6995 (match_operand:SF 2 "general_operand" "rmfF"))]
6996 "INTVAL (operands[0]) >= 4
6997 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7000 if (INTVAL (operands[0]) > 4)
7003 xoperands[0] = stack_pointer_rtx;
7004 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7006 if (INTVAL (xoperands[1]) <= 8)
7009 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7011 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7013 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7015 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7016 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7020 if (INTVAL (xoperands[1]) <= 0x7FFF)
7023 output_asm_insn (\"add%.w %1,%0\", xoperands);
7026 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7028 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7032 output_asm_insn (\"add%.l %1,%0\", xoperands);
7034 if (FP_REG_P (operands[2]))
7035 return \"fmove%.s %2,%@\";
7036 return \"move%.l %2,%@\";
7039 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7042 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7043 (match_operand:SI 0 "const_int_operand" "n")))
7044 (set (match_operand:SI 1 "push_operand" "=m")
7045 (match_operand:SI 2 "general_operand" "g"))]
7046 "INTVAL (operands[0]) >= 4
7047 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7050 if (INTVAL (operands[0]) > 4)
7053 xoperands[0] = stack_pointer_rtx;
7054 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7056 if (INTVAL (xoperands[1]) <= 8)
7059 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7061 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7063 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7065 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7066 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7070 if (INTVAL (xoperands[1]) <= 0x7FFF)
7073 output_asm_insn (\"add%.w %1,%0\", xoperands);
7077 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7079 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7084 output_asm_insn (\"add%.l %1,%0\", xoperands);
7086 if (operands[2] == const0_rtx)
7087 return \"clr%.l %@\";
7088 return \"move%.l %2,%@\";
7091 ;; Speed up pushing a single byte but leaving four bytes of space.
7094 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7095 (match_operand:QI 1 "general_operand" "dami"))
7096 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7097 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7102 if (GET_CODE (operands[1]) == REG)
7103 return \"move%.l %1,%-\";
7105 xoperands[1] = operands[1];
7107 = gen_rtx_MEM (QImode,
7108 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
7110 xoperands[3] = stack_pointer_rtx;
7112 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7114 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7119 [(set (match_operand:SI 0 "register_operand" "=d")
7121 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7122 (match_operand:HI 1 "general_operand" "rmn"))]
7123 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7126 if (GET_CODE (operands[1]) == CONST_INT)
7128 if (operands[1] == const0_rtx
7129 && (DATA_REG_P (operands[0])
7130 || GET_CODE (operands[0]) == MEM)
7131 /* clr insns on 68000 read before writing.
7132 This isn't so on the 68010, but we have no TARGET_68010. */
7133 && ((TARGET_68020 || TARGET_5200)
7134 || !(GET_CODE (operands[0]) == MEM
7135 && MEM_VOLATILE_P (operands[0]))))
7136 return \"clr%.w %0\";
7138 return \"move%.w %1,%0\";
7146 ;; jCC label ; abnormal loop termination
7147 ;; dbra dN, loop ; normal loop termination
7155 ;; Which moves the jCC condition outside the inner loop for free.
7158 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7159 [(cc0) (const_int 0)])
7160 (label_ref (match_operand 2 "" ""))
7165 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7168 (label_ref (match_operand 1 "" ""))
7171 (plus:HI (match_dup 0)
7173 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7177 output_dbcc_and_branch (operands);
7182 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7183 [(cc0) (const_int 0)])
7184 (label_ref (match_operand 2 "" ""))
7189 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7192 (label_ref (match_operand 1 "" ""))
7195 (plus:SI (match_dup 0)
7197 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7201 output_dbcc_and_branch (operands);
7206 ;; FPA multiply and add.
7208 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7209 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7210 (match_operand:DF 2 "general_operand" "xH,y,y"))
7211 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7214 fpma%.d %1,%w2,%w3,%0
7215 fpma%.d %x1,%x2,%x3,%0
7216 fpma%.d %x1,%x2,%x3,%0")
7219 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7220 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7221 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7222 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7225 fpma%.s %1,%w2,%w3,%0
7227 fpma%.s %1,%2,%3,%0")
7229 ;; FPA Multiply and subtract
7231 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7232 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7233 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7234 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7237 fpms%.d %3,%w2,%w1,%0
7238 fpms%.d %x3,%2,%x1,%0
7239 fpms%.d %x3,%2,%x1,%0")
7242 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7243 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7244 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7245 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7248 fpms%.s %3,%w2,%w1,%0
7250 fpms%.s %3,%2,%1,%0")
7253 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7254 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7255 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7256 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7259 fpmr%.d %2,%w1,%w3,%0
7260 fpmr%.d %x2,%1,%x3,%0
7261 fpmr%.d %x2,%1,%x3,%0")
7264 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7265 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7266 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7267 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7270 fpmr%.s %2,%w1,%w3,%0
7271 fpmr%.s %x2,%1,%x3,%0
7272 fpmr%.s %x2,%1,%x3,%0")
7274 ;; FPA Add and multiply
7276 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7277 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7278 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7279 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7282 fpam%.d %2,%w1,%w3,%0
7283 fpam%.d %x2,%1,%x3,%0
7284 fpam%.d %x2,%1,%x3,%0")
7287 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7288 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7289 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7290 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7293 fpam%.s %2,%w1,%w3,%0
7294 fpam%.s %x2,%1,%x3,%0
7295 fpam%.s %x2,%1,%x3,%0")
7297 ;;FPA Subtract and multiply
7299 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7300 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7301 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7302 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7305 fpsm%.d %2,%w1,%w3,%0
7306 fpsm%.d %x2,%1,%x3,%0
7307 fpsm%.d %x2,%1,%x3,%0")
7310 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7311 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7312 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7313 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7316 fpsm%.d %3,%w2,%w1,%0
7317 fpsm%.d %x3,%2,%x1,%0
7318 fpsm%.d %x3,%2,%x1,%0")
7321 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7322 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7323 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7324 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7327 fpsm%.s %2,%w1,%w3,%0
7328 fpsm%.s %x2,%1,%x3,%0
7329 fpsm%.s %x2,%1,%x3,%0")
7332 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7333 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7334 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7335 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7338 fpsm%.s %3,%w2,%w1,%0
7339 fpsm%.s %x3,%2,%x1,%0
7340 fpsm%.s %x3,%2,%x1,%0")
7342 (define_expand "tstxf"
7344 (match_operand:XF 0 "nonimmediate_operand" ""))]
7346 "m68k_last_compare_had_fp_operands = 1;")
7350 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7354 cc_status.flags = CC_IN_68881;
7355 return \"ftst%.x %0\";
7358 (define_expand "cmpxf"
7360 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7361 (match_operand:XF 1 "nonimmediate_operand" "")))]
7363 "m68k_last_compare_had_fp_operands = 1;")
7367 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7368 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7372 cc_status.flags = CC_IN_68881;
7373 #ifdef SGS_CMP_ORDER
7374 if (REG_P (operands[0]))
7376 if (REG_P (operands[1]))
7377 return \"fcmp%.x %0,%1\";
7379 return \"fcmp%.x %0,%f1\";
7381 cc_status.flags |= CC_REVERSED;
7382 return \"fcmp%.x %1,%f0\";
7384 if (REG_P (operands[0]))
7386 if (REG_P (operands[1]))
7387 return \"fcmp%.x %1,%0\";
7389 return \"fcmp%.x %f1,%0\";
7391 cc_status.flags |= CC_REVERSED;
7392 return \"fcmp%.x %f0,%1\";
7396 (define_insn "extendsfxf2"
7397 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7398 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7402 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7404 if (REGNO (operands[0]) == REGNO (operands[1]))
7406 /* Extending float to double in an fp-reg is a no-op.
7407 NOTICE_UPDATE_CC has already assumed that the
7408 cc will be set. So cancel what it did. */
7409 cc_status = cc_prev_status;
7412 return \"f%$move%.x %1,%0\";
7414 if (FP_REG_P (operands[0]))
7415 return \"f%$move%.s %f1,%0\";
7416 return \"fmove%.x %f1,%0\";
7420 (define_insn "extenddfxf2"
7421 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7423 (match_operand:DF 1 "general_operand" "f,m")))]
7427 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7429 if (REGNO (operands[0]) == REGNO (operands[1]))
7431 /* Extending float to double in an fp-reg is a no-op.
7432 NOTICE_UPDATE_CC has already assumed that the
7433 cc will be set. So cancel what it did. */
7434 cc_status = cc_prev_status;
7437 return \"fmove%.x %1,%0\";
7439 if (FP_REG_P (operands[0]))
7440 return \"f%&move%.d %f1,%0\";
7441 return \"fmove%.x %f1,%0\";
7444 (define_insn "truncxfdf2"
7445 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7447 (match_operand:XF 1 "general_operand" "f,f")))]
7451 if (REG_P (operands[0]))
7453 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7454 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7455 return \"move%.l %+,%0\";
7457 return \"fmove%.d %f1,%0\";
7460 (define_insn "truncxfsf2"
7461 [(set (match_operand:SF 0 "general_operand" "=dm")
7463 (match_operand:XF 1 "general_operand" "f")))]
7467 (define_insn "floatsixf2"
7468 [(set (match_operand:XF 0 "general_operand" "=f")
7469 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7473 (define_insn "floathixf2"
7474 [(set (match_operand:XF 0 "general_operand" "=f")
7475 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7479 (define_insn "floatqixf2"
7480 [(set (match_operand:XF 0 "general_operand" "=f")
7481 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7485 (define_insn "ftruncxf2"
7486 [(set (match_operand:XF 0 "general_operand" "=f")
7487 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7491 if (FP_REG_P (operands[1]))
7492 return \"fintrz%.x %f1,%0\";
7493 return \"fintrz%.x %f1,%0\";
7496 (define_insn "fixxfqi2"
7497 [(set (match_operand:QI 0 "general_operand" "=dm")
7498 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7502 (define_insn "fixxfhi2"
7503 [(set (match_operand:HI 0 "general_operand" "=dm")
7504 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7508 (define_insn "fixxfsi2"
7509 [(set (match_operand:SI 0 "general_operand" "=dm")
7510 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7515 [(set (match_operand:XF 0 "general_operand" "=f")
7516 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7517 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7522 [(set (match_operand:XF 0 "general_operand" "=f")
7523 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7524 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7529 [(set (match_operand:XF 0 "general_operand" "=f")
7530 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7531 (match_operand:XF 1 "general_operand" "0")))]
7535 (define_insn "addxf3"
7536 [(set (match_operand:XF 0 "general_operand" "=f")
7537 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7538 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7542 if (REG_P (operands[2]))
7543 return \"fadd%.x %2,%0\";
7544 return \"fadd%.x %f2,%0\";
7548 [(set (match_operand:XF 0 "general_operand" "=f")
7549 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7550 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7555 [(set (match_operand:XF 0 "general_operand" "=f")
7556 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7557 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7562 [(set (match_operand:XF 0 "general_operand" "=f")
7563 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7564 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7568 (define_insn "subxf3"
7569 [(set (match_operand:XF 0 "general_operand" "=f")
7570 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7571 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7575 if (REG_P (operands[2]))
7576 return \"fsub%.x %2,%0\";
7577 return \"fsub%.x %f2,%0\";
7581 [(set (match_operand:XF 0 "general_operand" "=f")
7582 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7583 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7588 [(set (match_operand:XF 0 "general_operand" "=f")
7589 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7590 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7595 [(set (match_operand:XF 0 "general_operand" "=f")
7596 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7597 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7601 (define_insn "mulxf3"
7602 [(set (match_operand:XF 0 "general_operand" "=f")
7603 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7604 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7608 if (REG_P (operands[2]))
7609 return \"fmul%.x %2,%0\";
7610 return \"fmul%.x %f2,%0\";
7614 [(set (match_operand:XF 0 "general_operand" "=f")
7615 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7616 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7621 [(set (match_operand:XF 0 "general_operand" "=f")
7622 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7623 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7628 [(set (match_operand:XF 0 "general_operand" "=f")
7629 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7630 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7634 (define_insn "divxf3"
7635 [(set (match_operand:XF 0 "general_operand" "=f")
7636 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7637 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7641 if (REG_P (operands[2]))
7642 return \"fdiv%.x %2,%0\";
7643 return \"fdiv%.x %f2,%0\";
7646 (define_expand "negxf2"
7647 [(set (match_operand:XF 0 "general_operand" "")
7648 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7652 /* ??? There isn't an FPA define_insn so we could handle it here too.
7653 For now we don't (paranoia). */
7661 target = operand_subword (operands[0], 0, 1, XFmode);
7662 result = expand_binop (SImode, xor_optab,
7663 operand_subword_force (operands[1], 0, XFmode),
7664 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7668 if (result != target)
7669 emit_move_insn (result, target);
7671 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7672 operand_subword_force (operands[1], 1, XFmode));
7673 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7674 operand_subword_force (operands[1], 2, XFmode));
7676 insns = get_insns ();
7679 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7684 (define_insn "negxf2_68881"
7685 [(set (match_operand:XF 0 "general_operand" "=f")
7686 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7690 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7691 return \"fneg%.x %1,%0\";
7692 return \"fneg%.x %f1,%0\";
7695 (define_expand "absxf2"
7696 [(set (match_operand:XF 0 "general_operand" "")
7697 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7701 /* ??? There isn't an FPA define_insn so we could handle it here too.
7702 For now we don't (paranoia). */
7710 target = operand_subword (operands[0], 0, 1, XFmode);
7711 result = expand_binop (SImode, and_optab,
7712 operand_subword_force (operands[1], 0, XFmode),
7713 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7717 if (result != target)
7718 emit_move_insn (result, target);
7720 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7721 operand_subword_force (operands[1], 1, XFmode));
7722 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7723 operand_subword_force (operands[1], 2, XFmode));
7725 insns = get_insns ();
7728 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7733 (define_insn "absxf2_68881"
7734 [(set (match_operand:XF 0 "general_operand" "=f")
7735 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7739 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7740 return \"fabs%.x %1,%0\";
7741 return \"fabs%.x %f1,%0\";
7744 (define_insn "sqrtxf2"
7745 [(set (match_operand:XF 0 "general_operand" "=f")
7746 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7750 (define_insn "sinsf2"
7751 [(set (match_operand:SF 0 "general_operand" "=f")
7752 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7753 "TARGET_68881 && flag_fast_math"
7756 if (FP_REG_P (operands[1]))
7757 return \"fsin%.x %1,%0\";
7759 return \"fsin%.s %1,%0\";
7762 (define_insn "sindf2"
7763 [(set (match_operand:DF 0 "general_operand" "=f")
7764 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7765 "TARGET_68881 && flag_fast_math"
7768 if (FP_REG_P (operands[1]))
7769 return \"fsin%.x %1,%0\";
7771 return \"fsin%.d %1,%0\";
7774 (define_insn "sinxf2"
7775 [(set (match_operand:XF 0 "general_operand" "=f")
7776 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7777 "TARGET_68881 && flag_fast_math"
7780 (define_insn "cossf2"
7781 [(set (match_operand:SF 0 "general_operand" "=f")
7782 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7783 "TARGET_68881 && flag_fast_math"
7786 if (FP_REG_P (operands[1]))
7787 return \"fcos%.x %1,%0\";
7789 return \"fcos%.s %1,%0\";
7792 (define_insn "cosdf2"
7793 [(set (match_operand:DF 0 "general_operand" "=f")
7794 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7795 "TARGET_68881 && flag_fast_math"
7798 if (FP_REG_P (operands[1]))
7799 return \"fcos%.x %1,%0\";
7801 return \"fcos%.d %1,%0\";
7804 (define_insn "cosxf2"
7805 [(set (match_operand:XF 0 "general_operand" "=f")
7806 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7807 "TARGET_68881 && flag_fast_math"