1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- Information about MCF5200 port.
25 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
26 ;;- 68k ISA. Differences include reduced support for byte and word
27 ;;- operands and the removal of BCD, bitfield, rotate, and integer
28 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
29 ;;- removed opcodes and addressing modes off.
33 ;;- instruction definitions
35 ;;- @@The original PO technology requires these to be ordered by speed,
36 ;;- @@ so that assigner will pick the fastest.
38 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
40 ;;- When naming insn's (operand 0 of define_insn) be careful about using
41 ;;- names from other targets machine descriptions.
43 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
44 ;;- updates for most instructions.
46 ;;- Operand classes for the register allocator:
47 ;;- 'a' one of the address registers can be used.
48 ;;- 'd' one of the data registers can be used.
49 ;;- 'f' one of the m68881/fpu registers can be used
50 ;;- 'r' either a data or an address register can be used.
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
57 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
60 ;;- Immediate integer operand constraints:
62 ;;- 'J' -32768 .. 32767
63 ;;- 'K' all integers EXCEPT -128 .. 127
65 ;;- 'M' all integers EXCEPT -256 .. 255
71 ;;- "%." size separator ("." or "") move%.l d0,d1
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TUNE_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
95 ;;- These new instructions aren't directly in the md. They are brought
96 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
99 ;;- Information about 68060 port.
101 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
102 ;;- be emulated in software by the OS. It is faster to avoid these
103 ;;- instructions and issue a library call rather than trapping into
104 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
105 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
106 ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off.
108 ;;- Some of these insn's are composites of several m68000 op codes.
109 ;;- The assembler (or final @@??) insures that the appropriate one is
120 ;; UNSPEC_VOLATILE usage:
123 [(UNSPECV_BLOCKAGE 0)
126 ;; Registers by name.
137 (include "predicates.md")
138 (include "constraints.md")
140 ;; Mode macros for floating point operations.
141 ;; Valid floating point modes
142 (define_mode_macro FP [SF DF (XF "TARGET_68881")])
143 ;; Mnemonic infix to round result
144 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
145 ;; Mnemonic infix to round result for mul or div instruction
146 (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
147 ;; Suffix specifying source operand format
148 (define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
149 ;; Allowable D registers
150 (define_mode_attr dreg [(SF "d") (DF "") (XF "")])
151 ;; Allowable 68881 constant constraints
152 (define_mode_attr const [(SF "F") (DF "G") (XF "")])
155 [(set (match_operand:DF 0 "push_operand" "=m")
156 (match_operand:DF 1 "general_operand" "ro<>fE"))]
159 if (FP_REG_P (operands[1]))
160 return "fmove%.d %f1,%0";
161 return output_move_double (operands);
164 (define_insn "pushdi"
165 [(set (match_operand:DI 0 "push_operand" "=m")
166 (match_operand:DI 1 "general_operand" "ro<>Fi"))]
169 return output_move_double (operands);
172 ;; We don't want to allow a constant operand for test insns because
173 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
174 ;; be folded while optimizing anyway.
176 (define_expand "tstdi"
177 [(parallel [(set (cc0)
178 (match_operand:DI 0 "nonimmediate_operand" ""))
179 (clobber (match_scratch:SI 1 ""))
180 (clobber (match_scratch:DI 2 ""))])]
182 "m68k_last_compare_had_fp_operands = 0;")
186 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
187 (clobber (match_scratch:SI 1 "=X,d"))
188 (clobber (match_scratch:DI 2 "=d,X"))]
191 if (which_alternative == 0)
195 xoperands[0] = operands[2];
196 xoperands[1] = operands[0];
197 output_move_double (xoperands);
198 cc_status.flags |= CC_REVERSED;
199 return "neg%.l %R2\;negx%.l %2";
201 if (find_reg_note (insn, REG_DEAD, operands[0]))
203 cc_status.flags |= CC_REVERSED;
204 return "neg%.l %R0\;negx%.l %0";
208 'sub' clears %1, and also clears the X cc bit
209 'tst' sets the Z cc bit according to the low part of the DImode operand
210 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
212 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
215 (define_expand "tstsi"
217 (match_operand:SI 0 "nonimmediate_operand" ""))]
219 "m68k_last_compare_had_fp_operands = 0;")
223 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
226 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
228 /* If you think that the 68020 does not support tstl a0,
229 reread page B-167 of the 68020 manual more carefully. */
230 /* On an address reg, cmpw may replace cmpl. */
231 return "cmp%.w #0,%0";
234 ;; This can't use an address register, because comparisons
235 ;; with address registers as second operand always test the whole word.
236 (define_expand "tsthi"
238 (match_operand:HI 0 "nonimmediate_operand" ""))]
240 "m68k_last_compare_had_fp_operands = 0;")
244 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
248 (define_expand "tstqi"
250 (match_operand:QI 0 "nonimmediate_operand" ""))]
252 "m68k_last_compare_had_fp_operands = 0;")
256 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
260 (define_expand "tst<mode>"
262 (match_operand:FP 0 "general_operand" ""))]
265 m68k_last_compare_had_fp_operands = 1;
268 (define_insn "tst<mode>_68881"
270 (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
273 cc_status.flags = CC_IN_68881;
274 if (FP_REG_P (operands[0]))
276 return "ftst%.<FP:prec> %0";
279 (define_insn "tst<mode>_cf"
281 (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
282 "TARGET_COLDFIRE_FPU"
284 cc_status.flags = CC_IN_68881;
285 if (FP_REG_P (operands[0]))
287 return "ftst%.<FP:prec> %0";
291 ;; compare instructions.
293 (define_expand "cmpdi"
296 (compare (match_operand:DI 0 "nonimmediate_operand" "")
297 (match_operand:DI 1 "general_operand" "")))
298 (clobber (match_dup 2))])]
300 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
304 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
305 (match_operand:DI 2 "general_operand" "d,0")))
306 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
309 if (rtx_equal_p (operands[0], operands[1]))
310 return "sub%.l %R2,%R0\;subx%.l %2,%0";
313 cc_status.flags |= CC_REVERSED;
314 return "sub%.l %R1,%R0\;subx%.l %1,%0";
318 (define_expand "cmpsi"
320 (compare (match_operand:SI 0 "nonimmediate_operand" "")
321 (match_operand:SI 1 "general_operand" "")))]
324 m68k_last_compare_had_fp_operands = 0;
327 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
330 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
331 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
334 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
335 return "cmpm%.l %1,%0";
336 if (REG_P (operands[1])
337 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
339 cc_status.flags |= CC_REVERSED;
340 return "cmp%.l %d0,%d1";
342 if (ADDRESS_REG_P (operands[0])
343 && GET_CODE (operands[1]) == CONST_INT
344 && INTVAL (operands[1]) < 0x8000
345 && INTVAL (operands[1]) >= -0x8000)
346 return "cmp%.w %1,%0";
347 return "cmp%.l %d1,%d0";
352 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
353 (match_operand:SI 1 "general_operand" "r,mrKs")))]
356 if (REG_P (operands[1])
357 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
359 cc_status.flags |= CC_REVERSED;
360 return "cmp%.l %d0,%d1";
362 return "cmp%.l %d1,%d0";
365 (define_expand "cmphi"
367 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
368 (match_operand:HI 1 "general_src_operand" "")))]
370 "m68k_last_compare_had_fp_operands = 0;")
374 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
375 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
378 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
379 return "cmpm%.w %1,%0";
380 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
381 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
383 cc_status.flags |= CC_REVERSED;
384 return "cmp%.w %d0,%d1";
386 return "cmp%.w %d1,%d0";
389 (define_expand "cmpqi"
391 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
392 (match_operand:QI 1 "general_src_operand" "")))]
394 "m68k_last_compare_had_fp_operands = 0;")
398 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
399 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
402 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
403 return "cmpm%.b %1,%0";
404 if (REG_P (operands[1])
405 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
407 cc_status.flags |= CC_REVERSED;
408 return "cmp%.b %d0,%d1";
410 return "cmp%.b %d1,%d0";
413 (define_expand "cmp<mode>"
415 (compare (match_operand:FP 0 "general_operand" "")
416 (match_operand:FP 1 "general_operand" "")))]
419 m68k_last_compare_had_fp_operands = 1;
420 if (TARGET_COLDFIRE && !reload_completed)
421 operands[1] = force_reg (<MODE>mode, operands[1]);
424 (define_insn "cmp<mode>_68881"
426 (compare (match_operand:FP 0 "general_operand" "f,m<FP:const>")
427 (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,f")))]
430 cc_status.flags = CC_IN_68881;
431 if (FP_REG_P (operands[0]))
433 if (FP_REG_P (operands[1]))
434 return "fcmp%.x %1,%0";
436 return "fcmp%.<FP:prec> %f1,%0";
438 cc_status.flags |= CC_REVERSED;
439 return "fcmp%.<FP:prec> %f0,%1";
442 (define_insn "cmp<mode>_cf"
444 (compare (match_operand:FP 0 "general_operand" "f,<FP:dreg><Q>U")
445 (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,f")))]
446 "TARGET_COLDFIRE_FPU"
448 cc_status.flags = CC_IN_68881;
449 if (FP_REG_P (operands[0]))
451 if (FP_REG_P (operands[1]))
452 return "fcmp%.d %1,%0";
454 return "fcmp%.<FP:prec> %f1,%0";
456 cc_status.flags |= CC_REVERSED;
457 return "fcmp%.<FP:prec> %f0,%1";
460 ;; Recognizers for btst instructions.
462 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
463 ;; specified as a constant, so we must disable all patterns that may extract
464 ;; from a MEM at a constant bit position if we can't use this as a constraint.
467 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
469 (minus:SI (const_int 7)
470 (match_operand:SI 1 "general_operand" "di"))))]
473 return output_btst (operands, operands[1], operands[0], insn, 7);
476 ;; This is the same as the above pattern except for the constraints. The 'i'
480 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
482 (minus:SI (const_int 7)
483 (match_operand:SI 1 "general_operand" "d"))))]
486 return output_btst (operands, operands[1], operands[0], insn, 7);
490 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
492 (minus:SI (const_int 31)
493 (match_operand:SI 1 "general_operand" "di"))))]
496 return output_btst (operands, operands[1], operands[0], insn, 31);
499 ;; The following two patterns are like the previous two
500 ;; except that they use the fact that bit-number operands
501 ;; are automatically masked to 3 or 5 bits.
504 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
506 (minus:SI (const_int 7)
508 (match_operand:SI 1 "register_operand" "d")
512 return output_btst (operands, operands[1], operands[0], insn, 7);
516 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
518 (minus:SI (const_int 31)
520 (match_operand:SI 1 "register_operand" "d")
524 return output_btst (operands, operands[1], operands[0], insn, 31);
527 ;; Nonoffsettable mem refs are ok in this one pattern
528 ;; since we don't try to adjust them.
530 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
532 (match_operand:SI 1 "const_int_operand" "n")))]
533 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
535 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
536 return output_btst (operands, operands[1], operands[0], insn, 7);
540 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
542 (match_operand:SI 1 "const_int_operand" "n")))]
545 if (GET_CODE (operands[0]) == MEM)
547 operands[0] = adjust_address (operands[0], QImode,
548 INTVAL (operands[1]) / 8);
549 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
550 return output_btst (operands, operands[1], operands[0], insn, 7);
552 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
553 return output_btst (operands, operands[1], operands[0], insn, 31);
556 ;; This is the same as the above pattern except for the constraints.
557 ;; The 'o' has been replaced with 'Q'.
560 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
562 (match_operand:SI 1 "const_int_operand" "n")))]
565 if (GET_CODE (operands[0]) == MEM)
567 operands[0] = adjust_address (operands[0], QImode,
568 INTVAL (operands[1]) / 8);
569 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
570 return output_btst (operands, operands[1], operands[0], insn, 7);
572 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
573 return output_btst (operands, operands[1], operands[0], insn, 31);
579 ;; A special case in which it is not desirable
580 ;; to reload the constant into a data register.
581 (define_insn "pushexthisi_const"
582 [(set (match_operand:SI 0 "push_operand" "=m")
583 (match_operand:SI 1 "const_int_operand" "J"))]
584 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
586 if (operands[1] == const0_rtx)
588 if (valid_mov3q_const (INTVAL (operands[1])))
589 return "mov3q%.l %1,%-";
594 ;(define_insn "swapsi"
595 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
596 ; (match_operand:SI 1 "general_operand" "+r"))
597 ; (set (match_dup 1) (match_dup 0))]
601 ;; Special case of fullword move when source is zero.
602 ;; The reason this is special is to avoid loading a zero
603 ;; into a data reg with moveq in order to store it elsewhere.
605 (define_insn "movsi_const0"
606 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
608 ;; clr insns on 68000 read before writing.
609 "((TARGET_68010 || TARGET_COLDFIRE)
610 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
612 if (ADDRESS_REG_P (operands[0]))
614 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
616 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
618 return "sub%.l %0,%0";
620 /* moveq is faster on the 68000. */
621 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
622 return "moveq #0,%0";
626 ;; General case of fullword move.
628 ;; This is the main "hook" for PIC code. When generating
629 ;; PIC, movsi is responsible for determining when the source address
630 ;; needs PIC relocation and appropriately calling legitimize_pic_address
631 ;; to perform the actual relocation.
633 ;; In both the PIC and non-PIC cases the patterns generated will
634 ;; matched by the next define_insn.
635 (define_expand "movsi"
636 [(set (match_operand:SI 0 "" "")
637 (match_operand:SI 1 "" ""))]
640 rtx tmp, base, offset;
642 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
644 /* The source is an address which requires PIC relocation.
645 Call legitimize_pic_address with the source, mode, and a relocation
646 register (a new pseudo, or the final destination if reload_in_progress
647 is set). Then fall through normally */
648 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
649 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
651 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
653 /* Don't allow writes to memory except via a register;
654 the m68k doesn't consider PC-relative addresses to be writable. */
655 if (symbolic_operand (operands[0], SImode))
656 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
657 else if (GET_CODE (operands[0]) == MEM
658 && symbolic_operand (XEXP (operands[0], 0), SImode))
659 operands[0] = gen_rtx_MEM (SImode,
660 force_reg (SImode, XEXP (operands[0], 0)));
662 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
664 split_const (operands[1], &base, &offset);
665 if (GET_CODE (base) == SYMBOL_REF
666 && !offset_within_block_p (base, INTVAL (offset)))
668 tmp = no_new_pseudos ? operands[0] : gen_reg_rtx (SImode);
669 emit_move_insn (tmp, base);
670 emit_insn (gen_addsi3 (operands[0], tmp, offset));
676 ;; General case of fullword move. The register constraints
677 ;; force integer constants in range for a moveq to be reloaded
678 ;; if they are headed for memory.
680 ;; Notes: make sure no alternative allows g vs g.
681 ;; We don't allow f-regs since fixed point cannot go in them.
682 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
683 (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
687 return output_move_simode (operands);
690 ;; ColdFire move instructions can have at most one operand of mode >= 6.
691 (define_insn "*movsi_cf"
692 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
693 (match_operand:SI 1 "general_operand" "g,Rr<Q>,U"))]
695 "* return output_move_simode (operands);")
697 ;; Special case of fullword move, where we need to get a non-GOT PIC
698 ;; reference into an address register.
700 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
701 (match_operand:SI 1 "pcrel_address" ""))]
704 if (push_operand (operands[0], SImode))
709 (define_expand "movhi"
710 [(set (match_operand:HI 0 "nonimmediate_operand" "")
711 (match_operand:HI 1 "general_operand" ""))]
716 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
717 (match_operand:HI 1 "general_src_operand" "gS"))]
719 "* return output_move_himode (operands);")
722 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
723 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
725 "* return output_move_himode (operands);")
727 (define_expand "movstricthi"
728 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
729 (match_operand:HI 1 "general_src_operand" ""))]
734 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
735 (match_operand:HI 1 "general_src_operand" "rmSn"))]
737 "* return output_move_stricthi (operands);")
740 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
741 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
743 "* return output_move_stricthi (operands);")
745 (define_expand "movqi"
746 [(set (match_operand:QI 0 "nonimmediate_operand" "")
747 (match_operand:QI 1 "general_src_operand" ""))]
752 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
753 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
755 "* return output_move_qimode (operands);")
758 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
759 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
761 "* return output_move_qimode (operands);")
763 (define_expand "movstrictqi"
764 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
765 (match_operand:QI 1 "general_src_operand" ""))]
770 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
771 (match_operand:QI 1 "general_src_operand" "dmSn"))]
773 "* return output_move_strictqi (operands);")
776 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
777 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
779 "* return output_move_strictqi (operands);")
781 (define_expand "pushqi1"
782 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
783 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
784 (match_operand:QI 0 "general_operand" ""))]
788 (define_expand "reload_insf"
789 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
790 (match_operand:SF 1 "general_operand" "mf"))
791 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
792 "TARGET_COLDFIRE_FPU"
794 if (emit_move_sequence (operands, SFmode, operands[2]))
797 /* We don't want the clobber emitted, so handle this ourselves. */
798 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
802 (define_expand "reload_outsf"
803 [(set (match_operand:SF 0 "general_operand" "")
804 (match_operand:SF 1 "register_operand" "f"))
805 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
806 "TARGET_COLDFIRE_FPU"
808 if (emit_move_sequence (operands, SFmode, operands[2]))
811 /* We don't want the clobber emitted, so handle this ourselves. */
812 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
816 (define_expand "movsf"
817 [(set (match_operand:SF 0 "nonimmediate_operand" "")
818 (match_operand:SF 1 "general_operand" ""))]
823 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
824 (match_operand:SF 1 "general_operand" "rmfF"))]
827 if (FP_REG_P (operands[0]))
829 if (FP_REG_P (operands[1]))
830 return "f%$move%.x %1,%0";
831 else if (ADDRESS_REG_P (operands[1]))
832 return "move%.l %1,%-\;f%$move%.s %+,%0";
833 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
834 return output_move_const_single (operands);
835 return "f%$move%.s %f1,%0";
837 if (FP_REG_P (operands[1]))
839 if (ADDRESS_REG_P (operands[0]))
840 return "fmove%.s %1,%-\;move%.l %+,%0";
841 return "fmove%.s %f1,%0";
843 if (operands[1] == CONST0_RTX (SFmode)
844 /* clr insns on 68000 read before writing. */
845 && ((TARGET_68010 || TARGET_COLDFIRE)
846 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
848 if (ADDRESS_REG_P (operands[0]))
850 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
852 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
854 return "sub%.l %0,%0";
856 /* moveq is faster on the 68000. */
857 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
858 return "moveq #0,%0";
861 return "move%.l %1,%0";
864 (define_insn "movsf_cf_soft"
865 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
866 (match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
867 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
869 return "move%.l %1,%0";
872 ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
873 ;; The move instructions can handle all combinations.
874 (define_insn "movsf_cf_hard"
875 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
877 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
879 "TARGET_COLDFIRE_FPU"
881 if (which_alternative == 4 || which_alternative == 5) {
885 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
886 REAL_VALUE_TO_TARGET_SINGLE (r, l);
887 xoperands[0] = operands[0];
888 xoperands[1] = GEN_INT (l);
889 if (which_alternative == 5) {
891 if (ADDRESS_REG_P (xoperands[0]))
892 output_asm_insn ("sub%.l %0,%0", xoperands);
894 output_asm_insn ("clr%.l %0", xoperands);
896 if (GET_CODE (operands[0]) == MEM
897 && symbolic_operand (XEXP (operands[0], 0), SImode))
898 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
900 output_asm_insn ("move%.l %1,%0", xoperands);
904 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
906 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands);
909 if (FP_REG_P (operands[0]))
911 if (ADDRESS_REG_P (operands[1]))
912 return "move%.l %1,%-;fsmove%.s %+,%0";
913 if (FP_REG_P (operands[1]))
914 return "fsmove%.d %1,%0";
915 return "fsmove%.s %f1,%0";
917 if (FP_REG_P (operands[1]))
919 if (ADDRESS_REG_P (operands[0]))
920 return "fmove%.s %1,%-;move%.l %+,%0";
921 return "fmove%.s %f1,%0";
923 if (operands[1] == CONST0_RTX (SFmode))
925 if (ADDRESS_REG_P (operands[0]))
926 return "sub%.l %0,%0";
929 return "move%.l %1,%0";
932 (define_expand "reload_indf"
933 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
934 (match_operand:DF 1 "general_operand" "mf"))
935 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
936 "TARGET_COLDFIRE_FPU"
938 if (emit_move_sequence (operands, DFmode, operands[2]))
941 /* We don't want the clobber emitted, so handle this ourselves. */
942 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
946 (define_expand "reload_outdf"
947 [(set (match_operand:DF 0 "general_operand" "")
948 (match_operand:DF 1 "register_operand" "f"))
949 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
950 "TARGET_COLDFIRE_FPU"
952 if (emit_move_sequence (operands, DFmode, operands[2]))
955 /* We don't want the clobber emitted, so handle this ourselves. */
956 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
960 (define_expand "movdf"
961 [(set (match_operand:DF 0 "nonimmediate_operand" "")
962 (match_operand:DF 1 "general_operand" ""))]
965 if (TARGET_COLDFIRE_FPU)
966 if (emit_move_sequence (operands, DFmode, 0))
971 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
972 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
973 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
974 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
977 if (FP_REG_P (operands[0]))
979 if (FP_REG_P (operands[1]))
980 return "f%&move%.x %1,%0";
981 if (REG_P (operands[1]))
984 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
985 output_asm_insn ("move%.l %1,%-", xoperands);
986 output_asm_insn ("move%.l %1,%-", operands);
987 return "f%&move%.d %+,%0";
989 if (GET_CODE (operands[1]) == CONST_DOUBLE)
990 return output_move_const_double (operands);
991 return "f%&move%.d %f1,%0";
993 else if (FP_REG_P (operands[1]))
995 if (REG_P (operands[0]))
997 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
998 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
999 return "move%.l %+,%0";
1002 return "fmove%.d %f1,%0";
1004 return output_move_double (operands);
1007 (define_insn "movdf_cf_soft"
1008 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1009 (match_operand:DF 1 "general_operand" "g,r"))]
1010 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1012 return output_move_double (operands);
1015 (define_insn "movdf_cf_hard"
1016 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1017 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1018 "TARGET_COLDFIRE_FPU"
1024 switch (which_alternative)
1027 return "fdmove%.d %1,%0";
1029 return "fmove%.d %1,%0";
1031 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
1033 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0";
1034 case 4: case 5: case 6:
1035 return output_move_double (operands);
1037 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1038 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1039 xoperands[0] = operands[0];
1040 xoperands[1] = GEN_INT (l[0]);
1041 xoperands[2] = GEN_INT (l[1]);
1042 if (operands[1] == CONST0_RTX (DFmode))
1043 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1047 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
1050 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
1056 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1057 ;; allowed. Most but not all have predicates and constraint that disallow
1058 ;; constants. Most but not all have output templates that handle constants.
1059 ;; See also LEGITIMATE_CONSTANT_P.
1061 (define_expand "movxf"
1062 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1063 (match_operand:XF 1 "general_operand" ""))]
1066 /* We can't rewrite operands during reload. */
1067 if (! reload_in_progress)
1069 if (CONSTANT_P (operands[1]))
1071 operands[1] = force_const_mem (XFmode, operands[1]);
1072 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1073 operands[1] = adjust_address (operands[1], XFmode, 0);
1075 if (flag_pic && TARGET_PCREL)
1077 /* Don't allow writes to memory except via a register; the
1078 m68k doesn't consider PC-relative addresses to be writable. */
1079 if (GET_CODE (operands[0]) == MEM
1080 && symbolic_operand (XEXP (operands[0], 0), SImode))
1081 operands[0] = gen_rtx_MEM (XFmode,
1082 force_reg (SImode, XEXP (operands[0], 0)));
1088 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r")
1089 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
1092 if (FP_REG_P (operands[0]))
1094 if (FP_REG_P (operands[1]))
1095 return "fmove%.x %1,%0";
1096 if (REG_P (operands[1]))
1099 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1100 output_asm_insn ("move%.l %1,%-", xoperands);
1101 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1102 output_asm_insn ("move%.l %1,%-", xoperands);
1103 output_asm_insn ("move%.l %1,%-", operands);
1104 return "fmove%.x %+,%0";
1106 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1107 return "fmove%.x %1,%0";
1108 return "fmove%.x %f1,%0";
1110 if (FP_REG_P (operands[1]))
1112 if (REG_P (operands[0]))
1114 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1115 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1116 output_asm_insn ("move%.l %+,%0", operands);
1117 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1118 return "move%.l %+,%0";
1120 /* Must be memory destination. */
1121 return "fmove%.x %f1,%0";
1123 return output_move_double (operands);
1127 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1128 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1129 "! TARGET_68881 && ! TARGET_COLDFIRE"
1131 if (FP_REG_P (operands[0]))
1133 if (FP_REG_P (operands[1]))
1134 return "fmove%.x %1,%0";
1135 if (REG_P (operands[1]))
1138 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1139 output_asm_insn ("move%.l %1,%-", xoperands);
1140 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1141 output_asm_insn ("move%.l %1,%-", xoperands);
1142 output_asm_insn ("move%.l %1,%-", operands);
1143 return "fmove%.x %+,%0";
1145 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1146 return "fmove%.x %1,%0";
1147 return "fmove%.x %f1,%0";
1149 if (FP_REG_P (operands[1]))
1151 if (REG_P (operands[0]))
1153 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1154 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1155 output_asm_insn ("move%.l %+,%0", operands);
1156 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1157 return "move%.l %+,%0";
1160 return "fmove%.x %f1,%0";
1162 return output_move_double (operands);
1166 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1167 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1168 "! TARGET_68881 && TARGET_COLDFIRE"
1169 "* return output_move_double (operands);")
1171 (define_expand "movdi"
1172 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1173 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1174 (match_operand:DI 1 "general_operand" ""))]
1178 ;; movdi can apply to fp regs in some cases
1180 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1181 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1182 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1183 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1184 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1185 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1186 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1189 if (FP_REG_P (operands[0]))
1191 if (FP_REG_P (operands[1]))
1192 return "fmove%.x %1,%0";
1193 if (REG_P (operands[1]))
1196 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1197 output_asm_insn ("move%.l %1,%-", xoperands);
1198 output_asm_insn ("move%.l %1,%-", operands);
1199 return "fmove%.d %+,%0";
1201 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1202 return output_move_const_double (operands);
1203 return "fmove%.d %f1,%0";
1205 else if (FP_REG_P (operands[1]))
1207 if (REG_P (operands[0]))
1209 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1210 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1211 return "move%.l %+,%0";
1214 return "fmove%.d %f1,%0";
1216 return output_move_double (operands);
1220 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1221 (match_operand:DI 1 "general_operand" "g,r"))]
1223 "* return output_move_double (operands);")
1225 ;; Thus goes after the move instructions
1226 ;; because the move instructions are better (require no spilling)
1227 ;; when they can apply. It goes before the add/sub insns
1228 ;; so we will prefer it to them.
1230 (define_insn "pushasi"
1231 [(set (match_operand:SI 0 "push_operand" "=m")
1232 (match_operand:SI 1 "address_operand" "p"))]
1236 ;; truncation instructions
1237 (define_insn "truncsiqi2"
1238 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1240 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1243 if (GET_CODE (operands[0]) == REG)
1245 /* Must clear condition codes, since the move.l bases them on
1246 the entire 32 bits, not just the desired 8 bits. */
1248 return "move%.l %1,%0";
1250 if (GET_CODE (operands[1]) == MEM)
1251 operands[1] = adjust_address (operands[1], QImode, 3);
1252 return "move%.b %1,%0";
1255 (define_insn "trunchiqi2"
1256 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1258 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1261 if (GET_CODE (operands[0]) == REG
1262 && (GET_CODE (operands[1]) == MEM
1263 || GET_CODE (operands[1]) == CONST_INT))
1265 /* Must clear condition codes, since the move.w bases them on
1266 the entire 16 bits, not just the desired 8 bits. */
1268 return "move%.w %1,%0";
1270 if (GET_CODE (operands[0]) == REG)
1272 /* Must clear condition codes, since the move.l bases them on
1273 the entire 32 bits, not just the desired 8 bits. */
1275 return "move%.l %1,%0";
1277 if (GET_CODE (operands[1]) == MEM)
1278 operands[1] = adjust_address (operands[1], QImode, 1);
1279 return "move%.b %1,%0";
1282 (define_insn "truncsihi2"
1283 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1285 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1288 if (GET_CODE (operands[0]) == REG)
1290 /* Must clear condition codes, since the move.l bases them on
1291 the entire 32 bits, not just the desired 8 bits. */
1293 return "move%.l %1,%0";
1295 if (GET_CODE (operands[1]) == MEM)
1296 operands[1] = adjust_address (operands[1], QImode, 2);
1297 return "move%.w %1,%0";
1300 ;; zero extension instructions
1302 ;; two special patterns to match various post_inc/pre_dec patterns
1303 (define_insn_and_split "*zero_extend_inc"
1304 [(set (match_operand 0 "post_inc_operand" "")
1305 (zero_extend (match_operand 1 "register_operand" "")))]
1306 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1307 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1308 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1316 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1319 (define_insn_and_split "*zero_extend_dec"
1320 [(set (match_operand 0 "pre_dec_operand" "")
1321 (zero_extend (match_operand 1 "register_operand" "")))]
1322 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) &&
1323 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1324 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1325 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1333 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1336 (define_insn_and_split "zero_extendqidi2"
1337 [(set (match_operand:DI 0 "register_operand" "")
1338 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1343 (zero_extend:SI (match_dup 1)))
1347 operands[2] = gen_lowpart (SImode, operands[0]);
1348 operands[3] = gen_highpart (SImode, operands[0]);
1351 (define_insn_and_split "zero_extendhidi2"
1352 [(set (match_operand:DI 0 "register_operand" "")
1353 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1358 (zero_extend:SI (match_dup 1)))
1362 operands[2] = gen_lowpart (SImode, operands[0]);
1363 operands[3] = gen_highpart (SImode, operands[0]);
1366 (define_expand "zero_extendsidi2"
1367 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1368 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1371 if (GET_CODE (operands[0]) == MEM
1372 && GET_CODE (operands[1]) == MEM)
1373 operands[1] = force_reg (SImode, operands[1]);
1376 (define_insn_and_split "*zero_extendsidi2"
1377 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1378 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1379 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1387 operands[2] = gen_lowpart (SImode, operands[0]);
1388 operands[3] = gen_highpart (SImode, operands[0]);
1391 (define_insn "*zero_extendhisi2_cf"
1392 [(set (match_operand:SI 0 "register_operand" "=d")
1393 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1397 (define_insn "zero_extendhisi2"
1398 [(set (match_operand:SI 0 "register_operand" "=d")
1399 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1403 (define_expand "zero_extendqihi2"
1404 [(set (match_operand:HI 0 "register_operand" "")
1405 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1409 (define_insn "*zero_extendqihi2"
1410 [(set (match_operand:HI 0 "register_operand" "=d")
1411 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1415 (define_insn "*zero_extendqisi2_cfv4"
1416 [(set (match_operand:SI 0 "register_operand" "=d")
1417 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1421 (define_insn "zero_extendqisi2"
1422 [(set (match_operand:SI 0 "register_operand" "=d")
1423 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1427 ;; these two pattern split everything else which isn't matched by
1428 ;; something else above
1430 [(set (match_operand 0 "register_operand" "")
1431 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1434 && reg_mentioned_p (operands[0], operands[1])"
1435 [(set (strict_low_part (match_dup 2))
1438 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))]
1440 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1441 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1])));
1442 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]);
1446 [(set (match_operand 0 "register_operand" "")
1447 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1448 "!TARGET_ISAB && reload_completed"
1451 (set (strict_low_part (match_dup 2))
1454 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1457 ;; sign extension instructions
1459 (define_insn "extendqidi2"
1460 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1461 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1465 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1467 return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
1468 if (TARGET_68020 || TARGET_COLDFIRE)
1470 if (ADDRESS_REG_P (operands[1]))
1471 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1473 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1477 if (ADDRESS_REG_P (operands[1]))
1478 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1480 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1484 (define_insn "extendhidi2"
1485 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1487 (match_operand:HI 1 "general_src_operand" "rmS")))]
1491 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1493 return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
1494 if (TARGET_68020 || TARGET_COLDFIRE)
1495 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1497 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1500 (define_insn "extendsidi2"
1501 [(set (match_operand:DI 0 "register_operand" "=d")
1502 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm")))]
1506 if (TARGET_68020 || TARGET_COLDFIRE)
1507 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
1509 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
1512 (define_insn "*extendsidi2_mem"
1513 [(set (match_operand:DI 0 "memory_operand" "=o,<")
1514 (sign_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm")))
1515 (clobber (match_scratch:SI 2 "=d,d"))]
1519 operands[3] = adjust_address (operands[0], SImode,
1520 which_alternative == 0 ? 4 : 0);
1521 operands[0] = adjust_address (operands[0], SImode, 0);
1522 if (TARGET_68020 || TARGET_COLDFIRE)
1523 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
1525 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
1528 ;; Special case when one can avoid register clobbering, copy and test
1529 ;; Maybe there is a way to make that the general case, by forcing the
1530 ;; result of the SI tree to be in the lower register of the DI target
1532 (define_insn "extendplussidi"
1533 [(set (match_operand:DI 0 "register_operand" "=d")
1534 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1535 (match_operand:SI 2 "general_operand" "rmn"))))]
1539 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1540 if (GET_CODE (operands[1]) == CONST_INT
1541 && (unsigned) INTVAL (operands[1]) > 8)
1543 rtx tmp = operands[1];
1545 operands[1] = operands[2];
1548 if (GET_CODE (operands[1]) == REG
1549 && REGNO (operands[1]) == REGNO (operands[3]))
1550 output_asm_insn ("add%.l %2,%3", operands);
1552 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1553 if (TARGET_68020 || TARGET_COLDFIRE)
1554 return "smi %0\;extb%.l %0";
1556 return "smi %0\;ext%.w %0\;ext%.l %0";
1559 (define_expand "extendhisi2"
1560 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1562 (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1566 (define_insn "*cfv4_extendhisi2"
1567 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1569 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1573 (define_insn "*68k_extendhisi2"
1574 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1576 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1579 if (ADDRESS_REG_P (operands[0]))
1580 return "move%.w %1,%0";
1584 (define_insn "extendqihi2"
1585 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1586 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1590 (define_expand "extendqisi2"
1591 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1592 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1593 "TARGET_68020 || TARGET_COLDFIRE"
1596 (define_insn "*cfv4_extendqisi2"
1597 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1598 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
1602 (define_insn "*68k_extendqisi2"
1603 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1604 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1605 "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)"
1608 ;; Conversions between float and double.
1610 (define_expand "extendsfdf2"
1611 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1613 (match_operand:SF 1 "general_operand" "")))]
1618 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1620 (match_operand:SF 1 "general_operand" "f,dmF")))]
1623 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1625 if (REGNO (operands[0]) == REGNO (operands[1]))
1627 /* Extending float to double in an fp-reg is a no-op.
1628 NOTICE_UPDATE_CC has already assumed that the
1629 cc will be set. So cancel what it did. */
1630 cc_status = cc_prev_status;
1633 return "f%&move%.x %1,%0";
1635 if (FP_REG_P (operands[0]))
1636 return "f%&move%.s %f1,%0";
1637 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1639 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1640 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1641 return "move%.l %+,%0";
1643 return "fmove%.d %f1,%0";
1646 (define_insn "extendsfdf2_cf"
1647 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
1649 (match_operand:SF 1 "general_operand" "f,<Q>U")))]
1650 "TARGET_COLDFIRE_FPU"
1652 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1654 if (REGNO (operands[0]) == REGNO (operands[1]))
1656 /* Extending float to double in an fp-reg is a no-op.
1657 NOTICE_UPDATE_CC has already assumed that the
1658 cc will be set. So cancel what it did. */
1659 cc_status = cc_prev_status;
1662 return "fdmove%.d %1,%0";
1664 return "fdmove%.s %f1,%0";
1667 ;; This cannot output into an f-reg because there is no way to be
1668 ;; sure of truncating in that case.
1669 (define_expand "truncdfsf2"
1670 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1672 (match_operand:DF 1 "general_operand" "")))]
1676 ;; On the '040 we can truncate in a register accurately and easily.
1678 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1680 (match_operand:DF 1 "general_operand" "fmG")))]
1681 "TARGET_68881 && TARGET_68040"
1683 if (FP_REG_P (operands[1]))
1684 return "f%$move%.x %1,%0";
1685 return "f%$move%.d %f1,%0";
1688 (define_insn "truncdfsf2_cf"
1689 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
1691 (match_operand:DF 1 "general_operand" "<Q>U,f")))]
1692 "TARGET_COLDFIRE_FPU"
1698 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1700 (match_operand:DF 1 "general_operand" "f")))]
1704 ;; Conversion between fixed point and floating point.
1705 ;; Note that among the fix-to-float insns
1706 ;; the ones that start with SImode come first.
1707 ;; That is so that an operand that is a CONST_INT
1708 ;; (and therefore lacks a specific machine mode).
1709 ;; will be recognized as SImode (which is always valid)
1710 ;; rather than as QImode or HImode.
1712 (define_expand "floatsi<mode>2"
1713 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1714 (float:FP (match_operand:SI 1 "general_operand" "")))]
1718 (define_insn "floatsi<mode>2_68881"
1719 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1720 (float:FP (match_operand:SI 1 "general_operand" "dmi")))]
1722 "f<FP:round>move%.l %1,%0")
1724 (define_insn "floatsi<mode>2_cf"
1725 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1726 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
1727 "TARGET_COLDFIRE_FPU"
1728 "f<FP:prec>move%.l %1,%0")
1731 (define_expand "floathi<mode>2"
1732 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1733 (float:FP (match_operand:HI 1 "general_operand" "")))]
1737 (define_insn "floathi<mode>2_68881"
1738 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1739 (float:FP (match_operand:HI 1 "general_operand" "dmn")))]
1743 (define_insn "floathi<mode>2_cf"
1744 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1745 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
1746 "TARGET_COLDFIRE_FPU"
1750 (define_expand "floatqi<mode>2"
1751 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1752 (float:FP (match_operand:QI 1 "general_operand" "")))]
1756 (define_insn "floatqi<mode>2_68881"
1757 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1758 (float:FP (match_operand:QI 1 "general_operand" "dmn")))]
1762 (define_insn "floatqi<mode>2_cf"
1763 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1764 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
1765 "TARGET_COLDFIRE_FPU"
1769 ;; New routines to convert floating-point values to integers
1770 ;; to be used on the '040. These should be faster than trapping
1771 ;; into the kernel to emulate fintrz. They should also be faster
1772 ;; than calling the subroutines fixsfsi or fixdfsi.
1774 (define_insn "fix_truncdfsi2"
1775 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1776 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1777 (clobber (match_scratch:SI 2 "=d"))
1778 (clobber (match_scratch:SI 3 "=d"))]
1779 "TARGET_68881 && TUNE_68040"
1782 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
1785 (define_insn "fix_truncdfhi2"
1786 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1787 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1788 (clobber (match_scratch:SI 2 "=d"))
1789 (clobber (match_scratch:SI 3 "=d"))]
1790 "TARGET_68881 && TUNE_68040"
1793 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
1796 (define_insn "fix_truncdfqi2"
1797 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1798 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1799 (clobber (match_scratch:SI 2 "=d"))
1800 (clobber (match_scratch:SI 3 "=d"))]
1801 "TARGET_68881 && TUNE_68040"
1804 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
1807 ;; Convert a float to a float whose value is an integer.
1808 ;; This is the first stage of converting it to an integer type.
1810 (define_expand "ftrunc<mode>2"
1811 [(set (match_operand:FP 0 "nonimmediate_operand" "")
1812 (fix:FP (match_operand:FP 1 "general_operand" "")))]
1813 "TARGET_HARD_FLOAT && !TUNE_68040"
1816 (define_insn "ftrunc<mode>2_68881"
1817 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1818 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
1819 "TARGET_68881 && !TUNE_68040"
1821 if (FP_REG_P (operands[1]))
1822 return "fintrz%.x %f1,%0";
1823 return "fintrz%.<FP:prec> %f1,%0";
1826 (define_insn "ftrunc<mode>2_cf"
1827 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
1828 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
1829 "TARGET_COLDFIRE_FPU"
1831 if (FP_REG_P (operands[1]))
1832 return "fintrz%.d %f1,%0";
1833 return "fintrz%.<FP:prec> %f1,%0";
1836 ;; Convert a float whose value is an integer
1837 ;; to an actual integer. Second stage of converting float to integer type.
1838 (define_expand "fix<mode>qi2"
1839 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1840 (fix:QI (match_operand:FP 1 "general_operand" "")))]
1844 (define_insn "fix<mode>qi2_68881"
1845 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1846 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
1850 (define_insn "fix<mode>qi2_cf"
1851 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
1852 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
1853 "TARGET_COLDFIRE_FPU"
1856 (define_expand "fix<mode>hi2"
1857 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1858 (fix:HI (match_operand:FP 1 "general_operand" "")))]
1862 (define_insn "fix<mode>hi2_68881"
1863 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1864 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
1868 (define_insn "fix<mode>hi2_cf"
1869 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
1870 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
1871 "TARGET_COLDFIRE_FPU"
1874 (define_expand "fix<mode>si2"
1875 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1876 (fix:SI (match_operand:FP 1 "general_operand" "")))]
1880 (define_insn "fix<mode>si2_68881"
1881 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1882 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
1886 (define_insn "fix<mode>si2_cf"
1887 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
1888 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
1889 "TARGET_COLDFIRE_FPU"
1895 (define_insn "adddi_lshrdi_63"
1896 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1897 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1900 (clobber (match_scratch:SI 2 "=d"))]
1903 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1904 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1906 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
1907 if (GET_CODE (operands[1]) == REG)
1908 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1909 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1910 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1911 operands[4] = operands[1];
1913 operands[4] = adjust_address (operands[1], SImode, 4);
1914 if (GET_CODE (operands[1]) == MEM
1915 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1916 output_asm_insn ("move%.l %4,%3", operands);
1917 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
1918 if (TARGET_68020 || TARGET_COLDFIRE)
1919 output_asm_insn ("extb%.l %2", operands);
1921 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
1922 if (GET_CODE (operands[1]) != MEM
1923 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1924 output_asm_insn ("move%.l %4,%3", operands);
1925 return "sub%.l %2,%3\;subx%.l %2,%0";
1928 (define_insn "adddi_sexthishl32"
1929 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1930 (plus:DI (ashift:DI (sign_extend:DI
1931 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1933 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1934 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1938 if (ADDRESS_REG_P (operands[0]))
1939 return "add%.w %1,%0";
1940 else if (ADDRESS_REG_P (operands[3]))
1941 return "move%.w %1,%3\;add%.l %3,%0";
1943 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
1946 (define_insn "*adddi_dilshr32"
1947 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1948 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1950 (match_operand:DI 2 "general_operand" "0,0")))]
1954 if (GET_CODE (operands[0]) == REG)
1955 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1957 operands[2] = adjust_address (operands[0], SImode, 4);
1958 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
1961 (define_insn "*adddi_dilshr32_cf"
1962 [(set (match_operand:DI 0 "register_operand" "=d")
1963 (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
1965 (match_operand:DI 2 "register_operand" "0")))]
1969 return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
1972 (define_insn "adddi_dishl32"
1973 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1974 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1975 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1976 ;; (const_int 32))))]
1977 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1979 (match_operand:DI 2 "general_operand" "0,0")))]
1983 if (GET_CODE (operands[1]) == REG)
1984 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1986 operands[1] = adjust_address (operands[1], SImode, 4);
1987 return "add%.l %1,%0";
1990 (define_insn "adddi3"
1991 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
1992 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
1993 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
1994 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
1997 if (DATA_REG_P (operands[0]))
1999 if (DATA_REG_P (operands[2]))
2000 return "add%.l %R2,%R0\;addx%.l %2,%0";
2001 else if (GET_CODE (operands[2]) == MEM
2002 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2003 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
2009 if (GET_CODE (operands[2]) == REG)
2011 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2014 else if (CONSTANT_P (operands[2]))
2015 split_double (operands[2], &high, &low);
2018 low = adjust_address (operands[2], SImode, 4);
2022 operands[1] = low, operands[2] = high;
2023 xoperands[0] = operands[3];
2024 if (GET_CODE (operands[1]) == CONST_INT
2025 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2026 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2028 xoperands[1] = operands[2];
2030 output_asm_insn (output_move_simode (xoperands), xoperands);
2031 if (GET_CODE (operands[1]) == CONST_INT)
2033 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2034 return "addq%.l %1,%R0\;addx%.l %3,%0";
2035 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2037 operands[1] = GEN_INT (-INTVAL (operands[1]));
2038 return "subq%.l %1,%R0\;subx%.l %3,%0";
2041 return "add%.l %1,%R0\;addx%.l %3,%0";
2046 gcc_assert (GET_CODE (operands[0]) == MEM);
2048 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2050 operands[1] = gen_rtx_MEM (SImode,
2051 plus_constant (XEXP(operands[0], 0), -8));
2052 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2054 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2056 operands[1] = XEXP(operands[0], 0);
2057 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
2061 operands[1] = adjust_address (operands[0], SImode, 4);
2062 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
2067 (define_insn "addsi_lshrsi_31"
2068 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2069 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2074 operands[2] = operands[0];
2075 operands[3] = gen_label_rtx();
2076 if (GET_CODE (operands[0]) == MEM)
2078 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2079 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2080 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2081 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2083 output_asm_insn ("move%.l %1,%0", operands);
2084 output_asm_insn (MOTOROLA ? "jbpl %l3" : "jpl %l3", operands);
2085 output_asm_insn ("addq%.l #1,%2", operands);
2086 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2087 CODE_LABEL_NUMBER (operands[3]));
2091 (define_expand "addsi3"
2092 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2093 (plus:SI (match_operand:SI 1 "general_operand" "")
2094 (match_operand:SI 2 "general_src_operand" "")))]
2098 ;; Note that the middle two alternatives are near-duplicates
2099 ;; in order to handle insns generated by reload.
2100 ;; This is needed since they are not themselves reloaded,
2101 ;; so commutativity won't apply to them.
2102 (define_insn "*addsi3_internal"
2103 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2104 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2105 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2109 "* return output_addsi3 (operands);")
2111 (define_insn "*addsi3_5200"
2112 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2113 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2114 (match_operand:SI 2 "general_src_operand" "dIL,rJK,a,mrIKLi")))]
2116 "* return output_addsi3 (operands);")
2119 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2120 (plus:SI (match_operand:SI 1 "general_operand" "0")
2122 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2126 (define_insn "addhi3"
2127 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2128 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2129 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2132 if (GET_CODE (operands[2]) == CONST_INT)
2134 /* If the constant would be a negative number when interpreted as
2135 HImode, make it negative. This is usually, but not always, done
2136 elsewhere in the compiler. First check for constants out of range,
2137 which could confuse us. */
2139 if (INTVAL (operands[2]) >= 32768)
2140 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2142 if (INTVAL (operands[2]) > 0
2143 && INTVAL (operands[2]) <= 8)
2144 return "addq%.w %2,%0";
2145 if (INTVAL (operands[2]) < 0
2146 && INTVAL (operands[2]) >= -8)
2148 operands[2] = GEN_INT (- INTVAL (operands[2]));
2149 return "subq%.w %2,%0";
2151 /* On the CPU32 it is faster to use two addqw instructions to
2152 add a small integer (8 < N <= 16) to a register.
2153 Likewise for subqw. */
2154 if (TUNE_CPU32 && REG_P (operands[0]))
2156 if (INTVAL (operands[2]) > 8
2157 && INTVAL (operands[2]) <= 16)
2159 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2160 return "addq%.w #8,%0\;addq%.w %2,%0";
2162 if (INTVAL (operands[2]) < -8
2163 && INTVAL (operands[2]) >= -16)
2165 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2166 return "subq%.w #8,%0\;subq%.w %2,%0";
2169 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2170 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2172 return "add%.w %2,%0";
2175 ;; These insns must use MATCH_DUP instead of the more expected
2176 ;; use of a matching constraint because the "output" here is also
2177 ;; an input, so you can't use the matching constraint. That also means
2178 ;; that you can't use the "%", so you need patterns with the matched
2179 ;; operand in both positions.
2182 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2183 (plus:HI (match_dup 0)
2184 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2187 if (GET_CODE (operands[1]) == CONST_INT)
2189 /* If the constant would be a negative number when interpreted as
2190 HImode, make it negative. This is usually, but not always, done
2191 elsewhere in the compiler. First check for constants out of range,
2192 which could confuse us. */
2194 if (INTVAL (operands[1]) >= 32768)
2195 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2197 if (INTVAL (operands[1]) > 0
2198 && INTVAL (operands[1]) <= 8)
2199 return "addq%.w %1,%0";
2200 if (INTVAL (operands[1]) < 0
2201 && INTVAL (operands[1]) >= -8)
2203 operands[1] = GEN_INT (- INTVAL (operands[1]));
2204 return "subq%.w %1,%0";
2206 /* On the CPU32 it is faster to use two addqw instructions to
2207 add a small integer (8 < N <= 16) to a register.
2208 Likewise for subqw. */
2209 if (TUNE_CPU32 && REG_P (operands[0]))
2211 if (INTVAL (operands[1]) > 8
2212 && INTVAL (operands[1]) <= 16)
2214 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2215 return "addq%.w #8,%0\;addq%.w %1,%0";
2217 if (INTVAL (operands[1]) < -8
2218 && INTVAL (operands[1]) >= -16)
2220 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2221 return "subq%.w #8,%0\;subq%.w %1,%0";
2224 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2225 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2227 return "add%.w %1,%0";
2231 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2232 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2236 if (GET_CODE (operands[1]) == CONST_INT)
2238 /* If the constant would be a negative number when interpreted as
2239 HImode, make it negative. This is usually, but not always, done
2240 elsewhere in the compiler. First check for constants out of range,
2241 which could confuse us. */
2243 if (INTVAL (operands[1]) >= 32768)
2244 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2246 if (INTVAL (operands[1]) > 0
2247 && INTVAL (operands[1]) <= 8)
2248 return "addq%.w %1,%0";
2249 if (INTVAL (operands[1]) < 0
2250 && INTVAL (operands[1]) >= -8)
2252 operands[1] = GEN_INT (- INTVAL (operands[1]));
2253 return "subq%.w %1,%0";
2255 /* On the CPU32 it is faster to use two addqw instructions to
2256 add a small integer (8 < N <= 16) to a register.
2257 Likewise for subqw. */
2258 if (TUNE_CPU32 && REG_P (operands[0]))
2260 if (INTVAL (operands[1]) > 8
2261 && INTVAL (operands[1]) <= 16)
2263 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2264 return "addq%.w #8,%0\;addq%.w %1,%0";
2266 if (INTVAL (operands[1]) < -8
2267 && INTVAL (operands[1]) >= -16)
2269 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2270 return "subq%.w #8,%0\;subq%.w %1,%0";
2273 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2274 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2276 return "add%.w %1,%0";
2279 (define_insn "addqi3"
2280 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2281 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2282 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2285 if (GET_CODE (operands[2]) == CONST_INT)
2287 if (INTVAL (operands[2]) >= 128)
2288 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2290 if (INTVAL (operands[2]) > 0
2291 && INTVAL (operands[2]) <= 8)
2292 return "addq%.b %2,%0";
2293 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2295 operands[2] = GEN_INT (- INTVAL (operands[2]));
2296 return "subq%.b %2,%0";
2299 return "add%.b %2,%0";
2303 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2304 (plus:QI (match_dup 0)
2305 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2308 if (GET_CODE (operands[1]) == CONST_INT)
2310 if (INTVAL (operands[1]) >= 128)
2311 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2313 if (INTVAL (operands[1]) > 0
2314 && INTVAL (operands[1]) <= 8)
2315 return "addq%.b %1,%0";
2316 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2318 operands[1] = GEN_INT (- INTVAL (operands[1]));
2319 return "subq%.b %1,%0";
2322 return "add%.b %1,%0";
2326 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2327 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2331 if (GET_CODE (operands[1]) == CONST_INT)
2333 if (INTVAL (operands[1]) >= 128)
2334 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2336 if (INTVAL (operands[1]) > 0
2337 && INTVAL (operands[1]) <= 8)
2338 return "addq%.b %1,%0";
2339 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2341 operands[1] = GEN_INT (- INTVAL (operands[1]));
2342 return "subq%.b %1,%0";
2345 return "add%.b %1,%0";
2348 (define_expand "add<mode>3"
2349 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2350 (plus:FP (match_operand:FP 1 "general_operand" "")
2351 (match_operand:FP 2 "general_operand" "")))]
2355 (define_insn "add<mode>3_floatsi_68881"
2356 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2357 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2358 (match_operand:FP 1 "general_operand" "0")))]
2360 "f<FP:round>add%.l %2,%0")
2362 (define_insn "add<mode>3_floathi_68881"
2363 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2364 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2365 (match_operand:FP 1 "general_operand" "0")))]
2367 "f<FP:round>add%.w %2,%0")
2369 (define_insn "add<mode>3_floatqi_68881"
2370 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2371 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2372 (match_operand:FP 1 "general_operand" "0")))]
2374 "f<FP:round>add%.b %2,%0")
2376 (define_insn "add<mode>3_68881"
2377 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2378 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2379 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2382 if (FP_REG_P (operands[2]))
2383 return "f<FP:round>add%.x %2,%0";
2384 return "f<FP:round>add%.<FP:prec> %f2,%0";
2387 (define_insn "add<mode>3_cf"
2388 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2389 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2390 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2391 "TARGET_COLDFIRE_FPU"
2393 if (FP_REG_P (operands[2]))
2394 return "f<FP:prec>add%.d %2,%0";
2395 return "f<FP:prec>add%.<FP:prec> %2,%0";
2398 ;; subtract instructions
2400 (define_insn "subdi_sexthishl32"
2401 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2402 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2403 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2405 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2409 if (ADDRESS_REG_P (operands[0]))
2410 return "sub%.w %2,%0";
2411 else if (ADDRESS_REG_P (operands[3]))
2412 return "move%.w %2,%3\;sub%.l %3,%0";
2414 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2417 (define_insn "subdi_dishl32"
2418 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2419 (minus:DI (match_dup 0)
2420 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2425 if (GET_CODE (operands[1]) == REG)
2426 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2428 operands[1] = adjust_address (operands[1], SImode, 4);
2429 return "sub%.l %1,%0";
2432 (define_insn "subdi3"
2433 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2434 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2435 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2436 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2439 if (DATA_REG_P (operands[0]))
2441 if (DATA_REG_P (operands[2]))
2442 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2443 else if (GET_CODE (operands[2]) == MEM
2444 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2446 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2453 if (GET_CODE (operands[2]) == REG)
2455 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2458 else if (CONSTANT_P (operands[2]))
2459 split_double (operands[2], &high, &low);
2462 low = adjust_address (operands[2], SImode, 4);
2466 operands[1] = low, operands[2] = high;
2467 xoperands[0] = operands[3];
2468 if (GET_CODE (operands[1]) == CONST_INT
2469 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2470 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2472 xoperands[1] = operands[2];
2474 output_asm_insn (output_move_simode (xoperands), xoperands);
2475 if (GET_CODE (operands[1]) == CONST_INT)
2477 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2478 return "subq%.l %1,%R0\;subx%.l %3,%0";
2479 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2481 operands[1] = GEN_INT (-INTVAL (operands[1]));
2482 return "addq%.l %1,%R0\;addx%.l %3,%0";
2485 return "sub%.l %1,%R0\;subx%.l %3,%0";
2490 gcc_assert (GET_CODE (operands[0]) == MEM);
2492 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2495 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2496 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2498 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2500 operands[1] = XEXP(operands[0], 0);
2501 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2505 operands[1] = adjust_address (operands[0], SImode, 4);
2506 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2511 (define_insn "subsi3"
2512 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2513 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2514 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2519 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2520 (minus:SI (match_operand:SI 1 "general_operand" "0")
2522 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2526 (define_insn "subhi3"
2527 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2528 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2529 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2534 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2535 (minus:HI (match_dup 0)
2536 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2540 (define_insn "subqi3"
2541 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2542 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2543 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2548 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2549 (minus:QI (match_dup 0)
2550 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2554 (define_expand "sub<mode>3"
2555 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2556 (minus:FP (match_operand:FP 1 "general_operand" "")
2557 (match_operand:FP 2 "general_operand" "")))]
2561 (define_insn "sub<mode>3_floatsi_68881"
2562 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2563 (minus:FP (match_operand:FP 1 "general_operand" "0")
2564 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2566 "f<FP:round>sub%.l %2,%0")
2568 (define_insn "sub<mode>3_floathi_68881"
2569 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2570 (minus:FP (match_operand:FP 1 "general_operand" "0")
2571 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2573 "f<FP:round>sub%.w %2,%0")
2575 (define_insn "sub<mode>3_floatqi_68881"
2576 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2577 (minus:FP (match_operand:FP 1 "general_operand" "0")
2578 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2580 "f<FP:round>sub%.b %2,%0")
2582 (define_insn "sub<mode>3_68881"
2583 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2584 (minus:FP (match_operand:FP 1 "general_operand" "0")
2585 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2588 if (FP_REG_P (operands[2]))
2589 return "f<FP:round>sub%.x %2,%0";
2590 return "f<FP:round>sub%.<FP:prec> %f2,%0";
2593 (define_insn "sub<mode>3_cf"
2594 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2595 (minus:FP (match_operand:FP 1 "general_operand" "0")
2596 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2597 "TARGET_COLDFIRE_FPU"
2599 if (FP_REG_P (operands[2]))
2600 return "f<FP:prec>sub%.d %2,%0";
2601 return "f<FP:prec>sub%.<FP:prec> %2,%0";
2604 ;; multiply instructions
2606 (define_insn "mulhi3"
2607 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2608 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2609 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2612 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2615 (define_insn "mulhisi3"
2616 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2617 (mult:SI (sign_extend:SI
2618 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2620 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2623 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2627 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2628 (mult:SI (sign_extend:SI
2629 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2630 (match_operand:SI 2 "const_int_operand" "n")))]
2631 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2633 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2636 (define_expand "mulsi3"
2637 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2638 (mult:SI (match_operand:SI 1 "general_operand" "")
2639 (match_operand:SI 2 "general_operand" "")))]
2640 "TARGET_68020 || TARGET_COLDFIRE"
2644 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2645 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2646 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2652 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2653 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2654 (match_operand:SI 2 "general_operand" "d<Q>")))]
2658 (define_insn "umulhisi3"
2659 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2660 (mult:SI (zero_extend:SI
2661 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2663 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2666 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2670 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2671 (mult:SI (zero_extend:SI
2672 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2673 (match_operand:SI 2 "const_int_operand" "n")))]
2674 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2676 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2679 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2680 ;; proper matching constraint. This is because the matching is between
2681 ;; the high-numbered word of the DImode operand[0] and operand[1].
2682 (define_expand "umulsidi3"
2684 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2685 (mult:SI (match_operand:SI 1 "register_operand" "")
2686 (match_operand:SI 2 "register_operand" "")))
2687 (set (subreg:SI (match_dup 0) 0)
2688 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2689 (zero_extend:DI (match_dup 2)))
2690 (const_int 32))))])]
2691 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2695 [(set (match_operand:SI 0 "register_operand" "=d")
2696 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2697 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2698 (set (match_operand:SI 3 "register_operand" "=d")
2699 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2700 (zero_extend:DI (match_dup 2)))
2702 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2705 ; Match immediate case. For 2.4 only match things < 2^31.
2706 ; It's tricky with larger values in these patterns since we need to match
2707 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2710 [(set (match_operand:SI 0 "register_operand" "=d")
2711 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2712 (match_operand:SI 2 "const_int_operand" "n")))
2713 (set (match_operand:SI 3 "register_operand" "=d")
2714 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2717 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE
2718 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2721 (define_expand "mulsidi3"
2723 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2724 (mult:SI (match_operand:SI 1 "register_operand" "")
2725 (match_operand:SI 2 "register_operand" "")))
2726 (set (subreg:SI (match_dup 0) 0)
2727 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2728 (sign_extend:DI (match_dup 2)))
2729 (const_int 32))))])]
2730 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2734 [(set (match_operand:SI 0 "register_operand" "=d")
2735 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2736 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2737 (set (match_operand:SI 3 "register_operand" "=d")
2738 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2739 (sign_extend:DI (match_dup 2)))
2741 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2745 [(set (match_operand:SI 0 "register_operand" "=d")
2746 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2747 (match_operand:SI 2 "const_int_operand" "n")))
2748 (set (match_operand:SI 3 "register_operand" "=d")
2749 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2752 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2755 (define_expand "umulsi3_highpart"
2757 [(set (match_operand:SI 0 "register_operand" "")
2760 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2761 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2763 (clobber (match_dup 3))])]
2764 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2766 operands[3] = gen_reg_rtx (SImode);
2768 if (GET_CODE (operands[2]) == CONST_INT)
2770 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2773 /* We have to adjust the operand order for the matching constraints. */
2774 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2775 operands[1], operands[2]));
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2784 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2785 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2787 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2788 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2791 (define_insn "const_umulsi3_highpart"
2792 [(set (match_operand:SI 0 "register_operand" "=d")
2795 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2796 (match_operand:DI 3 "const_uint32_operand" "n"))
2798 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2799 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2802 (define_expand "smulsi3_highpart"
2804 [(set (match_operand:SI 0 "register_operand" "")
2807 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2808 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2810 (clobber (match_dup 3))])]
2811 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2813 operands[3] = gen_reg_rtx (SImode);
2814 if (GET_CODE (operands[2]) == CONST_INT)
2816 /* We have to adjust the operand order for the matching constraints. */
2817 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2818 operands[1], operands[2]));
2824 [(set (match_operand:SI 0 "register_operand" "=d")
2827 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2828 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2830 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2831 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2834 (define_insn "const_smulsi3_highpart"
2835 [(set (match_operand:SI 0 "register_operand" "=d")
2838 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2839 (match_operand:DI 3 "const_sint32_operand" "n"))
2841 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2842 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
2845 (define_expand "mul<mode>3"
2846 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2847 (mult:FP (match_operand:FP 1 "general_operand" "")
2848 (match_operand:FP 2 "general_operand" "")))]
2852 (define_insn "mul<mode>3_floatsi_68881"
2853 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2854 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2855 (match_operand:FP 1 "general_operand" "0")))]
2859 ? "f<FP:round>mul%.l %2,%0"
2860 : "f<FP:round_mul>mul%.l %2,%0";
2863 (define_insn "mul<mode>3_floathi_68881"
2864 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2865 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2866 (match_operand:FP 1 "general_operand" "0")))]
2870 ? "f<FP:round>mul%.w %2,%0"
2871 : "f<FP:round_mul>mul%.w %2,%0";
2874 (define_insn "mul<mode>3_floatqi_68881"
2875 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2876 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2877 (match_operand:FP 1 "general_operand" "0")))]
2881 ? "f<FP:round>mul%.b %2,%0"
2882 : "f<FP:round_mul>mul%.b %2,%0";
2885 (define_insn "muldf_68881"
2886 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2887 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2888 (match_operand:DF 2 "general_operand" "fmG")))]
2891 if (GET_CODE (operands[2]) == CONST_DOUBLE
2892 && floating_exact_log2 (operands[2]) && !TUNE_68040_60)
2894 int i = floating_exact_log2 (operands[2]);
2895 operands[2] = GEN_INT (i);
2896 return "fscale%.l %2,%0";
2898 if (REG_P (operands[2]))
2899 return "f%&mul%.x %2,%0";
2900 return "f%&mul%.d %f2,%0";
2903 (define_insn "mulsf_68881"
2904 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2905 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2906 (match_operand:SF 2 "general_operand" "fdmF")))]
2909 if (FP_REG_P (operands[2]))
2910 return (TARGET_68040
2912 : "fsglmul%.x %2,%0");
2913 return (TARGET_68040
2915 : "fsglmul%.s %f2,%0");
2918 (define_insn "mulxf3_68881"
2919 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
2920 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
2921 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
2924 return "fmul%.x %f2,%0";
2927 (define_insn "fmul<mode>3_cf"
2928 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2929 (mult:FP (match_operand:FP 1 "general_operand" "%0")
2930 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
2931 "TARGET_COLDFIRE_FPU"
2933 if (FP_REG_P (operands[2]))
2934 return "f<FP:prec>mul%.d %2,%0";
2935 return "f<FP:prec>mul%.<FP:prec> %2,%0";
2938 ;; divide instructions
2940 (define_expand "div<mode>3"
2941 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2942 (div:FP (match_operand:FP 1 "general_operand" "")
2943 (match_operand:FP 2 "general_operand" "")))]
2947 (define_insn "div<mode>3_floatsi_68881"
2948 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2949 (div:FP (match_operand:FP 1 "general_operand" "0")
2950 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2954 ? "f<FP:round>div%.l %2,%0"
2955 : "f<FP:round_mul>div%.l %2,%0";
2958 (define_insn "div<mode>3_floathi_68881"
2959 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2960 (div:FP (match_operand:FP 1 "general_operand" "0")
2961 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2965 ? "f<FP:round>div%.w %2,%0"
2966 : "f<FP:round_mul>div%.w %2,%0";
2969 (define_insn "div<mode>3_floatqi_68881"
2970 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2971 (div:FP (match_operand:FP 1 "general_operand" "0")
2972 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
2976 ? "f<FP:round>div%.b %2,%0"
2977 : "f<FP:round_mul>div%.b %2,%0";
2980 (define_insn "div<mode>3_68881"
2981 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2982 (div:FP (match_operand:FP 1 "general_operand" "0")
2983 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2986 if (FP_REG_P (operands[2]))
2987 return (TARGET_68040
2988 ? "f<FP:round>div%.x %2,%0"
2989 : "f<FP:round_mul>div%.x %2,%0");
2990 return (TARGET_68040
2991 ? "f<FP:round>div%.<FP:prec> %f2,%0"
2992 : "f<FP:round_mul>div%.<FP:prec> %f2,%0");
2995 (define_insn "div<mode>3_cf"
2996 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2997 (div:FP (match_operand:FP 1 "general_operand" "0")
2998 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
2999 "TARGET_COLDFIRE_FPU"
3001 if (FP_REG_P (operands[2]))
3002 return "f<FP:prec>div%.d %2,%0";
3003 return "f<FP:prec>div%.<FP:prec> %2,%0";
3006 ;; Remainder instructions.
3008 (define_expand "divmodsi4"
3010 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3011 (div:SI (match_operand:SI 1 "general_operand" "")
3012 (match_operand:SI 2 "general_src_operand" "")))
3013 (set (match_operand:SI 3 "nonimmediate_operand" "")
3014 (mod:SI (match_dup 1) (match_dup 2)))])]
3015 "TARGET_68020 || TARGET_CF_HWDIV"
3019 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3020 (div:SI (match_operand:SI 1 "general_operand" "0")
3021 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3022 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3023 (mod:SI (match_dup 1) (match_dup 2)))]
3026 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3027 return "divs%.l %2,%0";
3028 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3029 return "rems%.l %2,%3:%0";
3031 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3035 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3036 (div:SI (match_operand:SI 1 "general_operand" "0")
3037 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3038 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3039 (mod:SI (match_dup 1) (match_dup 2)))]
3042 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3043 return "divs%.l %2,%0";
3045 return "divsl%.l %2,%3:%0";
3048 (define_expand "udivmodsi4"
3050 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3051 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3052 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3053 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3054 (umod:SI (match_dup 1) (match_dup 2)))])]
3055 "TARGET_68020 || TARGET_CF_HWDIV"
3059 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3060 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3061 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3062 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3063 (umod:SI (match_dup 1) (match_dup 2)))]
3066 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3067 return "divu%.l %2,%0";
3068 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3069 return "remu%.l %2,%3:%0";
3071 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3075 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3076 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3077 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3078 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3079 (umod:SI (match_dup 1) (match_dup 2)))]
3080 "TARGET_68020 && !TARGET_COLDFIRE"
3082 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3083 return "divu%.l %2,%0";
3085 return "divul%.l %2,%3:%0";
3088 (define_insn "divmodhi4"
3089 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3090 (div:HI (match_operand:HI 1 "general_operand" "0")
3091 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3092 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3093 (mod:HI (match_dup 1) (match_dup 2)))]
3094 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3096 output_asm_insn (MOTOROLA ?
3097 "ext%.l %0\;divs%.w %2,%0" :
3098 "extl %0\;divs %2,%0",
3100 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3103 return "move%.l %0,%3\;swap %3";
3109 (define_insn "udivmodhi4"
3110 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3111 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3112 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3113 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3114 (umod:HI (match_dup 1) (match_dup 2)))]
3115 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3118 output_asm_insn (MOTOROLA ?
3119 "mvz%.w %0,%0\;divu%.w %2,%0" :
3120 "mvz%.w %0,%0\;divu %2,%0",
3123 output_asm_insn (MOTOROLA ?
3124 "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
3125 "and%.l #0xFFFF,%0\;divu %2,%0",
3128 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3131 return "move%.l %0,%3\;swap %3";
3137 ;; logical-and instructions
3139 ;; "anddi3" is mainly here to help combine().
3140 (define_insn "anddi3"
3141 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3142 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3143 (match_operand:DI 2 "general_operand" "dn,don")))]
3147 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3148 if (CONSTANT_P (operands[2]))
3152 split_double (operands[2], &hi, &lo);
3154 switch (INTVAL (hi))
3157 output_asm_insn ("clr%.l %0", operands);
3165 xoperands[0] = operands[0];
3167 output_asm_insn (output_andsi3 (xoperands), xoperands);
3170 if (GET_CODE (operands[0]) == REG)
3171 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3173 operands[0] = adjust_address (operands[0], SImode, 4);
3174 switch (INTVAL (lo))
3177 output_asm_insn ("clr%.l %0", operands);
3185 xoperands[0] = operands[0];
3187 output_asm_insn (output_andsi3 (xoperands), xoperands);
3192 if (GET_CODE (operands[0]) != REG)
3194 operands[1] = adjust_address (operands[0], SImode, 4);
3195 return "and%.l %2,%0\;and%.l %R2,%1";
3197 if (GET_CODE (operands[2]) != REG)
3199 operands[1] = adjust_address (operands[2], SImode, 4);
3200 return "and%.l %2,%0\;and%.l %1,%R0";
3202 return "and%.l %2,%0\;and%.l %R2,%R0";
3205 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3206 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3207 ;; can't allocate pseudos into it.
3209 (define_expand "andsi3"
3210 [(set (match_operand:SI 0 "not_sp_operand" "")
3211 (and:SI (match_operand:SI 1 "general_operand" "")
3212 (match_operand:SI 2 "general_src_operand" "")))]
3216 ;; produced by split operations after reload finished
3217 (define_insn "*andsi3_split"
3218 [(set (match_operand:SI 0 "register_operand" "=d")
3219 (and:SI (match_operand:SI 1 "register_operand" "0")
3220 (match_operand:SI 2 "const_int_operand" "i")))]
3221 "reload_completed && !TARGET_COLDFIRE"
3223 return output_andsi3 (operands);
3226 (define_insn "andsi3_internal"
3227 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3228 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3229 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3232 return output_andsi3 (operands);
3235 (define_insn "andsi3_5200"
3236 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3237 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3238 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3242 && DATA_REG_P (operands[0])
3243 && GET_CODE (operands[2]) == CONST_INT)
3245 if (INTVAL (operands[2]) == 0x000000ff)
3246 return "mvz%.b %0,%0";
3247 else if (INTVAL (operands[2]) == 0x0000ffff)
3248 return "mvz%.w %0,%0";
3250 return output_andsi3 (operands);
3253 (define_insn "andhi3"
3254 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3255 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3256 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3261 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3262 (and:HI (match_dup 0)
3263 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3268 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3269 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3274 (define_insn "andqi3"
3275 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3276 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3277 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3282 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3283 (and:QI (match_dup 0)
3284 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3289 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3290 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3295 ;; inclusive-or instructions
3297 (define_insn "iordi_zext"
3298 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3299 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3300 (match_operand:DI 2 "general_operand" "0,0")))]
3306 if (GET_CODE (operands[0]) == REG)
3307 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3309 operands[0] = adjust_address (operands[0], SImode, 4);
3310 if (GET_MODE (operands[1]) == SImode)
3311 return "or%.l %1,%0";
3312 byte_mode = (GET_MODE (operands[1]) == QImode);
3313 if (GET_CODE (operands[0]) == MEM)
3314 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3317 return "or%.b %1,%0";
3319 return "or%.w %1,%0";
3322 ;; "iordi3" is mainly here to help combine().
3323 (define_insn "iordi3"
3324 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3325 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3326 (match_operand:DI 2 "general_operand" "dn,don")))]
3330 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3331 if (CONSTANT_P (operands[2]))
3335 split_double (operands[2], &hi, &lo);
3337 switch (INTVAL (hi))
3342 /* FIXME : a scratch register would be welcome here if operand[0]
3343 is not a register */
3344 output_asm_insn ("move%.l #-1,%0", operands);
3350 xoperands[0] = operands[0];
3352 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3355 if (GET_CODE (operands[0]) == REG)
3356 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3358 operands[0] = adjust_address (operands[0], SImode, 4);
3359 switch (INTVAL (lo))
3364 /* FIXME : a scratch register would be welcome here if operand[0]
3365 is not a register */
3366 output_asm_insn ("move%.l #-1,%0", operands);
3372 xoperands[0] = operands[0];
3374 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3379 if (GET_CODE (operands[0]) != REG)
3381 operands[1] = adjust_address (operands[0], SImode, 4);
3382 return "or%.l %2,%0\;or%.l %R2,%1";
3384 if (GET_CODE (operands[2]) != REG)
3386 operands[1] = adjust_address (operands[2], SImode, 4);
3387 return "or%.l %2,%0\;or%.l %1,%R0";
3389 return "or%.l %2,%0\;or%.l %R2,%R0";
3392 (define_expand "iorsi3"
3393 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3394 (ior:SI (match_operand:SI 1 "general_operand" "")
3395 (match_operand:SI 2 "general_src_operand" "")))]
3399 (define_insn "iorsi3_internal"
3400 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3401 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3402 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3405 return output_iorsi3 (operands);
3408 (define_insn "iorsi3_5200"
3409 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3410 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3411 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3414 return output_iorsi3 (operands);
3417 (define_insn "iorhi3"
3418 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3419 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3420 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3425 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3426 (ior:HI (match_dup 0)
3427 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3432 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3433 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3438 (define_insn "iorqi3"
3439 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3440 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3441 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3446 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3447 (ior:QI (match_dup 0)
3448 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3453 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3454 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3459 ;; On all 68k models, this makes faster code in a special case.
3460 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3462 (define_insn "iorsi_zexthi_ashl16"
3463 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3464 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3465 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3470 if (GET_CODE (operands[2]) != REG)
3471 operands[2] = adjust_address (operands[2], HImode, 2);
3472 if (GET_CODE (operands[2]) != REG
3473 || REGNO (operands[2]) != REGNO (operands[0]))
3474 output_asm_insn ("move%.w %2,%0", operands);
3475 return "swap %0\;mov%.w %1,%0";
3478 (define_insn "iorsi_zext"
3479 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3480 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3481 (match_operand:SI 2 "general_operand" "0,0")))]
3487 byte_mode = (GET_MODE (operands[1]) == QImode);
3488 if (GET_CODE (operands[0]) == MEM)
3489 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3492 return "or%.b %1,%0";
3494 return "or%.w %1,%0";
3499 ;; "xordi3" is mainly here to help combine().
3500 (define_insn "xordi3"
3501 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3502 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3503 (match_operand:DI 2 "general_operand" "dn")))]
3507 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3509 if (CONSTANT_P (operands[2]))
3513 split_double (operands[2], &hi, &lo);
3515 switch (INTVAL (hi))
3520 output_asm_insn ("not%.l %0", operands);
3523 /* FIXME : a scratch register would be welcome here if
3524 -128 <= INTVAL (hi) < -1 */
3528 xoperands[0] = operands[0];
3530 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3533 if (GET_CODE (operands[0]) == REG)
3534 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3536 operands[0] = adjust_address (operands[0], SImode, 4);
3537 switch (INTVAL (lo))
3542 output_asm_insn ("not%.l %0", operands);
3545 /* FIXME : a scratch register would be welcome here if
3546 -128 <= INTVAL (lo) < -1 */
3548 /* FIXME : this should be merged with xorsi3 */
3552 xoperands[0] = operands[0];
3554 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3559 if (GET_CODE (operands[0]) != REG)
3561 operands[1] = adjust_address (operands[0], SImode, 4);
3562 return "eor%.l %2,%0\;eor%.l %R2,%1";
3564 if (GET_CODE (operands[2]) != REG)
3566 operands[1] = adjust_address (operands[2], SImode, 4);
3567 return "eor%.l %2,%0\;eor%.l %1,%R0";
3569 return "eor%.l %2,%0\;eor%.l %R2,%R0";
3572 (define_expand "xorsi3"
3573 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3574 (xor:SI (match_operand:SI 1 "general_operand" "")
3575 (match_operand:SI 2 "general_operand" "")))]
3579 (define_insn "xorsi3_internal"
3580 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3581 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3582 (match_operand:SI 2 "general_operand" "di,dKT")))]
3586 return output_xorsi3 (operands);
3589 (define_insn "xorsi3_5200"
3590 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3591 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3592 (match_operand:SI 2 "general_operand" "d,Ks")))]
3595 return output_xorsi3 (operands);
3598 (define_insn "xorhi3"
3599 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3600 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3601 (match_operand:HI 2 "general_operand" "dn")))]
3606 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3607 (xor:HI (match_dup 0)
3608 (match_operand:HI 1 "general_operand" "dn")))]
3613 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3614 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3619 (define_insn "xorqi3"
3620 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3621 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3622 (match_operand:QI 2 "general_operand" "dn")))]
3627 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3628 (xor:QI (match_dup 0)
3629 (match_operand:QI 1 "general_operand" "dn")))]
3634 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3635 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3640 ;; negation instructions
3642 (define_expand "negdi2"
3643 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3644 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3647 if (TARGET_COLDFIRE)
3648 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3650 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3654 (define_insn "negdi2_internal"
3655 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3656 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3659 if (which_alternative == 0)
3660 return "neg%.l %0\;negx%.l %0";
3661 if (GET_CODE (operands[0]) == REG)
3662 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3664 operands[1] = adjust_address (operands[0], SImode, 4);
3665 if (ADDRESS_REG_P (operands[0]))
3666 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
3668 return "neg%.l %1\;negx%.l %0";
3671 (define_insn "negdi2_5200"
3672 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3673 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3676 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3677 return "neg%.l %1\;negx%.l %0";
3680 (define_expand "negsi2"
3681 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3682 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3685 if (TARGET_COLDFIRE)
3686 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3688 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3692 (define_insn "negsi2_internal"
3693 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3694 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3698 (define_insn "negsi2_5200"
3699 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3700 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3704 (define_insn "neghi2"
3705 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3706 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3711 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3712 (neg:HI (match_dup 0)))]
3716 (define_insn "negqi2"
3717 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3718 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3723 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3724 (neg:QI (match_dup 0)))]
3728 ;; If using software floating point, just flip the sign bit.
3730 (define_expand "negsf2"
3731 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3732 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3735 if (!TARGET_HARD_FLOAT)
3740 target = operand_subword_force (operands[0], 0, SFmode);
3741 result = expand_binop (SImode, xor_optab,
3742 operand_subword_force (operands[1], 0, SFmode),
3743 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3744 gcc_assert (result);
3746 if (result != target)
3747 emit_move_insn (result, target);
3749 /* Make a place for REG_EQUAL. */
3750 emit_move_insn (operands[0], operands[0]);
3755 (define_expand "negdf2"
3756 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3757 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3760 if (!TARGET_HARD_FLOAT)
3767 target = operand_subword (operands[0], 0, 1, DFmode);
3768 result = expand_binop (SImode, xor_optab,
3769 operand_subword_force (operands[1], 0, DFmode),
3770 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3771 gcc_assert (result);
3773 if (result != target)
3774 emit_move_insn (result, target);
3776 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3777 operand_subword_force (operands[1], 1, DFmode));
3779 insns = get_insns ();
3782 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3787 (define_expand "negxf2"
3788 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3789 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
3799 target = operand_subword (operands[0], 0, 1, XFmode);
3800 result = expand_binop (SImode, xor_optab,
3801 operand_subword_force (operands[1], 0, XFmode),
3802 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
3803 gcc_assert (result);
3805 if (result != target)
3806 emit_move_insn (result, target);
3808 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
3809 operand_subword_force (operands[1], 1, XFmode));
3810 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
3811 operand_subword_force (operands[1], 2, XFmode));
3813 insns = get_insns ();
3816 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3821 (define_insn "neg<mode>2_68881"
3822 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3823 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
3826 if (DATA_REG_P (operands[0]))
3828 operands[1] = GEN_INT (31);
3829 return "bchg %1,%0";
3831 if (FP_REG_P (operands[1]))
3832 return "f<FP:round>neg%.x %1,%0";
3833 return "f<FP:round>neg%.<FP:prec> %f1,%0";
3836 (define_insn "neg<mode>2_cf"
3837 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3838 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
3839 "TARGET_COLDFIRE_FPU"
3841 if (DATA_REG_P (operands[0]))
3843 operands[1] = GEN_INT (31);
3844 return "bchg %1,%0";
3846 if (FP_REG_P (operands[1]))
3847 return "f<FP:prec>neg%.d %1,%0";
3848 return "f<FP:prec>neg%.<FP:prec> %1,%0";
3851 ;; Sqrt instruction for the 68881
3853 (define_expand "sqrt<mode>2"
3854 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3855 (sqrt:FP (match_operand:FP 1 "general_operand" "")))]
3859 (define_insn "sqrt<mode>2_68881"
3860 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3861 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
3864 if (FP_REG_P (operands[1]))
3865 return "f<FP:round>sqrt%.x %1,%0";
3866 return "f<FP:round>sqrt%.<FP:prec> %1,%0";
3869 (define_insn "sqrt<mode>2_cf"
3870 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3871 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
3872 "TARGET_COLDFIRE_FPU"
3874 if (FP_REG_P (operands[1]))
3875 return "f<FP:prec>sqrt%.d %1,%0";
3876 return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
3878 ;; Absolute value instructions
3879 ;; If using software floating point, just zero the sign bit.
3881 (define_expand "abssf2"
3882 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3883 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3886 if (!TARGET_HARD_FLOAT)
3891 target = operand_subword_force (operands[0], 0, SFmode);
3892 result = expand_binop (SImode, and_optab,
3893 operand_subword_force (operands[1], 0, SFmode),
3894 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3895 gcc_assert (result);
3897 if (result != target)
3898 emit_move_insn (result, target);
3900 /* Make a place for REG_EQUAL. */
3901 emit_move_insn (operands[0], operands[0]);
3906 (define_expand "absdf2"
3907 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3908 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3911 if (!TARGET_HARD_FLOAT)
3918 target = operand_subword (operands[0], 0, 1, DFmode);
3919 result = expand_binop (SImode, and_optab,
3920 operand_subword_force (operands[1], 0, DFmode),
3921 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3922 gcc_assert (result);
3924 if (result != target)
3925 emit_move_insn (result, target);
3927 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3928 operand_subword_force (operands[1], 1, DFmode));
3930 insns = get_insns ();
3933 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3938 (define_expand "absxf2"
3939 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3940 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
3950 target = operand_subword (operands[0], 0, 1, XFmode);
3951 result = expand_binop (SImode, and_optab,
3952 operand_subword_force (operands[1], 0, XFmode),
3953 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3954 gcc_assert (result);
3956 if (result != target)
3957 emit_move_insn (result, target);
3959 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
3960 operand_subword_force (operands[1], 1, XFmode));
3961 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
3962 operand_subword_force (operands[1], 2, XFmode));
3964 insns = get_insns ();
3967 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3972 (define_insn "abs<mode>2_68881"
3973 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3974 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
3977 if (DATA_REG_P (operands[0]))
3979 operands[1] = GEN_INT (31);
3980 return "bclr %1,%0";
3982 if (FP_REG_P (operands[1]))
3983 return "f<FP:round>abs%.x %1,%0";
3984 return "f<FP:round>abs%.<FP:prec> %f1,%0";
3987 (define_insn "abs<mode>2_cf"
3988 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
3989 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
3990 "TARGET_COLDFIRE_FPU"
3992 if (DATA_REG_P (operands[0]))
3994 operands[1] = GEN_INT (31);
3995 return "bclr %1,%0";
3997 if (FP_REG_P (operands[1]))
3998 return "f<FP:prec>abs%.d %1,%0";
3999 return "f<FP:prec>abs%.<FP:prec> %1,%0";
4002 ;; bit indexing instructions
4004 ;; ColdFire ff1 instruction implements clz.
4005 (define_insn "clzsi2"
4006 [(set (match_operand:SI 0 "register_operand" "=d")
4007 (clz:SI (match_operand:SI 1 "register_operand" "0")))]
4008 "TARGET_ISAAPLUS || TARGET_ISAC"
4011 ;; one complement instructions
4013 ;; "one_cmpldi2" is mainly here to help combine().
4014 (define_insn "one_cmpldi2"
4015 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4016 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4020 if (GET_CODE (operands[0]) == REG)
4021 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4022 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4023 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4024 operands[1] = operands[0];
4026 operands[1] = adjust_address (operands[0], SImode, 4);
4027 return "not%.l %1\;not%.l %0";
4030 (define_expand "one_cmplsi2"
4031 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4032 (not:SI (match_operand:SI 1 "general_operand" "")))]
4035 if (TARGET_COLDFIRE)
4036 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4038 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4042 (define_insn "one_cmplsi2_internal"
4043 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4044 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4048 (define_insn "one_cmplsi2_5200"
4049 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4050 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4054 (define_insn "one_cmplhi2"
4055 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4056 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4061 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4062 (not:HI (match_dup 0)))]
4066 (define_insn "one_cmplqi2"
4067 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4068 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4073 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4074 (not:QI (match_dup 0)))]
4078 ;; arithmetic shift instructions
4079 ;; We don't need the shift memory by 1 bit instruction
4081 (define_insn "ashldi_extsi"
4082 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4084 (match_operator:DI 2 "extend_operator"
4085 [(match_operand:SI 1 "general_operand" "rm")])
4090 if (GET_CODE (operands[0]) == REG)
4091 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4093 operands[2] = adjust_address (operands[0], SImode, 4);
4094 if (ADDRESS_REG_P (operands[0]))
4095 return "move%.l %1,%0\;sub%.l %2,%2";
4097 return "move%.l %1,%0\;clr%.l %2";
4100 (define_insn "ashldi_sexthi"
4101 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4102 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4104 (clobber (match_scratch:SI 2 "=a,X"))]
4108 if (GET_CODE (operands[0]) == MEM)
4110 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4111 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
4112 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4113 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
4116 operands[3] = adjust_address (operands[0], SImode, 4);
4117 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
4120 else if (DATA_REG_P (operands[0]))
4121 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
4123 return "move%.w %1,%0\;sub%.l %R0,%R0";
4126 (define_insn "*ashldi3_const1"
4127 [(set (match_operand:DI 0 "register_operand" "=d")
4128 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4131 "add%.l %R0,%R0\;addx%.l %0,%0")
4134 [(set (match_operand:DI 0 "register_operand" "")
4135 (ashift:DI (match_operand:DI 1 "register_operand" "")
4137 "reload_completed && !TARGET_COLDFIRE"
4139 (ashift:DI (match_dup 1) (const_int 1)))
4141 (ashift:DI (match_dup 0) (const_int 1)))]
4145 [(set (match_operand:DI 0 "register_operand" "")
4146 (ashift:DI (match_operand:DI 1 "register_operand" "")
4148 "reload_completed && !TARGET_COLDFIRE"
4150 (ashift:DI (match_dup 1) (const_int 2)))
4152 (ashift:DI (match_dup 0) (const_int 1)))]
4156 [(set (match_operand:DI 0 "register_operand" "")
4157 (ashift:DI (match_operand:DI 1 "register_operand" "")
4159 "reload_completed && !TARGET_COLDFIRE"
4161 (rotate:SI (match_dup 2) (const_int 8)))
4163 (rotate:SI (match_dup 3) (const_int 8)))
4164 (set (strict_low_part (subreg:QI (match_dup 0) 3))
4165 (subreg:QI (match_dup 0) 7))
4166 (set (strict_low_part (subreg:QI (match_dup 0) 7))
4169 operands[2] = gen_highpart (SImode, operands[0]);
4170 operands[3] = gen_lowpart (SImode, operands[0]);
4174 [(set (match_operand:DI 0 "register_operand" "")
4175 (ashift:DI (match_operand:DI 1 "register_operand" "")
4177 "reload_completed && !TARGET_COLDFIRE"
4179 (rotate:SI (match_dup 2) (const_int 16)))
4181 (rotate:SI (match_dup 3) (const_int 16)))
4182 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4183 (subreg:HI (match_dup 0) 6))
4184 (set (strict_low_part (subreg:HI (match_dup 0) 6))
4187 operands[2] = gen_highpart (SImode, operands[0]);
4188 operands[3] = gen_lowpart (SImode, operands[0]);
4192 [(set (match_operand:DI 0 "pre_dec_operand" "")
4193 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4196 [(set (match_dup 0) (const_int 0))
4197 (set (match_dup 0) (match_dup 1))]
4199 operands[0] = adjust_address(operands[0], SImode, 0);
4200 operands[1] = gen_lowpart(SImode, operands[1]);
4204 [(set (match_operand:DI 0 "post_inc_operand" "")
4205 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4208 [(set (match_dup 0) (match_dup 1))
4209 (set (match_dup 0) (const_int 0))]
4211 operands[0] = adjust_address(operands[0], SImode, 0);
4212 operands[1] = gen_lowpart(SImode, operands[1]);
4215 (define_insn_and_split "*ashldi3_const32"
4216 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
4217 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
4221 "&& reload_completed"
4222 [(set (match_dup 4) (match_dup 3))
4223 (set (match_dup 2) (const_int 0))]
4224 "split_di(operands, 2, operands + 2, operands + 4);")
4227 [(set (match_operand:DI 0 "register_operand" "")
4228 (ashift:DI (match_operand:DI 1 "register_operand" "")
4229 (match_operand 2 "const_int_operand" "")))]
4230 "reload_completed && !TARGET_COLDFIRE
4231 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
4232 [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
4233 (set (match_dup 3) (match_dup 4))
4234 (set (match_dup 4) (const_int 0))]
4236 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4237 operands[3] = gen_highpart (SImode, operands[0]);
4238 operands[4] = gen_lowpart (SImode, operands[0]);
4242 [(set (match_operand:DI 0 "register_operand" "")
4243 (ashift:DI (match_operand:DI 1 "register_operand" "")
4245 "reload_completed && !TARGET_COLDFIRE"
4246 [(set (match_dup 2) (match_dup 3))
4248 (rotate:SI (match_dup 2) (const_int 16)))
4249 (set (match_dup 3) (const_int 0))
4250 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4253 operands[2] = gen_highpart (SImode, operands[0]);
4254 operands[3] = gen_lowpart (SImode, operands[0]);
4258 [(set (match_operand:DI 0 "register_operand" "")
4259 (ashift:DI (match_operand:DI 1 "register_operand" "")
4260 (match_operand 2 "const_int_operand" "")))]
4261 "reload_completed && !TARGET_COLDFIRE
4262 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
4263 [(set (match_dup 3) (match_dup 2))
4264 (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
4265 (set (match_dup 3) (match_dup 4))
4266 (set (match_dup 4) (const_int 0))]
4268 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4269 operands[3] = gen_highpart (SImode, operands[0]);
4270 operands[4] = gen_lowpart (SImode, operands[0]);
4273 (define_insn "*ashldi3"
4274 [(set (match_operand:DI 0 "register_operand" "=d")
4275 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4276 (match_operand 2 "const_int_operand" "n")))]
4278 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4279 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4280 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4283 (define_expand "ashldi3"
4284 [(set (match_operand:DI 0 "register_operand" "")
4285 (ashift:DI (match_operand:DI 1 "register_operand" "")
4286 (match_operand 2 "const_int_operand" "")))]
4289 /* ??? This is a named pattern like this is not allowed to FAIL based
4291 if (GET_CODE (operands[2]) != CONST_INT
4292 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4293 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4294 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4298 ;; On most 68k models, this makes faster code in a special case.
4300 (define_insn "ashlsi_16"
4301 [(set (match_operand:SI 0 "register_operand" "=d")
4302 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4307 return "swap %0\;clr%.w %0";
4310 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4311 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4313 ;; On the 68000, this makes faster code in a special case.
4315 (define_insn "ashlsi_17_24"
4316 [(set (match_operand:SI 0 "register_operand" "=d")
4317 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4318 (match_operand:SI 2 "const_int_operand" "n")))]
4320 && INTVAL (operands[2]) > 16
4321 && INTVAL (operands[2]) <= 24"
4325 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4326 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4329 (define_insn "ashlsi3"
4330 [(set (match_operand:SI 0 "register_operand" "=d")
4331 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4332 (match_operand:SI 2 "general_operand" "dI")))]
4335 if (operands[2] == const1_rtx)
4337 cc_status.flags = CC_NO_OVERFLOW;
4338 return "add%.l %0,%0";
4340 return "lsl%.l %2,%0";
4343 (define_insn "ashlhi3"
4344 [(set (match_operand:HI 0 "register_operand" "=d")
4345 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4346 (match_operand:HI 2 "general_operand" "dI")))]
4351 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4352 (ashift:HI (match_dup 0)
4353 (match_operand:HI 1 "general_operand" "dI")))]
4357 (define_insn "ashlqi3"
4358 [(set (match_operand:QI 0 "register_operand" "=d")
4359 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4360 (match_operand:QI 2 "general_operand" "dI")))]
4365 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4366 (ashift:QI (match_dup 0)
4367 (match_operand:QI 1 "general_operand" "dI")))]
4371 ;; On most 68k models, this makes faster code in a special case.
4373 (define_insn "ashrsi_16"
4374 [(set (match_operand:SI 0 "register_operand" "=d")
4375 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4378 "swap %0\;ext%.l %0")
4380 ;; On the 68000, this makes faster code in a special case.
4383 [(set (match_operand:SI 0 "register_operand" "=d")
4384 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4385 (match_operand:SI 2 "const_int_operand" "n")))]
4387 && INTVAL (operands[2]) > 16
4388 && INTVAL (operands[2]) <= 24"
4390 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4391 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4394 (define_insn "subreghi1ashrdi_const32"
4395 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4396 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4397 (const_int 32)) 6))]
4400 if (GET_CODE (operands[1]) != REG)
4401 operands[1] = adjust_address (operands[1], HImode, 2);
4402 return "move%.w %1,%0";
4405 (define_insn "subregsi1ashrdi_const32"
4406 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4407 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4408 (const_int 32)) 4))]
4411 return "move%.l %1,%0";
4414 (define_insn "*ashrdi3_const1"
4415 [(set (match_operand:DI 0 "register_operand" "=d")
4416 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4420 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4421 return "asr%.l #1,%0\;roxr%.l #1,%1";
4425 [(set (match_operand:DI 0 "register_operand" "")
4426 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4428 "reload_completed && !TARGET_COLDFIRE"
4430 (ashiftrt:DI (match_dup 1) (const_int 1)))
4432 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4436 [(set (match_operand:DI 0 "register_operand" "")
4437 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4439 "reload_completed && !TARGET_COLDFIRE"
4441 (ashiftrt:DI (match_dup 1) (const_int 2)))
4443 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4447 [(set (match_operand:DI 0 "register_operand" "")
4448 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4450 "reload_completed && !TARGET_COLDFIRE"
4451 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
4452 (subreg:QI (match_dup 0) 3))
4454 (ashiftrt:SI (match_dup 2) (const_int 8)))
4456 (rotatert:SI (match_dup 3) (const_int 8)))]
4458 operands[2] = gen_highpart (SImode, operands[0]);
4459 operands[3] = gen_lowpart (SImode, operands[0]);
4463 [(set (match_operand:DI 0 "register_operand" "")
4464 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4466 "reload_completed && !TARGET_COLDFIRE"
4467 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
4468 (subreg:HI (match_dup 0) 2))
4470 (rotate:SI (match_dup 2) (const_int 16)))
4472 (rotate:SI (match_dup 3) (const_int 16)))
4474 (sign_extend:SI (subreg:HI (match_dup 2) 2)))]
4476 operands[2] = gen_highpart (SImode, operands[0]);
4477 operands[3] = gen_lowpart (SImode, operands[0]);
4480 (define_insn "*ashrdi_const32"
4481 [(set (match_operand:DI 0 "register_operand" "=d")
4482 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
4488 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
4490 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
4493 (define_insn "*ashrdi_const32_mem"
4494 [(set (match_operand:DI 0 "memory_operand" "=o,<")
4495 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro")
4497 (clobber (match_scratch:SI 2 "=d,d"))]
4501 operands[3] = adjust_address (operands[0], SImode,
4502 which_alternative == 0 ? 4 : 0);
4503 operands[0] = adjust_address (operands[0], SImode, 0);
4504 if (TARGET_68020 || TARGET_COLDFIRE)
4505 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4507 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4511 [(set (match_operand:DI 0 "register_operand" "")
4512 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4514 "reload_completed && !TARGET_COLDFIRE"
4516 (ashiftrt:SI (match_dup 3) (const_int 31)))
4519 "split_di(operands, 1, operands + 2, operands + 3);")
4521 ;; The predicate below must be general_operand, because ashrdi3 allows that
4522 (define_insn "ashrdi_const"
4523 [(set (match_operand:DI 0 "register_operand" "=d")
4524 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4525 (match_operand 2 "const_int_operand" "n")))]
4527 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4528 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4529 || INTVAL (operands[2]) == 31
4530 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4532 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4534 if (INTVAL (operands[2]) == 48)
4535 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
4536 if (INTVAL (operands[2]) == 31)
4537 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
4538 if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)
4540 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4541 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
4542 "moveq %2,%1\;asr%.l %1,%0", operands);
4543 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
4544 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
4545 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
4550 (define_expand "ashrdi3"
4551 [(set (match_operand:DI 0 "register_operand" "")
4552 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4553 (match_operand 2 "const_int_operand" "")))]
4556 /* ??? This is a named pattern like this is not allowed to FAIL based
4558 if (GET_CODE (operands[2]) != CONST_INT
4559 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4560 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4561 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4565 ;; On all 68k models, this makes faster code in a special case.
4567 (define_insn "ashrsi_31"
4568 [(set (match_operand:SI 0 "register_operand" "=d")
4569 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4573 return "add%.l %0,%0\;subx%.l %0,%0";
4576 (define_insn "ashrsi3"
4577 [(set (match_operand:SI 0 "register_operand" "=d")
4578 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4579 (match_operand:SI 2 "general_operand" "dI")))]
4583 (define_insn "ashrhi3"
4584 [(set (match_operand:HI 0 "register_operand" "=d")
4585 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4586 (match_operand:HI 2 "general_operand" "dI")))]
4591 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4592 (ashiftrt:HI (match_dup 0)
4593 (match_operand:HI 1 "general_operand" "dI")))]
4597 (define_insn "ashrqi3"
4598 [(set (match_operand:QI 0 "register_operand" "=d")
4599 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4600 (match_operand:QI 2 "general_operand" "dI")))]
4605 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4606 (ashiftrt:QI (match_dup 0)
4607 (match_operand:QI 1 "general_operand" "dI")))]
4611 ;; logical shift instructions
4613 ;; commented out because of reload problems in 950612-1.c
4616 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4617 ;; (const_int 32)) 4))
4618 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4619 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4620 ;; (const_int 32)) 4))]
4623 ;; return "move%.l %0,%1";
4628 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4629 ;; (const_int 32)) 0))
4630 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4631 ;; (lshiftrt:DI (match_dup 0)
4632 ;; (const_int 32)))]
4635 ;; if (GET_CODE (operands[1]) == REG)
4636 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4638 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4639 ;; return "move%.l %0,%2\;clr%.l %1";
4642 (define_insn "subreg1lshrdi_const32"
4643 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4644 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4645 (const_int 32)) 4))]
4648 return "move%.l %1,%0";
4651 (define_insn "*lshrdi3_const1"
4652 [(set (match_operand:DI 0 "register_operand" "=d")
4653 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
4656 "lsr%.l #1,%0\;roxr%.l #1,%R0")
4659 [(set (match_operand:DI 0 "register_operand" "")
4660 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4662 "reload_completed && !TARGET_COLDFIRE"
4664 (lshiftrt:DI (match_dup 1) (const_int 1)))
4666 (lshiftrt:DI (match_dup 0) (const_int 1)))]
4670 [(set (match_operand:DI 0 "register_operand" "")
4671 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4673 "reload_completed && !TARGET_COLDFIRE"
4675 (lshiftrt:DI (match_dup 1) (const_int 2)))
4677 (lshiftrt:DI (match_dup 0) (const_int 1)))]
4681 [(set (match_operand:DI 0 "register_operand" "")
4682 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4684 "reload_completed && !TARGET_COLDFIRE"
4685 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
4686 (subreg:QI (match_dup 0) 3))
4688 (lshiftrt:SI (match_dup 2) (const_int 8)))
4690 (rotatert:SI (match_dup 3) (const_int 8)))]
4692 operands[2] = gen_highpart (SImode, operands[0]);
4693 operands[3] = gen_lowpart (SImode, operands[0]);
4697 [(set (match_operand:DI 0 "register_operand" "")
4698 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4700 "reload_completed && !TARGET_COLDFIRE"
4701 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
4702 (subreg:HI (match_dup 0) 2))
4703 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4706 (rotate:SI (match_dup 3) (const_int 16)))
4708 (rotate:SI (match_dup 2) (const_int 16)))]
4710 operands[2] = gen_highpart (SImode, operands[0]);
4711 operands[3] = gen_lowpart (SImode, operands[0]);
4715 [(set (match_operand:DI 0 "pre_dec_operand" "")
4716 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
4719 [(set (match_dup 0) (match_dup 1))
4720 (set (match_dup 0) (const_int 0))]
4722 operands[0] = adjust_address(operands[0], SImode, 0);
4723 operands[1] = gen_highpart(SImode, operands[1]);
4727 [(set (match_operand:DI 0 "post_inc_operand" "")
4728 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
4731 [(set (match_dup 0) (const_int 0))
4732 (set (match_dup 0) (match_dup 1))]
4734 operands[0] = adjust_address(operands[0], SImode, 0);
4735 operands[1] = gen_highpart(SImode, operands[1]);
4739 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4740 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
4743 [(set (match_dup 2) (match_dup 5))
4744 (set (match_dup 4) (const_int 0))]
4745 "split_di(operands, 2, operands + 2, operands + 4);")
4747 (define_insn "*lshrdi_const32"
4748 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
4749 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4755 [(set (match_operand:DI 0 "register_operand" "")
4756 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4757 (match_operand 2 "const_int_operand" "")))]
4758 "reload_completed && !TARGET_COLDFIRE
4759 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
4760 [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
4761 (set (match_dup 4) (match_dup 3))
4762 (set (match_dup 3) (const_int 0))]
4764 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4765 operands[3] = gen_highpart (SImode, operands[0]);
4766 operands[4] = gen_lowpart (SImode, operands[0]);
4770 [(set (match_operand:DI 0 "register_operand" "")
4771 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4774 [(set (match_dup 3) (match_dup 2))
4775 (set (strict_low_part (subreg:HI (match_dup 0) 6))
4777 (set (match_dup 2) (const_int 0))
4779 (rotate:SI (match_dup 3) (const_int 16)))]
4781 operands[2] = gen_highpart (SImode, operands[0]);
4782 operands[3] = gen_lowpart (SImode, operands[0]);
4786 [(set (match_operand:DI 0 "register_operand" "")
4787 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4788 (match_operand 2 "const_int_operand" "")))]
4789 "reload_completed && !TARGET_COLDFIRE
4790 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
4791 [(set (match_dup 4) (match_dup 2))
4792 (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4)))
4793 (set (match_dup 4) (match_dup 3))
4794 (set (match_dup 3) (const_int 0))]
4796 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4797 operands[3] = gen_highpart (SImode, operands[0]);
4798 operands[4] = gen_lowpart (SImode, operands[0]);
4801 (define_insn "*lshrdi_const63"
4802 [(set (match_operand:DI 0 "register_operand" "=d")
4803 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
4806 "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
4808 (define_insn "*lshrdi3_const"
4809 [(set (match_operand:DI 0 "register_operand" "=d")
4810 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
4811 (match_operand 2 "const_int_operand" "n")))]
4813 && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3)
4814 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4815 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4818 (define_expand "lshrdi3"
4819 [(set (match_operand:DI 0 "register_operand" "")
4820 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4821 (match_operand 2 "const_int_operand" "")))]
4824 /* ??? This is a named pattern like this is not allowed to FAIL based
4826 if (GET_CODE (operands[2]) != CONST_INT
4827 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4828 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4829 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4833 ;; On all 68k models, this makes faster code in a special case.
4835 (define_insn "lshrsi_31"
4836 [(set (match_operand:SI 0 "register_operand" "=d")
4837 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4841 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
4844 ;; On most 68k models, this makes faster code in a special case.
4846 (define_insn "lshrsi_16"
4847 [(set (match_operand:SI 0 "register_operand" "=d")
4848 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4853 return "clr%.w %0\;swap %0";
4856 ;; On the 68000, this makes faster code in a special case.
4858 (define_insn "lshrsi_17_24"
4859 [(set (match_operand:SI 0 "register_operand" "=d")
4860 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4861 (match_operand:SI 2 "const_int_operand" "n")))]
4863 && INTVAL (operands[2]) > 16
4864 && INTVAL (operands[2]) <= 24"
4866 /* I think lsr%.w sets the CC properly. */
4867 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4868 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
4871 (define_insn "lshrsi3"
4872 [(set (match_operand:SI 0 "register_operand" "=d")
4873 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4874 (match_operand:SI 2 "general_operand" "dI")))]
4878 (define_insn "lshrhi3"
4879 [(set (match_operand:HI 0 "register_operand" "=d")
4880 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4881 (match_operand:HI 2 "general_operand" "dI")))]
4886 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4887 (lshiftrt:HI (match_dup 0)
4888 (match_operand:HI 1 "general_operand" "dI")))]
4892 (define_insn "lshrqi3"
4893 [(set (match_operand:QI 0 "register_operand" "=d")
4894 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4895 (match_operand:QI 2 "general_operand" "dI")))]
4900 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4901 (lshiftrt:QI (match_dup 0)
4902 (match_operand:QI 1 "general_operand" "dI")))]
4906 ;; rotate instructions
4908 (define_insn "rotlsi3"
4909 [(set (match_operand:SI 0 "register_operand" "=d")
4910 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4911 (match_operand:SI 2 "general_operand" "dINO")))]
4914 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4916 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4918 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4919 return "ror%.l %2,%0";
4922 return "rol%.l %2,%0";
4925 (define_insn "rotlhi3"
4926 [(set (match_operand:HI 0 "register_operand" "=d")
4927 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4928 (match_operand:HI 2 "general_operand" "dIP")))]
4931 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4933 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4934 return "ror%.w %2,%0";
4937 return "rol%.w %2,%0";
4941 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4942 (rotate:HI (match_dup 0)
4943 (match_operand:HI 1 "general_operand" "dIP")))]
4946 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4948 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4949 return "ror%.w %2,%0";
4952 return "rol%.w %2,%0";
4955 (define_insn "rotlqi3"
4956 [(set (match_operand:QI 0 "register_operand" "=d")
4957 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4958 (match_operand:QI 2 "general_operand" "dI")))]
4961 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4963 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4964 return "ror%.b %2,%0";
4967 return "rol%.b %2,%0";
4971 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4972 (rotate:QI (match_dup 0)
4973 (match_operand:QI 1 "general_operand" "dI")))]
4976 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4978 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4979 return "ror%.b %2,%0";
4982 return "rol%.b %2,%0";
4985 (define_insn "rotrsi3"
4986 [(set (match_operand:SI 0 "register_operand" "=d")
4987 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4988 (match_operand:SI 2 "general_operand" "dI")))]
4992 (define_insn "rotrhi3"
4993 [(set (match_operand:HI 0 "register_operand" "=d")
4994 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4995 (match_operand:HI 2 "general_operand" "dI")))]
5000 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5001 (rotatert:HI (match_dup 0)
5002 (match_operand:HI 1 "general_operand" "dI")))]
5006 (define_insn "rotrqi3"
5007 [(set (match_operand:QI 0 "register_operand" "=d")
5008 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5009 (match_operand:QI 2 "general_operand" "dI")))]
5014 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5015 (rotatert:QI (match_dup 0)
5016 (match_operand:QI 1 "general_operand" "dI")))]
5021 ;; Bit set/clear in memory byte.
5023 ;; set bit, bit number is int
5024 (define_insn "bsetmemqi"
5025 [(set (match_operand:QI 0 "memory_operand" "+m")
5026 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5027 (match_operand:SI 1 "general_operand" "d")) 3)
5032 return "bset %1,%0";
5035 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5037 [(set (match_operand:QI 0 "memory_operand" "+m")
5038 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5039 (match_operator:SI 2 "extend_operator"
5040 [(match_operand 1 "general_operand" "d")])) 3)
5045 return "bset %1,%0";
5048 ;; clear bit, bit number is int
5049 (define_insn "bclrmemqi"
5050 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5052 (minus:SI (const_int 7)
5053 (match_operand:SI 1 "general_operand" "d")))
5058 return "bclr %1,%0";
5061 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5063 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5065 (minus:SI (const_int 7)
5066 (match_operator:SI 2 "extend_operator"
5067 [(match_operand 1 "general_operand" "d")])))
5072 return "bclr %1,%0";
5075 ;; Special cases of bit-field insns which we should
5076 ;; recognize in preference to the general case.
5077 ;; These handle aligned 8-bit and 16-bit fields,
5078 ;; which can usually be done with move instructions.
5081 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5082 ; alignment of structure members is specified.
5084 ; The move is allowed to be odd byte aligned, because that's still faster
5085 ; than an odd byte aligned bit-field instruction.
5088 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5090 (match_operand:SI 1 "const_int_operand" "n"))
5091 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5092 "TARGET_68020 && TARGET_BITFIELD
5093 && (INTVAL (operands[1]) % 8) == 0
5094 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5097 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5099 return "move%.l %2,%0";
5103 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5104 (match_operand:SI 1 "const_int_operand" "n")
5105 (match_operand:SI 2 "const_int_operand" "n"))
5106 (match_operand:SI 3 "register_operand" "d"))]
5107 "TARGET_68020 && TARGET_BITFIELD
5108 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5109 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5110 && (GET_CODE (operands[0]) == REG
5111 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5113 if (REG_P (operands[0]))
5115 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5116 return "bfins %3,%0{%b2:%b1}";
5119 operands[0] = adjust_address (operands[0],
5120 INTVAL (operands[1]) == 8 ? QImode : HImode,
5121 INTVAL (operands[2]) / 8);
5123 if (GET_CODE (operands[3]) == MEM)
5124 operands[3] = adjust_address (operands[3],
5125 INTVAL (operands[1]) == 8 ? QImode : HImode,
5126 (32 - INTVAL (operands[1])) / 8);
5128 if (INTVAL (operands[1]) == 8)
5129 return "move%.b %3,%0";
5130 return "move%.w %3,%0";
5135 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5136 ; alignment of structure members is specified.
5138 ; The move is allowed to be odd byte aligned, because that's still faster
5139 ; than an odd byte aligned bit-field instruction.
5142 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5143 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5145 (match_operand:SI 2 "const_int_operand" "n")))]
5146 "TARGET_68020 && TARGET_BITFIELD
5147 && (INTVAL (operands[2]) % 8) == 0
5148 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5151 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5153 return "move%.l %1,%0";
5157 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5158 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5159 (match_operand:SI 2 "const_int_operand" "n")
5160 (match_operand:SI 3 "const_int_operand" "n")))]
5161 "TARGET_68020 && TARGET_BITFIELD
5162 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5163 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5164 && (GET_CODE (operands[1]) == REG
5165 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5167 cc_status.flags |= CC_NOT_NEGATIVE;
5168 if (REG_P (operands[1]))
5170 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5171 return "bfextu %1{%b3:%b2},%0";
5175 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5177 output_asm_insn ("clr%.l %0", operands);
5178 if (GET_CODE (operands[0]) == MEM)
5179 operands[0] = adjust_address (operands[0],
5180 INTVAL (operands[2]) == 8 ? QImode : HImode,
5181 (32 - INTVAL (operands[1])) / 8);
5183 if (INTVAL (operands[2]) == 8)
5184 return "move%.b %1,%0";
5185 return "move%.w %1,%0";
5189 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5190 ; alignment of structure members is specified.
5192 ; The move is allowed to be odd byte aligned, because that's still faster
5193 ; than an odd byte aligned bit-field instruction.
5196 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5197 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5199 (match_operand:SI 2 "const_int_operand" "n")))]
5200 "TARGET_68020 && TARGET_BITFIELD
5201 && (INTVAL (operands[2]) % 8) == 0
5202 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5205 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5207 return "move%.l %1,%0";
5211 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5212 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5213 (match_operand:SI 2 "const_int_operand" "n")
5214 (match_operand:SI 3 "const_int_operand" "n")))]
5215 "TARGET_68020 && TARGET_BITFIELD
5216 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5217 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5218 && (GET_CODE (operands[1]) == REG
5219 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5221 if (REG_P (operands[1]))
5223 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5224 return "bfexts %1{%b3:%b2},%0";
5228 = adjust_address (operands[1],
5229 INTVAL (operands[2]) == 8 ? QImode : HImode,
5230 INTVAL (operands[3]) / 8);
5232 if (INTVAL (operands[2]) == 8)
5233 return "move%.b %1,%0\;extb%.l %0";
5234 return "move%.w %1,%0\;ext%.l %0";
5237 ;; Bit-field instructions, general cases.
5238 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5239 ;; so that its address is reloaded.
5241 (define_expand "extv"
5242 [(set (match_operand:SI 0 "register_operand" "")
5243 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5244 (match_operand:SI 2 "const_int_operand" "")
5245 (match_operand:SI 3 "const_int_operand" "")))]
5246 "TARGET_68020 && TARGET_BITFIELD"
5250 [(set (match_operand:SI 0 "register_operand" "=d")
5251 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5252 (match_operand:SI 2 "nonmemory_operand" "dn")
5253 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5254 "TARGET_68020 && TARGET_BITFIELD"
5255 "bfexts %1{%b3:%b2},%0")
5257 (define_expand "extzv"
5258 [(set (match_operand:SI 0 "register_operand" "")
5259 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5260 (match_operand:SI 2 "const_int_operand" "")
5261 (match_operand:SI 3 "const_int_operand" "")))]
5262 "TARGET_68020 && TARGET_BITFIELD"
5266 [(set (match_operand:SI 0 "register_operand" "=d")
5267 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5268 (match_operand:SI 2 "nonmemory_operand" "dn")
5269 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5270 "TARGET_68020 && TARGET_BITFIELD"
5272 if (GET_CODE (operands[2]) == CONST_INT)
5274 if (INTVAL (operands[2]) != 32)
5275 cc_status.flags |= CC_NOT_NEGATIVE;
5281 return "bfextu %1{%b3:%b2},%0";
5285 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5286 (match_operand:SI 1 "nonmemory_operand" "dn")
5287 (match_operand:SI 2 "nonmemory_operand" "dn"))
5288 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5289 (match_operand 3 "const_int_operand" "n")))]
5290 "TARGET_68020 && TARGET_BITFIELD
5291 && (INTVAL (operands[3]) == -1
5292 || (GET_CODE (operands[1]) == CONST_INT
5293 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5296 return "bfchg %0{%b2:%b1}";
5300 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5301 (match_operand:SI 1 "nonmemory_operand" "dn")
5302 (match_operand:SI 2 "nonmemory_operand" "dn"))
5304 "TARGET_68020 && TARGET_BITFIELD"
5307 return "bfclr %0{%b2:%b1}";
5311 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5312 (match_operand:SI 1 "general_operand" "dn")
5313 (match_operand:SI 2 "general_operand" "dn"))
5315 "TARGET_68020 && TARGET_BITFIELD"
5318 return "bfset %0{%b2:%b1}";
5321 (define_expand "insv"
5322 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5323 (match_operand:SI 1 "const_int_operand" "")
5324 (match_operand:SI 2 "const_int_operand" ""))
5325 (match_operand:SI 3 "register_operand" ""))]
5326 "TARGET_68020 && TARGET_BITFIELD"
5330 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5331 (match_operand:SI 1 "nonmemory_operand" "dn")
5332 (match_operand:SI 2 "nonmemory_operand" "dn"))
5333 (match_operand:SI 3 "register_operand" "d"))]
5334 "TARGET_68020 && TARGET_BITFIELD"
5335 "bfins %3,%0{%b2:%b1}")
5337 ;; Now recognize bit-field insns that operate on registers
5338 ;; (or at least were intended to do so).
5341 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5342 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5343 (match_operand:SI 2 "const_int_operand" "n")
5344 (match_operand:SI 3 "const_int_operand" "n")))]
5345 "TARGET_68020 && TARGET_BITFIELD"
5346 "bfexts %1{%b3:%b2},%0")
5349 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5350 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5351 (match_operand:SI 2 "const_int_operand" "n")
5352 (match_operand:SI 3 "const_int_operand" "n")))]
5353 "TARGET_68020 && TARGET_BITFIELD"
5355 if (GET_CODE (operands[2]) == CONST_INT)
5357 if (INTVAL (operands[2]) != 32)
5358 cc_status.flags |= CC_NOT_NEGATIVE;
5364 return "bfextu %1{%b3:%b2},%0";
5368 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5369 (match_operand:SI 1 "const_int_operand" "n")
5370 (match_operand:SI 2 "const_int_operand" "n"))
5372 "TARGET_68020 && TARGET_BITFIELD"
5375 return "bfclr %0{%b2:%b1}";
5379 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5380 (match_operand:SI 1 "const_int_operand" "n")
5381 (match_operand:SI 2 "const_int_operand" "n"))
5383 "TARGET_68020 && TARGET_BITFIELD"
5386 return "bfset %0{%b2:%b1}";
5390 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5391 (match_operand:SI 1 "const_int_operand" "n")
5392 (match_operand:SI 2 "const_int_operand" "n"))
5393 (match_operand:SI 3 "register_operand" "d"))]
5394 "TARGET_68020 && TARGET_BITFIELD"
5397 /* These special cases are now recognized by a specific pattern. */
5398 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5399 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5400 return "move%.w %3,%0";
5401 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5402 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5403 return "move%.b %3,%0";
5405 return "bfins %3,%0{%b2:%b1}";
5408 ;; Special patterns for optimizing bit-field instructions.
5412 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5413 (match_operand:SI 1 "const_int_operand" "n")
5414 (match_operand:SI 2 "general_operand" "dn")))]
5415 "TARGET_68020 && TARGET_BITFIELD"
5417 if (operands[1] == const1_rtx
5418 && GET_CODE (operands[2]) == CONST_INT)
5420 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5421 return output_btst (operands,
5422 GEN_INT (width - INTVAL (operands[2])),
5423 operands[0], insn, 1000);
5424 /* Pass 1000 as SIGNPOS argument so that btst will
5425 not think we are testing the sign bit for an `and'
5426 and assume that nonzero implies a negative result. */
5428 if (INTVAL (operands[1]) != 32)
5429 cc_status.flags = CC_NOT_NEGATIVE;
5430 return "bftst %0{%b2:%b1}";
5434 ;;; now handle the register cases
5437 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5438 (match_operand:SI 1 "const_int_operand" "n")
5439 (match_operand:SI 2 "general_operand" "dn")))]
5440 "TARGET_68020 && TARGET_BITFIELD"
5442 if (operands[1] == const1_rtx
5443 && GET_CODE (operands[2]) == CONST_INT)
5445 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5446 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5447 operands[0], insn, 1000);
5448 /* Pass 1000 as SIGNPOS argument so that btst will
5449 not think we are testing the sign bit for an `and'
5450 and assume that nonzero implies a negative result. */
5452 if (INTVAL (operands[1]) != 32)
5453 cc_status.flags = CC_NOT_NEGATIVE;
5454 return "bftst %0{%b2:%b1}";
5457 (define_insn "scc0_di"
5458 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5459 (match_operator 1 "valid_dbcc_comparison_p"
5460 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5463 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5466 (define_insn "scc0_di_5200"
5467 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5468 (match_operator 1 "valid_dbcc_comparison_p"
5469 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5472 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5475 (define_insn "scc_di"
5476 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5477 (match_operator 1 "valid_dbcc_comparison_p"
5478 [(match_operand:DI 2 "general_operand" "ro,r")
5479 (match_operand:DI 3 "general_operand" "r,ro")]))]
5482 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5485 (define_insn "scc_di_5200"
5486 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5487 (match_operator 1 "valid_dbcc_comparison_p"
5488 [(match_operand:DI 2 "general_operand" "ro,r")
5489 (match_operand:DI 3 "general_operand" "r,ro")]))]
5492 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5495 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5496 ;; memory, but we cannot allow it to be in memory in case the address
5497 ;; needs to be reloaded.
5499 (define_expand "seq"
5500 [(set (match_operand:QI 0 "register_operand" "")
5501 (eq:QI (cc0) (const_int 0)))]
5504 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5505 && m68k_last_compare_had_fp_operands)
5507 m68k_last_compare_had_fp_operands = 0;
5513 [(set (match_operand:QI 0 "register_operand" "=d")
5514 (eq:QI (cc0) (const_int 0)))]
5517 cc_status = cc_prev_status;
5518 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5521 (define_expand "sne"
5522 [(set (match_operand:QI 0 "register_operand" "")
5523 (ne:QI (cc0) (const_int 0)))]
5526 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5527 && m68k_last_compare_had_fp_operands)
5529 m68k_last_compare_had_fp_operands = 0;
5535 [(set (match_operand:QI 0 "register_operand" "=d")
5536 (ne:QI (cc0) (const_int 0)))]
5539 cc_status = cc_prev_status;
5540 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5543 (define_expand "sgt"
5544 [(set (match_operand:QI 0 "register_operand" "")
5545 (gt:QI (cc0) (const_int 0)))]
5548 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5549 && m68k_last_compare_had_fp_operands)
5551 m68k_last_compare_had_fp_operands = 0;
5557 [(set (match_operand:QI 0 "register_operand" "=d")
5558 (gt:QI (cc0) (const_int 0)))]
5561 cc_status = cc_prev_status;
5562 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5565 (define_expand "sgtu"
5566 [(set (match_operand:QI 0 "register_operand" "")
5567 (gtu:QI (cc0) (const_int 0)))]
5572 [(set (match_operand:QI 0 "register_operand" "=d")
5573 (gtu:QI (cc0) (const_int 0)))]
5576 cc_status = cc_prev_status;
5580 (define_expand "slt"
5581 [(set (match_operand:QI 0 "register_operand" "")
5582 (lt:QI (cc0) (const_int 0)))]
5585 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5586 && m68k_last_compare_had_fp_operands)
5588 m68k_last_compare_had_fp_operands = 0;
5594 [(set (match_operand:QI 0 "register_operand" "=d")
5595 (lt:QI (cc0) (const_int 0)))]
5598 cc_status = cc_prev_status;
5599 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5602 (define_expand "sltu"
5603 [(set (match_operand:QI 0 "register_operand" "")
5604 (ltu:QI (cc0) (const_int 0)))]
5609 [(set (match_operand:QI 0 "register_operand" "=d")
5610 (ltu:QI (cc0) (const_int 0)))]
5613 cc_status = cc_prev_status;
5617 (define_expand "sge"
5618 [(set (match_operand:QI 0 "register_operand" "")
5619 (ge:QI (cc0) (const_int 0)))]
5622 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5623 && m68k_last_compare_had_fp_operands)
5625 m68k_last_compare_had_fp_operands = 0;
5631 [(set (match_operand:QI 0 "register_operand" "=d")
5632 (ge:QI (cc0) (const_int 0)))]
5635 cc_status = cc_prev_status;
5636 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
5639 (define_expand "sgeu"
5640 [(set (match_operand:QI 0 "register_operand" "")
5641 (geu:QI (cc0) (const_int 0)))]
5646 [(set (match_operand:QI 0 "register_operand" "=d")
5647 (geu:QI (cc0) (const_int 0)))]
5650 cc_status = cc_prev_status;
5654 (define_expand "sle"
5655 [(set (match_operand:QI 0 "register_operand" "")
5656 (le:QI (cc0) (const_int 0)))]
5659 if ((TUNE_68060 || TARGET_COLDFIRE_FPU)
5660 && m68k_last_compare_had_fp_operands)
5662 m68k_last_compare_had_fp_operands = 0;
5668 [(set (match_operand:QI 0 "register_operand" "=d")
5669 (le:QI (cc0) (const_int 0)))]
5672 cc_status = cc_prev_status;
5673 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
5676 (define_expand "sleu"
5677 [(set (match_operand:QI 0 "register_operand" "")
5678 (leu:QI (cc0) (const_int 0)))]
5683 [(set (match_operand:QI 0 "register_operand" "=d")
5684 (leu:QI (cc0) (const_int 0)))]
5687 cc_status = cc_prev_status;
5691 (define_expand "sordered"
5692 [(set (match_operand:QI 0 "register_operand" "")
5693 (ordered:QI (cc0) (const_int 0)))]
5694 "TARGET_68881 && !TUNE_68060"
5696 gcc_assert (m68k_last_compare_had_fp_operands);
5697 m68k_last_compare_had_fp_operands = 0;
5700 (define_insn "*sordered_1"
5701 [(set (match_operand:QI 0 "register_operand" "=d")
5702 (ordered:QI (cc0) (const_int 0)))]
5703 "TARGET_68881 && !TUNE_68060"
5705 cc_status = cc_prev_status;
5709 (define_expand "sunordered"
5710 [(set (match_operand:QI 0 "register_operand" "")
5711 (unordered:QI (cc0) (const_int 0)))]
5712 "TARGET_68881 && !TUNE_68060"
5714 gcc_assert (m68k_last_compare_had_fp_operands);
5715 m68k_last_compare_had_fp_operands = 0;
5718 (define_insn "*sunordered_1"
5719 [(set (match_operand:QI 0 "register_operand" "=d")
5720 (unordered:QI (cc0) (const_int 0)))]
5721 "TARGET_68881 && !TUNE_68060"
5723 cc_status = cc_prev_status;
5727 (define_expand "suneq"
5728 [(set (match_operand:QI 0 "register_operand" "")
5729 (uneq:QI (cc0) (const_int 0)))]
5730 "TARGET_68881 && !TUNE_68060"
5732 gcc_assert (m68k_last_compare_had_fp_operands);
5733 m68k_last_compare_had_fp_operands = 0;
5736 (define_insn "*suneq_1"
5737 [(set (match_operand:QI 0 "register_operand" "=d")
5738 (uneq:QI (cc0) (const_int 0)))]
5739 "TARGET_68881 && !TUNE_68060"
5741 cc_status = cc_prev_status;
5745 (define_expand "sunge"
5746 [(set (match_operand:QI 0 "register_operand" "")
5747 (unge:QI (cc0) (const_int 0)))]
5748 "TARGET_68881 && !TUNE_68060"
5750 gcc_assert (m68k_last_compare_had_fp_operands);
5751 m68k_last_compare_had_fp_operands = 0;
5754 (define_insn "*sunge_1"
5755 [(set (match_operand:QI 0 "register_operand" "=d")
5756 (unge:QI (cc0) (const_int 0)))]
5757 "TARGET_68881 && !TUNE_68060"
5759 cc_status = cc_prev_status;
5763 (define_expand "sungt"
5764 [(set (match_operand:QI 0 "register_operand" "")
5765 (ungt:QI (cc0) (const_int 0)))]
5766 "TARGET_68881 && !TUNE_68060"
5768 gcc_assert (m68k_last_compare_had_fp_operands);
5769 m68k_last_compare_had_fp_operands = 0;
5772 (define_insn "*sungt_1"
5773 [(set (match_operand:QI 0 "register_operand" "=d")
5774 (ungt:QI (cc0) (const_int 0)))]
5775 "TARGET_68881 && !TUNE_68060"
5777 cc_status = cc_prev_status;
5781 (define_expand "sunle"
5782 [(set (match_operand:QI 0 "register_operand" "")
5783 (unle:QI (cc0) (const_int 0)))]
5784 "TARGET_68881 && !TUNE_68060"
5786 gcc_assert (m68k_last_compare_had_fp_operands);
5787 m68k_last_compare_had_fp_operands = 0;
5790 (define_insn "*sunle_1"
5791 [(set (match_operand:QI 0 "register_operand" "=d")
5792 (unle:QI (cc0) (const_int 0)))]
5793 "TARGET_68881 && !TUNE_68060"
5795 cc_status = cc_prev_status;
5799 (define_expand "sunlt"
5800 [(set (match_operand:QI 0 "register_operand" "")
5801 (unlt:QI (cc0) (const_int 0)))]
5802 "TARGET_68881 && !TUNE_68060"
5804 gcc_assert (m68k_last_compare_had_fp_operands);
5805 m68k_last_compare_had_fp_operands = 0;
5808 (define_insn "*sunlt_1"
5809 [(set (match_operand:QI 0 "register_operand" "=d")
5810 (unlt:QI (cc0) (const_int 0)))]
5811 "TARGET_68881 && !TUNE_68060"
5813 cc_status = cc_prev_status;
5817 (define_expand "sltgt"
5818 [(set (match_operand:QI 0 "register_operand" "")
5819 (ltgt:QI (cc0) (const_int 0)))]
5820 "TARGET_68881 && !TUNE_68060"
5822 gcc_assert (m68k_last_compare_had_fp_operands);
5823 m68k_last_compare_had_fp_operands = 0;
5826 (define_insn "*sltgt_1"
5827 [(set (match_operand:QI 0 "register_operand" "=d")
5828 (ltgt:QI (cc0) (const_int 0)))]
5829 "TARGET_68881 && !TUNE_68060"
5831 cc_status = cc_prev_status;
5835 (define_insn "*fsogt_1"
5836 [(set (match_operand:QI 0 "register_operand" "=d")
5837 (not:QI (unle:QI (cc0) (const_int 0))))]
5838 "TARGET_68881 && !TUNE_68060"
5840 cc_status = cc_prev_status;
5844 (define_insn "*fsoge_1"
5845 [(set (match_operand:QI 0 "register_operand" "=d")
5846 (not:QI (unlt:QI (cc0) (const_int 0))))]
5847 "TARGET_68881 && !TUNE_68060"
5849 cc_status = cc_prev_status;
5853 (define_insn "*fsolt_1"
5854 [(set (match_operand:QI 0 "register_operand" "=d")
5855 (not:QI (unge:QI (cc0) (const_int 0))))]
5856 "TARGET_68881 && !TUNE_68060"
5858 cc_status = cc_prev_status;
5862 (define_insn "*fsole_1"
5863 [(set (match_operand:QI 0 "register_operand" "=d")
5864 (not:QI (ungt:QI (cc0) (const_int 0))))]
5865 "TARGET_68881 && !TUNE_68060"
5867 cc_status = cc_prev_status;
5871 ;; Basic conditional jump instructions.
5873 (define_insn "beq0_di"
5875 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5877 (label_ref (match_operand 1 "" ","))
5879 (clobber (match_scratch:SI 2 "=d,d"))]
5883 if (which_alternative == 1)
5886 return "move%.l %0,%2\;or%.l %0,%2\;jbeq %l1";
5888 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
5890 if ((cc_prev_status.value1
5891 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5892 || (cc_prev_status.value2
5893 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5895 cc_status = cc_prev_status;
5896 return MOTOROLA ? "jbeq %l1" : "jeq %l1";
5898 if (GET_CODE (operands[0]) == REG)
5899 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5901 operands[3] = adjust_address (operands[0], SImode, 4);
5902 if (! ADDRESS_REG_P (operands[0]))
5904 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5906 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5909 return "or%.l %0,%2\;jbeq %l1";
5911 return "or%.l %0,%2\;jeq %l1";
5916 return "or%.l %3,%2\;jbeq %l1";
5918 return "or%.l %3,%2\;jeq %l1";
5922 return "move%.l %0,%2\;or%.l %3,%2\;jbeq %l1";
5924 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
5926 operands[4] = gen_label_rtx();
5927 if (TARGET_68020 || TARGET_COLDFIRE)
5930 output_asm_insn ("tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1", operands);
5932 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
5937 output_asm_insn ("cmp%.w #0,%0\;jbne %l4\;cmp%.w #0,%3\;jbeq %l1", operands);
5939 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
5941 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5942 CODE_LABEL_NUMBER (operands[4]));
5946 (define_insn "bne0_di"
5948 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5950 (label_ref (match_operand 1 "" ","))
5952 (clobber (match_scratch:SI 2 "=d,X"))]
5955 if ((cc_prev_status.value1
5956 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5957 || (cc_prev_status.value2
5958 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5960 cc_status = cc_prev_status;
5961 return MOTOROLA ? "jbne %l1" : "jne %l1";
5964 if (GET_CODE (operands[0]) == REG)
5965 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5967 operands[3] = adjust_address (operands[0], SImode, 4);
5968 if (!ADDRESS_REG_P (operands[0]))
5970 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5972 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5975 return "or%.l %0,%2\;jbne %l1";
5977 return "or%.l %0,%2\;jne %l1";
5982 return "or%.l %3,%2\;jbne %l1";
5984 return "or%.l %3,%2\;jne %l1";
5988 return "move%.l %0,%2\;or%.l %3,%2\;jbne %l1";
5990 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
5992 if (TARGET_68020 || TARGET_COLDFIRE)
5995 return "tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1";
5997 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
6002 return "cmp%.w #0,%0\;jbne %l1\;cmp%.w #0,%3\;jbne %l1";
6004 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
6008 (define_insn "bge0_di"
6010 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6012 (label_ref (match_operand 1 "" ""))
6016 if ((cc_prev_status.value1
6017 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6018 || (cc_prev_status.value2
6019 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6021 cc_status = cc_prev_status;
6022 if (cc_status.flags & CC_REVERSED)
6024 return MOTOROLA ? "jble %l1" : "jle %l1";
6028 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
6032 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6033 output_asm_insn("tst%.l %0", operands);
6036 /* On an address reg, cmpw may replace cmpl. */
6037 output_asm_insn("cmp%.w #0,%0", operands);
6039 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
6042 (define_insn "blt0_di"
6044 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6046 (label_ref (match_operand 1 "" ""))
6050 if ((cc_prev_status.value1
6051 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6052 || (cc_prev_status.value2
6053 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6055 cc_status = cc_prev_status;
6056 if (cc_status.flags & CC_REVERSED)
6058 return MOTOROLA ? "jbgt %l1" : "jgt %l1";
6062 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
6066 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6067 output_asm_insn("tst%.l %0", operands);
6070 /* On an address reg, cmpw may replace cmpl. */
6071 output_asm_insn("cmp%.w #0,%0", operands);
6074 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
6079 (if_then_else (eq (cc0)
6081 (label_ref (match_operand 0 "" ""))
6086 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
6088 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6093 (if_then_else (ne (cc0)
6095 (label_ref (match_operand 0 "" ""))
6100 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
6102 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6107 (if_then_else (gt (cc0)
6109 (label_ref (match_operand 0 "" ""))
6114 OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
6116 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
6121 (if_then_else (gtu (cc0)
6123 (label_ref (match_operand 0 "" ""))
6127 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
6132 (if_then_else (lt (cc0)
6134 (label_ref (match_operand 0 "" ""))
6139 OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
6141 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
6146 (if_then_else (ltu (cc0)
6148 (label_ref (match_operand 0 "" ""))
6152 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
6157 (if_then_else (ge (cc0)
6159 (label_ref (match_operand 0 "" ""))
6164 OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
6166 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
6171 (if_then_else (geu (cc0)
6173 (label_ref (match_operand 0 "" ""))
6177 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
6182 (if_then_else (le (cc0)
6184 (label_ref (match_operand 0 "" ""))
6189 OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
6191 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
6196 (if_then_else (leu (cc0)
6198 (label_ref (match_operand 0 "" ""))
6202 return MOTOROLA ? "jbls %l0" : "jls %l0";
6205 (define_insn "bordered"
6207 (if_then_else (ordered (cc0) (const_int 0))
6208 (label_ref (match_operand 0 "" ""))
6212 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6213 return MOTOROLA ? "fbor %l0" : "fjor %l0";
6216 (define_insn "bunordered"
6218 (if_then_else (unordered (cc0) (const_int 0))
6219 (label_ref (match_operand 0 "" ""))
6223 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6224 return MOTOROLA ? "fbun %l0" : "fjun %l0";
6227 (define_insn "buneq"
6229 (if_then_else (uneq (cc0) (const_int 0))
6230 (label_ref (match_operand 0 "" ""))
6234 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6235 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
6238 (define_insn "bunge"
6240 (if_then_else (unge (cc0) (const_int 0))
6241 (label_ref (match_operand 0 "" ""))
6245 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6246 return MOTOROLA ? "fbuge %l0" : "fjuge %l0";
6249 (define_insn "bungt"
6251 (if_then_else (ungt (cc0) (const_int 0))
6252 (label_ref (match_operand 0 "" ""))
6256 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6257 return MOTOROLA ? "fbugt %l0" : "fjugt %l0";
6260 (define_insn "bunle"
6262 (if_then_else (unle (cc0) (const_int 0))
6263 (label_ref (match_operand 0 "" ""))
6267 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6268 return MOTOROLA ? "fbule %l0" : "fjule %l0";
6271 (define_insn "bunlt"
6273 (if_then_else (unlt (cc0) (const_int 0))
6274 (label_ref (match_operand 0 "" ""))
6278 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6279 return MOTOROLA ? "fbult %l0" : "fjult %l0";
6282 (define_insn "bltgt"
6284 (if_then_else (ltgt (cc0) (const_int 0))
6285 (label_ref (match_operand 0 "" ""))
6289 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6290 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6293 ;; Negated conditional jump instructions.
6297 (if_then_else (eq (cc0)
6300 (label_ref (match_operand 0 "" ""))))]
6304 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
6306 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6311 (if_then_else (ne (cc0)
6314 (label_ref (match_operand 0 "" ""))))]
6318 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
6320 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6325 (if_then_else (gt (cc0)
6328 (label_ref (match_operand 0 "" ""))))]
6332 OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
6334 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
6339 (if_then_else (gtu (cc0)
6342 (label_ref (match_operand 0 "" ""))))]
6345 return MOTOROLA ? "jbls %l0" : "jls %l0";
6350 (if_then_else (lt (cc0)
6353 (label_ref (match_operand 0 "" ""))))]
6357 OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
6359 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
6364 (if_then_else (ltu (cc0)
6367 (label_ref (match_operand 0 "" ""))))]
6370 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
6375 (if_then_else (ge (cc0)
6378 (label_ref (match_operand 0 "" ""))))]
6382 OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
6384 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6389 (if_then_else (geu (cc0)
6392 (label_ref (match_operand 0 "" ""))))]
6395 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
6400 (if_then_else (le (cc0)
6403 (label_ref (match_operand 0 "" ""))))]
6407 OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
6409 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6414 (if_then_else (leu (cc0)
6417 (label_ref (match_operand 0 "" ""))))]
6420 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
6423 (define_insn "*bordered_rev"
6425 (if_then_else (ordered (cc0) (const_int 0))
6427 (label_ref (match_operand 0 "" ""))))]
6430 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6431 return MOTOROLA ? "fbun %l0" : "fjun %l0";
6434 (define_insn "*bunordered_rev"
6436 (if_then_else (unordered (cc0) (const_int 0))
6438 (label_ref (match_operand 0 "" ""))))]
6441 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6442 return MOTOROLA ? "fbor %l0" : "fjor %l0";
6445 (define_insn "*buneq_rev"
6447 (if_then_else (uneq (cc0) (const_int 0))
6449 (label_ref (match_operand 0 "" ""))))]
6452 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6453 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6456 (define_insn "*bunge_rev"
6458 (if_then_else (unge (cc0) (const_int 0))
6460 (label_ref (match_operand 0 "" ""))))]
6463 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6464 return MOTOROLA ? "fbolt %l0" : "fjolt %l0";
6467 (define_insn "*bungt_rev"
6469 (if_then_else (ungt (cc0) (const_int 0))
6471 (label_ref (match_operand 0 "" ""))))]
6474 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6475 return MOTOROLA ? "fbole %l0" : "fjole %l0";
6478 (define_insn "*bunle_rev"
6480 (if_then_else (unle (cc0) (const_int 0))
6482 (label_ref (match_operand 0 "" ""))))]
6485 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6486 return MOTOROLA ? "fbogt %l0" : "fjogt %l0";
6489 (define_insn "*bunlt_rev"
6491 (if_then_else (unlt (cc0) (const_int 0))
6493 (label_ref (match_operand 0 "" ""))))]
6496 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6497 return MOTOROLA ? "fboge %l0" : "fjoge %l0";
6500 (define_insn "*bltgt_rev"
6502 (if_then_else (ltgt (cc0) (const_int 0))
6504 (label_ref (match_operand 0 "" ""))))]
6507 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6508 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
6511 ;; Unconditional and other jump instructions
6514 (label_ref (match_operand 0 "" "")))]
6517 return MOTOROLA ? "jbra %l0" : "jra %l0";
6520 (define_expand "tablejump"
6521 [(parallel [(set (pc) (match_operand 0 "" ""))
6522 (use (label_ref (match_operand 1 "" "")))])]
6525 #ifdef CASE_VECTOR_PC_RELATIVE
6526 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6527 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6531 ;; Jump to variable address from dispatch table of absolute addresses.
6533 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6534 (use (label_ref (match_operand 1 "" "")))]
6537 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6540 ;; Jump to variable address from dispatch table of relative addresses.
6544 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6545 (use (label_ref (match_operand 1 "" "")))]
6548 #ifdef ASM_RETURN_CASE_JUMP
6549 ASM_RETURN_CASE_JUMP;
6551 if (TARGET_COLDFIRE)
6553 if (ADDRESS_REG_P (operands[0]))
6554 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6556 return "ext%.l %0\;jmp (2,pc,%0.l)";
6558 return "extl %0\;jmp pc@(2,%0:l)";
6561 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6565 ;; Decrement-and-branch insns.
6569 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6571 (label_ref (match_operand 1 "" ""))
6574 (plus:HI (match_dup 0)
6579 if (DATA_REG_P (operands[0]))
6580 return "dbra %0,%l1";
6581 if (GET_CODE (operands[0]) == MEM)
6583 "subq%.w #1,%0\;jbcc %l1" :
6584 "subqw #1,%0\;jcc %l1";
6586 "subq%.w #1,%0\;cmp%.w #-1,%0\;jbne %l1" :
6587 "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
6593 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6595 (label_ref (match_operand 1 "" ""))
6598 (plus:SI (match_dup 0)
6603 if (DATA_REG_P (operands[0]))
6605 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
6606 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6607 if (GET_CODE (operands[0]) == MEM)
6609 "subq%.l #1,%0\;jbcc %l1" :
6610 "subq%.l #1,%0\;jcc %l1";
6612 "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
6613 "subql #1,%0\;cmpl #-1,%0\;jne %l1";
6616 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6621 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6624 (label_ref (match_operand 1 "" ""))
6627 (plus:HI (match_dup 0)
6629 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6632 if (DATA_REG_P (operands[0]))
6633 return "dbra %0,%l1";
6634 if (GET_CODE (operands[0]) == MEM)
6636 "subq%.w #1,%0\;jbcc %l1" :
6637 "subq%.w #1,%0\;jcc %l1";
6639 "subq.w #1,%0\;cmp.w #-1,%0\;jbne %l1" :
6640 "subqw #1,%0\;cmpw #-1,%0\;jne %l1";
6643 (define_expand "decrement_and_branch_until_zero"
6644 [(parallel [(set (pc)
6646 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6649 (label_ref (match_operand 1 "" ""))
6652 (plus:SI (match_dup 0)
6660 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6663 (label_ref (match_operand 1 "" ""))
6666 (plus:SI (match_dup 0)
6668 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6671 if (DATA_REG_P (operands[0]))
6673 "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jbcc %l1" :
6674 "dbra %0,%l1\;clr%.w %0\;subql #1,%0\;jcc %l1";
6675 if (GET_CODE (operands[0]) == MEM)
6677 "subq%.l #1,%0\;jbcc %l1" :
6678 "subql #1,%0\;jcc %l1";
6680 "subq.l #1,%0\;cmp.l #-1,%0\;jbne %l1" :
6681 "subql #1,%0\;cmpl #-1,%0\;jne %l1";
6684 (define_expand "sibcall"
6685 [(call (match_operand:QI 0 "memory_operand" "")
6686 (match_operand:SI 1 "general_operand" ""))]
6689 operands[0] = m68k_legitimize_sibcall_address (operands[0]);
6692 (define_insn "*sibcall"
6693 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" ""))
6694 (match_operand:SI 1 "general_operand" ""))]
6695 "SIBLING_CALL_P (insn)"
6697 return output_sibcall (operands[0]);
6700 (define_expand "sibcall_value"
6701 [(set (match_operand 0 "" "")
6702 (call (match_operand:QI 1 "memory_operand" "")
6703 (match_operand:SI 2 "general_operand" "")))]
6706 operands[1] = m68k_legitimize_sibcall_address (operands[1]);
6709 (define_insn "*sibcall_value"
6710 [(set (match_operand 0 "" "=rf,rf")
6711 (call (mem:QI (match_operand:SI 1 "sibcall_operand" ""))
6712 (match_operand:SI 2 "general_operand" "")))]
6713 "SIBLING_CALL_P (insn)"
6715 operands[0] = operands[1];
6716 return output_sibcall (operands[0]);
6719 ;; Call subroutine with no return value.
6720 (define_expand "call"
6721 [(call (match_operand:QI 0 "memory_operand" "")
6722 (match_operand:SI 1 "general_operand" ""))]
6723 ;; Operand 1 not really used on the m68000.
6726 operands[0] = m68k_legitimize_call_address (operands[0]);
6729 (define_insn "*call"
6730 [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W"))
6731 (match_operand:SI 1 "general_operand" "g,g"))]
6732 ;; Operand 1 not really used on the m68000.
6733 "!SIBLING_CALL_P (insn)"
6735 return output_call (operands[0]);
6738 ;; Call subroutine, returning value in operand 0
6739 ;; (which must be a hard register).
6740 (define_expand "call_value"
6741 [(set (match_operand 0 "" "")
6742 (call (match_operand:QI 1 "memory_operand" "")
6743 (match_operand:SI 2 "general_operand" "")))]
6744 ;; Operand 2 not really used on the m68000.
6747 operands[1] = m68k_legitimize_call_address (operands[1]);
6750 (define_insn "*call_value"
6751 [(set (match_operand 0 "" "=rf,rf")
6752 (call (mem:QI (match_operand:SI 1 "call_operand" "a,W"))
6753 (match_operand:SI 2 "general_operand" "g,g")))]
6754 ;; Operand 2 not really used on the m68000.
6755 "!SIBLING_CALL_P (insn)"
6757 operands[0] = operands[1];
6758 return output_call (operands[0]);
6761 ;; Call subroutine returning any type.
6763 (define_expand "untyped_call"
6764 [(parallel [(call (match_operand 0 "" "")
6766 (match_operand 1 "" "")
6767 (match_operand 2 "" "")])]
6768 "NEEDS_UNTYPED_CALL"
6772 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6774 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6776 rtx set = XVECEXP (operands[2], 0, i);
6777 emit_move_insn (SET_DEST (set), SET_SRC (set));
6780 /* The optimizer does not know that the call sets the function value
6781 registers we stored in the result block. We avoid problems by
6782 claiming that all hard registers are used and clobbered at this
6784 emit_insn (gen_blockage ());
6789 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6790 ;; all of memory. This blocks insns from being moved across this point.
6792 (define_insn "blockage"
6793 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6802 (define_expand "prologue"
6806 m68k_expand_prologue ();
6810 (define_expand "epilogue"
6814 m68k_expand_epilogue (false);
6818 (define_expand "sibcall_epilogue"
6822 m68k_expand_epilogue (true);
6826 ;; Used for frameless functions which save no regs and allocate no locals.
6827 (define_expand "return"
6829 "m68k_use_return_insn ()"
6832 (define_insn "*return"
6836 if (m68k_interrupt_function_p (current_function_decl))
6838 else if (current_function_pops_args)
6840 operands[0] = GEN_INT (current_function_pops_args);
6847 (define_insn "*m68k_store_multiple"
6848 [(match_parallel 0 "" [(match_operand 1 "")])]
6849 "m68k_movem_pattern_p (operands[0], NULL, 0, true)"
6851 return m68k_output_movem (operands, operands[0], 0, true);
6854 (define_insn "*m68k_store_multiple_automod"
6855 [(match_parallel 0 ""
6856 [(set (match_operand:SI 1 "register_operand" "=a")
6857 (plus:SI (match_operand:SI 2 "register_operand" "1")
6858 (match_operand:SI 3 "const_int_operand")))])]
6859 "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)"
6861 return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true);
6864 (define_insn "*m68k_load_multiple"
6865 [(match_parallel 0 "" [(match_operand 1 "")])]
6866 "m68k_movem_pattern_p (operands[0], NULL, 0, false)"
6868 return m68k_output_movem (operands, operands[0], 0, false);
6871 (define_insn "*m68k_load_multiple_automod"
6872 [(match_parallel 0 ""
6873 [(set (match_operand:SI 1 "register_operand" "=a")
6874 (plus:SI (match_operand:SI 2 "register_operand" "1")
6875 (match_operand:SI 3 "const_int_operand")))])]
6876 "m68k_movem_pattern_p (operands[0], operands[1],
6877 INTVAL (operands[3]), false)"
6879 return m68k_output_movem (operands, operands[0],
6880 INTVAL (operands[3]), false);
6883 (define_expand "link"
6885 [(set (match_operand:SI 0 "register_operand")
6886 (plus:SI (reg:SI SP_REG) (const_int -4)))
6889 (set (reg:SI SP_REG)
6890 (plus:SI (reg:SI SP_REG)
6891 (match_operand:SI 1 "const_int_operand")))])]
6892 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
6894 operands[2] = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, -4));
6897 (define_insn "*link"
6898 [(set (match_operand:SI 0 "register_operand" "+r")
6899 (plus:SI (reg:SI SP_REG) (const_int -4)))
6900 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
6902 (set (reg:SI SP_REG)
6903 (plus:SI (reg:SI SP_REG)
6904 (match_operand:SI 1 "const_int_operand")))]
6905 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
6907 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
6909 return "link %0,%1";
6910 else if (INTVAL (operands[1]) >= -0x8000)
6911 return "link.w %0,%1";
6913 return "link.l %0,%1";
6916 (define_expand "unlink"
6918 [(set (match_operand:SI 0 "register_operand")
6920 (set (reg:SI SP_REG)
6921 (plus:SI (match_dup 0)
6925 operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0]));
6928 (define_insn "*unlink"
6929 [(set (match_operand:SI 0 "register_operand" "+r")
6930 (mem:SI (match_dup 0)))
6931 (set (reg:SI SP_REG)
6932 (plus:SI (match_dup 0)
6937 (define_insn "load_got"
6938 [(set (match_operand:SI 0 "register_operand" "=a")
6939 (unspec:SI [(const_int 0)] UNSPEC_GOT))]
6942 if (TARGET_ID_SHARED_LIBRARY)
6944 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
6945 return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0";
6949 if (TARGET_COLDFIRE)
6950 /* Load the full 32-bit PC-relative offset of
6951 _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to
6952 calculate the absolute value. The offset and "lea"
6953 operation word together occupy 6 bytes. */
6954 return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t"
6955 "lea (-6, %%pc, %0), %0");
6957 return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0";
6960 return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t"
6961 "lea %%pc@(0,%0:l),%0");
6964 (define_insn "indirect_jump"
6965 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6969 ;; This should not be used unless the add/sub insns can't be.
6972 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6973 (match_operand:QI 1 "address_operand" "p"))]
6976 /* Recognize an insn that refers to a table of offsets. Such an insn will
6977 need to refer to a label on the insn. So output one. Use the
6978 label-number of the table of offsets to generate this label. This code,
6979 and similar code above, assumes that there will be at most one reference
6981 if (GET_CODE (operands[1]) == PLUS
6982 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6983 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6985 rtx labelref = XEXP (operands[1], 1);
6987 asm_fprintf (asm_out_file, "\\t.set %LLI%d,.+2\\n",
6988 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6990 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
6991 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6993 return "lea %a1,%0";
6996 ;; This is the first machine-dependent peephole optimization.
6997 ;; It is useful when a floating value is returned from a function call
6998 ;; and then is moved into an FP register.
6999 ;; But it is mainly intended to test the support for these optimizations.
7002 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7003 (set (match_operand:DF 0 "register_operand" "=f")
7004 (match_operand:DF 1 "register_operand" "ad"))]
7005 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7008 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7009 output_asm_insn ("move%.l %1,%@", xoperands);
7010 output_asm_insn ("move%.l %1,%-", operands);
7011 return "fmove%.d %+,%0";
7014 ;; Optimize a stack-adjust followed by a push of an argument.
7015 ;; This is said to happen frequently with -msoft-float
7016 ;; when there are consecutive library calls.
7019 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7020 (match_operand:SI 0 "const_int_operand" "n")))
7021 (set (match_operand:SF 1 "push_operand" "=m")
7022 (match_operand:SF 2 "general_operand" "rmfF"))]
7023 "INTVAL (operands[0]) >= 4
7024 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7026 if (INTVAL (operands[0]) > 4)
7029 xoperands[0] = stack_pointer_rtx;
7030 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7031 if (INTVAL (xoperands[1]) <= 8)
7033 if (!TARGET_COLDFIRE)
7034 output_asm_insn ("addq%.w %1,%0", xoperands);
7036 output_asm_insn ("addq%.l %1,%0", xoperands);
7038 else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
7040 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7041 output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
7043 else if (INTVAL (xoperands[1]) <= 0x7FFF)
7046 output_asm_insn ("add%.w %1,%0", xoperands);
7048 output_asm_insn ("lea (%c1,%0),%0", xoperands);
7050 output_asm_insn ("lea %0@(%c1),%0", xoperands);
7053 output_asm_insn ("add%.l %1,%0", xoperands);
7055 if (FP_REG_P (operands[2]))
7056 return "fmove%.s %2,%@";
7057 return "move%.l %2,%@";
7060 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7063 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7064 (match_operand:SI 0 "const_int_operand" "n")))
7065 (set (match_operand:SI 1 "push_operand" "=m")
7066 (match_operand:SI 2 "general_operand" "g"))]
7067 "INTVAL (operands[0]) >= 4
7068 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7070 if (INTVAL (operands[0]) > 4)
7073 xoperands[0] = stack_pointer_rtx;
7074 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7075 if (INTVAL (xoperands[1]) <= 8)
7077 if (!TARGET_COLDFIRE)
7078 output_asm_insn ("addq%.w %1,%0", xoperands);
7080 output_asm_insn ("addq%.l %1,%0", xoperands);
7082 else if (TUNE_CPU32 && INTVAL (xoperands[1]) <= 16)
7084 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7085 output_asm_insn ("addq%.w #8,%0\;addq%.w %1,%0", xoperands);
7087 else if (INTVAL (xoperands[1]) <= 0x7FFF)
7090 output_asm_insn ("add%.w %1,%0", xoperands);
7092 output_asm_insn ("lea (%c1,%0),%0", xoperands);
7094 output_asm_insn ("lea %0@(%c1),%0", xoperands);
7097 output_asm_insn ("add%.l %1,%0", xoperands);
7099 if (operands[2] == const0_rtx)
7101 return "move%.l %2,%@";
7104 ;; Speed up pushing a single byte but leaving four bytes of space.
7107 [(set (mem:QI (pre_dec:SI (reg:SI SP_REG)))
7108 (match_operand:QI 1 "general_operand" "dami"))
7109 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (const_int 2)))]
7110 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7114 if (GET_CODE (operands[1]) == REG)
7115 return "move%.l %1,%-";
7117 xoperands[1] = operands[1];
7119 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7120 xoperands[3] = stack_pointer_rtx;
7121 if (!TARGET_COLDFIRE)
7122 output_asm_insn ("subq%.w #4,%3\;move%.b %1,%2", xoperands);
7124 output_asm_insn ("subq%.l #4,%3\;move%.b %1,%2", xoperands);
7129 [(set (match_operand:SI 0 "register_operand" "=d")
7131 (set (strict_low_part (subreg:HI (match_dup 0) 2))
7132 (match_operand:HI 1 "general_operand" "rmn"))]
7133 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7135 if (GET_CODE (operands[1]) == CONST_INT)
7137 if (operands[1] == const0_rtx
7138 && (DATA_REG_P (operands[0])
7139 || GET_CODE (operands[0]) == MEM)
7140 /* clr insns on 68000 read before writing. */
7141 && ((TARGET_68010 || TARGET_COLDFIRE)
7142 || !(GET_CODE (operands[0]) == MEM
7143 && MEM_VOLATILE_P (operands[0]))))
7146 return "move%.w %1,%0";
7154 ;; jCC label ; abnormal loop termination
7155 ;; dbra dN, loop ; normal loop termination
7163 ;; Which moves the jCC condition outside the inner loop for free.
7167 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7168 [(cc0) (const_int 0)])
7169 (label_ref (match_operand 2 "" ""))
7174 (ne (match_operand:HI 0 "register_operand" "")
7176 (label_ref (match_operand 1 "" ""))
7179 (plus:HI (match_dup 0)
7181 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7184 output_dbcc_and_branch (operands);
7189 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7190 [(cc0) (const_int 0)])
7191 (label_ref (match_operand 2 "" ""))
7196 (ne (match_operand:SI 0 "register_operand" "")
7198 (label_ref (match_operand 1 "" ""))
7201 (plus:SI (match_dup 0)
7203 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7206 output_dbcc_and_branch (operands);
7211 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7212 [(cc0) (const_int 0)])
7213 (label_ref (match_operand 2 "" ""))
7218 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7221 (label_ref (match_operand 1 "" ""))
7224 (plus:HI (match_dup 0)
7226 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7229 output_dbcc_and_branch (operands);
7234 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7235 [(cc0) (const_int 0)])
7236 (label_ref (match_operand 2 "" ""))
7241 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7244 (label_ref (match_operand 1 "" ""))
7247 (plus:SI (match_dup 0)
7249 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7252 output_dbcc_and_branch (operands);
7257 (define_insn "extendsfxf2"
7258 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7259 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7262 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7264 if (REGNO (operands[0]) == REGNO (operands[1]))
7266 /* Extending float to double in an fp-reg is a no-op.
7267 NOTICE_UPDATE_CC has already assumed that the
7268 cc will be set. So cancel what it did. */
7269 cc_status = cc_prev_status;
7272 return "f%$move%.x %1,%0";
7274 if (FP_REG_P (operands[0]))
7276 if (FP_REG_P (operands[1]))
7277 return "f%$move%.x %1,%0";
7278 else if (ADDRESS_REG_P (operands[1]))
7279 return "move%.l %1,%-\;f%$move%.s %+,%0";
7280 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7281 return output_move_const_single (operands);
7282 return "f%$move%.s %f1,%0";
7284 return "fmove%.x %f1,%0";
7288 (define_insn "extenddfxf2"
7289 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7291 (match_operand:DF 1 "general_operand" "f,rmE")))]
7294 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7296 if (REGNO (operands[0]) == REGNO (operands[1]))
7298 /* Extending float to double in an fp-reg is a no-op.
7299 NOTICE_UPDATE_CC has already assumed that the
7300 cc will be set. So cancel what it did. */
7301 cc_status = cc_prev_status;
7304 return "fmove%.x %1,%0";
7306 if (FP_REG_P (operands[0]))
7308 if (REG_P (operands[1]))
7311 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7312 output_asm_insn ("move%.l %1,%-", xoperands);
7313 output_asm_insn ("move%.l %1,%-", operands);
7314 return "f%&move%.d %+,%0";
7316 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7317 return output_move_const_double (operands);
7318 return "f%&move%.d %f1,%0";
7320 return "fmove%.x %f1,%0";
7323 (define_insn "truncxfdf2"
7324 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7326 (match_operand:XF 1 "general_operand" "f,f")))]
7329 if (REG_P (operands[0]))
7331 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
7332 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7333 return "move%.l %+,%0";
7335 return "fmove%.d %f1,%0";
7338 (define_insn "truncxfsf2"
7339 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7341 (match_operand:XF 1 "general_operand" "f")))]
7345 (define_insn "sin<mode>2"
7346 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7348 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))]
7349 "TARGET_68881 && flag_unsafe_math_optimizations"
7351 if (FP_REG_P (operands[1]))
7352 return "fsin%.x %1,%0";
7354 return "fsin%.<FP:prec> %1,%0";
7357 (define_insn "cos<mode>2"
7358 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7360 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))]
7361 "TARGET_68881 && flag_unsafe_math_optimizations"
7363 if (FP_REG_P (operands[1]))
7364 return "fcos%.x %1,%0";
7366 return "fcos%.<FP:prec> %1,%0";
7370 [(trap_if (const_int -1) (const_int 7))]
7374 (define_insn "conditional_trap"
7375 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7376 [(cc0) (const_int 0)])
7377 (match_operand:SI 1 "const_int_operand" "I"))]
7378 "TARGET_68020 && ! flags_in_68881 ()"
7380 switch (GET_CODE (operands[0]))
7382 case EQ: return "trapeq";
7383 case NE: return "trapne";
7384 case GT: return "trapgt";
7385 case GTU: return "traphi";
7386 case LT: return "traplt";
7387 case LTU: return "trapcs";
7388 case GE: return "trapge";
7389 case GEU: return "trapcc";
7390 case LE: return "traple";
7391 case LEU: return "trapls";
7392 default: gcc_unreachable ();