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[gcc.git] / gcc / config / mcore / mcore.h
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #ifndef GCC_MCORE_H
22 #define GCC_MCORE_H
23
24 /* RBE: need to move these elsewhere. */
25 #undef LIKE_PPC_ABI
26 #define MCORE_STRUCT_ARGS
27 /* RBE: end of "move elsewhere". */
28
29 #include "hwint.h"
30
31 #ifndef HAVE_MACHINE_MODES
32 #include "machmode.h"
33 #endif
34
35 /* Run-time Target Specification. */
36 #define TARGET_MCORE
37
38 /* Get tree.c to declare a target-specific specialization of
39 merge_decl_attributes. */
40 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
41
42 /* Support the __declspec keyword by turning them into attributes.
43 We currently only support: dllexport and dllimport.
44 Note that the current way we do this may result in a collision with
45 predefined attributes later on. This can be solved by using one attribute,
46 say __declspec__, and passing args to it. The problem with that approach
47 is that args are not accumulated: each new appearance would clobber any
48 existing args. XXX- FIXME the definition below relies upon string
49 concatenation, which is non-portable. */
50 #define CPP_PREDEFINES \
51 "-D__mcore__ -D__MCORE__=1 -D__declspec(x)=__attribute__((x))" SUBTARGET_CPP_PREDEFINES
52
53 /* If -m4align is ever re-enabled then uncomment this line as well:
54 #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */
55
56 #undef CPP_SPEC
57 #define CPP_SPEC " \
58 %{mbig-endian: \
59 %{mlittle-endian:%echoose either big or little endian, not both} \
60 -D__MCOREBE__} \
61 %{m210: \
62 %{m340:%echoose either m340 or m210 not both} \
63 %{mlittle-endian:%ethe m210 does not have little endian support} \
64 -D__M210__} \
65 %{!mbig-endian: -D__MCORELE__} \
66 %{!m210: -D__M340__} \
67 "
68 /* If -m4align is ever re-enabled then add this line to the defintion of CPP_SPEC
69 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
70
71 /* We don't have a -lg library, so don't put it in the list. */
72 #undef LIB_SPEC
73 #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
74
75 #undef ASM_SPEC
76 #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}"
77
78 #undef LINK_SPEC
79 #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X"
80
81 /* Can only count on 16 bits of availability; change to long would affect
82 many architecture specific files (other architectures...). */
83 extern int target_flags;
84
85 #define HARDLIT_BIT (1 << 0) /* Build in-line literals using 2 insns */
86 #define ALIGN8_BIT (1 << 1) /* Max alignment goes to 8 instead of 4 */
87 #define DIV_BIT (1 << 2) /* Generate divide instructions */
88 #define RELAX_IMM_BIT (1 << 3) /* Arbitrary immediates in and, or, tst */
89 #define W_FIELD_BIT (1 << 4) /* Generate bit insv/extv using SImode */
90 #define OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary */
91 #define CGDATA_BIT (1 << 6) /* Generate callgraph data */
92 #define SLOW_BYTES_BIT (1 << 7) /* Slow byte access */
93 #define LITTLE_END_BIT (1 << 8) /* Generate little endian code */
94 #define M340_BIT (1 << 9) /* Generate code for the m340 */
95
96 #define TARGET_DEFAULT \
97 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
98
99 #ifndef MULTILIB_DEFAULTS
100 #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" }
101 #endif
102
103 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
104 /* The ability to have 4 byte alignment is being suppressed for now.
105 If this ability is reenabled, you must enable the definition below
106 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
107 #if 0
108 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
109 #else
110 #define TARGET_8ALIGN 1
111 #endif
112 #define TARGET_DIV (target_flags & DIV_BIT)
113 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
114 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
115 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
116 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
117 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
118 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
119 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
120 #define TARGET_M340 (target_flags & M340_BIT)
121
122
123 #define TARGET_SWITCHES \
124 { {"hardlit", HARDLIT_BIT, \
125 N_("Inline constants if it can be done in 2 insns or less") }, \
126 {"no-hardlit", - HARDLIT_BIT, \
127 N_("inline constants if it only takes 1 instruction") }, \
128 {"4align", - ALIGN8_BIT, \
129 N_("Set maximum alignment to 4") }, \
130 {"8align", ALIGN8_BIT, \
131 N_("Set maximum alignment to 8") }, \
132 {"div", DIV_BIT, \
133 "" }, \
134 {"no-div", - DIV_BIT, \
135 N_("Do not use the divide instruction") }, \
136 {"relax-immediates", RELAX_IMM_BIT, \
137 "" }, \
138 {"no-relax-immediates", - RELAX_IMM_BIT, \
139 N_("Do not arbitary sized immediates in bit operations") }, \
140 {"wide-bitfields", W_FIELD_BIT, \
141 N_("Always treat bitfield as int-sized") }, \
142 {"no-wide-bitfields", - W_FIELD_BIT, \
143 "" }, \
144 {"4byte-functions", OVERALIGN_FUNC_BIT, \
145 N_("Force functions to be aligned to a 4 byte boundary") }, \
146 {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \
147 N_("Force functions to be aligned to a 2 byte boundary") }, \
148 {"callgraph-data", CGDATA_BIT, \
149 N_("Emit call graph information") }, \
150 {"no-callgraph-data", - CGDATA_BIT, \
151 "" }, \
152 {"slow-bytes", SLOW_BYTES_BIT, \
153 N_("Prefer word accesses over byte accesses") }, \
154 {"no-slow-bytes", - SLOW_BYTES_BIT, \
155 "" }, \
156 { "no-lsim", 0, "" }, \
157 {"little-endian", LITTLE_END_BIT, \
158 N_("Generate little endian code") }, \
159 {"big-endian", - LITTLE_END_BIT, \
160 "" }, \
161 {"210", - M340_BIT, \
162 "" }, \
163 {"340", M340_BIT, \
164 N_("Generate code for the M*Core M340") }, \
165 {"", TARGET_DEFAULT, \
166 "" } \
167 }
168
169 extern char * mcore_current_function_name;
170
171 /* Target specific options (as opposed to the switches above). */
172 extern const char * mcore_stack_increment_string;
173
174 #define TARGET_OPTIONS \
175 { \
176 {"stack-increment=", & mcore_stack_increment_string, \
177 N_("Maximum amount for a single stack increment operation")} \
178 }
179
180 /* The MCore ABI says that bitfields are unsigned by default. */
181 /* The EPOC C++ environment does not support exceptions. */
182 #define CC1_SPEC "-funsigned-bitfields %{!DIN_GCC:-fno-rtti} %{!DIN_GCC:-fno-exceptions}"
183
184 /* What options are we going to default to specific settings when
185 -O* happens; the user can subsequently override these settings.
186
187 Omitting the frame pointer is a very good idea on the MCore.
188 Scheduling isn't worth anything on the current MCore implementation. */
189 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
190 { \
191 if (LEVEL) \
192 { \
193 flag_no_function_cse = 1; \
194 flag_omit_frame_pointer = 1; \
195 \
196 if (LEVEL >= 2) \
197 { \
198 flag_caller_saves = 0; \
199 flag_schedule_insns = 0; \
200 flag_schedule_insns_after_reload = 0; \
201 } \
202 } \
203 if (SIZE) \
204 { \
205 target_flags &= ~ HARDLIT_BIT; \
206 } \
207 }
208
209 /* What options are we going to force to specific settings,
210 regardless of what the user thought he wanted.
211 We also use this for some post-processing of options. */
212 #define OVERRIDE_OPTIONS mcore_override_options ()
213
214 /* Target machine storage Layout. */
215
216 /* Define to use software floating point emulator for REAL_ARITHMETIC and
217 decimal <-> binary conversion. */
218 #define REAL_ARITHMETIC
219
220 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
221 if (GET_MODE_CLASS (MODE) == MODE_INT \
222 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
223 { \
224 (MODE) = SImode; \
225 (UNSIGNEDP) = 1; \
226 }
227
228 #define PROMOTE_FUNCTION_ARGS
229
230 #define PROMOTE_FUNCTION_RETURN
231
232 /* Define this if most significant bit is lowest numbered
233 in instructions that operate on numbered bit-fields. */
234 #define BITS_BIG_ENDIAN 0
235
236 /* Define this if most significant byte of a word is the lowest numbered. */
237 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
238
239 /* Define this if most significant word of a multiword number is the lowest
240 numbered. */
241 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
242
243 #define LIBGCC2_WORDS_BIG_ENDIAN 1
244 #ifdef __MCORELE__
245 #undef LIBGCC2_WORDS_BIG_ENDIAN
246 #define LIBGCC2_WORDS_BIG_ENDIAN 0
247 #endif
248
249 /* Number of bits in an addressable storage unit. */
250 #define BITS_PER_UNIT 8
251
252 /* Width in bits of a "word", which is the contents of a machine register.
253 Note that this is not necessarily the width of data type `int';
254 if using 16-bit ints on a 68000, this would still be 32.
255 But on a machine with 16-bit registers, this would be 16. */
256 #define BITS_PER_WORD 32
257 #define MAX_BITS_PER_WORD 32
258
259 /* Width of a word, in units (bytes). */
260 #define UNITS_PER_WORD 4
261
262 /* Width in bits of a pointer.
263 See also the macro `Pmode' defined below. */
264 #define POINTER_SIZE 32
265
266 /* A C expression for the size in bits of the type `long long' on the
267 target machine. If you don't define this, the default is two
268 words. */
269 #define LONG_LONG_TYPE_SIZE 64
270
271 /* the size of the boolean type -- in C++; */
272 #define BOOL_TYPE_SIZE 8
273
274 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
275 #define PARM_BOUNDARY 32
276
277 /* Doubles must be alogned to an 8 byte boundary. */
278 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
279 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
280 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
281
282 /* Boundary (in *bits*) on which stack pointer should be aligned. */
283 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
284
285 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
286 extern int mcore_stack_increment;
287 #define STACK_UNITS_MAXSTEP 4096
288
289 /* Allocation boundary (in *bits*) for the code of a function. */
290 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
291
292 /* Alignment of field after `int : 0' in a structure. */
293 #define EMPTY_FIELD_BOUNDARY 32
294
295 /* No data type wants to be aligned rounder than this. */
296 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
297
298 /* The best alignment to use in cases where we have a choice. */
299 #define FASTEST_ALIGNMENT 32
300
301 /* Every structures size must be a multiple of 8 bits. */
302 #define STRUCTURE_SIZE_BOUNDARY 8
303
304 /* Look at the fundamental type that is used for a bitfield and use
305 that to impose alignment on the enclosing structure.
306 struct s {int a:8}; should have same alignment as "int", not "char". */
307 #define PCC_BITFIELD_TYPE_MATTERS 1
308
309 /* Largest integer machine mode for structures. If undefined, the default
310 is GET_MODE_SIZE(DImode). */
311 #define MAX_FIXED_MODE_SIZE 32
312
313 /* Make strings word-aligned so strcpy from constants will be faster. */
314 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
315 ((TREE_CODE (EXP) == STRING_CST \
316 && (ALIGN) < FASTEST_ALIGNMENT) \
317 ? FASTEST_ALIGNMENT : (ALIGN))
318
319 /* Make arrays of chars word-aligned for the same reasons. */
320 #define DATA_ALIGNMENT(TYPE, ALIGN) \
321 (TREE_CODE (TYPE) == ARRAY_TYPE \
322 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
323 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
324
325 /* Set this nonzero if move instructions will actually fail to work
326 when given unaligned data. */
327 #define STRICT_ALIGNMENT 1
328
329 /* Standard register usage. */
330
331 /* Register allocation for our first guess
332
333 r0 stack pointer
334 r1 scratch, target reg for xtrb?
335 r2-r7 arguments.
336 r8-r14 call saved
337 r15 link register
338 ap arg pointer (doesn't really exist, always eliminated)
339 c c bit
340 fp frame pointer (doesn't really exist, always eliminated)
341 x19 two control registers */
342
343 /* Number of actual hardware registers.
344 The hardware registers are assigned numbers for the compiler
345 from 0 to just below FIRST_PSEUDO_REGISTER.
346 All registers that the compiler knows about must be given numbers,
347 even those that are not normally considered general registers.
348
349 MCore has 16 integer registers and 2 control registers + the arg
350 pointer. */
351
352 #define FIRST_PSEUDO_REGISTER 20
353
354 #define R1_REG 1 /* where literals are forced */
355 #define LK_REG 15 /* overloaded on general register */
356 #define AP_REG 16 /* fake arg pointer register */
357 /* RBE: mcore.md depends on CC_REG being set to 17 */
358 #define CC_REG 17 /* cant name it C_REG */
359 #define FP_REG 18 /* fake frame pointer register */
360
361 /* Specify the registers used for certain standard purposes.
362 The values of these macros are register numbers. */
363
364
365 #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */
366 #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */
367 #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */
368
369 /* The assembler's names for the registers. RFP need not always be used as
370 the Real framepointer; it can also be used as a normal general register.
371 Note that the name `fp' is horribly misleading since `fp' is in fact only
372 the argument-and-return-context pointer. */
373 #define REGISTER_NAMES \
374 { \
375 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
376 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
377 "apvirtual", "c", "fpvirtual", "x19" \
378 }
379
380 /* 1 for registers that have pervasive standard uses
381 and are not available for the register allocator. */
382 #define FIXED_REGISTERS \
383 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
384 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
385
386 /* 1 for registers not available across function calls.
387 These must include the FIXED_REGISTERS and also any
388 registers that can be used without being saved.
389 The latter must include the registers where values are returned
390 and the register where structure-value addresses are passed.
391 Aside from that, you can include as many other registers as you like. */
392
393 /* RBE: r15 {link register} not available across calls,
394 * But we don't mark it that way here... */
395 #define CALL_USED_REGISTERS \
396 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
397 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
398
399 /* The order in which register should be allocated. */
400 #define REG_ALLOC_ORDER \
401 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \
402 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
403
404 /* Return number of consecutive hard regs needed starting at reg REGNO
405 to hold something of mode MODE.
406 This is ordinarily the length in words of a value of mode MODE
407 but can be less for certain modes in special long registers.
408
409 On the MCore regs are UNITS_PER_WORD bits wide; */
410 #define HARD_REGNO_NREGS(REGNO, MODE) \
411 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
412
413 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
414 We may keep double values in even registers. */
415 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
416 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
417
418 /* Value is 1 if it is a good idea to tie two pseudo registers
419 when one has mode MODE1 and one has mode MODE2.
420 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
421 for any hard reg, then this must be 0 for correct output. */
422 #define MODES_TIEABLE_P(MODE1, MODE2) \
423 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
424
425 /* Value should be nonzero if functions must have frame pointers.
426 Zero means the frame pointer need not be set up (and parms may be accessed
427 via the stack pointer) in functions that seem suitable. */
428 #define FRAME_POINTER_REQUIRED 0
429
430 /* Definitions for register eliminations.
431
432 We have two registers that can be eliminated on the MCore. First, the
433 frame pointer register can often be eliminated in favor of the stack
434 pointer register. Secondly, the argument pointer register can always be
435 eliminated; it is replaced with either the stack or frame pointer. */
436
437 /* Base register for access to arguments of the function. */
438 #define ARG_POINTER_REGNUM 16
439
440 /* Register in which the static-chain is passed to a function. */
441 #define STATIC_CHAIN_REGNUM 1
442
443 /* This is an array of structures. Each structure initializes one pair
444 of eliminable registers. The "from" register number is given first,
445 followed by "to". Eliminations of the same "from" register are listed
446 in order of preference. */
447 #define ELIMINABLE_REGS \
448 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
449 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
450 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
451
452 /* Given FROM and TO register numbers, say whether this elimination
453 is allowed. */
454 #define CAN_ELIMINATE(FROM, TO) \
455 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
456
457 /* Define the offset between two registers, one to be eliminated, and the other
458 its replacement, at the start of a routine. */
459 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
460 OFFSET = mcore_initial_elimination_offset (FROM, TO)
461
462 /* Place that structure value return address is placed. */
463 #define STRUCT_VALUE 0
464
465 /* Define the classes of registers for register constraints in the
466 machine description. Also define ranges of constants.
467
468 One of the classes must always be named ALL_REGS and include all hard regs.
469 If there is more than one class, another class must be named NO_REGS
470 and contain no registers.
471
472 The name GENERAL_REGS must be the name of a class (or an alias for
473 another name such as ALL_REGS). This is the class of registers
474 that is allowed by "g" or "r" in a register constraint.
475 Also, registers outside this class are allocated only when
476 instructions express preferences for them.
477
478 The classes must be numbered in nondecreasing order; that is,
479 a larger-numbered class must never be contained completely
480 in a smaller-numbered class.
481
482 For any two classes, it is very desirable that there be another
483 class that represents their union. */
484
485 /* The MCore has only general registers. There are
486 also some special purpose registers: the T bit register, the
487 procedure Link and the Count Registers */
488 enum reg_class
489 {
490 NO_REGS,
491 ONLYR1_REGS,
492 LRW_REGS,
493 GENERAL_REGS,
494 C_REGS,
495 ALL_REGS,
496 LIM_REG_CLASSES
497 };
498
499 #define N_REG_CLASSES (int) LIM_REG_CLASSES
500
501 /* Give names of register classes as strings for dump file. */
502 #define REG_CLASS_NAMES \
503 { \
504 "NO_REGS", \
505 "ONLYR1_REGS", \
506 "LRW_REGS", \
507 "GENERAL_REGS", \
508 "C_REGS", \
509 "ALL_REGS", \
510 }
511
512 /* Define which registers fit in which classes.
513 This is an initializer for a vector of HARD_REG_SET
514 of length N_REG_CLASSES. */
515
516 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
517 #define REG_CLASS_CONTENTS \
518 { \
519 {0x000000}, /* NO_REGS */ \
520 {0x000002}, /* ONLYR1_REGS */ \
521 {0x007FFE}, /* LRW_REGS */ \
522 {0x01FFFF}, /* GENERAL_REGS */ \
523 {0x020000}, /* C_REGS */ \
524 {0x0FFFFF} /* ALL_REGS */ \
525 }
526
527 /* The same information, inverted:
528 Return the class number of the smallest class containing
529 reg number REGNO. This could be a conditional expression
530 or could index an array. */
531
532 extern int regno_reg_class[];
533 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
534
535 /* When defined, the compiler allows registers explicitly used in the
536 rtl to be used as spill registers but prevents the compiler from
537 extending the lifetime of these registers. */
538 #define SMALL_REGISTER_CLASSES 1
539
540 /* The class value for index registers, and the one for base regs. */
541 #define INDEX_REG_CLASS NO_REGS
542 #define BASE_REG_CLASS GENERAL_REGS
543
544 /* Get reg_class from a letter such as appears in the machine
545 description. */
546 extern enum reg_class reg_class_from_letter[];
547
548 #define REG_CLASS_FROM_LETTER(C) \
549 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C) - 'a'] : NO_REGS )
550
551 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
552 can be used to stand for particular ranges of immediate operands.
553 This macro defines what the ranges are.
554 C is the letter, and VALUE is a constant value.
555 Return 1 if VALUE is in the range specified by C.
556 I: loadable by movi (0..127)
557 J: arithmetic operand 1..32
558 K: shift operand 0..31
559 L: negative arithmetic operand -1..-32
560 M: powers of two, constants loadable by bgeni
561 N: powers of two minus 1, constants loadable by bmaski, including -1
562 O: allowed by cmov with two constants +/- 1 of each other
563 P: values we will generate 'inline' -- without an 'lrw'
564
565 Others defined for use after reload
566 Q: constant 1
567 R: a label
568 S: 0/1/2 cleared bits out of 32 [for bclri's]
569 T: 2 set bits out of 32 [for bseti's]
570 U: constant 0
571 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
572 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
573 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
574 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
575 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
576 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
577 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
578 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
579 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
580 CONST_OK_FOR_M(VALUE) || \
581 CONST_OK_FOR_N(VALUE) || \
582 CONST_OK_FOR_M((int)(VALUE) - 1) || \
583 CONST_OK_FOR_N((int)(VALUE) + 1))
584
585 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
586
587 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
588 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
589 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
590 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
591 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
592 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
593 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
594 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
595 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
596 : 0)
597
598 /* Similar, but for floating constants, and defining letters G and H.
599 Here VALUE is the CONST_DOUBLE rtx itself. */
600 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
601 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
602 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
603 : 0)
604
605 /* Letters in the range `Q' through `U' in a register constraint string
606 may be defined in a machine-dependent fashion to stand for arbitrary
607 operand types. */
608 #define EXTRA_CONSTRAINT(OP, C) \
609 ((C) == 'R' ? (GET_CODE (OP) == MEM \
610 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
611 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
612 && mcore_num_zeros (INTVAL (OP)) <= 2) \
613 : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \
614 && mcore_num_ones (INTVAL (OP)) == 2) \
615 : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \
616 && INTVAL(OP) == 1) \
617 : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \
618 && INTVAL(OP) == 0) \
619 : 0)
620
621 /* Given an rtx X being reloaded into a reg required to be
622 in class CLASS, return the class of reg to actually use.
623 In general this is just CLASS; but on some machines
624 in some cases it is preferable to use a more restrictive class. */
625 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
626
627 /* Return the register class of a scratch register needed to copy IN into
628 or out of a register in CLASS in MODE. If it can be done directly,
629 NO_REGS is returned. */
630 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
631
632 /* Return the maximum number of consecutive registers
633 needed to represent mode MODE in a register of class CLASS.
634
635 On MCore this is the size of MODE in words. */
636 #define CLASS_MAX_NREGS(CLASS, MODE) \
637 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
638
639 /* Stack layout; function entry, exit and calling. */
640
641 /* Define the number of register that can hold parameters.
642 These two macros are used only in other macro definitions below. */
643 #define NPARM_REGS 6
644 #define FIRST_PARM_REG 2
645 #define FIRST_RET_REG 2
646
647 /* Define this if pushing a word on the stack
648 makes the stack pointer a smaller address. */
649 #define STACK_GROWS_DOWNWARD
650
651 /* Define this if the nominal address of the stack frame
652 is at the high-address end of the local variables;
653 that is, each additional local variable allocated
654 goes at a more negative offset in the frame. */
655 /* We don't define this, because the MCore does not support
656 addresses with negative offsets. */
657 /* #define FRAME_GROWS_DOWNWARD */
658
659 /* Offset within stack frame to start allocating local variables at.
660 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
661 first local allocated. Otherwise, it is the offset to the BEGINNING
662 of the first local allocated. */
663 #define STARTING_FRAME_OFFSET 0
664
665 /* If defined, the maximum amount of space required for outgoing arguments
666 will be computed and placed into the variable
667 `current_function_outgoing_args_size'. No space will be pushed
668 onto the stack for each call; instead, the function prologue should
669 increase the stack frame size by this amount. */
670 #define ACCUMULATE_OUTGOING_ARGS 1
671
672 /* Offset of first parameter from the argument pointer register value. */
673 #define FIRST_PARM_OFFSET(FNDECL) 0
674
675 /* Value is the number of byte of arguments automatically
676 popped when returning from a subroutine call.
677 FUNTYPE is the data type of the function (as a tree),
678 or for a library call it is an identifier node for the subroutine name.
679 SIZE is the number of bytes of arguments passed on the stack.
680
681 On the MCore, the callee does not pop any of its arguments that were passed
682 on the stack. */
683 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
684
685 /* Define how to find the value returned by a function.
686 VALTYPE is the data type of the value (as a tree).
687 If the precise function being called is known, FUNC is its FUNCTION_DECL;
688 otherwise, FUNC is 0. */
689 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
690
691 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
692 we want to retain compatibility with older gcc versions. */
693 #define DEFAULT_PCC_STRUCT_RETURN 0
694
695 /* how we are going to return big values */
696 /*
697 * #define RETURN_IN_MEMORY(TYPE) \
698 * (TYPE_MODE (TYPE) == BLKmode \
699 * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
700 * && !(TYPE_MODE (TYPE) == SImode \
701 * || (TYPE_MODE (TYPE) == BLKmode \
702 * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \
703 * && int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
704 */
705
706
707 /* How many registers to use for struct return. */
708 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
709
710 /* Define how to find the value returned by a library function
711 assuming the value has mode MODE. */
712 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
713
714 /* 1 if N is a possible register number for a function value.
715 On the MCore, only r4 can return results. */
716 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
717
718 #define MUST_PASS_IN_STACK(MODE,TYPE) \
719 mcore_must_pass_on_stack (MODE, TYPE)
720
721 /* 1 if N is a possible register number for function argument passing. */
722 #define FUNCTION_ARG_REGNO_P(REGNO) \
723 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
724
725 /* Define a data type for recording info about an argument list
726 during the scan of that argument list. This data type should
727 hold all necessary information about the function itself
728 and about the args processed so far, enough to enable macros
729 such as FUNCTION_ARG to determine where the next arg should go.
730
731 On MCore, this is a single integer, which is a number of words
732 of arguments scanned so far (including the invisible argument,
733 if any, which holds the structure-value-address).
734 Thus NARGREGS or more means all following args should go on the stack. */
735 #define CUMULATIVE_ARGS int
736
737 #define ROUND_ADVANCE(SIZE) \
738 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
739
740 /* Round a register number up to a proper boundary for an arg of mode
741 MODE.
742
743 We round to an even reg for things larger than a word. */
744 #define ROUND_REG(X, MODE) \
745 ((TARGET_8ALIGN \
746 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
747 ? ((X) + ((X) & 1)) : (X))
748
749
750 /* Initialize a variable CUM of type CUMULATIVE_ARGS
751 for a call to a function whose data type is FNTYPE.
752 For a library call, FNTYPE is 0.
753
754 On MCore, the offset always starts at 0: the first parm reg is always
755 the same reg. */
756 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
757 ((CUM) = 0)
758
759 /* Update the data in CUM to advance over an argument
760 of mode MODE and data type TYPE.
761 (TYPE is null for libcalls where that information may not be
762 available.) */
763 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
764 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
765 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
766
767 /* Define where to put the arguments to a function. */
768 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
769 mcore_function_arg (CUM, MODE, TYPE, NAMED)
770
771 /* A C expression that indicates when an argument must be passed by
772 reference. If nonzero for an argument, a copy of that argument is
773 made in memory and a pointer to the argument is passed instead of
774 the argument itself. The pointer is passed in whatever way is
775 appropriate for passing a pointer to that type. */
776 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
777 MUST_PASS_IN_STACK (MODE, TYPE)
778
779 /* For an arg passed partly in registers and partly in memory,
780 this is the number of registers used.
781 For args passed entirely in registers or entirely in memory, zero.
782 Any arg that starts in the first NPARM_REGS regs but won't entirely
783 fit in them needs partial registers on the MCore. */
784 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
785 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
786
787 /* Perform any needed actions needed for a function that is receiving a
788 variable number of arguments. */
789 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
790 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
791
792 /* Call the function profiler with a given profile label. */
793 #define FUNCTION_PROFILER(STREAM,LABELNO) \
794 { \
795 fprintf (STREAM, " trap 1\n"); \
796 fprintf (STREAM, " .align 2\n"); \
797 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \
798 }
799
800 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
801 the stack pointer does not matter. The value is tested only in
802 functions that have frame pointers.
803 No definition is equivalent to always zero. */
804 #define EXIT_IGNORE_STACK 0
805
806 /* Output assembler code for a block containing the constant parts
807 of a trampoline, leaving space for the variable parts.
808
809 On the MCore, the trapoline looks like:
810 lrw r1, function
811 lrw r13, area
812 jmp r13
813 or r0, r0
814 .literals */
815 #define TRAMPOLINE_TEMPLATE(FILE) \
816 { \
817 fprintf ((FILE), " .short 0x7102\n"); \
818 fprintf ((FILE), " .short 0x7d02\n"); \
819 fprintf ((FILE), " .short 0x00cd\n"); \
820 fprintf ((FILE), " .short 0x1e00\n"); \
821 fprintf ((FILE), " .long 0\n"); \
822 fprintf ((FILE), " .long 0\n"); \
823 }
824
825 /* Length in units of the trampoline for entering a nested function. */
826 #define TRAMPOLINE_SIZE 12
827
828 /* Alignment required for a trampoline in units. */
829 #define TRAMPOLINE_ALIGN 4
830
831 /* Emit RTL insns to initialize the variable parts of a trampoline.
832 FNADDR is an RTX for the address of the function's pure code.
833 CXT is an RTX for the static chain value for the function. */
834 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
835 { \
836 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
837 (CXT)); \
838 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
839 (FNADDR)); \
840 }
841
842 /* Macros to check register numbers against specific register classes. */
843
844 /* These assume that REGNO is a hard or pseudo reg number.
845 They give nonzero only if REGNO is a hard reg of the suitable class
846 or a pseudo reg currently allocated to a suitable hard reg.
847 Since they use reg_renumber, they are safe only once reg_renumber
848 has been allocated, which happens in local-alloc.c. */
849 #define REGNO_OK_FOR_BASE_P(REGNO) \
850 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
851
852 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
853
854 /* Maximum number of registers that can appear in a valid memory
855 address. */
856 #define MAX_REGS_PER_ADDRESS 1
857
858 /* Recognize any constant value that is a valid address. */
859 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
860
861 /* Nonzero if the constant value X is a legitimate general operand.
862 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
863
864 On the MCore, allow anything but a double. */
865 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
866
867 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
868 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
869 and check its validity for a certain class.
870 We have two alternate definitions for each of them.
871 The usual definition accepts all pseudo regs; the other rejects
872 them unless they have been allocated suitable hard regs.
873 The symbol REG_OK_STRICT causes the latter definition to be used. */
874 #ifndef REG_OK_STRICT
875
876 /* Nonzero if X is a hard reg that can be used as a base reg
877 or if it is a pseudo reg. */
878 #define REG_OK_FOR_BASE_P(X) \
879 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
880
881 /* Nonzero if X is a hard reg that can be used as an index
882 or if it is a pseudo reg. */
883 #define REG_OK_FOR_INDEX_P(X) 0
884
885 #else
886
887 /* Nonzero if X is a hard reg that can be used as a base reg. */
888 #define REG_OK_FOR_BASE_P(X) \
889 REGNO_OK_FOR_BASE_P (REGNO (X))
890
891 /* Nonzero if X is a hard reg that can be used as an index. */
892 #define REG_OK_FOR_INDEX_P(X) 0
893
894 #endif
895 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
896 that is a valid memory address for an instruction.
897 The MODE argument is the machine mode for the MEM expression
898 that wants to use this address.
899
900 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
901 #define BASE_REGISTER_RTX_P(X) \
902 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
903
904 #define INDEX_REGISTER_RTX_P(X) \
905 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
906
907
908 /* Jump to LABEL if X is a valid address RTX. This must also take
909 REG_OK_STRICT into account when deciding about valid registers, but it uses
910 the above macros so we are in luck.
911
912 Allow REG
913 REG+disp
914
915 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
916 and for DI is 0..56 because we use two SI loads, etc. */
917 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
918 do \
919 { \
920 if (GET_CODE (OP) == CONST_INT) \
921 { \
922 if (GET_MODE_SIZE (MODE) >= 4 \
923 && (((unsigned)INTVAL (OP)) % 4) == 0 \
924 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
925 goto LABEL; \
926 if (GET_MODE_SIZE (MODE) == 2 \
927 && (((unsigned)INTVAL (OP)) % 2) == 0 \
928 && ((unsigned)INTVAL (OP)) <= 30) \
929 goto LABEL; \
930 if (GET_MODE_SIZE (MODE) == 1 \
931 && ((unsigned)INTVAL (OP)) <= 15) \
932 goto LABEL; \
933 } \
934 } \
935 while (0)
936
937 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
938 { \
939 if (BASE_REGISTER_RTX_P (X)) \
940 goto LABEL; \
941 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
942 { \
943 rtx xop0 = XEXP (X,0); \
944 rtx xop1 = XEXP (X,1); \
945 if (BASE_REGISTER_RTX_P (xop0)) \
946 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
947 if (BASE_REGISTER_RTX_P (xop1)) \
948 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
949 } \
950 }
951
952 /* Go to LABEL if ADDR (a legitimate address expression)
953 has an effect that depends on the machine mode it is used for. */
954 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
955 { \
956 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
957 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
958 goto LABEL; \
959 }
960
961 /* Specify the machine mode that this machine uses
962 for the index in the tablejump instruction. */
963 #define CASE_VECTOR_MODE SImode
964
965 /* Define this if the tablejump instruction expects the table
966 to contain offsets from the address of the table.
967 Do not define this if the table should contain absolute addresses. */
968 /* #define CASE_VECTOR_PC_RELATIVE */
969
970 /* Specify the tree operation to be used to convert reals to integers. */
971 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
972
973 /* This is the kind of divide that is easiest to do in the general case. */
974 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
975
976 /* 'char' is signed by default. */
977 #define DEFAULT_SIGNED_CHAR 0
978
979 /* The type of size_t unsigned int. */
980 #define SIZE_TYPE "unsigned int"
981
982 /* Don't cse the address of the function being compiled. */
983 #define NO_RECURSIVE_FUNCTION_CSE 1
984
985 /* Max number of bytes we can move from memory to memory
986 in one reasonably fast instruction. */
987 #define MOVE_MAX 4
988
989 /* Define if operations between registers always perform the operation
990 on the full register even if a narrower mode is specified. */
991 #define WORD_REGISTER_OPERATIONS
992
993 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
994 will either zero-extend or sign-extend. The value of this macro should
995 be the code that says which one of the two operations is implicitly
996 done, NIL if none. */
997 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
998
999 /* Nonzero if access to memory by bytes is slow and undesirable. */
1000 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
1001
1002 /* We assume that the store-condition-codes instructions store 0 for false
1003 and some other value for true. This is the value stored for true. */
1004 #define STORE_FLAG_VALUE 1
1005
1006 /* Immediate shift counts are truncated by the output routines (or was it
1007 the assembler?). Shift counts in a register are truncated by ARM. Note
1008 that the native compiler puts too large (> 32) immediate shift counts
1009 into a register and shifts by the register, letting the ARM decide what
1010 to do instead of doing that itself. */
1011 #define SHIFT_COUNT_TRUNCATED 1
1012
1013 /* All integers have the same format so truncation is easy. */
1014 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1015
1016 /* Define this if addresses of constant functions
1017 shouldn't be put through pseudo regs where they can be cse'd.
1018 Desirable on machines where ordinary constants are expensive
1019 but a CALL with constant address is cheap. */
1020 /* why is this defined??? -- dac */
1021 #define NO_FUNCTION_CSE 1
1022
1023 /* Chars and shorts should be passed as ints. */
1024 #define PROMOTE_PROTOTYPES 1
1025
1026 /* The machine modes of pointers and functions. */
1027 #define Pmode SImode
1028 #define FUNCTION_MODE Pmode
1029
1030 /* The relative costs of various types of constants. Note that cse.c defines
1031 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1032 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1033 case CONST_INT: \
1034 return mcore_const_costs (RTX, OUTER_CODE); \
1035 case CONST: \
1036 case LABEL_REF: \
1037 case SYMBOL_REF: \
1038 return 5; \
1039 case CONST_DOUBLE: \
1040 return 10;
1041
1042 /* provide the cost for an address calculation.
1043 All addressing modes cost the same on the MCore. */
1044 #define ADDRESS_COST(RTX) 1
1045
1046 /* Provide the cost of an rtl expression. */
1047 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1048 case AND: \
1049 return COSTS_N_INSNS (mcore_and_cost (X)); \
1050 case IOR: \
1051 return COSTS_N_INSNS (mcore_ior_cost (X)); \
1052 case DIV: \
1053 case UDIV: \
1054 case MOD: \
1055 case UMOD: \
1056 return COSTS_N_INSNS (100); \
1057 case FLOAT: \
1058 case FIX: \
1059 return 100;
1060
1061 /* Compute extra cost of moving data between one register class
1062 and another. All register moves are cheap. */
1063 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
1064
1065 #define WORD_REGISTER_OPERATIONS
1066
1067 /* Implicit library calls should use memcpy, not bcopy, etc. */
1068 #define TARGET_MEM_FUNCTIONS
1069
1070 /* Assembler output control. */
1071 #define ASM_COMMENT_START "\t//"
1072
1073 #define ASM_APP_ON "// inline asm begin\n"
1074 #define ASM_APP_OFF "// inline asm end\n"
1075
1076 #define FILE_ASM_OP "\t.file\n"
1077
1078 /* Switch to the text or data segment. */
1079 #define TEXT_SECTION_ASM_OP "\t.text"
1080 #define DATA_SECTION_ASM_OP "\t.data"
1081
1082 #undef EXTRA_SECTIONS
1083 #define EXTRA_SECTIONS in_ctors, in_dtors, SUBTARGET_EXTRA_SECTIONS
1084
1085 #undef EXTRA_SECTION_FUNCTIONS
1086 #define EXTRA_SECTION_FUNCTIONS \
1087 CTORS_SECTION_FUNCTION \
1088 DTORS_SECTION_FUNCTION \
1089 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
1090 SWITCH_SECTION_FUNCTION
1091
1092 #ifndef CTORS_SECTION_FUNCTION
1093 #define CTORS_SECTION_FUNCTION \
1094 void \
1095 ctors_section () \
1096 { \
1097 if (in_section != in_ctors) \
1098 { \
1099 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1100 in_section = in_ctors; \
1101 } \
1102 }
1103
1104 #define DTORS_SECTION_FUNCTION \
1105 void \
1106 dtors_section () \
1107 { \
1108 if (in_section != in_dtors) \
1109 { \
1110 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1111 in_section = in_dtors; \
1112 } \
1113 }
1114 #endif
1115
1116 /* Switch to SECTION (an `enum in_section').
1117
1118 ??? This facility should be provided by GCC proper.
1119 The problem is that we want to temporarily switch sections in
1120 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1121 afterwards. */
1122 #define SWITCH_SECTION_FUNCTION \
1123 void \
1124 switch_to_section (section, decl) \
1125 enum in_section section; \
1126 tree decl; \
1127 { \
1128 switch (section) \
1129 { \
1130 case in_text: text_section (); break; \
1131 case in_data: data_section (); break; \
1132 case in_named: named_section (decl, NULL, 0); break; \
1133 case in_ctors: ctors_section (); break; \
1134 case in_dtors: dtors_section (); break; \
1135 SUBTARGET_SWITCH_SECTIONS \
1136 default: abort (); break; \
1137 } \
1138 }
1139
1140 /* Switch into a generic section. */
1141 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
1142
1143 /* This is how to output an insn to push a register on the stack.
1144 It need not be very fast code. */
1145 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1146 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \
1147 reg_names[STACK_POINTER_REGNUM], \
1148 (STACK_BOUNDARY / BITS_PER_UNIT), \
1149 reg_names[REGNO], \
1150 reg_names[STACK_POINTER_REGNUM])
1151
1152 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1153 #define REG_PUSH_LENGTH 2
1154
1155 /* This is how to output an insn to pop a register from the stack. */
1156 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1157 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \
1158 reg_names[REGNO], \
1159 reg_names[STACK_POINTER_REGNUM], \
1160 reg_names[STACK_POINTER_REGNUM], \
1161 (STACK_BOUNDARY / BITS_PER_UNIT))
1162
1163
1164 /* DBX register number for a given compiler register number. */
1165 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1166
1167 /* Output a label definition. */
1168 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1169 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1170
1171 /* Output a reference to a label. */
1172 #undef ASM_OUTPUT_LABELREF
1173 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1174 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, MCORE_STRIP_NAME_ENCODING (NAME))
1175
1176
1177 /* This is how to output an assembler line
1178 that says to advance the location counter
1179 to a multiple of 2**LOG bytes. */
1180 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1181 if ((LOG) != 0) \
1182 fprintf (FILE, "\t.align\t%d\n", LOG)
1183
1184 #ifndef ASM_DECLARE_RESULT
1185 #define ASM_DECLARE_RESULT(FILE, RESULT)
1186 #endif
1187
1188 /* Strip export encoding from a function name. */
1189 #define MCORE_STRIP_NAME_ENCODING(SYM_NAME) \
1190 ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0))
1191
1192 /* Strip any text from SYM_NAME added by ENCODE_SECTION_INFO and store
1193 the result in VAR. */
1194 #undef STRIP_NAME_ENCODING
1195 #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \
1196 (VAR) = MCORE_STRIP_NAME_ENCODING (SYM_NAME)
1197
1198 #undef UNIQUE_SECTION
1199 #define UNIQUE_SECTION(DECL, RELOC) mcore_unique_section (DECL, RELOC)
1200
1201 #define REDO_SECTION_INFO_P(DECL) 1
1202
1203 #define MULTIPLE_SYMBOL_SPACES 1
1204
1205 #define SUPPORTS_ONE_ONLY 1
1206
1207 /* A pair of macros to output things for the callgraph data.
1208 VALUE means (to the tools that reads this info later):
1209 0 a call from src to dst
1210 1 the call is special (e.g. dst is "unknown" or "alloca")
1211 2 the call is special (e.g., the src is a table instead of routine)
1212
1213 Frame sizes are augmented with timestamps to help later tools
1214 differentiate between static entities with same names in different
1215 files. */
1216 extern long mcore_current_compilation_timestamp;
1217 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1218 do \
1219 { \
1220 if (mcore_current_compilation_timestamp == 0) \
1221 mcore_current_compilation_timestamp = time (0); \
1222 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \
1223 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1224 } \
1225 while (0)
1226
1227 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1228 do \
1229 { \
1230 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \
1231 (SRCNAME), (DSTNAME), (VALUE)); \
1232 } \
1233 while (0)
1234
1235 /* Output a globalising directive for a label. */
1236 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1237 (fprintf (STREAM, "\t.export\t"), \
1238 assemble_name (STREAM, NAME), \
1239 fputc ('\n',STREAM)) \
1240
1241 /* The prefix to add to user-visible assembler symbols. */
1242 #undef USER_LABEL_PREFIX
1243 #define USER_LABEL_PREFIX ""
1244
1245 /* Make an internal label into a string. */
1246 #undef ASM_GENERATE_INTERNAL_LABEL
1247 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1248 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM)
1249
1250 /* Output an internal label definition. */
1251 #undef ASM_OUTPUT_INTERNAL_LABEL
1252 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1253 fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1254
1255 /* Construct a private name. */
1256 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1257 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1258 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1259
1260 /* Jump tables must be 32 bit aligned. */
1261 #undef ASM_OUTPUT_CASE_LABEL
1262 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1263 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM);
1264
1265 /* Output a relative address. Not needed since jump tables are absolute
1266 but we must define it anyway. */
1267 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1268 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1269
1270 /* Output an element of a dispatch table. */
1271 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1272 fprintf (STREAM, "\t.long\t.L%d\n", VALUE)
1273
1274 /* Output various types of constants. */
1275
1276 /* This is how to output an assembler line defining a `double'. */
1277 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1278 do \
1279 { \
1280 char dstr[30]; \
1281 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1282 fprintf (FILE, "\t.double %s\n", dstr); \
1283 } \
1284 while (0)
1285
1286
1287 /* This is how to output an assembler line defining a `float' constant. */
1288 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1289 do \
1290 { \
1291 char dstr[30]; \
1292 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1293 fprintf (FILE, "\t.float %s\n", dstr); \
1294 } \
1295 while (0)
1296
1297 #define ASM_OUTPUT_INT(STREAM, EXP) \
1298 (fprintf (STREAM, "\t.long\t"), \
1299 output_addr_const (STREAM, (EXP)), \
1300 fputc ('\n', STREAM))
1301
1302 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1303 (fprintf (STREAM, "\t.short\t"), \
1304 output_addr_const (STREAM, (EXP)), \
1305 fputc ('\n', STREAM))
1306
1307 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1308 (fprintf (STREAM, "\t.byte\t"), \
1309 output_addr_const (STREAM, (EXP)), \
1310 fputc ('\n', STREAM))
1311
1312 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1313 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1314
1315 /* This is how to output an assembler line
1316 that says to advance the location counter by SIZE bytes. */
1317 #undef ASM_OUTPUT_SKIP
1318 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1319 fprintf (FILE, "\t.fill %d, 1\n", (SIZE))
1320
1321 /* This says how to output an assembler line
1322 to define a global common symbol, with alignment information. */
1323 /* XXX - for now we ignore the alignment. */
1324 #undef ASM_OUTPUT_ALIGNED_COMMON
1325 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1326 do \
1327 { \
1328 if (mcore_dllexport_name_p (NAME)) \
1329 MCORE_EXPORT_NAME (FILE, NAME) \
1330 if (! mcore_dllimport_name_p (NAME)) \
1331 { \
1332 fputs ("\t.comm\t", FILE); \
1333 assemble_name (FILE, NAME); \
1334 fprintf (FILE, ",%d\n", SIZE); \
1335 } \
1336 } \
1337 while (0)
1338
1339 /* This says how to output an assembler line
1340 to define an external symbol. */
1341 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1342 do \
1343 { \
1344 fputs ("\t.import\t", (FILE)); \
1345 assemble_name ((FILE), (NAME)); \
1346 fputs ("\n", (FILE)); \
1347 } \
1348 while (0)
1349
1350 #undef ASM_OUTPUT_EXTERNAL
1351 /* RBE: we undefined this and let gas do it's "undefined is imported"
1352 games. This is because when we use this, we get a marked
1353 reference through the call to assemble_name and this forces C++
1354 inlined member functions (or any inlined function) to be instantiated
1355 regardless of whether any callsites remain.
1356 This makes this aspect of the compiler non-ABI compliant. */
1357
1358 /* Similar, but for libcall. FUN is an rtx. */
1359 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1360 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1361 do \
1362 { \
1363 fprintf (FILE, "\t.import\t"); \
1364 assemble_name (FILE, XSTR (FUN, 0)); \
1365 fprintf (FILE, "\n"); \
1366 } \
1367 while (0)
1368
1369
1370 /* This says how to output an assembler line
1371 to define a local common symbol... */
1372 #undef ASM_OUTPUT_LOCAL
1373 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1374 (fputs ("\t.lcomm\t", FILE), \
1375 assemble_name (FILE, NAME), \
1376 fprintf (FILE, ",%d\n", SIZE))
1377
1378 /* ... and how to define a local common symbol whose alignment
1379 we wish to specify. ALIGN comes in as bits, we have to turn
1380 it into bytes. */
1381 #undef ASM_OUTPUT_ALIGNED_LOCAL
1382 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1383 do \
1384 { \
1385 fputs ("\t.bss\t", (FILE)); \
1386 assemble_name ((FILE), (NAME)); \
1387 fprintf ((FILE), ",%d,%d\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1388 } \
1389 while (0)
1390
1391 /* We must mark dll symbols specially. Definitions of dllexport'd objects
1392 install some info in the .drective (PE) or .exports (ELF) sections. */
1393 #undef ENCODE_SECTION_INFO
1394 #define ENCODE_SECTION_INFO(DECL) mcore_encode_section_info (DECL)
1395
1396 /* Print operand X (an rtx) in assembler syntax to file FILE.
1397 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1398 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1399 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1400
1401 /* Print a memory address as an operand to reference that memory location. */
1402 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1403
1404 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1405 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
1406
1407 /* This is to handle loads from the constant pool. */
1408 #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X)
1409
1410 /* This handles MCore dependent rtl simplifications. */
1411 #define MACHINE_DEPENDENT_SIMPLIFY(X,M,L,I,S) \
1412 mcore_dependent_simplify_rtx (X, M, L, I, S)
1413
1414 #define PREDICATE_CODES \
1415 { "mcore_arith_reg_operand", { REG, SUBREG }}, \
1416 { "mcore_general_movsrc_operand", { MEM, CONST_INT, REG, SUBREG }},\
1417 { "mcore_general_movdst_operand", { MEM, CONST_INT, REG, SUBREG }},\
1418 { "mcore_reload_operand", { MEM, REG, SUBREG }}, \
1419 { "mcore_arith_J_operand", { CONST_INT, REG, SUBREG }}, \
1420 { "mcore_arith_K_operand", { CONST_INT, REG, SUBREG }}, \
1421 { "mcore_arith_K_operand_not_0", { CONST_INT, REG, SUBREG }}, \
1422 { "mcore_arith_M_operand", { CONST_INT, REG, SUBREG }}, \
1423 { "mcore_arith_K_S_operand", { CONST_INT, REG, SUBREG }}, \
1424 { "mcore_arith_O_operand", { CONST_INT, REG, SUBREG }}, \
1425 { "mcore_arith_imm_operand", { CONST_INT, REG, SUBREG }}, \
1426 { "mcore_arith_any_imm_operand", { CONST_INT, REG, SUBREG }}, \
1427 { "mcore_literal_K_operand", { CONST_INT }}, \
1428 { "mcore_addsub_operand", { CONST_INT, REG, SUBREG }}, \
1429 { "mcore_compare_operand", { CONST_INT, REG, SUBREG }}, \
1430 { "mcore_load_multiple_operation", { PARALLEL }}, \
1431 { "mcore_store_multiple_operation", { PARALLEL }}, \
1432 { "mcore_call_address_operand", { REG, SUBREG, CONST_INT }}, \
1433
1434 #endif /* ! GCC_MCORE_H */