projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Backend for Motorola's MCore processors.
[gcc.git] / gcc / config / mcore / mcore.h
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #ifndef __MCORE__H
22 #define __MCORE__H
23
24 /* RBE: need to move these elsewhere. */
25 #undef LIKE_PPC_ABI
26 #define MCORE_STRUCT_ARGS
27 /* RBE: end of "move elsewhere". */
28
29 #include "hwint.h"
30
31 #ifndef HAVE_MACHINE_MODES
32 #include "machmode.h"
33 #endif
34
35 /* Run-time Target Specification. */
36 #define TARGET_MCORE
37
38 /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
39 is a valid machine specific attribute for DECL.
40 The attributes in ATTRIBUTES have previously been assigned to DECL. */
41 #undef VALID_MACHINE_DECL_ATTRIBUTE
42 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
43 mcore_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
44
45 #define MERGE_MACHINE_DECL_ATTRIBUTES(OLD, NEW) \
46 mcore_merge_machine_decl_attributes (OLD, NEW)
47
48 /* Support the __declspec keyword by turning them into attributes.
49 We currently only support: dllexport and dllimport.
50 Note that the current way we do this may result in a collision with
51 predefined attributes later on. This can be solved by using one attribute,
52 say __declspec__, and passing args to it. The problem with that approach
53 is that args are not accumulated: each new appearance would clobber any
54 existing args. XXX- FIXME the definition below relies upon string
55 concatenation, which is non-portable. */
56 #define CPP_PREDEFINES \
57 "-D__mcore__ -D__MCORE__=1 -D__declspec(x)=__attribute__((x))" SUBTARGET_CPP_PREDEFINES
58
59 /* If -m4align is ever re-enabled then uncomment this line as well:
60 #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */
61
62 #undef CPP_SPEC
63 #define CPP_SPEC " \
64 %{mbig-endian: \
65 %{mlittle-endian:%echoose either big or little endian, not both} \
66 -D__MCOREBE__} \
67 %{m210: \
68 %{m340:%echoose either m340 or m210 not both} \
69 %{mlittle-endian:%ethe m210 does not have little endian support} \
70 -D__M210__} \
71 %{!mbig-endian: -D__MCORELE__} \
72 %{!m210: -D__M340__} \
73 "
74 /* If -m4align is ever re-enabled then add this line to the defintion of CPP_SPEC
75 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
76
77 /* We don't have a -lg library, so don't put it in the list. */
78 #undef LIB_SPEC
79 #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
80
81 #undef ASM_SPEC
82 #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}"
83
84 #undef LINK_SPEC
85 #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X"
86
87 /* Can only count on 16 bits of availability; change to long would affect
88 many architecture specific files (other architectures...). */
89 extern int target_flags;
90
91 #define HARDLIT_BIT (1 << 0) /* Build in-line literals using 2 insns */
92 #define ALIGN8_BIT (1 << 1) /* Max alignment goes to 8 instead of 4 */
93 #define DIV_BIT (1 << 2) /* Generate divide instructions */
94 #define RELAX_IMM_BIT (1 << 3) /* Arbitrary immediates in and, or, tst */
95 #define W_FIELD_BIT (1 << 4) /* Generate bit insv/extv using SImode */
96 #define OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary */
97 #define CGDATA_BIT (1 << 6) /* Generate callgraph data */
98 #define SLOW_BYTES_BIT (1 << 7) /* Slow byte access */
99 #define LITTLE_END_BIT (1 << 8) /* Generate little endian code */
100 #define M340_BIT (1 << 9) /* Generate code for the m340 */
101
102 #define TARGET_DEFAULT \
103 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
104
105 #ifndef MULTILIB_DEFAULTS
106 #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" }
107 #endif
108
109 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
110 /* The ability to have 4 byte alignment is being suppressed for now.
111 If this ability is reenabled, you must enable the definition below
112 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
113 #if 0
114 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
115 #else
116 #define TARGET_8ALIGN 1
117 #endif
118 #define TARGET_DIV (target_flags & DIV_BIT)
119 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
120 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
121 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
122 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
123 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
124 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
125 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
126 #define TARGET_M340 (target_flags & M340_BIT)
127
128
129 #define TARGET_SWITCHES \
130 { {"hardlit", HARDLIT_BIT, \
131 "Inline constants if it can be done in 2 insns or less" }, \
132 {"no-hardlit", - HARDLIT_BIT, \
133 "inline constants if it only takes 1 instruction" }, \
134 {"4align", - ALIGN8_BIT, \
135 "Set maximum alignment to 4" }, \
136 {"8align", ALIGN8_BIT, \
137 "Set maximum alignment to 8" }, \
138 {"div", DIV_BIT, \
139 "" }, \
140 {"no-div", - DIV_BIT, \
141 "Do not use the divide instruction" }, \
142 {"relax-immediates", RELAX_IMM_BIT, \
143 "" }, \
144 {"no-relax-immediates", - RELAX_IMM_BIT, \
145 "Do not arbitary sized immediates in bit operations" }, \
146 {"wide-bitfields", W_FIELD_BIT, \
147 "Always treat bitfield as int-sized" }, \
148 {"no-wide-bitfields", - W_FIELD_BIT, \
149 "" }, \
150 {"4byte-functions", OVERALIGN_FUNC_BIT, \
151 "Force functions to be aligned to a 4 byte boundary" }, \
152 {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \
153 "Force functions to be aligned to a 2 byte boundary" }, \
154 {"callgraph-data", CGDATA_BIT, \
155 "Emit call graph information" }, \
156 {"no-callgraph-data", - CGDATA_BIT, \
157 "" }, \
158 {"slow-bytes", SLOW_BYTES_BIT, \
159 "Prefer word accesses over byte accesses" }, \
160 {"no-slow-bytes", - SLOW_BYTES_BIT, \
161 "" }, \
162 { "no-lsim", 0, "" }, \
163 {"little-endian", LITTLE_END_BIT, \
164 "Generate little endian code" }, \
165 {"big-endian", - LITTLE_END_BIT, \
166 "" }, \
167 {"210", - M340_BIT, \
168 "" }, \
169 {"340", M340_BIT, \
170 "Generate code for the M*Core M340" }, \
171 {"", TARGET_DEFAULT, \
172 "" } \
173 }
174
175 extern char * mcore_current_function_name;
176
177 /* Target specific options (as opposed to the switches above). */
178 extern const char * mcore_stack_increment_string;
179
180 #define TARGET_OPTIONS \
181 { \
182 {"stack-increment=", & mcore_stack_increment_string, \
183 "Maximum amount for a single stack increment operation"} \
184 }
185
186 /* The MCore ABI says that bitfields are unsigned by default. */
187 /* The EPOC C++ environment does not support exceptions. */
188 #define CC1_SPEC "-funsigned-bitfields %{!DIN_GCC:-fno-rtti} %{!DIN_GCC:-fno-exceptions}"
189
190 /* What options are we going to default to specific settings when
191 -O* happens; the user can subsequently override these settings.
192
193 Omitting the frame pointer is a very good idea on the MCore.
194 Scheduling isn't worth anything on the current MCore implementation. */
195 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
196 { \
197 if (LEVEL) \
198 { \
199 flag_no_function_cse = 1; \
200 flag_omit_frame_pointer = 1; \
201 \
202 if (LEVEL >= 2) \
203 { \
204 flag_caller_saves = 0; \
205 flag_schedule_insns = 0; \
206 flag_schedule_insns_after_reload = 0; \
207 } \
208 } \
209 if (SIZE) \
210 { \
211 target_flags &= ~ HARDLIT_BIT; \
212 } \
213 }
214
215 /* What options are we going to force to specific settings,
216 regardless of what the user thought he wanted.
217 We also use this for some post-processing of options. */
218 #define OVERRIDE_OPTIONS mcore_override_options ()
219
220 /* Target machine storage Layout. */
221
222 /* Define to use software floating point emulator for REAL_ARITHMETIC and
223 decimal <-> binary conversion. */
224 #define REAL_ARITHMETIC
225
226 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
227 if (GET_MODE_CLASS (MODE) == MODE_INT \
228 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
229 { \
230 (MODE) = SImode; \
231 (UNSIGNEDP) = 1; \
232 }
233
234 #define PROMOTE_FUNCTION_ARGS
235
236 #define PROMOTE_FUNCTION_RETURN
237
238 /* Define this if most significant bit is lowest numbered
239 in instructions that operate on numbered bit-fields. */
240 #define BITS_BIG_ENDIAN 0
241
242 /* Define this if most significant byte of a word is the lowest numbered. */
243 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
244
245 /* Define this if most significant word of a multiword number is the lowest
246 numbered. */
247 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
248
249 #define LIBGCC2_WORDS_BIG_ENDIAN 1
250 #ifdef __MCORELE__
251 #undef LIBGCC2_WORDS_BIG_ENDIAN
252 #define LIBGCC2_WORDS_BIG_ENDIAN 0
253 #endif
254
255 /* Number of bits in an addressable storage unit. */
256 #define BITS_PER_UNIT 8
257
258 /* Width in bits of a "word", which is the contents of a machine register.
259 Note that this is not necessarily the width of data type `int';
260 if using 16-bit ints on a 68000, this would still be 32.
261 But on a machine with 16-bit registers, this would be 16. */
262 #define BITS_PER_WORD 32
263 #define MAX_BITS_PER_WORD 32
264
265 /* Width of a word, in units (bytes). */
266 #define UNITS_PER_WORD 4
267
268 /* Width in bits of a pointer.
269 See also the macro `Pmode' defined below. */
270 #define POINTER_SIZE 32
271
272 /* A C expression for the size in bits of the type `long long' on the
273 target machine. If you don't define this, the default is two
274 words. */
275 #define LONG_LONG_TYPE_SIZE 64
276
277 /* the size of the boolean type -- in C++; */
278 #define BOOL_TYPE_SIZE 8
279
280 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
281 #define PARM_BOUNDARY 32
282
283 /* Doubles must be alogned to an 8 byte boundary. */
284 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
285 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
286 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
287
288 /* Boundary (in *bits*) on which stack pointer should be aligned. */
289 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
290
291 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
292 extern int mcore_stack_increment;
293 #define STACK_UNITS_MAXSTEP 4096
294
295 /* Allocation boundary (in *bits*) for the code of a function. */
296 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
297
298 /* Alignment of field after `int : 0' in a structure. */
299 #define EMPTY_FIELD_BOUNDARY 32
300
301 /* No data type wants to be aligned rounder than this. */
302 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
303
304 /* The best alignment to use in cases where we have a choice. */
305 #define FASTEST_ALIGNMENT 32
306
307 /* Every structures size must be a multiple of 8 bits. */
308 #define STRUCTURE_SIZE_BOUNDARY 8
309
310 /* Look at the fundamental type that is used for a bitfield and use
311 that to impose alignment on the enclosing structure.
312 struct s {int a:8}; should have same alignment as "int", not "char". */
313 #define PCC_BITFIELD_TYPE_MATTERS 1
314
315 /* Largest integer machine mode for structures. If undefined, the default
316 is GET_MODE_SIZE(DImode). */
317 #define MAX_FIXED_MODE_SIZE 32
318
319 /* Make strings word-aligned so strcpy from constants will be faster. */
320 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
321 ((TREE_CODE (EXP) == STRING_CST \
322 && (ALIGN) < FASTEST_ALIGNMENT) \
323 ? FASTEST_ALIGNMENT : (ALIGN))
324
325 /* Make arrays of chars word-aligned for the same reasons. */
326 #define DATA_ALIGNMENT(TYPE, ALIGN) \
327 (TREE_CODE (TYPE) == ARRAY_TYPE \
328 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
329 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
330
331 /* Set this nonzero if move instructions will actually fail to work
332 when given unaligned data. */
333 #define STRICT_ALIGNMENT 1
334
335 /* Standard register usage. */
336
337 /* Register allocation for our first guess
338
339 r0 stack pointer
340 r1 scratch, target reg for xtrb?
341 r2-r7 arguments.
342 r8-r14 call saved
343 r15 link register
344 ap arg pointer (doesn't really exist, always eliminated)
345 c c bit
346 fp frame pointer (doesn't really exist, always eliminated)
347 x19 two control registers */
348
349 /* Number of actual hardware registers.
350 The hardware registers are assigned numbers for the compiler
351 from 0 to just below FIRST_PSEUDO_REGISTER.
352 All registers that the compiler knows about must be given numbers,
353 even those that are not normally considered general registers.
354
355 MCore has 16 integer registers and 2 control registers + the arg
356 pointer. */
357
358 #define FIRST_PSEUDO_REGISTER 20
359
360 #define R1_REG 1 /* where literals are forced */
361 #define LK_REG 15 /* overloaded on general register */
362 #define AP_REG 16 /* fake arg pointer register */
363 /* RBE: mcore.md depends on CC_REG being set to 17 */
364 #define CC_REG 17 /* cant name it C_REG */
365 #define FP_REG 18 /* fake frame pointer register */
366
367 /* Specify the registers used for certain standard purposes.
368 The values of these macros are register numbers. */
369
370
371 #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */
372 #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */
373 #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */
374
375 /* The assembler's names for the registers. RFP need not always be used as
376 the Real framepointer; it can also be used as a normal general register.
377 Note that the name `fp' is horribly misleading since `fp' is in fact only
378 the argument-and-return-context pointer. */
379 #define REGISTER_NAMES \
380 { \
381 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
382 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
383 "apvirtual", "c", "fpvirtual", "x19" \
384 }
385
386 /* 1 for registers that have pervasive standard uses
387 and are not available for the register allocator. */
388 #define FIXED_REGISTERS \
389 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
390 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
391
392 /* 1 for registers not available across function calls.
393 These must include the FIXED_REGISTERS and also any
394 registers that can be used without being saved.
395 The latter must include the registers where values are returned
396 and the register where structure-value addresses are passed.
397 Aside from that, you can include as many other registers as you like. */
398
399 /* RBE: r15 {link register} not available across calls,
400 * But we don't mark it that way here... */
401 #define CALL_USED_REGISTERS \
402 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
403 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
404
405 /* The order in which register should be allocated. */
406 #define REG_ALLOC_ORDER \
407 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \
408 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
409
410 /* Return number of consecutive hard regs needed starting at reg REGNO
411 to hold something of mode MODE.
412 This is ordinarily the length in words of a value of mode MODE
413 but can be less for certain modes in special long registers.
414
415 On the MCore regs are UNITS_PER_WORD bits wide; */
416 #define HARD_REGNO_NREGS(REGNO, MODE) \
417 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
418
419 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
420 We may keep double values in even registers. */
421 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
422 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
423
424 /* Value is 1 if it is a good idea to tie two pseudo registers
425 when one has mode MODE1 and one has mode MODE2.
426 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
427 for any hard reg, then this must be 0 for correct output. */
428 #define MODES_TIEABLE_P(MODE1, MODE2) \
429 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
430
431 /* Value should be nonzero if functions must have frame pointers.
432 Zero means the frame pointer need not be set up (and parms may be accessed
433 via the stack pointer) in functions that seem suitable. */
434 #define FRAME_POINTER_REQUIRED 0
435
436 /* Definitions for register eliminations.
437
438 We have two registers that can be eliminated on the MCore. First, the
439 frame pointer register can often be eliminated in favor of the stack
440 pointer register. Secondly, the argument pointer register can always be
441 eliminated; it is replaced with either the stack or frame pointer. */
442
443 /* Base register for access to arguments of the function. */
444 #define ARG_POINTER_REGNUM 16
445
446 /* Register in which the static-chain is passed to a function. */
447 #define STATIC_CHAIN_REGNUM 1
448
449 /* This is an array of structures. Each structure initializes one pair
450 of eliminable registers. The "from" register number is given first,
451 followed by "to". Eliminations of the same "from" register are listed
452 in order of preference. */
453 #define ELIMINABLE_REGS \
454 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
455 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
456 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
457
458 /* Given FROM and TO register numbers, say whether this elimination
459 is allowed. */
460 #define CAN_ELIMINATE(FROM, TO) \
461 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
462
463 /* Define the offset between two registers, one to be eliminated, and the other
464 its replacement, at the start of a routine. */
465 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
466 OFFSET = mcore_initial_elimination_offset (FROM, TO)
467
468 /* Place that structure value return address is placed. */
469 #define STRUCT_VALUE 0
470
471 /* Define the classes of registers for register constraints in the
472 machine description. Also define ranges of constants.
473
474 One of the classes must always be named ALL_REGS and include all hard regs.
475 If there is more than one class, another class must be named NO_REGS
476 and contain no registers.
477
478 The name GENERAL_REGS must be the name of a class (or an alias for
479 another name such as ALL_REGS). This is the class of registers
480 that is allowed by "g" or "r" in a register constraint.
481 Also, registers outside this class are allocated only when
482 instructions express preferences for them.
483
484 The classes must be numbered in nondecreasing order; that is,
485 a larger-numbered class must never be contained completely
486 in a smaller-numbered class.
487
488 For any two classes, it is very desirable that there be another
489 class that represents their union. */
490
491 /* The MCore has only general registers. There are
492 also some special purpose registers: the T bit register, the
493 procedure Link and the Count Registers */
494 enum reg_class
495 {
496 NO_REGS,
497 ONLYR1_REGS,
498 LRW_REGS,
499 GENERAL_REGS,
500 C_REGS,
501 ALL_REGS,
502 LIM_REG_CLASSES
503 };
504
505 #define N_REG_CLASSES (int) LIM_REG_CLASSES
506
507 /* Give names of register classes as strings for dump file. */
508 #define REG_CLASS_NAMES \
509 { \
510 "NO_REGS", \
511 "ONLYR1_REGS", \
512 "LRW_REGS", \
513 "GENERAL_REGS", \
514 "C_REGS", \
515 "ALL_REGS", \
516 }
517
518 /* Define which registers fit in which classes.
519 This is an initializer for a vector of HARD_REG_SET
520 of length N_REG_CLASSES. */
521
522 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
523 #define REG_CLASS_CONTENTS \
524 { \
525 {0x000000}, /* NO_REGS */ \
526 {0x000002}, /* ONLYR1_REGS */ \
527 {0x007FFE}, /* LRW_REGS */ \
528 {0x01FFFF}, /* GENERAL_REGS */ \
529 {0x020000}, /* C_REGS */ \
530 {0x0FFFFF} /* ALL_REGS */ \
531 }
532
533 /* The same information, inverted:
534 Return the class number of the smallest class containing
535 reg number REGNO. This could be a conditional expression
536 or could index an array. */
537
538 extern int regno_reg_class[];
539 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
540
541 /* When defined, the compiler allows registers explicitly used in the
542 rtl to be used as spill registers but prevents the compiler from
543 extending the lifetime of these registers. */
544 #define SMALL_REGISTER_CLASSES 1
545
546 /* The class value for index registers, and the one for base regs. */
547 #define INDEX_REG_CLASS NO_REGS
548 #define BASE_REG_CLASS GENERAL_REGS
549
550 /* Get reg_class from a letter such as appears in the machine
551 description. */
552 extern enum reg_class reg_class_from_letter[];
553
554 #define REG_CLASS_FROM_LETTER(C) \
555 ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C) - 'a'] : NO_REGS )
556
557 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
558 can be used to stand for particular ranges of immediate operands.
559 This macro defines what the ranges are.
560 C is the letter, and VALUE is a constant value.
561 Return 1 if VALUE is in the range specified by C.
562 I: loadable by movi (0..127)
563 J: arithmetic operand 1..32
564 K: shift operand 0..31
565 L: negative arithmetic operand -1..-32
566 M: powers of two, constants loadable by bgeni
567 N: powers of two minus 1, constants loadable by bmaski, including -1
568 O: allowed by cmov with two constants +/- 1 of each other
569 P: values we will generate 'inline' -- without an 'lrw'
570
571 Others defined for use after reload
572 Q: constant 1
573 R: a label
574 S: 0/1/2 cleared bits out of 32 [for bclri's]
575 T: 2 set bits out of 32 [for bseti's]
576 U: constant 0
577 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
578 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
579 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
580 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
581 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
582 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
583 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
584 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
585 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
586 CONST_OK_FOR_M(VALUE) || \
587 CONST_OK_FOR_N(VALUE) || \
588 CONST_OK_FOR_M((int)(VALUE) - 1) || \
589 CONST_OK_FOR_N((int)(VALUE) + 1))
590
591 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
592
593 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
594 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
595 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
596 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
597 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
598 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
599 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
600 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
601 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
602 : 0)
603
604 /* Similar, but for floating constants, and defining letters G and H.
605 Here VALUE is the CONST_DOUBLE rtx itself. */
606 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
607 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
608 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
609 : 0)
610
611 /* Letters in the range `Q' through `U' in a register constraint string
612 may be defined in a machine-dependent fashion to stand for arbitrary
613 operand types. */
614 #define EXTRA_CONSTRAINT(OP, C) \
615 ((C) == 'R' ? (GET_CODE (OP) == MEM \
616 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
617 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
618 && mcore_num_zeros (INTVAL (OP)) <= 2) \
619 : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \
620 && mcore_num_ones (INTVAL (OP)) == 2) \
621 : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \
622 && INTVAL(OP) == 1) \
623 : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \
624 && INTVAL(OP) == 0) \
625 : 0)
626
627 /* Given an rtx X being reloaded into a reg required to be
628 in class CLASS, return the class of reg to actually use.
629 In general this is just CLASS; but on some machines
630 in some cases it is preferable to use a more restrictive class. */
631 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
632
633 /* Return the register class of a scratch register needed to copy IN into
634 or out of a register in CLASS in MODE. If it can be done directly,
635 NO_REGS is returned. */
636 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
637
638 /* Return the maximum number of consecutive registers
639 needed to represent mode MODE in a register of class CLASS.
640
641 On MCore this is the size of MODE in words. */
642 #define CLASS_MAX_NREGS(CLASS, MODE) \
643 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
644
645 /* Stack layout; function entry, exit and calling. */
646
647 /* Define the number of register that can hold parameters.
648 These two macros are used only in other macro definitions below. */
649 #define NPARM_REGS 6
650 #define FIRST_PARM_REG 2
651 #define FIRST_RET_REG 2
652
653 /* Define this if pushing a word on the stack
654 makes the stack pointer a smaller address. */
655 #define STACK_GROWS_DOWNWARD
656
657 /* Define this if the nominal address of the stack frame
658 is at the high-address end of the local variables;
659 that is, each additional local variable allocated
660 goes at a more negative offset in the frame. */
661 /* We don't define this, because the MCore does not support
662 addresses with negative offsets. */
663 /* #define FRAME_GROWS_DOWNWARD */
664
665 /* Offset within stack frame to start allocating local variables at.
666 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
667 first local allocated. Otherwise, it is the offset to the BEGINNING
668 of the first local allocated. */
669 #define STARTING_FRAME_OFFSET 0
670
671 /* If defined, the maximum amount of space required for outgoing arguments
672 will be computed and placed into the variable
673 `current_function_outgoing_args_size'. No space will be pushed
674 onto the stack for each call; instead, the function prologue should
675 increase the stack frame size by this amount. */
676 #define ACCUMULATE_OUTGOING_ARGS
677
678 /* Offset of first parameter from the argument pointer register value. */
679 #define FIRST_PARM_OFFSET(FNDECL) 0
680
681 /* Value is the number of byte of arguments automatically
682 popped when returning from a subroutine call.
683 FUNTYPE is the data type of the function (as a tree),
684 or for a library call it is an identifier node for the subroutine name.
685 SIZE is the number of bytes of arguments passed on the stack.
686
687 On the MCore, the callee does not pop any of its arguments that were passed
688 on the stack. */
689 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
690
691 /* Define how to find the value returned by a function.
692 VALTYPE is the data type of the value (as a tree).
693 If the precise function being called is known, FUNC is its FUNCTION_DECL;
694 otherwise, FUNC is 0. */
695 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
696
697 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
698 we want to retain compatibility with older gcc versions. */
699 #define DEFAULT_PCC_STRUCT_RETURN 0
700
701 /* how we are going to return big values */
702 /*
703 * #define RETURN_IN_MEMORY(TYPE) \
704 * (TYPE_MODE (TYPE) == BLKmode \
705 * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
706 * && !(TYPE_MODE (TYPE) == SImode \
707 * || (TYPE_MODE (TYPE) == BLKmode \
708 * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \
709 * && int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
710 */
711
712
713 /* How many registers to use for struct return. */
714 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
715
716 /* Define how to find the value returned by a library function
717 assuming the value has mode MODE. */
718 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
719
720 /* 1 if N is a possible register number for a function value.
721 On the MCore, only r4 can return results. */
722 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
723
724 #define MUST_PASS_IN_STACK(MODE,TYPE) \
725 mcore_must_pass_on_stack (MODE, TYPE)
726
727 /* 1 if N is a possible register number for function argument passing. */
728 #define FUNCTION_ARG_REGNO_P(REGNO) \
729 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
730
731 /* Define a data type for recording info about an argument list
732 during the scan of that argument list. This data type should
733 hold all necessary information about the function itself
734 and about the args processed so far, enough to enable macros
735 such as FUNCTION_ARG to determine where the next arg should go.
736
737 On MCore, this is a single integer, which is a number of words
738 of arguments scanned so far (including the invisible argument,
739 if any, which holds the structure-value-address).
740 Thus NARGREGS or more means all following args should go on the stack. */
741 #define CUMULATIVE_ARGS int
742
743 #define ROUND_ADVANCE(SIZE) \
744 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
745
746 /* Round a register number up to a proper boundary for an arg of mode
747 MODE.
748
749 We round to an even reg for things larger than a word. */
750 #define ROUND_REG(X, MODE) \
751 ((TARGET_8ALIGN \
752 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
753 ? ((X) + ((X) & 1)) : (X))
754
755
756 /* Initialize a variable CUM of type CUMULATIVE_ARGS
757 for a call to a function whose data type is FNTYPE.
758 For a library call, FNTYPE is 0.
759
760 On MCore, the offset always starts at 0: the first parm reg is always
761 the same reg. */
762 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
763 ((CUM) = 0)
764
765 /* Update the data in CUM to advance over an argument
766 of mode MODE and data type TYPE.
767 (TYPE is null for libcalls where that information may not be
768 available.) */
769 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
770 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
771 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
772
773 /* Define where to put the arguments to a function. */
774 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
775 mcore_function_arg (CUM, MODE, TYPE, NAMED)
776
777 /* A C expression that indicates when an argument must be passed by
778 reference. If nonzero for an argument, a copy of that argument is
779 made in memory and a pointer to the argument is passed instead of
780 the argument itself. The pointer is passed in whatever way is
781 appropriate for passing a pointer to that type. */
782 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
783 MUST_PASS_IN_STACK (MODE, TYPE)
784
785 /* For an arg passed partly in registers and partly in memory,
786 this is the number of registers used.
787 For args passed entirely in registers or entirely in memory, zero.
788 Any arg that starts in the first NPARM_REGS regs but won't entirely
789 fit in them needs partial registers on the MCore. */
790 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
791 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
792
793 /* Perform any needed actions needed for a function that is receiving a
794 variable number of arguments. */
795 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
796 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
797
798 /* Call the function profiler with a given profile label. */
799 #define FUNCTION_PROFILER(STREAM,LABELNO) \
800 { \
801 fprintf (STREAM, " trap 1\n"); \
802 fprintf (STREAM, " .align 2\n"); \
803 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \
804 }
805
806 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
807 the stack pointer does not matter. The value is tested only in
808 functions that have frame pointers.
809 No definition is equivalent to always zero. */
810 #define EXIT_IGNORE_STACK 0
811
812 /* Output assembler code for a block containing the constant parts
813 of a trampoline, leaving space for the variable parts.
814
815 On the MCore, the trapoline looks like:
816 lrw r1, function
817 lrw r13, area
818 jmp r13
819 or r0, r0
820 .literals */
821 #define TRAMPOLINE_TEMPLATE(FILE) \
822 { \
823 fprintf ((FILE), " .short 0x7102\n"); \
824 fprintf ((FILE), " .short 0x7d02\n"); \
825 fprintf ((FILE), " .short 0x00cd\n"); \
826 fprintf ((FILE), " .short 0x1e00\n"); \
827 fprintf ((FILE), " .long 0\n"); \
828 fprintf ((FILE), " .long 0\n"); \
829 }
830
831 /* Length in units of the trampoline for entering a nested function. */
832 #define TRAMPOLINE_SIZE 12
833
834 /* Alignment required for a trampoline in units. */
835 #define TRAMPOLINE_ALIGN 4
836
837 /* Emit RTL insns to initialize the variable parts of a trampoline.
838 FNADDR is an RTX for the address of the function's pure code.
839 CXT is an RTX for the static chain value for the function. */
840 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
841 { \
842 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
843 (CXT)); \
844 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
845 (FNADDR)); \
846 }
847
848 /* Macros to check register numbers against specific register classes. */
849
850 /* These assume that REGNO is a hard or pseudo reg number.
851 They give nonzero only if REGNO is a hard reg of the suitable class
852 or a pseudo reg currently allocated to a suitable hard reg.
853 Since they use reg_renumber, they are safe only once reg_renumber
854 has been allocated, which happens in local-alloc.c. */
855 #define REGNO_OK_FOR_BASE_P(REGNO) \
856 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
857
858 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
859
860 /* Maximum number of registers that can appear in a valid memory
861 address. */
862 #define MAX_REGS_PER_ADDRESS 1
863
864 /* Recognize any constant value that is a valid address. */
865 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
866
867 /* Nonzero if the constant value X is a legitimate general operand.
868 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
869
870 On the MCore, allow anything but a double. */
871 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
872
873 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
874 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
875 and check its validity for a certain class.
876 We have two alternate definitions for each of them.
877 The usual definition accepts all pseudo regs; the other rejects
878 them unless they have been allocated suitable hard regs.
879 The symbol REG_OK_STRICT causes the latter definition to be used. */
880 #ifndef REG_OK_STRICT
881
882 /* Nonzero if X is a hard reg that can be used as a base reg
883 or if it is a pseudo reg. */
884 #define REG_OK_FOR_BASE_P(X) \
885 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
886
887 /* Nonzero if X is a hard reg that can be used as an index
888 or if it is a pseudo reg. */
889 #define REG_OK_FOR_INDEX_P(X) 0
890
891 #else
892
893 /* Nonzero if X is a hard reg that can be used as a base reg. */
894 #define REG_OK_FOR_BASE_P(X) \
895 REGNO_OK_FOR_BASE_P (REGNO (X))
896
897 /* Nonzero if X is a hard reg that can be used as an index. */
898 #define REG_OK_FOR_INDEX_P(X) 0
899
900 #endif
901 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
902 that is a valid memory address for an instruction.
903 The MODE argument is the machine mode for the MEM expression
904 that wants to use this address.
905
906 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
907 #define BASE_REGISTER_RTX_P(X) \
908 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
909
910 #define INDEX_REGISTER_RTX_P(X) \
911 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
912
913
914 /* Jump to LABEL if X is a valid address RTX. This must also take
915 REG_OK_STRICT into account when deciding about valid registers, but it uses
916 the above macros so we are in luck.
917
918 Allow REG
919 REG+disp
920
921 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
922 and for DI is 0..56 because we use two SI loads, etc. */
923 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
924 do \
925 { \
926 if (GET_CODE (OP) == CONST_INT) \
927 { \
928 if (GET_MODE_SIZE (MODE) >= 4 \
929 && (((unsigned)INTVAL (OP)) % 4) == 0 \
930 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
931 goto LABEL; \
932 if (GET_MODE_SIZE (MODE) == 2 \
933 && (((unsigned)INTVAL (OP)) % 2) == 0 \
934 && ((unsigned)INTVAL (OP)) <= 30) \
935 goto LABEL; \
936 if (GET_MODE_SIZE (MODE) == 1 \
937 && ((unsigned)INTVAL (OP)) <= 15) \
938 goto LABEL; \
939 } \
940 } \
941 while (0)
942
943 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
944 { \
945 if (BASE_REGISTER_RTX_P (X)) \
946 goto LABEL; \
947 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
948 { \
949 rtx xop0 = XEXP (X,0); \
950 rtx xop1 = XEXP (X,1); \
951 if (BASE_REGISTER_RTX_P (xop0)) \
952 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
953 if (BASE_REGISTER_RTX_P (xop1)) \
954 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
955 } \
956 }
957
958 /* Go to LABEL if ADDR (a legitimate address expression)
959 has an effect that depends on the machine mode it is used for. */
960 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
961 { \
962 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
963 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
964 goto LABEL; \
965 }
966
967 /* Specify the machine mode that this machine uses
968 for the index in the tablejump instruction. */
969 #define CASE_VECTOR_MODE SImode
970
971 /* Define this if the tablejump instruction expects the table
972 to contain offsets from the address of the table.
973 Do not define this if the table should contain absolute addresses. */
974 /* #define CASE_VECTOR_PC_RELATIVE */
975
976 /* Specify the tree operation to be used to convert reals to integers. */
977 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
978
979 /* This is the kind of divide that is easiest to do in the general case. */
980 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
981
982 /* 'char' is signed by default. */
983 #define DEFAULT_SIGNED_CHAR 0
984
985 /* The type of size_t unsigned int. */
986 #define SIZE_TYPE "unsigned int"
987
988 /* Don't cse the address of the function being compiled. */
989 #define NO_RECURSIVE_FUNCTION_CSE 1
990
991 /* Max number of bytes we can move from memory to memory
992 in one reasonably fast instruction. */
993 #define MOVE_MAX 4
994
995 /* Define if operations between registers always perform the operation
996 on the full register even if a narrower mode is specified. */
997 #define WORD_REGISTER_OPERATIONS
998
999 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1000 will either zero-extend or sign-extend. The value of this macro should
1001 be the code that says which one of the two operations is implicitly
1002 done, NIL if none. */
1003 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1004
1005 /* Nonzero if access to memory by bytes is slow and undesirable. */
1006 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
1007
1008 /* We assume that the store-condition-codes instructions store 0 for false
1009 and some other value for true. This is the value stored for true. */
1010 #define STORE_FLAG_VALUE 1
1011
1012 /* Immediate shift counts are truncated by the output routines (or was it
1013 the assembler?). Shift counts in a register are truncated by ARM. Note
1014 that the native compiler puts too large (> 32) immediate shift counts
1015 into a register and shifts by the register, letting the ARM decide what
1016 to do instead of doing that itself. */
1017 #define SHIFT_COUNT_TRUNCATED 1
1018
1019 /* All integers have the same format so truncation is easy. */
1020 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1021
1022 /* Define this if addresses of constant functions
1023 shouldn't be put through pseudo regs where they can be cse'd.
1024 Desirable on machines where ordinary constants are expensive
1025 but a CALL with constant address is cheap. */
1026 /* why is this defined??? -- dac */
1027 #define NO_FUNCTION_CSE 1
1028
1029 /* Chars and shorts should be passed as ints. */
1030 #define PROMOTE_PROTOTYPES 1
1031
1032 /* The machine modes of pointers and functions. */
1033 #define Pmode SImode
1034 #define FUNCTION_MODE Pmode
1035
1036 /* The relative costs of various types of constants. Note that cse.c defines
1037 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1038 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1039 case CONST_INT: \
1040 return mcore_const_costs (RTX, OUTER_CODE); \
1041 case CONST: \
1042 case LABEL_REF: \
1043 case SYMBOL_REF: \
1044 return 5; \
1045 case CONST_DOUBLE: \
1046 return 10;
1047
1048 /* provide the cost for an address calculation.
1049 All addressing modes cost the same on the MCore. */
1050 #define ADDRESS_COST(RTX) 1
1051
1052 /* Provide the cost of an rtl expression. */
1053 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1054 case AND: \
1055 return COSTS_N_INSNS (mcore_and_cost (X)); \
1056 case IOR: \
1057 return COSTS_N_INSNS (mcore_ior_cost (X)); \
1058 case DIV: \
1059 case UDIV: \
1060 case MOD: \
1061 case UMOD: \
1062 return COSTS_N_INSNS (100); \
1063 case FLOAT: \
1064 case FIX: \
1065 return 100;
1066
1067 /* Compute extra cost of moving data between one register class
1068 and another. All register moves are cheap. */
1069 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) 2
1070
1071 #define WORD_REGISTER_OPERATIONS
1072
1073 /* Provided in ANSI C MCore libraries. */
1074 #undef HAVE_ATEXIT
1075 #define HAVE_ATEXIT 1
1076
1077 /* Implicit library calls should use memcpy, not bcopy, etc. */
1078 #define TARGET_MEM_FUNCTIONS
1079
1080 /* Assembler output control. */
1081 #define ASM_COMMENT_START "\t//"
1082
1083 #define ASM_APP_ON "// inline asm begin\n"
1084 #define ASM_APP_OFF "// inline asm end\n"
1085
1086 #define FILE_ASM_OP "\t.file\n"
1087
1088 /* Switch to the text or data segment. */
1089 #define TEXT_SECTION_ASM_OP "\t.text"
1090 #define DATA_SECTION_ASM_OP "\t.data"
1091
1092 #undef EXTRA_SECTIONS
1093 #define EXTRA_SECTIONS in_ctors, in_dtors, SUBTARGET_EXTRA_SECTIONS
1094
1095 #undef EXTRA_SECTION_FUNCTIONS
1096 #define EXTRA_SECTION_FUNCTIONS \
1097 CTORS_SECTION_FUNCTION \
1098 DTORS_SECTION_FUNCTION \
1099 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
1100 SWITCH_SECTION_FUNCTION
1101
1102 #ifndef CTORS_SECTION_FUNCTION
1103 #define CTORS_SECTION_FUNCTION \
1104 void \
1105 ctors_section () \
1106 { \
1107 if (in_section != in_ctors) \
1108 { \
1109 fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
1110 in_section = in_ctors; \
1111 } \
1112 }
1113
1114 #define DTORS_SECTION_FUNCTION \
1115 void \
1116 dtors_section () \
1117 { \
1118 if (in_section != in_dtors) \
1119 { \
1120 fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
1121 in_section = in_dtors; \
1122 } \
1123 }
1124 #endif
1125
1126 /* Switch to SECTION (an `enum in_section').
1127
1128 ??? This facility should be provided by GCC proper.
1129 The problem is that we want to temporarily switch sections in
1130 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1131 afterwards. */
1132 #define SWITCH_SECTION_FUNCTION \
1133 void \
1134 switch_to_section (section, decl) \
1135 enum in_section section; \
1136 tree decl; \
1137 { \
1138 switch (section) \
1139 { \
1140 case in_text: text_section (); break; \
1141 case in_data: data_section (); break; \
1142 case in_named: named_section (decl, NULL, 0); break; \
1143 case in_ctors: ctors_section (); break; \
1144 case in_dtors: dtors_section (); break; \
1145 SUBTARGET_SWITCH_SECTIONS \
1146 default: abort (); break; \
1147 } \
1148 }
1149
1150
1151 #define ASM_OUTPUT_SECTION(file, nam) \
1152 do { fprintf (file, "\t.section\t%s\n", nam); } while (0)
1153
1154 /* This is how to output an insn to push a register on the stack.
1155 It need not be very fast code. */
1156 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1157 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \
1158 reg_names[STACK_POINTER_REGNUM], \
1159 (STACK_BOUNDARY / BITS_PER_UNIT), \
1160 reg_names[REGNO], \
1161 reg_names[STACK_POINTER_REGNUM])
1162
1163 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1164 #define REG_PUSH_LENGTH 2
1165
1166 /* This is how to output an insn to pop a register from the stack. */
1167 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1168 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \
1169 reg_names[REGNO], \
1170 reg_names[STACK_POINTER_REGNUM], \
1171 reg_names[STACK_POINTER_REGNUM], \
1172 (STACK_BOUNDARY / BITS_PER_UNIT))
1173
1174
1175 /* DBX register number for a given compiler register number. */
1176 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1177
1178 /* Output a label definition. */
1179 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1180 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1181
1182 /* Output a reference to a label. */
1183 #undef ASM_OUTPUT_LABELREF
1184 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1185 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, MCORE_STRIP_NAME_ENCODING (NAME))
1186
1187
1188 /* This is how to output an assembler line
1189 that says to advance the location counter
1190 to a multiple of 2**LOG bytes. */
1191 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1192 if ((LOG) != 0) \
1193 fprintf (FILE, "\t.align\t%d\n", LOG)
1194
1195 #ifndef ASM_DECLARE_RESULT
1196 #define ASM_DECLARE_RESULT(FILE, RESULT)
1197 #endif
1198
1199 /* Strip export encoding from a function name. */
1200 #define MCORE_STRIP_NAME_ENCODING(SYM_NAME) \
1201 ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0))
1202
1203 /* Strip any text from SYM_NAME added by ENCODE_SECTION_INFO and store
1204 the result in VAR. */
1205 #undef STRIP_NAME_ENCODING
1206 #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \
1207 (VAR) = MCORE_STRIP_NAME_ENCODING (SYM_NAME)
1208
1209 #undef UNIQUE_SECTION
1210 #define UNIQUE_SECTION(DECL, RELOC) mcore_unique_section (DECL, RELOC)
1211
1212 #define REDO_SECTION_INFO_P(DECL) 1
1213
1214 #define MULTIPLE_SYMBOL_SPACES 1
1215
1216 #define SUPPORTS_ONE_ONLY 1
1217
1218 /* A pair of macros to output things for the callgraph data.
1219 VALUE means (to the tools that reads this info later):
1220 0 a call from src to dst
1221 1 the call is special (e.g. dst is "unknown" or "alloca")
1222 2 the call is special (e.g., the src is a table instead of routine)
1223
1224 Frame sizes are augmented with timestamps to help later tools
1225 differentiate between static entities with same names in different
1226 files. */
1227 extern long mcore_current_compilation_timestamp;
1228 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1229 do \
1230 { \
1231 if (mcore_current_compilation_timestamp == 0) \
1232 mcore_current_compilation_timestamp = time (0); \
1233 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \
1234 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1235 } \
1236 while (0)
1237
1238 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1239 do \
1240 { \
1241 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \
1242 (SRCNAME), (DSTNAME), (VALUE)); \
1243 } \
1244 while (0)
1245
1246 /* Output a globalising directive for a label. */
1247 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1248 (fprintf (STREAM, "\t.export\t"), \
1249 assemble_name (STREAM, NAME), \
1250 fputc ('\n',STREAM)) \
1251
1252 /* The prefix to add to user-visible assembler symbols. */
1253 #undef USER_LABEL_PREFIX
1254 #define USER_LABEL_PREFIX ""
1255
1256 /* Make an internal label into a string. */
1257 #undef ASM_GENERATE_INTERNAL_LABEL
1258 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1259 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM)
1260
1261 /* Output an internal label definition. */
1262 #undef ASM_OUTPUT_INTERNAL_LABEL
1263 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1264 fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1265
1266 /* Construct a private name. */
1267 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1268 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1269 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1270
1271 /* Jump tables must be 32 bit aligned. */
1272 #undef ASM_OUTPUT_CASE_LABEL
1273 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1274 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM);
1275
1276 /* Output a relative address. Not needed since jump tables are absolute
1277 but we must define it anyway. */
1278 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1279 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1280
1281 /* Output an element of a dispatch table. */
1282 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1283 fprintf (STREAM, "\t.long\t.L%d\n", VALUE)
1284
1285 /* Output various types of constants. */
1286
1287 /* This is how to output an assembler line defining a `double'. */
1288 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1289 do \
1290 { \
1291 char dstr[30]; \
1292 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1293 fprintf (FILE, "\t.double %s\n", dstr); \
1294 } \
1295 while (0)
1296
1297
1298 /* This is how to output an assembler line defining a `float' constant. */
1299 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1300 do \
1301 { \
1302 char dstr[30]; \
1303 REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
1304 fprintf (FILE, "\t.float %s\n", dstr); \
1305 } \
1306 while (0)
1307
1308 #define ASM_OUTPUT_INT(STREAM, EXP) \
1309 (fprintf (STREAM, "\t.long\t"), \
1310 output_addr_const (STREAM, (EXP)), \
1311 fputc ('\n', STREAM))
1312
1313 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1314 (fprintf (STREAM, "\t.short\t"), \
1315 output_addr_const (STREAM, (EXP)), \
1316 fputc ('\n', STREAM))
1317
1318 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1319 (fprintf (STREAM, "\t.byte\t"), \
1320 output_addr_const (STREAM, (EXP)), \
1321 fputc ('\n', STREAM))
1322
1323 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1324 fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
1325
1326 /* This is how to output an assembler line
1327 that says to advance the location counter by SIZE bytes. */
1328 #undef ASM_OUTPUT_SKIP
1329 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1330 fprintf (FILE, "\t.fill %d, 1\n", (SIZE))
1331
1332 /* This says how to output an assembler line
1333 to define a global common symbol, with alignment information. */
1334 /* XXX - for now we ignore the alignment. */
1335 #undef ASM_OUTPUT_ALIGNED_COMMON
1336 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1337 do \
1338 { \
1339 if (mcore_dllexport_name_p (NAME)) \
1340 MCORE_EXPORT_NAME (FILE, NAME) \
1341 if (! mcore_dllimport_name_p (NAME)) \
1342 { \
1343 fputs ("\t.comm\t", FILE); \
1344 assemble_name (FILE, NAME); \
1345 fprintf (FILE, ",%d\n", SIZE); \
1346 } \
1347 } \
1348 while (0)
1349
1350 /* This says how to output an assembler line
1351 to define an external symbol. */
1352 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1353 do \
1354 { \
1355 fputs ("\t.import\t", (FILE)); \
1356 assemble_name ((FILE), (NAME)); \
1357 fputs ("\n", (FILE)); \
1358 } \
1359 while (0)
1360
1361 #undef ASM_OUTPUT_EXTERNAL
1362 /* RBE: we undefined this and let gas do it's "undefined is imported"
1363 games. This is because when we use this, we get a marked
1364 reference through the call to assemble_name and this forces C++
1365 inlined member functions (or any inlined function) to be instantiated
1366 regardless of whether any callsites remain.
1367 This makes this aspect of the compiler non-ABI compliant. */
1368
1369 /* Similar, but for libcall. FUN is an rtx. */
1370 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1371 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1372 do \
1373 { \
1374 fprintf (FILE, "\t.import\t"); \
1375 assemble_name (FILE, XSTR (FUN, 0)); \
1376 fprintf (FILE, "\n"); \
1377 } \
1378 while (0)
1379
1380
1381 /* This says how to output an assembler line
1382 to define a local common symbol... */
1383 #undef ASM_OUTPUT_LOCAL
1384 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1385 (fputs ("\t.lcomm\t", FILE), \
1386 assemble_name (FILE, NAME), \
1387 fprintf (FILE, ",%d\n", SIZE))
1388
1389 /* ... and how to define a local common symbol whose alignment
1390 we wish to specify. ALIGN comes in as bits, we have to turn
1391 it into bytes. */
1392 #undef ASM_OUTPUT_ALIGNED_LOCAL
1393 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1394 do \
1395 { \
1396 fputs ("\t.bss\t", (FILE)); \
1397 assemble_name ((FILE), (NAME)); \
1398 fprintf ((FILE), ",%d,%d\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1399 } \
1400 while (0)
1401
1402 /* We must mark dll symbols specially. Definitions of dllexport'd objects
1403 install some info in the .drective (PE) or .exports (ELF) sections. */
1404 #undef ENCODE_SECTION_INFO
1405 #define ENCODE_SECTION_INFO(DECL) mcore_encode_section_info (DECL)
1406
1407 /* The assembler's parentheses characters. */
1408 #define ASM_OPEN_PAREN "("
1409 #define ASM_CLOSE_PAREN ")"
1410
1411 /* Target characters. */
1412 #define TARGET_BELL 007
1413 #define TARGET_BS 010
1414 #define TARGET_TAB 011
1415 #define TARGET_NEWLINE 012
1416 #define TARGET_VT 013
1417 #define TARGET_FF 014
1418 #define TARGET_CR 015
1419
1420 /* Print operand X (an rtx) in assembler syntax to file FILE.
1421 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1422 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1423 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1424
1425 /* Print a memory address as an operand to reference that memory location. */
1426 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1427
1428 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1429 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
1430
1431 /* This is to handle loads from the constant pool. */
1432 #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X)
1433
1434 /* This handles MCore dependent rtl simplifications. */
1435 #define MACHINE_DEPENDENT_SIMPLIFY(X,M,L,I,S) \
1436 mcore_dependent_simplify_rtx (X, M, L, I, S)
1437
1438 #define PREDICATE_CODES \
1439 { "mcore_arith_reg_operand", { REG, SUBREG }}, \
1440 { "mcore_general_movsrc_operand", { MEM, CONST_INT, REG, SUBREG }},\
1441 { "mcore_general_movdst_operand", { MEM, CONST_INT, REG, SUBREG }},\
1442 { "mcore_reload_operand", { MEM, REG, SUBREG }}, \
1443 { "mcore_arith_J_operand", { CONST_INT, REG, SUBREG }}, \
1444 { "mcore_arith_K_operand", { CONST_INT, REG, SUBREG }}, \
1445 { "mcore_arith_K_operand_not_0", { CONST_INT, REG, SUBREG }}, \
1446 { "mcore_arith_M_operand", { CONST_INT, REG, SUBREG }}, \
1447 { "mcore_arith_K_S_operand", { CONST_INT, REG, SUBREG }}, \
1448 { "mcore_arith_O_operand", { CONST_INT, REG, SUBREG }}, \
1449 { "mcore_arith_imm_operand", { CONST_INT, REG, SUBREG }}, \
1450 { "mcore_arith_any_imm_operand", { CONST_INT, REG, SUBREG }}, \
1451 { "mcore_literal_K_operand", { CONST_INT }}, \
1452 { "mcore_addsub_operand", { CONST_INT, REG, SUBREG }}, \
1453 { "mcore_compare_operand", { CONST_INT, REG, SUBREG }}, \
1454 { "mcore_load_multiple_operation", { PARALLEL }}, \
1455 { "mcore_store_multiple_operation", { PARALLEL }}, \
1456 { "mcore_call_address_operand", { REG, SUBREG, CONST_INT }}, \
1457
1458 #endif /* __MCORE__H */