projects / gcc.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
1750a.h, [...] (BITS_PER_WORD): Delete.
[gcc.git] / gcc / config / mcore / mcore.h
1 /* Definitions of target machine for GNU compiler,
2 for Motorola M*CORE Processor.
3 Copyright (C) 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #ifndef GCC_MCORE_H
23 #define GCC_MCORE_H
24
25 /* RBE: need to move these elsewhere. */
26 #undef LIKE_PPC_ABI
27 #define MCORE_STRUCT_ARGS
28 /* RBE: end of "move elsewhere". */
29
30 #include "hwint.h"
31
32 #ifndef HAVE_MACHINE_MODES
33 #include "machmode.h"
34 #endif
35
36 /* Run-time Target Specification. */
37 #define TARGET_MCORE
38
39 /* Get tree.c to declare a target-specific specialization of
40 merge_decl_attributes. */
41 #define TARGET_DLLIMPORT_DECL_ATTRIBUTES
42
43 /* Support the __declspec keyword by turning them into attributes.
44 We currently only support: dllexport and dllimport.
45 Note that the current way we do this may result in a collision with
46 predefined attributes later on. This can be solved by using one attribute,
47 say __declspec__, and passing args to it. The problem with that approach
48 is that args are not accumulated: each new appearance would clobber any
49 existing args. XXX- FIXME the definition below relies upon string
50 concatenation, which is non-portable. */
51 #define CPP_PREDEFINES \
52 "-D__mcore__ -D__MCORE__=1 -D__declspec(x)=__attribute__((x))" SUBTARGET_CPP_PREDEFINES
53
54 /* If -m4align is ever re-enabled then uncomment this line as well:
55 #define CPP_SPEC "%{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}" */
56
57 #undef CPP_SPEC
58 #define CPP_SPEC " \
59 %{mbig-endian: \
60 %{mlittle-endian:%echoose either big or little endian, not both} \
61 -D__MCOREBE__} \
62 %{m210: \
63 %{m340:%echoose either m340 or m210 not both} \
64 %{mlittle-endian:%ethe m210 does not have little endian support} \
65 -D__M210__} \
66 %{!mbig-endian: -D__MCORELE__} \
67 %{!m210: -D__M340__} \
68 "
69 /* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
70 %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__} */
71
72 /* We don't have a -lg library, so don't put it in the list. */
73 #undef LIB_SPEC
74 #define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
75
76 #undef ASM_SPEC
77 #define ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}"
78
79 #undef LINK_SPEC
80 #define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X"
81
82 /* Can only count on 16 bits of availability; change to long would affect
83 many architecture specific files (other architectures...). */
84 extern int target_flags;
85
86 #define HARDLIT_BIT (1 << 0) /* Build in-line literals using 2 insns */
87 #define ALIGN8_BIT (1 << 1) /* Max alignment goes to 8 instead of 4 */
88 #define DIV_BIT (1 << 2) /* Generate divide instructions */
89 #define RELAX_IMM_BIT (1 << 3) /* Arbitrary immediates in and, or, tst */
90 #define W_FIELD_BIT (1 << 4) /* Generate bit insv/extv using SImode */
91 #define OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary */
92 #define CGDATA_BIT (1 << 6) /* Generate callgraph data */
93 #define SLOW_BYTES_BIT (1 << 7) /* Slow byte access */
94 #define LITTLE_END_BIT (1 << 8) /* Generate little endian code */
95 #define M340_BIT (1 << 9) /* Generate code for the m340 */
96
97 #define TARGET_DEFAULT \
98 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)
99
100 #ifndef MULTILIB_DEFAULTS
101 #define MULTILIB_DEFAULTS { "mlittle-endian", "m340" }
102 #endif
103
104 #define TARGET_HARDLIT (target_flags & HARDLIT_BIT)
105 /* The ability to have 4 byte alignment is being suppressed for now.
106 If this ability is reenabled, you must enable the definition below
107 *and* edit t-mcore to enable multilibs for 4 byte alignment code. */
108 #if 0
109 #define TARGET_8ALIGN (target_flags & ALIGN8_BIT)
110 #else
111 #define TARGET_8ALIGN 1
112 #endif
113 #define TARGET_DIV (target_flags & DIV_BIT)
114 #define TARGET_RELAX_IMM (target_flags & RELAX_IMM_BIT)
115 #define TARGET_W_FIELD (target_flags & W_FIELD_BIT)
116 #define TARGET_OVERALIGN_FUNC (target_flags & OVERALIGN_FUNC_BIT)
117 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
118 #define TARGET_CG_DATA (target_flags & CGDATA_BIT)
119 #define TARGET_SLOW_BYTES (target_flags & SLOW_BYTES_BIT)
120 #define TARGET_LITTLE_END (target_flags & LITTLE_END_BIT)
121 #define TARGET_M340 (target_flags & M340_BIT)
122
123
124 #define TARGET_SWITCHES \
125 { {"hardlit", HARDLIT_BIT, \
126 N_("Inline constants if it can be done in 2 insns or less") }, \
127 {"no-hardlit", - HARDLIT_BIT, \
128 N_("Inline constants if it only takes 1 instruction") }, \
129 {"4align", - ALIGN8_BIT, \
130 N_("Set maximum alignment to 4") }, \
131 {"8align", ALIGN8_BIT, \
132 N_("Set maximum alignment to 8") }, \
133 {"div", DIV_BIT, \
134 "" }, \
135 {"no-div", - DIV_BIT, \
136 N_("Do not use the divide instruction") }, \
137 {"relax-immediates", RELAX_IMM_BIT, \
138 "" }, \
139 {"no-relax-immediates", - RELAX_IMM_BIT, \
140 N_("Do not arbitary sized immediates in bit operations") }, \
141 {"wide-bitfields", W_FIELD_BIT, \
142 N_("Always treat bit-field as int-sized") }, \
143 {"no-wide-bitfields", - W_FIELD_BIT, \
144 "" }, \
145 {"4byte-functions", OVERALIGN_FUNC_BIT, \
146 N_("Force functions to be aligned to a 4 byte boundary") }, \
147 {"no-4byte-functions", - OVERALIGN_FUNC_BIT, \
148 N_("Force functions to be aligned to a 2 byte boundary") }, \
149 {"callgraph-data", CGDATA_BIT, \
150 N_("Emit call graph information") }, \
151 {"no-callgraph-data", - CGDATA_BIT, \
152 "" }, \
153 {"slow-bytes", SLOW_BYTES_BIT, \
154 N_("Prefer word accesses over byte accesses") }, \
155 {"no-slow-bytes", - SLOW_BYTES_BIT, \
156 "" }, \
157 { "no-lsim", 0, "" }, \
158 {"little-endian", LITTLE_END_BIT, \
159 N_("Generate little endian code") }, \
160 {"big-endian", - LITTLE_END_BIT, \
161 "" }, \
162 {"210", - M340_BIT, \
163 "" }, \
164 {"340", M340_BIT, \
165 N_("Generate code for the M*Core M340") }, \
166 {"", TARGET_DEFAULT, \
167 "" } \
168 }
169
170 extern char * mcore_current_function_name;
171
172 /* Target specific options (as opposed to the switches above). */
173 extern const char * mcore_stack_increment_string;
174
175 #define TARGET_OPTIONS \
176 { \
177 {"stack-increment=", & mcore_stack_increment_string, \
178 N_("Maximum amount for a single stack increment operation")} \
179 }
180
181 /* The MCore ABI says that bitfields are unsigned by default. */
182 /* The EPOC C++ environment does not support exceptions. */
183 #define CC1_SPEC "-funsigned-bitfields %{!DIN_GCC:-fno-rtti} %{!DIN_GCC:-fno-exceptions}"
184
185 /* What options are we going to default to specific settings when
186 -O* happens; the user can subsequently override these settings.
187
188 Omitting the frame pointer is a very good idea on the MCore.
189 Scheduling isn't worth anything on the current MCore implementation. */
190 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
191 { \
192 if (LEVEL) \
193 { \
194 flag_no_function_cse = 1; \
195 flag_omit_frame_pointer = 1; \
196 \
197 if (LEVEL >= 2) \
198 { \
199 flag_caller_saves = 0; \
200 flag_schedule_insns = 0; \
201 flag_schedule_insns_after_reload = 0; \
202 } \
203 } \
204 if (SIZE) \
205 { \
206 target_flags &= ~ HARDLIT_BIT; \
207 } \
208 }
209
210 /* What options are we going to force to specific settings,
211 regardless of what the user thought he wanted.
212 We also use this for some post-processing of options. */
213 #define OVERRIDE_OPTIONS mcore_override_options ()
214
215 /* Target machine storage Layout. */
216
217 /* Define to use software floating point emulator for REAL_ARITHMETIC and
218 decimal <-> binary conversion. */
219 #define REAL_ARITHMETIC
220
221 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
222 if (GET_MODE_CLASS (MODE) == MODE_INT \
223 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
224 { \
225 (MODE) = SImode; \
226 (UNSIGNEDP) = 1; \
227 }
228
229 #define PROMOTE_FUNCTION_ARGS
230
231 #define PROMOTE_FUNCTION_RETURN
232
233 /* Define this if most significant bit is lowest numbered
234 in instructions that operate on numbered bit-fields. */
235 #define BITS_BIG_ENDIAN 0
236
237 /* Define this if most significant byte of a word is the lowest numbered. */
238 #define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)
239
240 /* Define this if most significant word of a multiword number is the lowest
241 numbered. */
242 #define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)
243
244 #define LIBGCC2_WORDS_BIG_ENDIAN 1
245 #ifdef __MCORELE__
246 #undef LIBGCC2_WORDS_BIG_ENDIAN
247 #define LIBGCC2_WORDS_BIG_ENDIAN 0
248 #endif
249
250 #define MAX_BITS_PER_WORD 32
251
252 /* Width of a word, in units (bytes). */
253 #define UNITS_PER_WORD 4
254
255 /* Width in bits of a pointer.
256 See also the macro `Pmode' defined below. */
257 #define POINTER_SIZE 32
258
259 /* A C expression for the size in bits of the type `long long' on the
260 target machine. If you don't define this, the default is two
261 words. */
262 #define LONG_LONG_TYPE_SIZE 64
263
264 /* the size of the boolean type -- in C++; */
265 #define BOOL_TYPE_SIZE 8
266
267 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
268 #define PARM_BOUNDARY 32
269
270 /* Doubles must be alogned to an 8 byte boundary. */
271 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
272 ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
273 ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
274
275 /* Boundary (in *bits*) on which stack pointer should be aligned. */
276 #define STACK_BOUNDARY (TARGET_8ALIGN ? 64 : 32)
277
278 /* Largest increment in UNITS we allow the stack to grow in a single operation. */
279 extern int mcore_stack_increment;
280 #define STACK_UNITS_MAXSTEP 4096
281
282 /* Allocation boundary (in *bits*) for the code of a function. */
283 #define FUNCTION_BOUNDARY ((TARGET_OVERALIGN_FUNC) ? 32 : 16)
284
285 /* Alignment of field after `int : 0' in a structure. */
286 #define EMPTY_FIELD_BOUNDARY 32
287
288 /* No data type wants to be aligned rounder than this. */
289 #define BIGGEST_ALIGNMENT (TARGET_8ALIGN ? 64 : 32)
290
291 /* The best alignment to use in cases where we have a choice. */
292 #define FASTEST_ALIGNMENT 32
293
294 /* Every structures size must be a multiple of 8 bits. */
295 #define STRUCTURE_SIZE_BOUNDARY 8
296
297 /* Look at the fundamental type that is used for a bitfield and use
298 that to impose alignment on the enclosing structure.
299 struct s {int a:8}; should have same alignment as "int", not "char". */
300 #define PCC_BITFIELD_TYPE_MATTERS 1
301
302 /* Largest integer machine mode for structures. If undefined, the default
303 is GET_MODE_SIZE(DImode). */
304 #define MAX_FIXED_MODE_SIZE 32
305
306 /* Make strings word-aligned so strcpy from constants will be faster. */
307 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
308 ((TREE_CODE (EXP) == STRING_CST \
309 && (ALIGN) < FASTEST_ALIGNMENT) \
310 ? FASTEST_ALIGNMENT : (ALIGN))
311
312 /* Make arrays of chars word-aligned for the same reasons. */
313 #define DATA_ALIGNMENT(TYPE, ALIGN) \
314 (TREE_CODE (TYPE) == ARRAY_TYPE \
315 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
316 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
317
318 /* Set this nonzero if move instructions will actually fail to work
319 when given unaligned data. */
320 #define STRICT_ALIGNMENT 1
321
322 /* Standard register usage. */
323
324 /* Register allocation for our first guess
325
326 r0 stack pointer
327 r1 scratch, target reg for xtrb?
328 r2-r7 arguments.
329 r8-r14 call saved
330 r15 link register
331 ap arg pointer (doesn't really exist, always eliminated)
332 c c bit
333 fp frame pointer (doesn't really exist, always eliminated)
334 x19 two control registers */
335
336 /* Number of actual hardware registers.
337 The hardware registers are assigned numbers for the compiler
338 from 0 to just below FIRST_PSEUDO_REGISTER.
339 All registers that the compiler knows about must be given numbers,
340 even those that are not normally considered general registers.
341
342 MCore has 16 integer registers and 2 control registers + the arg
343 pointer. */
344
345 #define FIRST_PSEUDO_REGISTER 20
346
347 #define R1_REG 1 /* where literals are forced */
348 #define LK_REG 15 /* overloaded on general register */
349 #define AP_REG 16 /* fake arg pointer register */
350 /* RBE: mcore.md depends on CC_REG being set to 17 */
351 #define CC_REG 17 /* can't name it C_REG */
352 #define FP_REG 18 /* fake frame pointer register */
353
354 /* Specify the registers used for certain standard purposes.
355 The values of these macros are register numbers. */
356
357
358 #undef PC_REGNUM /* Define this if the program counter is overloaded on a register. */
359 #define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments. */
360 #define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8. */
361
362 /* The assembler's names for the registers. RFP need not always be used as
363 the Real framepointer; it can also be used as a normal general register.
364 Note that the name `fp' is horribly misleading since `fp' is in fact only
365 the argument-and-return-context pointer. */
366 #define REGISTER_NAMES \
367 { \
368 "sp", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
369 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
370 "apvirtual", "c", "fpvirtual", "x19" \
371 }
372
373 /* 1 for registers that have pervasive standard uses
374 and are not available for the register allocator. */
375 #define FIXED_REGISTERS \
376 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
377 { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
378
379 /* 1 for registers not available across function calls.
380 These must include the FIXED_REGISTERS and also any
381 registers that can be used without being saved.
382 The latter must include the registers where values are returned
383 and the register where structure-value addresses are passed.
384 Aside from that, you can include as many other registers as you like. */
385
386 /* RBE: r15 {link register} not available across calls,
387 * But we don't mark it that way here... */
388 #define CALL_USED_REGISTERS \
389 /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap c fp x19 */ \
390 { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1}
391
392 /* The order in which register should be allocated. */
393 #define REG_ALLOC_ORDER \
394 /* r7 r6 r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r1 r0 ap c fp x19*/ \
395 { 7, 6, 5, 4, 3, 2, 15, 14, 13, 12, 11, 10, 9, 8, 1, 0, 16, 17, 18, 19}
396
397 /* Return number of consecutive hard regs needed starting at reg REGNO
398 to hold something of mode MODE.
399 This is ordinarily the length in words of a value of mode MODE
400 but can be less for certain modes in special long registers.
401
402 On the MCore regs are UNITS_PER_WORD bits wide; */
403 #define HARD_REGNO_NREGS(REGNO, MODE) \
404 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
405
406 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
407 We may keep double values in even registers. */
408 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
409 ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))
410
411 /* Value is 1 if it is a good idea to tie two pseudo registers
412 when one has mode MODE1 and one has mode MODE2.
413 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
414 for any hard reg, then this must be 0 for correct output. */
415 #define MODES_TIEABLE_P(MODE1, MODE2) \
416 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
417
418 /* Value should be nonzero if functions must have frame pointers.
419 Zero means the frame pointer need not be set up (and parms may be accessed
420 via the stack pointer) in functions that seem suitable. */
421 #define FRAME_POINTER_REQUIRED 0
422
423 /* Definitions for register eliminations.
424
425 We have two registers that can be eliminated on the MCore. First, the
426 frame pointer register can often be eliminated in favor of the stack
427 pointer register. Secondly, the argument pointer register can always be
428 eliminated; it is replaced with either the stack or frame pointer. */
429
430 /* Base register for access to arguments of the function. */
431 #define ARG_POINTER_REGNUM 16
432
433 /* Register in which the static-chain is passed to a function. */
434 #define STATIC_CHAIN_REGNUM 1
435
436 /* This is an array of structures. Each structure initializes one pair
437 of eliminable registers. The "from" register number is given first,
438 followed by "to". Eliminations of the same "from" register are listed
439 in order of preference. */
440 #define ELIMINABLE_REGS \
441 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
442 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
443 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
444
445 /* Given FROM and TO register numbers, say whether this elimination
446 is allowed. */
447 #define CAN_ELIMINATE(FROM, TO) \
448 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
449
450 /* Define the offset between two registers, one to be eliminated, and the other
451 its replacement, at the start of a routine. */
452 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
453 OFFSET = mcore_initial_elimination_offset (FROM, TO)
454
455 /* Place that structure value return address is placed. */
456 #define STRUCT_VALUE 0
457
458 /* Define the classes of registers for register constraints in the
459 machine description. Also define ranges of constants.
460
461 One of the classes must always be named ALL_REGS and include all hard regs.
462 If there is more than one class, another class must be named NO_REGS
463 and contain no registers.
464
465 The name GENERAL_REGS must be the name of a class (or an alias for
466 another name such as ALL_REGS). This is the class of registers
467 that is allowed by "g" or "r" in a register constraint.
468 Also, registers outside this class are allocated only when
469 instructions express preferences for them.
470
471 The classes must be numbered in nondecreasing order; that is,
472 a larger-numbered class must never be contained completely
473 in a smaller-numbered class.
474
475 For any two classes, it is very desirable that there be another
476 class that represents their union. */
477
478 /* The MCore has only general registers. There are
479 also some special purpose registers: the T bit register, the
480 procedure Link and the Count Registers */
481 enum reg_class
482 {
483 NO_REGS,
484 ONLYR1_REGS,
485 LRW_REGS,
486 GENERAL_REGS,
487 C_REGS,
488 ALL_REGS,
489 LIM_REG_CLASSES
490 };
491
492 #define N_REG_CLASSES (int) LIM_REG_CLASSES
493
494 /* Give names of register classes as strings for dump file. */
495 #define REG_CLASS_NAMES \
496 { \
497 "NO_REGS", \
498 "ONLYR1_REGS", \
499 "LRW_REGS", \
500 "GENERAL_REGS", \
501 "C_REGS", \
502 "ALL_REGS", \
503 }
504
505 /* Define which registers fit in which classes.
506 This is an initializer for a vector of HARD_REG_SET
507 of length N_REG_CLASSES. */
508
509 /* ??? STACK_POINTER_REGNUM should be excluded from LRW_REGS. */
510 #define REG_CLASS_CONTENTS \
511 { \
512 {0x000000}, /* NO_REGS */ \
513 {0x000002}, /* ONLYR1_REGS */ \
514 {0x007FFE}, /* LRW_REGS */ \
515 {0x01FFFF}, /* GENERAL_REGS */ \
516 {0x020000}, /* C_REGS */ \
517 {0x0FFFFF} /* ALL_REGS */ \
518 }
519
520 /* The same information, inverted:
521 Return the class number of the smallest class containing
522 reg number REGNO. This could be a conditional expression
523 or could index an array. */
524
525 extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
526 #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
527
528 /* When defined, the compiler allows registers explicitly used in the
529 rtl to be used as spill registers but prevents the compiler from
530 extending the lifetime of these registers. */
531 #define SMALL_REGISTER_CLASSES 1
532
533 /* The class value for index registers, and the one for base regs. */
534 #define INDEX_REG_CLASS NO_REGS
535 #define BASE_REG_CLASS GENERAL_REGS
536
537 /* Get reg_class from a letter such as appears in the machine
538 description. */
539 extern const enum reg_class reg_class_from_letter[];
540
541 #define REG_CLASS_FROM_LETTER(C) \
542 ( ISLOWER (C) ? reg_class_from_letter[(C) - 'a'] : NO_REGS )
543
544 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
545 can be used to stand for particular ranges of immediate operands.
546 This macro defines what the ranges are.
547 C is the letter, and VALUE is a constant value.
548 Return 1 if VALUE is in the range specified by C.
549 I: loadable by movi (0..127)
550 J: arithmetic operand 1..32
551 K: shift operand 0..31
552 L: negative arithmetic operand -1..-32
553 M: powers of two, constants loadable by bgeni
554 N: powers of two minus 1, constants loadable by bmaski, including -1
555 O: allowed by cmov with two constants +/- 1 of each other
556 P: values we will generate 'inline' -- without an 'lrw'
557
558 Others defined for use after reload
559 Q: constant 1
560 R: a label
561 S: 0/1/2 cleared bits out of 32 [for bclri's]
562 T: 2 set bits out of 32 [for bseti's]
563 U: constant 0
564 xxxS: 1 cleared bit out of 32 (complement of power of 2). for bclri
565 xxxT: 2 cleared bits out of 32. for pairs of bclris. */
566 #define CONST_OK_FOR_I(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 0x7f)
567 #define CONST_OK_FOR_J(VALUE) (((int)(VALUE)) > 0 && ((int)(VALUE)) <= 32)
568 #define CONST_OK_FOR_L(VALUE) (((int)(VALUE)) < 0 && ((int)(VALUE)) >= -32)
569 #define CONST_OK_FOR_K(VALUE) (((int)(VALUE)) >= 0 && ((int)(VALUE)) <= 31)
570 #define CONST_OK_FOR_M(VALUE) (exact_log2 (VALUE) >= 0)
571 #define CONST_OK_FOR_N(VALUE) (((int)(VALUE)) == -1 || exact_log2 ((VALUE) + 1) >= 0)
572 #define CONST_OK_FOR_O(VALUE) (CONST_OK_FOR_I(VALUE) || \
573 CONST_OK_FOR_M(VALUE) || \
574 CONST_OK_FOR_N(VALUE) || \
575 CONST_OK_FOR_M((int)(VALUE) - 1) || \
576 CONST_OK_FOR_N((int)(VALUE) + 1))
577
578 #define CONST_OK_FOR_P(VALUE) (mcore_const_ok_for_inline (VALUE))
579
580 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
581 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
582 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
583 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
584 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
585 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
586 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
587 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
588 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
589 : 0)
590
591 /* Similar, but for floating constants, and defining letters G and H.
592 Here VALUE is the CONST_DOUBLE rtx itself. */
593 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
594 ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
595 && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
596 : 0)
597
598 /* Letters in the range `Q' through `U' in a register constraint string
599 may be defined in a machine-dependent fashion to stand for arbitrary
600 operand types. */
601 #define EXTRA_CONSTRAINT(OP, C) \
602 ((C) == 'R' ? (GET_CODE (OP) == MEM \
603 && GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
604 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
605 && mcore_num_zeros (INTVAL (OP)) <= 2) \
606 : (C) == 'T' ? (GET_CODE (OP) == CONST_INT \
607 && mcore_num_ones (INTVAL (OP)) == 2) \
608 : (C) == 'Q' ? (GET_CODE (OP) == CONST_INT \
609 && INTVAL(OP) == 1) \
610 : (C) == 'U' ? (GET_CODE (OP) == CONST_INT \
611 && INTVAL(OP) == 0) \
612 : 0)
613
614 /* Given an rtx X being reloaded into a reg required to be
615 in class CLASS, return the class of reg to actually use.
616 In general this is just CLASS; but on some machines
617 in some cases it is preferable to use a more restrictive class. */
618 #define PREFERRED_RELOAD_CLASS(X, CLASS) mcore_reload_class (X, CLASS)
619
620 /* Return the register class of a scratch register needed to copy IN into
621 or out of a register in CLASS in MODE. If it can be done directly,
622 NO_REGS is returned. */
623 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
624
625 /* Return the maximum number of consecutive registers
626 needed to represent mode MODE in a register of class CLASS.
627
628 On MCore this is the size of MODE in words. */
629 #define CLASS_MAX_NREGS(CLASS, MODE) \
630 (ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
631
632 /* Stack layout; function entry, exit and calling. */
633
634 /* Define the number of register that can hold parameters.
635 These two macros are used only in other macro definitions below. */
636 #define NPARM_REGS 6
637 #define FIRST_PARM_REG 2
638 #define FIRST_RET_REG 2
639
640 /* Define this if pushing a word on the stack
641 makes the stack pointer a smaller address. */
642 #define STACK_GROWS_DOWNWARD
643
644 /* Define this if the nominal address of the stack frame
645 is at the high-address end of the local variables;
646 that is, each additional local variable allocated
647 goes at a more negative offset in the frame. */
648 /* We don't define this, because the MCore does not support
649 addresses with negative offsets. */
650 /* #define FRAME_GROWS_DOWNWARD */
651
652 /* Offset within stack frame to start allocating local variables at.
653 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
654 first local allocated. Otherwise, it is the offset to the BEGINNING
655 of the first local allocated. */
656 #define STARTING_FRAME_OFFSET 0
657
658 /* If defined, the maximum amount of space required for outgoing arguments
659 will be computed and placed into the variable
660 `current_function_outgoing_args_size'. No space will be pushed
661 onto the stack for each call; instead, the function prologue should
662 increase the stack frame size by this amount. */
663 #define ACCUMULATE_OUTGOING_ARGS 1
664
665 /* Offset of first parameter from the argument pointer register value. */
666 #define FIRST_PARM_OFFSET(FNDECL) 0
667
668 /* Value is the number of byte of arguments automatically
669 popped when returning from a subroutine call.
670 FUNTYPE is the data type of the function (as a tree),
671 or for a library call it is an identifier node for the subroutine name.
672 SIZE is the number of bytes of arguments passed on the stack.
673
674 On the MCore, the callee does not pop any of its arguments that were passed
675 on the stack. */
676 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
677
678 /* Define how to find the value returned by a function.
679 VALTYPE is the data type of the value (as a tree).
680 If the precise function being called is known, FUNC is its FUNCTION_DECL;
681 otherwise, FUNC is 0. */
682 #define FUNCTION_VALUE(VALTYPE, FUNC) mcore_function_value (VALTYPE, FUNC)
683
684 /* Don't default to pcc-struct-return, because gcc is the only compiler, and
685 we want to retain compatibility with older gcc versions. */
686 #define DEFAULT_PCC_STRUCT_RETURN 0
687
688 /* how we are going to return big values */
689 /*
690 * #define RETURN_IN_MEMORY(TYPE) \
691 * (TYPE_MODE (TYPE) == BLKmode \
692 * || ((TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE(TYPE) == UNION_TYPE) \
693 * && !(TYPE_MODE (TYPE) == SImode \
694 * || (TYPE_MODE (TYPE) == BLKmode \
695 * && TYPE_ALIGN (TYPE) == BITS_PER_WORD \
696 * && int_size_in_bytes (TYPE) == UNITS_PER_WORD))))
697 */
698
699
700 /* How many registers to use for struct return. */
701 #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 2 * UNITS_PER_WORD)
702
703 /* Define how to find the value returned by a library function
704 assuming the value has mode MODE. */
705 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
706
707 /* 1 if N is a possible register number for a function value.
708 On the MCore, only r4 can return results. */
709 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
710
711 #define MUST_PASS_IN_STACK(MODE,TYPE) \
712 mcore_must_pass_on_stack (MODE, TYPE)
713
714 /* 1 if N is a possible register number for function argument passing. */
715 #define FUNCTION_ARG_REGNO_P(REGNO) \
716 ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
717
718 /* Define a data type for recording info about an argument list
719 during the scan of that argument list. This data type should
720 hold all necessary information about the function itself
721 and about the args processed so far, enough to enable macros
722 such as FUNCTION_ARG to determine where the next arg should go.
723
724 On MCore, this is a single integer, which is a number of words
725 of arguments scanned so far (including the invisible argument,
726 if any, which holds the structure-value-address).
727 Thus NARGREGS or more means all following args should go on the stack. */
728 #define CUMULATIVE_ARGS int
729
730 #define ROUND_ADVANCE(SIZE) \
731 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
732
733 /* Round a register number up to a proper boundary for an arg of mode
734 MODE.
735
736 We round to an even reg for things larger than a word. */
737 #define ROUND_REG(X, MODE) \
738 ((TARGET_8ALIGN \
739 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
740 ? ((X) + ((X) & 1)) : (X))
741
742
743 /* Initialize a variable CUM of type CUMULATIVE_ARGS
744 for a call to a function whose data type is FNTYPE.
745 For a library call, FNTYPE is 0.
746
747 On MCore, the offset always starts at 0: the first parm reg is always
748 the same reg. */
749 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
750 ((CUM) = 0)
751
752 /* Update the data in CUM to advance over an argument
753 of mode MODE and data type TYPE.
754 (TYPE is null for libcalls where that information may not be
755 available.) */
756 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
757 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
758 + ((NAMED) * mcore_num_arg_regs (MODE, TYPE)))) \
759
760 /* Define where to put the arguments to a function. */
761 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
762 mcore_function_arg (CUM, MODE, TYPE, NAMED)
763
764 /* A C expression that indicates when an argument must be passed by
765 reference. If nonzero for an argument, a copy of that argument is
766 made in memory and a pointer to the argument is passed instead of
767 the argument itself. The pointer is passed in whatever way is
768 appropriate for passing a pointer to that type. */
769 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
770 MUST_PASS_IN_STACK (MODE, TYPE)
771
772 /* For an arg passed partly in registers and partly in memory,
773 this is the number of registers used.
774 For args passed entirely in registers or entirely in memory, zero.
775 Any arg that starts in the first NPARM_REGS regs but won't entirely
776 fit in them needs partial registers on the MCore. */
777 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
778 mcore_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
779
780 /* Perform any needed actions needed for a function that is receiving a
781 variable number of arguments. */
782 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
783 mcore_setup_incoming_varargs (ASF, MODE, TYPE, & PAS)
784
785 /* Call the function profiler with a given profile label. */
786 #define FUNCTION_PROFILER(STREAM,LABELNO) \
787 { \
788 fprintf (STREAM, " trap 1\n"); \
789 fprintf (STREAM, " .align 2\n"); \
790 fprintf (STREAM, " .long LP%d\n", (LABELNO)); \
791 }
792
793 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
794 the stack pointer does not matter. The value is tested only in
795 functions that have frame pointers.
796 No definition is equivalent to always zero. */
797 #define EXIT_IGNORE_STACK 0
798
799 /* Output assembler code for a block containing the constant parts
800 of a trampoline, leaving space for the variable parts.
801
802 On the MCore, the trapoline looks like:
803 lrw r1, function
804 lrw r13, area
805 jmp r13
806 or r0, r0
807 .literals */
808 #define TRAMPOLINE_TEMPLATE(FILE) \
809 { \
810 fprintf ((FILE), " .short 0x7102\n"); \
811 fprintf ((FILE), " .short 0x7d02\n"); \
812 fprintf ((FILE), " .short 0x00cd\n"); \
813 fprintf ((FILE), " .short 0x1e00\n"); \
814 fprintf ((FILE), " .long 0\n"); \
815 fprintf ((FILE), " .long 0\n"); \
816 }
817
818 /* Length in units of the trampoline for entering a nested function. */
819 #define TRAMPOLINE_SIZE 12
820
821 /* Alignment required for a trampoline in bits. */
822 #define TRAMPOLINE_ALIGNMENT 32
823
824 /* Emit RTL insns to initialize the variable parts of a trampoline.
825 FNADDR is an RTX for the address of the function's pure code.
826 CXT is an RTX for the static chain value for the function. */
827 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
828 { \
829 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
830 (CXT)); \
831 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
832 (FNADDR)); \
833 }
834
835 /* Macros to check register numbers against specific register classes. */
836
837 /* These assume that REGNO is a hard or pseudo reg number.
838 They give nonzero only if REGNO is a hard reg of the suitable class
839 or a pseudo reg currently allocated to a suitable hard reg.
840 Since they use reg_renumber, they are safe only once reg_renumber
841 has been allocated, which happens in local-alloc.c. */
842 #define REGNO_OK_FOR_BASE_P(REGNO) \
843 ((REGNO) < AP_REG || (unsigned) reg_renumber[(REGNO)] < AP_REG)
844
845 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
846
847 /* Maximum number of registers that can appear in a valid memory
848 address. */
849 #define MAX_REGS_PER_ADDRESS 1
850
851 /* Recognize any constant value that is a valid address. */
852 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
853
854 /* Nonzero if the constant value X is a legitimate general operand.
855 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
856
857 On the MCore, allow anything but a double. */
858 #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
859
860 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
861 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
862 and check its validity for a certain class.
863 We have two alternate definitions for each of them.
864 The usual definition accepts all pseudo regs; the other rejects
865 them unless they have been allocated suitable hard regs.
866 The symbol REG_OK_STRICT causes the latter definition to be used. */
867 #ifndef REG_OK_STRICT
868
869 /* Nonzero if X is a hard reg that can be used as a base reg
870 or if it is a pseudo reg. */
871 #define REG_OK_FOR_BASE_P(X) \
872 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
873
874 /* Nonzero if X is a hard reg that can be used as an index
875 or if it is a pseudo reg. */
876 #define REG_OK_FOR_INDEX_P(X) 0
877
878 #else
879
880 /* Nonzero if X is a hard reg that can be used as a base reg. */
881 #define REG_OK_FOR_BASE_P(X) \
882 REGNO_OK_FOR_BASE_P (REGNO (X))
883
884 /* Nonzero if X is a hard reg that can be used as an index. */
885 #define REG_OK_FOR_INDEX_P(X) 0
886
887 #endif
888 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
889 that is a valid memory address for an instruction.
890 The MODE argument is the machine mode for the MEM expression
891 that wants to use this address.
892
893 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
894 #define BASE_REGISTER_RTX_P(X) \
895 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
896
897 #define INDEX_REGISTER_RTX_P(X) \
898 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
899
900
901 /* Jump to LABEL if X is a valid address RTX. This must also take
902 REG_OK_STRICT into account when deciding about valid registers, but it uses
903 the above macros so we are in luck.
904
905 Allow REG
906 REG+disp
907
908 A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
909 and for DI is 0..56 because we use two SI loads, etc. */
910 #define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
911 do \
912 { \
913 if (GET_CODE (OP) == CONST_INT) \
914 { \
915 if (GET_MODE_SIZE (MODE) >= 4 \
916 && (((unsigned)INTVAL (OP)) % 4) == 0 \
917 && ((unsigned)INTVAL (OP)) <= 64 - GET_MODE_SIZE (MODE)) \
918 goto LABEL; \
919 if (GET_MODE_SIZE (MODE) == 2 \
920 && (((unsigned)INTVAL (OP)) % 2) == 0 \
921 && ((unsigned)INTVAL (OP)) <= 30) \
922 goto LABEL; \
923 if (GET_MODE_SIZE (MODE) == 1 \
924 && ((unsigned)INTVAL (OP)) <= 15) \
925 goto LABEL; \
926 } \
927 } \
928 while (0)
929
930 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
931 { \
932 if (BASE_REGISTER_RTX_P (X)) \
933 goto LABEL; \
934 else if (GET_CODE (X) == PLUS || GET_CODE (X) == LO_SUM) \
935 { \
936 rtx xop0 = XEXP (X,0); \
937 rtx xop1 = XEXP (X,1); \
938 if (BASE_REGISTER_RTX_P (xop0)) \
939 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
940 if (BASE_REGISTER_RTX_P (xop1)) \
941 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
942 } \
943 }
944
945 /* Go to LABEL if ADDR (a legitimate address expression)
946 has an effect that depends on the machine mode it is used for. */
947 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
948 { \
949 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
950 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
951 goto LABEL; \
952 }
953
954 /* Specify the machine mode that this machine uses
955 for the index in the tablejump instruction. */
956 #define CASE_VECTOR_MODE SImode
957
958 /* Define this if the tablejump instruction expects the table
959 to contain offsets from the address of the table.
960 Do not define this if the table should contain absolute addresses. */
961 /* #define CASE_VECTOR_PC_RELATIVE */
962
963 /* 'char' is signed by default. */
964 #define DEFAULT_SIGNED_CHAR 0
965
966 /* The type of size_t unsigned int. */
967 #define SIZE_TYPE "unsigned int"
968
969 /* Don't cse the address of the function being compiled. */
970 #define NO_RECURSIVE_FUNCTION_CSE 1
971
972 /* Max number of bytes we can move from memory to memory
973 in one reasonably fast instruction. */
974 #define MOVE_MAX 4
975
976 /* Define if operations between registers always perform the operation
977 on the full register even if a narrower mode is specified. */
978 #define WORD_REGISTER_OPERATIONS
979
980 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
981 will either zero-extend or sign-extend. The value of this macro should
982 be the code that says which one of the two operations is implicitly
983 done, NIL if none. */
984 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
985
986 /* Nonzero if access to memory by bytes is slow and undesirable. */
987 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
988
989 /* We assume that the store-condition-codes instructions store 0 for false
990 and some other value for true. This is the value stored for true. */
991 #define STORE_FLAG_VALUE 1
992
993 /* Immediate shift counts are truncated by the output routines (or was it
994 the assembler?). Shift counts in a register are truncated by ARM. Note
995 that the native compiler puts too large (> 32) immediate shift counts
996 into a register and shifts by the register, letting the ARM decide what
997 to do instead of doing that itself. */
998 #define SHIFT_COUNT_TRUNCATED 1
999
1000 /* All integers have the same format so truncation is easy. */
1001 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1002
1003 /* Define this if addresses of constant functions
1004 shouldn't be put through pseudo regs where they can be cse'd.
1005 Desirable on machines where ordinary constants are expensive
1006 but a CALL with constant address is cheap. */
1007 /* why is this defined??? -- dac */
1008 #define NO_FUNCTION_CSE 1
1009
1010 /* Chars and shorts should be passed as ints. */
1011 #define PROMOTE_PROTOTYPES 1
1012
1013 /* The machine modes of pointers and functions. */
1014 #define Pmode SImode
1015 #define FUNCTION_MODE Pmode
1016
1017 /* The relative costs of various types of constants. Note that cse.c defines
1018 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1019 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1020 case CONST_INT: \
1021 return mcore_const_costs (RTX, OUTER_CODE); \
1022 case CONST: \
1023 case LABEL_REF: \
1024 case SYMBOL_REF: \
1025 return 5; \
1026 case CONST_DOUBLE: \
1027 return 10;
1028
1029 /* provide the cost for an address calculation.
1030 All addressing modes cost the same on the MCore. */
1031 #define ADDRESS_COST(RTX) 1
1032
1033 /* Provide the cost of an rtl expression. */
1034 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1035 case AND: \
1036 return COSTS_N_INSNS (mcore_and_cost (X)); \
1037 case IOR: \
1038 return COSTS_N_INSNS (mcore_ior_cost (X)); \
1039 case DIV: \
1040 case UDIV: \
1041 case MOD: \
1042 case UMOD: \
1043 return COSTS_N_INSNS (100); \
1044 case FLOAT: \
1045 case FIX: \
1046 return 100;
1047
1048 /* Compute extra cost of moving data between one register class
1049 and another. All register moves are cheap. */
1050 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
1051
1052 #define WORD_REGISTER_OPERATIONS
1053
1054 /* Implicit library calls should use memcpy, not bcopy, etc. */
1055 #define TARGET_MEM_FUNCTIONS
1056
1057 /* Assembler output control. */
1058 #define ASM_COMMENT_START "\t//"
1059
1060 #define ASM_APP_ON "// inline asm begin\n"
1061 #define ASM_APP_OFF "// inline asm end\n"
1062
1063 #define FILE_ASM_OP "\t.file\n"
1064
1065 /* Switch to the text or data segment. */
1066 #define TEXT_SECTION_ASM_OP "\t.text"
1067 #define DATA_SECTION_ASM_OP "\t.data"
1068
1069 #undef EXTRA_SECTIONS
1070 #define EXTRA_SECTIONS SUBTARGET_EXTRA_SECTIONS
1071
1072 #undef EXTRA_SECTION_FUNCTIONS
1073 #define EXTRA_SECTION_FUNCTIONS \
1074 SUBTARGET_EXTRA_SECTION_FUNCTIONS \
1075 SWITCH_SECTION_FUNCTION
1076
1077 /* Switch to SECTION (an `enum in_section').
1078
1079 ??? This facility should be provided by GCC proper.
1080 The problem is that we want to temporarily switch sections in
1081 ASM_DECLARE_OBJECT_NAME and then switch back to the original section
1082 afterwards. */
1083 #define SWITCH_SECTION_FUNCTION \
1084 static void switch_to_section PARAMS ((enum in_section, tree)); \
1085 static void \
1086 switch_to_section (section, decl) \
1087 enum in_section section; \
1088 tree decl; \
1089 { \
1090 switch (section) \
1091 { \
1092 case in_text: text_section (); break; \
1093 case in_data: data_section (); break; \
1094 case in_named: named_section (decl, NULL, 0); break; \
1095 SUBTARGET_SWITCH_SECTIONS \
1096 default: abort (); break; \
1097 } \
1098 }
1099
1100 /* Switch into a generic section. */
1101 #undef TARGET_ASM_NAMED_SECTION
1102 #define TARGET_ASM_NAMED_SECTION mcore_asm_named_section
1103
1104 /* This is how to output an insn to push a register on the stack.
1105 It need not be very fast code. */
1106 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1107 fprintf (FILE, "\tsubi\t %s,%d\n\tstw\t %s,(%s)\n", \
1108 reg_names[STACK_POINTER_REGNUM], \
1109 (STACK_BOUNDARY / BITS_PER_UNIT), \
1110 reg_names[REGNO], \
1111 reg_names[STACK_POINTER_REGNUM])
1112
1113 /* Length in instructions of the code output by ASM_OUTPUT_REG_PUSH. */
1114 #define REG_PUSH_LENGTH 2
1115
1116 /* This is how to output an insn to pop a register from the stack. */
1117 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1118 fprintf (FILE, "\tldw\t %s,(%s)\n\taddi\t %s,%d\n", \
1119 reg_names[REGNO], \
1120 reg_names[STACK_POINTER_REGNUM], \
1121 reg_names[STACK_POINTER_REGNUM], \
1122 (STACK_BOUNDARY / BITS_PER_UNIT))
1123
1124
1125 /* Output a label definition. */
1126 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1127 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1128
1129 /* Output a reference to a label. */
1130 #undef ASM_OUTPUT_LABELREF
1131 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1132 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, MCORE_STRIP_NAME_ENCODING (NAME))
1133
1134
1135 /* This is how to output an assembler line
1136 that says to advance the location counter
1137 to a multiple of 2**LOG bytes. */
1138 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1139 if ((LOG) != 0) \
1140 fprintf (FILE, "\t.align\t%d\n", LOG)
1141
1142 #ifndef ASM_DECLARE_RESULT
1143 #define ASM_DECLARE_RESULT(FILE, RESULT)
1144 #endif
1145
1146 /* Strip export encoding from a function name. */
1147 #define MCORE_STRIP_NAME_ENCODING(SYM_NAME) \
1148 ((SYM_NAME) + ((SYM_NAME)[0] == '@' ? 3 : 0))
1149
1150 /* Strip any text from SYM_NAME added by ENCODE_SECTION_INFO and store
1151 the result in VAR. */
1152 #undef STRIP_NAME_ENCODING
1153 #define STRIP_NAME_ENCODING(VAR, SYM_NAME) \
1154 (VAR) = MCORE_STRIP_NAME_ENCODING (SYM_NAME)
1155
1156 #undef UNIQUE_SECTION
1157 #define UNIQUE_SECTION(DECL, RELOC) mcore_unique_section (DECL, RELOC)
1158
1159 #define MULTIPLE_SYMBOL_SPACES 1
1160
1161 #define SUPPORTS_ONE_ONLY 1
1162
1163 /* A pair of macros to output things for the callgraph data.
1164 VALUE means (to the tools that reads this info later):
1165 0 a call from src to dst
1166 1 the call is special (e.g. dst is "unknown" or "alloca")
1167 2 the call is special (e.g., the src is a table instead of routine)
1168
1169 Frame sizes are augmented with timestamps to help later tools
1170 differentiate between static entities with same names in different
1171 files. */
1172 extern long mcore_current_compilation_timestamp;
1173 #define ASM_OUTPUT_CG_NODE(FILE,SRCNAME,VALUE) \
1174 do \
1175 { \
1176 if (mcore_current_compilation_timestamp == 0) \
1177 mcore_current_compilation_timestamp = time (0); \
1178 fprintf ((FILE),"\t.equ\t__$frame$size$_%s_$_%08lx,%d\n", \
1179 (SRCNAME), mcore_current_compilation_timestamp, (VALUE)); \
1180 } \
1181 while (0)
1182
1183 #define ASM_OUTPUT_CG_EDGE(FILE,SRCNAME,DSTNAME,VALUE) \
1184 do \
1185 { \
1186 fprintf ((FILE),"\t.equ\t__$function$call$_%s_$_%s,%d\n", \
1187 (SRCNAME), (DSTNAME), (VALUE)); \
1188 } \
1189 while (0)
1190
1191 /* Output a globalising directive for a label. */
1192 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1193 (fprintf (STREAM, "\t.export\t"), \
1194 assemble_name (STREAM, NAME), \
1195 fputc ('\n',STREAM)) \
1196
1197 /* The prefix to add to user-visible assembler symbols. */
1198 #undef USER_LABEL_PREFIX
1199 #define USER_LABEL_PREFIX ""
1200
1201 /* Make an internal label into a string. */
1202 #undef ASM_GENERATE_INTERNAL_LABEL
1203 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1204 sprintf (STRING, "*.%s%ld", PREFIX, (long) NUM)
1205
1206 /* Output an internal label definition. */
1207 #undef ASM_OUTPUT_INTERNAL_LABEL
1208 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1209 fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1210
1211 /* Construct a private name. */
1212 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1213 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1214 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1215
1216 /* Jump tables must be 32 bit aligned. */
1217 #undef ASM_OUTPUT_CASE_LABEL
1218 #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
1219 fprintf (STREAM, "\t.align 2\n.%s%d:\n", PREFIX, NUM);
1220
1221 /* Output a relative address. Not needed since jump tables are absolute
1222 but we must define it anyway. */
1223 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1224 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1225
1226 /* Output an element of a dispatch table. */
1227 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1228 fprintf (STREAM, "\t.long\t.L%d\n", VALUE)
1229
1230 /* Output various types of constants. */
1231
1232 /* This is how to output an assembler line
1233 that says to advance the location counter by SIZE bytes. */
1234 #undef ASM_OUTPUT_SKIP
1235 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1236 fprintf (FILE, "\t.fill %d, 1\n", (SIZE))
1237
1238 /* This says how to output an assembler line
1239 to define a global common symbol, with alignment information. */
1240 /* XXX - for now we ignore the alignment. */
1241 #undef ASM_OUTPUT_ALIGNED_COMMON
1242 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1243 do \
1244 { \
1245 if (mcore_dllexport_name_p (NAME)) \
1246 MCORE_EXPORT_NAME (FILE, NAME) \
1247 if (! mcore_dllimport_name_p (NAME)) \
1248 { \
1249 fputs ("\t.comm\t", FILE); \
1250 assemble_name (FILE, NAME); \
1251 fprintf (FILE, ",%d\n", SIZE); \
1252 } \
1253 } \
1254 while (0)
1255
1256 /* This says how to output an assembler line
1257 to define an external symbol. */
1258 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1259 do \
1260 { \
1261 fputs ("\t.import\t", (FILE)); \
1262 assemble_name ((FILE), (NAME)); \
1263 fputs ("\n", (FILE)); \
1264 } \
1265 while (0)
1266
1267 #undef ASM_OUTPUT_EXTERNAL
1268 /* RBE: we undefined this and let gas do it's "undefined is imported"
1269 games. This is because when we use this, we get a marked
1270 reference through the call to assemble_name and this forces C++
1271 inlined member functions (or any inlined function) to be instantiated
1272 regardless of whether any callsites remain.
1273 This makes this aspect of the compiler non-ABI compliant. */
1274
1275 /* Similar, but for libcall. FUN is an rtx. */
1276 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
1277 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1278 do \
1279 { \
1280 fprintf (FILE, "\t.import\t"); \
1281 assemble_name (FILE, XSTR (FUN, 0)); \
1282 fprintf (FILE, "\n"); \
1283 } \
1284 while (0)
1285
1286
1287 /* This says how to output an assembler line
1288 to define a local common symbol... */
1289 #undef ASM_OUTPUT_LOCAL
1290 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1291 (fputs ("\t.lcomm\t", FILE), \
1292 assemble_name (FILE, NAME), \
1293 fprintf (FILE, ",%d\n", SIZE))
1294
1295 /* ... and how to define a local common symbol whose alignment
1296 we wish to specify. ALIGN comes in as bits, we have to turn
1297 it into bytes. */
1298 #undef ASM_OUTPUT_ALIGNED_LOCAL
1299 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1300 do \
1301 { \
1302 fputs ("\t.bss\t", (FILE)); \
1303 assemble_name ((FILE), (NAME)); \
1304 fprintf ((FILE), ",%d,%d\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1305 } \
1306 while (0)
1307
1308 /* We must mark dll symbols specially. Definitions of dllexport'd objects
1309 install some info in the .drective (PE) or .exports (ELF) sections. */
1310 #undef ENCODE_SECTION_INFO
1311 #define ENCODE_SECTION_INFO(DECL, FIRST) \
1312 mcore_encode_section_info (DECL, FIRST)
1313
1314 /* Print operand X (an rtx) in assembler syntax to file FILE.
1315 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1316 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1317 #define PRINT_OPERAND(STREAM, X, CODE) mcore_print_operand (STREAM, X, CODE)
1318
1319 /* Print a memory address as an operand to reference that memory location. */
1320 #define PRINT_OPERAND_ADDRESS(STREAM,X) mcore_print_operand_address (STREAM, X)
1321
1322 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1323 ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
1324
1325 /* This is to handle loads from the constant pool. */
1326 #define MACHINE_DEPENDENT_REORG(X) mcore_dependent_reorg (X)
1327
1328 #define PREDICATE_CODES \
1329 { "mcore_arith_reg_operand", { REG, SUBREG }}, \
1330 { "mcore_general_movsrc_operand", { MEM, CONST_INT, REG, SUBREG }},\
1331 { "mcore_general_movdst_operand", { MEM, CONST_INT, REG, SUBREG }},\
1332 { "mcore_reload_operand", { MEM, REG, SUBREG }}, \
1333 { "mcore_arith_J_operand", { CONST_INT, REG, SUBREG }}, \
1334 { "mcore_arith_K_operand", { CONST_INT, REG, SUBREG }}, \
1335 { "mcore_arith_K_operand_not_0", { CONST_INT, REG, SUBREG }}, \
1336 { "mcore_arith_M_operand", { CONST_INT, REG, SUBREG }}, \
1337 { "mcore_arith_K_S_operand", { CONST_INT, REG, SUBREG }}, \
1338 { "mcore_arith_O_operand", { CONST_INT, REG, SUBREG }}, \
1339 { "mcore_arith_imm_operand", { CONST_INT, REG, SUBREG }}, \
1340 { "mcore_arith_any_imm_operand", { CONST_INT, REG, SUBREG }}, \
1341 { "mcore_literal_K_operand", { CONST_INT }}, \
1342 { "mcore_addsub_operand", { CONST_INT, REG, SUBREG }}, \
1343 { "mcore_compare_operand", { CONST_INT, REG, SUBREG }}, \
1344 { "mcore_load_multiple_operation", { PARALLEL }}, \
1345 { "mcore_store_multiple_operation", { PARALLEL }}, \
1346 { "mcore_call_address_operand", { REG, SUBREG, CONST_INT }}, \
1347
1348 #endif /* ! GCC_MCORE_H */