1 ;; Pipeline model for Loongson gs264e cores.
3 ;; Copyright (C) 2018-2021 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Uncomment the following line to output automata for debugging.
22 ;; (automata_option "v")
24 ;; Automaton for integer instructions.
25 (define_automaton "gs264e_a_alu")
27 ;; Automaton for floating-point instructions.
28 (define_automaton "gs264e_a_falu")
30 ;; Automaton for memory operations.
31 (define_automaton "gs264e_a_mem")
33 ;; Describe the resources.
35 (define_cpu_unit "gs264e_alu1" "gs264e_a_alu")
36 (define_cpu_unit "gs264e_mem1" "gs264e_a_mem")
37 (define_cpu_unit "gs264e_falu1" "gs264e_a_falu")
39 ;; Describe instruction reservations.
41 (define_insn_reservation "gs264e_arith" 1
42 (and (eq_attr "cpu" "gs264e")
43 (eq_attr "type" "arith,clz,const,logical,
44 move,nop,shift,signext,slt"))
47 (define_insn_reservation "gs264e_branch" 1
48 (and (eq_attr "cpu" "gs264e")
49 (eq_attr "type" "branch,jump,call,condmove,trap"))
52 (define_insn_reservation "gs264e_mfhilo" 1
53 (and (eq_attr "cpu" "gs264e")
54 (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
57 ;; Operation imul3nc is fully pipelined.
58 (define_insn_reservation "gs264e_imul3nc" 7
59 (and (eq_attr "cpu" "gs264e")
60 (eq_attr "type" "imul3nc"))
63 (define_insn_reservation "gs264e_imul" 7
64 (and (eq_attr "cpu" "gs264e")
65 (eq_attr "type" "imul,imadd"))
68 (define_insn_reservation "gs264e_idiv_si" 12
69 (and (eq_attr "cpu" "gs264e")
70 (and (eq_attr "type" "idiv")
71 (eq_attr "mode" "SI")))
74 (define_insn_reservation "gs264e_idiv_di" 25
75 (and (eq_attr "cpu" "gs264e")
76 (and (eq_attr "type" "idiv")
77 (eq_attr "mode" "DI")))
80 (define_insn_reservation "gs264e_load" 4
81 (and (eq_attr "cpu" "gs264e")
82 (eq_attr "type" "load"))
85 (define_insn_reservation "gs264e_fpload" 4
86 (and (eq_attr "cpu" "gs264e")
87 (eq_attr "type" "load,mfc,mtc"))
90 (define_insn_reservation "gs264e_prefetch" 0
91 (and (eq_attr "cpu" "gs264e")
92 (eq_attr "type" "prefetch,prefetchx"))
95 (define_insn_reservation "gs264e_store" 0
96 (and (eq_attr "cpu" "gs264e")
97 (eq_attr "type" "store,fpstore,fpidxstore"))
100 (define_insn_reservation "gs264e_fadd" 4
101 (and (eq_attr "cpu" "gs264e")
102 (eq_attr "type" "fadd,fmul,fmadd"))
105 (define_insn_reservation "gs264e_fcmp" 2
106 (and (eq_attr "cpu" "gs264e")
107 (eq_attr "type" "fabs,fcmp,fmove,fneg"))
110 (define_insn_reservation "gs264e_fcvt" 4
111 (and (eq_attr "cpu" "gs264e")
112 (eq_attr "type" "fcvt"))
115 (define_insn_reservation "gs264e_fdiv_sf" 12
116 (and (eq_attr "cpu" "gs264e")
117 (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
118 (eq_attr "mode" "SF")))
121 (define_insn_reservation "gs264e_fdiv_df" 19
122 (and (eq_attr "cpu" "gs264e")
123 (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
124 (eq_attr "mode" "DF")))
127 ;; Force single-dispatch for unknown or multi.
128 (define_insn_reservation "gs264e_unknown" 1
129 (and (eq_attr "cpu" "gs264e")
130 (eq_attr "type" "unknown,multi,atomic,syncloop"))
131 "gs264e_alu1 + gs264e_falu1 + gs264e_mem1")
133 ;; End of DFA-based pipeline description for gs264e