1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type
{
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting
{
153 R10K_CACHE_BARRIER_NONE
,
154 R10K_CACHE_BARRIER_STORE
,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type
{
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type
{
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET
,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY
,
201 MIPS_BUILTIN_CMP_ALL
,
202 MIPS_BUILTIN_CMP_UPPER
,
203 MIPS_BUILTIN_CMP_LOWER
,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE
,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition
{
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions
[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY
)
243 /* Information about a function's frame layout. */
244 struct mips_frame_info
GTY(()) {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size
;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size
;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size
;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size
;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* Likewise doubleword accumulator X ($acX). */
265 unsigned int acc_mask
;
267 /* The number of GPRs, FPRs, doubleword accumulators and COP0
271 unsigned int num_acc
;
272 unsigned int num_cop0_regs
;
274 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
275 save slots from the top of the frame, or zero if no such slots are
277 HOST_WIDE_INT gp_save_offset
;
278 HOST_WIDE_INT fp_save_offset
;
279 HOST_WIDE_INT acc_save_offset
;
280 HOST_WIDE_INT cop0_save_offset
;
282 /* Likewise, but giving offsets from the bottom of the frame. */
283 HOST_WIDE_INT gp_sp_offset
;
284 HOST_WIDE_INT fp_sp_offset
;
285 HOST_WIDE_INT acc_sp_offset
;
286 HOST_WIDE_INT cop0_sp_offset
;
288 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
289 HOST_WIDE_INT arg_pointer_offset
;
291 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
292 HOST_WIDE_INT hard_frame_pointer_offset
;
295 struct machine_function
GTY(()) {
296 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
297 rtx mips16_gp_pseudo_rtx
;
299 /* The number of extra stack bytes taken up by register varargs.
300 This area is allocated by the callee at the very top of the frame. */
303 /* The current frame information, calculated by mips_compute_frame_info. */
304 struct mips_frame_info frame
;
306 /* The register to use as the function's global pointer, or INVALID_REGNUM
307 if the function doesn't need one. */
308 unsigned int global_pointer
;
310 /* True if mips_adjust_insn_length should ignore an instruction's
312 bool ignore_hazard_length_p
;
314 /* True if the whole function is suitable for .set noreorder and
316 bool all_noreorder_p
;
318 /* True if the function is known to have an instruction that needs $gp. */
321 /* True if we have emitted an instruction to initialize
322 mips16_gp_pseudo_rtx. */
323 bool initialized_mips16_gp_pseudo_p
;
325 /* True if this is an interrupt handler. */
326 bool interrupt_handler_p
;
328 /* True if this is an interrupt handler that uses shadow registers. */
329 bool use_shadow_register_set_p
;
331 /* True if this is an interrupt handler that should keep interrupts
333 bool keep_interrupts_masked_p
;
335 /* True if this is an interrupt handler that should use DERET
337 bool use_debug_exception_return_p
;
340 /* Information about a single argument. */
341 struct mips_arg_info
{
342 /* True if the argument is passed in a floating-point register, or
343 would have been if we hadn't run out of registers. */
346 /* The number of words passed in registers, rounded up. */
347 unsigned int reg_words
;
349 /* For EABI, the offset of the first register from GP_ARG_FIRST or
350 FP_ARG_FIRST. For other ABIs, the offset of the first register from
351 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
352 comment for details).
354 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
356 unsigned int reg_offset
;
358 /* The number of words that must be passed on the stack, rounded up. */
359 unsigned int stack_words
;
361 /* The offset from the start of the stack overflow area of the argument's
362 first stack word. Only meaningful when STACK_WORDS is nonzero. */
363 unsigned int stack_offset
;
366 /* Information about an address described by mips_address_type.
372 REG is the base register and OFFSET is the constant offset.
375 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
376 is the type of symbol it references.
379 SYMBOL_TYPE is the type of symbol that the address references. */
380 struct mips_address_info
{
381 enum mips_address_type type
;
384 enum mips_symbol_type symbol_type
;
387 /* One stage in a constant building sequence. These sequences have
391 A = A CODE[1] VALUE[1]
392 A = A CODE[2] VALUE[2]
395 where A is an accumulator, each CODE[i] is a binary rtl operation
396 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
397 struct mips_integer_op
{
399 unsigned HOST_WIDE_INT value
;
402 /* The largest number of operations needed to load an integer constant.
403 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
404 When the lowest bit is clear, we can try, but reject a sequence with
405 an extra SLL at the end. */
406 #define MIPS_MAX_INTEGER_OPS 7
408 /* Information about a MIPS16e SAVE or RESTORE instruction. */
409 struct mips16e_save_restore_info
{
410 /* The number of argument registers saved by a SAVE instruction.
411 0 for RESTORE instructions. */
414 /* Bit X is set if the instruction saves or restores GPR X. */
417 /* The total number of bytes to allocate. */
421 /* Global variables for machine-dependent things. */
423 /* The -G setting, or the configuration's default small-data limit if
424 no -G option is given. */
425 static unsigned int mips_small_data_threshold
;
427 /* The number of file directives written by mips_output_filename. */
428 int num_source_filenames
;
430 /* The name that appeared in the last .file directive written by
431 mips_output_filename, or "" if mips_output_filename hasn't
432 written anything yet. */
433 const char *current_function_file
= "";
435 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
438 /* Arrays that map GCC register numbers to debugger register numbers. */
439 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
440 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
442 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
447 /* True if we're writing out a branch-likely instruction rather than a
449 static bool mips_branch_likely
;
451 /* The operands passed to the last cmpMM expander. */
454 /* The current instruction-set architecture. */
455 enum processor_type mips_arch
;
456 const struct mips_cpu_info
*mips_arch_info
;
458 /* The processor that we should tune the code for. */
459 enum processor_type mips_tune
;
460 const struct mips_cpu_info
*mips_tune_info
;
462 /* The ISA level associated with mips_arch. */
465 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
466 static const struct mips_cpu_info
*mips_isa_option_info
;
468 /* Which ABI to use. */
469 int mips_abi
= MIPS_ABI_DEFAULT
;
471 /* Which cost information to use. */
472 const struct mips_rtx_cost_data
*mips_cost
;
474 /* The ambient target flags, excluding MASK_MIPS16. */
475 static int mips_base_target_flags
;
477 /* True if MIPS16 is the default mode. */
478 bool mips_base_mips16
;
480 /* The ambient values of other global variables. */
481 static int mips_base_schedule_insns
; /* flag_schedule_insns */
482 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
483 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
484 static int mips_base_align_loops
; /* align_loops */
485 static int mips_base_align_jumps
; /* align_jumps */
486 static int mips_base_align_functions
; /* align_functions */
488 /* The -mcode-readable setting. */
489 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
491 /* The -mr10k-cache-barrier setting. */
492 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier
;
494 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
495 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
497 /* Index C is true if character C is a valid PRINT_OPERAND punctation
499 bool mips_print_operand_punct
[256];
501 static GTY (()) int mips_output_filename_first_time
= 1;
503 /* mips_split_p[X] is true if symbols of type X can be split by
504 mips_split_symbol. */
505 bool mips_split_p
[NUM_SYMBOL_TYPES
];
507 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
508 can be split by mips_split_symbol. */
509 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
511 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
512 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
513 if they are matched by a special .md file pattern. */
514 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
516 /* Likewise for HIGHs. */
517 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
519 /* Index R is the smallest register class that contains register R. */
520 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
521 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
522 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
523 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
524 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
525 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
526 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
527 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
528 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
529 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
530 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
531 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
532 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
533 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
534 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
535 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
536 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
537 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
538 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
539 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
540 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
541 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
542 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
543 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
544 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
545 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
546 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
547 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
548 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
549 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
550 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
551 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
552 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
553 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
554 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
555 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
556 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
557 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
558 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
559 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
560 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
561 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
562 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
563 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
564 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
565 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
566 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
567 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
570 /* The value of TARGET_ATTRIBUTE_TABLE. */
571 const struct attribute_spec mips_attribute_table
[] = {
572 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
573 { "long_call", 0, 0, false, true, true, NULL
},
574 { "far", 0, 0, false, true, true, NULL
},
575 { "near", 0, 0, false, true, true, NULL
},
576 /* We would really like to treat "mips16" and "nomips16" as type
577 attributes, but GCC doesn't provide the hooks we need to support
578 the right conversion rules. As declaration attributes, they affect
579 code generation but don't carry other semantics. */
580 { "mips16", 0, 0, true, false, false, NULL
},
581 { "nomips16", 0, 0, true, false, false, NULL
},
582 /* Allow functions to be specified as interrupt handlers */
583 { "interrupt", 0, 0, false, true, true, NULL
},
584 { "use_shadow_register_set", 0, 0, false, true, true, NULL
},
585 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
},
586 { "use_debug_exception_return", 0, 0, false, true, true, NULL
},
587 { NULL
, 0, 0, false, false, false, NULL
}
590 /* A table describing all the processors GCC knows about. Names are
591 matched in the order listed. The first mention of an ISA level is
592 taken as the canonical name for that ISA.
594 To ease comparison, please keep this table in the same order
595 as GAS's mips_cpu_info_table. Please also make sure that
596 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
597 options correctly. */
598 static const struct mips_cpu_info mips_cpu_info_table
[] = {
599 /* Entries for generic ISAs. */
600 { "mips1", PROCESSOR_R3000
, 1, 0 },
601 { "mips2", PROCESSOR_R6000
, 2, 0 },
602 { "mips3", PROCESSOR_R4000
, 3, 0 },
603 { "mips4", PROCESSOR_R8000
, 4, 0 },
604 /* Prefer not to use branch-likely instructions for generic MIPS32rX
605 and MIPS64rX code. The instructions were officially deprecated
606 in revisions 2 and earlier, but revision 3 is likely to downgrade
607 that to a recommendation to avoid the instructions in code that
608 isn't tuned to a specific processor. */
609 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
610 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
611 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
612 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
613 { "mips64r2", PROCESSOR_5KC
, 65, PTF_AVOID_BRANCHLIKELY
},
615 /* MIPS I processors. */
616 { "r3000", PROCESSOR_R3000
, 1, 0 },
617 { "r2000", PROCESSOR_R3000
, 1, 0 },
618 { "r3900", PROCESSOR_R3900
, 1, 0 },
620 /* MIPS II processors. */
621 { "r6000", PROCESSOR_R6000
, 2, 0 },
623 /* MIPS III processors. */
624 { "r4000", PROCESSOR_R4000
, 3, 0 },
625 { "vr4100", PROCESSOR_R4100
, 3, 0 },
626 { "vr4111", PROCESSOR_R4111
, 3, 0 },
627 { "vr4120", PROCESSOR_R4120
, 3, 0 },
628 { "vr4130", PROCESSOR_R4130
, 3, 0 },
629 { "vr4300", PROCESSOR_R4300
, 3, 0 },
630 { "r4400", PROCESSOR_R4000
, 3, 0 },
631 { "r4600", PROCESSOR_R4600
, 3, 0 },
632 { "orion", PROCESSOR_R4600
, 3, 0 },
633 { "r4650", PROCESSOR_R4650
, 3, 0 },
634 /* ST Loongson 2E/2F processors. */
635 { "loongson2e", PROCESSOR_LOONGSON_2E
, 3, PTF_AVOID_BRANCHLIKELY
},
636 { "loongson2f", PROCESSOR_LOONGSON_2F
, 3, PTF_AVOID_BRANCHLIKELY
},
638 /* MIPS IV processors. */
639 { "r8000", PROCESSOR_R8000
, 4, 0 },
640 { "r10000", PROCESSOR_R10000
, 4, 0 },
641 { "r12000", PROCESSOR_R10000
, 4, 0 },
642 { "r14000", PROCESSOR_R10000
, 4, 0 },
643 { "r16000", PROCESSOR_R10000
, 4, 0 },
644 { "vr5000", PROCESSOR_R5000
, 4, 0 },
645 { "vr5400", PROCESSOR_R5400
, 4, 0 },
646 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
647 { "rm7000", PROCESSOR_R7000
, 4, 0 },
648 { "rm9000", PROCESSOR_R9000
, 4, 0 },
650 /* MIPS32 processors. */
651 { "4kc", PROCESSOR_4KC
, 32, 0 },
652 { "4km", PROCESSOR_4KC
, 32, 0 },
653 { "4kp", PROCESSOR_4KP
, 32, 0 },
654 { "4ksc", PROCESSOR_4KC
, 32, 0 },
656 /* MIPS32 Release 2 processors. */
657 { "m4k", PROCESSOR_M4K
, 33, 0 },
658 { "4kec", PROCESSOR_4KC
, 33, 0 },
659 { "4kem", PROCESSOR_4KC
, 33, 0 },
660 { "4kep", PROCESSOR_4KP
, 33, 0 },
661 { "4ksd", PROCESSOR_4KC
, 33, 0 },
663 { "24kc", PROCESSOR_24KC
, 33, 0 },
664 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
665 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
666 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
667 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
668 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
670 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP. */
671 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
672 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
673 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
674 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
675 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
677 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP. */
678 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
679 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
680 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
681 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
682 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
684 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2. */
685 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
686 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
687 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
688 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
689 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
690 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
692 /* MIPS64 processors. */
693 { "5kc", PROCESSOR_5KC
, 64, 0 },
694 { "5kf", PROCESSOR_5KF
, 64, 0 },
695 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
696 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
697 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
698 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
699 { "xlr", PROCESSOR_XLR
, 64, 0 },
701 /* MIPS64 Release 2 processors. */
702 { "octeon", PROCESSOR_OCTEON
, 65, PTF_AVOID_BRANCHLIKELY
}
705 /* Default costs. If these are used for a processor we should look
706 up the actual costs. */
707 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
708 COSTS_N_INSNS (7), /* fp_mult_sf */ \
709 COSTS_N_INSNS (8), /* fp_mult_df */ \
710 COSTS_N_INSNS (23), /* fp_div_sf */ \
711 COSTS_N_INSNS (36), /* fp_div_df */ \
712 COSTS_N_INSNS (10), /* int_mult_si */ \
713 COSTS_N_INSNS (10), /* int_mult_di */ \
714 COSTS_N_INSNS (69), /* int_div_si */ \
715 COSTS_N_INSNS (69), /* int_div_di */ \
716 2, /* branch_cost */ \
717 4 /* memory_latency */
719 /* Floating-point costs for processors without an FPU. Just assume that
720 all floating-point libcalls are very expensive. */
721 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
722 COSTS_N_INSNS (256), /* fp_mult_sf */ \
723 COSTS_N_INSNS (256), /* fp_mult_df */ \
724 COSTS_N_INSNS (256), /* fp_div_sf */ \
725 COSTS_N_INSNS (256) /* fp_div_df */
727 /* Costs to use when optimizing for size. */
728 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
729 COSTS_N_INSNS (1), /* fp_add */
730 COSTS_N_INSNS (1), /* fp_mult_sf */
731 COSTS_N_INSNS (1), /* fp_mult_df */
732 COSTS_N_INSNS (1), /* fp_div_sf */
733 COSTS_N_INSNS (1), /* fp_div_df */
734 COSTS_N_INSNS (1), /* int_mult_si */
735 COSTS_N_INSNS (1), /* int_mult_di */
736 COSTS_N_INSNS (1), /* int_div_si */
737 COSTS_N_INSNS (1), /* int_div_di */
739 4 /* memory_latency */
742 /* Costs to use when optimizing for speed, indexed by processor. */
743 static const struct mips_rtx_cost_data mips_rtx_cost_data
[PROCESSOR_MAX
] = {
745 COSTS_N_INSNS (2), /* fp_add */
746 COSTS_N_INSNS (4), /* fp_mult_sf */
747 COSTS_N_INSNS (5), /* fp_mult_df */
748 COSTS_N_INSNS (12), /* fp_div_sf */
749 COSTS_N_INSNS (19), /* fp_div_df */
750 COSTS_N_INSNS (12), /* int_mult_si */
751 COSTS_N_INSNS (12), /* int_mult_di */
752 COSTS_N_INSNS (35), /* int_div_si */
753 COSTS_N_INSNS (35), /* int_div_di */
755 4 /* memory_latency */
759 COSTS_N_INSNS (6), /* int_mult_si */
760 COSTS_N_INSNS (6), /* int_mult_di */
761 COSTS_N_INSNS (36), /* int_div_si */
762 COSTS_N_INSNS (36), /* int_div_di */
764 4 /* memory_latency */
768 COSTS_N_INSNS (36), /* int_mult_si */
769 COSTS_N_INSNS (36), /* int_mult_di */
770 COSTS_N_INSNS (37), /* int_div_si */
771 COSTS_N_INSNS (37), /* int_div_di */
773 4 /* memory_latency */
777 COSTS_N_INSNS (4), /* int_mult_si */
778 COSTS_N_INSNS (11), /* int_mult_di */
779 COSTS_N_INSNS (36), /* int_div_si */
780 COSTS_N_INSNS (68), /* int_div_di */
782 4 /* memory_latency */
785 COSTS_N_INSNS (4), /* fp_add */
786 COSTS_N_INSNS (4), /* fp_mult_sf */
787 COSTS_N_INSNS (5), /* fp_mult_df */
788 COSTS_N_INSNS (17), /* fp_div_sf */
789 COSTS_N_INSNS (32), /* fp_div_df */
790 COSTS_N_INSNS (4), /* int_mult_si */
791 COSTS_N_INSNS (11), /* int_mult_di */
792 COSTS_N_INSNS (36), /* int_div_si */
793 COSTS_N_INSNS (68), /* int_div_di */
795 4 /* memory_latency */
798 COSTS_N_INSNS (4), /* fp_add */
799 COSTS_N_INSNS (4), /* fp_mult_sf */
800 COSTS_N_INSNS (5), /* fp_mult_df */
801 COSTS_N_INSNS (17), /* fp_div_sf */
802 COSTS_N_INSNS (32), /* fp_div_df */
803 COSTS_N_INSNS (4), /* int_mult_si */
804 COSTS_N_INSNS (7), /* int_mult_di */
805 COSTS_N_INSNS (42), /* int_div_si */
806 COSTS_N_INSNS (72), /* int_div_di */
808 4 /* memory_latency */
812 COSTS_N_INSNS (5), /* int_mult_si */
813 COSTS_N_INSNS (5), /* int_mult_di */
814 COSTS_N_INSNS (41), /* int_div_si */
815 COSTS_N_INSNS (41), /* int_div_di */
817 4 /* memory_latency */
820 COSTS_N_INSNS (8), /* fp_add */
821 COSTS_N_INSNS (8), /* fp_mult_sf */
822 COSTS_N_INSNS (10), /* fp_mult_df */
823 COSTS_N_INSNS (34), /* fp_div_sf */
824 COSTS_N_INSNS (64), /* fp_div_df */
825 COSTS_N_INSNS (5), /* int_mult_si */
826 COSTS_N_INSNS (5), /* int_mult_di */
827 COSTS_N_INSNS (41), /* int_div_si */
828 COSTS_N_INSNS (41), /* int_div_di */
830 4 /* memory_latency */
833 COSTS_N_INSNS (4), /* fp_add */
834 COSTS_N_INSNS (4), /* fp_mult_sf */
835 COSTS_N_INSNS (5), /* fp_mult_df */
836 COSTS_N_INSNS (17), /* fp_div_sf */
837 COSTS_N_INSNS (32), /* fp_div_df */
838 COSTS_N_INSNS (5), /* int_mult_si */
839 COSTS_N_INSNS (5), /* int_mult_di */
840 COSTS_N_INSNS (41), /* int_div_si */
841 COSTS_N_INSNS (41), /* int_div_di */
843 4 /* memory_latency */
847 COSTS_N_INSNS (5), /* int_mult_si */
848 COSTS_N_INSNS (5), /* int_mult_di */
849 COSTS_N_INSNS (41), /* int_div_si */
850 COSTS_N_INSNS (41), /* int_div_di */
852 4 /* memory_latency */
855 COSTS_N_INSNS (8), /* fp_add */
856 COSTS_N_INSNS (8), /* fp_mult_sf */
857 COSTS_N_INSNS (10), /* fp_mult_df */
858 COSTS_N_INSNS (34), /* fp_div_sf */
859 COSTS_N_INSNS (64), /* fp_div_df */
860 COSTS_N_INSNS (5), /* int_mult_si */
861 COSTS_N_INSNS (5), /* int_mult_di */
862 COSTS_N_INSNS (41), /* int_div_si */
863 COSTS_N_INSNS (41), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (4), /* fp_add */
869 COSTS_N_INSNS (4), /* fp_mult_sf */
870 COSTS_N_INSNS (5), /* fp_mult_df */
871 COSTS_N_INSNS (17), /* fp_div_sf */
872 COSTS_N_INSNS (32), /* fp_div_df */
873 COSTS_N_INSNS (5), /* int_mult_si */
874 COSTS_N_INSNS (5), /* int_mult_di */
875 COSTS_N_INSNS (41), /* int_div_si */
876 COSTS_N_INSNS (41), /* int_div_di */
878 4 /* memory_latency */
881 COSTS_N_INSNS (6), /* fp_add */
882 COSTS_N_INSNS (6), /* fp_mult_sf */
883 COSTS_N_INSNS (7), /* fp_mult_df */
884 COSTS_N_INSNS (25), /* fp_div_sf */
885 COSTS_N_INSNS (48), /* fp_div_df */
886 COSTS_N_INSNS (5), /* int_mult_si */
887 COSTS_N_INSNS (5), /* int_mult_di */
888 COSTS_N_INSNS (41), /* int_div_si */
889 COSTS_N_INSNS (41), /* int_div_di */
891 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (72), /* int_div_si */
908 COSTS_N_INSNS (72), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (2), /* fp_add */
914 COSTS_N_INSNS (4), /* fp_mult_sf */
915 COSTS_N_INSNS (5), /* fp_mult_df */
916 COSTS_N_INSNS (12), /* fp_div_sf */
917 COSTS_N_INSNS (19), /* fp_div_df */
918 COSTS_N_INSNS (2), /* int_mult_si */
919 COSTS_N_INSNS (2), /* int_mult_di */
920 COSTS_N_INSNS (35), /* int_div_si */
921 COSTS_N_INSNS (35), /* int_div_di */
923 4 /* memory_latency */
926 COSTS_N_INSNS (3), /* fp_add */
927 COSTS_N_INSNS (5), /* fp_mult_sf */
928 COSTS_N_INSNS (6), /* fp_mult_df */
929 COSTS_N_INSNS (15), /* fp_div_sf */
930 COSTS_N_INSNS (16), /* fp_div_df */
931 COSTS_N_INSNS (17), /* int_mult_si */
932 COSTS_N_INSNS (17), /* int_mult_di */
933 COSTS_N_INSNS (38), /* int_div_si */
934 COSTS_N_INSNS (38), /* int_div_di */
936 6 /* memory_latency */
939 COSTS_N_INSNS (6), /* fp_add */
940 COSTS_N_INSNS (7), /* fp_mult_sf */
941 COSTS_N_INSNS (8), /* fp_mult_df */
942 COSTS_N_INSNS (23), /* fp_div_sf */
943 COSTS_N_INSNS (36), /* fp_div_df */
944 COSTS_N_INSNS (10), /* int_mult_si */
945 COSTS_N_INSNS (10), /* int_mult_di */
946 COSTS_N_INSNS (69), /* int_div_si */
947 COSTS_N_INSNS (69), /* int_div_di */
949 6 /* memory_latency */
961 /* The only costs that appear to be updated here are
962 integer multiplication. */
964 COSTS_N_INSNS (4), /* int_mult_si */
965 COSTS_N_INSNS (6), /* int_mult_di */
966 COSTS_N_INSNS (69), /* int_div_si */
967 COSTS_N_INSNS (69), /* int_div_di */
969 4 /* memory_latency */
981 COSTS_N_INSNS (6), /* fp_add */
982 COSTS_N_INSNS (4), /* fp_mult_sf */
983 COSTS_N_INSNS (5), /* fp_mult_df */
984 COSTS_N_INSNS (23), /* fp_div_sf */
985 COSTS_N_INSNS (36), /* fp_div_df */
986 COSTS_N_INSNS (5), /* int_mult_si */
987 COSTS_N_INSNS (5), /* int_mult_di */
988 COSTS_N_INSNS (36), /* int_div_si */
989 COSTS_N_INSNS (36), /* int_div_di */
991 4 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (5), /* fp_mult_sf */
996 COSTS_N_INSNS (6), /* fp_mult_df */
997 COSTS_N_INSNS (30), /* fp_div_sf */
998 COSTS_N_INSNS (59), /* fp_div_df */
999 COSTS_N_INSNS (3), /* int_mult_si */
1000 COSTS_N_INSNS (4), /* int_mult_di */
1001 COSTS_N_INSNS (42), /* int_div_si */
1002 COSTS_N_INSNS (74), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (5), /* fp_mult_sf */
1009 COSTS_N_INSNS (6), /* fp_mult_df */
1010 COSTS_N_INSNS (30), /* fp_div_sf */
1011 COSTS_N_INSNS (59), /* fp_div_df */
1012 COSTS_N_INSNS (5), /* int_mult_si */
1013 COSTS_N_INSNS (9), /* int_mult_di */
1014 COSTS_N_INSNS (42), /* int_div_si */
1015 COSTS_N_INSNS (74), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* The only costs that are changed here are
1021 integer multiplication. */
1022 COSTS_N_INSNS (6), /* fp_add */
1023 COSTS_N_INSNS (7), /* fp_mult_sf */
1024 COSTS_N_INSNS (8), /* fp_mult_df */
1025 COSTS_N_INSNS (23), /* fp_div_sf */
1026 COSTS_N_INSNS (36), /* fp_div_df */
1027 COSTS_N_INSNS (5), /* int_mult_si */
1028 COSTS_N_INSNS (9), /* int_mult_di */
1029 COSTS_N_INSNS (69), /* int_div_si */
1030 COSTS_N_INSNS (69), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1038 /* The only costs that are changed here are
1039 integer multiplication. */
1040 COSTS_N_INSNS (6), /* fp_add */
1041 COSTS_N_INSNS (7), /* fp_mult_sf */
1042 COSTS_N_INSNS (8), /* fp_mult_df */
1043 COSTS_N_INSNS (23), /* fp_div_sf */
1044 COSTS_N_INSNS (36), /* fp_div_df */
1045 COSTS_N_INSNS (3), /* int_mult_si */
1046 COSTS_N_INSNS (8), /* int_mult_di */
1047 COSTS_N_INSNS (69), /* int_div_si */
1048 COSTS_N_INSNS (69), /* int_div_di */
1049 1, /* branch_cost */
1050 4 /* memory_latency */
1053 COSTS_N_INSNS (2), /* fp_add */
1054 COSTS_N_INSNS (2), /* fp_mult_sf */
1055 COSTS_N_INSNS (2), /* fp_mult_df */
1056 COSTS_N_INSNS (12), /* fp_div_sf */
1057 COSTS_N_INSNS (19), /* fp_div_df */
1058 COSTS_N_INSNS (5), /* int_mult_si */
1059 COSTS_N_INSNS (9), /* int_mult_di */
1060 COSTS_N_INSNS (34), /* int_div_si */
1061 COSTS_N_INSNS (66), /* int_div_di */
1062 1, /* branch_cost */
1063 4 /* memory_latency */
1066 /* These costs are the same as the SB-1A below. */
1067 COSTS_N_INSNS (4), /* fp_add */
1068 COSTS_N_INSNS (4), /* fp_mult_sf */
1069 COSTS_N_INSNS (4), /* fp_mult_df */
1070 COSTS_N_INSNS (24), /* fp_div_sf */
1071 COSTS_N_INSNS (32), /* fp_div_df */
1072 COSTS_N_INSNS (3), /* int_mult_si */
1073 COSTS_N_INSNS (4), /* int_mult_di */
1074 COSTS_N_INSNS (36), /* int_div_si */
1075 COSTS_N_INSNS (68), /* int_div_di */
1076 1, /* branch_cost */
1077 4 /* memory_latency */
1080 /* These costs are the same as the SB-1 above. */
1081 COSTS_N_INSNS (4), /* fp_add */
1082 COSTS_N_INSNS (4), /* fp_mult_sf */
1083 COSTS_N_INSNS (4), /* fp_mult_df */
1084 COSTS_N_INSNS (24), /* fp_div_sf */
1085 COSTS_N_INSNS (32), /* fp_div_df */
1086 COSTS_N_INSNS (3), /* int_mult_si */
1087 COSTS_N_INSNS (4), /* int_mult_di */
1088 COSTS_N_INSNS (36), /* int_div_si */
1089 COSTS_N_INSNS (68), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1097 /* Need to replace first five with the costs of calling the appropriate
1099 COSTS_N_INSNS (256), /* fp_add */
1100 COSTS_N_INSNS (256), /* fp_mult_sf */
1101 COSTS_N_INSNS (256), /* fp_mult_df */
1102 COSTS_N_INSNS (256), /* fp_div_sf */
1103 COSTS_N_INSNS (256), /* fp_div_df */
1104 COSTS_N_INSNS (8), /* int_mult_si */
1105 COSTS_N_INSNS (8), /* int_mult_di */
1106 COSTS_N_INSNS (72), /* int_div_si */
1107 COSTS_N_INSNS (72), /* int_div_di */
1108 1, /* branch_cost */
1109 4 /* memory_latency */
1113 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1114 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1115 struct mflip_mips16_entry
GTY (()) {
1119 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1121 /* Hash table callbacks for mflip_mips16_htab. */
1124 mflip_mips16_htab_hash (const void *entry
)
1126 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1130 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1132 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1133 (const char *) name
) == 0;
1136 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1137 mode, false if it should next add an attribute for the opposite mode. */
1138 static GTY(()) bool mips16_flipper
;
1140 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1141 for -mflip-mips16. Return true if it should use "mips16" and false if
1142 it should use "nomips16". */
1145 mflip_mips16_use_mips16_p (tree decl
)
1147 struct mflip_mips16_entry
*entry
;
1152 /* Use the opposite of the command-line setting for anonymous decls. */
1153 if (!DECL_NAME (decl
))
1154 return !mips_base_mips16
;
1156 if (!mflip_mips16_htab
)
1157 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1158 mflip_mips16_htab_eq
, NULL
);
1160 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1161 hash
= htab_hash_string (name
);
1162 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1163 entry
= (struct mflip_mips16_entry
*) *slot
;
1166 mips16_flipper
= !mips16_flipper
;
1167 entry
= GGC_NEW (struct mflip_mips16_entry
);
1169 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1172 return entry
->mips16_p
;
1175 /* Predicates to test for presence of "near" and "far"/"long_call"
1176 attributes on the given TYPE. */
1179 mips_near_type_p (const_tree type
)
1181 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1185 mips_far_type_p (const_tree type
)
1187 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1188 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1191 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1194 mips_mips16_decl_p (const_tree decl
)
1196 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1200 mips_nomips16_decl_p (const_tree decl
)
1202 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1205 /* Check if the interrupt attribute is set for a function. */
1208 mips_interrupt_type_p (tree type
)
1210 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1213 /* Check if the attribute to use shadow register set is set for a function. */
1216 mips_use_shadow_register_set_p (tree type
)
1218 return lookup_attribute ("use_shadow_register_set",
1219 TYPE_ATTRIBUTES (type
)) != NULL
;
1222 /* Check if the attribute to keep interrupts masked is set for a function. */
1225 mips_keep_interrupts_masked_p (tree type
)
1227 return lookup_attribute ("keep_interrupts_masked",
1228 TYPE_ATTRIBUTES (type
)) != NULL
;
1231 /* Check if the attribute to use debug exception return is set for
1235 mips_use_debug_exception_return_p (tree type
)
1237 return lookup_attribute ("use_debug_exception_return",
1238 TYPE_ATTRIBUTES (type
)) != NULL
;
1241 /* Return true if function DECL is a MIPS16 function. Return the ambient
1242 setting if DECL is null. */
1245 mips_use_mips16_mode_p (tree decl
)
1249 /* Nested functions must use the same frame pointer as their
1250 parent and must therefore use the same ISA mode. */
1251 tree parent
= decl_function_context (decl
);
1254 if (mips_mips16_decl_p (decl
))
1256 if (mips_nomips16_decl_p (decl
))
1259 return mips_base_mips16
;
1262 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1265 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1267 /* Disallow mixed near/far attributes. */
1268 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1270 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1275 /* Implement TARGET_INSERT_ATTRIBUTES. */
1278 mips_insert_attributes (tree decl
, tree
*attributes
)
1281 bool mips16_p
, nomips16_p
;
1283 /* Check for "mips16" and "nomips16" attributes. */
1284 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1285 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1286 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1289 error ("%qs attribute only applies to functions", "mips16");
1291 error ("%qs attribute only applies to functions", "nomips16");
1295 mips16_p
|= mips_mips16_decl_p (decl
);
1296 nomips16_p
|= mips_nomips16_decl_p (decl
);
1297 if (mips16_p
|| nomips16_p
)
1299 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1300 if (mips16_p
&& nomips16_p
)
1301 error ("%qs cannot have both %<mips16%> and "
1302 "%<nomips16%> attributes",
1303 IDENTIFIER_POINTER (DECL_NAME (decl
)));
1305 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1307 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1308 "mips16" attribute, arbitrarily pick one. We must pick the same
1309 setting for duplicate declarations of a function. */
1310 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1311 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1316 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1319 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1321 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1322 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1323 error ("%qs redeclared with conflicting %qs attributes",
1324 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "mips16");
1325 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1326 error ("%qs redeclared with conflicting %qs attributes",
1327 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "nomips16");
1329 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1330 DECL_ATTRIBUTES (newdecl
));
1333 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1334 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1337 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1339 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1341 *base_ptr
= XEXP (x
, 0);
1342 *offset_ptr
= INTVAL (XEXP (x
, 1));
1351 static unsigned int mips_build_integer (struct mips_integer_op
*,
1352 unsigned HOST_WIDE_INT
);
1354 /* A subroutine of mips_build_integer, with the same interface.
1355 Assume that the final action in the sequence should be a left shift. */
1358 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1360 unsigned int i
, shift
;
1362 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1363 since signed numbers are easier to load than unsigned ones. */
1365 while ((value
& 1) == 0)
1366 value
/= 2, shift
++;
1368 i
= mips_build_integer (codes
, value
);
1369 codes
[i
].code
= ASHIFT
;
1370 codes
[i
].value
= shift
;
1374 /* As for mips_build_shift, but assume that the final action will be
1375 an IOR or PLUS operation. */
1378 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1380 unsigned HOST_WIDE_INT high
;
1383 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1384 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1386 /* The constant is too complex to load with a simple LUI/ORI pair,
1387 so we want to give the recursive call as many trailing zeros as
1388 possible. In this case, we know bit 16 is set and that the
1389 low 16 bits form a negative number. If we subtract that number
1390 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1391 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1392 codes
[i
].code
= PLUS
;
1393 codes
[i
].value
= CONST_LOW_PART (value
);
1397 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1398 bits gives a value with at least 17 trailing zeros. */
1399 i
= mips_build_integer (codes
, high
);
1400 codes
[i
].code
= IOR
;
1401 codes
[i
].value
= value
& 0xffff;
1406 /* Fill CODES with a sequence of rtl operations to load VALUE.
1407 Return the number of operations needed. */
1410 mips_build_integer (struct mips_integer_op
*codes
,
1411 unsigned HOST_WIDE_INT value
)
1413 if (SMALL_OPERAND (value
)
1414 || SMALL_OPERAND_UNSIGNED (value
)
1415 || LUI_OPERAND (value
))
1417 /* The value can be loaded with a single instruction. */
1418 codes
[0].code
= UNKNOWN
;
1419 codes
[0].value
= value
;
1422 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1424 /* Either the constant is a simple LUI/ORI combination or its
1425 lowest bit is set. We don't want to shift in this case. */
1426 return mips_build_lower (codes
, value
);
1428 else if ((value
& 0xffff) == 0)
1430 /* The constant will need at least three actions. The lowest
1431 16 bits are clear, so the final action will be a shift. */
1432 return mips_build_shift (codes
, value
);
1436 /* The final action could be a shift, add or inclusive OR.
1437 Rather than use a complex condition to select the best
1438 approach, try both mips_build_shift and mips_build_lower
1439 and pick the one that gives the shortest sequence.
1440 Note that this case is only used once per constant. */
1441 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1442 unsigned int cost
, alt_cost
;
1444 cost
= mips_build_shift (codes
, value
);
1445 alt_cost
= mips_build_lower (alt_codes
, value
);
1446 if (alt_cost
< cost
)
1448 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1455 /* Return true if symbols of type TYPE require a GOT access. */
1458 mips_got_symbol_type_p (enum mips_symbol_type type
)
1462 case SYMBOL_GOT_PAGE_OFST
:
1463 case SYMBOL_GOT_DISP
:
1471 /* Return true if X is a thread-local symbol. */
1474 mips_tls_symbol_p (rtx x
)
1476 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1479 /* Return true if SYMBOL_REF X is associated with a global symbol
1480 (in the STB_GLOBAL sense). */
1483 mips_global_symbol_p (const_rtx x
)
1485 const_tree decl
= SYMBOL_REF_DECL (x
);
1488 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1490 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1491 or weak symbols. Relocations in the object file will be against
1492 the target symbol, so it's that symbol's binding that matters here. */
1493 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1496 /* Return true if function X is a libgcc MIPS16 stub function. */
1499 mips16_stub_function_p (const_rtx x
)
1501 return (GET_CODE (x
) == SYMBOL_REF
1502 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1505 /* Return true if function X is a locally-defined and locally-binding
1509 mips16_local_function_p (const_rtx x
)
1511 return (GET_CODE (x
) == SYMBOL_REF
1512 && SYMBOL_REF_LOCAL_P (x
)
1513 && !SYMBOL_REF_EXTERNAL_P (x
)
1514 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1517 /* Return true if SYMBOL_REF X binds locally. */
1520 mips_symbol_binds_local_p (const_rtx x
)
1522 return (SYMBOL_REF_DECL (x
)
1523 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1524 : SYMBOL_REF_LOCAL_P (x
));
1527 /* Return true if rtx constants of mode MODE should be put into a small
1531 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1533 return (!TARGET_EMBEDDED_DATA
1534 && TARGET_LOCAL_SDATA
1535 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1538 /* Return true if X should not be moved directly into register $25.
1539 We need this because many versions of GAS will treat "la $25,foo" as
1540 part of a call sequence and so allow a global "foo" to be lazily bound. */
1543 mips_dangerous_for_la25_p (rtx x
)
1545 return (!TARGET_EXPLICIT_RELOCS
1547 && GET_CODE (x
) == SYMBOL_REF
1548 && mips_global_symbol_p (x
));
1551 /* Return true if calls to X might need $25 to be valid on entry. */
1554 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1556 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1559 /* MIPS16 stub functions are guaranteed not to use $25. */
1560 if (mips16_stub_function_p (x
))
1563 if (GET_CODE (x
) == SYMBOL_REF
)
1565 /* If PLTs and copy relocations are available, the static linker
1566 will make sure that $25 is valid on entry to the target function. */
1567 if (TARGET_ABICALLS_PIC0
)
1570 /* Locally-defined functions use absolute accesses to set up
1571 the global pointer. */
1572 if (TARGET_ABSOLUTE_ABICALLS
1573 && mips_symbol_binds_local_p (x
)
1574 && !SYMBOL_REF_EXTERNAL_P (x
))
1581 /* Return the method that should be used to access SYMBOL_REF or
1582 LABEL_REF X in context CONTEXT. */
1584 static enum mips_symbol_type
1585 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1588 return SYMBOL_GOT_DISP
;
1590 if (GET_CODE (x
) == LABEL_REF
)
1592 /* LABEL_REFs are used for jump tables as well as text labels.
1593 Only return SYMBOL_PC_RELATIVE if we know the label is in
1594 the text section. */
1595 if (TARGET_MIPS16_SHORT_JUMP_TABLES
)
1596 return SYMBOL_PC_RELATIVE
;
1598 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1599 return SYMBOL_GOT_PAGE_OFST
;
1601 return SYMBOL_ABSOLUTE
;
1604 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1606 if (SYMBOL_REF_TLS_MODEL (x
))
1609 if (CONSTANT_POOL_ADDRESS_P (x
))
1611 if (TARGET_MIPS16_TEXT_LOADS
)
1612 return SYMBOL_PC_RELATIVE
;
1614 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1615 return SYMBOL_PC_RELATIVE
;
1617 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1618 return SYMBOL_GP_RELATIVE
;
1621 /* Do not use small-data accesses for weak symbols; they may end up
1623 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1624 return SYMBOL_GP_RELATIVE
;
1626 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1628 if (TARGET_ABICALLS_PIC2
1629 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1631 /* There are three cases to consider:
1633 - o32 PIC (either with or without explicit relocs)
1634 - n32/n64 PIC without explicit relocs
1635 - n32/n64 PIC with explicit relocs
1637 In the first case, both local and global accesses will use an
1638 R_MIPS_GOT16 relocation. We must correctly predict which of
1639 the two semantics (local or global) the assembler and linker
1640 will apply. The choice depends on the symbol's binding rather
1641 than its visibility.
1643 In the second case, the assembler will not use R_MIPS_GOT16
1644 relocations, but it chooses between local and global accesses
1645 in the same way as for o32 PIC.
1647 In the third case we have more freedom since both forms of
1648 access will work for any kind of symbol. However, there seems
1649 little point in doing things differently. */
1650 if (mips_global_symbol_p (x
))
1651 return SYMBOL_GOT_DISP
;
1653 return SYMBOL_GOT_PAGE_OFST
;
1656 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1657 return SYMBOL_FORCE_TO_MEM
;
1659 return SYMBOL_ABSOLUTE
;
1662 /* Classify the base of symbolic expression X, given that X appears in
1665 static enum mips_symbol_type
1666 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1670 split_const (x
, &x
, &offset
);
1671 if (UNSPEC_ADDRESS_P (x
))
1672 return UNSPEC_ADDRESS_TYPE (x
);
1674 return mips_classify_symbol (x
, context
);
1677 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1678 is the alignment in bytes of SYMBOL_REF X. */
1681 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1683 HOST_WIDE_INT align
;
1685 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1686 return IN_RANGE (offset
, 0, align
- 1);
1689 /* Return true if X is a symbolic constant that can be used in context
1690 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1693 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1694 enum mips_symbol_type
*symbol_type
)
1698 split_const (x
, &x
, &offset
);
1699 if (UNSPEC_ADDRESS_P (x
))
1701 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1702 x
= UNSPEC_ADDRESS (x
);
1704 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1706 *symbol_type
= mips_classify_symbol (x
, context
);
1707 if (*symbol_type
== SYMBOL_TLS
)
1713 if (offset
== const0_rtx
)
1716 /* Check whether a nonzero offset is valid for the underlying
1718 switch (*symbol_type
)
1720 case SYMBOL_ABSOLUTE
:
1721 case SYMBOL_FORCE_TO_MEM
:
1722 case SYMBOL_32_HIGH
:
1723 case SYMBOL_64_HIGH
:
1726 /* If the target has 64-bit pointers and the object file only
1727 supports 32-bit symbols, the values of those symbols will be
1728 sign-extended. In this case we can't allow an arbitrary offset
1729 in case the 32-bit value X + OFFSET has a different sign from X. */
1730 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1731 return offset_within_block_p (x
, INTVAL (offset
));
1733 /* In other cases the relocations can handle any offset. */
1736 case SYMBOL_PC_RELATIVE
:
1737 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1738 In this case, we no longer have access to the underlying constant,
1739 but the original symbol-based access was known to be valid. */
1740 if (GET_CODE (x
) == LABEL_REF
)
1745 case SYMBOL_GP_RELATIVE
:
1746 /* Make sure that the offset refers to something within the
1747 same object block. This should guarantee that the final
1748 PC- or GP-relative offset is within the 16-bit limit. */
1749 return offset_within_block_p (x
, INTVAL (offset
));
1751 case SYMBOL_GOT_PAGE_OFST
:
1752 case SYMBOL_GOTOFF_PAGE
:
1753 /* If the symbol is global, the GOT entry will contain the symbol's
1754 address, and we will apply a 16-bit offset after loading it.
1755 If the symbol is local, the linker should provide enough local
1756 GOT entries for a 16-bit offset, but larger offsets may lead
1758 return SMALL_INT (offset
);
1762 /* There is no carry between the HI and LO REL relocations, so the
1763 offset is only valid if we know it won't lead to such a carry. */
1764 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1766 case SYMBOL_GOT_DISP
:
1767 case SYMBOL_GOTOFF_DISP
:
1768 case SYMBOL_GOTOFF_CALL
:
1769 case SYMBOL_GOTOFF_LOADGP
:
1772 case SYMBOL_GOTTPREL
:
1780 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1781 single instruction. We rely on the fact that, in the worst case,
1782 all instructions involved in a MIPS16 address calculation are usually
1786 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1790 case SYMBOL_ABSOLUTE
:
1791 /* When using 64-bit symbols, we need 5 preparatory instructions,
1794 lui $at,%highest(symbol)
1795 daddiu $at,$at,%higher(symbol)
1797 daddiu $at,$at,%hi(symbol)
1800 The final address is then $at + %lo(symbol). With 32-bit
1801 symbols we just need a preparatory LUI for normal mode and
1802 a preparatory LI and SLL for MIPS16. */
1803 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1805 case SYMBOL_GP_RELATIVE
:
1806 /* Treat GP-relative accesses as taking a single instruction on
1807 MIPS16 too; the copy of $gp can often be shared. */
1810 case SYMBOL_PC_RELATIVE
:
1811 /* PC-relative constants can be only be used with ADDIUPC,
1812 DADDIUPC, LWPC and LDPC. */
1813 if (mode
== MAX_MACHINE_MODE
1814 || GET_MODE_SIZE (mode
) == 4
1815 || GET_MODE_SIZE (mode
) == 8)
1818 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1821 case SYMBOL_FORCE_TO_MEM
:
1822 /* LEAs will be converted into constant-pool references by
1824 if (mode
== MAX_MACHINE_MODE
)
1827 /* The constant must be loaded and then dereferenced. */
1830 case SYMBOL_GOT_DISP
:
1831 /* The constant will have to be loaded from the GOT before it
1832 is used in an address. */
1833 if (mode
!= MAX_MACHINE_MODE
)
1838 case SYMBOL_GOT_PAGE_OFST
:
1839 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1840 local/global classification is accurate. The worst cases are:
1842 (1) For local symbols when generating o32 or o64 code. The assembler
1848 ...and the final address will be $at + %lo(symbol).
1850 (2) For global symbols when -mxgot. The assembler will use:
1852 lui $at,%got_hi(symbol)
1855 ...and the final address will be $at + %got_lo(symbol). */
1858 case SYMBOL_GOTOFF_PAGE
:
1859 case SYMBOL_GOTOFF_DISP
:
1860 case SYMBOL_GOTOFF_CALL
:
1861 case SYMBOL_GOTOFF_LOADGP
:
1862 case SYMBOL_32_HIGH
:
1863 case SYMBOL_64_HIGH
:
1869 case SYMBOL_GOTTPREL
:
1872 /* A 16-bit constant formed by a single relocation, or a 32-bit
1873 constant formed from a high 16-bit relocation and a low 16-bit
1874 relocation. Use mips_split_p to determine which. 32-bit
1875 constants need an "lui; addiu" sequence for normal mode and
1876 an "li; sll; addiu" sequence for MIPS16 mode. */
1877 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1880 /* We don't treat a bare TLS symbol as a constant. */
1886 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1887 to load symbols of type TYPE into a register. Return 0 if the given
1888 type of symbol cannot be used as an immediate operand.
1890 Otherwise, return the number of instructions needed to load or store
1891 values of mode MODE to or from addresses of type TYPE. Return 0 if
1892 the given type of symbol is not valid in addresses.
1894 In both cases, treat extended MIPS16 instructions as two instructions. */
1897 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1899 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1902 /* A for_each_rtx callback. Stop the search if *X references a
1903 thread-local symbol. */
1906 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1908 return mips_tls_symbol_p (*x
);
1911 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1914 mips_cannot_force_const_mem (rtx x
)
1916 enum mips_symbol_type type
;
1919 /* There is no assembler syntax for expressing an address-sized
1921 if (GET_CODE (x
) == HIGH
)
1924 /* As an optimization, reject constants that mips_legitimize_move
1927 Suppose we have a multi-instruction sequence that loads constant C
1928 into register R. If R does not get allocated a hard register, and
1929 R is used in an operand that allows both registers and memory
1930 references, reload will consider forcing C into memory and using
1931 one of the instruction's memory alternatives. Returning false
1932 here will force it to use an input reload instead. */
1933 if (GET_CODE (x
) == CONST_INT
&& LEGITIMATE_CONSTANT_P (x
))
1936 split_const (x
, &base
, &offset
);
1937 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
)
1938 && type
!= SYMBOL_FORCE_TO_MEM
)
1940 /* The same optimization as for CONST_INT. */
1941 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
1944 /* If MIPS16 constant pools live in the text section, they should
1945 not refer to anything that might need run-time relocation. */
1946 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
1950 /* TLS symbols must be computed by mips_legitimize_move. */
1951 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1957 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1958 constants when we're using a per-function constant pool. */
1961 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1962 const_rtx x ATTRIBUTE_UNUSED
)
1964 return !TARGET_MIPS16_PCREL_LOADS
;
1967 /* Return true if register REGNO is a valid base register for mode MODE.
1968 STRICT_P is true if REG_OK_STRICT is in effect. */
1971 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1974 if (!HARD_REGISTER_NUM_P (regno
))
1978 regno
= reg_renumber
[regno
];
1981 /* These fake registers will be eliminated to either the stack or
1982 hard frame pointer, both of which are usually valid base registers.
1983 Reload deals with the cases where the eliminated form isn't valid. */
1984 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1987 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1988 values, nothing smaller. There are two problems here:
1990 (a) Instantiating virtual registers can introduce new uses of the
1991 stack pointer. If these virtual registers are valid addresses,
1992 the stack pointer should be too.
1994 (b) Most uses of the stack pointer are not made explicit until
1995 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1996 We don't know until that stage whether we'll be eliminating to the
1997 stack pointer (which needs the restriction) or the hard frame
1998 pointer (which doesn't).
2000 All in all, it seems more consistent to only enforce this restriction
2001 during and after reload. */
2002 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2003 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2005 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2008 /* Return true if X is a valid base register for mode MODE.
2009 STRICT_P is true if REG_OK_STRICT is in effect. */
2012 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2014 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2018 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2021 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2022 can address a value of mode MODE. */
2025 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2027 /* Check that X is a signed 16-bit number. */
2028 if (!const_arith_operand (x
, Pmode
))
2031 /* We may need to split multiword moves, so make sure that every word
2033 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2034 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2040 /* Return true if a LO_SUM can address a value of mode MODE when the
2041 LO_SUM symbol has type SYMBOL_TYPE. */
2044 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2046 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2048 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2051 /* Check that there is a known low-part relocation. */
2052 if (mips_lo_relocs
[symbol_type
] == NULL
)
2055 /* We may need to split multiword moves, so make sure that each word
2056 can be accessed without inducing a carry. This is mainly needed
2057 for o64, which has historically only guaranteed 64-bit alignment
2058 for 128-bit types. */
2059 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2060 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2066 /* Return true if X is a valid address for machine mode MODE. If it is,
2067 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2071 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2072 enum machine_mode mode
, bool strict_p
)
2074 switch (GET_CODE (x
))
2078 info
->type
= ADDRESS_REG
;
2080 info
->offset
= const0_rtx
;
2081 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2084 info
->type
= ADDRESS_REG
;
2085 info
->reg
= XEXP (x
, 0);
2086 info
->offset
= XEXP (x
, 1);
2087 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2088 && mips_valid_offset_p (info
->offset
, mode
));
2091 info
->type
= ADDRESS_LO_SUM
;
2092 info
->reg
= XEXP (x
, 0);
2093 info
->offset
= XEXP (x
, 1);
2094 /* We have to trust the creator of the LO_SUM to do something vaguely
2095 sane. Target-independent code that creates a LO_SUM should also
2096 create and verify the matching HIGH. Target-independent code that
2097 adds an offset to a LO_SUM must prove that the offset will not
2098 induce a carry. Failure to do either of these things would be
2099 a bug, and we are not required to check for it here. The MIPS
2100 backend itself should only create LO_SUMs for valid symbolic
2101 constants, with the high part being either a HIGH or a copy
2104 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2105 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2106 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2109 /* Small-integer addresses don't occur very often, but they
2110 are legitimate if $0 is a valid base register. */
2111 info
->type
= ADDRESS_CONST_INT
;
2112 return !TARGET_MIPS16
&& SMALL_INT (x
);
2117 info
->type
= ADDRESS_SYMBOLIC
;
2118 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2120 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2121 && !mips_split_p
[info
->symbol_type
]);
2128 /* Return true if X is a legitimate address for a memory operand of mode
2129 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
2132 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2134 struct mips_address_info addr
;
2136 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2139 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2142 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2144 struct mips_address_info addr
;
2146 return (mips_classify_address (&addr
, x
, mode
, false)
2147 && addr
.type
== ADDRESS_REG
2148 && addr
.reg
== stack_pointer_rtx
);
2151 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2152 address instruction. Note that such addresses are not considered
2153 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
2154 is so restricted. */
2157 mips_lwxs_address_p (rtx addr
)
2160 && GET_CODE (addr
) == PLUS
2161 && REG_P (XEXP (addr
, 1)))
2163 rtx offset
= XEXP (addr
, 0);
2164 if (GET_CODE (offset
) == MULT
2165 && REG_P (XEXP (offset
, 0))
2166 && GET_CODE (XEXP (offset
, 1)) == CONST_INT
2167 && INTVAL (XEXP (offset
, 1)) == 4)
2173 /* Return true if a value at OFFSET bytes from base register BASE can be
2174 accessed using an unextended MIPS16 instruction. MODE is the mode of
2177 Usually the offset in an unextended instruction is a 5-bit field.
2178 The offset is unsigned and shifted left once for LH and SH, twice
2179 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2180 an 8-bit immediate field that's shifted left twice. */
2183 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2184 unsigned HOST_WIDE_INT offset
)
2186 if (offset
% GET_MODE_SIZE (mode
) == 0)
2188 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2189 return offset
< 256U * GET_MODE_SIZE (mode
);
2190 return offset
< 32U * GET_MODE_SIZE (mode
);
2195 /* Return the number of instructions needed to load or store a value
2196 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2197 Assume that multiword moves may need to be split into word moves
2198 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2201 For MIPS16 code, count extended instructions as two instructions. */
2204 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2206 struct mips_address_info addr
;
2209 /* BLKmode is used for single unaligned loads and stores and should
2210 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2211 meaningless, so we have to single it out as a special case one way
2213 if (mode
!= BLKmode
&& might_split_p
)
2214 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2218 if (mips_classify_address (&addr
, x
, mode
, false))
2223 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2224 UINTVAL (addr
.offset
)))
2228 case ADDRESS_LO_SUM
:
2229 return TARGET_MIPS16
? factor
* 2 : factor
;
2231 case ADDRESS_CONST_INT
:
2234 case ADDRESS_SYMBOLIC
:
2235 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2240 /* Return the number of instructions needed to load constant X.
2241 Return 0 if X isn't a valid constant. */
2244 mips_const_insns (rtx x
)
2246 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2247 enum mips_symbol_type symbol_type
;
2250 switch (GET_CODE (x
))
2253 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2255 || !mips_split_p
[symbol_type
])
2258 /* This is simply an LUI for normal mode. It is an extended
2259 LI followed by an extended SLL for MIPS16. */
2260 return TARGET_MIPS16
? 4 : 1;
2264 /* Unsigned 8-bit constants can be loaded using an unextended
2265 LI instruction. Unsigned 16-bit constants can be loaded
2266 using an extended LI. Negative constants must be loaded
2267 using LI and then negated. */
2268 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2269 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2270 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2271 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2274 return mips_build_integer (codes
, INTVAL (x
));
2278 /* Allow zeros for normal mode, where we can use $0. */
2279 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2285 /* See if we can refer to X directly. */
2286 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2287 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2289 /* Otherwise try splitting the constant into a base and offset.
2290 If the offset is a 16-bit value, we can load the base address
2291 into a register and then use (D)ADDIU to add in the offset.
2292 If the offset is larger, we can load the base and offset
2293 into separate registers and add them together with (D)ADDU.
2294 However, the latter is only possible before reload; during
2295 and after reload, we must have the option of forcing the
2296 constant into the pool instead. */
2297 split_const (x
, &x
, &offset
);
2300 int n
= mips_const_insns (x
);
2303 if (SMALL_INT (offset
))
2305 else if (!targetm
.cannot_force_const_mem (x
))
2306 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2313 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2321 /* X is a doubleword constant that can be handled by splitting it into
2322 two words and loading each word separately. Return the number of
2323 instructions required to do this. */
2326 mips_split_const_insns (rtx x
)
2328 unsigned int low
, high
;
2330 low
= mips_const_insns (mips_subword (x
, false));
2331 high
= mips_const_insns (mips_subword (x
, true));
2332 gcc_assert (low
> 0 && high
> 0);
2336 /* Return the number of instructions needed to implement INSN,
2337 given that it loads from or stores to MEM. Count extended
2338 MIPS16 instructions as two instructions. */
2341 mips_load_store_insns (rtx mem
, rtx insn
)
2343 enum machine_mode mode
;
2347 gcc_assert (MEM_P (mem
));
2348 mode
= GET_MODE (mem
);
2350 /* Try to prove that INSN does not need to be split. */
2351 might_split_p
= true;
2352 if (GET_MODE_BITSIZE (mode
) == 64)
2354 set
= single_set (insn
);
2355 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2356 might_split_p
= false;
2359 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2362 /* Return the number of instructions needed for an integer division. */
2365 mips_idiv_insns (void)
2370 if (TARGET_CHECK_ZERO_DIV
)
2372 if (GENERATE_DIVIDE_TRAPS
)
2378 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2383 /* Emit a move from SRC to DEST. Assume that the move expanders can
2384 handle all moves if !can_create_pseudo_p (). The distinction is
2385 important because, unlike emit_move_insn, the move expanders know
2386 how to force Pmode objects into the constant pool even when the
2387 constant pool address is not itself legitimate. */
2390 mips_emit_move (rtx dest
, rtx src
)
2392 return (can_create_pseudo_p ()
2393 ? emit_move_insn (dest
, src
)
2394 : emit_move_insn_1 (dest
, src
));
2397 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2400 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2402 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2403 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2406 /* Compute (CODE OP0 OP1) and store the result in a new register
2407 of mode MODE. Return that new register. */
2410 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2414 reg
= gen_reg_rtx (mode
);
2415 mips_emit_binary (code
, reg
, op0
, op1
);
2419 /* Copy VALUE to a register and return that register. If new pseudos
2420 are allowed, copy it into a new register, otherwise use DEST. */
2423 mips_force_temporary (rtx dest
, rtx value
)
2425 if (can_create_pseudo_p ())
2426 return force_reg (Pmode
, value
);
2429 mips_emit_move (dest
, value
);
2434 /* Emit a call sequence with call pattern PATTERN and return the call
2435 instruction itself (which is not necessarily the last instruction
2436 emitted). ORIG_ADDR is the original, unlegitimized address,
2437 ADDR is the legitimized form, and LAZY_P is true if the call
2438 address is lazily-bound. */
2441 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2445 insn
= emit_call_insn (pattern
);
2447 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2449 /* MIPS16 JALRs only take MIPS16 registers. If the target
2450 function requires $25 to be valid on entry, we must copy it
2451 there separately. The move instruction can be put in the
2452 call's delay slot. */
2453 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2454 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2455 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2459 /* Lazy-binding stubs require $gp to be valid on entry. */
2460 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2464 /* See the comment above load_call<mode> for details. */
2465 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2466 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2467 emit_insn (gen_update_got_version ());
2472 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2473 then add CONST_INT OFFSET to the result. */
2476 mips_unspec_address_offset (rtx base
, rtx offset
,
2477 enum mips_symbol_type symbol_type
)
2479 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2480 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2481 if (offset
!= const0_rtx
)
2482 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2483 return gen_rtx_CONST (Pmode
, base
);
2486 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2487 type SYMBOL_TYPE. */
2490 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2494 split_const (address
, &base
, &offset
);
2495 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2498 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2499 high part to BASE and return the result. Just return BASE otherwise.
2500 TEMP is as for mips_force_temporary.
2502 The returned expression can be used as the first operand to a LO_SUM. */
2505 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2506 enum mips_symbol_type symbol_type
)
2508 if (mips_split_p
[symbol_type
])
2510 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2511 addr
= mips_force_temporary (temp
, addr
);
2512 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2517 /* Return an instruction that copies $gp into register REG. We want
2518 GCC to treat the register's value as constant, so that its value
2519 can be rematerialized on demand. */
2522 gen_load_const_gp (rtx reg
)
2524 return (Pmode
== SImode
2525 ? gen_load_const_gp_si (reg
)
2526 : gen_load_const_gp_di (reg
));
2529 /* Return a pseudo register that contains the value of $gp throughout
2530 the current function. Such registers are needed by MIPS16 functions,
2531 for which $gp itself is not a valid base register or addition operand. */
2534 mips16_gp_pseudo_reg (void)
2536 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2537 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2539 /* Don't emit an instruction to initialize the pseudo register if
2540 we are being called from the tree optimizers' cost-calculation
2542 if (!cfun
->machine
->initialized_mips16_gp_pseudo_p
2543 && (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
))
2547 push_topmost_sequence ();
2549 scan
= get_insns ();
2550 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2551 scan
= NEXT_INSN (scan
);
2553 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2554 emit_insn_after (insn
, scan
);
2556 pop_topmost_sequence ();
2558 cfun
->machine
->initialized_mips16_gp_pseudo_p
= true;
2561 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2564 /* Return a base register that holds pic_offset_table_rtx.
2565 TEMP, if nonnull, is a scratch Pmode base register. */
2568 mips_pic_base_register (rtx temp
)
2571 return pic_offset_table_rtx
;
2573 if (can_create_pseudo_p ())
2574 return mips16_gp_pseudo_reg ();
2577 /* The first post-reload split exposes all references to $gp
2578 (both uses and definitions). All references must remain
2579 explicit after that point.
2581 It is safe to introduce uses of $gp at any time, so for
2582 simplicity, we do that before the split too. */
2583 mips_emit_move (temp
, pic_offset_table_rtx
);
2585 emit_insn (gen_load_const_gp (temp
));
2589 /* Create and return a GOT reference of type TYPE for address ADDR.
2590 TEMP, if nonnull, is a scratch Pmode base register. */
2593 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2595 rtx base
, high
, lo_sum_symbol
;
2597 base
= mips_pic_base_register (temp
);
2599 /* If we used the temporary register to load $gp, we can't use
2600 it for the high part as well. */
2601 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2604 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2605 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2607 if (type
== SYMBOL_GOTOFF_CALL
)
2608 return (Pmode
== SImode
2609 ? gen_unspec_callsi (high
, lo_sum_symbol
)
2610 : gen_unspec_calldi (high
, lo_sum_symbol
));
2612 return (Pmode
== SImode
2613 ? gen_unspec_gotsi (high
, lo_sum_symbol
)
2614 : gen_unspec_gotdi (high
, lo_sum_symbol
));
2617 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2618 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2619 constant in that context and can be split into high and low parts.
2620 If so, and if LOW_OUT is nonnull, emit the high part and store the
2621 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2623 TEMP is as for mips_force_temporary and is used to load the high
2624 part into a register.
2626 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2627 a legitimize SET_SRC for an .md pattern, otherwise the low part
2628 is guaranteed to be a legitimate address for mode MODE. */
2631 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2633 enum mips_symbol_context context
;
2634 enum mips_symbol_type symbol_type
;
2637 context
= (mode
== MAX_MACHINE_MODE
2638 ? SYMBOL_CONTEXT_LEA
2639 : SYMBOL_CONTEXT_MEM
);
2640 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2642 addr
= XEXP (addr
, 0);
2643 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2644 && mips_symbol_insns (symbol_type
, mode
) > 0
2645 && mips_split_hi_p
[symbol_type
])
2648 switch (symbol_type
)
2650 case SYMBOL_GOT_PAGE_OFST
:
2651 /* The high part of a page/ofst pair is loaded from the GOT. */
2652 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2663 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2664 && mips_symbol_insns (symbol_type
, mode
) > 0
2665 && mips_split_p
[symbol_type
])
2668 switch (symbol_type
)
2670 case SYMBOL_GOT_DISP
:
2671 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2672 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2675 case SYMBOL_GP_RELATIVE
:
2676 high
= mips_pic_base_register (temp
);
2677 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2681 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2682 high
= mips_force_temporary (temp
, high
);
2683 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2692 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2693 mips_force_temporary; it is only needed when OFFSET is not a
2697 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2699 if (!SMALL_OPERAND (offset
))
2705 /* Load the full offset into a register so that we can use
2706 an unextended instruction for the address itself. */
2707 high
= GEN_INT (offset
);
2712 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2713 high
= GEN_INT (CONST_HIGH_PART (offset
));
2714 offset
= CONST_LOW_PART (offset
);
2716 high
= mips_force_temporary (temp
, high
);
2717 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2719 return plus_constant (reg
, offset
);
2722 /* The __tls_get_attr symbol. */
2723 static GTY(()) rtx mips_tls_symbol
;
2725 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2726 the TLS symbol we are referencing and TYPE is the symbol type to use
2727 (either global dynamic or local dynamic). V0 is an RTX for the
2728 return value location. */
2731 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2735 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2737 if (!mips_tls_symbol
)
2738 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2740 loc
= mips_unspec_address (sym
, type
);
2744 emit_insn (gen_rtx_SET (Pmode
, a0
,
2745 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2746 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2747 const0_rtx
, NULL_RTX
, false);
2748 RTL_CONST_CALL_P (insn
) = 1;
2749 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2750 insn
= get_insns ();
2757 /* Return a pseudo register that contains the current thread pointer. */
2764 tp
= gen_reg_rtx (Pmode
);
2765 if (Pmode
== DImode
)
2766 emit_insn (gen_tls_get_tp_di (tp
));
2768 emit_insn (gen_tls_get_tp_si (tp
));
2772 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2773 its address. The return value will be both a valid address and a valid
2774 SET_SRC (either a REG or a LO_SUM). */
2777 mips_legitimize_tls_address (rtx loc
)
2779 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
;
2780 enum tls_model model
;
2784 sorry ("MIPS16 TLS");
2785 return gen_reg_rtx (Pmode
);
2788 model
= SYMBOL_REF_TLS_MODEL (loc
);
2789 /* Only TARGET_ABICALLS code can have more than one module; other
2790 code must be be static and should not use a GOT. All TLS models
2791 reduce to local exec in this situation. */
2792 if (!TARGET_ABICALLS
)
2793 model
= TLS_MODEL_LOCAL_EXEC
;
2797 case TLS_MODEL_GLOBAL_DYNAMIC
:
2798 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2799 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2800 dest
= gen_reg_rtx (Pmode
);
2801 emit_libcall_block (insn
, dest
, v0
, loc
);
2804 case TLS_MODEL_LOCAL_DYNAMIC
:
2805 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2806 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2807 tmp1
= gen_reg_rtx (Pmode
);
2809 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2810 share the LDM result with other LD model accesses. */
2811 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2813 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2815 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2816 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2817 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2820 case TLS_MODEL_INITIAL_EXEC
:
2821 tp
= mips_get_tp ();
2822 tmp1
= gen_reg_rtx (Pmode
);
2823 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2824 if (Pmode
== DImode
)
2825 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2827 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2828 dest
= gen_reg_rtx (Pmode
);
2829 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2832 case TLS_MODEL_LOCAL_EXEC
:
2833 tp
= mips_get_tp ();
2834 tmp1
= mips_unspec_offset_high (NULL
, tp
, loc
, SYMBOL_TPREL
);
2835 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2836 mips_unspec_address (loc
, SYMBOL_TPREL
));
2845 /* If X is not a valid address for mode MODE, force it into a register. */
2848 mips_force_address (rtx x
, enum machine_mode mode
)
2850 if (!mips_legitimate_address_p (mode
, x
, false))
2851 x
= force_reg (Pmode
, x
);
2855 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2856 be legitimized in a way that the generic machinery might not expect,
2857 put the new address in *XLOC and return true. MODE is the mode of
2858 the memory being accessed. */
2861 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2864 HOST_WIDE_INT offset
;
2866 if (mips_tls_symbol_p (*xloc
))
2868 *xloc
= mips_legitimize_tls_address (*xloc
);
2872 /* See if the address can split into a high part and a LO_SUM. */
2873 if (mips_split_symbol (NULL
, *xloc
, mode
, &addr
))
2875 *xloc
= mips_force_address (addr
, mode
);
2879 /* Handle BASE + OFFSET using mips_add_offset. */
2880 mips_split_plus (*xloc
, &base
, &offset
);
2883 if (!mips_valid_base_register_p (base
, mode
, false))
2884 base
= copy_to_mode_reg (Pmode
, base
);
2885 addr
= mips_add_offset (NULL
, base
, offset
);
2886 *xloc
= mips_force_address (addr
, mode
);
2892 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2895 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2897 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2898 enum machine_mode mode
;
2899 unsigned int i
, num_ops
;
2902 mode
= GET_MODE (dest
);
2903 num_ops
= mips_build_integer (codes
, value
);
2905 /* Apply each binary operation to X. Invariant: X is a legitimate
2906 source operand for a SET pattern. */
2907 x
= GEN_INT (codes
[0].value
);
2908 for (i
= 1; i
< num_ops
; i
++)
2910 if (!can_create_pseudo_p ())
2912 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2916 x
= force_reg (mode
, x
);
2917 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2920 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2923 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2924 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2928 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2932 /* Split moves of big integers into smaller pieces. */
2933 if (splittable_const_int_operand (src
, mode
))
2935 mips_move_integer (dest
, dest
, INTVAL (src
));
2939 /* Split moves of symbolic constants into high/low pairs. */
2940 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
2942 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
2946 /* Generate the appropriate access sequences for TLS symbols. */
2947 if (mips_tls_symbol_p (src
))
2949 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
2953 /* If we have (const (plus symbol offset)), and that expression cannot
2954 be forced into memory, load the symbol first and add in the offset.
2955 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2956 forced into memory, as it usually produces better code. */
2957 split_const (src
, &base
, &offset
);
2958 if (offset
!= const0_rtx
2959 && (targetm
.cannot_force_const_mem (src
)
2960 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
2962 base
= mips_force_temporary (dest
, base
);
2963 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
2967 src
= force_const_mem (mode
, src
);
2969 /* When using explicit relocs, constant pool references are sometimes
2970 not legitimate addresses. */
2971 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
2972 mips_emit_move (dest
, src
);
2975 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2976 sequence that is valid. */
2979 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2981 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2983 mips_emit_move (dest
, force_reg (mode
, src
));
2987 /* We need to deal with constants that would be legitimate
2988 immediate_operands but aren't legitimate move_operands. */
2989 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2991 mips_legitimize_const_move (mode
, dest
, src
);
2992 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2998 /* Return true if value X in context CONTEXT is a small-data address
2999 that can be rewritten as a LO_SUM. */
3002 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3004 enum mips_symbol_type symbol_type
;
3006 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3007 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3008 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3009 && symbol_type
== SYMBOL_GP_RELATIVE
);
3012 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3013 containing MEM, or null if none. */
3016 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3018 enum mips_symbol_context context
;
3020 if (GET_CODE (*loc
) == LO_SUM
)
3025 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3030 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3031 return mips_rewrite_small_data_p (*loc
, context
);
3034 /* Return true if OP refers to small data symbols directly, not through
3038 mips_small_data_pattern_p (rtx op
)
3040 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3043 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3044 DATA is the containing MEM, or null if none. */
3047 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3049 enum mips_symbol_context context
;
3053 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3057 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3058 if (mips_rewrite_small_data_p (*loc
, context
))
3059 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3061 if (GET_CODE (*loc
) == LO_SUM
)
3067 /* Rewrite instruction pattern PATTERN so that it refers to small data
3068 using explicit relocations. */
3071 mips_rewrite_small_data (rtx pattern
)
3073 pattern
= copy_insn (pattern
);
3074 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3078 /* We need a lot of little routines to check the range of MIPS16 immediate
3082 m16_check_op (rtx op
, int low
, int high
, int mask
)
3084 return (GET_CODE (op
) == CONST_INT
3085 && IN_RANGE (INTVAL (op
), low
, high
)
3086 && (INTVAL (op
) & mask
) == 0);
3090 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3092 return m16_check_op (op
, 0x1, 0x8, 0);
3096 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3098 return m16_check_op (op
, -0x8, 0x7, 0);
3102 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3104 return m16_check_op (op
, -0x7, 0x8, 0);
3108 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3110 return m16_check_op (op
, -0x10, 0xf, 0);
3114 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3116 return m16_check_op (op
, -0xf, 0x10, 0);
3120 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3122 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3126 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3128 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3132 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3134 return m16_check_op (op
, -0x80, 0x7f, 0);
3138 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3140 return m16_check_op (op
, -0x7f, 0x80, 0);
3144 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3146 return m16_check_op (op
, 0x0, 0xff, 0);
3150 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3152 return m16_check_op (op
, -0xff, 0x0, 0);
3156 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3158 return m16_check_op (op
, -0x1, 0xfe, 0);
3162 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3164 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3168 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3170 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3174 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3176 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3180 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3182 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3185 /* The cost of loading values from the constant pool. It should be
3186 larger than the cost of any constant we want to synthesize inline. */
3187 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3189 /* Return the cost of X when used as an operand to the MIPS16 instruction
3190 that implements CODE. Return -1 if there is no such instruction, or if
3191 X is not a valid immediate operand for it. */
3194 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3201 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3202 other shifts are extended. The shift patterns truncate the shift
3203 count to the right size, so there are no out-of-range values. */
3204 if (IN_RANGE (x
, 1, 8))
3206 return COSTS_N_INSNS (1);
3209 if (IN_RANGE (x
, -128, 127))
3211 if (SMALL_OPERAND (x
))
3212 return COSTS_N_INSNS (1);
3216 /* Like LE, but reject the always-true case. */
3220 /* We add 1 to the immediate and use SLT. */
3223 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3226 if (IN_RANGE (x
, 0, 255))
3228 if (SMALL_OPERAND_UNSIGNED (x
))
3229 return COSTS_N_INSNS (1);
3234 /* Equality comparisons with 0 are cheap. */
3244 /* Return true if there is a non-MIPS16 instruction that implements CODE
3245 and if that instruction accepts X as an immediate operand. */
3248 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3255 /* All shift counts are truncated to a valid constant. */
3260 /* Likewise rotates, if the target supports rotates at all. */
3266 /* These instructions take 16-bit unsigned immediates. */
3267 return SMALL_OPERAND_UNSIGNED (x
);
3272 /* These instructions take 16-bit signed immediates. */
3273 return SMALL_OPERAND (x
);
3279 /* The "immediate" forms of these instructions are really
3280 implemented as comparisons with register 0. */
3285 /* Likewise, meaning that the only valid immediate operand is 1. */
3289 /* We add 1 to the immediate and use SLT. */
3290 return SMALL_OPERAND (x
+ 1);
3293 /* Likewise SLTU, but reject the always-true case. */
3294 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3298 /* The bit position and size are immediate operands. */
3299 return ISA_HAS_EXT_INS
;
3302 /* By default assume that $0 can be used for 0. */
3307 /* Return the cost of binary operation X, given that the instruction
3308 sequence for a word-sized or smaller operation has cost SINGLE_COST
3309 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3312 mips_binary_cost (rtx x
, int single_cost
, int double_cost
)
3316 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3321 + rtx_cost (XEXP (x
, 0), 0, !optimize_size
)
3322 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), !optimize_size
));
3325 /* Return the cost of floating-point multiplications of mode MODE. */
3328 mips_fp_mult_cost (enum machine_mode mode
)
3330 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3333 /* Return the cost of floating-point divisions of mode MODE. */
3336 mips_fp_div_cost (enum machine_mode mode
)
3338 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3341 /* Return the cost of sign-extending OP to mode MODE, not including the
3342 cost of OP itself. */
3345 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3348 /* Extended loads are as cheap as unextended ones. */
3351 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3352 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3355 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3356 /* We can use SEB or SEH. */
3357 return COSTS_N_INSNS (1);
3359 /* We need to use a shift left and a shift right. */
3360 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3363 /* Return the cost of zero-extending OP to mode MODE, not including the
3364 cost of OP itself. */
3367 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3370 /* Extended loads are as cheap as unextended ones. */
3373 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3374 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3375 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3377 if (GENERATE_MIPS16E
)
3378 /* We can use ZEB or ZEH. */
3379 return COSTS_N_INSNS (1);
3382 /* We need to load 0xff or 0xffff into a register and use AND. */
3383 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3385 /* We can use ANDI. */
3386 return COSTS_N_INSNS (1);
3389 /* Implement TARGET_RTX_COSTS. */
3392 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
3395 enum machine_mode mode
= GET_MODE (x
);
3396 bool float_mode_p
= FLOAT_MODE_P (mode
);
3400 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3401 appear in the instruction stream, and the cost of a comparison is
3402 really the cost of the branch or scc condition. At the time of
3403 writing, GCC only uses an explicit outer COMPARE code when optabs
3404 is testing whether a constant is expensive enough to force into a
3405 register. We want optabs to pass such constants through the MIPS
3406 expanders instead, so make all constants very cheap here. */
3407 if (outer_code
== COMPARE
)
3409 gcc_assert (CONSTANT_P (x
));
3417 /* Treat *clear_upper32-style ANDs as having zero cost in the
3418 second operand. The cost is entirely in the first operand.
3420 ??? This is needed because we would otherwise try to CSE
3421 the constant operand. Although that's the right thing for
3422 instructions that continue to be a register operation throughout
3423 compilation, it is disastrous for instructions that could
3424 later be converted into a memory operation. */
3426 && outer_code
== AND
3427 && UINTVAL (x
) == 0xffffffff)
3435 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3444 /* When not optimizing for size, we care more about the cost
3445 of hot code, and hot code is often in a loop. If a constant
3446 operand needs to be forced into a register, we will often be
3447 able to hoist the constant load out of the loop, so the load
3448 should not contribute to the cost. */
3450 || mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3462 if (force_to_mem_operand (x
, VOIDmode
))
3464 *total
= COSTS_N_INSNS (1);
3467 cost
= mips_const_insns (x
);
3470 /* If the constant is likely to be stored in a GPR, SETs of
3471 single-insn constants are as cheap as register sets; we
3472 never want to CSE them.
3474 Don't reduce the cost of storing a floating-point zero in
3475 FPRs. If we have a zero in an FPR for other reasons, we
3476 can get better cfg-cleanup and delayed-branch results by
3477 using it consistently, rather than using $0 sometimes and
3478 an FPR at other times. Also, moves between floating-point
3479 registers are sometimes cheaper than (D)MTC1 $0. */
3481 && outer_code
== SET
3482 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3484 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3485 want to CSE the constant itself. It is usually better to
3486 have N copies of the last operation in the sequence and one
3487 shared copy of the other operations. (Note that this is
3488 not true for MIPS16 code, where the final operation in the
3489 sequence is often an extended instruction.)
3491 Also, if we have a CONST_INT, we don't know whether it is
3492 for a word or doubleword operation, so we cannot rely on
3493 the result of mips_build_integer. */
3494 else if (!TARGET_MIPS16
3495 && (outer_code
== SET
|| mode
== VOIDmode
))
3497 *total
= COSTS_N_INSNS (cost
);
3500 /* The value will need to be fetched from the constant pool. */
3501 *total
= CONSTANT_POOL_COST
;
3505 /* If the address is legitimate, return the number of
3506 instructions it needs. */
3508 cost
= mips_address_insns (addr
, mode
, true);
3511 *total
= COSTS_N_INSNS (cost
+ 1);
3514 /* Check for a scaled indexed address. */
3515 if (mips_lwxs_address_p (addr
))
3517 *total
= COSTS_N_INSNS (2);
3520 /* Otherwise use the default handling. */
3524 *total
= COSTS_N_INSNS (6);
3528 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3532 /* Check for a *clear_upper32 pattern and treat it like a zero
3533 extension. See the pattern's comment for details. */
3536 && CONST_INT_P (XEXP (x
, 1))
3537 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3539 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3540 + rtx_cost (XEXP (x
, 0), 0, speed
));
3547 /* Double-word operations use two single-word operations. */
3548 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3556 if (CONSTANT_P (XEXP (x
, 1)))
3557 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3559 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3564 *total
= mips_cost
->fp_add
;
3566 *total
= COSTS_N_INSNS (4);
3570 /* Low-part immediates need an extended MIPS16 instruction. */
3571 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3572 + rtx_cost (XEXP (x
, 0), 0, speed
));
3587 /* Branch comparisons have VOIDmode, so use the first operand's
3589 mode
= GET_MODE (XEXP (x
, 0));
3590 if (FLOAT_MODE_P (mode
))
3592 *total
= mips_cost
->fp_add
;
3595 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3600 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3601 && TARGET_FUSED_MADD
3602 && !HONOR_NANS (mode
)
3603 && !HONOR_SIGNED_ZEROS (mode
))
3605 /* See if we can use NMADD or NMSUB. See mips.md for the
3606 associated patterns. */
3607 rtx op0
= XEXP (x
, 0);
3608 rtx op1
= XEXP (x
, 1);
3609 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3611 *total
= (mips_fp_mult_cost (mode
)
3612 + rtx_cost (XEXP (XEXP (op0
, 0), 0), 0, speed
)
3613 + rtx_cost (XEXP (op0
, 1), 0, speed
)
3614 + rtx_cost (op1
, 0, speed
));
3617 if (GET_CODE (op1
) == MULT
)
3619 *total
= (mips_fp_mult_cost (mode
)
3620 + rtx_cost (op0
, 0, speed
)
3621 + rtx_cost (XEXP (op1
, 0), 0, speed
)
3622 + rtx_cost (XEXP (op1
, 1), 0, speed
));
3631 /* If this is part of a MADD or MSUB, treat the PLUS as
3634 && TARGET_FUSED_MADD
3635 && GET_CODE (XEXP (x
, 0)) == MULT
)
3638 *total
= mips_cost
->fp_add
;
3642 /* Double-word operations require three single-word operations and
3643 an SLTU. The MIPS16 version then needs to move the result of
3644 the SLTU from $24 to a MIPS16 register. */
3645 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3646 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4));
3651 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3652 && TARGET_FUSED_MADD
3653 && !HONOR_NANS (mode
)
3654 && HONOR_SIGNED_ZEROS (mode
))
3656 /* See if we can use NMADD or NMSUB. See mips.md for the
3657 associated patterns. */
3658 rtx op
= XEXP (x
, 0);
3659 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3660 && GET_CODE (XEXP (op
, 0)) == MULT
)
3662 *total
= (mips_fp_mult_cost (mode
)
3663 + rtx_cost (XEXP (XEXP (op
, 0), 0), 0, speed
)
3664 + rtx_cost (XEXP (XEXP (op
, 0), 1), 0, speed
)
3665 + rtx_cost (XEXP (op
, 1), 0, speed
));
3671 *total
= mips_cost
->fp_add
;
3673 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3678 *total
= mips_fp_mult_cost (mode
);
3679 else if (mode
== DImode
&& !TARGET_64BIT
)
3680 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3681 where the mulsidi3 always includes an MFHI and an MFLO. */
3682 *total
= (optimize_size
3683 ? COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9)
3684 : mips_cost
->int_mult_si
* 3 + 6);
3685 else if (optimize_size
)
3686 *total
= (ISA_HAS_MUL3
? 1 : 2);
3687 else if (mode
== DImode
)
3688 *total
= mips_cost
->int_mult_di
;
3690 *total
= mips_cost
->int_mult_si
;
3694 /* Check for a reciprocal. */
3697 && flag_unsafe_math_optimizations
3698 && XEXP (x
, 0) == CONST1_RTX (mode
))
3700 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3701 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3702 division as being free. */
3703 *total
= rtx_cost (XEXP (x
, 1), 0, speed
);
3705 *total
= mips_fp_div_cost (mode
) + rtx_cost (XEXP (x
, 1), 0, speed
);
3714 *total
= mips_fp_div_cost (mode
);
3723 /* It is our responsibility to make division by a power of 2
3724 as cheap as 2 register additions if we want the division
3725 expanders to be used for such operations; see the setting
3726 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3727 should always produce shorter code than using
3728 expand_sdiv2_pow2. */
3730 && CONST_INT_P (XEXP (x
, 1))
3731 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3733 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), 0, speed
);
3736 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3738 else if (mode
== DImode
)
3739 *total
= mips_cost
->int_div_di
;
3741 *total
= mips_cost
->int_div_si
;
3745 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3749 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3753 case UNSIGNED_FLOAT
:
3756 case FLOAT_TRUNCATE
:
3757 *total
= mips_cost
->fp_add
;
3765 /* Implement TARGET_ADDRESS_COST. */
3768 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3770 return mips_address_insns (addr
, SImode
, false);
3773 /* Return one word of double-word value OP, taking into account the fixed
3774 endianness of certain registers. HIGH_P is true to select the high part,
3775 false to select the low part. */
3778 mips_subword (rtx op
, bool high_p
)
3780 unsigned int byte
, offset
;
3781 enum machine_mode mode
;
3783 mode
= GET_MODE (op
);
3784 if (mode
== VOIDmode
)
3785 mode
= TARGET_64BIT
? TImode
: DImode
;
3787 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
3788 byte
= UNITS_PER_WORD
;
3792 if (FP_REG_RTX_P (op
))
3794 /* Paired FPRs are always ordered little-endian. */
3795 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
3796 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
3800 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
3802 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
3805 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3808 mips_split_64bit_move_p (rtx dest
, rtx src
)
3813 /* FPR-to-FPR moves can be done in a single instruction, if they're
3815 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
3818 /* Check for floating-point loads and stores. */
3819 if (ISA_HAS_LDC1_SDC1
)
3821 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
3823 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
3829 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3830 this function handles 64-bit moves for which mips_split_64bit_move_p
3831 holds. For 64-bit targets, this function handles 128-bit moves. */
3834 mips_split_doubleword_move (rtx dest
, rtx src
)
3838 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
3840 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
3841 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
3842 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
3843 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
3844 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
3845 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
3846 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
3847 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
3848 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
3849 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
3850 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
3851 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
3852 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
3853 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
3857 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
3859 low_dest
= mips_subword (dest
, false);
3860 mips_emit_move (low_dest
, mips_subword (src
, false));
3862 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
3864 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
3866 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
3868 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
3870 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
3872 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
3876 /* The operation can be split into two normal moves. Decide in
3877 which order to do them. */
3878 low_dest
= mips_subword (dest
, false);
3879 if (REG_P (low_dest
)
3880 && reg_overlap_mentioned_p (low_dest
, src
))
3882 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3883 mips_emit_move (low_dest
, mips_subword (src
, false));
3887 mips_emit_move (low_dest
, mips_subword (src
, false));
3888 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3893 /* Return the appropriate instructions to move SRC into DEST. Assume
3894 that SRC is operand 1 and DEST is operand 0. */
3897 mips_output_move (rtx dest
, rtx src
)
3899 enum rtx_code dest_code
, src_code
;
3900 enum machine_mode mode
;
3901 enum mips_symbol_type symbol_type
;
3904 dest_code
= GET_CODE (dest
);
3905 src_code
= GET_CODE (src
);
3906 mode
= GET_MODE (dest
);
3907 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
3909 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
3912 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
3913 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
3915 if (dest_code
== REG
)
3917 if (GP_REG_P (REGNO (dest
)))
3918 return "move\t%0,%z1";
3920 /* Moves to HI are handled by special .md insns. */
3921 if (REGNO (dest
) == LO_REGNUM
)
3924 if (DSP_ACC_REG_P (REGNO (dest
)))
3926 static char retval
[] = "mt__\t%z1,%q0";
3928 retval
[2] = reg_names
[REGNO (dest
)][4];
3929 retval
[3] = reg_names
[REGNO (dest
)][5];
3933 if (FP_REG_P (REGNO (dest
)))
3934 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3936 if (ALL_COP_REG_P (REGNO (dest
)))
3938 static char retval
[] = "dmtc_\t%z1,%0";
3940 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3941 return dbl_p
? retval
: retval
+ 1;
3944 if (dest_code
== MEM
)
3945 switch (GET_MODE_SIZE (mode
))
3947 case 1: return "sb\t%z1,%0";
3948 case 2: return "sh\t%z1,%0";
3949 case 4: return "sw\t%z1,%0";
3950 case 8: return "sd\t%z1,%0";
3953 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
3955 if (src_code
== REG
)
3957 /* Moves from HI are handled by special .md insns. */
3958 if (REGNO (src
) == LO_REGNUM
)
3960 /* When generating VR4120 or VR4130 code, we use MACC and
3961 DMACC instead of MFLO. This avoids both the normal
3962 MIPS III HI/LO hazards and the errata related to
3965 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3969 if (DSP_ACC_REG_P (REGNO (src
)))
3971 static char retval
[] = "mf__\t%0,%q1";
3973 retval
[2] = reg_names
[REGNO (src
)][4];
3974 retval
[3] = reg_names
[REGNO (src
)][5];
3978 if (FP_REG_P (REGNO (src
)))
3979 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3981 if (ALL_COP_REG_P (REGNO (src
)))
3983 static char retval
[] = "dmfc_\t%0,%1";
3985 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3986 return dbl_p
? retval
: retval
+ 1;
3989 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
3990 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3993 if (src_code
== MEM
)
3994 switch (GET_MODE_SIZE (mode
))
3996 case 1: return "lbu\t%0,%1";
3997 case 2: return "lhu\t%0,%1";
3998 case 4: return "lw\t%0,%1";
3999 case 8: return "ld\t%0,%1";
4002 if (src_code
== CONST_INT
)
4004 /* Don't use the X format for the operand itself, because that
4005 will give out-of-range numbers for 64-bit hosts and 32-bit
4008 return "li\t%0,%1\t\t\t# %X1";
4010 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4013 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4017 if (src_code
== HIGH
)
4018 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4020 if (CONST_GP_P (src
))
4021 return "move\t%0,%1";
4023 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4024 && mips_lo_relocs
[symbol_type
] != 0)
4026 /* A signed 16-bit constant formed by applying a relocation
4027 operator to a symbolic address. */
4028 gcc_assert (!mips_split_p
[symbol_type
]);
4029 return "li\t%0,%R1";
4032 if (symbolic_operand (src
, VOIDmode
))
4034 gcc_assert (TARGET_MIPS16
4035 ? TARGET_MIPS16_TEXT_LOADS
4036 : !TARGET_EXPLICIT_RELOCS
);
4037 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4040 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4042 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4044 if (GET_MODE (dest
) == V2SFmode
)
4045 return "mov.ps\t%0,%1";
4047 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4050 if (dest_code
== MEM
)
4051 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4053 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4055 if (src_code
== MEM
)
4056 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4058 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4060 static char retval
[] = "l_c_\t%0,%1";
4062 retval
[1] = (dbl_p
? 'd' : 'w');
4063 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4066 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4068 static char retval
[] = "s_c_\t%1,%0";
4070 retval
[1] = (dbl_p
? 'd' : 'w');
4071 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4077 /* Return true if CMP1 is a suitable second operand for integer ordering
4078 test CODE. See also the *sCC patterns in mips.md. */
4081 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4087 return reg_or_0_operand (cmp1
, VOIDmode
);
4091 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4095 return arith_operand (cmp1
, VOIDmode
);
4098 return sle_operand (cmp1
, VOIDmode
);
4101 return sleu_operand (cmp1
, VOIDmode
);
4108 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4109 integer ordering test *CODE, or if an equivalent combination can
4110 be formed by adjusting *CODE and *CMP1. When returning true, update
4111 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4115 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4116 enum machine_mode mode
)
4118 HOST_WIDE_INT plus_one
;
4120 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4123 if (GET_CODE (*cmp1
) == CONST_INT
)
4127 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4128 if (INTVAL (*cmp1
) < plus_one
)
4131 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4137 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4141 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4152 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4153 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4154 is nonnull, it's OK to set TARGET to the inverse of the result and
4155 flip *INVERT_PTR instead. */
4158 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4159 rtx target
, rtx cmp0
, rtx cmp1
)
4161 enum machine_mode mode
;
4163 /* First see if there is a MIPS instruction that can do this operation.
4164 If not, try doing the same for the inverse operation. If that also
4165 fails, force CMP1 into a register and try again. */
4166 mode
= GET_MODE (cmp0
);
4167 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4168 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4171 enum rtx_code inv_code
= reverse_condition (code
);
4172 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4174 cmp1
= force_reg (mode
, cmp1
);
4175 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4177 else if (invert_ptr
== 0)
4181 inv_target
= mips_force_binary (GET_MODE (target
),
4182 inv_code
, cmp0
, cmp1
);
4183 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4187 *invert_ptr
= !*invert_ptr
;
4188 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4193 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4194 The register will have the same mode as CMP0. */
4197 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4199 if (cmp1
== const0_rtx
)
4202 if (uns_arith_operand (cmp1
, VOIDmode
))
4203 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4204 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4206 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4207 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4210 /* Convert *CODE into a code that can be used in a floating-point
4211 scc instruction (C.cond.fmt). Return true if the values of
4212 the condition code registers will be inverted, with 0 indicating
4213 that the condition holds. */
4216 mips_reversed_fp_cond (enum rtx_code
*code
)
4223 *code
= reverse_condition_maybe_unordered (*code
);
4231 /* Convert a comparison into something that can be used in a branch or
4232 conditional move. cmp_operands[0] and cmp_operands[1] are the values
4233 being compared and *CODE is the code used to compare them.
4235 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4236 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4237 otherwise any standard branch condition can be used. The standard branch
4240 - EQ or NE between two registers.
4241 - any comparison between a register and zero. */
4244 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4246 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
4248 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
4250 *op0
= cmp_operands
[0];
4251 *op1
= cmp_operands
[1];
4253 else if (*code
== EQ
|| *code
== NE
)
4257 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
4262 *op0
= cmp_operands
[0];
4263 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
4268 /* The comparison needs a separate scc instruction. Store the
4269 result of the scc in *OP0 and compare it against zero. */
4270 bool invert
= false;
4271 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
4272 mips_emit_int_order_test (*code
, &invert
, *op0
,
4273 cmp_operands
[0], cmp_operands
[1]);
4274 *code
= (invert
? EQ
: NE
);
4278 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands
[0])))
4280 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4281 mips_emit_binary (*code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
4287 enum rtx_code cmp_code
;
4289 /* Floating-point tests use a separate C.cond.fmt comparison to
4290 set a condition code register. The branch or conditional move
4291 will then compare that register against zero.
4293 Set CMP_CODE to the code of the comparison instruction and
4294 *CODE to the code that the branch or move should use. */
4296 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4298 ? gen_reg_rtx (CCmode
)
4299 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4301 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
4305 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
4306 Store the result in TARGET and return true if successful.
4308 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
4311 mips_expand_scc (enum rtx_code code
, rtx target
)
4313 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
4316 if (code
== EQ
|| code
== NE
)
4319 && reg_imm10_operand (cmp_operands
[1], GET_MODE (cmp_operands
[1])))
4320 mips_emit_binary (code
, target
, cmp_operands
[0], cmp_operands
[1]);
4323 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
4324 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4328 mips_emit_int_order_test (code
, 0, target
,
4329 cmp_operands
[0], cmp_operands
[1]);
4333 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
4334 CODE and jump to OPERANDS[0] if the condition holds. */
4337 mips_expand_conditional_branch (rtx
*operands
, enum rtx_code code
)
4339 rtx op0
, op1
, condition
;
4341 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4342 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4343 emit_jump_insn (gen_condjump (condition
, operands
[0]));
4348 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4349 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4352 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4353 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4358 reversed_p
= mips_reversed_fp_cond (&cond
);
4359 cmp_result
= gen_reg_rtx (CCV2mode
);
4360 emit_insn (gen_scc_ps (cmp_result
,
4361 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4363 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4366 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4370 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4371 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4372 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4375 mips_expand_conditional_move (rtx
*operands
)
4380 code
= GET_CODE (operands
[1]);
4381 mips_emit_compare (&code
, &op0
, &op1
, true);
4382 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
),
4383 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4384 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4385 operands
[2], operands
[3])));
4388 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4389 then trap if the condition holds. */
4392 mips_expand_conditional_trap (enum rtx_code code
)
4395 enum machine_mode mode
;
4397 /* MIPS conditional trap instructions don't have GT or LE flavors,
4398 so we must swap the operands and convert to LT and GE respectively. */
4405 code
= swap_condition (code
);
4406 op0
= cmp_operands
[1];
4407 op1
= cmp_operands
[0];
4411 op0
= cmp_operands
[0];
4412 op1
= cmp_operands
[1];
4416 mode
= GET_MODE (cmp_operands
[0]);
4417 op0
= force_reg (mode
, op0
);
4418 if (!arith_operand (op1
, mode
))
4419 op1
= force_reg (mode
, op1
);
4421 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4422 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4426 /* Initialize *CUM for a call to a function of type FNTYPE. */
4429 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4431 memset (cum
, 0, sizeof (*cum
));
4432 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4433 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4436 /* Fill INFO with information about a single argument. CUM is the
4437 cumulative state for earlier arguments. MODE is the mode of this
4438 argument and TYPE is its type (if known). NAMED is true if this
4439 is a named (fixed) argument rather than a variable one. */
4442 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4443 enum machine_mode mode
, tree type
, int named
)
4445 bool doubleword_aligned_p
;
4446 unsigned int num_bytes
, num_words
, max_regs
;
4448 /* Work out the size of the argument. */
4449 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4450 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4452 /* Decide whether it should go in a floating-point register, assuming
4453 one is free. Later code checks for availability.
4455 The checks against UNITS_PER_FPVALUE handle the soft-float and
4456 single-float cases. */
4460 /* The EABI conventions have traditionally been defined in terms
4461 of TYPE_MODE, regardless of the actual type. */
4462 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4463 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4464 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4469 /* Only leading floating-point scalars are passed in
4470 floating-point registers. We also handle vector floats the same
4471 say, which is OK because they are not covered by the standard ABI. */
4472 info
->fpr_p
= (!cum
->gp_reg_found
4473 && cum
->arg_number
< 2
4475 || SCALAR_FLOAT_TYPE_P (type
)
4476 || VECTOR_FLOAT_TYPE_P (type
))
4477 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4478 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4479 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4484 /* Scalar, complex and vector floating-point types are passed in
4485 floating-point registers, as long as this is a named rather
4486 than a variable argument. */
4487 info
->fpr_p
= (named
4488 && (type
== 0 || FLOAT_TYPE_P (type
))
4489 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4490 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4491 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4492 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4494 /* ??? According to the ABI documentation, the real and imaginary
4495 parts of complex floats should be passed in individual registers.
4496 The real and imaginary parts of stack arguments are supposed
4497 to be contiguous and there should be an extra word of padding
4500 This has two problems. First, it makes it impossible to use a
4501 single "void *" va_list type, since register and stack arguments
4502 are passed differently. (At the time of writing, MIPSpro cannot
4503 handle complex float varargs correctly.) Second, it's unclear
4504 what should happen when there is only one register free.
4506 For now, we assume that named complex floats should go into FPRs
4507 if there are two FPRs free, otherwise they should be passed in the
4508 same way as a struct containing two floats. */
4510 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4511 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4513 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4514 info
->fpr_p
= false;
4524 /* See whether the argument has doubleword alignment. */
4525 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
4527 /* Set REG_OFFSET to the register count we're interested in.
4528 The EABI allocates the floating-point registers separately,
4529 but the other ABIs allocate them like integer registers. */
4530 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4534 /* Advance to an even register if the argument is doubleword-aligned. */
4535 if (doubleword_aligned_p
)
4536 info
->reg_offset
+= info
->reg_offset
& 1;
4538 /* Work out the offset of a stack argument. */
4539 info
->stack_offset
= cum
->stack_words
;
4540 if (doubleword_aligned_p
)
4541 info
->stack_offset
+= info
->stack_offset
& 1;
4543 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4545 /* Partition the argument between registers and stack. */
4546 info
->reg_words
= MIN (num_words
, max_regs
);
4547 info
->stack_words
= num_words
- info
->reg_words
;
4550 /* INFO describes a register argument that has the normal format for the
4551 argument's mode. Return the register it uses, assuming that FPRs are
4552 available if HARD_FLOAT_P. */
4555 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4557 if (!info
->fpr_p
|| !hard_float_p
)
4558 return GP_ARG_FIRST
+ info
->reg_offset
;
4559 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4560 /* In o32, the second argument is always passed in $f14
4561 for TARGET_DOUBLE_FLOAT, regardless of whether the
4562 first argument was a word or doubleword. */
4563 return FP_ARG_FIRST
+ 2;
4565 return FP_ARG_FIRST
+ info
->reg_offset
;
4568 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4571 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4573 return !TARGET_OLDABI
;
4576 /* Implement FUNCTION_ARG. */
4579 mips_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4580 tree type
, int named
)
4582 struct mips_arg_info info
;
4584 /* We will be called with a mode of VOIDmode after the last argument
4585 has been seen. Whatever we return will be passed to the call expander.
4586 If we need a MIPS16 fp_code, return a REG with the code stored as
4588 if (mode
== VOIDmode
)
4590 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4591 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4596 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4598 /* Return straight away if the whole argument is passed on the stack. */
4599 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4602 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4603 contains a double in its entirety, then that 64-bit chunk is passed
4604 in a floating-point register. */
4606 && TARGET_HARD_FLOAT
4609 && TREE_CODE (type
) == RECORD_TYPE
4610 && TYPE_SIZE_UNIT (type
)
4611 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4615 /* First check to see if there is any such field. */
4616 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4617 if (TREE_CODE (field
) == FIELD_DECL
4618 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4619 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4620 && host_integerp (bit_position (field
), 0)
4621 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4626 /* Now handle the special case by returning a PARALLEL
4627 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4628 chunks are passed in registers. */
4630 HOST_WIDE_INT bitpos
;
4633 /* assign_parms checks the mode of ENTRY_PARM, so we must
4634 use the actual mode here. */
4635 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4638 field
= TYPE_FIELDS (type
);
4639 for (i
= 0; i
< info
.reg_words
; i
++)
4643 for (; field
; field
= TREE_CHAIN (field
))
4644 if (TREE_CODE (field
) == FIELD_DECL
4645 && int_bit_position (field
) >= bitpos
)
4649 && int_bit_position (field
) == bitpos
4650 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4651 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4652 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4654 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4657 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4658 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4660 bitpos
+= BITS_PER_WORD
;
4666 /* Handle the n32/n64 conventions for passing complex floating-point
4667 arguments in FPR pairs. The real part goes in the lower register
4668 and the imaginary part goes in the upper register. */
4671 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4674 enum machine_mode inner
;
4677 inner
= GET_MODE_INNER (mode
);
4678 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4679 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4681 /* Real part in registers, imaginary part on stack. */
4682 gcc_assert (info
.stack_words
== info
.reg_words
);
4683 return gen_rtx_REG (inner
, regno
);
4687 gcc_assert (info
.stack_words
== 0);
4688 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4689 gen_rtx_REG (inner
, regno
),
4691 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4693 regno
+ info
.reg_words
/ 2),
4694 GEN_INT (GET_MODE_SIZE (inner
)));
4695 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4699 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4702 /* Implement FUNCTION_ARG_ADVANCE. */
4705 mips_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4706 tree type
, int named
)
4708 struct mips_arg_info info
;
4710 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4713 cum
->gp_reg_found
= true;
4715 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4716 an explanation of what this code does. It assumes that we're using
4717 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4719 if (cum
->arg_number
< 2 && info
.fpr_p
)
4720 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4722 /* Advance the register count. This has the effect of setting
4723 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4724 argument required us to skip the final GPR and pass the whole
4725 argument on the stack. */
4726 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4727 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4728 else if (info
.reg_words
> 0)
4729 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4731 /* Advance the stack word count. */
4732 if (info
.stack_words
> 0)
4733 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4738 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4741 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
4742 enum machine_mode mode
, tree type
, bool named
)
4744 struct mips_arg_info info
;
4746 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4747 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
4750 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4751 PARM_BOUNDARY bits of alignment, but will be given anything up
4752 to STACK_BOUNDARY bits if the type requires it. */
4755 mips_function_arg_boundary (enum machine_mode mode
, tree type
)
4757 unsigned int alignment
;
4759 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
4760 if (alignment
< PARM_BOUNDARY
)
4761 alignment
= PARM_BOUNDARY
;
4762 if (alignment
> STACK_BOUNDARY
)
4763 alignment
= STACK_BOUNDARY
;
4767 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4768 upward rather than downward. In other words, return true if the
4769 first byte of the stack slot has useful data, false if the last
4773 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
4775 /* On little-endian targets, the first byte of every stack argument
4776 is passed in the first byte of the stack slot. */
4777 if (!BYTES_BIG_ENDIAN
)
4780 /* Otherwise, integral types are padded downward: the last byte of a
4781 stack argument is passed in the last byte of the stack slot. */
4783 ? (INTEGRAL_TYPE_P (type
)
4784 || POINTER_TYPE_P (type
)
4785 || FIXED_POINT_TYPE_P (type
))
4786 : (SCALAR_INT_MODE_P (mode
)
4787 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
4790 /* Big-endian o64 pads floating-point arguments downward. */
4791 if (mips_abi
== ABI_O64
)
4792 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4795 /* Other types are padded upward for o32, o64, n32 and n64. */
4796 if (mips_abi
!= ABI_EABI
)
4799 /* Arguments smaller than a stack slot are padded downward. */
4800 if (mode
!= BLKmode
)
4801 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
4803 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
4806 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4807 if the least significant byte of the register has useful data. Return
4808 the opposite if the most significant byte does. */
4811 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4813 /* No shifting is required for floating-point arguments. */
4814 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4815 return !BYTES_BIG_ENDIAN
;
4817 /* Otherwise, apply the same padding to register arguments as we do
4818 to stack arguments. */
4819 return mips_pad_arg_upward (mode
, type
);
4822 /* Return nonzero when an argument must be passed by reference. */
4825 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4826 enum machine_mode mode
, const_tree type
,
4827 bool named ATTRIBUTE_UNUSED
)
4829 if (mips_abi
== ABI_EABI
)
4833 /* ??? How should SCmode be handled? */
4834 if (mode
== DImode
|| mode
== DFmode
4835 || mode
== DQmode
|| mode
== UDQmode
4836 || mode
== DAmode
|| mode
== UDAmode
)
4839 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4840 return size
== -1 || size
> UNITS_PER_WORD
;
4844 /* If we have a variable-sized parameter, we have no choice. */
4845 return targetm
.calls
.must_pass_in_stack (mode
, type
);
4849 /* Implement TARGET_CALLEE_COPIES. */
4852 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4853 enum machine_mode mode ATTRIBUTE_UNUSED
,
4854 const_tree type ATTRIBUTE_UNUSED
, bool named
)
4856 return mips_abi
== ABI_EABI
&& named
;
4859 /* See whether VALTYPE is a record whose fields should be returned in
4860 floating-point registers. If so, return the number of fields and
4861 list them in FIELDS (which should have two elements). Return 0
4864 For n32 & n64, a structure with one or two fields is returned in
4865 floating-point registers as long as every field has a floating-point
4869 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
4877 if (TREE_CODE (valtype
) != RECORD_TYPE
)
4881 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
4883 if (TREE_CODE (field
) != FIELD_DECL
)
4886 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
4892 fields
[i
++] = field
;
4897 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4898 a value in the most significant part of $2/$3 if:
4900 - the target is big-endian;
4902 - the value has a structure or union type (we generalize this to
4903 cover aggregates from other languages too); and
4905 - the structure is not returned in floating-point registers. */
4908 mips_return_in_msb (const_tree valtype
)
4912 return (TARGET_NEWABI
4913 && TARGET_BIG_ENDIAN
4914 && AGGREGATE_TYPE_P (valtype
)
4915 && mips_fpr_return_fields (valtype
, fields
) == 0);
4918 /* Return true if the function return value MODE will get returned in a
4919 floating-point register. */
4922 mips_return_mode_in_fpr_p (enum machine_mode mode
)
4924 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4925 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
4926 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4927 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
4930 /* Return the representation of an FPR return register when the
4931 value being returned in FP_RETURN has mode VALUE_MODE and the
4932 return type itself has mode TYPE_MODE. On NewABI targets,
4933 the two modes may be different for structures like:
4935 struct __attribute__((packed)) foo { float f; }
4937 where we return the SFmode value of "f" in FP_RETURN, but where
4938 the structure itself has mode BLKmode. */
4941 mips_return_fpr_single (enum machine_mode type_mode
,
4942 enum machine_mode value_mode
)
4946 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
4947 if (type_mode
!= value_mode
)
4949 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
4950 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
4955 /* Return a composite value in a pair of floating-point registers.
4956 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4957 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4960 For n32 & n64, $f0 always holds the first value and $f2 the second.
4961 Otherwise the values are packed together as closely as possible. */
4964 mips_return_fpr_pair (enum machine_mode mode
,
4965 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
4966 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
4970 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
4971 return gen_rtx_PARALLEL
4974 gen_rtx_EXPR_LIST (VOIDmode
,
4975 gen_rtx_REG (mode1
, FP_RETURN
),
4977 gen_rtx_EXPR_LIST (VOIDmode
,
4978 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
4979 GEN_INT (offset2
))));
4983 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4984 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4985 VALTYPE is null and MODE is the mode of the return value. */
4988 mips_function_value (const_tree valtype
, enum machine_mode mode
)
4995 mode
= TYPE_MODE (valtype
);
4996 unsigned_p
= TYPE_UNSIGNED (valtype
);
4998 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4999 we must promote the mode just as PROMOTE_MODE does. */
5000 mode
= promote_mode (valtype
, mode
, &unsigned_p
, 1);
5002 /* Handle structures whose fields are returned in $f0/$f2. */
5003 switch (mips_fpr_return_fields (valtype
, fields
))
5006 return mips_return_fpr_single (mode
,
5007 TYPE_MODE (TREE_TYPE (fields
[0])));
5010 return mips_return_fpr_pair (mode
,
5011 TYPE_MODE (TREE_TYPE (fields
[0])),
5012 int_byte_position (fields
[0]),
5013 TYPE_MODE (TREE_TYPE (fields
[1])),
5014 int_byte_position (fields
[1]));
5017 /* If a value is passed in the most significant part of a register, see
5018 whether we have to round the mode up to a whole number of words. */
5019 if (mips_return_in_msb (valtype
))
5021 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5022 if (size
% UNITS_PER_WORD
!= 0)
5024 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5025 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5029 /* For EABI, the class of return register depends entirely on MODE.
5030 For example, "struct { some_type x; }" and "union { some_type x; }"
5031 are returned in the same way as a bare "some_type" would be.
5032 Other ABIs only use FPRs for scalar, complex or vector types. */
5033 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5034 return gen_rtx_REG (mode
, GP_RETURN
);
5039 /* Handle long doubles for n32 & n64. */
5041 return mips_return_fpr_pair (mode
,
5043 DImode
, GET_MODE_SIZE (mode
) / 2);
5045 if (mips_return_mode_in_fpr_p (mode
))
5047 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5048 return mips_return_fpr_pair (mode
,
5049 GET_MODE_INNER (mode
), 0,
5050 GET_MODE_INNER (mode
),
5051 GET_MODE_SIZE (mode
) / 2);
5053 return gen_rtx_REG (mode
, FP_RETURN
);
5057 return gen_rtx_REG (mode
, GP_RETURN
);
5060 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5061 all BLKmode objects are returned in memory. Under the n32, n64
5062 and embedded ABIs, small structures are returned in a register.
5063 Objects with varying size must still be returned in memory, of
5067 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5069 return (TARGET_OLDABI
5070 ? TYPE_MODE (type
) == BLKmode
5071 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5074 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5077 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5078 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5081 CUMULATIVE_ARGS local_cum
;
5082 int gp_saved
, fp_saved
;
5084 /* The caller has advanced CUM up to, but not beyond, the last named
5085 argument. Advance a local copy of CUM past the last "real" named
5086 argument, to find out how many registers are left over. */
5088 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, true);
5090 /* Found out how many registers we need to save. */
5091 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5092 fp_saved
= (EABI_FLOAT_VARARGS_P
5093 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5102 ptr
= plus_constant (virtual_incoming_args_rtx
,
5103 REG_PARM_STACK_SPACE (cfun
->decl
)
5104 - gp_saved
* UNITS_PER_WORD
);
5105 mem
= gen_frame_mem (BLKmode
, ptr
);
5106 set_mem_alias_set (mem
, get_varargs_alias_set ());
5108 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5113 /* We can't use move_block_from_reg, because it will use
5115 enum machine_mode mode
;
5118 /* Set OFF to the offset from virtual_incoming_args_rtx of
5119 the first float register. The FP save area lies below
5120 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5121 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5122 off
-= fp_saved
* UNITS_PER_FPREG
;
5124 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5126 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5127 i
+= MAX_FPRS_PER_FMT
)
5131 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
5132 mem
= gen_frame_mem (mode
, ptr
);
5133 set_mem_alias_set (mem
, get_varargs_alias_set ());
5134 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5135 off
+= UNITS_PER_HWFPVALUE
;
5139 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5140 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5141 + fp_saved
* UNITS_PER_FPREG
);
5144 /* Implement TARGET_BUILTIN_VA_LIST. */
5147 mips_build_builtin_va_list (void)
5149 if (EABI_FLOAT_VARARGS_P
)
5151 /* We keep 3 pointers, and two offsets.
5153 Two pointers are to the overflow area, which starts at the CFA.
5154 One of these is constant, for addressing into the GPR save area
5155 below it. The other is advanced up the stack through the
5158 The third pointer is to the bottom of the GPR save area.
5159 Since the FPR save area is just below it, we can address
5160 FPR slots off this pointer.
5162 We also keep two one-byte offsets, which are to be subtracted
5163 from the constant pointers to yield addresses in the GPR and
5164 FPR save areas. These are downcounted as float or non-float
5165 arguments are used, and when they get to zero, the argument
5166 must be obtained from the overflow region. */
5167 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5170 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5172 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
5174 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
5176 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
5178 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
5179 unsigned_char_type_node
);
5180 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
5181 unsigned_char_type_node
);
5182 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5183 warn on every user file. */
5184 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5185 array
= build_array_type (unsigned_char_type_node
,
5186 build_index_type (index
));
5187 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
5189 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5190 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5191 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5192 DECL_FIELD_CONTEXT (f_goff
) = record
;
5193 DECL_FIELD_CONTEXT (f_foff
) = record
;
5194 DECL_FIELD_CONTEXT (f_res
) = record
;
5196 TYPE_FIELDS (record
) = f_ovfl
;
5197 TREE_CHAIN (f_ovfl
) = f_gtop
;
5198 TREE_CHAIN (f_gtop
) = f_ftop
;
5199 TREE_CHAIN (f_ftop
) = f_goff
;
5200 TREE_CHAIN (f_goff
) = f_foff
;
5201 TREE_CHAIN (f_foff
) = f_res
;
5203 layout_type (record
);
5206 else if (TARGET_IRIX
&& TARGET_IRIX6
)
5207 /* On IRIX 6, this type is 'char *'. */
5208 return build_pointer_type (char_type_node
);
5210 /* Otherwise, we use 'void *'. */
5211 return ptr_type_node
;
5214 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5217 mips_va_start (tree valist
, rtx nextarg
)
5219 if (EABI_FLOAT_VARARGS_P
)
5221 const CUMULATIVE_ARGS
*cum
;
5222 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5223 tree ovfl
, gtop
, ftop
, goff
, foff
;
5225 int gpr_save_area_size
;
5226 int fpr_save_area_size
;
5229 cum
= &crtl
->args
.info
;
5231 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5233 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5235 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5236 f_gtop
= TREE_CHAIN (f_ovfl
);
5237 f_ftop
= TREE_CHAIN (f_gtop
);
5238 f_goff
= TREE_CHAIN (f_ftop
);
5239 f_foff
= TREE_CHAIN (f_goff
);
5241 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5243 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5245 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5247 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5249 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5252 /* Emit code to initialize OVFL, which points to the next varargs
5253 stack argument. CUM->STACK_WORDS gives the number of stack
5254 words used by named arguments. */
5255 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5256 if (cum
->stack_words
> 0)
5257 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
5258 size_int (cum
->stack_words
* UNITS_PER_WORD
));
5259 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5260 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5262 /* Emit code to initialize GTOP, the top of the GPR save area. */
5263 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5264 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5265 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5267 /* Emit code to initialize FTOP, the top of the FPR save area.
5268 This address is gpr_save_area_bytes below GTOP, rounded
5269 down to the next fp-aligned boundary. */
5270 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5271 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5272 fpr_offset
&= -UNITS_PER_FPVALUE
;
5274 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
5275 size_int (-fpr_offset
));
5276 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5277 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5279 /* Emit code to initialize GOFF, the offset from GTOP of the
5280 next GPR argument. */
5281 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5282 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5283 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5285 /* Likewise emit code to initialize FOFF, the offset from FTOP
5286 of the next FPR argument. */
5287 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5288 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5289 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5293 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
5294 std_expand_builtin_va_start (valist
, nextarg
);
5298 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5301 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5307 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5309 type
= build_pointer_type (type
);
5311 if (!EABI_FLOAT_VARARGS_P
)
5312 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5315 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5316 tree ovfl
, top
, off
, align
;
5317 HOST_WIDE_INT size
, rsize
, osize
;
5320 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5321 f_gtop
= TREE_CHAIN (f_ovfl
);
5322 f_ftop
= TREE_CHAIN (f_gtop
);
5323 f_goff
= TREE_CHAIN (f_ftop
);
5324 f_foff
= TREE_CHAIN (f_goff
);
5328 TOP be the top of the GPR or FPR save area;
5329 OFF be the offset from TOP of the next register;
5330 ADDR_RTX be the address of the argument;
5331 SIZE be the number of bytes in the argument type;
5332 RSIZE be the number of bytes used to store the argument
5333 when it's in the register save area; and
5334 OSIZE be the number of bytes used to store it when it's
5335 in the stack overflow area.
5337 The code we want is:
5339 1: off &= -rsize; // round down
5342 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5347 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5348 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5352 [1] and [9] can sometimes be optimized away. */
5354 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5356 size
= int_size_in_bytes (type
);
5358 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5359 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5361 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5362 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5363 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5364 unshare_expr (valist
), f_foff
, NULL_TREE
);
5366 /* When va_start saves FPR arguments to the stack, each slot
5367 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5368 argument's precision. */
5369 rsize
= UNITS_PER_HWFPVALUE
;
5371 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5372 (= PARM_BOUNDARY bits). This can be different from RSIZE
5375 (1) On 32-bit targets when TYPE is a structure such as:
5377 struct s { float f; };
5379 Such structures are passed in paired FPRs, so RSIZE
5380 will be 8 bytes. However, the structure only takes
5381 up 4 bytes of memory, so OSIZE will only be 4.
5383 (2) In combinations such as -mgp64 -msingle-float
5384 -fshort-double. Doubles passed in registers will then take
5385 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5386 stack take up UNITS_PER_WORD bytes. */
5387 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5391 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5392 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5393 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5394 unshare_expr (valist
), f_goff
, NULL_TREE
);
5395 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5396 if (rsize
> UNITS_PER_WORD
)
5398 /* [1] Emit code for: off &= -rsize. */
5399 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5400 build_int_cst (TREE_TYPE (off
), -rsize
));
5401 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5406 /* [2] Emit code to branch if off == 0. */
5407 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
5408 build_int_cst (TREE_TYPE (off
), 0));
5409 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5411 /* [5] Emit code for: off -= rsize. We do this as a form of
5412 post-decrement not available to C. */
5413 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5414 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5416 /* [4] Emit code for:
5417 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5418 t
= fold_convert (sizetype
, t
);
5419 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5420 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
5421 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5423 u
= size_int (rsize
- size
);
5424 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5426 COND_EXPR_THEN (addr
) = t
;
5428 if (osize
> UNITS_PER_WORD
)
5430 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5431 u
= size_int (osize
- 1);
5432 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
),
5433 unshare_expr (ovfl
), u
);
5434 t
= fold_convert (sizetype
, t
);
5435 u
= size_int (-osize
);
5436 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
5437 t
= fold_convert (TREE_TYPE (ovfl
), t
);
5438 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5439 unshare_expr (ovfl
), t
);
5444 /* [10, 11] Emit code for:
5445 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5447 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5448 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5449 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5451 u
= size_int (osize
- size
);
5452 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5455 /* String [9] and [10, 11] together. */
5457 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5458 COND_EXPR_ELSE (addr
) = t
;
5460 addr
= fold_convert (build_pointer_type (type
), addr
);
5461 addr
= build_va_arg_indirect_ref (addr
);
5465 addr
= build_va_arg_indirect_ref (addr
);
5470 /* Start a definition of function NAME. MIPS16_P indicates whether the
5471 function contains MIPS16 code. */
5474 mips_start_function_definition (const char *name
, bool mips16_p
)
5477 fprintf (asm_out_file
, "\t.set\tmips16\n");
5479 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5481 if (!flag_inhibit_size_directive
)
5483 fputs ("\t.ent\t", asm_out_file
);
5484 assemble_name (asm_out_file
, name
);
5485 fputs ("\n", asm_out_file
);
5488 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5490 /* Start the definition proper. */
5491 assemble_name (asm_out_file
, name
);
5492 fputs (":\n", asm_out_file
);
5495 /* End a function definition started by mips_start_function_definition. */
5498 mips_end_function_definition (const char *name
)
5500 if (!flag_inhibit_size_directive
)
5502 fputs ("\t.end\t", asm_out_file
);
5503 assemble_name (asm_out_file
, name
);
5504 fputs ("\n", asm_out_file
);
5508 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5511 mips_ok_for_lazy_binding_p (rtx x
)
5513 return (TARGET_USE_GOT
5514 && GET_CODE (x
) == SYMBOL_REF
5515 && !SYMBOL_REF_BIND_NOW_P (x
)
5516 && !mips_symbol_binds_local_p (x
));
5519 /* Load function address ADDR into register DEST. TYPE is as for
5520 mips_expand_call. Return true if we used an explicit lazy-binding
5524 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
5526 /* If we're generating PIC, and this call is to a global function,
5527 try to allow its address to be resolved lazily. This isn't
5528 possible for sibcalls when $gp is call-saved because the value
5529 of $gp on entry to the stub would be our caller's gp, not ours. */
5530 if (TARGET_EXPLICIT_RELOCS
5531 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
5532 && mips_ok_for_lazy_binding_p (addr
))
5534 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
5535 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
5540 mips_emit_move (dest
, addr
);
5545 /* Each locally-defined hard-float MIPS16 function has a local symbol
5546 associated with it. This hash table maps the function symbol (FUNC)
5547 to the local symbol (LOCAL). */
5548 struct mips16_local_alias
GTY(()) {
5552 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
5554 /* Hash table callbacks for mips16_local_aliases. */
5557 mips16_local_aliases_hash (const void *entry
)
5559 const struct mips16_local_alias
*alias
;
5561 alias
= (const struct mips16_local_alias
*) entry
;
5562 return htab_hash_string (XSTR (alias
->func
, 0));
5566 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
5568 const struct mips16_local_alias
*alias1
, *alias2
;
5570 alias1
= (const struct mips16_local_alias
*) entry1
;
5571 alias2
= (const struct mips16_local_alias
*) entry2
;
5572 return rtx_equal_p (alias1
->func
, alias2
->func
);
5575 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5576 Return a local alias for it, creating a new one if necessary. */
5579 mips16_local_alias (rtx func
)
5581 struct mips16_local_alias
*alias
, tmp_alias
;
5584 /* Create the hash table if this is the first call. */
5585 if (mips16_local_aliases
== NULL
)
5586 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
5587 mips16_local_aliases_eq
, NULL
);
5589 /* Look up the function symbol, creating a new entry if need be. */
5590 tmp_alias
.func
= func
;
5591 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
5592 gcc_assert (slot
!= NULL
);
5594 alias
= (struct mips16_local_alias
*) *slot
;
5597 const char *func_name
, *local_name
;
5600 /* Create a new SYMBOL_REF for the local symbol. The choice of
5601 __fn_local_* is based on the __fn_stub_* names that we've
5602 traditionally used for the non-MIPS16 stub. */
5603 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
5604 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
5605 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
5606 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
5608 /* Create a new structure to represent the mapping. */
5609 alias
= GGC_NEW (struct mips16_local_alias
);
5611 alias
->local
= local
;
5614 return alias
->local
;
5617 /* A chained list of functions for which mips16_build_call_stub has already
5618 generated a stub. NAME is the name of the function and FP_RET_P is true
5619 if the function returns a value in floating-point registers. */
5620 struct mips16_stub
{
5621 struct mips16_stub
*next
;
5625 static struct mips16_stub
*mips16_stubs
;
5627 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5630 mips16_stub_function (const char *name
)
5634 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5635 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
5639 /* Return the two-character string that identifies floating-point
5640 return mode MODE in the name of a MIPS16 function stub. */
5643 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5647 else if (mode
== DFmode
)
5649 else if (mode
== SCmode
)
5651 else if (mode
== DCmode
)
5653 else if (mode
== V2SFmode
)
5659 /* Write instructions to move a 32-bit value between general register
5660 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5661 from GPREG to FPREG and 'f' to move in the opposite direction. */
5664 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5666 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5667 reg_names
[gpreg
], reg_names
[fpreg
]);
5670 /* Likewise for 64-bit values. */
5673 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5676 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5677 reg_names
[gpreg
], reg_names
[fpreg
]);
5678 else if (TARGET_FLOAT64
)
5680 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5681 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5682 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5683 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5687 /* Move the least-significant word. */
5688 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5689 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5690 /* ...then the most significant word. */
5691 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5692 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5696 /* Write out code to move floating-point arguments into or out of
5697 general registers. FP_CODE is the code describing which arguments
5698 are present (see the comment above the definition of CUMULATIVE_ARGS
5699 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5702 mips_output_args_xfer (int fp_code
, char direction
)
5704 unsigned int gparg
, fparg
, f
;
5705 CUMULATIVE_ARGS cum
;
5707 /* This code only works for o32 and o64. */
5708 gcc_assert (TARGET_OLDABI
);
5710 mips_init_cumulative_args (&cum
, NULL
);
5712 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5714 enum machine_mode mode
;
5715 struct mips_arg_info info
;
5719 else if ((f
& 3) == 2)
5724 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5725 gparg
= mips_arg_regno (&info
, false);
5726 fparg
= mips_arg_regno (&info
, true);
5729 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5731 mips_output_64bit_xfer (direction
, gparg
, fparg
);
5733 mips_function_arg_advance (&cum
, mode
, NULL
, true);
5737 /* Write a MIPS16 stub for the current function. This stub is used
5738 for functions which take arguments in the floating-point registers.
5739 It is normal-mode code that moves the floating-point arguments
5740 into the general registers and then jumps to the MIPS16 code. */
5743 mips16_build_function_stub (void)
5745 const char *fnname
, *alias_name
, *separator
;
5746 char *secname
, *stubname
;
5751 /* Create the name of the stub, and its unique section. */
5752 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
5753 alias
= mips16_local_alias (symbol
);
5755 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
5756 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
5757 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
5758 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
5760 /* Build a decl for the stub. */
5761 stubdecl
= build_decl (FUNCTION_DECL
, get_identifier (stubname
),
5762 build_function_type (void_type_node
, NULL_TREE
));
5763 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5764 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
, void_type_node
);
5766 /* Output a comment. */
5767 fprintf (asm_out_file
, "\t# Stub function for %s (",
5768 current_function_name ());
5770 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
5772 fprintf (asm_out_file
, "%s%s", separator
,
5773 (f
& 3) == 1 ? "float" : "double");
5776 fprintf (asm_out_file
, ")\n");
5778 /* Start the function definition. */
5779 assemble_start_function (stubdecl
, stubname
);
5780 mips_start_function_definition (stubname
, false);
5782 /* If generating pic2 code, either set up the global pointer or
5784 if (TARGET_ABICALLS_PIC2
)
5786 if (TARGET_ABSOLUTE_ABICALLS
)
5787 fprintf (asm_out_file
, "\t.option\tpic0\n");
5790 output_asm_insn ("%(.cpload\t%^%)", NULL
);
5791 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5792 target function is. Use a local GOT access when loading the
5793 symbol, to cut down on the number of unnecessary GOT entries
5794 for stubs that aren't needed. */
5795 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
5800 /* Load the address of the MIPS16 function into $25. Do this first so
5801 that targets with coprocessor interlocks can use an MFC1 to fill the
5803 output_asm_insn ("la\t%^,%0", &symbol
);
5805 /* Move the arguments from floating-point registers to general registers. */
5806 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
5808 /* Jump to the MIPS16 function. */
5809 output_asm_insn ("jr\t%^", NULL
);
5811 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
5812 fprintf (asm_out_file
, "\t.option\tpic2\n");
5814 mips_end_function_definition (stubname
);
5816 /* If the linker needs to create a dynamic symbol for the target
5817 function, it will associate the symbol with the stub (which,
5818 unlike the target function, follows the proper calling conventions).
5819 It is therefore useful to have a local alias for the target function,
5820 so that it can still be identified as MIPS16 code. As an optimization,
5821 this symbol can also be used for indirect MIPS16 references from
5822 within this file. */
5823 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
5825 switch_to_section (function_section (current_function_decl
));
5828 /* The current function is a MIPS16 function that returns a value in an FPR.
5829 Copy the return value from its soft-float to its hard-float location.
5830 libgcc2 has special non-MIPS16 helper functions for each case. */
5833 mips16_copy_fpr_return_value (void)
5835 rtx fn
, insn
, retval
;
5837 enum machine_mode return_mode
;
5840 return_type
= DECL_RESULT (current_function_decl
);
5841 return_mode
= DECL_MODE (return_type
);
5843 name
= ACONCAT (("__mips16_ret_",
5844 mips16_call_stub_mode_suffix (return_mode
),
5846 fn
= mips16_stub_function (name
);
5848 /* The function takes arguments in $2 (and possibly $3), so calls
5849 to it cannot be lazily bound. */
5850 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
5852 /* Model the call as something that takes the GPR return value as
5853 argument and returns an "updated" value. */
5854 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
5855 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
5856 const0_rtx
, NULL_RTX
, false);
5857 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
5860 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5861 RETVAL is the location of the return value, or null if this is
5862 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5863 arguments and FP_CODE is the code built by mips_function_arg;
5864 see the comment above CUMULATIVE_ARGS for details.
5866 There are three alternatives:
5868 - If a stub was needed, emit the call and return the call insn itself.
5870 - If we can avoid using a stub by redirecting the call, set *FN_PTR
5871 to the new target and return null.
5873 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
5876 A stub is needed for calls to functions that, in normal mode,
5877 receive arguments in FPRs or return values in FPRs. The stub
5878 copies the arguments from their soft-float positions to their
5879 hard-float positions, calls the real function, then copies the
5880 return value from its hard-float position to its soft-float
5883 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
5884 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
5885 automatically redirects the JAL to the stub, otherwise the JAL
5886 continues to call FN directly. */
5889 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
5893 struct mips16_stub
*l
;
5896 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5897 we were invoked with the -msoft-float option. */
5898 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
5901 /* Figure out whether the value might come back in a floating-point
5903 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
5905 /* We don't need to do anything if there were no floating-point
5906 arguments and the value will not be returned in a floating-point
5908 if (fp_code
== 0 && !fp_ret_p
)
5911 /* We don't need to do anything if this is a call to a special
5912 MIPS16 support function. */
5914 if (mips16_stub_function_p (fn
))
5917 /* This code will only work for o32 and o64 abis. The other ABI's
5918 require more sophisticated support. */
5919 gcc_assert (TARGET_OLDABI
);
5921 /* If we're calling via a function pointer, use one of the magic
5922 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5923 Each stub expects the function address to arrive in register $2. */
5924 if (GET_CODE (fn
) != SYMBOL_REF
5925 || !call_insn_operand (fn
, VOIDmode
))
5928 rtx stub_fn
, insn
, addr
;
5931 /* If this is a locally-defined and locally-binding function,
5932 avoid the stub by calling the local alias directly. */
5933 if (mips16_local_function_p (fn
))
5935 *fn_ptr
= mips16_local_alias (fn
);
5939 /* Create a SYMBOL_REF for the libgcc.a function. */
5941 sprintf (buf
, "__mips16_call_stub_%s_%d",
5942 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
5945 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
5946 stub_fn
= mips16_stub_function (buf
);
5948 /* The function uses $2 as an argument, so calls to it
5949 cannot be lazily bound. */
5950 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
5952 /* Load the target function into $2. */
5953 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
5954 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
5956 /* Emit the call. */
5957 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
5958 args_size
, NULL_RTX
, lazy_p
);
5960 /* Tell GCC that this call does indeed use the value of $2. */
5961 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
5963 /* If we are handling a floating-point return value, we need to
5964 save $18 in the function prologue. Putting a note on the
5965 call will mean that df_regs_ever_live_p ($18) will be true if the
5966 call is not eliminated, and we can check that in the prologue
5969 CALL_INSN_FUNCTION_USAGE (insn
) =
5970 gen_rtx_EXPR_LIST (VOIDmode
,
5971 gen_rtx_CLOBBER (VOIDmode
,
5972 gen_rtx_REG (word_mode
, 18)),
5973 CALL_INSN_FUNCTION_USAGE (insn
));
5978 /* We know the function we are going to call. If we have already
5979 built a stub, we don't need to do anything further. */
5980 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
5981 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
5982 if (strcmp (l
->name
, fnname
) == 0)
5987 const char *separator
;
5988 char *secname
, *stubname
;
5989 tree stubid
, stubdecl
;
5992 /* If the function does not return in FPRs, the special stub
5996 If the function does return in FPRs, the stub section is named
5997 .mips16.call.fp.FNNAME
5999 Build a decl for the stub. */
6000 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6002 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6004 stubid
= get_identifier (stubname
);
6005 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
6006 build_function_type (void_type_node
, NULL_TREE
));
6007 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6008 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
,
6011 /* Output a comment. */
6012 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6014 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6018 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6020 fprintf (asm_out_file
, "%s%s", separator
,
6021 (f
& 3) == 1 ? "float" : "double");
6024 fprintf (asm_out_file
, ")\n");
6026 /* Start the function definition. */
6027 assemble_start_function (stubdecl
, stubname
);
6028 mips_start_function_definition (stubname
, false);
6032 /* Load the address of the MIPS16 function into $25. Do this
6033 first so that targets with coprocessor interlocks can use
6034 an MFC1 to fill the delay slot. */
6035 if (TARGET_EXPLICIT_RELOCS
)
6037 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6038 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6041 output_asm_insn ("la\t%^,%0", &fn
);
6044 /* Move the arguments from general registers to floating-point
6046 mips_output_args_xfer (fp_code
, 't');
6050 /* Jump to the previously-loaded address. */
6051 output_asm_insn ("jr\t%^", NULL
);
6055 /* Save the return address in $18 and call the non-MIPS16 function.
6056 The stub's caller knows that $18 might be clobbered, even though
6057 $18 is usually a call-saved register. */
6058 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6059 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
6060 output_asm_insn (MIPS_CALL ("jal", &fn
, 0), &fn
);
6062 /* Move the result from floating-point registers to
6063 general registers. */
6064 switch (GET_MODE (retval
))
6067 mips_output_32bit_xfer ('f', GP_RETURN
+ 1,
6068 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6071 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6072 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6074 /* On 64-bit targets, complex floats are returned in
6075 a single GPR, such that "sd" on a suitably-aligned
6076 target would store the value correctly. */
6077 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6078 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6079 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6080 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6081 reg_names
[GP_RETURN
],
6082 reg_names
[GP_RETURN
],
6083 reg_names
[GP_RETURN
+ 1]);
6088 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6089 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6093 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6099 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6102 #ifdef ASM_DECLARE_FUNCTION_SIZE
6103 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6106 mips_end_function_definition (stubname
);
6108 /* Record this stub. */
6109 l
= XNEW (struct mips16_stub
);
6110 l
->name
= xstrdup (fnname
);
6111 l
->fp_ret_p
= fp_ret_p
;
6112 l
->next
= mips16_stubs
;
6116 /* If we expect a floating-point return value, but we've built a
6117 stub which does not expect one, then we're in trouble. We can't
6118 use the existing stub, because it won't handle the floating-point
6119 value. We can't build a new stub, because the linker won't know
6120 which stub to use for the various calls in this object file.
6121 Fortunately, this case is illegal, since it means that a function
6122 was declared in two different ways in a single compilation. */
6123 if (fp_ret_p
&& !l
->fp_ret_p
)
6124 error ("cannot handle inconsistent calls to %qs", fnname
);
6126 if (retval
== NULL_RTX
)
6127 insn
= gen_call_internal_direct (fn
, args_size
);
6129 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6130 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6132 /* If we are calling a stub which handles a floating-point return
6133 value, we need to arrange to save $18 in the prologue. We do this
6134 by marking the function call as using the register. The prologue
6135 will later see that it is used, and emit code to save it. */
6137 CALL_INSN_FUNCTION_USAGE (insn
) =
6138 gen_rtx_EXPR_LIST (VOIDmode
,
6139 gen_rtx_CLOBBER (VOIDmode
,
6140 gen_rtx_REG (word_mode
, 18)),
6141 CALL_INSN_FUNCTION_USAGE (insn
));
6146 /* Expand a call of type TYPE. RESULT is where the result will go (null
6147 for "call"s and "sibcall"s), ADDR is the address of the function,
6148 ARGS_SIZE is the size of the arguments and AUX is the value passed
6149 to us by mips_function_arg. LAZY_P is true if this call already
6150 involves a lazily-bound function address (such as when calling
6151 functions through a MIPS16 hard-float stub).
6153 Return the call itself. */
6156 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6157 rtx args_size
, rtx aux
, bool lazy_p
)
6159 rtx orig_addr
, pattern
, insn
;
6162 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6163 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6166 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6171 if (!call_insn_operand (addr
, VOIDmode
))
6173 if (type
== MIPS_CALL_EPILOGUE
)
6174 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6176 addr
= gen_reg_rtx (Pmode
);
6177 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6182 rtx (*fn
) (rtx
, rtx
);
6184 if (type
== MIPS_CALL_EPILOGUE
&& TARGET_SPLIT_CALLS
)
6185 fn
= gen_call_split
;
6186 else if (type
== MIPS_CALL_SIBCALL
)
6187 fn
= gen_sibcall_internal
;
6189 fn
= gen_call_internal
;
6191 pattern
= fn (addr
, args_size
);
6193 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6195 /* Handle return values created by mips_return_fpr_pair. */
6196 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6199 if (type
== MIPS_CALL_EPILOGUE
&& TARGET_SPLIT_CALLS
)
6200 fn
= gen_call_value_multiple_split
;
6201 else if (type
== MIPS_CALL_SIBCALL
)
6202 fn
= gen_sibcall_value_multiple_internal
;
6204 fn
= gen_call_value_multiple_internal
;
6206 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6207 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6208 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6212 rtx (*fn
) (rtx
, rtx
, rtx
);
6214 if (type
== MIPS_CALL_EPILOGUE
&& TARGET_SPLIT_CALLS
)
6215 fn
= gen_call_value_split
;
6216 else if (type
== MIPS_CALL_SIBCALL
)
6217 fn
= gen_sibcall_value_internal
;
6219 fn
= gen_call_value_internal
;
6221 /* Handle return values created by mips_return_fpr_single. */
6222 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6223 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6224 pattern
= fn (result
, addr
, args_size
);
6227 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6230 /* Split call instruction INSN into a $gp-clobbering call and
6231 (where necessary) an instruction to restore $gp from its save slot.
6232 CALL_PATTERN is the pattern of the new call. */
6235 mips_split_call (rtx insn
, rtx call_pattern
)
6239 new_insn
= emit_call_insn (call_pattern
);
6240 CALL_INSN_FUNCTION_USAGE (new_insn
)
6241 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn
));
6242 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6243 /* Pick a temporary register that is suitable for both MIPS16 and
6244 non-MIPS16 code. $4 and $5 are used for returning complex double
6245 values in soft-float code, so $6 is the first suitable candidate. */
6246 mips_restore_gp (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6249 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6252 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6254 if (!TARGET_SIBCALLS
)
6257 /* Interrupt handlers need special epilogue code and therefore can't
6259 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6262 /* We can't do a sibcall if the called function is a MIPS16 function
6263 because there is no direct "jx" instruction equivalent to "jalx" to
6264 switch the ISA mode. We only care about cases where the sibling
6265 and normal calls would both be direct. */
6267 && mips_use_mips16_mode_p (decl
)
6268 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6271 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6272 functions could be MIPS16 ones unless an attribute explicitly tells
6274 if (TARGET_INTERLINK_MIPS16
6276 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6277 && !mips_nomips16_decl_p (decl
)
6278 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6285 /* Emit code to move general operand SRC into condition-code
6286 register DEST given that SCRATCH is a scratch TFmode FPR.
6293 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6296 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6300 /* Change the source to SFmode. */
6302 src
= adjust_address (src
, SFmode
, 0);
6303 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6304 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6306 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6307 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6309 mips_emit_move (copy_rtx (fp1
), src
);
6310 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6311 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6314 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6315 Assume that the areas do not overlap. */
6318 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6320 HOST_WIDE_INT offset
, delta
;
6321 unsigned HOST_WIDE_INT bits
;
6323 enum machine_mode mode
;
6326 /* Work out how many bits to move at a time. If both operands have
6327 half-word alignment, it is usually better to move in half words.
6328 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6329 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6330 Otherwise move word-sized chunks. */
6331 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6332 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6333 bits
= BITS_PER_WORD
/ 2;
6335 bits
= BITS_PER_WORD
;
6337 mode
= mode_for_size (bits
, MODE_INT
, 0);
6338 delta
= bits
/ BITS_PER_UNIT
;
6340 /* Allocate a buffer for the temporary registers. */
6341 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6343 /* Load as many BITS-sized chunks as possible. Use a normal load if
6344 the source has enough alignment, otherwise use left/right pairs. */
6345 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6347 regs
[i
] = gen_reg_rtx (mode
);
6348 if (MEM_ALIGN (src
) >= bits
)
6349 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6352 rtx part
= adjust_address (src
, BLKmode
, offset
);
6353 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
6358 /* Copy the chunks to the destination. */
6359 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6360 if (MEM_ALIGN (dest
) >= bits
)
6361 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6364 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6365 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6369 /* Mop up any left-over bytes. */
6370 if (offset
< length
)
6372 src
= adjust_address (src
, BLKmode
, offset
);
6373 dest
= adjust_address (dest
, BLKmode
, offset
);
6374 move_by_pieces (dest
, src
, length
- offset
,
6375 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6379 /* Helper function for doing a loop-based block operation on memory
6380 reference MEM. Each iteration of the loop will operate on LENGTH
6383 Create a new base register for use within the loop and point it to
6384 the start of MEM. Create a new memory reference that uses this
6385 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6388 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6389 rtx
*loop_reg
, rtx
*loop_mem
)
6391 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6393 /* Although the new mem does not refer to a known location,
6394 it does keep up to LENGTH bytes of alignment. */
6395 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6396 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6399 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6400 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6401 the memory regions do not overlap. */
6404 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6405 HOST_WIDE_INT bytes_per_iter
)
6407 rtx label
, src_reg
, dest_reg
, final_src
;
6408 HOST_WIDE_INT leftover
;
6410 leftover
= length
% bytes_per_iter
;
6413 /* Create registers and memory references for use within the loop. */
6414 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6415 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6417 /* Calculate the value that SRC_REG should have after the last iteration
6419 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
6422 /* Emit the start of the loop. */
6423 label
= gen_label_rtx ();
6426 /* Emit the loop body. */
6427 mips_block_move_straight (dest
, src
, bytes_per_iter
);
6429 /* Move on to the next block. */
6430 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
6431 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
6433 /* Emit the loop condition. */
6434 if (Pmode
== DImode
)
6435 emit_insn (gen_cmpdi (src_reg
, final_src
));
6437 emit_insn (gen_cmpsi (src_reg
, final_src
));
6438 emit_jump_insn (gen_bne (label
));
6440 /* Mop up any left-over bytes. */
6442 mips_block_move_straight (dest
, src
, leftover
);
6445 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6446 memory reference SRC to memory reference DEST. */
6449 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
6451 if (GET_CODE (length
) == CONST_INT
)
6453 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
6455 mips_block_move_straight (dest
, src
, INTVAL (length
));
6460 mips_block_move_loop (dest
, src
, INTVAL (length
),
6461 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
6468 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6471 mips_expand_synci_loop (rtx begin
, rtx end
)
6473 rtx inc
, label
, cmp
, cmp_result
;
6475 /* Load INC with the cache line size (rdhwr INC,$1). */
6476 inc
= gen_reg_rtx (Pmode
);
6477 emit_insn (Pmode
== SImode
6478 ? gen_rdhwr_synci_step_si (inc
)
6479 : gen_rdhwr_synci_step_di (inc
));
6481 /* Loop back to here. */
6482 label
= gen_label_rtx ();
6485 emit_insn (gen_synci (begin
));
6487 cmp
= mips_force_binary (Pmode
, GTU
, begin
, end
);
6489 mips_emit_binary (PLUS
, begin
, begin
, inc
);
6491 cmp_result
= gen_rtx_EQ (VOIDmode
, cmp
, const0_rtx
);
6492 emit_jump_insn (gen_condjump (cmp_result
, label
));
6495 /* Expand a QI or HI mode atomic memory operation.
6497 GENERATOR contains a pointer to the gen_* function that generates
6498 the SI mode underlying atomic operation using masks that we
6501 RESULT is the return register for the operation. Its value is NULL
6504 MEM is the location of the atomic access.
6506 OLDVAL is the first operand for the operation.
6508 NEWVAL is the optional second operand for the operation. Its value
6509 is NULL if unused. */
6512 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
6513 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
6515 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
6516 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
6518 enum machine_mode mode
;
6520 mode
= GET_MODE (mem
);
6522 /* Compute the address of the containing SImode value. */
6523 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
6524 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
6525 force_reg (Pmode
, GEN_INT (-4)));
6527 /* Create a memory reference for it. */
6528 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
6529 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
6530 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
6532 /* Work out the byte offset of the QImode or HImode value,
6533 counting from the least significant byte. */
6534 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
6535 if (TARGET_BIG_ENDIAN
)
6536 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
6538 /* Multiply by eight to convert the shift value from bytes to bits. */
6539 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
6541 /* Make the final shift an SImode value, so that it can be used in
6542 SImode operations. */
6543 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
6545 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6546 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
6547 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
6548 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
6550 /* Compute the equivalent exclusive mask. */
6551 inverted_mask
= gen_reg_rtx (SImode
);
6552 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
6553 gen_rtx_NOT (SImode
, mask
)));
6555 /* Shift the old value into place. */
6556 if (oldval
!= const0_rtx
)
6558 oldval
= convert_modes (SImode
, mode
, oldval
, true);
6559 oldval
= force_reg (SImode
, oldval
);
6560 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
6563 /* Do the same for the new value. */
6564 if (newval
&& newval
!= const0_rtx
)
6566 newval
= convert_modes (SImode
, mode
, newval
, true);
6567 newval
= force_reg (SImode
, newval
);
6568 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
6571 /* Do the SImode atomic access. */
6573 res
= gen_reg_rtx (SImode
);
6575 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
6577 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
6579 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
6585 /* Shift and convert the result. */
6586 mips_emit_binary (AND
, res
, res
, mask
);
6587 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
6588 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
6592 /* Return true if it is possible to use left/right accesses for a
6593 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6594 returning true, update *OP, *LEFT and *RIGHT as follows:
6596 *OP is a BLKmode reference to the whole field.
6598 *LEFT is a QImode reference to the first byte if big endian or
6599 the last byte if little endian. This address can be used in the
6600 left-side instructions (LWL, SWL, LDL, SDL).
6602 *RIGHT is a QImode reference to the opposite end of the field and
6603 can be used in the patterning right-side instruction. */
6606 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
6607 rtx
*left
, rtx
*right
)
6611 /* Check that the operand really is a MEM. Not all the extv and
6612 extzv predicates are checked. */
6616 /* Check that the size is valid. */
6617 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
6620 /* We can only access byte-aligned values. Since we are always passed
6621 a reference to the first byte of the field, it is not necessary to
6622 do anything with BITPOS after this check. */
6623 if (bitpos
% BITS_PER_UNIT
!= 0)
6626 /* Reject aligned bitfields: we want to use a normal load or store
6627 instead of a left/right pair. */
6628 if (MEM_ALIGN (*op
) >= width
)
6631 /* Adjust *OP to refer to the whole field. This also has the effect
6632 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6633 *op
= adjust_address (*op
, BLKmode
, 0);
6634 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
6636 /* Get references to both ends of the field. We deliberately don't
6637 use the original QImode *OP for FIRST since the new BLKmode one
6638 might have a simpler address. */
6639 first
= adjust_address (*op
, QImode
, 0);
6640 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
6642 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6643 correspond to the MSB and RIGHT to the LSB. */
6644 if (TARGET_BIG_ENDIAN
)
6645 *left
= first
, *right
= last
;
6647 *left
= last
, *right
= first
;
6652 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6653 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6654 the operation is the equivalent of:
6656 (set DEST (*_extract SRC WIDTH BITPOS))
6658 Return true on success. */
6661 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6662 HOST_WIDE_INT bitpos
)
6664 rtx left
, right
, temp
;
6666 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6667 be a paradoxical word_mode subreg. This is the only case in which
6668 we allow the destination to be larger than the source. */
6669 if (GET_CODE (dest
) == SUBREG
6670 && GET_MODE (dest
) == DImode
6671 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
6672 dest
= SUBREG_REG (dest
);
6674 /* After the above adjustment, the destination must be the same
6675 width as the source. */
6676 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
6679 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
6682 temp
= gen_reg_rtx (GET_MODE (dest
));
6683 if (GET_MODE (dest
) == DImode
)
6685 emit_insn (gen_mov_ldl (temp
, src
, left
));
6686 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
6690 emit_insn (gen_mov_lwl (temp
, src
, left
));
6691 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
6696 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6697 BITPOS and SRC are the operands passed to the expander; the operation
6698 is the equivalent of:
6700 (set (zero_extract DEST WIDTH BITPOS) SRC)
6702 Return true on success. */
6705 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6706 HOST_WIDE_INT bitpos
)
6709 enum machine_mode mode
;
6711 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
6714 mode
= mode_for_size (width
, MODE_INT
, 0);
6715 src
= gen_lowpart (mode
, src
);
6718 emit_insn (gen_mov_sdl (dest
, src
, left
));
6719 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
6723 emit_insn (gen_mov_swl (dest
, src
, left
));
6724 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
6729 /* Return true if X is a MEM with the same size as MODE. */
6732 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
6739 size
= MEM_SIZE (x
);
6740 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
6743 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6744 source of an "ext" instruction or the destination of an "ins"
6745 instruction. OP must be a register operand and the following
6746 conditions must hold:
6748 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6749 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6750 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6752 Also reject lengths equal to a word as they are better handled
6753 by the move patterns. */
6756 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
6758 if (!ISA_HAS_EXT_INS
6759 || !register_operand (op
, VOIDmode
)
6760 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
6763 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
6766 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
6772 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6773 operation if MAXLEN is the maxium length of consecutive bits that
6774 can make up MASK. MODE is the mode of the operation. See
6775 mask_low_and_shift_len for the actual definition. */
6778 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
6780 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
6783 /* The canonical form of a mask-low-and-shift-left operation is
6784 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6785 cleared. Thus we need to shift MASK to the right before checking if it
6786 is a valid mask value. MODE is the mode of the operation. If true
6787 return the length of the mask, otherwise return -1. */
6790 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
6792 HOST_WIDE_INT shval
;
6794 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
6795 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
6798 /* Return true if -msplit-addresses is selected and should be honored.
6800 -msplit-addresses is a half-way house between explicit relocations
6801 and the traditional assembler macros. It can split absolute 32-bit
6802 symbolic constants into a high/lo_sum pair but uses macros for other
6805 Like explicit relocation support for REL targets, it relies
6806 on GNU extensions in the assembler and the linker.
6808 Although this code should work for -O0, it has traditionally
6809 been treated as an optimization. */
6812 mips_split_addresses_p (void)
6814 return (TARGET_SPLIT_ADDRESSES
6818 && !ABI_HAS_64BIT_SYMBOLS
);
6821 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6824 mips_init_relocs (void)
6826 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
6827 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
6828 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
6829 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
6831 if (ABI_HAS_64BIT_SYMBOLS
)
6833 if (TARGET_EXPLICIT_RELOCS
)
6835 mips_split_p
[SYMBOL_64_HIGH
] = true;
6836 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
6837 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
6839 mips_split_p
[SYMBOL_64_MID
] = true;
6840 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
6841 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
6843 mips_split_p
[SYMBOL_64_LOW
] = true;
6844 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
6845 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
6847 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6848 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6853 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
6855 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6856 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
6857 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6859 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
6865 /* The high part is provided by a pseudo copy of $gp. */
6866 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
6867 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
6869 else if (TARGET_EXPLICIT_RELOCS
)
6870 /* Small data constants are kept whole until after reload,
6871 then lowered by mips_rewrite_small_data. */
6872 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
6874 if (TARGET_EXPLICIT_RELOCS
)
6876 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
6879 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
6880 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
6884 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
6885 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
6888 /* Expose the use of $28 as soon as possible. */
6889 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
6893 /* The HIGH and LO_SUM are matched by special .md patterns. */
6894 mips_split_p
[SYMBOL_GOT_DISP
] = true;
6896 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
6897 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
6898 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
6900 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
6901 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
6902 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
6907 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
6909 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
6910 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
6912 /* Expose the use of $28 as soon as possible. */
6913 mips_split_p
[SYMBOL_GOT_DISP
] = true;
6919 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
6920 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
6921 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
6924 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
6925 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
6927 mips_split_p
[SYMBOL_DTPREL
] = true;
6928 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
6929 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
6931 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
6933 mips_split_p
[SYMBOL_TPREL
] = true;
6934 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
6935 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
6937 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
6940 /* If OP is an UNSPEC address, return the address to which it refers,
6941 otherwise return OP itself. */
6944 mips_strip_unspec_address (rtx op
)
6948 split_const (op
, &base
, &offset
);
6949 if (UNSPEC_ADDRESS_P (base
))
6950 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
6954 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6955 in context CONTEXT. RELOCS is the array of relocations to use. */
6958 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
6959 const char **relocs
)
6961 enum mips_symbol_type symbol_type
;
6964 symbol_type
= mips_classify_symbolic_expression (op
, context
);
6965 gcc_assert (relocs
[symbol_type
]);
6967 fputs (relocs
[symbol_type
], file
);
6968 output_addr_const (file
, mips_strip_unspec_address (op
));
6969 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
6974 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6975 The punctuation characters are:
6977 '(' Start a nested ".set noreorder" block.
6978 ')' End a nested ".set noreorder" block.
6979 '[' Start a nested ".set noat" block.
6980 ']' End a nested ".set noat" block.
6981 '<' Start a nested ".set nomacro" block.
6982 '>' End a nested ".set nomacro" block.
6983 '*' Behave like %(%< if generating a delayed-branch sequence.
6984 '#' Print a nop if in a ".set noreorder" block.
6985 '/' Like '#', but do nothing within a delayed-branch sequence.
6986 '?' Print "l" if mips_branch_likely is true
6987 '~' Print a nop if mips_branch_likely is true
6988 '.' Print the name of the register with a hard-wired zero (zero or $0).
6989 '@' Print the name of the assembler temporary register (at or $1).
6990 '^' Print the name of the pic call-through register (t9 or $25).
6991 '+' Print the name of the gp register (usually gp or $28).
6992 '$' Print the name of the stack pointer register (sp or $29).
6993 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6994 '-' Print ".set pop" under the same conditions for '|'.
6996 See also mips_init_print_operand_pucnt. */
6999 mips_print_operand_punctuation (FILE *file
, int ch
)
7004 if (set_noreorder
++ == 0)
7005 fputs (".set\tnoreorder\n\t", file
);
7009 gcc_assert (set_noreorder
> 0);
7010 if (--set_noreorder
== 0)
7011 fputs ("\n\t.set\treorder", file
);
7015 if (set_noat
++ == 0)
7016 fputs (".set\tnoat\n\t", file
);
7020 gcc_assert (set_noat
> 0);
7021 if (--set_noat
== 0)
7022 fputs ("\n\t.set\tat", file
);
7026 if (set_nomacro
++ == 0)
7027 fputs (".set\tnomacro\n\t", file
);
7031 gcc_assert (set_nomacro
> 0);
7032 if (--set_nomacro
== 0)
7033 fputs ("\n\t.set\tmacro", file
);
7037 if (final_sequence
!= 0)
7039 mips_print_operand_punctuation (file
, '(');
7040 mips_print_operand_punctuation (file
, '<');
7045 if (set_noreorder
!= 0)
7046 fputs ("\n\tnop", file
);
7050 /* Print an extra newline so that the delayed insn is separated
7051 from the following ones. This looks neater and is consistent
7052 with non-nop delayed sequences. */
7053 if (set_noreorder
!= 0 && final_sequence
== 0)
7054 fputs ("\n\tnop\n", file
);
7058 if (mips_branch_likely
)
7063 if (mips_branch_likely
)
7064 fputs ("\n\tnop", file
);
7068 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7072 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
7076 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7080 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7084 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7089 fputs (".set\tpush\n\t.set\tmips2\n\t", file
);
7094 fputs ("\n\t.set\tpop", file
);
7103 /* Initialize mips_print_operand_punct. */
7106 mips_init_print_operand_punct (void)
7110 for (p
= "()[]<>*#/?~.@^+$|-"; *p
; p
++)
7111 mips_print_operand_punct
[(unsigned char) *p
] = true;
7114 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7115 associated with condition CODE. Print the condition part of the
7119 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7133 /* Conveniently, the MIPS names for these conditions are the same
7134 as their RTL equivalents. */
7135 fputs (GET_RTX_NAME (code
), file
);
7139 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7144 /* Likewise floating-point branches. */
7147 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7152 fputs ("c1f", file
);
7156 fputs ("c1t", file
);
7160 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7165 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7167 'X' Print CONST_INT OP in hexadecimal format.
7168 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7169 'd' Print CONST_INT OP in decimal.
7170 'm' Print one less than CONST_INT OP in decimal.
7171 'h' Print the high-part relocation associated with OP, after stripping
7173 'R' Print the low-part relocation associated with OP.
7174 'C' Print the integer branch condition for comparison OP.
7175 'N' Print the inverse of the integer branch condition for comparison OP.
7176 'F' Print the FPU branch condition for comparison OP.
7177 'W' Print the inverse of the FPU branch condition for comparison OP.
7178 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7179 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7180 't' Like 'T', but with the EQ/NE cases reversed
7181 'Y' Print mips_fp_conditions[INTVAL (OP)]
7182 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7183 'q' Print a DSP accumulator register.
7184 'D' Print the second part of a double-word register or memory operand.
7185 'L' Print the low-order register in a double-word register operand.
7186 'M' Print high-order register in a double-word register operand.
7187 'z' Print $0 if OP is zero, otherwise print OP normally. */
7190 mips_print_operand (FILE *file
, rtx op
, int letter
)
7194 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
7196 mips_print_operand_punctuation (file
, letter
);
7201 code
= GET_CODE (op
);
7206 if (GET_CODE (op
) == CONST_INT
)
7207 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7209 output_operand_lossage ("invalid use of '%%%c'", letter
);
7213 if (GET_CODE (op
) == CONST_INT
)
7214 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7216 output_operand_lossage ("invalid use of '%%%c'", letter
);
7220 if (GET_CODE (op
) == CONST_INT
)
7221 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7223 output_operand_lossage ("invalid use of '%%%c'", letter
);
7227 if (GET_CODE (op
) == CONST_INT
)
7228 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7230 output_operand_lossage ("invalid use of '%%%c'", letter
);
7236 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7240 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7244 mips_print_int_branch_condition (file
, code
, letter
);
7248 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7252 mips_print_float_branch_condition (file
, code
, letter
);
7256 mips_print_float_branch_condition (file
, reverse_condition (code
),
7263 int truth
= (code
== NE
) == (letter
== 'T');
7264 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7269 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7270 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7272 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7279 mips_print_operand (file
, op
, 0);
7285 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7286 fprintf (file
, "$ac0");
7287 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7288 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7290 output_operand_lossage ("invalid use of '%%%c'", letter
);
7298 unsigned int regno
= REGNO (op
);
7299 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7300 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7303 /* We need to print $0 .. $31 for COP0 registers. */
7304 if (COP0_REG_P (regno
))
7305 fprintf (file
, "$%s", ®_names
[regno
][4]);
7307 fprintf (file
, "%s", reg_names
[regno
]);
7313 output_address (plus_constant (XEXP (op
, 0), 4));
7315 output_address (XEXP (op
, 0));
7319 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7320 fputs (reg_names
[GP_REG_FIRST
], file
);
7321 else if (CONST_GP_P (op
))
7322 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7324 output_addr_const (file
, mips_strip_unspec_address (op
));
7330 /* Output address operand X to FILE. */
7333 mips_print_operand_address (FILE *file
, rtx x
)
7335 struct mips_address_info addr
;
7337 if (mips_classify_address (&addr
, x
, word_mode
, true))
7341 mips_print_operand (file
, addr
.offset
, 0);
7342 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7345 case ADDRESS_LO_SUM
:
7346 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
7348 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7351 case ADDRESS_CONST_INT
:
7352 output_addr_const (file
, x
);
7353 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
7356 case ADDRESS_SYMBOLIC
:
7357 output_addr_const (file
, mips_strip_unspec_address (x
));
7363 /* Implement TARGET_ENCODE_SECTION_INFO. */
7366 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
7368 default_encode_section_info (decl
, rtl
, first
);
7370 if (TREE_CODE (decl
) == FUNCTION_DECL
)
7372 rtx symbol
= XEXP (rtl
, 0);
7373 tree type
= TREE_TYPE (decl
);
7375 /* Encode whether the symbol is short or long. */
7376 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
7377 || mips_far_type_p (type
))
7378 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
7382 /* Implement TARGET_SELECT_RTX_SECTION. */
7385 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7386 unsigned HOST_WIDE_INT align
)
7388 /* ??? Consider using mergeable small data sections. */
7389 if (mips_rtx_constant_in_small_data_p (mode
))
7390 return get_named_section (NULL
, ".sdata", 0);
7392 return default_elf_select_rtx_section (mode
, x
, align
);
7395 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7397 The complication here is that, with the combination TARGET_ABICALLS
7398 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7399 absolute addresses, and should therefore not be included in the
7400 read-only part of a DSO. Handle such cases by selecting a normal
7401 data section instead of a read-only one. The logic apes that in
7402 default_function_rodata_section. */
7405 mips_function_rodata_section (tree decl
)
7407 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
7408 return default_function_rodata_section (decl
);
7410 if (decl
&& DECL_SECTION_NAME (decl
))
7412 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7413 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7415 char *rname
= ASTRDUP (name
);
7417 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7419 else if (flag_function_sections
7420 && flag_data_sections
7421 && strncmp (name
, ".text.", 6) == 0)
7423 char *rname
= ASTRDUP (name
);
7424 memcpy (rname
+ 1, "data", 4);
7425 return get_section (rname
, SECTION_WRITE
, decl
);
7428 return data_section
;
7431 /* Implement TARGET_IN_SMALL_DATA_P. */
7434 mips_in_small_data_p (const_tree decl
)
7436 unsigned HOST_WIDE_INT size
;
7438 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7441 /* We don't yet generate small-data references for -mabicalls
7442 or VxWorks RTP code. See the related -G handling in
7443 mips_override_options. */
7444 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
7447 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7451 /* Reject anything that isn't in a known small-data section. */
7452 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7453 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7456 /* If a symbol is defined externally, the assembler will use the
7457 usual -G rules when deciding how to implement macros. */
7458 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
7461 else if (TARGET_EMBEDDED_DATA
)
7463 /* Don't put constants into the small data section: we want them
7464 to be in ROM rather than RAM. */
7465 if (TREE_CODE (decl
) != VAR_DECL
)
7468 if (TREE_READONLY (decl
)
7469 && !TREE_SIDE_EFFECTS (decl
)
7470 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7474 /* Enforce -mlocal-sdata. */
7475 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
7478 /* Enforce -mextern-sdata. */
7479 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
7481 if (DECL_EXTERNAL (decl
))
7483 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
7487 /* We have traditionally not treated zero-sized objects as small data,
7488 so this is now effectively part of the ABI. */
7489 size
= int_size_in_bytes (TREE_TYPE (decl
));
7490 return size
> 0 && size
<= mips_small_data_threshold
;
7493 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7494 anchors for small data: the GP register acts as an anchor in that
7495 case. We also don't want to use them for PC-relative accesses,
7496 where the PC acts as an anchor. */
7499 mips_use_anchors_for_symbol_p (const_rtx symbol
)
7501 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
7503 case SYMBOL_PC_RELATIVE
:
7504 case SYMBOL_GP_RELATIVE
:
7508 return default_use_anchors_for_symbol_p (symbol
);
7512 /* The MIPS debug format wants all automatic variables and arguments
7513 to be in terms of the virtual frame pointer (stack pointer before
7514 any adjustment in the function), while the MIPS 3.0 linker wants
7515 the frame pointer to be the stack pointer after the initial
7516 adjustment. So, we do the adjustment here. The arg pointer (which
7517 is eliminated) points to the virtual frame pointer, while the frame
7518 pointer (which may be eliminated) points to the stack pointer after
7519 the initial adjustments. */
7522 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
7524 rtx offset2
= const0_rtx
;
7525 rtx reg
= eliminate_constant_term (addr
, &offset2
);
7528 offset
= INTVAL (offset2
);
7530 if (reg
== stack_pointer_rtx
7531 || reg
== frame_pointer_rtx
7532 || reg
== hard_frame_pointer_rtx
)
7534 offset
-= cfun
->machine
->frame
.total_size
;
7535 if (reg
== hard_frame_pointer_rtx
)
7536 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7539 /* sdbout_parms does not want this to crash for unrecognized cases. */
7541 else if (reg
!= arg_pointer_rtx
)
7542 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7549 /* Implement ASM_OUTPUT_EXTERNAL. */
7552 mips_output_external (FILE *file
, tree decl
, const char *name
)
7554 default_elf_asm_output_external (file
, decl
, name
);
7556 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7557 set in order to avoid putting out names that are never really
7559 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
7561 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
7563 /* When using assembler macros, emit .extern directives for
7564 all small-data externs so that the assembler knows how
7567 In most cases it would be safe (though pointless) to emit
7568 .externs for other symbols too. One exception is when an
7569 object is within the -G limit but declared by the user to
7570 be in a section other than .sbss or .sdata. */
7571 fputs ("\t.extern\t", file
);
7572 assemble_name (file
, name
);
7573 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
7574 int_size_in_bytes (TREE_TYPE (decl
)));
7576 else if (TARGET_IRIX
7577 && mips_abi
== ABI_32
7578 && TREE_CODE (decl
) == FUNCTION_DECL
)
7580 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7581 `.global name .text' directive for every used but
7582 undefined function. If we don't, the linker may perform
7583 an optimization (skipping over the insns that set $gp)
7584 when it is unsafe. */
7585 fputs ("\t.globl ", file
);
7586 assemble_name (file
, name
);
7587 fputs (" .text\n", file
);
7592 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7595 mips_output_filename (FILE *stream
, const char *name
)
7597 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7599 if (write_symbols
== DWARF2_DEBUG
)
7601 else if (mips_output_filename_first_time
)
7603 mips_output_filename_first_time
= 0;
7604 num_source_filenames
+= 1;
7605 current_function_file
= name
;
7606 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7607 output_quoted_string (stream
, name
);
7608 putc ('\n', stream
);
7610 /* If we are emitting stabs, let dbxout.c handle this (except for
7611 the mips_output_filename_first_time case). */
7612 else if (write_symbols
== DBX_DEBUG
)
7614 else if (name
!= current_function_file
7615 && strcmp (name
, current_function_file
) != 0)
7617 num_source_filenames
+= 1;
7618 current_function_file
= name
;
7619 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7620 output_quoted_string (stream
, name
);
7621 putc ('\n', stream
);
7625 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7627 static void ATTRIBUTE_UNUSED
7628 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7633 fputs ("\t.dtprelword\t", file
);
7637 fputs ("\t.dtpreldword\t", file
);
7643 output_addr_const (file
, x
);
7644 fputs ("+0x8000", file
);
7647 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7650 mips_dwarf_register_span (rtx reg
)
7653 enum machine_mode mode
;
7655 /* By default, GCC maps increasing register numbers to increasing
7656 memory locations, but paired FPRs are always little-endian,
7657 regardless of the prevailing endianness. */
7658 mode
= GET_MODE (reg
);
7659 if (FP_REG_P (REGNO (reg
))
7660 && TARGET_BIG_ENDIAN
7661 && MAX_FPRS_PER_FMT
> 1
7662 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
7664 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
7665 high
= mips_subword (reg
, true);
7666 low
= mips_subword (reg
, false);
7667 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
7673 /* Implement ASM_OUTPUT_ASCII. */
7676 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
7682 fprintf (stream
, "\t.ascii\t\"");
7683 for (i
= 0; i
< len
; i
++)
7687 c
= (unsigned char) string
[i
];
7690 if (c
== '\\' || c
== '\"')
7692 putc ('\\', stream
);
7700 fprintf (stream
, "\\%03o", c
);
7704 if (cur_pos
> 72 && i
+1 < len
)
7707 fprintf (stream
, "\"\n\t.ascii\t\"");
7710 fprintf (stream
, "\"\n");
7713 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7714 macros, mark the symbol as written so that mips_asm_output_external
7715 won't emit an .extern for it. STREAM is the output file, NAME is the
7716 name of the symbol, INIT_STRING is the string that should be written
7717 before the symbol and FINAL_STRING is the string that should be
7718 written after it. FINAL_STRING is a printf format that consumes the
7719 remaining arguments. */
7722 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
7723 const char *final_string
, ...)
7727 fputs (init_string
, stream
);
7728 assemble_name (stream
, name
);
7729 va_start (ap
, final_string
);
7730 vfprintf (stream
, final_string
, ap
);
7733 if (!TARGET_EXPLICIT_RELOCS
)
7735 tree name_tree
= get_identifier (name
);
7736 TREE_ASM_WRITTEN (name_tree
) = 1;
7740 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7741 NAME is the name of the object and ALIGN is the required alignment
7742 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7743 alignment argument. */
7746 mips_declare_common_object (FILE *stream
, const char *name
,
7747 const char *init_string
,
7748 unsigned HOST_WIDE_INT size
,
7749 unsigned int align
, bool takes_alignment_p
)
7751 if (!takes_alignment_p
)
7753 size
+= (align
/ BITS_PER_UNIT
) - 1;
7754 size
-= size
% (align
/ BITS_PER_UNIT
);
7755 mips_declare_object (stream
, name
, init_string
,
7756 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
7759 mips_declare_object (stream
, name
, init_string
,
7760 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
7761 size
, align
/ BITS_PER_UNIT
);
7764 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7765 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7768 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
7769 unsigned HOST_WIDE_INT size
,
7772 /* If the target wants uninitialized const declarations in
7773 .rdata then don't put them in .comm. */
7774 if (TARGET_EMBEDDED_DATA
7775 && TARGET_UNINIT_CONST_IN_RODATA
7776 && TREE_CODE (decl
) == VAR_DECL
7777 && TREE_READONLY (decl
)
7778 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
7780 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
7781 targetm
.asm_out
.globalize_label (stream
, name
);
7783 switch_to_section (readonly_data_section
);
7784 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
7785 mips_declare_object (stream
, name
, "",
7786 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
7790 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
7794 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7795 extern int size_directive_output
;
7797 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7798 definitions except that it uses mips_declare_object to emit the label. */
7801 mips_declare_object_name (FILE *stream
, const char *name
,
7802 tree decl ATTRIBUTE_UNUSED
)
7804 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7805 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
7808 size_directive_output
= 0;
7809 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
7813 size_directive_output
= 1;
7814 size
= int_size_in_bytes (TREE_TYPE (decl
));
7815 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7818 mips_declare_object (stream
, name
, "", ":\n");
7821 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7824 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
7828 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
7829 if (!flag_inhibit_size_directive
7830 && DECL_SIZE (decl
) != 0
7833 && DECL_INITIAL (decl
) == error_mark_node
7834 && !size_directive_output
)
7838 size_directive_output
= 1;
7839 size
= int_size_in_bytes (TREE_TYPE (decl
));
7840 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7845 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7846 with the current ABI. */
7849 mips_mdebug_abi_name (void)
7862 return TARGET_64BIT
? "eabi64" : "eabi32";
7868 /* Implement TARGET_ASM_FILE_START. */
7871 mips_file_start (void)
7873 default_file_start ();
7875 /* Generate a special section to describe the ABI switches used to
7876 produce the resultant binary. This is unnecessary on IRIX and
7877 causes unwanted warnings from the native linker. */
7880 /* Record the ABI itself. Modern versions of binutils encode
7881 this information in the ELF header flags, but GDB needs the
7882 information in order to correctly debug binaries produced by
7883 older binutils. See the function mips_gdbarch_init in
7885 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
7886 mips_mdebug_abi_name ());
7888 /* There is no ELF header flag to distinguish long32 forms of the
7889 EABI from long64 forms. Emit a special section to help tools
7890 such as GDB. Do the same for o64, which is sometimes used with
7892 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
7893 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
7894 "\t.previous\n", TARGET_LONG64
? 64 : 32);
7896 #ifdef HAVE_AS_GNU_ATTRIBUTE
7897 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
7898 (TARGET_HARD_FLOAT_ABI
7899 ? (TARGET_DOUBLE_FLOAT
7900 ? ((!TARGET_64BIT
&& TARGET_FLOAT64
) ? 4 : 1) : 2) : 3));
7904 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7905 if (TARGET_ABICALLS
)
7907 fprintf (asm_out_file
, "\t.abicalls\n");
7908 if (TARGET_ABICALLS_PIC0
)
7909 fprintf (asm_out_file
, "\t.option\tpic0\n");
7912 if (flag_verbose_asm
)
7913 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7915 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
7918 /* Make the last instruction frame-related and note that it performs
7919 the operation described by FRAME_PATTERN. */
7922 mips_set_frame_expr (rtx frame_pattern
)
7926 insn
= get_last_insn ();
7927 RTX_FRAME_RELATED_P (insn
) = 1;
7928 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7933 /* Return a frame-related rtx that stores REG at MEM.
7934 REG must be a single register. */
7937 mips_frame_set (rtx mem
, rtx reg
)
7941 /* If we're saving the return address register and the DWARF return
7942 address column differs from the hard register number, adjust the
7943 note reg to refer to the former. */
7944 if (REGNO (reg
) == GP_REG_FIRST
+ 31
7945 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
7946 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
7948 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
7949 RTX_FRAME_RELATED_P (set
) = 1;
7954 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7955 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7956 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7957 static const unsigned char mips16e_s2_s8_regs
[] = {
7958 30, 23, 22, 21, 20, 19, 18
7960 static const unsigned char mips16e_a0_a3_regs
[] = {
7964 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7965 ordered from the uppermost in memory to the lowest in memory. */
7966 static const unsigned char mips16e_save_restore_regs
[] = {
7967 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7970 /* Return the index of the lowest X in the range [0, SIZE) for which
7971 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7974 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
7979 for (i
= 0; i
< size
; i
++)
7980 if (BITSET_P (mask
, regs
[i
]))
7986 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7987 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7988 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7989 is true for all indexes (X, SIZE). */
7992 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
7993 unsigned int size
, unsigned int *num_regs_ptr
)
7997 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
7998 for (i
++; i
< size
; i
++)
7999 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8002 *mask_ptr
|= 1 << regs
[i
];
8006 /* Return a simplified form of X using the register values in REG_VALUES.
8007 REG_VALUES[R] is the last value assigned to hard register R, or null
8008 if R has not been modified.
8010 This function is rather limited, but is good enough for our purposes. */
8013 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8015 x
= avoid_constant_pool_reference (x
);
8019 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8020 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8021 x0
, GET_MODE (XEXP (x
, 0)));
8024 if (ARITHMETIC_P (x
))
8026 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8027 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8028 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8032 && reg_values
[REGNO (x
)]
8033 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8034 return reg_values
[REGNO (x
)];
8039 /* Return true if (set DEST SRC) stores an argument register into its
8040 caller-allocated save slot, storing the number of that argument
8041 register in *REGNO_PTR if so. REG_VALUES is as for
8042 mips16e_collect_propagate_value. */
8045 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8046 unsigned int *regno_ptr
)
8048 unsigned int argno
, regno
;
8049 HOST_WIDE_INT offset
, required_offset
;
8052 /* Check that this is a word-mode store. */
8053 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8056 /* Check that the register being saved is an unmodified argument
8058 regno
= REGNO (src
);
8059 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8061 argno
= regno
- GP_ARG_FIRST
;
8063 /* Check whether the address is an appropriate stack-pointer or
8064 frame-pointer access. */
8065 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8066 mips_split_plus (addr
, &base
, &offset
);
8067 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8068 if (base
== hard_frame_pointer_rtx
)
8069 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8070 else if (base
!= stack_pointer_rtx
)
8072 if (offset
!= required_offset
)
8079 /* A subroutine of mips_expand_prologue, called only when generating
8080 MIPS16e SAVE instructions. Search the start of the function for any
8081 instructions that save argument registers into their caller-allocated
8082 save slots. Delete such instructions and return a value N such that
8083 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8084 instructions redundant. */
8087 mips16e_collect_argument_saves (void)
8089 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8090 rtx insn
, next
, set
, dest
, src
;
8091 unsigned int nargs
, regno
;
8093 push_topmost_sequence ();
8095 memset (reg_values
, 0, sizeof (reg_values
));
8096 for (insn
= get_insns (); insn
; insn
= next
)
8098 next
= NEXT_INSN (insn
);
8105 set
= PATTERN (insn
);
8106 if (GET_CODE (set
) != SET
)
8109 dest
= SET_DEST (set
);
8110 src
= SET_SRC (set
);
8111 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8113 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8116 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8119 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8120 reg_values
[REGNO (dest
)]
8121 = mips16e_collect_propagate_value (src
, reg_values
);
8125 pop_topmost_sequence ();
8130 /* Return a move between register REGNO and memory location SP + OFFSET.
8131 Make the move a load if RESTORE_P, otherwise make it a frame-related
8135 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
8140 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
8141 reg
= gen_rtx_REG (SImode
, regno
);
8143 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
8144 : mips_frame_set (mem
, reg
));
8147 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8148 The instruction must:
8150 - Allocate or deallocate SIZE bytes in total; SIZE is known
8153 - Save or restore as many registers in *MASK_PTR as possible.
8154 The instruction saves the first registers at the top of the
8155 allocated area, with the other registers below it.
8157 - Save NARGS argument registers above the allocated area.
8159 (NARGS is always zero if RESTORE_P.)
8161 The SAVE and RESTORE instructions cannot save and restore all general
8162 registers, so there may be some registers left over for the caller to
8163 handle. Destructively modify *MASK_PTR so that it contains the registers
8164 that still need to be saved or restored. The caller can save these
8165 registers in the memory immediately below *OFFSET_PTR, which is a
8166 byte offset from the bottom of the allocated stack area. */
8169 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8170 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8174 HOST_WIDE_INT offset
, top_offset
;
8175 unsigned int i
, regno
;
8178 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8180 /* Calculate the number of elements in the PARALLEL. We need one element
8181 for the stack adjustment, one for each argument register save, and one
8182 for each additional register move. */
8184 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8185 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8188 /* Create the final PARALLEL. */
8189 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8192 /* Add the stack pointer adjustment. */
8193 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8194 plus_constant (stack_pointer_rtx
,
8195 restore_p
? size
: -size
));
8196 RTX_FRAME_RELATED_P (set
) = 1;
8197 XVECEXP (pattern
, 0, n
++) = set
;
8199 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8200 top_offset
= restore_p
? size
: 0;
8202 /* Save the arguments. */
8203 for (i
= 0; i
< nargs
; i
++)
8205 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8206 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
8207 XVECEXP (pattern
, 0, n
++) = set
;
8210 /* Then fill in the other register moves. */
8211 offset
= top_offset
;
8212 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8214 regno
= mips16e_save_restore_regs
[i
];
8215 if (BITSET_P (*mask_ptr
, regno
))
8217 offset
-= UNITS_PER_WORD
;
8218 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
8219 XVECEXP (pattern
, 0, n
++) = set
;
8220 *mask_ptr
&= ~(1 << regno
);
8224 /* Tell the caller what offset it should use for the remaining registers. */
8225 *offset_ptr
= size
+ (offset
- top_offset
);
8227 gcc_assert (n
== XVECLEN (pattern
, 0));
8232 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8233 pointer. Return true if PATTERN matches the kind of instruction
8234 generated by mips16e_build_save_restore. If INFO is nonnull,
8235 initialize it when returning true. */
8238 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8239 struct mips16e_save_restore_info
*info
)
8241 unsigned int i
, nargs
, mask
, extra
;
8242 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8243 rtx set
, reg
, mem
, base
;
8246 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8249 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8250 top_offset
= adjust
> 0 ? adjust
: 0;
8252 /* Interpret all other members of the PARALLEL. */
8253 save_offset
= top_offset
- UNITS_PER_WORD
;
8257 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8259 /* Check that we have a SET. */
8260 set
= XVECEXP (pattern
, 0, n
);
8261 if (GET_CODE (set
) != SET
)
8264 /* Check that the SET is a load (if restoring) or a store
8266 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
8270 /* Check that the address is the sum of the stack pointer and a
8271 possibly-zero constant offset. */
8272 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
8273 if (base
!= stack_pointer_rtx
)
8276 /* Check that SET's other operand is a register. */
8277 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
8281 /* Check for argument saves. */
8282 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
8283 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
8285 else if (offset
== save_offset
)
8287 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
8288 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
8291 mask
|= 1 << REGNO (reg
);
8292 save_offset
-= UNITS_PER_WORD
;
8298 /* Check that the restrictions on register ranges are met. */
8300 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
8301 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
8302 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
8303 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
8307 /* Make sure that the topmost argument register is not saved twice.
8308 The checks above ensure that the same is then true for the other
8309 argument registers. */
8310 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
8313 /* Pass back information, if requested. */
8316 info
->nargs
= nargs
;
8318 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
8324 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8325 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8326 the null terminator. */
8329 mips16e_add_register_range (char *s
, unsigned int min_reg
,
8330 unsigned int max_reg
)
8332 if (min_reg
!= max_reg
)
8333 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
8335 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
8339 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8340 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8343 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
8345 static char buffer
[300];
8347 struct mips16e_save_restore_info info
;
8348 unsigned int i
, end
;
8351 /* Parse the pattern. */
8352 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
8355 /* Add the mnemonic. */
8356 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
8359 /* Save the arguments. */
8361 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
8362 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
8363 else if (info
.nargs
== 1)
8364 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
8366 /* Emit the amount of stack space to allocate or deallocate. */
8367 s
+= sprintf (s
, "%d", (int) info
.size
);
8369 /* Save or restore $16. */
8370 if (BITSET_P (info
.mask
, 16))
8371 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
8373 /* Save or restore $17. */
8374 if (BITSET_P (info
.mask
, 17))
8375 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
8377 /* Save or restore registers in the range $s2...$s8, which
8378 mips16e_s2_s8_regs lists in decreasing order. Note that this
8379 is a software register range; the hardware registers are not
8380 numbered consecutively. */
8381 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
8382 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
8384 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
8385 mips16e_s2_s8_regs
[i
]);
8387 /* Save or restore registers in the range $a0...$a3. */
8388 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
8389 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
8391 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
8392 mips16e_a0_a3_regs
[end
- 1]);
8394 /* Save or restore $31. */
8395 if (BITSET_P (info
.mask
, 31))
8396 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 31]);
8401 /* Return true if the current function has an insn that implicitly
8405 mips_function_has_gp_insn (void)
8407 /* Don't bother rechecking if we found one last time. */
8408 if (!cfun
->machine
->has_gp_insn_p
)
8412 push_topmost_sequence ();
8413 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8414 if (USEFUL_INSN_P (insn
)
8415 && (get_attr_got (insn
) != GOT_UNSET
8416 || mips_small_data_pattern_p (PATTERN (insn
))))
8418 cfun
->machine
->has_gp_insn_p
= true;
8421 pop_topmost_sequence ();
8423 return cfun
->machine
->has_gp_insn_p
;
8426 /* Return true if the current function returns its value in a floating-point
8427 register in MIPS16 mode. */
8430 mips16_cfun_returns_in_fpr_p (void)
8432 tree return_type
= DECL_RESULT (current_function_decl
);
8433 return (TARGET_MIPS16
8434 && TARGET_HARD_FLOAT_ABI
8435 && !aggregate_value_p (return_type
, current_function_decl
)
8436 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
8439 /* Return the register that should be used as the global pointer
8440 within this function. Return INVALID_REGNUM if the function
8441 doesn't need a global pointer. */
8444 mips_global_pointer (void)
8448 /* $gp is always available unless we're using a GOT. */
8449 if (!TARGET_USE_GOT
)
8450 return GLOBAL_POINTER_REGNUM
;
8452 /* We must always provide $gp when it is used implicitly. */
8453 if (!TARGET_EXPLICIT_RELOCS
)
8454 return GLOBAL_POINTER_REGNUM
;
8456 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8459 return GLOBAL_POINTER_REGNUM
;
8461 /* If the function has a nonlocal goto, $gp must hold the correct
8462 global pointer for the target function. */
8463 if (crtl
->has_nonlocal_goto
)
8464 return GLOBAL_POINTER_REGNUM
;
8466 /* There's no need to initialize $gp if it isn't referenced now,
8467 and if we can be sure that no new references will be added during
8469 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM
)
8470 && !mips_function_has_gp_insn ())
8472 /* The function doesn't use $gp at the moment. If we're generating
8473 -call_nonpic code, no new uses will be introduced during or after
8475 if (TARGET_ABICALLS_PIC0
)
8476 return INVALID_REGNUM
;
8478 /* We need to handle the following implicit gp references:
8480 - Reload can sometimes introduce constant pool references
8481 into a function that otherwise didn't need them. For example,
8482 suppose we have an instruction like:
8484 (set (reg:DF R1) (float:DF (reg:SI R2)))
8486 If R2 turns out to be constant such as 1, the instruction may
8487 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8488 the option of using this constant if R2 doesn't get allocated
8491 In cases like these, reload will have added the constant to the
8492 pool but no instruction will yet refer to it.
8494 - MIPS16 functions that return in FPRs need to call an
8495 external libgcc routine. */
8496 if (!crtl
->uses_const_pool
8497 && !mips16_cfun_returns_in_fpr_p ())
8498 return INVALID_REGNUM
;
8501 /* We need a global pointer, but perhaps we can use a call-clobbered
8502 register instead of $gp. */
8503 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
8504 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8505 if (!df_regs_ever_live_p (regno
)
8506 && call_really_used_regs
[regno
]
8507 && !fixed_regs
[regno
]
8508 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
8511 return GLOBAL_POINTER_REGNUM
;
8514 /* Return true if REGNO is a register that is ordinarily call-clobbered
8515 but must nevertheless be preserved by an interrupt handler. */
8518 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
8520 if (MD_REG_P (regno
))
8523 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
8526 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
8528 /* $0 is hard-wired. */
8529 if (regno
== GP_REG_FIRST
)
8532 /* The interrupt handler can treat kernel registers as
8533 scratch registers. */
8534 if (KERNEL_REG_P (regno
))
8537 /* The function will return the stack pointer to its original value
8539 if (regno
== STACK_POINTER_REGNUM
)
8542 /* Otherwise, return true for registers that aren't ordinarily
8544 return call_really_used_regs
[regno
];
8550 /* Return true if the current function should treat register REGNO
8554 mips_cfun_call_saved_reg_p (unsigned int regno
)
8556 /* Interrupt handlers need to save extra registers. */
8557 if (cfun
->machine
->interrupt_handler_p
8558 && mips_interrupt_extra_call_saved_reg_p (regno
))
8561 /* call_insns preserve $28 unless they explicitly say otherwise,
8562 so call_really_used_regs[] treats $28 as call-saved. However,
8563 we want the ABI property rather than the default call_insn
8565 return (regno
== GLOBAL_POINTER_REGNUM
8566 ? TARGET_CALL_SAVED_GP
8567 : !call_really_used_regs
[regno
]);
8570 /* Return true if the function body might clobber register REGNO.
8571 We know that REGNO is call-saved. */
8574 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
8576 /* Some functions should be treated as clobbering all call-saved
8578 if (crtl
->saves_all_registers
)
8581 /* DF handles cases where a register is explicitly referenced in
8582 the rtl. Incoming values are passed in call-clobbered registers,
8583 so we can assume that any live call-saved register is set within
8585 if (df_regs_ever_live_p (regno
))
8588 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8589 These clobbers are not explicit in the rtl. */
8590 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
8593 /* If we're using a call-saved global pointer, the function's
8594 prologue will need to set it up. */
8595 if (cfun
->machine
->global_pointer
== regno
)
8598 /* The function's prologue will need to set the frame pointer if
8599 frame_pointer_needed. */
8600 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
8603 /* If a MIPS16 function returns a value in FPRs, its epilogue
8604 will need to call an external libgcc routine. This yet-to-be
8605 generated call_insn will clobber $31. */
8606 if (regno
== GP_REG_FIRST
+ 31 && mips16_cfun_returns_in_fpr_p ())
8609 /* If REGNO is ordinarily call-clobbered, we must assume that any
8610 called function could modify it. */
8611 if (cfun
->machine
->interrupt_handler_p
8612 && !current_function_is_leaf
8613 && mips_interrupt_extra_call_saved_reg_p (regno
))
8619 /* Return true if the current function must save register REGNO. */
8622 mips_save_reg_p (unsigned int regno
)
8624 if (mips_cfun_call_saved_reg_p (regno
))
8626 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
8629 /* Save both registers in an FPR pair if either one is used. This is
8630 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8631 register to be used without the even register. */
8632 if (FP_REG_P (regno
)
8633 && MAX_FPRS_PER_FMT
== 2
8634 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
8638 /* We need to save the incoming return address if __builtin_eh_return
8639 is being used to set a different return address. */
8640 if (regno
== GP_REG_FIRST
+ 31 && crtl
->calls_eh_return
)
8646 /* Populate the current function's mips_frame_info structure.
8648 MIPS stack frames look like:
8650 +-------------------------------+
8652 | incoming stack arguments |
8654 +-------------------------------+
8656 | caller-allocated save area |
8657 A | for register arguments |
8659 +-------------------------------+ <-- incoming stack pointer
8661 | callee-allocated save area |
8662 B | for arguments that are |
8663 | split between registers and |
8666 +-------------------------------+ <-- arg_pointer_rtx
8668 C | callee-allocated save area |
8669 | for register varargs |
8671 +-------------------------------+ <-- frame_pointer_rtx
8672 | | + cop0_sp_offset
8673 | COP0 reg save area | + UNITS_PER_WORD
8675 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
8676 | | + UNITS_PER_WORD
8677 | accumulator save area |
8679 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
8680 | | + UNITS_PER_HWFPVALUE
8683 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
8684 | | + UNITS_PER_WORD
8687 +-------------------------------+
8689 | local variables | | var_size
8691 +-------------------------------+
8693 | $gp save area | | cprestore_size
8695 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8697 | outgoing stack arguments |
8699 +-------------------------------+
8701 | caller-allocated save area |
8702 | for register arguments |
8704 +-------------------------------+ <-- stack_pointer_rtx
8706 hard_frame_pointer_rtx for
8709 At least two of A, B and C will be empty.
8711 Dynamic stack allocations such as alloca insert data at point P.
8712 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8713 hard_frame_pointer_rtx unchanged. */
8716 mips_compute_frame_info (void)
8718 struct mips_frame_info
*frame
;
8719 HOST_WIDE_INT offset
, size
;
8720 unsigned int regno
, i
;
8722 /* Set this function's interrupt properties. */
8723 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
8726 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
8727 else if (TARGET_HARD_FLOAT
)
8728 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
8729 else if (TARGET_MIPS16
)
8730 error ("interrupt handlers cannot be MIPS16 functions");
8733 cfun
->machine
->interrupt_handler_p
= true;
8734 cfun
->machine
->use_shadow_register_set_p
=
8735 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
8736 cfun
->machine
->keep_interrupts_masked_p
=
8737 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
8738 cfun
->machine
->use_debug_exception_return_p
=
8739 mips_use_debug_exception_return_p (TREE_TYPE
8740 (current_function_decl
));
8744 frame
= &cfun
->machine
->frame
;
8745 memset (frame
, 0, sizeof (*frame
));
8746 size
= get_frame_size ();
8748 cfun
->machine
->global_pointer
= mips_global_pointer ();
8750 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8751 area and the $gp save slot. This area isn't needed in leaf functions,
8752 but if the target-independent frame size is nonzero, we're committed
8753 to allocating it anyway. */
8754 if (size
== 0 && current_function_is_leaf
)
8756 /* The MIPS 3.0 linker does not like functions that dynamically
8757 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8758 looks like we are trying to create a second frame pointer to the
8759 function, so allocate some stack space to make it happy. */
8760 if (cfun
->calls_alloca
)
8761 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
8763 frame
->args_size
= 0;
8764 frame
->cprestore_size
= 0;
8768 frame
->args_size
= crtl
->outgoing_args_size
;
8769 frame
->cprestore_size
= STARTING_FRAME_OFFSET
- frame
->args_size
;
8771 offset
= frame
->args_size
+ frame
->cprestore_size
;
8773 /* Move above the local variables. */
8774 frame
->var_size
= MIPS_STACK_ALIGN (size
);
8775 offset
+= frame
->var_size
;
8777 /* Find out which GPRs we need to save. */
8778 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8779 if (mips_save_reg_p (regno
))
8782 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
8785 /* If this function calls eh_return, we must also save and restore the
8786 EH data registers. */
8787 if (crtl
->calls_eh_return
)
8788 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
8791 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
8794 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8795 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8796 save all later registers too. */
8797 if (GENERATE_MIPS16E_SAVE_RESTORE
)
8799 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
8800 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
8801 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
8802 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
8805 /* Move above the GPR save area. */
8806 if (frame
->num_gp
> 0)
8808 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
8809 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
8812 /* Find out which FPRs we need to save. This loop must iterate over
8813 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
8814 if (TARGET_HARD_FLOAT
)
8815 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
8816 if (mips_save_reg_p (regno
))
8818 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
8819 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
8822 /* Move above the FPR save area. */
8823 if (frame
->num_fp
> 0)
8825 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
8826 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
8829 /* Add in space for the interrupt context information. */
8830 if (cfun
->machine
->interrupt_handler_p
)
8833 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
8836 frame
->acc_mask
|= (1 << 0);
8839 /* Check accumulators 1, 2, 3. */
8840 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
8841 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
8844 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
8847 /* All interrupt context functions need space to preserve STATUS. */
8848 frame
->num_cop0_regs
++;
8850 /* If we don't keep interrupts masked, we need to save EPC. */
8851 if (!cfun
->machine
->keep_interrupts_masked_p
)
8852 frame
->num_cop0_regs
++;
8855 /* Move above the accumulator save area. */
8856 if (frame
->num_acc
> 0)
8858 /* Each accumulator needs 2 words. */
8859 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
8860 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
8863 /* Move above the COP0 register save area. */
8864 if (frame
->num_cop0_regs
> 0)
8866 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
8867 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
8870 /* Move above the callee-allocated varargs save area. */
8871 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
8872 frame
->arg_pointer_offset
= offset
;
8874 /* Move above the callee-allocated area for pretend stack arguments. */
8875 offset
+= crtl
->args
.pretend_args_size
;
8876 frame
->total_size
= offset
;
8878 /* Work out the offsets of the save areas from the top of the frame. */
8879 if (frame
->gp_sp_offset
> 0)
8880 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
8881 if (frame
->fp_sp_offset
> 0)
8882 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
8883 if (frame
->acc_sp_offset
> 0)
8884 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
8885 if (frame
->num_cop0_regs
> 0)
8886 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
8888 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8889 arguments. This tends to increase the chances of using unextended
8890 instructions for local variables and incoming arguments. */
8892 frame
->hard_frame_pointer_offset
= frame
->args_size
;
8895 /* Return the style of GP load sequence that is being used for the
8896 current function. */
8898 enum mips_loadgp_style
8899 mips_current_loadgp_style (void)
8901 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
8907 if (TARGET_ABSOLUTE_ABICALLS
)
8908 return LOADGP_ABSOLUTE
;
8910 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
8913 /* Implement FRAME_POINTER_REQUIRED. */
8916 mips_frame_pointer_required (void)
8918 /* If the function contains dynamic stack allocations, we need to
8919 use the frame pointer to access the static parts of the frame. */
8920 if (cfun
->calls_alloca
)
8923 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8924 reload may be unable to compute the address of a local variable,
8925 since there is no way to add a large constant to the stack pointer
8926 without using a second temporary register. */
8929 mips_compute_frame_info ();
8930 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
8937 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8938 or argument pointer. TO is either the stack pointer or hard frame
8942 mips_initial_elimination_offset (int from
, int to
)
8944 HOST_WIDE_INT offset
;
8946 mips_compute_frame_info ();
8948 /* Set OFFSET to the offset from the soft frame pointer, which is also
8949 the offset from the end-of-prologue stack pointer. */
8952 case FRAME_POINTER_REGNUM
:
8956 case ARG_POINTER_REGNUM
:
8957 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
8964 if (to
== HARD_FRAME_POINTER_REGNUM
)
8965 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8970 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8973 mips_extra_live_on_entry (bitmap regs
)
8977 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8978 the global pointer. */
8979 if (!TARGET_ABSOLUTE_ABICALLS
)
8980 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
8982 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
8983 the global pointer. */
8985 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
8987 /* See the comment above load_call<mode> for details. */
8988 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
8992 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8996 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9001 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
9004 /* Emit code to change the current function's return address to
9005 ADDRESS. SCRATCH is available as a scratch register, if needed.
9006 ADDRESS and SCRATCH are both word-mode GPRs. */
9009 mips_set_return_address (rtx address
, rtx scratch
)
9013 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, 31));
9014 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9015 cfun
->machine
->frame
.gp_sp_offset
);
9016 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9019 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
9020 register if need be. */
9023 mips_cprestore_slot (rtx temp
)
9025 const struct mips_frame_info
*frame
;
9027 HOST_WIDE_INT offset
;
9029 frame
= &cfun
->machine
->frame
;
9030 if (frame_pointer_needed
)
9032 base
= hard_frame_pointer_rtx
;
9033 offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9037 base
= stack_pointer_rtx
;
9038 offset
= frame
->args_size
;
9040 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
9043 /* Restore $gp from its save slot, using TEMP as a temporary base register
9044 if need be. This function is for o32 and o64 abicalls only. */
9047 mips_restore_gp (rtx temp
)
9049 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
9051 if (cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9056 mips_emit_move (temp
, mips_cprestore_slot (temp
));
9057 mips_emit_move (pic_offset_table_rtx
, temp
);
9060 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
));
9061 if (!TARGET_EXPLICIT_RELOCS
)
9062 emit_insn (gen_blockage ());
9065 /* A function to save or store a register. The first argument is the
9066 register and the second is the stack slot. */
9067 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
9069 /* Use FN to save or restore register REGNO. MODE is the register's
9070 mode and OFFSET is the offset of its save slot from the current
9074 mips_save_restore_reg (enum machine_mode mode
, int regno
,
9075 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
9079 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
9080 fn (gen_rtx_REG (mode
, regno
), mem
);
9083 /* Call FN for each accumlator that is saved by the current function.
9084 SP_OFFSET is the offset of the current stack pointer from the start
9088 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
9090 HOST_WIDE_INT offset
;
9093 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
9094 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
9096 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
9097 offset
-= UNITS_PER_WORD
;
9098 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
9099 offset
-= UNITS_PER_WORD
;
9102 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
9103 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
9104 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
9106 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9107 offset
-= UNITS_PER_WORD
;
9111 /* Call FN for each register that is saved by the current function.
9112 SP_OFFSET is the offset of the current stack pointer from the start
9116 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
9117 mips_save_restore_fn fn
)
9119 enum machine_mode fpr_mode
;
9120 HOST_WIDE_INT offset
;
9123 /* Save registers starting from high to low. The debuggers prefer at least
9124 the return register be stored at func+4, and also it allows us not to
9125 need a nop in the epilogue if at least one register is reloaded in
9126 addition to return address. */
9127 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
9128 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
9129 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
9131 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9132 offset
-= UNITS_PER_WORD
;
9135 /* This loop must iterate over the same space as its companion in
9136 mips_compute_frame_info. */
9137 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
9138 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
9139 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
9140 regno
>= FP_REG_FIRST
;
9141 regno
-= MAX_FPRS_PER_FMT
)
9142 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
9144 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
9145 offset
-= GET_MODE_SIZE (fpr_mode
);
9149 /* If we're generating n32 or n64 abicalls, and the current function
9150 does not use $28 as its global pointer, emit a cplocal directive.
9151 Use pic_offset_table_rtx as the argument to the directive. */
9154 mips_output_cplocal (void)
9156 if (!TARGET_EXPLICIT_RELOCS
9157 && cfun
->machine
->global_pointer
!= INVALID_REGNUM
9158 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
9159 output_asm_insn (".cplocal %+", 0);
9162 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9165 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9169 #ifdef SDB_DEBUGGING_INFO
9170 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
9171 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
9174 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9175 floating-point arguments. */
9177 && TARGET_HARD_FLOAT_ABI
9178 && crtl
->args
.info
.fp_code
!= 0)
9179 mips16_build_function_stub ();
9181 /* Get the function name the same way that toplev.c does before calling
9182 assemble_start_function. This is needed so that the name used here
9183 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9184 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9185 mips_start_function_definition (fnname
, TARGET_MIPS16
);
9187 /* Stop mips_file_end from treating this function as external. */
9188 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
9189 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
9191 /* Output MIPS-specific frame information. */
9192 if (!flag_inhibit_size_directive
)
9194 const struct mips_frame_info
*frame
;
9196 frame
= &cfun
->machine
->frame
;
9198 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9200 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
9201 "# vars= " HOST_WIDE_INT_PRINT_DEC
9203 ", args= " HOST_WIDE_INT_PRINT_DEC
9204 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
9205 reg_names
[frame_pointer_needed
9206 ? HARD_FRAME_POINTER_REGNUM
9207 : STACK_POINTER_REGNUM
],
9208 (frame_pointer_needed
9209 ? frame
->total_size
- frame
->hard_frame_pointer_offset
9210 : frame
->total_size
),
9211 reg_names
[GP_REG_FIRST
+ 31],
9213 frame
->num_gp
, frame
->num_fp
,
9215 frame
->cprestore_size
);
9217 /* .mask MASK, OFFSET. */
9218 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9219 frame
->mask
, frame
->gp_save_offset
);
9221 /* .fmask MASK, OFFSET. */
9222 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9223 frame
->fmask
, frame
->fp_save_offset
);
9226 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9227 Also emit the ".set noreorder; .set nomacro" sequence for functions
9229 if (mips_current_loadgp_style () == LOADGP_OLDABI
)
9233 /* This is a fixed-form sequence. The position of the
9234 first two instructions is important because of the
9235 way _gp_disp is defined. */
9236 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9237 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9238 output_asm_insn ("sll\t$2,16", 0);
9239 output_asm_insn ("addu\t$2,$3", 0);
9241 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
9242 else if (!cfun
->machine
->all_noreorder_p
)
9243 output_asm_insn ("%(.cpload\t%^%)", 0);
9245 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
9247 else if (cfun
->machine
->all_noreorder_p
)
9248 output_asm_insn ("%(%<", 0);
9250 /* Tell the assembler which register we're using as the global
9251 pointer. This is needed for thunks, since they can use either
9252 explicit relocs or assembler macros. */
9253 mips_output_cplocal ();
9256 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9259 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9260 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9264 /* Reinstate the normal $gp. */
9265 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
9266 mips_output_cplocal ();
9268 if (cfun
->machine
->all_noreorder_p
)
9270 /* Avoid using %>%) since it adds excess whitespace. */
9271 output_asm_insn (".set\tmacro", 0);
9272 output_asm_insn (".set\treorder", 0);
9273 set_noreorder
= set_nomacro
= 0;
9276 /* Get the function name the same way that toplev.c does before calling
9277 assemble_start_function. This is needed so that the name used here
9278 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9279 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9280 mips_end_function_definition (fnname
);
9283 /* Save register REG to MEM. Make the instruction frame-related. */
9286 mips_save_reg (rtx reg
, rtx mem
)
9288 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
9292 if (mips_split_64bit_move_p (mem
, reg
))
9293 mips_split_doubleword_move (mem
, reg
);
9295 mips_emit_move (mem
, reg
);
9297 x1
= mips_frame_set (mips_subword (mem
, false),
9298 mips_subword (reg
, false));
9299 x2
= mips_frame_set (mips_subword (mem
, true),
9300 mips_subword (reg
, true));
9301 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
9305 if (REGNO (reg
) == HI_REGNUM
)
9308 emit_insn (gen_mfhidi_ti (MIPS_PROLOGUE_TEMP (DImode
),
9309 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
9311 emit_insn (gen_mfhisi_di (MIPS_PROLOGUE_TEMP (SImode
),
9312 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
9313 mips_emit_move (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
9315 else if ((TARGET_MIPS16
9316 && REGNO (reg
) != GP_REG_FIRST
+ 31
9317 && !M16_REG_P (REGNO (reg
)))
9318 || ACC_REG_P (REGNO (reg
)))
9320 /* If the register has no direct store instruction, move it
9321 through a temporary. Note that there's a special MIPS16
9322 instruction to save $31. */
9323 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
9324 mips_emit_move (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
9327 mips_emit_move (mem
, reg
);
9329 mips_set_frame_expr (mips_frame_set (mem
, reg
));
9333 /* The __gnu_local_gp symbol. */
9335 static GTY(()) rtx mips_gnu_local_gp
;
9337 /* If we're generating n32 or n64 abicalls, emit instructions
9338 to set up the global pointer. */
9341 mips_emit_loadgp (void)
9343 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
9345 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
9346 switch (mips_current_loadgp_style ())
9348 case LOADGP_ABSOLUTE
:
9349 if (mips_gnu_local_gp
== NULL
)
9351 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
9352 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
9354 emit_insn (Pmode
== SImode
9355 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
9356 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
9360 /* Added by mips_output_function_prologue. */
9364 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
9365 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
9366 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
9367 emit_insn (Pmode
== SImode
9368 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
9369 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
9373 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
9374 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
9375 emit_insn (Pmode
== SImode
9376 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
9377 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
9385 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx
, pic_reg
));
9387 /* Emit a blockage if there are implicit uses of the GP register.
9388 This includes profiled functions, because FUNCTION_PROFILE uses
9390 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
9391 emit_insn (gen_loadgp_blockage ());
9394 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9397 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
9399 return GET_CODE (*x
) == REG
&& KERNEL_REG_P (REGNO (*x
));
9402 /* Expand the "prologue" pattern. */
9405 mips_expand_prologue (void)
9407 const struct mips_frame_info
*frame
;
9412 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
9413 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
9415 frame
= &cfun
->machine
->frame
;
9416 size
= frame
->total_size
;
9418 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9419 bytes beforehand; this is enough to cover the register save area
9420 without going out of range. */
9421 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
9422 || frame
->num_cop0_regs
> 0)
9424 HOST_WIDE_INT step1
;
9426 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
9427 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9429 HOST_WIDE_INT offset
;
9430 unsigned int mask
, regno
;
9432 /* Try to merge argument stores into the save instruction. */
9433 nargs
= mips16e_collect_argument_saves ();
9435 /* Build the save instruction. */
9437 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
9439 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
9442 /* Check if we need to save other registers. */
9443 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
9444 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
9446 offset
-= UNITS_PER_WORD
;
9447 mips_save_restore_reg (word_mode
, regno
,
9448 offset
, mips_save_reg
);
9453 if (cfun
->machine
->interrupt_handler_p
)
9455 HOST_WIDE_INT offset
;
9458 /* If this interrupt is using a shadow register set, we need to
9459 get the stack pointer from the previous register set. */
9460 if (cfun
->machine
->use_shadow_register_set_p
)
9461 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
9462 stack_pointer_rtx
));
9464 if (!cfun
->machine
->keep_interrupts_masked_p
)
9466 /* Move from COP0 Cause to K0. */
9467 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
9468 gen_rtx_REG (SImode
,
9469 COP0_CAUSE_REG_NUM
)));
9470 /* Move from COP0 EPC to K1. */
9471 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
9472 gen_rtx_REG (SImode
,
9473 COP0_EPC_REG_NUM
)));
9476 /* Allocate the first part of the frame. */
9477 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
9479 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
9482 /* Start at the uppermost location for saving. */
9483 offset
= frame
->cop0_sp_offset
- size
;
9484 if (!cfun
->machine
->keep_interrupts_masked_p
)
9486 /* Push EPC into its stack slot. */
9487 mem
= gen_frame_mem (word_mode
,
9488 plus_constant (stack_pointer_rtx
,
9490 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
9491 offset
-= UNITS_PER_WORD
;
9494 /* Move from COP0 Status to K1. */
9495 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
9496 gen_rtx_REG (SImode
,
9497 COP0_STATUS_REG_NUM
)));
9499 /* Right justify the RIPL in k0. */
9500 if (!cfun
->machine
->keep_interrupts_masked_p
)
9501 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
9502 gen_rtx_REG (SImode
, K0_REG_NUM
),
9503 GEN_INT (CAUSE_IPL
)));
9505 /* Push Status into its stack slot. */
9506 mem
= gen_frame_mem (word_mode
,
9507 plus_constant (stack_pointer_rtx
, offset
));
9508 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
9509 offset
-= UNITS_PER_WORD
;
9511 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
9512 if (!cfun
->machine
->keep_interrupts_masked_p
)
9513 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
9516 gen_rtx_REG (SImode
, K0_REG_NUM
)));
9518 if (!cfun
->machine
->keep_interrupts_masked_p
)
9519 /* Enable interrupts by clearing the KSU ERL and EXL bits.
9520 IE is already the correct value, so we don't have to do
9521 anything explicit. */
9522 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
9525 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
9527 /* Disable interrupts by clearing the KSU, ERL, EXL,
9529 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
9532 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
9536 insn
= gen_add3_insn (stack_pointer_rtx
,
9539 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
9542 mips_for_each_saved_acc (size
, mips_save_reg
);
9543 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
9547 /* Allocate the rest of the frame. */
9550 if (SMALL_OPERAND (-size
))
9551 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
9553 GEN_INT (-size
)))) = 1;
9556 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
9559 /* There are no instructions to add or subtract registers
9560 from the stack pointer, so use the frame pointer as a
9561 temporary. We should always be using a frame pointer
9562 in this case anyway. */
9563 gcc_assert (frame_pointer_needed
);
9564 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
9565 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
9566 hard_frame_pointer_rtx
,
9567 MIPS_PROLOGUE_TEMP (Pmode
)));
9568 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
9571 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
9573 MIPS_PROLOGUE_TEMP (Pmode
)));
9575 /* Describe the combined effect of the previous instructions. */
9577 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9578 plus_constant (stack_pointer_rtx
, -size
)));
9582 /* Set up the frame pointer, if we're using one. */
9583 if (frame_pointer_needed
)
9585 HOST_WIDE_INT offset
;
9587 offset
= frame
->hard_frame_pointer_offset
;
9590 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
9591 RTX_FRAME_RELATED_P (insn
) = 1;
9593 else if (SMALL_OPERAND (offset
))
9595 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
9596 stack_pointer_rtx
, GEN_INT (offset
));
9597 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
9601 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
9602 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
9603 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
9604 hard_frame_pointer_rtx
,
9605 MIPS_PROLOGUE_TEMP (Pmode
)));
9607 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
9608 plus_constant (stack_pointer_rtx
, offset
)));
9612 mips_emit_loadgp ();
9614 /* Initialize the $gp save slot. */
9615 if (frame
->cprestore_size
> 0
9616 && cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
9619 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode
)),
9621 else if (TARGET_ABICALLS_PIC2
)
9622 emit_insn (gen_cprestore (GEN_INT (frame
->args_size
)));
9624 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode
)),
9625 pic_offset_table_rtx
);
9628 /* We need to search back to the last use of K0 or K1. */
9629 if (cfun
->machine
->interrupt_handler_p
)
9631 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
9633 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
9635 /* Emit a move from K1 to COP0 Status after insn. */
9636 gcc_assert (insn
!= NULL_RTX
);
9637 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
9638 gen_rtx_REG (SImode
, K1_REG_NUM
)),
9642 /* If we are profiling, make sure no instructions are scheduled before
9643 the call to mcount. */
9645 emit_insn (gen_blockage ());
9648 /* Emit instructions to restore register REG from slot MEM. */
9651 mips_restore_reg (rtx reg
, rtx mem
)
9653 /* There's no MIPS16 instruction to load $31 directly. Load into
9654 $7 instead and adjust the return insn appropriately. */
9655 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
9656 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
9658 if (REGNO (reg
) == HI_REGNUM
)
9660 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
9662 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
9663 MIPS_EPILOGUE_TEMP (DImode
),
9664 gen_rtx_REG (DImode
, LO_REGNUM
)));
9666 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
9667 MIPS_EPILOGUE_TEMP (SImode
),
9668 gen_rtx_REG (SImode
, LO_REGNUM
)));
9670 else if ((TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
9671 || ACC_REG_P (REGNO (reg
)))
9673 /* Can't restore directly; move through a temporary. */
9674 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
9675 mips_emit_move (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
9678 mips_emit_move (reg
, mem
);
9681 /* Emit any instructions needed before a return. */
9684 mips_expand_before_return (void)
9686 /* When using a call-clobbered gp, we start out with unified call
9687 insns that include instructions to restore the gp. We then split
9688 these unified calls after reload. These split calls explicitly
9689 clobber gp, so there is no need to define
9690 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9692 For consistency, we should also insert an explicit clobber of $28
9693 before return insns, so that the post-reload optimizers know that
9694 the register is not live on exit. */
9695 if (TARGET_CALL_CLOBBERED_GP
)
9696 emit_clobber (pic_offset_table_rtx
);
9699 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9703 mips_expand_epilogue (bool sibcall_p
)
9705 const struct mips_frame_info
*frame
;
9706 HOST_WIDE_INT step1
, step2
;
9707 rtx base
, target
, insn
;
9709 if (!sibcall_p
&& mips_can_use_return_insn ())
9711 emit_jump_insn (gen_return ());
9715 /* In MIPS16 mode, if the return value should go into a floating-point
9716 register, we need to call a helper routine to copy it over. */
9717 if (mips16_cfun_returns_in_fpr_p ())
9718 mips16_copy_fpr_return_value ();
9720 /* Split the frame into two. STEP1 is the amount of stack we should
9721 deallocate before restoring the registers. STEP2 is the amount we
9722 should deallocate afterwards.
9724 Start off by assuming that no registers need to be restored. */
9725 frame
= &cfun
->machine
->frame
;
9726 step1
= frame
->total_size
;
9729 /* Work out which register holds the frame address. */
9730 if (!frame_pointer_needed
)
9731 base
= stack_pointer_rtx
;
9734 base
= hard_frame_pointer_rtx
;
9735 step1
-= frame
->hard_frame_pointer_offset
;
9738 /* If we need to restore registers, deallocate as much stack as
9739 possible in the second step without going out of range. */
9740 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
9741 || frame
->num_cop0_regs
> 0)
9743 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
9747 /* Set TARGET to BASE + STEP1. */
9753 /* Get an rtx for STEP1 that we can add to BASE. */
9754 adjust
= GEN_INT (step1
);
9755 if (!SMALL_OPERAND (step1
))
9757 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
9758 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
9761 /* Normal mode code can copy the result straight into $sp. */
9763 target
= stack_pointer_rtx
;
9765 emit_insn (gen_add3_insn (target
, base
, adjust
));
9768 /* Copy TARGET into the stack pointer. */
9769 if (target
!= stack_pointer_rtx
)
9770 mips_emit_move (stack_pointer_rtx
, target
);
9772 /* If we're using addressing macros, $gp is implicitly used by all
9773 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9775 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
9776 emit_insn (gen_blockage ());
9778 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
9780 unsigned int regno
, mask
;
9781 HOST_WIDE_INT offset
;
9784 /* Generate the restore instruction. */
9786 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
9788 /* Restore any other registers manually. */
9789 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
9790 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
9792 offset
-= UNITS_PER_WORD
;
9793 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
9796 /* Restore the remaining registers and deallocate the final bit
9798 emit_insn (restore
);
9802 /* Restore the registers. */
9803 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
9804 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
9807 if (cfun
->machine
->interrupt_handler_p
)
9809 HOST_WIDE_INT offset
;
9812 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
9813 if (!cfun
->machine
->keep_interrupts_masked_p
)
9815 /* Restore the original EPC. */
9816 mem
= gen_frame_mem (word_mode
,
9817 plus_constant (stack_pointer_rtx
, offset
));
9818 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
9819 offset
-= UNITS_PER_WORD
;
9821 /* Move to COP0 EPC. */
9822 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
9823 gen_rtx_REG (SImode
, K0_REG_NUM
)));
9826 /* Restore the original Status. */
9827 mem
= gen_frame_mem (word_mode
,
9828 plus_constant (stack_pointer_rtx
, offset
));
9829 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
9830 offset
-= UNITS_PER_WORD
;
9832 /* If we don't use shoadow register set, we need to update SP. */
9833 if (!cfun
->machine
->use_shadow_register_set_p
&& step2
> 0)
9834 emit_insn (gen_add3_insn (stack_pointer_rtx
,
9838 /* Move to COP0 Status. */
9839 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
9840 gen_rtx_REG (SImode
, K0_REG_NUM
)));
9844 /* Deallocate the final bit of the frame. */
9846 emit_insn (gen_add3_insn (stack_pointer_rtx
,
9852 /* Add in the __builtin_eh_return stack adjustment. We need to
9853 use a temporary in MIPS16 code. */
9854 if (crtl
->calls_eh_return
)
9858 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
9859 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
9860 MIPS_EPILOGUE_TEMP (Pmode
),
9861 EH_RETURN_STACKADJ_RTX
));
9862 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
9865 emit_insn (gen_add3_insn (stack_pointer_rtx
,
9867 EH_RETURN_STACKADJ_RTX
));
9872 mips_expand_before_return ();
9873 if (cfun
->machine
->interrupt_handler_p
)
9875 /* Interrupt handlers generate eret or deret. */
9876 if (cfun
->machine
->use_debug_exception_return_p
)
9877 emit_jump_insn (gen_mips_deret ());
9879 emit_jump_insn (gen_mips_eret ());
9885 /* When generating MIPS16 code, the normal
9886 mips_for_each_saved_gpr_and_fpr path will restore the return
9887 address into $7 rather than $31. */
9889 && !GENERATE_MIPS16E_SAVE_RESTORE
9890 && BITSET_P (frame
->mask
, 31))
9891 regno
= GP_REG_FIRST
+ 7;
9893 regno
= GP_REG_FIRST
+ 31;
9894 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
9898 /* Search from the beginning to the first use of K0 or K1. */
9899 if (cfun
->machine
->interrupt_handler_p
9900 && !cfun
->machine
->keep_interrupts_masked_p
)
9902 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
9904 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
9906 gcc_assert (insn
!= NULL_RTX
);
9907 /* Insert disable interrupts before the first use of K0 or K1. */
9908 emit_insn_before (gen_mips_di (), insn
);
9909 emit_insn_before (gen_mips_ehb (), insn
);
9913 /* Return nonzero if this function is known to have a null epilogue.
9914 This allows the optimizer to omit jumps to jumps if no stack
9918 mips_can_use_return_insn (void)
9920 /* Interrupt handlers need to go through the epilogue. */
9921 if (cfun
->machine
->interrupt_handler_p
)
9924 if (!reload_completed
)
9930 /* In MIPS16 mode, a function that returns a floating-point value
9931 needs to arrange to copy the return value into the floating-point
9933 if (mips16_cfun_returns_in_fpr_p ())
9936 return cfun
->machine
->frame
.total_size
== 0;
9939 /* Return true if register REGNO can store a value of mode MODE.
9940 The result of this function is cached in mips_hard_regno_mode_ok. */
9943 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
9946 enum mode_class mclass
;
9948 if (mode
== CCV2mode
)
9951 && (regno
- ST_REG_FIRST
) % 2 == 0);
9953 if (mode
== CCV4mode
)
9956 && (regno
- ST_REG_FIRST
) % 4 == 0);
9961 return regno
== FPSW_REGNUM
;
9963 return (ST_REG_P (regno
)
9965 || FP_REG_P (regno
));
9968 size
= GET_MODE_SIZE (mode
);
9969 mclass
= GET_MODE_CLASS (mode
);
9971 if (GP_REG_P (regno
))
9972 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
9974 if (FP_REG_P (regno
)
9975 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
9976 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
9978 /* Allow TFmode for CCmode reloads. */
9979 if (mode
== TFmode
&& ISA_HAS_8CC
)
9982 /* Allow 64-bit vector modes for Loongson-2E/2F. */
9983 if (TARGET_LOONGSON_VECTORS
9984 && (mode
== V2SImode
9990 if (mclass
== MODE_FLOAT
9991 || mclass
== MODE_COMPLEX_FLOAT
9992 || mclass
== MODE_VECTOR_FLOAT
)
9993 return size
<= UNITS_PER_FPVALUE
;
9995 /* Allow integer modes that fit into a single register. We need
9996 to put integers into FPRs when using instructions like CVT
9997 and TRUNC. There's no point allowing sizes smaller than a word,
9998 because the FPU has no appropriate load/store instructions. */
9999 if (mclass
== MODE_INT
)
10000 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
10003 if (ACC_REG_P (regno
)
10004 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
10006 if (MD_REG_P (regno
))
10008 /* After a multiplication or division, clobbering HI makes
10009 the value of LO unpredictable, and vice versa. This means
10010 that, for all interesting cases, HI and LO are effectively
10013 We model this by requiring that any value that uses HI
10015 if (size
<= UNITS_PER_WORD
* 2)
10016 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
10020 /* DSP accumulators do not have the same restrictions as
10021 HI and LO, so we can treat them as normal doubleword
10023 if (size
<= UNITS_PER_WORD
)
10026 if (size
<= UNITS_PER_WORD
* 2
10027 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
10032 if (ALL_COP_REG_P (regno
))
10033 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
10035 if (regno
== GOT_VERSION_REGNUM
)
10036 return mode
== SImode
;
10041 /* Implement HARD_REGNO_NREGS. */
10044 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
10046 if (ST_REG_P (regno
))
10047 /* The size of FP status registers is always 4, because they only hold
10048 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10049 return (GET_MODE_SIZE (mode
) + 3) / 4;
10051 if (FP_REG_P (regno
))
10052 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
10054 /* All other registers are word-sized. */
10055 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
10058 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10059 in mips_hard_regno_nregs. */
10062 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
10068 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
10069 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
10071 size
= MIN (size
, 4);
10072 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
10074 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
10076 size
= MIN (size
, UNITS_PER_FPREG
);
10077 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
10079 if (!hard_reg_set_empty_p (left
))
10080 size
= MIN (size
, UNITS_PER_WORD
);
10081 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
10084 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10087 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
10088 enum machine_mode to ATTRIBUTE_UNUSED
,
10089 enum reg_class rclass
)
10091 /* There are several problems with changing the modes of values
10092 in floating-point registers:
10094 - When a multi-word value is stored in paired floating-point
10095 registers, the first register always holds the low word.
10096 We therefore can't allow FPRs to change between single-word
10097 and multi-word modes on big-endian targets.
10099 - GCC assumes that each word of a multiword register can be accessed
10100 individually using SUBREGs. This is not true for floating-point
10101 registers if they are bigger than a word.
10103 - Loading a 32-bit value into a 64-bit floating-point register
10104 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10105 We can't allow FPRs to change from SImode to to a wider mode on
10108 - If the FPU has already interpreted a value in one format, we must
10109 not ask it to treat the value as having a different format.
10111 We therefore disallow all mode changes involving FPRs. */
10112 return reg_classes_intersect_p (FP_REGS
, rclass
);
10115 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10118 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
10123 return TARGET_HARD_FLOAT
;
10126 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
10129 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
10136 /* Implement MODES_TIEABLE_P. */
10139 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
10141 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10142 prefer to put one of them in FPRs. */
10143 return (mode1
== mode2
10144 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
10145 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
10148 /* Implement PREFERRED_RELOAD_CLASS. */
10151 mips_preferred_reload_class (rtx x
, enum reg_class rclass
)
10153 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
10156 if (reg_class_subset_p (FP_REGS
, rclass
)
10157 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
10160 if (reg_class_subset_p (GR_REGS
, rclass
))
10163 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
10169 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10170 Return a "canonical" class to represent it in later calculations. */
10172 static enum reg_class
10173 mips_canonicalize_move_class (enum reg_class rclass
)
10175 /* All moves involving accumulator registers have the same cost. */
10176 if (reg_class_subset_p (rclass
, ACC_REGS
))
10179 /* Likewise promote subclasses of general registers to the most
10180 interesting containing class. */
10181 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
10183 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
10184 rclass
= GENERAL_REGS
;
10189 /* Return the cost of moving a value of mode MODE from a register of
10190 class FROM to a GPR. Return 0 for classes that are unions of other
10191 classes handled by this function. */
10194 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10195 enum reg_class from
)
10200 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10204 /* MFLO and MFHI. */
10212 /* LUI followed by MOVF. */
10218 /* This choice of value is historical. */
10226 /* Return the cost of moving a value of mode MODE from a GPR to a
10227 register of class TO. Return 0 for classes that are unions of
10228 other classes handled by this function. */
10231 mips_move_from_gpr_cost (enum machine_mode mode
, enum reg_class to
)
10236 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10240 /* MTLO and MTHI. */
10248 /* A secondary reload through an FPR scratch. */
10249 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
10250 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
10255 /* This choice of value is historical. */
10263 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10264 maximum of the move costs for subclasses; regclass will work out
10265 the maximum for us. */
10268 mips_register_move_cost (enum machine_mode mode
,
10269 enum reg_class from
, enum reg_class to
)
10271 enum reg_class dregs
;
10274 from
= mips_canonicalize_move_class (from
);
10275 to
= mips_canonicalize_move_class (to
);
10277 /* Handle moves that can be done without using general-purpose registers. */
10278 if (from
== FP_REGS
)
10280 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
10284 /* The sequence generated by mips_expand_fcc_reload. */
10288 /* Handle cases in which only one class deviates from the ideal. */
10289 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
10291 return mips_move_from_gpr_cost (mode
, to
);
10293 return mips_move_to_gpr_cost (mode
, from
);
10295 /* Handles cases that require a GPR temporary. */
10296 cost1
= mips_move_to_gpr_cost (mode
, from
);
10299 cost2
= mips_move_from_gpr_cost (mode
, to
);
10301 return cost1
+ cost2
;
10307 /* Implement TARGET_IRA_COVER_CLASSES. */
10309 static const enum reg_class
*
10310 mips_ira_cover_classes (void)
10312 static const enum reg_class acc_classes
[] = {
10313 GR_AND_ACC_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10314 ST_REGS
, LIM_REG_CLASSES
10316 static const enum reg_class no_acc_classes
[] = {
10317 GR_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10318 ST_REGS
, LIM_REG_CLASSES
10321 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10322 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10323 as a cover class only works well when we keep per-register costs.
10324 Using it when not optimizing can cause us to think accumulators
10325 have the same cost as GPRs in cases where GPRs are actually much
10327 return TARGET_MIPS16
|| !optimize
? no_acc_classes
: acc_classes
;
10330 /* Return the register class required for a secondary register when
10331 copying between one of the registers in RCLASS and value X, which
10332 has mode MODE. X is the source of the move if IN_P, otherwise it
10333 is the destination. Return NO_REGS if no secondary register is
10337 mips_secondary_reload_class (enum reg_class rclass
,
10338 enum machine_mode mode
, rtx x
, bool in_p
)
10342 /* If X is a constant that cannot be loaded into $25, it must be loaded
10343 into some other GPR. No other register class allows a direct move. */
10344 if (mips_dangerous_for_la25_p (x
))
10345 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
10347 regno
= true_regnum (x
);
10350 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10351 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
10357 /* Copying from accumulator registers to anywhere other than a general
10358 register requires a temporary general register. */
10359 if (reg_class_subset_p (rclass
, ACC_REGS
))
10360 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
10361 if (ACC_REG_P (regno
))
10362 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10364 /* We can only copy a value to a condition code register from a
10365 floating-point register, and even then we require a scratch
10366 floating-point register. We can only copy a value out of a
10367 condition-code register into a general register. */
10368 if (reg_class_subset_p (rclass
, ST_REGS
))
10372 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
10374 if (ST_REG_P (regno
))
10378 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10381 if (reg_class_subset_p (rclass
, FP_REGS
))
10384 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
10385 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10386 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10389 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
10390 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10393 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
10394 /* We can force the constant to memory and use lwc1
10395 and ldc1. As above, we will use pairs of lwc1s if
10396 ldc1 is not supported. */
10399 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
10400 /* In this case we can use mov.fmt. */
10403 /* Otherwise, we need to reload through an integer register. */
10406 if (FP_REG_P (regno
))
10407 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10412 /* Implement TARGET_MODE_REP_EXTENDED. */
10415 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
10417 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10418 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
10419 return SIGN_EXTEND
;
10424 /* Implement TARGET_VALID_POINTER_MODE. */
10427 mips_valid_pointer_mode (enum machine_mode mode
)
10429 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
10432 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10435 mips_vector_mode_supported_p (enum machine_mode mode
)
10440 return TARGET_PAIRED_SINGLE_FLOAT
;
10455 return TARGET_LOONGSON_VECTORS
;
10462 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10465 mips_scalar_mode_supported_p (enum machine_mode mode
)
10467 if (ALL_FIXED_POINT_MODE_P (mode
)
10468 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
10471 return default_scalar_mode_supported_p (mode
);
10474 /* Implement TARGET_INIT_LIBFUNCS. */
10476 #include "config/gofast.h"
10479 mips_init_libfuncs (void)
10481 if (TARGET_FIX_VR4120
)
10483 /* Register the special divsi3 and modsi3 functions needed to work
10484 around VR4120 division errata. */
10485 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
10486 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
10489 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
10491 /* Register the MIPS16 -mhard-float stubs. */
10492 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
10493 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
10494 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
10495 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
10497 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
10498 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
10499 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
10500 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
10501 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
10502 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
10503 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
10505 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
10506 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
10507 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
10509 if (TARGET_DOUBLE_FLOAT
)
10511 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
10512 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
10513 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
10514 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
10516 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
10517 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
10518 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
10519 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
10520 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
10521 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
10522 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
10524 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
10525 "__mips16_extendsfdf2");
10526 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
10527 "__mips16_truncdfsf2");
10528 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
10529 "__mips16_fix_truncdfsi");
10530 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
10531 "__mips16_floatsidf");
10532 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
10533 "__mips16_floatunsidf");
10537 /* Register the gofast functions if selected using --enable-gofast. */
10538 gofast_maybe_init_libfuncs ();
10540 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
10541 on an external non-MIPS16 routine to implement __sync_synchronize. */
10543 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
10546 /* Return the length of INSN. LENGTH is the initial length computed by
10547 attributes in the machine-description file. */
10550 mips_adjust_insn_length (rtx insn
, int length
)
10552 /* A unconditional jump has an unfilled delay slot if it is not part
10553 of a sequence. A conditional jump normally has a delay slot, but
10554 does not on MIPS16. */
10555 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
10558 /* See how many nops might be needed to avoid hardware hazards. */
10559 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
10560 switch (get_attr_hazard (insn
))
10574 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
10575 the .md file length attributes are 4-based for both modes.
10576 Adjust the MIPS16 ones here. */
10583 /* Return an asm sequence to start a noat block and load the address
10584 of a label into $1. */
10587 mips_output_load_label (void)
10589 if (TARGET_EXPLICIT_RELOCS
)
10593 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10596 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10599 if (ISA_HAS_LOAD_DELAY
)
10600 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10601 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10605 if (Pmode
== DImode
)
10606 return "%[dla\t%@,%0";
10608 return "%[la\t%@,%0";
10612 /* Return the assembly code for INSN, which has the operands given by
10613 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10614 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10615 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10616 version of BRANCH_IF_TRUE. */
10619 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
10620 const char *branch_if_true
,
10621 const char *branch_if_false
)
10623 unsigned int length
;
10624 rtx taken
, not_taken
;
10626 gcc_assert (LABEL_P (operands
[1]));
10628 length
= get_attr_length (insn
);
10631 /* Just a simple conditional branch. */
10632 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
10633 return branch_if_true
;
10636 /* Generate a reversed branch around a direct jump. This fallback does
10637 not use branch-likely instructions. */
10638 mips_branch_likely
= false;
10639 not_taken
= gen_label_rtx ();
10640 taken
= operands
[1];
10642 /* Generate the reversed branch to NOT_TAKEN. */
10643 operands
[1] = not_taken
;
10644 output_asm_insn (branch_if_false
, operands
);
10646 /* If INSN has a delay slot, we must provide delay slots for both the
10647 branch to NOT_TAKEN and the conditional jump. We must also ensure
10648 that INSN's delay slot is executed in the appropriate cases. */
10649 if (final_sequence
)
10651 /* This first delay slot will always be executed, so use INSN's
10652 delay slot if is not annulled. */
10653 if (!INSN_ANNULLED_BRANCH_P (insn
))
10655 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
10656 asm_out_file
, optimize
, 1, NULL
);
10657 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
10660 output_asm_insn ("nop", 0);
10661 fprintf (asm_out_file
, "\n");
10664 /* Output the unconditional branch to TAKEN. */
10666 output_asm_insn ("j\t%0%/", &taken
);
10669 output_asm_insn (mips_output_load_label (), &taken
);
10670 output_asm_insn ("jr\t%@%]%/", 0);
10673 /* Now deal with its delay slot; see above. */
10674 if (final_sequence
)
10676 /* This delay slot will only be executed if the branch is taken.
10677 Use INSN's delay slot if is annulled. */
10678 if (INSN_ANNULLED_BRANCH_P (insn
))
10680 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
10681 asm_out_file
, optimize
, 1, NULL
);
10682 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
10685 output_asm_insn ("nop", 0);
10686 fprintf (asm_out_file
, "\n");
10689 /* Output NOT_TAKEN. */
10690 targetm
.asm_out
.internal_label (asm_out_file
, "L",
10691 CODE_LABEL_NUMBER (not_taken
));
10695 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10696 if some ordering condition is true. The condition is given by
10697 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10698 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10699 its second is always zero. */
10702 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
10704 const char *branch
[2];
10706 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10707 Make BRANCH[0] branch on the inverse condition. */
10708 switch (GET_CODE (operands
[0]))
10710 /* These cases are equivalent to comparisons against zero. */
10712 inverted_p
= !inverted_p
;
10713 /* Fall through. */
10715 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%1");
10716 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%1");
10719 /* These cases are always true or always false. */
10721 inverted_p
= !inverted_p
;
10722 /* Fall through. */
10724 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%1");
10725 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%1");
10729 branch
[!inverted_p
] = MIPS_BRANCH ("b%C0z", "%2,%1");
10730 branch
[inverted_p
] = MIPS_BRANCH ("b%N0z", "%2,%1");
10733 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
10736 /* Return the assembly code for __sync_*() loop LOOP. The loop should support
10737 both normal and likely branches, using %? and %~ where appropriate. */
10740 mips_output_sync_loop (const char *loop
)
10742 /* Use branch-likely instructions to work around the LL/SC R10000 errata. */
10743 mips_branch_likely
= TARGET_FIX_R10000
;
10747 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
10748 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
10750 When working around R4000 and R4400 errata, we need to make sure that
10751 the division is not immediately followed by a shift[1][2]. We also
10752 need to stop the division from being put into a branch delay slot[3].
10753 The easiest way to avoid both problems is to add a nop after the
10754 division. When a divide-by-zero check is needed, this nop can be
10755 used to fill the branch delay slot.
10757 [1] If a double-word or a variable shift executes immediately
10758 after starting an integer division, the shift may give an
10759 incorrect result. See quotations of errata #16 and #28 from
10760 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10761 in mips.md for details.
10763 [2] A similar bug to [1] exists for all revisions of the
10764 R4000 and the R4400 when run in an MC configuration.
10765 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10767 "19. In this following sequence:
10769 ddiv (or ddivu or div or divu)
10770 dsll32 (or dsrl32, dsra32)
10772 if an MPT stall occurs, while the divide is slipping the cpu
10773 pipeline, then the following double shift would end up with an
10776 Workaround: The compiler needs to avoid generating any
10777 sequence with divide followed by extended double shift."
10779 This erratum is also present in "MIPS R4400MC Errata, Processor
10780 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10781 & 3.0" as errata #10 and #4, respectively.
10783 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10784 (also valid for MIPS R4000MC processors):
10786 "52. R4000SC: This bug does not apply for the R4000PC.
10788 There are two flavors of this bug:
10790 1) If the instruction just after divide takes an RF exception
10791 (tlb-refill, tlb-invalid) and gets an instruction cache
10792 miss (both primary and secondary) and the line which is
10793 currently in secondary cache at this index had the first
10794 data word, where the bits 5..2 are set, then R4000 would
10795 get a wrong result for the div.
10800 ------------------- # end-of page. -tlb-refill
10805 ------------------- # end-of page. -tlb-invalid
10808 2) If the divide is in the taken branch delay slot, where the
10809 target takes RF exception and gets an I-cache miss for the
10810 exception vector or where I-cache miss occurs for the
10811 target address, under the above mentioned scenarios, the
10812 div would get wrong results.
10815 j r2 # to next page mapped or unmapped
10816 div r8,r9 # this bug would be there as long
10817 # as there is an ICache miss and
10818 nop # the "data pattern" is present
10821 beq r0, r0, NextPage # to Next page
10825 This bug is present for div, divu, ddiv, and ddivu
10828 Workaround: For item 1), OS could make sure that the next page
10829 after the divide instruction is also mapped. For item 2), the
10830 compiler could make sure that the divide instruction is not in
10831 the branch delay slot."
10833 These processors have PRId values of 0x00004220 and 0x00004300 for
10834 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10837 mips_output_division (const char *division
, rtx
*operands
)
10842 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
10844 output_asm_insn (s
, operands
);
10847 if (TARGET_CHECK_ZERO_DIV
)
10851 output_asm_insn (s
, operands
);
10852 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
10854 else if (GENERATE_DIVIDE_TRAPS
)
10856 output_asm_insn (s
, operands
);
10857 s
= "teq\t%2,%.,7";
10861 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
10862 output_asm_insn (s
, operands
);
10863 s
= "break\t7%)\n1:";
10869 /* Return true if IN_INSN is a multiply-add or multiply-subtract
10870 instruction and if OUT_INSN assigns to the accumulator operand. */
10873 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
10877 x
= single_set (in_insn
);
10883 if (GET_CODE (x
) == PLUS
10884 && GET_CODE (XEXP (x
, 0)) == MULT
10885 && reg_set_p (XEXP (x
, 1), out_insn
))
10888 if (GET_CODE (x
) == MINUS
10889 && GET_CODE (XEXP (x
, 1)) == MULT
10890 && reg_set_p (XEXP (x
, 0), out_insn
))
10896 /* True if the dependency between OUT_INSN and IN_INSN is on the store
10897 data rather than the address. We need this because the cprestore
10898 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
10899 which causes the default routine to abort. We just return false
10903 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
10905 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
10908 return !store_data_bypass_p (out_insn
, in_insn
);
10912 /* Variables and flags used in scheduler hooks when tuning for
10916 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
10919 /* If true, then next ALU1/2 instruction will go to ALU1. */
10922 /* If true, then next FALU1/2 unstruction will go to FALU1. */
10925 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
10926 int alu1_core_unit_code
;
10927 int alu2_core_unit_code
;
10928 int falu1_core_unit_code
;
10929 int falu2_core_unit_code
;
10931 /* True if current cycle has a multi instruction.
10932 This flag is used in mips_ls2_dfa_post_advance_cycle. */
10933 bool cycle_has_multi_p
;
10935 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
10936 These are used in mips_ls2_dfa_post_advance_cycle to initialize
10938 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
10939 instruction to go ALU1. */
10940 rtx alu1_turn_enabled_insn
;
10941 rtx alu2_turn_enabled_insn
;
10942 rtx falu1_turn_enabled_insn
;
10943 rtx falu2_turn_enabled_insn
;
10946 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10947 dependencies have no cost, except on the 20Kc where output-dependence
10948 is treated like input-dependence. */
10951 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
10952 rtx dep ATTRIBUTE_UNUSED
, int cost
)
10954 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
10957 if (REG_NOTE_KIND (link
) != 0)
10962 /* Return the number of instructions that can be issued per cycle. */
10965 mips_issue_rate (void)
10969 case PROCESSOR_74KC
:
10970 case PROCESSOR_74KF2_1
:
10971 case PROCESSOR_74KF1_1
:
10972 case PROCESSOR_74KF3_2
:
10973 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10974 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10975 but in reality only a maximum of 3 insns can be issued as
10976 floating-point loads and stores also require a slot in the
10978 case PROCESSOR_R10000
:
10979 /* All R10K Processors are quad-issue (being the first MIPS
10980 processors to support this feature). */
10983 case PROCESSOR_20KC
:
10984 case PROCESSOR_R4130
:
10985 case PROCESSOR_R5400
:
10986 case PROCESSOR_R5500
:
10987 case PROCESSOR_R7000
:
10988 case PROCESSOR_R9000
:
10989 case PROCESSOR_OCTEON
:
10992 case PROCESSOR_SB1
:
10993 case PROCESSOR_SB1A
:
10994 /* This is actually 4, but we get better performance if we claim 3.
10995 This is partly because of unwanted speculative code motion with the
10996 larger number, and partly because in most common cases we can't
10997 reach the theoretical max of 4. */
11000 case PROCESSOR_LOONGSON_2E
:
11001 case PROCESSOR_LOONGSON_2F
:
11009 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11012 mips_ls2_init_dfa_post_cycle_insn (void)
11015 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11016 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
11020 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11021 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
11025 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11026 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
11030 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11031 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
11034 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
11035 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
11036 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
11037 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
11040 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11041 Init data used in mips_dfa_post_advance_cycle. */
11044 mips_init_dfa_post_cycle_insn (void)
11046 if (TUNE_LOONGSON_2EF
)
11047 mips_ls2_init_dfa_post_cycle_insn ();
11050 /* Initialize STATE when scheduling for Loongson 2E/2F.
11051 Support round-robin dispatch scheme by enabling only one of
11052 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11056 mips_ls2_dfa_post_advance_cycle (state_t state
)
11058 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
11060 /* Though there are no non-pipelined ALU1 insns,
11061 we can get an instruction of type 'multi' before reload. */
11062 gcc_assert (mips_ls2
.cycle_has_multi_p
);
11063 mips_ls2
.alu1_turn_p
= false;
11066 mips_ls2
.cycle_has_multi_p
= false;
11068 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
11069 /* We have a non-pipelined alu instruction in the core,
11070 adjust round-robin counter. */
11071 mips_ls2
.alu1_turn_p
= true;
11073 if (mips_ls2
.alu1_turn_p
)
11075 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
11076 gcc_unreachable ();
11080 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
11081 gcc_unreachable ();
11084 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
11086 /* There are no non-pipelined FALU1 insns. */
11087 gcc_unreachable ();
11088 mips_ls2
.falu1_turn_p
= false;
11091 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
11092 /* We have a non-pipelined falu instruction in the core,
11093 adjust round-robin counter. */
11094 mips_ls2
.falu1_turn_p
= true;
11096 if (mips_ls2
.falu1_turn_p
)
11098 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
11099 gcc_unreachable ();
11103 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
11104 gcc_unreachable ();
11108 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
11109 This hook is being called at the start of each cycle. */
11112 mips_dfa_post_advance_cycle (void)
11114 if (TUNE_LOONGSON_2EF
)
11115 mips_ls2_dfa_post_advance_cycle (curr_state
);
11118 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11119 be as wide as the scheduling freedom in the DFA. */
11122 mips_multipass_dfa_lookahead (void)
11124 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11128 if (TUNE_LOONGSON_2EF
)
11137 /* Remove the instruction at index LOWER from ready queue READY and
11138 reinsert it in front of the instruction at index HIGHER. LOWER must
11142 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
11147 new_head
= ready
[lower
];
11148 for (i
= lower
; i
< higher
; i
++)
11149 ready
[i
] = ready
[i
+ 1];
11150 ready
[i
] = new_head
;
11153 /* If the priority of the instruction at POS2 in the ready queue READY
11154 is within LIMIT units of that of the instruction at POS1, swap the
11155 instructions if POS2 is not already less than POS1. */
11158 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
11161 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
11165 temp
= ready
[pos1
];
11166 ready
[pos1
] = ready
[pos2
];
11167 ready
[pos2
] = temp
;
11171 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
11172 that may clobber hi or lo. */
11173 static rtx mips_macc_chains_last_hilo
;
11175 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
11176 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
11179 mips_macc_chains_record (rtx insn
)
11181 if (get_attr_may_clobber_hilo (insn
))
11182 mips_macc_chains_last_hilo
= insn
;
11185 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
11186 has NREADY elements, looking for a multiply-add or multiply-subtract
11187 instruction that is cumulative with mips_macc_chains_last_hilo.
11188 If there is one, promote it ahead of anything else that might
11189 clobber hi or lo. */
11192 mips_macc_chains_reorder (rtx
*ready
, int nready
)
11196 if (mips_macc_chains_last_hilo
!= 0)
11197 for (i
= nready
- 1; i
>= 0; i
--)
11198 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
11200 for (j
= nready
- 1; j
> i
; j
--)
11201 if (recog_memoized (ready
[j
]) >= 0
11202 && get_attr_may_clobber_hilo (ready
[j
]))
11204 mips_promote_ready (ready
, i
, j
);
11211 /* The last instruction to be scheduled. */
11212 static rtx vr4130_last_insn
;
11214 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
11215 points to an rtx that is initially an instruction. Nullify the rtx
11216 if the instruction uses the value of register X. */
11219 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
11224 insn_ptr
= (rtx
*) data
;
11227 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
11231 /* Return true if there is true register dependence between vr4130_last_insn
11235 vr4130_true_reg_dependence_p (rtx insn
)
11237 note_stores (PATTERN (vr4130_last_insn
),
11238 vr4130_true_reg_dependence_p_1
, &insn
);
11242 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
11243 the ready queue and that INSN2 is the instruction after it, return
11244 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
11245 in which INSN1 and INSN2 can probably issue in parallel, but for
11246 which (INSN2, INSN1) should be less sensitive to instruction
11247 alignment than (INSN1, INSN2). See 4130.md for more details. */
11250 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
11252 sd_iterator_def sd_it
;
11255 /* Check for the following case:
11257 1) there is some other instruction X with an anti dependence on INSN1;
11258 2) X has a higher priority than INSN2; and
11259 3) X is an arithmetic instruction (and thus has no unit restrictions).
11261 If INSN1 is the last instruction blocking X, it would better to
11262 choose (INSN1, X) over (INSN2, INSN1). */
11263 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
11264 if (DEP_TYPE (dep
) == REG_DEP_ANTI
11265 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
11266 && recog_memoized (DEP_CON (dep
)) >= 0
11267 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
11270 if (vr4130_last_insn
!= 0
11271 && recog_memoized (insn1
) >= 0
11272 && recog_memoized (insn2
) >= 0)
11274 /* See whether INSN1 and INSN2 use different execution units,
11275 or if they are both ALU-type instructions. If so, they can
11276 probably execute in parallel. */
11277 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
11278 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
11279 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
11281 /* If only one of the instructions has a dependence on
11282 vr4130_last_insn, prefer to schedule the other one first. */
11283 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
11284 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
11285 if (dep1_p
!= dep2_p
)
11288 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
11289 is not an ALU-type instruction and if INSN1 uses the same
11290 execution unit. (Note that if this condition holds, we already
11291 know that INSN2 uses a different execution unit.) */
11292 if (class1
!= VR4130_CLASS_ALU
11293 && recog_memoized (vr4130_last_insn
) >= 0
11294 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
11301 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
11302 queue with at least two instructions. Swap the first two if
11303 vr4130_swap_insns_p says that it could be worthwhile. */
11306 vr4130_reorder (rtx
*ready
, int nready
)
11308 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
11309 mips_promote_ready (ready
, nready
- 2, nready
- 1);
11312 /* Record whether last 74k AGEN instruction was a load or store. */
11313 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
11315 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
11316 resets to TYPE_UNKNOWN state. */
11319 mips_74k_agen_init (rtx insn
)
11321 if (!insn
|| !NONJUMP_INSN_P (insn
))
11322 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
11325 enum attr_type type
= get_attr_type (insn
);
11326 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
11327 mips_last_74k_agen_insn
= type
;
11331 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
11332 loads to be grouped together, and multiple stores to be grouped
11333 together. Swap things around in the ready queue to make this happen. */
11336 mips_74k_agen_reorder (rtx
*ready
, int nready
)
11339 int store_pos
, load_pos
;
11344 for (i
= nready
- 1; i
>= 0; i
--)
11346 rtx insn
= ready
[i
];
11347 if (USEFUL_INSN_P (insn
))
11348 switch (get_attr_type (insn
))
11351 if (store_pos
== -1)
11356 if (load_pos
== -1)
11365 if (load_pos
== -1 || store_pos
== -1)
11368 switch (mips_last_74k_agen_insn
)
11371 /* Prefer to schedule loads since they have a higher latency. */
11373 /* Swap loads to the front of the queue. */
11374 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
11377 /* Swap stores to the front of the queue. */
11378 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
11385 /* Implement TARGET_SCHED_INIT. */
11388 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
11389 int max_ready ATTRIBUTE_UNUSED
)
11391 mips_macc_chains_last_hilo
= 0;
11392 vr4130_last_insn
= 0;
11393 mips_74k_agen_init (NULL_RTX
);
11395 /* When scheduling for Loongson2, branch instructions go to ALU1,
11396 therefore basic block is most likely to start with round-robin counter
11397 pointed to ALU2. */
11398 mips_ls2
.alu1_turn_p
= false;
11399 mips_ls2
.falu1_turn_p
= true;
11402 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
11405 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
11406 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
11408 if (!reload_completed
11409 && TUNE_MACC_CHAINS
11411 mips_macc_chains_reorder (ready
, *nreadyp
);
11413 if (reload_completed
11415 && !TARGET_VR4130_ALIGN
11417 vr4130_reorder (ready
, *nreadyp
);
11420 mips_74k_agen_reorder (ready
, *nreadyp
);
11422 return mips_issue_rate ();
11425 /* Update round-robin counters for ALU1/2 and FALU1/2. */
11428 mips_ls2_variable_issue (rtx insn
)
11430 if (mips_ls2
.alu1_turn_p
)
11432 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
11433 mips_ls2
.alu1_turn_p
= false;
11437 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
11438 mips_ls2
.alu1_turn_p
= true;
11441 if (mips_ls2
.falu1_turn_p
)
11443 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
11444 mips_ls2
.falu1_turn_p
= false;
11448 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
11449 mips_ls2
.falu1_turn_p
= true;
11452 if (recog_memoized (insn
) >= 0)
11453 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
11456 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11459 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
11460 rtx insn
, int more
)
11462 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
11463 if (USEFUL_INSN_P (insn
))
11466 if (!reload_completed
&& TUNE_MACC_CHAINS
)
11467 mips_macc_chains_record (insn
);
11468 vr4130_last_insn
= insn
;
11470 mips_74k_agen_init (insn
);
11471 else if (TUNE_LOONGSON_2EF
)
11472 mips_ls2_variable_issue (insn
);
11475 /* Instructions of type 'multi' should all be split before
11476 the second scheduling pass. */
11477 gcc_assert (!reload_completed
11478 || recog_memoized (insn
) < 0
11479 || get_attr_type (insn
) != TYPE_MULTI
);
11484 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11485 return the first operand of the associated PREF or PREFX insn. */
11488 mips_prefetch_cookie (rtx write
, rtx locality
)
11490 /* store_streamed / load_streamed. */
11491 if (INTVAL (locality
) <= 0)
11492 return GEN_INT (INTVAL (write
) + 4);
11494 /* store / load. */
11495 if (INTVAL (locality
) <= 2)
11498 /* store_retained / load_retained. */
11499 return GEN_INT (INTVAL (write
) + 6);
11502 /* Flags that indicate when a built-in function is available.
11504 BUILTIN_AVAIL_NON_MIPS16
11505 The function is available on the current target, but only
11506 in non-MIPS16 mode. */
11507 #define BUILTIN_AVAIL_NON_MIPS16 1
11509 /* Declare an availability predicate for built-in functions that
11510 require non-MIPS16 mode and also require COND to be true.
11511 NAME is the main part of the predicate's name. */
11512 #define AVAIL_NON_MIPS16(NAME, COND) \
11513 static unsigned int \
11514 mips_builtin_avail_##NAME (void) \
11516 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
11519 /* This structure describes a single built-in function. */
11520 struct mips_builtin_description
{
11521 /* The code of the main .md file instruction. See mips_builtin_type
11522 for more information. */
11523 enum insn_code icode
;
11525 /* The floating-point comparison code to use with ICODE, if any. */
11526 enum mips_fp_condition cond
;
11528 /* The name of the built-in function. */
11531 /* Specifies how the function should be expanded. */
11532 enum mips_builtin_type builtin_type
;
11534 /* The function's prototype. */
11535 enum mips_function_type function_type
;
11537 /* Whether the function is available. */
11538 unsigned int (*avail
) (void);
11541 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
11542 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
11543 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
11544 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
11545 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
11546 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
11547 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
11548 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
11549 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
11551 /* Construct a mips_builtin_description from the given arguments.
11553 INSN is the name of the associated instruction pattern, without the
11554 leading CODE_FOR_mips_.
11556 CODE is the floating-point condition code associated with the
11557 function. It can be 'f' if the field is not applicable.
11559 NAME is the name of the function itself, without the leading
11562 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
11564 AVAIL is the name of the availability predicate, without the leading
11565 mips_builtin_avail_. */
11566 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
11567 FUNCTION_TYPE, AVAIL) \
11568 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
11569 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
11570 mips_builtin_avail_ ## AVAIL }
11572 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
11573 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
11574 are as for MIPS_BUILTIN. */
11575 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11576 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
11578 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
11579 are subject to mips_builtin_avail_<AVAIL>. */
11580 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
11581 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
11582 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
11583 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
11584 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
11586 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11587 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
11588 while the any and all forms are subject to mips_builtin_avail_mips3d. */
11589 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
11590 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
11591 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
11593 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
11594 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
11596 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
11597 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
11599 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
11600 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
11603 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11604 are subject to mips_builtin_avail_mips3d. */
11605 #define CMP_4S_BUILTINS(INSN, COND) \
11606 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
11607 MIPS_BUILTIN_CMP_ANY, \
11608 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
11609 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
11610 MIPS_BUILTIN_CMP_ALL, \
11611 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
11613 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11614 instruction requires mips_builtin_avail_<AVAIL>. */
11615 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
11616 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
11617 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11619 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
11620 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11623 /* Define all the built-in functions related to C.cond.fmt condition COND. */
11624 #define CMP_BUILTINS(COND) \
11625 MOVTF_BUILTINS (c, COND, paired_single), \
11626 MOVTF_BUILTINS (cabs, COND, mips3d), \
11627 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
11628 CMP_PS_BUILTINS (c, COND, paired_single), \
11629 CMP_PS_BUILTINS (cabs, COND, mips3d), \
11630 CMP_4S_BUILTINS (c, COND), \
11631 CMP_4S_BUILTINS (cabs, COND)
11633 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
11634 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
11635 and AVAIL are as for MIPS_BUILTIN. */
11636 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11637 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
11638 FUNCTION_TYPE, AVAIL)
11640 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11641 branch instruction. AVAIL is as for MIPS_BUILTIN. */
11642 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
11643 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
11644 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
11646 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
11647 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11648 builtin_description field. */
11649 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
11650 { CODE_FOR_loongson_ ## INSN, 0, "__builtin_loongson_" #FN_NAME, \
11651 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_loongson }
11653 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
11654 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11655 builtin_description field. */
11656 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
11657 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
11659 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
11660 We use functions of this form when the same insn can be usefully applied
11661 to more than one datatype. */
11662 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
11663 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
11665 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11666 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11667 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11668 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11669 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11670 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11672 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
11673 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
11674 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
11675 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
11676 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
11677 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
11678 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
11679 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
11680 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
11681 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
11682 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
11683 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
11684 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
11685 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
11686 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
11687 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
11688 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
11689 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
11690 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
11691 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
11692 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
11693 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
11694 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
11695 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
11696 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
11697 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
11698 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
11699 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
11700 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
11702 static const struct mips_builtin_description mips_builtins
[] = {
11703 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
11704 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
11705 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
11706 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
11707 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
11708 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
11709 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
11710 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
11712 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
11713 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
11714 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
11715 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
11716 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
11718 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
11719 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
11720 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
11721 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
11722 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
11723 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
11725 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
11726 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
11727 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
11728 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
11729 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
11730 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
11732 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
11734 /* Built-in functions for the SB-1 processor. */
11735 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
11737 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
11738 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11739 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11740 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11741 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
11742 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
11743 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11744 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11745 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11746 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
11747 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
11748 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11749 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11750 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11751 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
11752 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
11753 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
11754 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
11755 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
11756 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
11757 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
11758 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
11759 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
11760 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11761 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11762 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11763 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11764 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11765 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11766 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11767 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
11768 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
11769 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
11770 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
11771 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11772 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
11773 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
11774 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
11775 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11776 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
11777 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
11778 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11779 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
11780 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
11781 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
11782 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
11783 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
11784 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
11785 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
11786 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
11787 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
11788 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
11789 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
11790 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
11791 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
11792 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
11793 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
11794 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
11795 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11796 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
11797 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
11798 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
11799 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
11800 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
11801 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
11802 BPOSGE_BUILTIN (32, dsp
),
11804 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
11805 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
11806 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11807 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11808 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
11809 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
11810 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
11811 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
11812 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
11813 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
11814 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
11815 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11816 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11817 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11818 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11819 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11820 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
11821 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
11822 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
11823 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
11824 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
11825 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
11826 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
11827 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11828 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11829 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
11830 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
11831 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11832 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11833 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11834 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11835 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11836 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
11837 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11838 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
11840 /* Built-in functions for the DSP ASE (32-bit only). */
11841 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
11842 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
11843 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
11844 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
11845 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11846 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11847 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11848 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
11849 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
11850 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11851 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11852 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11853 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
11854 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11855 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11856 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11857 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11858 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11859 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
11860 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
11861 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
11863 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
11864 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11865 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11866 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dspr2_32
),
11867 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dspr2_32
),
11868 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dspr2_32
),
11869 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dspr2_32
),
11870 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11871 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dspr2_32
),
11872 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dspr2_32
),
11873 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11874 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11875 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11876 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11877 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11878 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
11880 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
11881 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
11882 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
11883 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
11884 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11885 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11886 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11887 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11888 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11889 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11890 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
11891 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
11892 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11893 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11894 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11895 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11896 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
11897 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11898 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11899 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11900 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
11901 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11902 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11903 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11904 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11905 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11906 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11907 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11908 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11909 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11910 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11911 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11912 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11913 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11914 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11915 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11916 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11917 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11918 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
11919 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
11920 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11921 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11922 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11923 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11924 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11925 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11926 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11927 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11928 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
11929 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11930 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11931 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11932 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11933 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
11934 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
11935 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11936 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11937 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11938 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
11939 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11940 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
11941 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
11942 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI
),
11943 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI
),
11944 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
11945 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
11946 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
11947 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
11948 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
11949 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
11950 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
11951 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
11952 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
11953 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
11954 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
11955 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
11956 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11957 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11958 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11959 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11960 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11961 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11962 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
11963 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
11964 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11965 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11966 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11967 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11968 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11969 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11970 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11971 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11972 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11973 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11974 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
11975 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
11976 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
11977 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
11978 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
11979 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
11981 /* Sundry other built-in functions. */
11982 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
11985 /* MODE is a vector mode whose elements have type TYPE. Return the type
11986 of the vector itself. */
11989 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
11991 static tree types
[2 * (int) MAX_MACHINE_MODE
];
11994 mode_index
= (int) mode
;
11996 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
11997 mode_index
+= MAX_MACHINE_MODE
;
11999 if (types
[mode_index
] == NULL_TREE
)
12000 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
12001 return types
[mode_index
];
12004 /* Return a type for 'const volatile void *'. */
12007 mips_build_cvpointer_type (void)
12011 if (cache
== NULL_TREE
)
12012 cache
= build_pointer_type (build_qualified_type
12014 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
12018 /* Source-level argument types. */
12019 #define MIPS_ATYPE_VOID void_type_node
12020 #define MIPS_ATYPE_INT integer_type_node
12021 #define MIPS_ATYPE_POINTER ptr_type_node
12022 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12024 /* Standard mode-based argument types. */
12025 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12026 #define MIPS_ATYPE_SI intSI_type_node
12027 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12028 #define MIPS_ATYPE_DI intDI_type_node
12029 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12030 #define MIPS_ATYPE_SF float_type_node
12031 #define MIPS_ATYPE_DF double_type_node
12033 /* Vector argument types. */
12034 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12035 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12036 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12037 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12038 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12039 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12040 #define MIPS_ATYPE_UV2SI \
12041 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12042 #define MIPS_ATYPE_UV4HI \
12043 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12044 #define MIPS_ATYPE_UV8QI \
12045 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12047 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12048 their associated MIPS_ATYPEs. */
12049 #define MIPS_FTYPE_ATYPES1(A, B) \
12050 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12052 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12053 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12055 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12056 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12058 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12059 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12062 /* Return the function type associated with function prototype TYPE. */
12065 mips_build_function_type (enum mips_function_type type
)
12067 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
12069 if (types
[(int) type
] == NULL_TREE
)
12072 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12073 case MIPS_FTYPE_NAME##NUM ARGS: \
12074 types[(int) type] \
12075 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12078 #include "config/mips/mips-ftypes.def"
12079 #undef DEF_MIPS_FTYPE
12081 gcc_unreachable ();
12084 return types
[(int) type
];
12087 /* Implement TARGET_INIT_BUILTINS. */
12090 mips_init_builtins (void)
12092 const struct mips_builtin_description
*d
;
12095 /* Iterate through all of the bdesc arrays, initializing all of the
12096 builtin functions. */
12097 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
12099 d
= &mips_builtins
[i
];
12101 add_builtin_function (d
->name
,
12102 mips_build_function_type (d
->function_type
),
12103 i
, BUILT_IN_MD
, NULL
, NULL
);
12107 /* Take argument ARGNO from EXP's argument list and convert it into a
12108 form suitable for input operand OPNO of instruction ICODE. Return the
12112 mips_prepare_builtin_arg (enum insn_code icode
,
12113 unsigned int opno
, tree exp
, unsigned int argno
)
12117 enum machine_mode mode
;
12119 arg
= CALL_EXPR_ARG (exp
, argno
);
12120 value
= expand_normal (arg
);
12121 mode
= insn_data
[icode
].operand
[opno
].mode
;
12122 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
12124 /* We need to get the mode from ARG for two reasons:
12126 - to cope with address operands, where MODE is the mode of the
12127 memory, rather than of VALUE itself.
12129 - to cope with special predicates like pmode_register_operand,
12130 where MODE is VOIDmode. */
12131 value
= copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg
)), value
);
12133 /* Check the predicate again. */
12134 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
12136 error ("invalid argument to built-in function");
12144 /* Return an rtx suitable for output operand OP of instruction ICODE.
12145 If TARGET is non-null, try to use it where possible. */
12148 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
12150 enum machine_mode mode
;
12152 mode
= insn_data
[icode
].operand
[op
].mode
;
12153 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
12154 target
= gen_reg_rtx (mode
);
12159 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
12160 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
12161 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
12162 suggests a good place to put the result. */
12165 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
12168 rtx ops
[MAX_RECOG_OPERANDS
];
12171 /* Map any target to operand 0. */
12175 target
= mips_prepare_builtin_target (icode
, opno
, target
);
12176 ops
[opno
] = target
;
12180 /* Map the arguments to the other operands. The n_operands value
12181 for an expander includes match_dups and match_scratches as well as
12182 match_operands, so n_operands is only an upper bound on the number
12183 of arguments to the expander function. */
12184 gcc_assert (opno
+ call_expr_nargs (exp
) <= insn_data
[icode
].n_operands
);
12185 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++, opno
++)
12186 ops
[opno
] = mips_prepare_builtin_arg (icode
, opno
, exp
, argno
);
12191 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
12195 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
12199 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
12203 gcc_unreachable ();
12208 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
12209 function; TYPE says which. EXP is the CALL_EXPR that calls the
12210 function, ICODE is the instruction that should be used to compare
12211 the first two arguments, and COND is the condition it should test.
12212 TARGET, if nonnull, suggests a good place to put the result. */
12215 mips_expand_builtin_movtf (enum mips_builtin_type type
,
12216 enum insn_code icode
, enum mips_fp_condition cond
,
12217 rtx target
, tree exp
)
12219 rtx cmp_result
, op0
, op1
;
12221 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
12222 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
12223 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
12224 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
12226 icode
= CODE_FOR_mips_cond_move_tf_ps
;
12227 target
= mips_prepare_builtin_target (icode
, 0, target
);
12228 if (type
== MIPS_BUILTIN_MOVT
)
12230 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
12231 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
12235 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
12236 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
12238 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
12242 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
12243 into TARGET otherwise. Return TARGET. */
12246 mips_builtin_branch_and_move (rtx condition
, rtx target
,
12247 rtx value_if_true
, rtx value_if_false
)
12249 rtx true_label
, done_label
;
12251 true_label
= gen_label_rtx ();
12252 done_label
= gen_label_rtx ();
12254 /* First assume that CONDITION is false. */
12255 mips_emit_move (target
, value_if_false
);
12257 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
12258 emit_jump_insn (gen_condjump (condition
, true_label
));
12259 emit_jump_insn (gen_jump (done_label
));
12262 /* Fix TARGET if CONDITION is true. */
12263 emit_label (true_label
);
12264 mips_emit_move (target
, value_if_true
);
12266 emit_label (done_label
);
12270 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
12271 the CALL_EXPR that calls the function, ICODE is the code of the
12272 comparison instruction, and COND is the condition it should test.
12273 TARGET, if nonnull, suggests a good place to put the boolean result. */
12276 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
12277 enum insn_code icode
, enum mips_fp_condition cond
,
12278 rtx target
, tree exp
)
12280 rtx offset
, condition
, cmp_result
, args
[MAX_RECOG_OPERANDS
];
12283 if (target
== 0 || GET_MODE (target
) != SImode
)
12284 target
= gen_reg_rtx (SImode
);
12286 /* The instruction should have a target operand, an operand for each
12287 argument, and an operand for COND. */
12288 gcc_assert (call_expr_nargs (exp
) + 2 == insn_data
[icode
].n_operands
);
12290 /* Prepare the operands to the comparison. */
12291 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
12292 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
12293 args
[argno
] = mips_prepare_builtin_arg (icode
, argno
+ 1, exp
, argno
);
12295 switch (insn_data
[icode
].n_operands
)
12298 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
12303 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
12304 args
[2], args
[3], GEN_INT (cond
)));
12308 gcc_unreachable ();
12311 /* If the comparison sets more than one register, we define the result
12312 to be 0 if all registers are false and -1 if all registers are true.
12313 The value of the complete result is indeterminate otherwise. */
12314 switch (builtin_type
)
12316 case MIPS_BUILTIN_CMP_ALL
:
12317 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
12318 return mips_builtin_branch_and_move (condition
, target
,
12319 const0_rtx
, const1_rtx
);
12321 case MIPS_BUILTIN_CMP_UPPER
:
12322 case MIPS_BUILTIN_CMP_LOWER
:
12323 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
12324 condition
= gen_single_cc (cmp_result
, offset
);
12325 return mips_builtin_branch_and_move (condition
, target
,
12326 const1_rtx
, const0_rtx
);
12329 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
12330 return mips_builtin_branch_and_move (condition
, target
,
12331 const1_rtx
, const0_rtx
);
12335 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
12336 if nonnull, suggests a good place to put the boolean result. */
12339 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
12341 rtx condition
, cmp_result
;
12344 if (target
== 0 || GET_MODE (target
) != SImode
)
12345 target
= gen_reg_rtx (SImode
);
12347 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
12349 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
12354 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
12355 return mips_builtin_branch_and_move (condition
, target
,
12356 const1_rtx
, const0_rtx
);
12359 /* Implement TARGET_EXPAND_BUILTIN. */
12362 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
12363 enum machine_mode mode
, int ignore
)
12366 unsigned int fcode
, avail
;
12367 const struct mips_builtin_description
*d
;
12369 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12370 fcode
= DECL_FUNCTION_CODE (fndecl
);
12371 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
12372 d
= &mips_builtins
[fcode
];
12373 avail
= d
->avail ();
12374 gcc_assert (avail
!= 0);
12377 error ("built-in function %qs not supported for MIPS16",
12378 IDENTIFIER_POINTER (DECL_NAME (fndecl
)));
12379 return ignore
? const0_rtx
: CONST0_RTX (mode
);
12381 switch (d
->builtin_type
)
12383 case MIPS_BUILTIN_DIRECT
:
12384 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
12386 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
12387 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
12389 case MIPS_BUILTIN_MOVT
:
12390 case MIPS_BUILTIN_MOVF
:
12391 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
12392 d
->cond
, target
, exp
);
12394 case MIPS_BUILTIN_CMP_ANY
:
12395 case MIPS_BUILTIN_CMP_ALL
:
12396 case MIPS_BUILTIN_CMP_UPPER
:
12397 case MIPS_BUILTIN_CMP_LOWER
:
12398 case MIPS_BUILTIN_CMP_SINGLE
:
12399 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
12400 d
->cond
, target
, exp
);
12402 case MIPS_BUILTIN_BPOSGE32
:
12403 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
12405 gcc_unreachable ();
12408 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
12409 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
12410 struct mips16_constant
{
12411 struct mips16_constant
*next
;
12414 enum machine_mode mode
;
12417 /* Information about an incomplete MIPS16 constant pool. FIRST is the
12418 first constant, HIGHEST_ADDRESS is the highest address that the first
12419 byte of the pool can have, and INSN_ADDRESS is the current instruction
12421 struct mips16_constant_pool
{
12422 struct mips16_constant
*first
;
12423 int highest_address
;
12427 /* Add constant VALUE to POOL and return its label. MODE is the
12428 value's mode (used for CONST_INTs, etc.). */
12431 mips16_add_constant (struct mips16_constant_pool
*pool
,
12432 rtx value
, enum machine_mode mode
)
12434 struct mips16_constant
**p
, *c
;
12435 bool first_of_size_p
;
12437 /* See whether the constant is already in the pool. If so, return the
12438 existing label, otherwise leave P pointing to the place where the
12439 constant should be added.
12441 Keep the pool sorted in increasing order of mode size so that we can
12442 reduce the number of alignments needed. */
12443 first_of_size_p
= true;
12444 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
12446 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
12447 return (*p
)->label
;
12448 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
12450 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
12451 first_of_size_p
= false;
12454 /* In the worst case, the constant needed by the earliest instruction
12455 will end up at the end of the pool. The entire pool must then be
12456 accessible from that instruction.
12458 When adding the first constant, set the pool's highest address to
12459 the address of the first out-of-range byte. Adjust this address
12460 downwards each time a new constant is added. */
12461 if (pool
->first
== 0)
12462 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
12463 of the instruction with the lowest two bits clear. The base PC
12464 value for LDPC has the lowest three bits clear. Assume the worst
12465 case here; namely that the PC-relative instruction occupies the
12466 last 2 bytes in an aligned word. */
12467 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
12468 pool
->highest_address
-= GET_MODE_SIZE (mode
);
12469 if (first_of_size_p
)
12470 /* Take into account the worst possible padding due to alignment. */
12471 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
12473 /* Create a new entry. */
12474 c
= XNEW (struct mips16_constant
);
12477 c
->label
= gen_label_rtx ();
12484 /* Output constant VALUE after instruction INSN and return the last
12485 instruction emitted. MODE is the mode of the constant. */
12488 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
12490 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
12492 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
12493 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
12496 if (SCALAR_FLOAT_MODE_P (mode
))
12497 return emit_insn_after (gen_consttable_float (value
), insn
);
12499 if (VECTOR_MODE_P (mode
))
12503 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
12504 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
12505 CONST_VECTOR_ELT (value
, i
), insn
);
12509 gcc_unreachable ();
12512 /* Dump out the constants in CONSTANTS after INSN. */
12515 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
12517 struct mips16_constant
*c
, *next
;
12521 for (c
= constants
; c
!= NULL
; c
= next
)
12523 /* If necessary, increase the alignment of PC. */
12524 if (align
< GET_MODE_SIZE (c
->mode
))
12526 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
12527 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
12529 align
= GET_MODE_SIZE (c
->mode
);
12531 insn
= emit_label_after (c
->label
, insn
);
12532 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
12538 emit_barrier_after (insn
);
12541 /* Return the length of instruction INSN. */
12544 mips16_insn_length (rtx insn
)
12548 rtx body
= PATTERN (insn
);
12549 if (GET_CODE (body
) == ADDR_VEC
)
12550 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
12551 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
12552 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
12554 return get_attr_length (insn
);
12557 /* If *X is a symbolic constant that refers to the constant pool, add
12558 the constant to POOL and rewrite *X to use the constant's label. */
12561 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
12563 rtx base
, offset
, label
;
12565 split_const (*x
, &base
, &offset
);
12566 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
12568 label
= mips16_add_constant (pool
, get_pool_constant (base
),
12569 get_pool_mode (base
));
12570 base
= gen_rtx_LABEL_REF (Pmode
, label
);
12571 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
12575 /* This structure is used to communicate with mips16_rewrite_pool_refs.
12576 INSN is the instruction we're rewriting and POOL points to the current
12578 struct mips16_rewrite_pool_refs_info
{
12580 struct mips16_constant_pool
*pool
;
12583 /* Rewrite *X so that constant pool references refer to the constant's
12584 label instead. DATA points to a mips16_rewrite_pool_refs_info
12588 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
12590 struct mips16_rewrite_pool_refs_info
*info
=
12591 (struct mips16_rewrite_pool_refs_info
*) data
;
12593 if (force_to_mem_operand (*x
, Pmode
))
12595 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
12596 validate_change (info
->insn
, x
, mem
, false);
12601 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
12605 if (TARGET_MIPS16_TEXT_LOADS
)
12606 mips16_rewrite_pool_constant (info
->pool
, x
);
12608 return GET_CODE (*x
) == CONST
? -1 : 0;
12611 /* Build MIPS16 constant pools. */
12614 mips16_lay_out_constants (void)
12616 struct mips16_constant_pool pool
;
12617 struct mips16_rewrite_pool_refs_info info
;
12620 if (!TARGET_MIPS16_PCREL_LOADS
)
12623 split_all_insns_noflow ();
12625 memset (&pool
, 0, sizeof (pool
));
12626 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
12628 /* Rewrite constant pool references in INSN. */
12633 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
12636 pool
.insn_address
+= mips16_insn_length (insn
);
12638 if (pool
.first
!= NULL
)
12640 /* If there are no natural barriers between the first user of
12641 the pool and the highest acceptable address, we'll need to
12642 create a new instruction to jump around the constant pool.
12643 In the worst case, this instruction will be 4 bytes long.
12645 If it's too late to do this transformation after INSN,
12646 do it immediately before INSN. */
12647 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
12651 label
= gen_label_rtx ();
12653 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
12654 JUMP_LABEL (jump
) = label
;
12655 LABEL_NUSES (label
) = 1;
12656 barrier
= emit_barrier_after (jump
);
12658 emit_label_after (label
, barrier
);
12659 pool
.insn_address
+= 4;
12662 /* See whether the constant pool is now out of range of the first
12663 user. If so, output the constants after the previous barrier.
12664 Note that any instructions between BARRIER and INSN (inclusive)
12665 will use negative offsets to refer to the pool. */
12666 if (pool
.insn_address
> pool
.highest_address
)
12668 mips16_emit_constants (pool
.first
, barrier
);
12672 else if (BARRIER_P (insn
))
12676 mips16_emit_constants (pool
.first
, get_last_insn ());
12679 /* Return true if it is worth r10k_simplify_address's while replacing
12680 an address with X. We are looking for constants, and for addresses
12681 at a known offset from the incoming stack pointer. */
12684 r10k_simplified_address_p (rtx x
)
12686 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
12688 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
12691 /* X is an expression that appears in INSN. Try to use the UD chains
12692 to simplify it, returning the simplified form on success and the
12693 original form otherwise. Replace the incoming value of $sp with
12694 virtual_incoming_args_rtx (which should never occur in X otherwise). */
12697 r10k_simplify_address (rtx x
, rtx insn
)
12699 rtx newx
, op0
, op1
, set
, def_insn
, note
;
12701 struct df_link
*defs
;
12706 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
12707 if (op0
!= XEXP (x
, 0))
12708 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
12709 op0
, GET_MODE (XEXP (x
, 0)));
12711 else if (BINARY_P (x
))
12713 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
12714 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
12715 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
12716 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
12718 else if (GET_CODE (x
) == LO_SUM
)
12720 /* LO_SUMs can be offset from HIGHs, if we know they won't
12721 overflow. See mips_classify_address for the rationale behind
12723 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
12724 if (GET_CODE (op0
) == HIGH
)
12725 newx
= XEXP (x
, 1);
12727 else if (REG_P (x
))
12729 /* Uses are recorded by regno_reg_rtx, not X itself. */
12730 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
12732 defs
= DF_REF_CHAIN (use
);
12734 /* Require a single definition. */
12735 if (defs
&& defs
->next
== NULL
)
12738 if (DF_REF_IS_ARTIFICIAL (def
))
12740 /* Replace the incoming value of $sp with
12741 virtual_incoming_args_rtx. */
12742 if (x
== stack_pointer_rtx
12743 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
12744 newx
= virtual_incoming_args_rtx
;
12746 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
12749 /* Make sure that DEF_INSN is a single set of REG. */
12750 def_insn
= DF_REF_INSN (def
);
12751 if (NONJUMP_INSN_P (def_insn
))
12753 set
= single_set (def_insn
);
12754 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
12756 /* Prefer to use notes, since the def-use chains
12757 are often shorter. */
12758 note
= find_reg_equal_equiv_note (def_insn
);
12760 newx
= XEXP (note
, 0);
12762 newx
= SET_SRC (set
);
12763 newx
= r10k_simplify_address (newx
, def_insn
);
12769 if (newx
&& r10k_simplified_address_p (newx
))
12774 /* Return true if ADDRESS is known to be an uncached address
12775 on R10K systems. */
12778 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
12780 unsigned HOST_WIDE_INT upper
;
12782 /* Check for KSEG1. */
12783 if (address
+ 0x60000000 < 0x20000000)
12786 /* Check for uncached XKPHYS addresses. */
12787 if (Pmode
== DImode
)
12789 upper
= (address
>> 40) & 0xf9ffff;
12790 if (upper
== 0x900000 || upper
== 0xb80000)
12796 /* Return true if we can prove that an access to address X in instruction
12797 INSN would be safe from R10K speculation. This X is a general
12798 expression; it might not be a legitimate address. */
12801 r10k_safe_address_p (rtx x
, rtx insn
)
12804 HOST_WIDE_INT offset_val
;
12806 x
= r10k_simplify_address (x
, insn
);
12808 /* Check for references to the stack frame. It doesn't really matter
12809 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
12810 allows us to assume that accesses to any part of the eventual frame
12811 is safe from speculation at any point in the function. */
12812 mips_split_plus (x
, &base
, &offset_val
);
12813 if (base
== virtual_incoming_args_rtx
12814 && offset_val
>= -cfun
->machine
->frame
.total_size
12815 && offset_val
< cfun
->machine
->frame
.args_size
)
12818 /* Check for uncached addresses. */
12819 if (CONST_INT_P (x
))
12820 return r10k_uncached_address_p (INTVAL (x
));
12822 /* Check for accesses to a static object. */
12823 split_const (x
, &base
, &offset
);
12824 return offset_within_block_p (base
, INTVAL (offset
));
12827 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
12828 an in-range access to an automatic variable, or to an object with
12829 a link-time-constant address. */
12832 r10k_safe_mem_expr_p (tree expr
, rtx offset
)
12834 if (expr
== NULL_TREE
12835 || offset
== NULL_RTX
12836 || !CONST_INT_P (offset
)
12837 || INTVAL (offset
) < 0
12838 || INTVAL (offset
) >= int_size_in_bytes (TREE_TYPE (expr
)))
12841 while (TREE_CODE (expr
) == COMPONENT_REF
)
12843 expr
= TREE_OPERAND (expr
, 0);
12844 if (expr
== NULL_TREE
)
12848 return DECL_P (expr
);
12851 /* A for_each_rtx callback for which DATA points to the instruction
12852 containing *X. Stop the search if we find a MEM that is not safe
12853 from R10K speculation. */
12856 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
12864 if (r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
12867 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
12873 /* A note_stores callback for which DATA points to an instruction pointer.
12874 If *DATA is nonnull, make it null if it X contains a MEM that is not
12875 safe from R10K speculation. */
12878 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12883 insn_ptr
= (rtx
*) data
;
12884 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
12885 *insn_ptr
= NULL_RTX
;
12888 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
12889 Return nonzero if the call is not to a declared function. */
12892 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12901 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
12907 /* Return true if instruction INSN needs to be protected by an R10K
12911 r10k_needs_protection_p (rtx insn
)
12914 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
12916 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
12918 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
12919 return insn
== NULL_RTX
;
12922 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
12925 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
12926 edge is unconditional. */
12929 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
12934 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
12935 if (!single_succ_p (e
->src
)
12936 || !TEST_BIT (protected_bbs
, e
->src
->index
)
12937 || (e
->flags
& EDGE_COMPLEX
) != 0)
12942 /* Implement -mr10k-cache-barrier= for the current function. */
12945 r10k_insert_cache_barriers (void)
12947 int *rev_post_order
;
12950 sbitmap protected_bbs
;
12951 rtx insn
, end
, unprotected_region
;
12955 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
12959 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
12960 compute_bb_for_insn ();
12962 /* Create def-use chains. */
12963 df_set_flags (DF_EQ_NOTES
);
12964 df_chain_add_problem (DF_UD_CHAIN
);
12967 /* Calculate dominators. */
12968 calculate_dominance_info (CDI_DOMINATORS
);
12970 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
12971 X is protected by a cache barrier. */
12972 protected_bbs
= sbitmap_alloc (last_basic_block
);
12973 sbitmap_zero (protected_bbs
);
12975 /* Iterate over the basic blocks in reverse post-order. */
12976 rev_post_order
= XNEWVEC (int, last_basic_block
);
12977 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
12978 for (i
= 0; i
< n
; i
++)
12980 bb
= BASIC_BLOCK (rev_post_order
[i
]);
12982 /* If this block is only reached by unconditional edges, and if the
12983 source of every edge is protected, the beginning of the block is
12985 if (r10k_protected_bb_p (bb
, protected_bbs
))
12986 unprotected_region
= NULL_RTX
;
12988 unprotected_region
= pc_rtx
;
12989 end
= NEXT_INSN (BB_END (bb
));
12991 /* UNPROTECTED_REGION is:
12993 - null if we are processing a protected region,
12994 - pc_rtx if we are processing an unprotected region but have
12995 not yet found the first instruction in it
12996 - the first instruction in an unprotected region otherwise. */
12997 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
12999 if (unprotected_region
&& INSN_P (insn
))
13001 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
13002 /* This CACHE instruction protects the following code. */
13003 unprotected_region
= NULL_RTX
;
13006 /* See if INSN is the first instruction in this
13007 unprotected region. */
13008 if (unprotected_region
== pc_rtx
)
13009 unprotected_region
= insn
;
13011 /* See if INSN needs to be protected. If so,
13012 we must insert a cache barrier somewhere between
13013 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13014 clear which position is better performance-wise,
13015 but as a tie-breaker, we assume that it is better
13016 to allow delay slots to be back-filled where
13017 possible, and that it is better not to insert
13018 barriers in the middle of already-scheduled code.
13019 We therefore insert the barrier at the beginning
13021 if (r10k_needs_protection_p (insn
))
13023 emit_insn_before (gen_r10k_cache_barrier (),
13024 unprotected_region
);
13025 unprotected_region
= NULL_RTX
;
13031 /* The called function is not required to protect the exit path.
13032 The code that follows a call is therefore unprotected. */
13033 unprotected_region
= pc_rtx
;
13036 /* Record whether the end of this block is protected. */
13037 if (unprotected_region
== NULL_RTX
)
13038 SET_BIT (protected_bbs
, bb
->index
);
13040 XDELETEVEC (rev_post_order
);
13042 sbitmap_free (protected_bbs
);
13044 free_dominance_info (CDI_DOMINATORS
);
13046 df_finish_pass (false);
13048 free_bb_for_insn ();
13051 /* A temporary variable used by for_each_rtx callbacks, etc. */
13052 static rtx mips_sim_insn
;
13054 /* A structure representing the state of the processor pipeline.
13055 Used by the mips_sim_* family of functions. */
13057 /* The maximum number of instructions that can be issued in a cycle.
13058 (Caches mips_issue_rate.) */
13059 unsigned int issue_rate
;
13061 /* The current simulation time. */
13064 /* How many more instructions can be issued in the current cycle. */
13065 unsigned int insns_left
;
13067 /* LAST_SET[X].INSN is the last instruction to set register X.
13068 LAST_SET[X].TIME is the time at which that instruction was issued.
13069 INSN is null if no instruction has yet set register X. */
13073 } last_set
[FIRST_PSEUDO_REGISTER
];
13075 /* The pipeline's current DFA state. */
13079 /* Reset STATE to the initial simulation state. */
13082 mips_sim_reset (struct mips_sim
*state
)
13085 state
->insns_left
= state
->issue_rate
;
13086 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
13087 state_reset (state
->dfa_state
);
13090 /* Initialize STATE before its first use. DFA_STATE points to an
13091 allocated but uninitialized DFA state. */
13094 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
13096 state
->issue_rate
= mips_issue_rate ();
13097 state
->dfa_state
= dfa_state
;
13098 mips_sim_reset (state
);
13101 /* Advance STATE by one clock cycle. */
13104 mips_sim_next_cycle (struct mips_sim
*state
)
13107 state
->insns_left
= state
->issue_rate
;
13108 state_transition (state
->dfa_state
, 0);
13111 /* Advance simulation state STATE until instruction INSN can read
13115 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
13117 unsigned int regno
, end_regno
;
13119 end_regno
= END_REGNO (reg
);
13120 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
13121 if (state
->last_set
[regno
].insn
!= 0)
13125 t
= (state
->last_set
[regno
].time
13126 + insn_latency (state
->last_set
[regno
].insn
, insn
));
13127 while (state
->time
< t
)
13128 mips_sim_next_cycle (state
);
13132 /* A for_each_rtx callback. If *X is a register, advance simulation state
13133 DATA until mips_sim_insn can read the register's value. */
13136 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
13139 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
13143 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
13146 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
13148 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
13151 /* Advance simulation state STATE until all of INSN's register
13152 dependencies are satisfied. */
13155 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
13157 mips_sim_insn
= insn
;
13158 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
13161 /* Advance simulation state STATE until the units required by
13162 instruction INSN are available. */
13165 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
13169 tmp_state
= alloca (state_size ());
13170 while (state
->insns_left
== 0
13171 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
13172 state_transition (tmp_state
, insn
) >= 0))
13173 mips_sim_next_cycle (state
);
13176 /* Advance simulation state STATE until INSN is ready to issue. */
13179 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
13181 mips_sim_wait_regs (state
, insn
);
13182 mips_sim_wait_units (state
, insn
);
13185 /* mips_sim_insn has just set X. Update the LAST_SET array
13186 in simulation state DATA. */
13189 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
13191 struct mips_sim
*state
;
13193 state
= (struct mips_sim
*) data
;
13196 unsigned int regno
, end_regno
;
13198 end_regno
= END_REGNO (x
);
13199 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
13201 state
->last_set
[regno
].insn
= mips_sim_insn
;
13202 state
->last_set
[regno
].time
= state
->time
;
13207 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
13208 can issue immediately (i.e., that mips_sim_wait_insn has already
13212 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
13214 state_transition (state
->dfa_state
, insn
);
13215 state
->insns_left
--;
13217 mips_sim_insn
= insn
;
13218 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
13221 /* Simulate issuing a NOP in state STATE. */
13224 mips_sim_issue_nop (struct mips_sim
*state
)
13226 if (state
->insns_left
== 0)
13227 mips_sim_next_cycle (state
);
13228 state
->insns_left
--;
13231 /* Update simulation state STATE so that it's ready to accept the instruction
13232 after INSN. INSN should be part of the main rtl chain, not a member of a
13236 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
13238 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
13240 mips_sim_issue_nop (state
);
13242 switch (GET_CODE (SEQ_BEGIN (insn
)))
13246 /* We can't predict the processor state after a call or label. */
13247 mips_sim_reset (state
);
13251 /* The delay slots of branch likely instructions are only executed
13252 when the branch is taken. Therefore, if the caller has simulated
13253 the delay slot instruction, STATE does not really reflect the state
13254 of the pipeline for the instruction after the delay slot. Also,
13255 branch likely instructions tend to incur a penalty when not taken,
13256 so there will probably be an extra delay between the branch and
13257 the instruction after the delay slot. */
13258 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
13259 mips_sim_reset (state
);
13267 /* The VR4130 pipeline issues aligned pairs of instructions together,
13268 but it stalls the second instruction if it depends on the first.
13269 In order to cut down the amount of logic required, this dependence
13270 check is not based on a full instruction decode. Instead, any non-SPECIAL
13271 instruction is assumed to modify the register specified by bits 20-16
13272 (which is usually the "rt" field).
13274 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
13275 input, so we can end up with a false dependence between the branch
13276 and its delay slot. If this situation occurs in instruction INSN,
13277 try to avoid it by swapping rs and rt. */
13280 vr4130_avoid_branch_rt_conflict (rtx insn
)
13284 first
= SEQ_BEGIN (insn
);
13285 second
= SEQ_END (insn
);
13287 && NONJUMP_INSN_P (second
)
13288 && GET_CODE (PATTERN (first
)) == SET
13289 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
13290 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
13292 /* Check for the right kind of condition. */
13293 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
13294 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
13295 && REG_P (XEXP (cond
, 0))
13296 && REG_P (XEXP (cond
, 1))
13297 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
13298 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
13300 /* SECOND mentions the rt register but not the rs register. */
13301 rtx tmp
= XEXP (cond
, 0);
13302 XEXP (cond
, 0) = XEXP (cond
, 1);
13303 XEXP (cond
, 1) = tmp
;
13308 /* Implement -mvr4130-align. Go through each basic block and simulate the
13309 processor pipeline. If we find that a pair of instructions could execute
13310 in parallel, and the first of those instructions is not 8-byte aligned,
13311 insert a nop to make it aligned. */
13314 vr4130_align_insns (void)
13316 struct mips_sim state
;
13317 rtx insn
, subinsn
, last
, last2
, next
;
13322 /* LAST is the last instruction before INSN to have a nonzero length.
13323 LAST2 is the last such instruction before LAST. */
13327 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
13330 mips_sim_init (&state
, alloca (state_size ()));
13331 for (insn
= get_insns (); insn
!= 0; insn
= next
)
13333 unsigned int length
;
13335 next
= NEXT_INSN (insn
);
13337 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
13338 This isn't really related to the alignment pass, but we do it on
13339 the fly to avoid a separate instruction walk. */
13340 vr4130_avoid_branch_rt_conflict (insn
);
13342 if (USEFUL_INSN_P (insn
))
13343 FOR_EACH_SUBINSN (subinsn
, insn
)
13345 mips_sim_wait_insn (&state
, subinsn
);
13347 /* If we want this instruction to issue in parallel with the
13348 previous one, make sure that the previous instruction is
13349 aligned. There are several reasons why this isn't worthwhile
13350 when the second instruction is a call:
13352 - Calls are less likely to be performance critical,
13353 - There's a good chance that the delay slot can execute
13354 in parallel with the call.
13355 - The return address would then be unaligned.
13357 In general, if we're going to insert a nop between instructions
13358 X and Y, it's better to insert it immediately after X. That
13359 way, if the nop makes Y aligned, it will also align any labels
13360 between X and Y. */
13361 if (state
.insns_left
!= state
.issue_rate
13362 && !CALL_P (subinsn
))
13364 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
13366 /* SUBINSN is the first instruction in INSN and INSN is
13367 aligned. We want to align the previous instruction
13368 instead, so insert a nop between LAST2 and LAST.
13370 Note that LAST could be either a single instruction
13371 or a branch with a delay slot. In the latter case,
13372 LAST, like INSN, is already aligned, but the delay
13373 slot must have some extra delay that stops it from
13374 issuing at the same time as the branch. We therefore
13375 insert a nop before the branch in order to align its
13377 emit_insn_after (gen_nop (), last2
);
13380 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
13382 /* SUBINSN is the delay slot of INSN, but INSN is
13383 currently unaligned. Insert a nop between
13384 LAST and INSN to align it. */
13385 emit_insn_after (gen_nop (), last
);
13389 mips_sim_issue_insn (&state
, subinsn
);
13391 mips_sim_finish_insn (&state
, insn
);
13393 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
13394 length
= get_attr_length (insn
);
13397 /* If the instruction is an asm statement or multi-instruction
13398 mips.md patern, the length is only an estimate. Insert an
13399 8 byte alignment after it so that the following instructions
13400 can be handled correctly. */
13401 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
13402 && (recog_memoized (insn
) < 0 || length
>= 8))
13404 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
13405 next
= NEXT_INSN (next
);
13406 mips_sim_next_cycle (&state
);
13409 else if (length
& 4)
13410 aligned_p
= !aligned_p
;
13415 /* See whether INSN is an aligned label. */
13416 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
13422 /* This structure records that the current function has a LO_SUM
13423 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
13424 the largest offset applied to BASE by all such LO_SUMs. */
13425 struct mips_lo_sum_offset
{
13427 HOST_WIDE_INT offset
;
13430 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
13433 mips_hash_base (rtx base
)
13435 int do_not_record_p
;
13437 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
13440 /* Hash-table callbacks for mips_lo_sum_offsets. */
13443 mips_lo_sum_offset_hash (const void *entry
)
13445 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
13449 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
13451 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
13452 (const_rtx
) value
);
13455 /* Look up symbolic constant X in HTAB, which is a hash table of
13456 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
13457 paired with a recorded LO_SUM, otherwise record X in the table. */
13460 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
13464 struct mips_lo_sum_offset
*entry
;
13466 /* Split X into a base and offset. */
13467 split_const (x
, &base
, &offset
);
13468 if (UNSPEC_ADDRESS_P (base
))
13469 base
= UNSPEC_ADDRESS (base
);
13471 /* Look up the base in the hash table. */
13472 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
13476 entry
= (struct mips_lo_sum_offset
*) *slot
;
13477 if (option
== INSERT
)
13481 entry
= XNEW (struct mips_lo_sum_offset
);
13482 entry
->base
= base
;
13483 entry
->offset
= INTVAL (offset
);
13488 if (INTVAL (offset
) > entry
->offset
)
13489 entry
->offset
= INTVAL (offset
);
13492 return INTVAL (offset
) <= entry
->offset
;
13495 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
13496 Record every LO_SUM in *LOC. */
13499 mips_record_lo_sum (rtx
*loc
, void *data
)
13501 if (GET_CODE (*loc
) == LO_SUM
)
13502 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
13506 /* Return true if INSN is a SET of an orphaned high-part relocation.
13507 HTAB is a hash table of mips_lo_sum_offsets that describes all the
13508 LO_SUMs in the current function. */
13511 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
13513 enum mips_symbol_type type
;
13516 set
= single_set (insn
);
13519 /* Check for %his. */
13521 if (GET_CODE (x
) == HIGH
13522 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
13523 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
13525 /* Check for local %gots (and %got_pages, which is redundant but OK). */
13526 if (GET_CODE (x
) == UNSPEC
13527 && XINT (x
, 1) == UNSPEC_LOAD_GOT
13528 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
13529 SYMBOL_CONTEXT_LEA
, &type
)
13530 && type
== SYMBOL_GOTOFF_PAGE
)
13531 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
13536 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
13537 INSN and a previous instruction, avoid it by inserting nops after
13540 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
13541 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
13542 before using the value of that register. *HILO_DELAY counts the
13543 number of instructions since the last hilo hazard (that is,
13544 the number of instructions since the last MFLO or MFHI).
13546 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
13547 for the next instruction.
13549 LO_REG is an rtx for the LO register, used in dependence checking. */
13552 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
13553 rtx
*delayed_reg
, rtx lo_reg
)
13558 pattern
= PATTERN (insn
);
13560 /* Do not put the whole function in .set noreorder if it contains
13561 an asm statement. We don't know whether there will be hazards
13562 between the asm statement and the gcc-generated code. */
13563 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
13564 cfun
->machine
->all_noreorder_p
= false;
13566 /* Ignore zero-length instructions (barriers and the like). */
13567 ninsns
= get_attr_length (insn
) / 4;
13571 /* Work out how many nops are needed. Note that we only care about
13572 registers that are explicitly mentioned in the instruction's pattern.
13573 It doesn't matter that calls use the argument registers or that they
13574 clobber hi and lo. */
13575 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
13576 nops
= 2 - *hilo_delay
;
13577 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
13582 /* Insert the nops between this instruction and the previous one.
13583 Each new nop takes us further from the last hilo hazard. */
13584 *hilo_delay
+= nops
;
13586 emit_insn_after (gen_hazard_nop (), after
);
13588 /* Set up the state for the next instruction. */
13589 *hilo_delay
+= ninsns
;
13591 if (INSN_CODE (insn
) >= 0)
13592 switch (get_attr_hazard (insn
))
13602 set
= single_set (insn
);
13604 *delayed_reg
= SET_DEST (set
);
13609 /* Go through the instruction stream and insert nops where necessary.
13610 Also delete any high-part relocations whose partnering low parts
13611 are now all dead. See if the whole function can then be put into
13612 .set noreorder and .set nomacro. */
13615 mips_reorg_process_insns (void)
13617 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
13621 /* Force all instructions to be split into their final form. */
13622 split_all_insns_noflow ();
13624 /* Recalculate instruction lengths without taking nops into account. */
13625 cfun
->machine
->ignore_hazard_length_p
= true;
13626 shorten_branches (get_insns ());
13628 cfun
->machine
->all_noreorder_p
= true;
13630 /* We don't track MIPS16 PC-relative offsets closely enough to make
13631 a good job of "set .noreorder" code in MIPS16 mode. */
13633 cfun
->machine
->all_noreorder_p
= false;
13635 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
13636 if (!TARGET_EXPLICIT_RELOCS
)
13637 cfun
->machine
->all_noreorder_p
= false;
13639 /* Profiled functions can't be all noreorder because the profiler
13640 support uses assembler macros. */
13642 cfun
->machine
->all_noreorder_p
= false;
13644 /* Code compiled with -mfix-vr4120 can't be all noreorder because
13645 we rely on the assembler to work around some errata. */
13646 if (TARGET_FIX_VR4120
)
13647 cfun
->machine
->all_noreorder_p
= false;
13649 /* The same is true for -mfix-vr4130 if we might generate MFLO or
13650 MFHI instructions. Note that we avoid using MFLO and MFHI if
13651 the VR4130 MACC and DMACC instructions are available instead;
13652 see the *mfhilo_{si,di}_macc patterns. */
13653 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
13654 cfun
->machine
->all_noreorder_p
= false;
13656 htab
= htab_create (37, mips_lo_sum_offset_hash
,
13657 mips_lo_sum_offset_eq
, free
);
13659 /* Make a first pass over the instructions, recording all the LO_SUMs. */
13660 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
13661 FOR_EACH_SUBINSN (subinsn
, insn
)
13662 if (INSN_P (subinsn
))
13663 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
13668 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
13670 /* Make a second pass over the instructions. Delete orphaned
13671 high-part relocations or turn them into NOPs. Avoid hazards
13672 by inserting NOPs. */
13673 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
13675 next_insn
= NEXT_INSN (insn
);
13678 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
13680 /* If we find an orphaned high-part relocation in a delay
13681 slot, it's easier to turn that instruction into a NOP than
13682 to delete it. The delay slot will be a NOP either way. */
13683 FOR_EACH_SUBINSN (subinsn
, insn
)
13684 if (INSN_P (subinsn
))
13686 if (mips_orphaned_high_part_p (htab
, subinsn
))
13688 PATTERN (subinsn
) = gen_nop ();
13689 INSN_CODE (subinsn
) = CODE_FOR_nop
;
13691 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
13692 &delayed_reg
, lo_reg
);
13698 /* INSN is a single instruction. Delete it if it's an
13699 orphaned high-part relocation. */
13700 if (mips_orphaned_high_part_p (htab
, insn
))
13701 delete_insn (insn
);
13702 /* Also delete cache barriers if the last instruction
13703 was an annulled branch. INSN will not be speculatively
13705 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
13707 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
13708 delete_insn (insn
);
13711 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
13712 &delayed_reg
, lo_reg
);
13719 htab_delete (htab
);
13722 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
13727 mips16_lay_out_constants ();
13728 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
13729 r10k_insert_cache_barriers ();
13730 if (optimize
> 0 && flag_delayed_branch
)
13731 dbr_schedule (get_insns ());
13732 mips_reorg_process_insns ();
13734 && TARGET_EXPLICIT_RELOCS
13736 && TARGET_VR4130_ALIGN
)
13737 vr4130_align_insns ();
13740 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
13741 in order to avoid duplicating too much logic from elsewhere. */
13744 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
13745 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
13748 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
13749 bool use_sibcall_p
;
13751 /* Pretend to be a post-reload pass while generating rtl. */
13752 reload_completed
= 1;
13754 /* Mark the end of the (empty) prologue. */
13755 emit_note (NOTE_INSN_PROLOGUE_END
);
13757 /* Determine if we can use a sibcall to call FUNCTION directly. */
13758 fnaddr
= XEXP (DECL_RTL (function
), 0);
13759 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
13760 && const_call_insn_operand (fnaddr
, Pmode
));
13762 /* Determine if we need to load FNADDR from the GOT. */
13764 && (mips_got_symbol_type_p
13765 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
13767 /* Pick a global pointer. Use a call-clobbered register if
13768 TARGET_CALL_SAVED_GP. */
13769 cfun
->machine
->global_pointer
13770 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
13771 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
13773 /* Set up the global pointer for n32 or n64 abicalls. */
13774 mips_emit_loadgp ();
13777 /* We need two temporary registers in some cases. */
13778 temp1
= gen_rtx_REG (Pmode
, 2);
13779 temp2
= gen_rtx_REG (Pmode
, 3);
13781 /* Find out which register contains the "this" pointer. */
13782 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
13783 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
13785 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
13787 /* Add DELTA to THIS_RTX. */
13790 rtx offset
= GEN_INT (delta
);
13791 if (!SMALL_OPERAND (delta
))
13793 mips_emit_move (temp1
, offset
);
13796 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
13799 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
13800 if (vcall_offset
!= 0)
13804 /* Set TEMP1 to *THIS_RTX. */
13805 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
13807 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
13808 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
13810 /* Load the offset and add it to THIS_RTX. */
13811 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
13812 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
13815 /* Jump to the target function. Use a sibcall if direct jumps are
13816 allowed, otherwise load the address into a register first. */
13819 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
13820 SIBLING_CALL_P (insn
) = 1;
13824 /* This is messy. GAS treats "la $25,foo" as part of a call
13825 sequence and may allow a global "foo" to be lazily bound.
13826 The general move patterns therefore reject this combination.
13828 In this context, lazy binding would actually be OK
13829 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
13830 TARGET_CALL_SAVED_GP; see mips_load_call_address.
13831 We must therefore load the address via a temporary
13832 register if mips_dangerous_for_la25_p.
13834 If we jump to the temporary register rather than $25,
13835 the assembler can use the move insn to fill the jump's
13838 We can use the same technique for MIPS16 code, where $25
13839 is not a valid JR register. */
13840 if (TARGET_USE_PIC_FN_ADDR_REG
13842 && !mips_dangerous_for_la25_p (fnaddr
))
13843 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
13844 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
13846 if (TARGET_USE_PIC_FN_ADDR_REG
13847 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
13848 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
13849 emit_jump_insn (gen_indirect_jump (temp1
));
13852 /* Run just enough of rest_of_compilation. This sequence was
13853 "borrowed" from alpha.c. */
13854 insn
= get_insns ();
13855 insn_locators_alloc ();
13856 split_all_insns_noflow ();
13857 mips16_lay_out_constants ();
13858 shorten_branches (insn
);
13859 final_start_function (insn
, file
, 1);
13860 final (insn
, file
, 1);
13861 final_end_function ();
13862 free_after_compilation (cfun
);
13864 /* Clean up the vars set above. Note that final_end_function resets
13865 the global pointer for us. */
13866 reload_completed
= 0;
13869 /* The last argument passed to mips_set_mips16_mode, or negative if the
13870 function hasn't been called yet.
13872 There are two copies of this information. One is saved and restored
13873 by the PCH process while the other is specific to this compiler
13874 invocation. The information calculated by mips_set_mips16_mode
13875 is invalid unless the two variables are the same. */
13876 static int was_mips16_p
= -1;
13877 static GTY(()) int was_mips16_pch_p
= -1;
13879 /* Set up the target-dependent global state so that it matches the
13880 current function's ISA mode. */
13883 mips_set_mips16_mode (int mips16_p
)
13885 if (mips16_p
== was_mips16_p
13886 && mips16_p
== was_mips16_pch_p
)
13889 /* Restore base settings of various flags. */
13890 target_flags
= mips_base_target_flags
;
13891 flag_schedule_insns
= mips_base_schedule_insns
;
13892 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
13893 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
13894 align_loops
= mips_base_align_loops
;
13895 align_jumps
= mips_base_align_jumps
;
13896 align_functions
= mips_base_align_functions
;
13900 /* Switch to MIPS16 mode. */
13901 target_flags
|= MASK_MIPS16
;
13903 /* Don't run the scheduler before reload, since it tends to
13904 increase register pressure. */
13905 flag_schedule_insns
= 0;
13907 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
13908 the whole function to be in a single section. */
13909 flag_reorder_blocks_and_partition
= 0;
13911 /* Don't move loop invariants, because it tends to increase
13912 register pressure. It also introduces an extra move in cases
13913 where the constant is the first operand in a two-operand binary
13914 instruction, or when it forms a register argument to a functon
13916 flag_move_loop_invariants
= 0;
13918 target_flags
|= MASK_EXPLICIT_RELOCS
;
13920 /* Experiments suggest we get the best overall section-anchor
13921 results from using the range of an unextended LW or SW. Code
13922 that makes heavy use of byte or short accesses can do better
13923 with ranges of 0...31 and 0...63 respectively, but most code is
13924 sensitive to the range of LW and SW instead. */
13925 targetm
.min_anchor_offset
= 0;
13926 targetm
.max_anchor_offset
= 127;
13928 if (flag_pic
&& !TARGET_OLDABI
)
13929 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
13932 sorry ("MIPS16 -mxgot code");
13934 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
13935 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
13939 /* Switch to normal (non-MIPS16) mode. */
13940 target_flags
&= ~MASK_MIPS16
;
13942 /* Provide default values for align_* for 64-bit targets. */
13945 if (align_loops
== 0)
13947 if (align_jumps
== 0)
13949 if (align_functions
== 0)
13950 align_functions
= 8;
13953 targetm
.min_anchor_offset
= -32768;
13954 targetm
.max_anchor_offset
= 32767;
13957 /* (Re)initialize MIPS target internals for new ISA. */
13958 mips_init_relocs ();
13960 if (was_mips16_p
>= 0 || was_mips16_pch_p
>= 0)
13961 /* Reinitialize target-dependent state. */
13964 was_mips16_p
= mips16_p
;
13965 was_mips16_pch_p
= mips16_p
;
13968 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
13969 function should use the MIPS16 ISA and switch modes accordingly. */
13972 mips_set_current_function (tree fndecl
)
13974 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
13977 /* Allocate a chunk of memory for per-function machine-dependent data. */
13979 static struct machine_function
*
13980 mips_init_machine_status (void)
13982 return ((struct machine_function
*)
13983 ggc_alloc_cleared (sizeof (struct machine_function
)));
13986 /* Return the processor associated with the given ISA level, or null
13987 if the ISA isn't valid. */
13989 static const struct mips_cpu_info
*
13990 mips_cpu_info_from_isa (int isa
)
13994 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
13995 if (mips_cpu_info_table
[i
].isa
== isa
)
13996 return mips_cpu_info_table
+ i
;
14001 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14002 with a final "000" replaced by "k". Ignore case.
14004 Note: this function is shared between GCC and GAS. */
14007 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14009 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14010 given
++, canonical
++;
14012 return ((*given
== 0 && *canonical
== 0)
14013 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14016 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14017 CPU name. We've traditionally allowed a lot of variation here.
14019 Note: this function is shared between GCC and GAS. */
14022 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14024 /* First see if the name matches exactly, or with a final "000"
14025 turned into "k". */
14026 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14029 /* If not, try comparing based on numerical designation alone.
14030 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14031 if (TOLOWER (*given
) == 'r')
14033 if (!ISDIGIT (*given
))
14036 /* Skip over some well-known prefixes in the canonical name,
14037 hoping to find a number there too. */
14038 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14040 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14042 else if (TOLOWER (canonical
[0]) == 'r')
14045 return mips_strict_matching_cpu_name_p (canonical
, given
);
14048 /* Return the mips_cpu_info entry for the processor or ISA given
14049 by CPU_STRING. Return null if the string isn't recognized.
14051 A similar function exists in GAS. */
14053 static const struct mips_cpu_info
*
14054 mips_parse_cpu (const char *cpu_string
)
14059 /* In the past, we allowed upper-case CPU names, but it doesn't
14060 work well with the multilib machinery. */
14061 for (s
= cpu_string
; *s
!= 0; s
++)
14064 warning (0, "CPU names must be lower case");
14068 /* 'from-abi' selects the most compatible architecture for the given
14069 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14070 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14072 if (strcasecmp (cpu_string
, "from-abi") == 0)
14073 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
14074 : ABI_NEEDS_64BIT_REGS
? 3
14075 : (TARGET_64BIT
? 3 : 1));
14077 /* 'default' has traditionally been a no-op. Probably not very useful. */
14078 if (strcasecmp (cpu_string
, "default") == 0)
14081 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
14082 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
14083 return mips_cpu_info_table
+ i
;
14088 /* Set up globals to generate code for the ISA or processor
14089 described by INFO. */
14092 mips_set_architecture (const struct mips_cpu_info
*info
)
14096 mips_arch_info
= info
;
14097 mips_arch
= info
->cpu
;
14098 mips_isa
= info
->isa
;
14102 /* Likewise for tuning. */
14105 mips_set_tune (const struct mips_cpu_info
*info
)
14109 mips_tune_info
= info
;
14110 mips_tune
= info
->cpu
;
14114 /* Implement TARGET_HANDLE_OPTION. */
14117 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
14122 if (strcmp (arg
, "32") == 0)
14124 else if (strcmp (arg
, "o64") == 0)
14125 mips_abi
= ABI_O64
;
14126 else if (strcmp (arg
, "n32") == 0)
14127 mips_abi
= ABI_N32
;
14128 else if (strcmp (arg
, "64") == 0)
14130 else if (strcmp (arg
, "eabi") == 0)
14131 mips_abi
= ABI_EABI
;
14138 return mips_parse_cpu (arg
) != 0;
14141 mips_isa_option_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
14142 return mips_isa_option_info
!= 0;
14144 case OPT_mno_flush_func
:
14145 mips_cache_flush_func
= NULL
;
14148 case OPT_mcode_readable_
:
14149 if (strcmp (arg
, "yes") == 0)
14150 mips_code_readable
= CODE_READABLE_YES
;
14151 else if (strcmp (arg
, "pcrel") == 0)
14152 mips_code_readable
= CODE_READABLE_PCREL
;
14153 else if (strcmp (arg
, "no") == 0)
14154 mips_code_readable
= CODE_READABLE_NO
;
14159 case OPT_mr10k_cache_barrier_
:
14160 if (strcmp (arg
, "load-store") == 0)
14161 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_LOAD_STORE
;
14162 else if (strcmp (arg
, "store") == 0)
14163 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_STORE
;
14164 else if (strcmp (arg
, "none") == 0)
14165 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
14175 /* Implement OVERRIDE_OPTIONS. */
14178 mips_override_options (void)
14180 int i
, start
, regno
, mode
;
14182 /* Process flags as though we were generating non-MIPS16 code. */
14183 mips_base_mips16
= TARGET_MIPS16
;
14184 target_flags
&= ~MASK_MIPS16
;
14186 #ifdef SUBTARGET_OVERRIDE_OPTIONS
14187 SUBTARGET_OVERRIDE_OPTIONS
;
14190 /* Set the small data limit. */
14191 mips_small_data_threshold
= (g_switch_set
14193 : MIPS_DEFAULT_GVALUE
);
14195 /* The following code determines the architecture and register size.
14196 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
14197 The GAS and GCC code should be kept in sync as much as possible. */
14199 if (mips_arch_string
!= 0)
14200 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
14202 if (mips_isa_option_info
!= 0)
14204 if (mips_arch_info
== 0)
14205 mips_set_architecture (mips_isa_option_info
);
14206 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
14207 error ("%<-%s%> conflicts with the other architecture options, "
14208 "which specify a %s processor",
14209 mips_isa_option_info
->name
,
14210 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
14213 if (mips_arch_info
== 0)
14215 #ifdef MIPS_CPU_STRING_DEFAULT
14216 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
14218 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
14222 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
14223 error ("%<-march=%s%> is not compatible with the selected ABI",
14224 mips_arch_info
->name
);
14226 /* Optimize for mips_arch, unless -mtune selects a different processor. */
14227 if (mips_tune_string
!= 0)
14228 mips_set_tune (mips_parse_cpu (mips_tune_string
));
14230 if (mips_tune_info
== 0)
14231 mips_set_tune (mips_arch_info
);
14233 if ((target_flags_explicit
& MASK_64BIT
) != 0)
14235 /* The user specified the size of the integer registers. Make sure
14236 it agrees with the ABI and ISA. */
14237 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
14238 error ("%<-mgp64%> used with a 32-bit processor");
14239 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
14240 error ("%<-mgp32%> used with a 64-bit ABI");
14241 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
14242 error ("%<-mgp64%> used with a 32-bit ABI");
14246 /* Infer the integer register size from the ABI and processor.
14247 Restrict ourselves to 32-bit registers if that's all the
14248 processor has, or if the ABI cannot handle 64-bit registers. */
14249 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
14250 target_flags
&= ~MASK_64BIT
;
14252 target_flags
|= MASK_64BIT
;
14255 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
14257 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
14258 error ("unsupported combination: %s", "-mfp64 -msingle-float");
14259 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
14260 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
14261 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
14263 if (!ISA_HAS_MXHC1
)
14264 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
14265 " the target supports the mfhc1 and mthc1 instructions");
14266 else if (mips_abi
!= ABI_32
)
14267 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
14273 /* -msingle-float selects 32-bit float registers. Otherwise the
14274 float registers should be the same size as the integer ones. */
14275 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
14276 target_flags
|= MASK_FLOAT64
;
14278 target_flags
&= ~MASK_FLOAT64
;
14281 /* End of code shared with GAS. */
14283 /* If no -mlong* option was given, infer it from the other options. */
14284 if ((target_flags_explicit
& MASK_LONG64
) == 0)
14286 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
14287 target_flags
|= MASK_LONG64
;
14289 target_flags
&= ~MASK_LONG64
;
14292 if (!TARGET_OLDABI
)
14293 flag_pcc_struct_return
= 0;
14295 /* Decide which rtx_costs structure to use. */
14297 mips_cost
= &mips_rtx_cost_optimize_size
;
14299 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
14301 /* If the user hasn't specified a branch cost, use the processor's
14303 if (mips_branch_cost
== 0)
14304 mips_branch_cost
= mips_cost
->branch_cost
;
14306 /* If neither -mbranch-likely nor -mno-branch-likely was given
14307 on the command line, set MASK_BRANCHLIKELY based on the target
14308 architecture and tuning flags. Annulled delay slots are a
14309 size win, so we only consider the processor-specific tuning
14310 for !optimize_size. */
14311 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
14313 if (ISA_HAS_BRANCHLIKELY
14315 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
14316 target_flags
|= MASK_BRANCHLIKELY
;
14318 target_flags
&= ~MASK_BRANCHLIKELY
;
14320 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
14321 warning (0, "the %qs architecture does not support branch-likely"
14322 " instructions", mips_arch_info
->name
);
14324 /* The effect of -mabicalls isn't defined for the EABI. */
14325 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
14327 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
14328 target_flags
&= ~MASK_ABICALLS
;
14331 if (TARGET_ABICALLS_PIC2
)
14332 /* We need to set flag_pic for executables as well as DSOs
14333 because we may reference symbols that are not defined in
14334 the final executable. (MIPS does not use things like
14335 copy relocs, for example.)
14337 There is a body of code that uses __PIC__ to distinguish
14338 between -mabicalls and -mno-abicalls code. The non-__PIC__
14339 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
14340 long as any indirect jumps use $25. */
14343 /* -mvr4130-align is a "speed over size" optimization: it usually produces
14344 faster code, but at the expense of more nops. Enable it at -O3 and
14346 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
14347 target_flags
|= MASK_VR4130_ALIGN
;
14349 /* Prefer a call to memcpy over inline code when optimizing for size,
14350 though see MOVE_RATIO in mips.h. */
14351 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
14352 target_flags
|= MASK_MEMCPY
;
14354 /* If we have a nonzero small-data limit, check that the -mgpopt
14355 setting is consistent with the other target flags. */
14356 if (mips_small_data_threshold
> 0)
14360 if (!TARGET_EXPLICIT_RELOCS
)
14361 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
14363 TARGET_LOCAL_SDATA
= false;
14364 TARGET_EXTERN_SDATA
= false;
14368 if (TARGET_VXWORKS_RTP
)
14369 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
14371 if (TARGET_ABICALLS
)
14372 warning (0, "cannot use small-data accesses for %qs",
14377 #ifdef MIPS_TFMODE_FORMAT
14378 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
14381 /* Make sure that the user didn't turn off paired single support when
14382 MIPS-3D support is requested. */
14384 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
14385 && !TARGET_PAIRED_SINGLE_FLOAT
)
14386 error ("%<-mips3d%> requires %<-mpaired-single%>");
14388 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
14390 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
14392 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
14393 and TARGET_HARD_FLOAT_ABI are both true. */
14394 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
14395 error ("%qs must be used with %qs",
14396 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
14397 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
14399 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
14401 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
14402 warning (0, "the %qs architecture does not support paired-single"
14403 " instructions", mips_arch_info
->name
);
14405 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14406 && !TARGET_CACHE_BUILTIN
)
14408 error ("%qs requires a target that provides the %qs instruction",
14409 "-mr10k-cache-barrier", "cache");
14410 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
14413 /* If TARGET_DSPR2, enable MASK_DSP. */
14415 target_flags
|= MASK_DSP
;
14417 /* .eh_frame addresses should be the same width as a C pointer.
14418 Most MIPS ABIs support only one pointer size, so the assembler
14419 will usually know exactly how big an .eh_frame address is.
14421 Unfortunately, this is not true of the 64-bit EABI. The ABI was
14422 originally defined to use 64-bit pointers (i.e. it is LP64), and
14423 this is still the default mode. However, we also support an n32-like
14424 ILP32 mode, which is selected by -mlong32. The problem is that the
14425 assembler has traditionally not had an -mlong option, so it has
14426 traditionally not known whether we're using the ILP32 or LP64 form.
14428 As it happens, gas versions up to and including 2.19 use _32-bit_
14429 addresses for EABI64 .cfi_* directives. This is wrong for the
14430 default LP64 mode, so we can't use the directives by default.
14431 Moreover, since gas's current behavior is at odds with gcc's
14432 default behavior, it seems unwise to rely on future versions
14433 of gas behaving the same way. We therefore avoid using .cfi
14434 directives for -mlong32 as well. */
14435 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
14436 flag_dwarf2_cfi_asm
= 0;
14438 mips_init_print_operand_punct ();
14440 /* Set up array to map GCC register number to debug register number.
14441 Ignore the special purpose register numbers. */
14443 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14445 mips_dbx_regno
[i
] = INVALID_REGNUM
;
14446 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
14447 mips_dwarf_regno
[i
] = i
;
14449 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
14452 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
14453 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
14454 mips_dbx_regno
[i
] = i
+ start
;
14456 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
14457 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
14458 mips_dbx_regno
[i
] = i
+ start
;
14460 /* Accumulator debug registers use big-endian ordering. */
14461 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
14462 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
14463 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
14464 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
14465 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
14467 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
14468 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
14471 /* Set up mips_hard_regno_mode_ok. */
14472 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
14473 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
14474 mips_hard_regno_mode_ok
[(int)mode
][regno
]
14475 = mips_hard_regno_mode_ok_p (regno
, mode
);
14477 /* Function to allocate machine-dependent function status. */
14478 init_machine_status
= &mips_init_machine_status
;
14480 /* Default to working around R4000 errata only if the processor
14481 was selected explicitly. */
14482 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
14483 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
14484 target_flags
|= MASK_FIX_R4000
;
14486 /* Default to working around R4400 errata only if the processor
14487 was selected explicitly. */
14488 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
14489 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
14490 target_flags
|= MASK_FIX_R4400
;
14492 /* Default to working around R10000 errata only if the processor
14493 was selected explicitly. */
14494 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
14495 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r10000"))
14496 target_flags
|= MASK_FIX_R10000
;
14498 /* Make sure that branch-likely instructions available when using
14499 -mfix-r10000. The instructions are not available if either:
14501 1. -mno-branch-likely was passed.
14502 2. The selected ISA does not support branch-likely and
14503 the command line does not include -mbranch-likely. */
14504 if (TARGET_FIX_R10000
14505 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
14506 ? !ISA_HAS_BRANCHLIKELY
14507 : !TARGET_BRANCHLIKELY
))
14508 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
14510 /* Save base state of options. */
14511 mips_base_target_flags
= target_flags
;
14512 mips_base_schedule_insns
= flag_schedule_insns
;
14513 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
14514 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
14515 mips_base_align_loops
= align_loops
;
14516 mips_base_align_jumps
= align_jumps
;
14517 mips_base_align_functions
= align_functions
;
14519 /* Now select the ISA mode.
14521 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
14522 MIPS16 mode afterwards if need be. */
14523 mips_set_mips16_mode (false);
14526 /* Swap the register information for registers I and I + 1, which
14527 currently have the wrong endianness. Note that the registers'
14528 fixedness and call-clobberedness might have been set on the
14532 mips_swap_registers (unsigned int i
)
14537 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
14538 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
14540 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
14541 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
14542 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
14543 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
14549 /* Implement CONDITIONAL_REGISTER_USAGE. */
14552 mips_conditional_register_usage (void)
14557 /* These DSP control register fields are global. */
14558 global_regs
[CCDSP_PO_REGNUM
] = 1;
14559 global_regs
[CCDSP_SC_REGNUM
] = 1;
14565 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
14566 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
14568 if (!TARGET_HARD_FLOAT
)
14572 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
14573 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
14574 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
14575 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
14577 else if (! ISA_HAS_8CC
)
14581 /* We only have a single condition-code register. We implement
14582 this by fixing all the condition-code registers and generating
14583 RTL that refers directly to ST_REG_FIRST. */
14584 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
14585 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
14587 /* In MIPS16 mode, we permit the $t temporary registers to be used
14588 for reload. We prohibit the unused $s registers, since they
14589 are call-saved, and saving them via a MIPS16 register would
14590 probably waste more time than just reloading the value. */
14593 fixed_regs
[18] = call_used_regs
[18] = 1;
14594 fixed_regs
[19] = call_used_regs
[19] = 1;
14595 fixed_regs
[20] = call_used_regs
[20] = 1;
14596 fixed_regs
[21] = call_used_regs
[21] = 1;
14597 fixed_regs
[22] = call_used_regs
[22] = 1;
14598 fixed_regs
[23] = call_used_regs
[23] = 1;
14599 fixed_regs
[26] = call_used_regs
[26] = 1;
14600 fixed_regs
[27] = call_used_regs
[27] = 1;
14601 fixed_regs
[30] = call_used_regs
[30] = 1;
14603 /* $f20-$f23 are call-clobbered for n64. */
14604 if (mips_abi
== ABI_64
)
14607 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
14608 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
14610 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
14612 if (mips_abi
== ABI_N32
)
14615 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
14616 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
14618 /* Make sure that double-register accumulator values are correctly
14619 ordered for the current endianness. */
14620 if (TARGET_LITTLE_ENDIAN
)
14622 unsigned int regno
;
14624 mips_swap_registers (MD_REG_FIRST
);
14625 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
14626 mips_swap_registers (regno
);
14630 /* Initialize vector TARGET to VALS. */
14633 mips_expand_vector_init (rtx target
, rtx vals
)
14635 enum machine_mode mode
;
14636 enum machine_mode inner
;
14637 unsigned int i
, n_elts
;
14640 mode
= GET_MODE (target
);
14641 inner
= GET_MODE_INNER (mode
);
14642 n_elts
= GET_MODE_NUNITS (mode
);
14644 gcc_assert (VECTOR_MODE_P (mode
));
14646 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
14647 for (i
= 0; i
< n_elts
; i
++)
14648 emit_move_insn (adjust_address_nv (mem
, inner
, i
* GET_MODE_SIZE (inner
)),
14649 XVECEXP (vals
, 0, i
));
14651 emit_move_insn (target
, mem
);
14654 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
14655 other registers for instructions for which it is possible. This
14656 encourages the compiler to use CMP in cases where an XOR would
14657 require some register shuffling. */
14660 mips_order_regs_for_local_alloc (void)
14664 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14665 reg_alloc_order
[i
] = i
;
14669 /* It really doesn't matter where we put register 0, since it is
14670 a fixed register anyhow. */
14671 reg_alloc_order
[0] = 24;
14672 reg_alloc_order
[24] = 0;
14676 /* Implement EPILOGUE_USES. */
14679 mips_epilogue_uses (unsigned int regno
)
14681 /* Say that the epilogue uses the return address register. Note that
14682 in the case of sibcalls, the values "used by the epilogue" are
14683 considered live at the start of the called function. */
14687 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
14688 See the comment above load_call<mode> for details. */
14689 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
14692 /* An interrupt handler must preserve some registers that are
14693 ordinarily call-clobbered. */
14694 if (cfun
->machine
->interrupt_handler_p
14695 && mips_interrupt_extra_call_saved_reg_p (regno
))
14701 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
14704 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
14706 return GET_CODE (*x
) == REG
&& REGNO (*x
) == AT_REGNUM
;
14710 /* Implement FINAL_PRESCAN_INSN. */
14713 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
14717 /* We need to emit ".set noat" before an instruction that accesses
14719 if (recog_memoized (insn
) >= 0)
14720 for (i
= 0; i
< noperands
; i
++)
14721 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
14722 if (set_noat
++ == 0)
14723 fprintf (asm_out_file
, "\t.set\tnoat\n");
14726 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
14729 mips_final_postscan_insn (FILE *file
, rtx insn
, rtx
*opvec
, int noperands
)
14733 /* Close any ".set noat" block opened by mips_final_prescan_insn. */
14734 if (recog_memoized (insn
) >= 0)
14735 for (i
= 0; i
< noperands
; i
++)
14736 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
14737 if (--set_noat
== 0)
14738 fprintf (file
, "\t.set\tat\n");
14741 /* Initialize the GCC target structure. */
14742 #undef TARGET_ASM_ALIGNED_HI_OP
14743 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
14744 #undef TARGET_ASM_ALIGNED_SI_OP
14745 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
14746 #undef TARGET_ASM_ALIGNED_DI_OP
14747 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
14749 #undef TARGET_ASM_FUNCTION_PROLOGUE
14750 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
14751 #undef TARGET_ASM_FUNCTION_EPILOGUE
14752 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
14753 #undef TARGET_ASM_SELECT_RTX_SECTION
14754 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
14755 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
14756 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
14758 #undef TARGET_SCHED_INIT
14759 #define TARGET_SCHED_INIT mips_sched_init
14760 #undef TARGET_SCHED_REORDER
14761 #define TARGET_SCHED_REORDER mips_sched_reorder
14762 #undef TARGET_SCHED_REORDER2
14763 #define TARGET_SCHED_REORDER2 mips_sched_reorder
14764 #undef TARGET_SCHED_VARIABLE_ISSUE
14765 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
14766 #undef TARGET_SCHED_ADJUST_COST
14767 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
14768 #undef TARGET_SCHED_ISSUE_RATE
14769 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
14770 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
14771 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
14772 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
14773 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
14774 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14775 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14776 mips_multipass_dfa_lookahead
14778 #undef TARGET_DEFAULT_TARGET_FLAGS
14779 #define TARGET_DEFAULT_TARGET_FLAGS \
14781 | TARGET_CPU_DEFAULT \
14782 | TARGET_ENDIAN_DEFAULT \
14783 | TARGET_FP_EXCEPTIONS_DEFAULT \
14784 | MASK_CHECK_ZERO_DIV \
14786 #undef TARGET_HANDLE_OPTION
14787 #define TARGET_HANDLE_OPTION mips_handle_option
14789 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14790 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
14792 #undef TARGET_INSERT_ATTRIBUTES
14793 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
14794 #undef TARGET_MERGE_DECL_ATTRIBUTES
14795 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
14796 #undef TARGET_SET_CURRENT_FUNCTION
14797 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
14799 #undef TARGET_VALID_POINTER_MODE
14800 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
14801 #undef TARGET_RTX_COSTS
14802 #define TARGET_RTX_COSTS mips_rtx_costs
14803 #undef TARGET_ADDRESS_COST
14804 #define TARGET_ADDRESS_COST mips_address_cost
14806 #undef TARGET_IN_SMALL_DATA_P
14807 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
14809 #undef TARGET_MACHINE_DEPENDENT_REORG
14810 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
14812 #undef TARGET_ASM_FILE_START
14813 #define TARGET_ASM_FILE_START mips_file_start
14814 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
14815 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
14817 #undef TARGET_INIT_LIBFUNCS
14818 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
14820 #undef TARGET_BUILD_BUILTIN_VA_LIST
14821 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
14822 #undef TARGET_EXPAND_BUILTIN_VA_START
14823 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
14824 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14825 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
14827 #undef TARGET_PROMOTE_FUNCTION_ARGS
14828 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
14829 #undef TARGET_PROMOTE_FUNCTION_RETURN
14830 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
14831 #undef TARGET_PROMOTE_PROTOTYPES
14832 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
14834 #undef TARGET_RETURN_IN_MEMORY
14835 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
14836 #undef TARGET_RETURN_IN_MSB
14837 #define TARGET_RETURN_IN_MSB mips_return_in_msb
14839 #undef TARGET_ASM_OUTPUT_MI_THUNK
14840 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
14841 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14842 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14844 #undef TARGET_SETUP_INCOMING_VARARGS
14845 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
14846 #undef TARGET_STRICT_ARGUMENT_NAMING
14847 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
14848 #undef TARGET_MUST_PASS_IN_STACK
14849 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14850 #undef TARGET_PASS_BY_REFERENCE
14851 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
14852 #undef TARGET_CALLEE_COPIES
14853 #define TARGET_CALLEE_COPIES mips_callee_copies
14854 #undef TARGET_ARG_PARTIAL_BYTES
14855 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
14857 #undef TARGET_MODE_REP_EXTENDED
14858 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
14860 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14861 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
14863 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14864 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
14866 #undef TARGET_INIT_BUILTINS
14867 #define TARGET_INIT_BUILTINS mips_init_builtins
14868 #undef TARGET_EXPAND_BUILTIN
14869 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
14871 #undef TARGET_HAVE_TLS
14872 #define TARGET_HAVE_TLS HAVE_AS_TLS
14874 #undef TARGET_CANNOT_FORCE_CONST_MEM
14875 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
14877 #undef TARGET_ENCODE_SECTION_INFO
14878 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
14880 #undef TARGET_ATTRIBUTE_TABLE
14881 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
14882 /* All our function attributes are related to how out-of-line copies should
14883 be compiled or called. They don't in themselves prevent inlining. */
14884 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14885 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14887 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14888 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
14890 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14891 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
14892 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
14893 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
14895 #undef TARGET_COMP_TYPE_ATTRIBUTES
14896 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
14898 #ifdef HAVE_AS_DTPRELWORD
14899 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14900 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
14902 #undef TARGET_DWARF_REGISTER_SPAN
14903 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
14905 #undef TARGET_IRA_COVER_CLASSES
14906 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
14908 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
14909 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
14911 struct gcc_target targetm
= TARGET_INITIALIZER
;
14913 #include "gt-mips.h"