gcc/config/mips/mips.c

   1 /* Subroutines used for MIPS code generation.
   2    Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
   4    Contributed by A. Lichnewsky, lich@inria.inria.fr.
   5    Changes by Michael Meissner, meissner@osf.org.
   6    64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
   7    Brendan Eich, brendan@microunity.com.
   8
   9 This file is part of GCC.
  10
  11 GCC is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 GCC is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with GCC; see the file COPYING.  If not, write to
  23 the Free Software Foundation, 59 Temple Place - Suite 330,
  24 Boston, MA 02111-1307, USA.  */
  25
  26 #include "config.h"
  27 #include "system.h"
  28 #include "coretypes.h"
  29 #include "tm.h"
  30 #include <signal.h>
  31 #include "rtl.h"
  32 #include "regs.h"
  33 #include "hard-reg-set.h"
  34 #include "real.h"
  35 #include "insn-config.h"
  36 #include "conditions.h"
  37 #include "insn-attr.h"
  38 #include "recog.h"
  39 #include "toplev.h"
  40 #include "output.h"
  41 #include "tree.h"
  42 #include "function.h"
  43 #include "expr.h"
  44 #include "optabs.h"
  45 #include "flags.h"
  46 #include "reload.h"
  47 #include "tm_p.h"
  48 #include "ggc.h"
  49 #include "gstab.h"
  50 #include "hashtab.h"
  51 #include "debug.h"
  52 #include "target.h"
  53 #include "target-def.h"
  54 #include "integrate.h"
  55 #include "langhooks.h"
  56 #include "cfglayout.h"
  57
  58 /* Enumeration for all of the relational tests, so that we can build
  59    arrays indexed by the test type, and not worry about the order
  60    of EQ, NE, etc.  */
  61
  62 enum internal_test {
  63   ITEST_EQ,
  64   ITEST_NE,
  65   ITEST_GT,
  66   ITEST_GE,
  67   ITEST_LT,
  68   ITEST_LE,
  69   ITEST_GTU,
  70   ITEST_GEU,
  71   ITEST_LTU,
  72   ITEST_LEU,
  73   ITEST_MAX
  74 };
  75
  76 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF.  */
  77 #define UNSPEC_ADDRESS_P(X)                                     \
  78   (GET_CODE (X) == UNSPEC                                       \
  79    && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST                       \
  80    && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
  81
  82 /* Extract the symbol or label from UNSPEC wrapper X.  */
  83 #define UNSPEC_ADDRESS(X) \
  84   XVECEXP (X, 0, 0)
  85
  86 /* Extract the symbol type from UNSPEC wrapper X.  */
  87 #define UNSPEC_ADDRESS_TYPE(X) \
  88   ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
  89
  90 /* True if X is (const $gp).  This is used to initialize the mips16
  91    gp pseudo register.  */
  92 #define CONST_GP_P(X) \
  93   (GET_CODE (X) == CONST && XEXP (X, 0) == pic_offset_table_rtx)
  94
  95 /* The maximum distance between the top of the stack frame and the
  96    value $sp has when we save & restore registers.
  97
  98    Use a maximum gap of 0x100 in the mips16 case.  We can then use
  99    unextended instructions to save and restore registers, and to
 100    allocate and deallocate the top part of the frame.
 101
 102    The value in the !mips16 case must be a SMALL_OPERAND and must
 103    preserve the maximum stack alignment.  It could really be 0x7ff0,
 104    but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
 105    multi-instruction addu sequence.  Use 0x7fe0 to work around this.  */
 106 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
 107
 108 /* Classifies a SYMBOL_REF, LABEL_REF or UNSPEC address.
 109
 110    SYMBOL_GENERAL
 111        Used when none of the below apply.
 112
 113    SYMBOL_SMALL_DATA
 114        The symbol refers to something in a small data section.
 115
 116    SYMBOL_CONSTANT_POOL
 117        The symbol refers to something in the mips16 constant pool.
 118
 119    SYMBOL_GOT_LOCAL
 120        The symbol refers to local data that will be found using
 121        the global offset table.
 122
 123    SYMBOL_GOT_GLOBAL
 124        Likewise non-local data.
 125
 126    SYMBOL_GOTOFF_PAGE
 127        An UNSPEC wrapper around a SYMBOL_GOT_LOCAL.  It represents the
 128        offset from _gp of a GOT page entry.
 129
 130    SYMBOL_GOTOFF_GLOBAL
 131        An UNSPEC wrapper around a SYMBOL_GOT_GLOBAL.  It represents the
 132        the offset from _gp of the symbol's GOT entry.
 133
 134    SYMBOL_GOTOFF_CALL
 135        Like SYMBOL_GOTOFF_GLOBAL, but used when calling a global function.
 136        The GOT entry is allowed to point to a stub rather than to the
 137        function itself.
 138
 139    SYMBOL_GOTOFF_LOADGP
 140        An UNSPEC wrapper around a function's address.  It represents the
 141        offset of _gp from the start of the function.  */
 142 enum mips_symbol_type {
 143   SYMBOL_GENERAL,
 144   SYMBOL_SMALL_DATA,
 145   SYMBOL_CONSTANT_POOL,
 146   SYMBOL_GOT_LOCAL,
 147   SYMBOL_GOT_GLOBAL,
 148   SYMBOL_GOTOFF_PAGE,
 149   SYMBOL_GOTOFF_GLOBAL,
 150   SYMBOL_GOTOFF_CALL,
 151   SYMBOL_GOTOFF_LOADGP
 152 };
 153 #define NUM_SYMBOL_TYPES (SYMBOL_GOTOFF_LOADGP + 1)
 154
 155
 156 /* Classifies an address.
 157
 158    ADDRESS_REG
 159        A natural register + offset address.  The register satisfies
 160        mips_valid_base_register_p and the offset is a const_arith_operand.
 161
 162    ADDRESS_LO_SUM
 163        A LO_SUM rtx.  The first operand is a valid base register and
 164        the second operand is a symbolic address.
 165
 166    ADDRESS_CONST_INT
 167        A signed 16-bit constant address.
 168
 169    ADDRESS_SYMBOLIC:
 170        A constant symbolic address (equivalent to CONSTANT_SYMBOLIC).  */
 171 enum mips_address_type {
 172   ADDRESS_REG,
 173   ADDRESS_LO_SUM,
 174   ADDRESS_CONST_INT,
 175   ADDRESS_SYMBOLIC
 176 };
 177
 178 /* A function to save or store a register.  The first argument is the
 179    register and the second is the stack slot.  */
 180 typedef void (*mips_save_restore_fn) (rtx, rtx);
 181
 182 struct constant;
 183 struct mips_arg_info;
 184 struct mips_address_info;
 185 struct mips_integer_op;
 186
 187 static enum mips_symbol_type mips_classify_symbol (rtx);
 188 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
 189 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
 190 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
 191 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
 192 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
 193 static bool mips_classify_address (struct mips_address_info *, rtx,
 194                                    enum machine_mode, int);
 195 static int mips_symbol_insns (enum mips_symbol_type);
 196 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
 197 static rtx mips_force_temporary (rtx, rtx);
 198 static rtx mips_split_symbol (rtx, rtx);
 199 static rtx mips_unspec_address (rtx, enum mips_symbol_type);
 200 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
 201 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
 202 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
 203 static unsigned int mips_build_lower (struct mips_integer_op *,
 204                                       unsigned HOST_WIDE_INT);
 205 static unsigned int mips_build_integer (struct mips_integer_op *,
 206                                         unsigned HOST_WIDE_INT);
 207 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
 208 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
 209 static int m16_check_op (rtx, int, int, int);
 210 static bool mips_rtx_costs (rtx, int, int, int *);
 211 static int mips_address_cost (rtx);
 212 static enum internal_test map_test_to_internal_test (enum rtx_code);
 213 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
 214                                      enum rtx_code *);
 215 static void mips_load_call_address (rtx, rtx, int);
 216 static bool mips_function_ok_for_sibcall (tree, tree);
 217 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
 218 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
 219 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
 220 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
 221                            tree, int, struct mips_arg_info *);
 222 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
 223 static void mips_set_architecture (const struct mips_cpu_info *);
 224 static void mips_set_tune (const struct mips_cpu_info *);
 225 static struct machine_function *mips_init_machine_status (void);
 226 static void print_operand_reloc (FILE *, rtx, const char **);
 227 static bool mips_assemble_integer (rtx, unsigned int, int);
 228 static void mips_file_start (void);
 229 static void mips_file_end (void);
 230 static bool mips_rewrite_small_data_p (rtx);
 231 static int small_data_pattern_1 (rtx *, void *);
 232 static int mips_rewrite_small_data_1 (rtx *, void *);
 233 static bool mips_function_has_gp_insn (void);
 234 static unsigned int mips_global_pointer (void);
 235 static bool mips_save_reg_p (unsigned int);
 236 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
 237                                    mips_save_restore_fn);
 238 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
 239 static void mips_output_cplocal (void);
 240 static void mips_emit_loadgp (void);
 241 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
 242 static void mips_set_frame_expr (rtx);
 243 static rtx mips_frame_set (rtx, rtx);
 244 static void mips_save_reg (rtx, rtx);
 245 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
 246 static void mips_restore_reg (rtx, rtx);
 247 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
 248                                   HOST_WIDE_INT, tree);
 249 static int symbolic_expression_p (rtx);
 250 static void mips_select_rtx_section (enum machine_mode, rtx,
 251                                      unsigned HOST_WIDE_INT);
 252 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
 253                                   ATTRIBUTE_UNUSED;
 254 static bool mips_in_small_data_p (tree);
 255 static void mips_encode_section_info (tree, rtx, int);
 256 static int mips_fpr_return_fields (tree, tree *);
 257 static bool mips_return_in_msb (tree);
 258 static rtx mips_return_fpr_pair (enum machine_mode mode,
 259                                  enum machine_mode mode1, HOST_WIDE_INT,
 260                                  enum machine_mode mode2, HOST_WIDE_INT);
 261 static rtx mips16_gp_pseudo_reg (void);
 262 static void mips16_fp_args (FILE *, int, int);
 263 static void build_mips16_function_stub (FILE *);
 264 static rtx add_constant (struct constant **, rtx, enum machine_mode);
 265 static void dump_constants (struct constant *, rtx);
 266 static rtx mips_find_symbol (rtx);
 267 static void mips16_lay_out_constants (void);
 268 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
 269 static void mips_avoid_hazards (void);
 270 static void mips_reorg (void);
 271 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
 272 static bool mips_matching_cpu_name_p (const char *, const char *);
 273 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 274 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
 275 static int mips_adjust_cost (rtx, rtx, rtx, int);
 276 static bool mips_return_in_memory (tree, tree);
 277 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
 278 static int mips_issue_rate (void);
 279 static int mips_use_dfa_pipeline_interface (void);
 280 static void mips_init_libfuncs (void);
 281 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
 282                                          tree, int *, int);
 283 static tree mips_build_builtin_va_list (void);
 284
 285 #if TARGET_IRIX
 286 static void irix_asm_named_section_1 (const char *, unsigned int,
 287                                       unsigned int);
 288 static void irix_asm_named_section (const char *, unsigned int);
 289 static int irix_section_align_entry_eq (const void *, const void *);
 290 static hashval_t irix_section_align_entry_hash (const void *);
 291 static void irix_file_start (void);
 292 static int irix_section_align_1 (void **, void *);
 293 static void copy_file_data (FILE *, FILE *);
 294 static void irix_file_end (void);
 295 static unsigned int irix_section_type_flags (tree, const char *, int);
 296 #endif
 297
 298 /* Structure to be filled in by compute_frame_size with register
 299    save masks, and offsets for the current function.  */
 300
 301 struct mips_frame_info GTY(())
 302 {
 303   HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */
 304   HOST_WIDE_INT var_size;       /* # bytes that variables take up */
 305   HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */
 306   HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
 307   HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */
 308   HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */
 309   unsigned int mask;            /* mask of saved gp registers */
 310   unsigned int fmask;           /* mask of saved fp registers */
 311   HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
 312   HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
 313   HOST_WIDE_INT gp_sp_offset;   /* offset from new sp to store gp registers */
 314   HOST_WIDE_INT fp_sp_offset;   /* offset from new sp to store fp registers */
 315   bool initialized;             /* true if frame size already calculated */
 316   int num_gp;                   /* number of gp registers saved */
 317   int num_fp;                   /* number of fp registers saved */
 318 };
 319
 320 struct machine_function GTY(()) {
 321   /* Pseudo-reg holding the address of the current function when
 322      generating embedded PIC code.  */
 323   rtx embedded_pic_fnaddr_rtx;
 324
 325   /* Pseudo-reg holding the value of $28 in a mips16 function which
 326      refers to GP relative global variables.  */
 327   rtx mips16_gp_pseudo_rtx;
 328
 329   /* Current frame information, calculated by compute_frame_size.  */
 330   struct mips_frame_info frame;
 331
 332   /* Length of instructions in function; mips16 only.  */
 333   long insns_len;
 334
 335   /* The register to use as the global pointer within this function.  */
 336   unsigned int global_pointer;
 337
 338   /* True if mips_adjust_insn_length should ignore an instruction's
 339      hazard attribute.  */
 340   bool ignore_hazard_length_p;
 341
 342   /* True if the whole function is suitable for .set noreorder and
 343      .set nomacro.  */
 344   bool all_noreorder_p;
 345
 346   /* True if the function is known to have an instruction that needs $gp.  */
 347   bool has_gp_insn_p;
 348 };
 349
 350 /* Information about a single argument.  */
 351 struct mips_arg_info
 352 {
 353   /* True if the argument is passed in a floating-point register, or
 354      would have been if we hadn't run out of registers.  */
 355   bool fpr_p;
 356
 357   /* The argument's size, in bytes.  */
 358   unsigned int num_bytes;
 359
 360   /* The number of words passed in registers, rounded up.  */
 361   unsigned int reg_words;
 362
 363   /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
 364      or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
 365      on the stack.  */
 366   unsigned int reg_offset;
 367
 368   /* The number of words that must be passed on the stack, rounded up.  */
 369   unsigned int stack_words;
 370
 371   /* The offset from the start of the stack overflow area of the argument's
 372      first stack word.  Only meaningful when STACK_WORDS is nonzero.  */
 373   unsigned int stack_offset;
 374 };
 375
 376
 377 /* Information about an address described by mips_address_type.
 378
 379    ADDRESS_CONST_INT
 380        No fields are used.
 381
 382    ADDRESS_REG
 383        REG is the base register and OFFSET is the constant offset.
 384
 385    ADDRESS_LO_SUM
 386        REG is the register that contains the high part of the address,
 387        OFFSET is the symbolic address being referenced and SYMBOL_TYPE
 388        is the type of OFFSET's symbol.
 389
 390    ADDRESS_SYMBOLIC
 391        SYMBOL_TYPE is the type of symbol being referenced.  */
 392
 393 struct mips_address_info
 394 {
 395   enum mips_address_type type;
 396   rtx reg;
 397   rtx offset;
 398   enum mips_symbol_type symbol_type;
 399 };
 400
 401
 402 /* One stage in a constant building sequence.  These sequences have
 403    the form:
 404
 405         A = VALUE[0]
 406         A = A CODE[1] VALUE[1]
 407         A = A CODE[2] VALUE[2]
 408         ...
 409
 410    where A is an accumulator, each CODE[i] is a binary rtl operation
 411    and each VALUE[i] is a constant integer.  */
 412 struct mips_integer_op {
 413   enum rtx_code code;
 414   unsigned HOST_WIDE_INT value;
 415 };
 416
 417
 418 /* The largest number of operations needed to load an integer constant.
 419    The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
 420    When the lowest bit is clear, we can try, but reject a sequence with
 421    an extra SLL at the end.  */
 422 #define MIPS_MAX_INTEGER_OPS 7
 423
 424
 425 /* Global variables for machine-dependent things.  */
 426
 427 /* Threshold for data being put into the small data/bss area, instead
 428    of the normal data area.  */
 429 int mips_section_threshold = -1;
 430
 431 /* Count the number of .file directives, so that .loc is up to date.  */
 432 int num_source_filenames = 0;
 433
 434 /* Count the number of sdb related labels are generated (to find block
 435    start and end boundaries).  */
 436 int sdb_label_count = 0;
 437
 438 /* Next label # for each statement for Silicon Graphics IRIS systems.  */
 439 int sym_lineno = 0;
 440
 441 /* Linked list of all externals that are to be emitted when optimizing
 442    for the global pointer if they haven't been declared by the end of
 443    the program with an appropriate .comm or initialization.  */
 444
 445 struct extern_list GTY (())
 446 {
 447   struct extern_list *next;     /* next external */
 448   const char *name;             /* name of the external */
 449   int size;                     /* size in bytes */
 450 };
 451
 452 static GTY (()) struct extern_list *extern_head = 0;
 453
 454 /* Name of the file containing the current function.  */
 455 const char *current_function_file = "";
 456
 457 /* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
 458 int set_noreorder;
 459 int set_noat;
 460 int set_nomacro;
 461 int set_volatile;
 462
 463 /* The next branch instruction is a branch likely, not branch normal.  */
 464 int mips_branch_likely;
 465
 466 /* Cached operands, and operator to compare for use in set/branch/trap
 467    on condition codes.  */
 468 rtx branch_cmp[2];
 469
 470 /* what type of branch to use */
 471 enum cmp_type branch_type;
 472
 473 /* The target cpu for code generation.  */
 474 enum processor_type mips_arch;
 475 const struct mips_cpu_info *mips_arch_info;
 476
 477 /* The target cpu for optimization and scheduling.  */
 478 enum processor_type mips_tune;
 479 const struct mips_cpu_info *mips_tune_info;
 480
 481 /* Which instruction set architecture to use.  */
 482 int mips_isa;
 483
 484 /* Which ABI to use.  */
 485 int mips_abi;
 486
 487 /* Strings to hold which cpu and instruction set architecture to use.  */
 488 const char *mips_arch_string;   /* for -march=<xxx> */
 489 const char *mips_tune_string;   /* for -mtune=<xxx> */
 490 const char *mips_isa_string;    /* for -mips{1,2,3,4} */
 491 const char *mips_abi_string;    /* for -mabi={32,n32,64,eabi} */
 492
 493 /* Whether we are generating mips16 hard float code.  In mips16 mode
 494    we always set TARGET_SOFT_FLOAT; this variable is nonzero if
 495    -msoft-float was not specified by the user, which means that we
 496    should arrange to call mips32 hard floating point code.  */
 497 int mips16_hard_float;
 498
 499 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
 500
 501 /* If TRUE, we split addresses into their high and low parts in the RTL.  */
 502 int mips_split_addresses;
 503
 504 /* Mode used for saving/restoring general purpose registers.  */
 505 static enum machine_mode gpr_mode;
 506
 507 /* Array giving truth value on whether or not a given hard register
 508    can support a given mode.  */
 509 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
 510
 511 /* The length of all strings seen when compiling for the mips16.  This
 512    is used to tell how many strings are in the constant pool, so that
 513    we can see if we may have an overflow.  This is reset each time the
 514    constant pool is output.  */
 515 int mips_string_length;
 516
 517 /* When generating mips16 code, a list of all strings that are to be
 518    output after the current function.  */
 519
 520 static GTY(()) rtx mips16_strings;
 521
 522 /* In mips16 mode, we build a list of all the string constants we see
 523    in a particular function.  */
 524
 525 struct string_constant
 526 {
 527   struct string_constant *next;
 528   const char *label;
 529 };
 530
 531 static struct string_constant *string_constants;
 532
 533 /* List of all MIPS punctuation characters used by print_operand.  */
 534 char mips_print_operand_punct[256];
 535
 536 /* Map GCC register number to debugger register number.  */
 537 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
 538
 539 /* A copy of the original flag_delayed_branch: see override_options.  */
 540 static int mips_flag_delayed_branch;
 541
 542 static GTY (()) int mips_output_filename_first_time = 1;
 543
 544 /* mips_split_p[X] is true if symbols of type X can be split by
 545    mips_split_symbol().  */
 546 static bool mips_split_p[NUM_SYMBOL_TYPES];
 547
 548 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
 549    appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or
 550    if they are matched by a special .md file pattern.  */
 551 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
 552
 553 /* Likewise for HIGHs.  */
 554 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
 555
 556 /* Hardware names for the registers.  If -mrnames is used, this
 557    will be overwritten with mips_sw_reg_names.  */
 558
 559 char mips_reg_names[][8] =
 560 {
 561  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
 562  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
 563  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
 564  "$24",  "$25",  "$26",  "$27",  "$28",  "$sp",  "$fp",  "$31",
 565  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
 566  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
 567  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
 568  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
 569  "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
 570  "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
 571  "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
 572  "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
 573  "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
 574  "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
 575  "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
 576  "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
 577  "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
 578  "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
 579  "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
 580  "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
 581  "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
 582  "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
 583 };
 584
 585 /* Mips software names for the registers, used to overwrite the
 586    mips_reg_names array.  */
 587
 588 char mips_sw_reg_names[][8] =
 589 {
 590   "$zero","$at",  "$v0",  "$v1",  "$a0",  "$a1",  "$a2",  "$a3",
 591   "$t0",  "$t1",  "$t2",  "$t3",  "$t4",  "$t5",  "$t6",  "$t7",
 592   "$s0",  "$s1",  "$s2",  "$s3",  "$s4",  "$s5",  "$s6",  "$s7",
 593   "$t8",  "$t9",  "$k0",  "$k1",  "$gp",  "$sp",  "$fp",  "$ra",
 594   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
 595   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
 596   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
 597   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
 598   "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
 599   "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
 600   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
 601   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
 602   "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
 603   "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
 604   "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
 605   "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
 606   "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
 607   "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
 608   "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
 609   "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
 610   "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
 611   "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
 612 };
 613
 614 /* Map hard register number to register class */
 615 const enum reg_class mips_regno_to_class[] =
 616 {
 617   LEA_REGS,     LEA_REGS,       M16_NA_REGS,    M16_NA_REGS,
 618   M16_REGS,     M16_REGS,       M16_REGS,       M16_REGS,
 619   LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
 620   LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
 621   M16_NA_REGS,  M16_NA_REGS,    LEA_REGS,       LEA_REGS,
 622   LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
 623   T_REG,        PIC_FN_ADDR_REG, LEA_REGS,      LEA_REGS,
 624   LEA_REGS,     LEA_REGS,       LEA_REGS,       LEA_REGS,
 625   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 626   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 627   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 628   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 629   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 630   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 631   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 632   FP_REGS,      FP_REGS,        FP_REGS,        FP_REGS,
 633   HI_REG,       LO_REG,         NO_REGS,        ST_REGS,
 634   ST_REGS,      ST_REGS,        ST_REGS,        ST_REGS,
 635   ST_REGS,      ST_REGS,        ST_REGS,        NO_REGS,
 636   NO_REGS,      ALL_REGS,       ALL_REGS,       NO_REGS,
 637   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 638   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 639   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 640   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 641   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 642   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 643   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 644   COP0_REGS,    COP0_REGS,      COP0_REGS,      COP0_REGS,
 645   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 646   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 647   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 648   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 649   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 650   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 651   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 652   COP2_REGS,    COP2_REGS,      COP2_REGS,      COP2_REGS,
 653   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 654   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 655   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 656   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 657   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 658   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 659   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS,
 660   COP3_REGS,    COP3_REGS,      COP3_REGS,      COP3_REGS
 661 };
 662
 663 /* Map register constraint character to register class.  */
 664 enum reg_class mips_char_to_class[256];
 665 \f
 666 /* A table describing all the processors gcc knows about.  Names are
 667    matched in the order listed.  The first mention of an ISA level is
 668    taken as the canonical name for that ISA.
 669
 670    To ease comparison, please keep this table in the same order as
 671    gas's mips_cpu_info_table[].  */
 672 const struct mips_cpu_info mips_cpu_info_table[] = {
 673   /* Entries for generic ISAs */
 674   { "mips1", PROCESSOR_R3000, 1 },
 675   { "mips2", PROCESSOR_R6000, 2 },
 676   { "mips3", PROCESSOR_R4000, 3 },
 677   { "mips4", PROCESSOR_R8000, 4 },
 678   { "mips32", PROCESSOR_4KC, 32 },
 679   { "mips32r2", PROCESSOR_M4K, 33 },
 680   { "mips64", PROCESSOR_5KC, 64 },
 681
 682   /* MIPS I */
 683   { "r3000", PROCESSOR_R3000, 1 },
 684   { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
 685   { "r3900", PROCESSOR_R3900, 1 },
 686
 687   /* MIPS II */
 688   { "r6000", PROCESSOR_R6000, 2 },
 689
 690   /* MIPS III */
 691   { "r4000", PROCESSOR_R4000, 3 },
 692   { "vr4100", PROCESSOR_R4100, 3 },
 693   { "vr4111", PROCESSOR_R4111, 3 },
 694   { "vr4120", PROCESSOR_R4120, 3 },
 695   { "vr4300", PROCESSOR_R4300, 3 },
 696   { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
 697   { "r4600", PROCESSOR_R4600, 3 },
 698   { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
 699   { "r4650", PROCESSOR_R4650, 3 },
 700
 701   /* MIPS IV */
 702   { "r8000", PROCESSOR_R8000, 4 },
 703   { "vr5000", PROCESSOR_R5000, 4 },
 704   { "vr5400", PROCESSOR_R5400, 4 },
 705   { "vr5500", PROCESSOR_R5500, 4 },
 706   { "rm7000", PROCESSOR_R7000, 4 },
 707   { "rm9000", PROCESSOR_R9000, 4 },
 708
 709   /* MIPS32 */
 710   { "4kc", PROCESSOR_4KC, 32 },
 711   { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
 712
 713   /* MIPS32 Release 2 */
 714   { "m4k", PROCESSOR_M4K, 33 },
 715
 716   /* MIPS64 */
 717   { "5kc", PROCESSOR_5KC, 64 },
 718   { "20kc", PROCESSOR_20KC, 64 },
 719   { "sb1", PROCESSOR_SB1, 64 },
 720   { "sr71000", PROCESSOR_SR71000, 64 },
 721
 722   /* End marker */
 723   { 0, 0, 0 }
 724 };
 725 \f
 726 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT.  */
 727 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
 728 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
 729 #endif
 730 \f
 731 /* Initialize the GCC target structure.  */
 732 #undef TARGET_ASM_ALIGNED_HI_OP
 733 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
 734 #undef TARGET_ASM_ALIGNED_SI_OP
 735 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
 736 #undef TARGET_ASM_INTEGER
 737 #define TARGET_ASM_INTEGER mips_assemble_integer
 738
 739 #undef TARGET_ASM_FUNCTION_PROLOGUE
 740 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
 741 #undef TARGET_ASM_FUNCTION_EPILOGUE
 742 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
 743 #undef TARGET_ASM_SELECT_RTX_SECTION
 744 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
 745
 746 #undef TARGET_SCHED_ADJUST_COST
 747 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
 748 #undef TARGET_SCHED_ISSUE_RATE
 749 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
 750 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
 751 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
 752
 753 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 754 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
 755
 756 #undef TARGET_VALID_POINTER_MODE
 757 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
 758 #undef TARGET_RTX_COSTS
 759 #define TARGET_RTX_COSTS mips_rtx_costs
 760 #undef TARGET_ADDRESS_COST
 761 #define TARGET_ADDRESS_COST mips_address_cost
 762
 763 #undef TARGET_ENCODE_SECTION_INFO
 764 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
 765 #undef TARGET_IN_SMALL_DATA_P
 766 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
 767
 768 #undef TARGET_MACHINE_DEPENDENT_REORG
 769 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
 770
 771 #undef TARGET_ASM_FILE_START
 772 #undef TARGET_ASM_FILE_END
 773 #if TARGET_IRIX
 774 #define TARGET_ASM_FILE_START irix_file_start
 775 #define TARGET_ASM_FILE_END irix_file_end
 776 #else
 777 #define TARGET_ASM_FILE_START mips_file_start
 778 #define TARGET_ASM_FILE_END mips_file_end
 779 #endif
 780 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
 781 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
 782
 783 #if TARGET_IRIX
 784 #undef TARGET_SECTION_TYPE_FLAGS
 785 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
 786 #endif
 787
 788 #undef TARGET_INIT_LIBFUNCS
 789 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
 790
 791 #undef TARGET_BUILD_BUILTIN_VA_LIST
 792 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
 793
 794 #undef TARGET_PROMOTE_FUNCTION_ARGS
 795 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
 796 #undef TARGET_PROMOTE_FUNCTION_RETURN
 797 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
 798 #undef TARGET_PROMOTE_PROTOTYPES
 799 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
 800
 801 #undef TARGET_RETURN_IN_MEMORY
 802 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
 803 #undef TARGET_RETURN_IN_MSB
 804 #define TARGET_RETURN_IN_MSB mips_return_in_msb
 805
 806 #undef TARGET_ASM_OUTPUT_MI_THUNK
 807 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
 808 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
 809 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
 810
 811 #undef TARGET_SETUP_INCOMING_VARARGS
 812 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
 813 #undef TARGET_STRICT_ARGUMENT_NAMING
 814 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
 815
 816 struct gcc_target targetm = TARGET_INITIALIZER;
 817 \f
 818 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF.  */
 819
 820 static enum mips_symbol_type
 821 mips_classify_symbol (rtx x)
 822 {
 823   if (GET_CODE (x) == LABEL_REF)
 824     return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
 825
 826   if (GET_CODE (x) != SYMBOL_REF)
 827     abort ();
 828
 829   if (CONSTANT_POOL_ADDRESS_P (x))
 830     {
 831       if (TARGET_MIPS16)
 832         return SYMBOL_CONSTANT_POOL;
 833
 834       if (TARGET_ABICALLS)
 835         return SYMBOL_GOT_LOCAL;
 836
 837       if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
 838         return SYMBOL_SMALL_DATA;
 839
 840       return SYMBOL_GENERAL;
 841     }
 842
 843   if (SYMBOL_REF_SMALL_P (x))
 844     return SYMBOL_SMALL_DATA;
 845
 846   /* When generating mips16 code, SYMBOL_REF_FLAG indicates a string
 847      in the current function's constant pool.  */
 848   if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
 849     return SYMBOL_CONSTANT_POOL;
 850
 851   if (TARGET_ABICALLS)
 852     {
 853       if (SYMBOL_REF_DECL (x) == 0)
 854         return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
 855
 856       /* There are three cases to consider:
 857
 858             - o32 PIC (either with or without explicit relocs)
 859             - n32/n64 PIC without explicit relocs
 860             - n32/n64 PIC with explicit relocs
 861
 862          In the first case, both local and global accesses will use an
 863          R_MIPS_GOT16 relocation.  We must correctly predict which of
 864          the two semantics (local or global) the assembler and linker
 865          will apply.  The choice doesn't depend on the symbol's
 866          visibility, so we deliberately ignore decl_visibility and
 867          binds_local_p here.
 868
 869          In the second case, the assembler will not use R_MIPS_GOT16
 870          relocations, but it chooses between local and global accesses
 871          in the same way as for o32 PIC.
 872
 873          In the third case we have more freedom since both forms of
 874          access will work for any kind of symbol.  However, there seems
 875          little point in doing things differently.  */
 876       if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
 877         return SYMBOL_GOT_GLOBAL;
 878
 879       return SYMBOL_GOT_LOCAL;
 880     }
 881
 882   return SYMBOL_GENERAL;
 883 }
 884
 885
 886 /* Split X into a base and a constant offset, storing them in *BASE
 887    and *OFFSET respectively.  */
 888
 889 static void
 890 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
 891 {
 892   *offset = 0;
 893
 894   if (GET_CODE (x) == CONST)
 895     x = XEXP (x, 0);
 896
 897   if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
 898     {
 899       *offset += INTVAL (XEXP (x, 1));
 900       x = XEXP (x, 0);
 901     }
 902   *base = x;
 903 }
 904
 905
 906 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
 907    to the same object as SYMBOL.  */
 908
 909 static bool
 910 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
 911 {
 912   if (GET_CODE (symbol) != SYMBOL_REF)
 913     return false;
 914
 915   if (CONSTANT_POOL_ADDRESS_P (symbol)
 916       && offset >= 0
 917       && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
 918     return true;
 919
 920   if (SYMBOL_REF_DECL (symbol) != 0
 921       && offset >= 0
 922       && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
 923     return true;
 924
 925   return false;
 926 }
 927
 928
 929 /* Return true if X is a symbolic constant that can be calculated in
 930    the same way as a bare symbol.  If it is, store the type of the
 931    symbol in *SYMBOL_TYPE.  */
 932
 933 static bool
 934 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
 935 {
 936   HOST_WIDE_INT offset;
 937
 938   mips_split_const (x, &x, &offset);
 939   if (UNSPEC_ADDRESS_P (x))
 940     *symbol_type = UNSPEC_ADDRESS_TYPE (x);
 941   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
 942     *symbol_type = mips_classify_symbol (x);
 943   else
 944     return false;
 945
 946   if (offset == 0)
 947     return true;
 948
 949   /* Check whether a nonzero offset is valid for the underlying
 950      relocations.  */
 951   switch (*symbol_type)
 952     {
 953     case SYMBOL_GENERAL:
 954       /* If the target has 64-bit pointers and the object file only
 955          supports 32-bit symbols, the values of those symbols will be
 956          sign-extended.  In this case we can't allow an arbitrary offset
 957          in case the 32-bit value X + OFFSET has a different sign from X.  */
 958       if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
 959         return mips_offset_within_object_p (x, offset);
 960
 961       /* In other cases the relocations can handle any offset.  */
 962       return true;
 963
 964     case SYMBOL_SMALL_DATA:
 965     case SYMBOL_CONSTANT_POOL:
 966       /* Make sure that the offset refers to something within the
 967          underlying object.  This should guarantee that the final
 968          PC- or GP-relative offset is within the 16-bit limit.  */
 969       return mips_offset_within_object_p (x, offset);
 970
 971     case SYMBOL_GOT_LOCAL:
 972     case SYMBOL_GOTOFF_PAGE:
 973       /* The linker should provide enough local GOT entries for a
 974          16-bit offset.  Larger offsets may lead to GOT overflow.  */
 975       return SMALL_OPERAND (offset);
 976
 977     case SYMBOL_GOT_GLOBAL:
 978     case SYMBOL_GOTOFF_GLOBAL:
 979     case SYMBOL_GOTOFF_CALL:
 980     case SYMBOL_GOTOFF_LOADGP:
 981       return false;
 982     }
 983   abort ();
 984 }
 985
 986
 987 /* This function is used to implement REG_MODE_OK_FOR_BASE_P.  */
 988
 989 int
 990 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
 991 {
 992   if (regno >= FIRST_PSEUDO_REGISTER)
 993     {
 994       if (!strict)
 995         return true;
 996       regno = reg_renumber[regno];
 997     }
 998
 999   /* These fake registers will be eliminated to either the stack or
1000      hard frame pointer, both of which are usually valid base registers.
1001      Reload deals with the cases where the eliminated form isn't valid.  */
1002   if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1003     return true;
1004
1005   /* In mips16 mode, the stack pointer can only address word and doubleword
1006      values, nothing smaller.  There are two problems here:
1007
1008        (a) Instantiating virtual registers can introduce new uses of the
1009            stack pointer.  If these virtual registers are valid addresses,
1010            the stack pointer should be too.
1011
1012        (b) Most uses of the stack pointer are not made explicit until
1013            FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1014            We don't know until that stage whether we'll be eliminating to the
1015            stack pointer (which needs the restriction) or the hard frame
1016            pointer (which doesn't).
1017
1018      All in all, it seems more consistent to only enforce this restriction
1019      during and after reload.  */
1020   if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1021     return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1022
1023   return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1024 }
1025
1026
1027 /* Return true if X is a valid base register for the given mode.
1028    Allow only hard registers if STRICT.  */
1029
1030 static bool
1031 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1032 {
1033   if (!strict && GET_CODE (x) == SUBREG)
1034     x = SUBREG_REG (x);
1035
1036   return (GET_CODE (x) == REG
1037           && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1038 }
1039
1040
1041 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1042    with mode MODE.  This is used for both symbolic and LO_SUM addresses.  */
1043
1044 static bool
1045 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1046                          enum machine_mode mode)
1047 {
1048   switch (symbol_type)
1049     {
1050     case SYMBOL_GENERAL:
1051       return !TARGET_MIPS16;
1052
1053     case SYMBOL_SMALL_DATA:
1054       return true;
1055
1056     case SYMBOL_CONSTANT_POOL:
1057       /* PC-relative addressing is only available for lw, sw, ld and sd.  */
1058       return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1059
1060     case SYMBOL_GOT_LOCAL:
1061       return true;
1062
1063     case SYMBOL_GOT_GLOBAL:
1064       /* The address will have to be loaded from the GOT first.  */
1065       return false;
1066
1067     case SYMBOL_GOTOFF_PAGE:
1068     case SYMBOL_GOTOFF_GLOBAL:
1069     case SYMBOL_GOTOFF_CALL:
1070     case SYMBOL_GOTOFF_LOADGP:
1071       return true;
1072     }
1073   abort ();
1074 }
1075
1076
1077 /* Return true if X is a valid address for machine mode MODE.  If it is,
1078    fill in INFO appropriately.  STRICT is true if we should only accept
1079    hard base registers.  */
1080
1081 static bool
1082 mips_classify_address (struct mips_address_info *info, rtx x,
1083                        enum machine_mode mode, int strict)
1084 {
1085   switch (GET_CODE (x))
1086     {
1087     case REG:
1088     case SUBREG:
1089       info->type = ADDRESS_REG;
1090       info->reg = x;
1091       info->offset = const0_rtx;
1092       return mips_valid_base_register_p (info->reg, mode, strict);
1093
1094     case PLUS:
1095       info->type = ADDRESS_REG;
1096       info->reg = XEXP (x, 0);
1097       info->offset = XEXP (x, 1);
1098       return (mips_valid_base_register_p (info->reg, mode, strict)
1099               && const_arith_operand (info->offset, VOIDmode));
1100
1101     case LO_SUM:
1102       info->type = ADDRESS_LO_SUM;
1103       info->reg = XEXP (x, 0);
1104       info->offset = XEXP (x, 1);
1105       return (mips_valid_base_register_p (info->reg, mode, strict)
1106               && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1107               && mips_symbolic_address_p (info->symbol_type, mode)
1108               && mips_lo_relocs[info->symbol_type] != 0);
1109
1110     case CONST_INT:
1111       /* Small-integer addresses don't occur very often, but they
1112          are legitimate if $0 is a valid base register.  */
1113       info->type = ADDRESS_CONST_INT;
1114       return !TARGET_MIPS16 && SMALL_INT (x);
1115
1116     case CONST:
1117     case LABEL_REF:
1118     case SYMBOL_REF:
1119       info->type = ADDRESS_SYMBOLIC;
1120       return (mips_symbolic_constant_p (x, &info->symbol_type)
1121               && mips_symbolic_address_p (info->symbol_type, mode)
1122               && !mips_split_p[info->symbol_type]);
1123
1124     default:
1125       return false;
1126     }
1127 }
1128 \f
1129 /* Return the number of instructions needed to load a symbol of the
1130    given type into a register.  If valid in an address, the same number
1131    of instructions are needed for loads and stores.  Treat extended
1132    mips16 instructions as two instructions.  */
1133
1134 static int
1135 mips_symbol_insns (enum mips_symbol_type type)
1136 {
1137   switch (type)
1138     {
1139     case SYMBOL_GENERAL:
1140       /* In mips16 code, general symbols must be fetched from the
1141          constant pool.  */
1142       if (TARGET_MIPS16)
1143         return 0;
1144
1145       /* When using 64-bit symbols, we need 5 preparatory instructions,
1146          such as:
1147
1148              lui     $at,%highest(symbol)
1149              daddiu  $at,$at,%higher(symbol)
1150              dsll    $at,$at,16
1151              daddiu  $at,$at,%hi(symbol)
1152              dsll    $at,$at,16
1153
1154          The final address is then $at + %lo(symbol).  With 32-bit
1155          symbols we just need a preparatory lui.  */
1156       return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1157
1158     case SYMBOL_SMALL_DATA:
1159       return 1;
1160
1161     case SYMBOL_CONSTANT_POOL:
1162       /* This case is for mips16 only.  Assume we'll need an
1163          extended instruction.  */
1164       return 2;
1165
1166     case SYMBOL_GOT_LOCAL:
1167     case SYMBOL_GOT_GLOBAL:
1168       /* Unless -funit-at-a-time is in effect, we can't be sure whether
1169          the local/global classification is accurate.  See override_options
1170          for details.
1171
1172          The worst cases are:
1173
1174          (1) For local symbols when generating o32 or o64 code.  The assembler
1175              will use:
1176
1177                  lw           $at,%got(symbol)
1178                  nop
1179
1180              ...and the final address will be $at + %lo(symbol).
1181
1182          (2) For global symbols when -mxgot.  The assembler will use:
1183
1184                  lui     $at,%got_hi(symbol)
1185                  (d)addu $at,$at,$gp
1186
1187              ...and the final address will be $at + %got_lo(symbol).  */
1188       return 3;
1189
1190     case SYMBOL_GOTOFF_PAGE:
1191     case SYMBOL_GOTOFF_GLOBAL:
1192     case SYMBOL_GOTOFF_CALL:
1193     case SYMBOL_GOTOFF_LOADGP:
1194       /* Check whether the offset is a 16- or 32-bit value.  */
1195       return mips_split_p[type] ? 2 : 1;
1196     }
1197   abort ();
1198 }
1199
1200
1201 /* Return true if a value at OFFSET bytes from BASE can be accessed
1202    using an unextended mips16 instruction.  MODE is the mode of the
1203    value.
1204
1205    Usually the offset in an unextended instruction is a 5-bit field.
1206    The offset is unsigned and shifted left once for HIs, twice
1207    for SIs, and so on.  An exception is SImode accesses off the
1208    stack pointer, which have an 8-bit immediate field.  */
1209
1210 static bool
1211 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1212 {
1213   if (TARGET_MIPS16
1214       && GET_CODE (offset) == CONST_INT
1215       && INTVAL (offset) >= 0
1216       && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1217     {
1218       if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1219         return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1220       return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1221     }
1222   return false;
1223 }
1224
1225
1226 /* Return the number of instructions needed to load or store a value
1227    of mode MODE at X.  Return 0 if X isn't valid for MODE.
1228
1229    For mips16 code, count extended instructions as two instructions.  */
1230
1231 int
1232 mips_address_insns (rtx x, enum machine_mode mode)
1233 {
1234   struct mips_address_info addr;
1235   int factor;
1236
1237   /* Each word of a multi-word value will be accessed individually.  */
1238   factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1239   if (mips_classify_address (&addr, x, mode, false))
1240     switch (addr.type)
1241       {
1242       case ADDRESS_REG:
1243         if (TARGET_MIPS16
1244             && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1245           return factor * 2;
1246         return factor;
1247
1248       case ADDRESS_LO_SUM:
1249         return (TARGET_MIPS16 ? factor * 2 : factor);
1250
1251       case ADDRESS_CONST_INT:
1252         return factor;
1253
1254       case ADDRESS_SYMBOLIC:
1255         return factor * mips_symbol_insns (addr.symbol_type);
1256       }
1257   return 0;
1258 }
1259
1260
1261 /* Likewise for constant X.  */
1262
1263 int
1264 mips_const_insns (rtx x)
1265 {
1266   struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1267   enum mips_symbol_type symbol_type;
1268   HOST_WIDE_INT offset;
1269
1270   switch (GET_CODE (x))
1271     {
1272     case CONSTANT_P_RTX:
1273       return 1;
1274
1275     case HIGH:
1276       if (TARGET_MIPS16
1277           || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1278           || !mips_split_p[symbol_type])
1279         return 0;
1280
1281       return 1;
1282
1283     case CONST_INT:
1284       if (TARGET_MIPS16)
1285         /* Unsigned 8-bit constants can be loaded using an unextended
1286            LI instruction.  Unsigned 16-bit constants can be loaded
1287            using an extended LI.  Negative constants must be loaded
1288            using LI and then negated.  */
1289         return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1290                 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1291                 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1292                 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1293                 : 0);
1294
1295       return mips_build_integer (codes, INTVAL (x));
1296
1297     case CONST_DOUBLE:
1298       return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1299
1300     case CONST:
1301       if (CONST_GP_P (x))
1302         return 1;
1303
1304       /* See if we can refer to X directly.  */
1305       if (mips_symbolic_constant_p (x, &symbol_type))
1306         return mips_symbol_insns (symbol_type);
1307
1308       /* Otherwise try splitting the constant into a base and offset.
1309          16-bit offsets can be added using an extra addiu.  Larger offsets
1310          must be calculated separately and then added to the base.  */
1311       mips_split_const (x, &x, &offset);
1312       if (offset != 0)
1313         {
1314           int n = mips_const_insns (x);
1315           if (n != 0)
1316             {
1317               if (SMALL_OPERAND (offset))
1318                 return n + 1;
1319               else
1320                 return n + 1 + mips_build_integer (codes, offset);
1321             }
1322         }
1323       return 0;
1324
1325     case SYMBOL_REF:
1326     case LABEL_REF:
1327       return mips_symbol_insns (mips_classify_symbol (x));
1328
1329     default:
1330       return 0;
1331     }
1332 }
1333
1334
1335 /* Return the number of instructions needed for memory reference X.
1336    Count extended mips16 instructions as two instructions.  */
1337
1338 int
1339 mips_fetch_insns (rtx x)
1340 {
1341   if (GET_CODE (x) != MEM)
1342     abort ();
1343
1344   return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1345 }
1346
1347
1348 /* Return truth value of whether OP can be used as an operands
1349    where a register or 16 bit unsigned integer is needed.  */
1350
1351 int
1352 uns_arith_operand (rtx op, enum machine_mode mode)
1353 {
1354   if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1355     return 1;
1356
1357   return register_operand (op, mode);
1358 }
1359
1360
1361 /* True if OP can be treated as a signed 16-bit constant.  */
1362
1363 int
1364 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1365 {
1366   return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1367 }
1368
1369
1370 /* Return true if OP is a register operand or a signed 16-bit constant.  */
1371
1372 int
1373 arith_operand (rtx op, enum machine_mode mode)
1374 {
1375   return const_arith_operand (op, mode) || register_operand (op, mode);
1376 }
1377
1378 /* Return truth value of whether OP is an integer which fits in 16 bits.  */
1379
1380 int
1381 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1382 {
1383   return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1384 }
1385
1386 /* Return truth value of whether OP is a register or the constant 0.
1387    Do not accept 0 in mips16 mode since $0 is not one of the core 8
1388    registers.  */
1389
1390 int
1391 reg_or_0_operand (rtx op, enum machine_mode mode)
1392 {
1393   switch (GET_CODE (op))
1394     {
1395     case CONST_INT:
1396       if (TARGET_MIPS16)
1397         return 0;
1398       return INTVAL (op) == 0;
1399
1400     case CONST_DOUBLE:
1401       if (TARGET_MIPS16)
1402         return 0;
1403       return op == CONST0_RTX (mode);
1404
1405     default:
1406       return register_operand (op, mode);
1407     }
1408 }
1409
1410 /* Accept a register or the floating point constant 1 in the appropriate mode.  */
1411
1412 int
1413 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1414 {
1415   REAL_VALUE_TYPE d;
1416
1417   switch (GET_CODE (op))
1418     {
1419     case CONST_DOUBLE:
1420       if (mode != GET_MODE (op)
1421           || (mode != DFmode && mode != SFmode))
1422         return 0;
1423
1424       REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1425       return REAL_VALUES_EQUAL (d, dconst1);
1426
1427     default:
1428       return register_operand (op, mode);
1429     }
1430 }
1431
1432 /* Accept the floating point constant 1 in the appropriate mode.  */
1433
1434 int
1435 const_float_1_operand (rtx op, enum machine_mode mode)
1436 {
1437   REAL_VALUE_TYPE d;
1438
1439   if (GET_CODE (op) != CONST_DOUBLE
1440       || mode != GET_MODE (op)
1441       || (mode != DFmode && mode != SFmode))
1442     return 0;
1443
1444   REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1445
1446   return REAL_VALUES_EQUAL (d, dconst1);
1447 }
1448
1449 /* Return true if OP is either the HI or LO register.  */
1450
1451 int
1452 hilo_operand (rtx op, enum machine_mode mode)
1453 {
1454   return ((mode == VOIDmode || mode == GET_MODE (op))
1455           && REG_P (op) && MD_REG_P (REGNO (op)));
1456 }
1457
1458 /* Return true if OP is an extension operator.  */
1459
1460 int
1461 extend_operator (rtx op, enum machine_mode mode)
1462 {
1463   return ((mode == VOIDmode || mode == GET_MODE (op))
1464           && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1465 }
1466
1467 /* Return nonzero if the code of this rtx pattern is EQ or NE.  */
1468
1469 int
1470 equality_op (rtx op, enum machine_mode mode)
1471 {
1472   if (mode != GET_MODE (op))
1473     return 0;
1474
1475   return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1476 }
1477
1478 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1479
1480 int
1481 cmp_op (rtx op, enum machine_mode mode)
1482 {
1483   if (mode != GET_MODE (op))
1484     return 0;
1485
1486   return GET_RTX_CLASS (GET_CODE (op)) == '<';
1487 }
1488
1489 /* Return nonzero if the code is a relational operation suitable for a
1490    conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1491    We need this in the insn that expands `trap_if' in order to prevent
1492    combine from erroneously altering the condition.  */
1493
1494 int
1495 trap_cmp_op (rtx op, enum machine_mode mode)
1496 {
1497   if (mode != GET_MODE (op))
1498     return 0;
1499
1500   switch (GET_CODE (op))
1501     {
1502     case EQ:
1503     case NE:
1504     case LT:
1505     case LTU:
1506     case GE:
1507     case GEU:
1508       return 1;
1509
1510     default:
1511       return 0;
1512     }
1513 }
1514
1515 /* Return nonzero if the operand is either the PC or a label_ref.  */
1516
1517 int
1518 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1519 {
1520   if (op == pc_rtx)
1521     return 1;
1522
1523   if (GET_CODE (op) == LABEL_REF)
1524     return 1;
1525
1526   return 0;
1527 }
1528
1529 /* Test for a valid call address.  */
1530
1531 int
1532 call_insn_operand (rtx op, enum machine_mode mode)
1533 {
1534   enum mips_symbol_type symbol_type;
1535
1536   if (mips_symbolic_constant_p (op, &symbol_type))
1537     switch (symbol_type)
1538       {
1539       case SYMBOL_GENERAL:
1540         /* If -mlong-calls, force all calls to use register addressing.  */
1541         return !TARGET_LONG_CALLS;
1542
1543       case SYMBOL_GOT_GLOBAL:
1544         /* Without explicit relocs, there is no special syntax for
1545            loading the address of a call destination into a register.
1546            Using "la $25,foo; jal $25" would prevent the lazy binding
1547            of "foo", so keep the address of global symbols with the
1548            jal macro.  */
1549         return !TARGET_EXPLICIT_RELOCS;
1550
1551       default:
1552         return false;
1553       }
1554   return register_operand (op, mode);
1555 }
1556
1557
1558 /* Return nonzero if OP is valid as a source operand for a move
1559    instruction.  */
1560
1561 int
1562 move_operand (rtx op, enum machine_mode mode)
1563 {
1564   enum mips_symbol_type symbol_type;
1565
1566   if (!general_operand (op, mode))
1567     return false;
1568
1569   switch (GET_CODE (op))
1570     {
1571     case CONST_INT:
1572       /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1573          CONST_INTs that can't be loaded using simple insns.  */
1574       if (TARGET_MIPS16)
1575         return true;
1576
1577       /* Otherwise check whether the constant can be loaded in a single
1578          instruction.  */
1579       return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1580
1581     case CONST:
1582     case SYMBOL_REF:
1583     case LABEL_REF:
1584       if (CONST_GP_P (op))
1585         return true;
1586
1587       return (mips_symbolic_constant_p (op, &symbol_type)
1588               && !mips_split_p[symbol_type]);
1589
1590     default:
1591       return true;
1592     }
1593 }
1594
1595
1596 /* Accept any operand that can appear in a mips16 constant table
1597    instruction.  We can't use any of the standard operand functions
1598    because for these instructions we accept values that are not
1599    accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs.  */
1600
1601 int
1602 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1603 {
1604   return CONSTANT_P (op);
1605 }
1606
1607 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1608    possibly with an offset.  */
1609
1610 int
1611 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1612 {
1613   enum mips_symbol_type symbol_type;
1614
1615   return mips_symbolic_constant_p (op, &symbol_type);
1616 }
1617
1618
1619 /* Return true if we're generating PIC and OP is a global symbol.  */
1620
1621 int
1622 global_got_operand (rtx op, enum machine_mode mode)
1623 {
1624   enum mips_symbol_type symbol_type;
1625
1626   return ((mode == VOIDmode || mode == GET_MODE (op))
1627           && mips_symbolic_constant_p (op, &symbol_type)
1628           && symbol_type == SYMBOL_GOT_GLOBAL);
1629 }
1630
1631
1632 /* Likewise for local symbols.  */
1633
1634 int
1635 local_got_operand (rtx op, enum machine_mode mode)
1636 {
1637   enum mips_symbol_type symbol_type;
1638
1639   return ((mode == VOIDmode || mode == GET_MODE (op))
1640           && mips_symbolic_constant_p (op, &symbol_type)
1641           && symbol_type == SYMBOL_GOT_LOCAL);
1642 }
1643
1644
1645 /* Return true if OP is a memory reference that uses the stack pointer
1646    as a base register.  */
1647
1648 int
1649 stack_operand (rtx op, enum machine_mode mode)
1650 {
1651   struct mips_address_info addr;
1652
1653   return ((mode == VOIDmode || mode == GET_MODE (op))
1654           && GET_CODE (op) == MEM
1655           && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1656           && addr.type == ADDRESS_REG
1657           && addr.reg == stack_pointer_rtx);
1658 }
1659
1660
1661 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS.  It
1662    returns a nonzero value if X is a legitimate address for a memory
1663    operand of the indicated MODE.  STRICT is nonzero if this function
1664    is called during reload.  */
1665
1666 bool
1667 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1668 {
1669   struct mips_address_info addr;
1670
1671   return mips_classify_address (&addr, x, mode, strict);
1672 }
1673
1674
1675 /* Copy VALUE to a register and return that register.  If new psuedos
1676    are allowed, copy it into a new register, otherwise use DEST.  */
1677
1678 static rtx
1679 mips_force_temporary (rtx dest, rtx value)
1680 {
1681   if (!no_new_pseudos)
1682     return force_reg (Pmode, value);
1683   else
1684     {
1685       emit_move_insn (copy_rtx (dest), value);
1686       return dest;
1687     }
1688 }
1689
1690
1691 /* Return a LO_SUM expression for ADDR.  TEMP is as for mips_force_temporary
1692    and is used to load the high part into a register.  */
1693
1694 static rtx
1695 mips_split_symbol (rtx temp, rtx addr)
1696 {
1697   rtx high;
1698
1699   if (TARGET_MIPS16)
1700     high = mips16_gp_pseudo_reg ();
1701   else
1702     high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1703   return gen_rtx_LO_SUM (Pmode, high, addr);
1704 }
1705
1706
1707 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1708    type SYMBOL_TYPE.  */
1709
1710 static rtx
1711 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1712 {
1713   rtx base;
1714   HOST_WIDE_INT offset;
1715
1716   mips_split_const (address, &base, &offset);
1717   base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1718                          UNSPEC_ADDRESS_FIRST + symbol_type);
1719   return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1720 }
1721
1722
1723 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1724    high part to BASE and return the result.  Just return BASE otherwise.
1725    TEMP is available as a temporary register if needed.
1726
1727    The returned expression can be used as the first operand to a LO_SUM.  */
1728
1729 static rtx
1730 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1731                          enum mips_symbol_type symbol_type)
1732 {
1733   if (mips_split_p[symbol_type])
1734     {
1735       addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1736       addr = mips_force_temporary (temp, addr);
1737       return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1738     }
1739   return base;
1740 }
1741
1742
1743 /* Return the offset of a GOT page entry for local address ADDR.  */
1744
1745 rtx
1746 mips_gotoff_page (rtx addr)
1747 {
1748   return mips_unspec_address (addr, SYMBOL_GOTOFF_PAGE);
1749 }
1750
1751
1752 /* Return the offset of ADDR's GOT entry from _gp.  ADDR is a
1753    global_got_operand.  */
1754
1755 rtx
1756 mips_gotoff_global (rtx addr)
1757 {
1758   return mips_unspec_address (addr, SYMBOL_GOTOFF_GLOBAL);
1759 }
1760
1761
1762 /* Return a legitimate address for REG + OFFSET.  This function will
1763    create a temporary register if OFFSET is not a SMALL_OPERAND.  */
1764
1765 static rtx
1766 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1767 {
1768   if (!SMALL_OPERAND (offset))
1769     reg = expand_simple_binop (GET_MODE (reg), PLUS,
1770                                GEN_INT (CONST_HIGH_PART (offset)),
1771                                reg, NULL, 0, OPTAB_WIDEN);
1772
1773   return plus_constant (reg, CONST_LOW_PART (offset));
1774 }
1775
1776
1777 /* This function is used to implement LEGITIMIZE_ADDRESS.  If *XLOC can
1778    be legitimized in a way that the generic machinery might not expect,
1779    put the new address in *XLOC and return true.  MODE is the mode of
1780    the memory being accessed.  */
1781
1782 bool
1783 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1784 {
1785   enum mips_symbol_type symbol_type;
1786
1787   /* See if the address can split into a high part and a LO_SUM.  */
1788   if (mips_symbolic_constant_p (*xloc, &symbol_type)
1789       && mips_symbolic_address_p (symbol_type, mode)
1790       && mips_split_p[symbol_type])
1791     {
1792       *xloc = mips_split_symbol (0, *xloc);
1793       return true;
1794     }
1795
1796   if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1797     {
1798       /* Handle REG + CONSTANT using mips_add_offset.  */
1799       rtx reg;
1800
1801       reg = XEXP (*xloc, 0);
1802       if (!mips_valid_base_register_p (reg, mode, 0))
1803         reg = copy_to_mode_reg (Pmode, reg);
1804       *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1805       return true;
1806     }
1807
1808   return false;
1809 }
1810
1811
1812 /* Subroutine of mips_build_integer (with the same interface).
1813    Assume that the final action in the sequence should be a left shift.  */
1814
1815 static unsigned int
1816 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1817 {
1818   unsigned int i, shift;
1819
1820   /* Shift VALUE right until its lowest bit is set.  Shift arithmetically
1821      since signed numbers are easier to load than unsigned ones.  */
1822   shift = 0;
1823   while ((value & 1) == 0)
1824     value /= 2, shift++;
1825
1826   i = mips_build_integer (codes, value);
1827   codes[i].code = ASHIFT;
1828   codes[i].value = shift;
1829   return i + 1;
1830 }
1831
1832
1833 /* As for mips_build_shift, but assume that the final action will be
1834    an IOR or PLUS operation.  */
1835
1836 static unsigned int
1837 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1838 {
1839   unsigned HOST_WIDE_INT high;
1840   unsigned int i;
1841
1842   high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1843   if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1844     {
1845       /* The constant is too complex to load with a simple lui/ori pair
1846          so our goal is to clear as many trailing zeros as possible.
1847          In this case, we know bit 16 is set and that the low 16 bits
1848          form a negative number.  If we subtract that number from VALUE,
1849          we will clear at least the lowest 17 bits, maybe more.  */
1850       i = mips_build_integer (codes, CONST_HIGH_PART (value));
1851       codes[i].code = PLUS;
1852       codes[i].value = CONST_LOW_PART (value);
1853     }
1854   else
1855     {
1856       i = mips_build_integer (codes, high);
1857       codes[i].code = IOR;
1858       codes[i].value = value & 0xffff;
1859     }
1860   return i + 1;
1861 }
1862
1863
1864 /* Fill CODES with a sequence of rtl operations to load VALUE.
1865    Return the number of operations needed.  */
1866
1867 static unsigned int
1868 mips_build_integer (struct mips_integer_op *codes,
1869                     unsigned HOST_WIDE_INT value)
1870 {
1871   if (SMALL_OPERAND (value)
1872       || SMALL_OPERAND_UNSIGNED (value)
1873       || LUI_OPERAND (value))
1874     {
1875       /* The value can be loaded with a single instruction.  */
1876       codes[0].code = NIL;
1877       codes[0].value = value;
1878       return 1;
1879     }
1880   else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1881     {
1882       /* Either the constant is a simple LUI/ORI combination or its
1883          lowest bit is set.  We don't want to shift in this case.  */
1884       return mips_build_lower (codes, value);
1885     }
1886   else if ((value & 0xffff) == 0)
1887     {
1888       /* The constant will need at least three actions.  The lowest
1889          16 bits are clear, so the final action will be a shift.  */
1890       return mips_build_shift (codes, value);
1891     }
1892   else
1893     {
1894       /* The final action could be a shift, add or inclusive OR.
1895          Rather than use a complex condition to select the best
1896          approach, try both mips_build_shift and mips_build_lower
1897          and pick the one that gives the shortest sequence.
1898          Note that this case is only used once per constant.  */
1899       struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1900       unsigned int cost, alt_cost;
1901
1902       cost = mips_build_shift (codes, value);
1903       alt_cost = mips_build_lower (alt_codes, value);
1904       if (alt_cost < cost)
1905         {
1906           memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1907           cost = alt_cost;
1908         }
1909       return cost;
1910     }
1911 }
1912
1913
1914 /* Move VALUE into register DEST.  */
1915
1916 static void
1917 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1918 {
1919   struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1920   enum machine_mode mode;
1921   unsigned int i, cost;
1922   rtx x;
1923
1924   mode = GET_MODE (dest);
1925   cost = mips_build_integer (codes, value);
1926
1927   /* Apply each binary operation to X.  Invariant: X is a legitimate
1928      source operand for a SET pattern.  */
1929   x = GEN_INT (codes[0].value);
1930   for (i = 1; i < cost; i++)
1931     {
1932       if (no_new_pseudos)
1933         emit_move_insn (dest, x), x = dest;
1934       else
1935         x = force_reg (mode, x);
1936       x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1937     }
1938
1939   emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1940 }
1941
1942
1943 /* Subroutine of mips_legitimize_move.  Move constant SRC into register
1944    DEST given that SRC satisfies immediate_operand but doesn't satisfy
1945    move_operand.  */
1946
1947 static void
1948 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1949 {
1950   rtx base;
1951   HOST_WIDE_INT offset;
1952   enum mips_symbol_type symbol_type;
1953
1954   /* Split moves of big integers into smaller pieces.  In mips16 code,
1955      it's better to force the constant into memory instead.  */
1956   if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1957     {
1958       mips_move_integer (dest, INTVAL (src));
1959       return;
1960     }
1961
1962   /* See if the symbol can be split.  For mips16, this is often worse than
1963      forcing it in the constant pool since it needs the single-register form
1964      of addiu or daddiu.  */
1965   if (!TARGET_MIPS16
1966       && mips_symbolic_constant_p (src, &symbol_type)
1967       && mips_split_p[symbol_type])
1968     {
1969       emit_move_insn (dest, mips_split_symbol (dest, src));
1970       return;
1971     }
1972
1973   /* If we have (const (plus symbol offset)), load the symbol first
1974      and then add in the offset.  This is usually better than forcing
1975      the constant into memory, at least in non-mips16 code.  */
1976   mips_split_const (src, &base, &offset);
1977   if (!TARGET_MIPS16
1978       && offset != 0
1979       && (!no_new_pseudos || SMALL_OPERAND (offset)))
1980     {
1981       base = mips_force_temporary (dest, base);
1982       emit_move_insn (dest, mips_add_offset (base, offset));
1983       return;
1984     }
1985
1986   src = force_const_mem (mode, src);
1987
1988   /* When using explicit relocs, constant pool references are sometimes
1989      not legitimate addresses.  */
1990   if (!memory_operand (src, VOIDmode))
1991     src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1992   emit_move_insn (dest, src);
1993 }
1994
1995
1996 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1997    sequence that is valid.  */
1998
1999 bool
2000 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2001 {
2002   if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2003     {
2004       emit_move_insn (dest, force_reg (mode, src));
2005       return true;
2006     }
2007
2008   /* The source of an SImode move must be a move_operand.  Likewise
2009      DImode moves on 64-bit targets.  We need to deal with constants
2010      that would be legitimate immediate_operands but not legitimate
2011      move_operands.  */
2012   if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2013       && CONSTANT_P (src)
2014       && !move_operand (src, mode))
2015     {
2016       mips_legitimize_const_move (mode, dest, src);
2017       set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2018       return true;
2019     }
2020   return false;
2021 }
2022 \f
2023 /* We need a lot of little routines to check constant values on the
2024    mips16.  These are used to figure out how long the instruction will
2025    be.  It would be much better to do this using constraints, but
2026    there aren't nearly enough letters available.  */
2027
2028 static int
2029 m16_check_op (rtx op, int low, int high, int mask)
2030 {
2031   return (GET_CODE (op) == CONST_INT
2032           && INTVAL (op) >= low
2033           && INTVAL (op) <= high
2034           && (INTVAL (op) & mask) == 0);
2035 }
2036
2037 int
2038 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2039 {
2040   return m16_check_op (op, 0x1, 0x8, 0);
2041 }
2042
2043 int
2044 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2045 {
2046   return m16_check_op (op, - 0x8, 0x7, 0);
2047 }
2048
2049 int
2050 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2051 {
2052   return m16_check_op (op, - 0x7, 0x8, 0);
2053 }
2054
2055 int
2056 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2057 {
2058   return m16_check_op (op, - 0x10, 0xf, 0);
2059 }
2060
2061 int
2062 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2063 {
2064   return m16_check_op (op, - 0xf, 0x10, 0);
2065 }
2066
2067 int
2068 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2069 {
2070   return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2071 }
2072
2073 int
2074 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2075 {
2076   return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2077 }
2078
2079 int
2080 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2081 {
2082   return m16_check_op (op, - 0x80, 0x7f, 0);
2083 }
2084
2085 int
2086 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2087 {
2088   return m16_check_op (op, - 0x7f, 0x80, 0);
2089 }
2090
2091 int
2092 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2093 {
2094   return m16_check_op (op, 0x0, 0xff, 0);
2095 }
2096
2097 int
2098 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2099 {
2100   return m16_check_op (op, - 0xff, 0x0, 0);
2101 }
2102
2103 int
2104 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2105 {
2106   return m16_check_op (op, - 0x1, 0xfe, 0);
2107 }
2108
2109 int
2110 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2111 {
2112   return m16_check_op (op, 0x0, 0xff << 2, 3);
2113 }
2114
2115 int
2116 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2117 {
2118   return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2119 }
2120
2121 int
2122 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2123 {
2124   return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2125 }
2126
2127 int
2128 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2129 {
2130   return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2131 }
2132
2133 /* References to the string table on the mips16 only use a small
2134    offset if the function is small.  We can't check for LABEL_REF here,
2135    because the offset is always large if the label is before the
2136    referencing instruction.  */
2137
2138 int
2139 m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2140 {
2141   if (GET_CODE (op) == SYMBOL_REF
2142       && SYMBOL_REF_FLAG (op)
2143       && cfun->machine->insns_len > 0
2144       && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2145           < 4 * 0x100))
2146     {
2147       struct string_constant *l;
2148
2149       /* Make sure this symbol is on thelist of string constants to be
2150          output for this function.  It is possible that it has already
2151          been output, in which case this requires a large offset.  */
2152       for (l = string_constants; l != NULL; l = l->next)
2153         if (strcmp (l->label, XSTR (op, 0)) == 0)
2154           return 1;
2155     }
2156
2157   return 0;
2158 }
2159
2160 int
2161 m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2162 {
2163   if (GET_CODE (op) == SYMBOL_REF
2164       && SYMBOL_REF_FLAG (op)
2165       && cfun->machine->insns_len > 0
2166       && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2167           < 4 * 0x20))
2168     {
2169       struct string_constant *l;
2170
2171       /* Make sure this symbol is on thelist of string constants to be
2172          output for this function.  It is possible that it has already
2173          been output, in which case this requires a large offset.  */
2174       for (l = string_constants; l != NULL; l = l->next)
2175         if (strcmp (l->label, XSTR (op, 0)) == 0)
2176           return 1;
2177     }
2178
2179   return 0;
2180 }
2181 \f
2182 static bool
2183 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2184 {
2185   enum machine_mode mode = GET_MODE (x);
2186
2187   switch (code)
2188     {
2189     case CONST_INT:
2190       if (!TARGET_MIPS16)
2191         {
2192           /* Always return 0, since we don't have different sized
2193              instructions, hence different costs according to Richard
2194              Kenner */
2195           *total = 0;
2196           return true;
2197         }
2198
2199       /* A number between 1 and 8 inclusive is efficient for a shift.
2200          Otherwise, we will need an extended instruction.  */
2201       if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2202           || (outer_code) == LSHIFTRT)
2203         {
2204           if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2205             *total = 0;
2206           else
2207             *total = COSTS_N_INSNS (1);
2208           return true;
2209         }
2210
2211       /* We can use cmpi for an xor with an unsigned 16 bit value.  */
2212       if ((outer_code) == XOR
2213           && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2214         {
2215           *total = 0;
2216           return true;
2217         }
2218
2219       /* We may be able to use slt or sltu for a comparison with a
2220          signed 16 bit value.  (The boundary conditions aren't quite
2221          right, but this is just a heuristic anyhow.)  */
2222       if (((outer_code) == LT || (outer_code) == LE
2223            || (outer_code) == GE || (outer_code) == GT
2224            || (outer_code) == LTU || (outer_code) == LEU
2225            || (outer_code) == GEU || (outer_code) == GTU)
2226           && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2227         {
2228           *total = 0;
2229           return true;
2230         }
2231
2232       /* Equality comparisons with 0 are cheap.  */
2233       if (((outer_code) == EQ || (outer_code) == NE)
2234           && INTVAL (x) == 0)
2235         {
2236           *total = 0;
2237           return true;
2238         }
2239
2240       /* Otherwise fall through to the handling below.  */
2241
2242     case CONST:
2243     case SYMBOL_REF:
2244     case LABEL_REF:
2245     case CONST_DOUBLE:
2246       if (LEGITIMATE_CONSTANT_P (x))
2247         {
2248           *total = COSTS_N_INSNS (1);
2249           return true;
2250         }
2251       else
2252         {
2253           /* The value will need to be fetched from the constant pool.  */
2254           *total = CONSTANT_POOL_COST;
2255           return true;
2256         }
2257
2258     case MEM:
2259       {
2260         /* If the address is legitimate, return the number of
2261            instructions it needs, otherwise use the default handling.  */
2262         int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2263         if (n > 0)
2264           {
2265             *total = COSTS_N_INSNS (1 + n);
2266             return true;
2267           }
2268         return false;
2269       }
2270
2271     case FFS:
2272       *total = COSTS_N_INSNS (6);
2273       return true;
2274
2275     case NOT:
2276       *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2277       return true;
2278
2279     case AND:
2280     case IOR:
2281     case XOR:
2282       if (mode == DImode && !TARGET_64BIT)
2283         {
2284           *total = COSTS_N_INSNS (2);
2285           return true;
2286         }
2287       return false;
2288
2289     case ASHIFT:
2290     case ASHIFTRT:
2291     case LSHIFTRT:
2292       if (mode == DImode && !TARGET_64BIT)
2293         {
2294           *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2295                                   ? 4 : 12);
2296           return true;
2297         }
2298       return false;
2299
2300     case ABS:
2301       if (mode == SFmode || mode == DFmode)
2302         *total = COSTS_N_INSNS (1);
2303       else
2304         *total = COSTS_N_INSNS (4);
2305       return true;
2306
2307     case LO_SUM:
2308       *total = COSTS_N_INSNS (1);
2309       return true;
2310
2311     case PLUS:
2312     case MINUS:
2313       if (mode == SFmode || mode == DFmode)
2314         {
2315           if (TUNE_MIPS3000 || TUNE_MIPS3900)
2316             *total = COSTS_N_INSNS (2);
2317           else if (TUNE_MIPS6000)
2318             *total = COSTS_N_INSNS (3);
2319           else
2320             *total = COSTS_N_INSNS (6);
2321           return true;
2322         }
2323       if (mode == DImode && !TARGET_64BIT)
2324         {
2325           *total = COSTS_N_INSNS (4);
2326           return true;
2327         }
2328       return false;
2329
2330     case NEG:
2331       if (mode == DImode && !TARGET_64BIT)
2332         {
2333           *total = 4;
2334           return true;
2335         }
2336       return false;
2337
2338     case MULT:
2339       if (mode == SFmode)
2340         {
2341           if (TUNE_MIPS3000
2342               || TUNE_MIPS3900
2343               || TUNE_MIPS5000)
2344             *total = COSTS_N_INSNS (4);
2345           else if (TUNE_MIPS6000
2346                    || TUNE_MIPS5400
2347                    || TUNE_MIPS5500)
2348             *total = COSTS_N_INSNS (5);
2349           else
2350             *total = COSTS_N_INSNS (7);
2351           return true;
2352         }
2353
2354       if (mode == DFmode)
2355         {
2356           if (TUNE_MIPS3000
2357               || TUNE_MIPS3900
2358               || TUNE_MIPS5000)
2359             *total = COSTS_N_INSNS (5);
2360           else if (TUNE_MIPS6000
2361                    || TUNE_MIPS5400
2362                    || TUNE_MIPS5500)
2363             *total = COSTS_N_INSNS (6);
2364           else
2365             *total = COSTS_N_INSNS (8);
2366           return true;
2367         }
2368
2369       if (TUNE_MIPS3000)
2370         *total = COSTS_N_INSNS (12);
2371       else if (TUNE_MIPS3900)
2372         *total = COSTS_N_INSNS (2);
2373       else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2374         *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2375       else if (TUNE_MIPS7000)
2376         *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2377       else if (TUNE_MIPS9000)
2378         *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2379       else if (TUNE_MIPS6000)
2380         *total = COSTS_N_INSNS (17);
2381       else if (TUNE_MIPS5000)
2382         *total = COSTS_N_INSNS (5);
2383       else
2384         *total = COSTS_N_INSNS (10);
2385       return true;
2386
2387     case DIV:
2388     case MOD:
2389       if (mode == SFmode)
2390         {
2391           if (TUNE_MIPS3000
2392               || TUNE_MIPS3900)
2393             *total = COSTS_N_INSNS (12);
2394           else if (TUNE_MIPS6000)
2395             *total = COSTS_N_INSNS (15);
2396           else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2397             *total = COSTS_N_INSNS (30);
2398           else
2399             *total = COSTS_N_INSNS (23);
2400           return true;
2401         }
2402
2403       if (mode == DFmode)
2404         {
2405           if (TUNE_MIPS3000
2406               || TUNE_MIPS3900)
2407             *total = COSTS_N_INSNS (19);
2408           else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2409             *total = COSTS_N_INSNS (59);
2410           else if (TUNE_MIPS6000)
2411             *total = COSTS_N_INSNS (16);
2412           else
2413             *total = COSTS_N_INSNS (36);
2414           return true;
2415         }
2416       /* Fall through.  */
2417
2418     case UDIV:
2419     case UMOD:
2420       if (TUNE_MIPS3000
2421           || TUNE_MIPS3900)
2422         *total = COSTS_N_INSNS (35);
2423       else if (TUNE_MIPS6000)
2424         *total = COSTS_N_INSNS (38);
2425       else if (TUNE_MIPS5000)
2426         *total = COSTS_N_INSNS (36);
2427       else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2428         *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2429       else
2430         *total = COSTS_N_INSNS (69);
2431       return true;
2432
2433     case SIGN_EXTEND:
2434       /* A sign extend from SImode to DImode in 64 bit mode is often
2435          zero instructions, because the result can often be used
2436          directly by another instruction; we'll call it one.  */
2437       if (TARGET_64BIT && mode == DImode
2438           && GET_MODE (XEXP (x, 0)) == SImode)
2439         *total = COSTS_N_INSNS (1);
2440       else
2441         *total = COSTS_N_INSNS (2);
2442       return true;
2443
2444     case ZERO_EXTEND:
2445       if (TARGET_64BIT && mode == DImode
2446           && GET_MODE (XEXP (x, 0)) == SImode)
2447         *total = COSTS_N_INSNS (2);
2448       else
2449         *total = COSTS_N_INSNS (1);
2450       return true;
2451
2452     default:
2453       return false;
2454     }
2455 }
2456
2457 /* Provide the costs of an addressing mode that contains ADDR.
2458    If ADDR is not a valid address, its cost is irrelevant.  */
2459
2460 static int
2461 mips_address_cost (rtx addr)
2462 {
2463   return mips_address_insns (addr, SImode);
2464 }
2465 \f
2466 /* Return a pseudo that points to the address of the current function.
2467    The first time it is called for a function, an initializer for the
2468    pseudo is emitted in the beginning of the function.  */
2469
2470 rtx
2471 embedded_pic_fnaddr_reg (void)
2472 {
2473   if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2474     {
2475       rtx seq;
2476
2477       cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2478
2479       /* Output code at function start to initialize the pseudo-reg.  */
2480       /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2481          inline functions, because it is called after RTL for the function
2482          has been copied.  The pseudo-reg in embedded_pic_fnaddr_rtx however
2483          does not get copied, and ends up not matching the rest of the RTL.
2484          This solution works, but means that we get unnecessary code to
2485          initialize this value every time a function is inlined into another
2486          function.  */
2487       start_sequence ();
2488       emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2489                                  XEXP (DECL_RTL (current_function_decl), 0)));
2490       seq = get_insns ();
2491       end_sequence ();
2492       push_topmost_sequence ();
2493       emit_insn_after (seq, get_insns ());
2494       pop_topmost_sequence ();
2495     }
2496
2497   return cfun->machine->embedded_pic_fnaddr_rtx;
2498 }
2499
2500 /* Return RTL for the offset from the current function to the argument.
2501    X is the symbol whose offset from the current function we want.  */
2502
2503 rtx
2504 embedded_pic_offset (rtx x)
2505 {
2506   /* Make sure it is emitted.  */
2507   embedded_pic_fnaddr_reg ();
2508
2509   return
2510     gen_rtx_CONST (Pmode,
2511                    gen_rtx_MINUS (Pmode, x,
2512                                   XEXP (DECL_RTL (current_function_decl), 0)));
2513 }
2514 \f
2515 /* Return one word of double-word value OP, taking into account the fixed
2516    endianness of certain registers.  HIGH_P is true to select the high part,
2517    false to select the low part.  */
2518
2519 rtx
2520 mips_subword (rtx op, int high_p)
2521 {
2522   unsigned int byte;
2523   enum machine_mode mode;
2524
2525   mode = GET_MODE (op);
2526   if (mode == VOIDmode)
2527     mode = DImode;
2528
2529   if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2530     byte = UNITS_PER_WORD;
2531   else
2532     byte = 0;
2533
2534   if (GET_CODE (op) == REG)
2535     {
2536       if (FP_REG_P (REGNO (op)))
2537         return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2538       if (REGNO (op) == HI_REGNUM)
2539         return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2540     }
2541
2542   if (GET_CODE (op) == MEM)
2543     return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2544
2545   return simplify_gen_subreg (word_mode, op, mode, byte);
2546 }
2547
2548
2549 /* Return true if a 64-bit move from SRC to DEST should be split into two.  */
2550
2551 bool
2552 mips_split_64bit_move_p (rtx dest, rtx src)
2553 {
2554   if (TARGET_64BIT)
2555     return false;
2556
2557   /* FP->FP moves can be done in a single instruction.  */
2558   if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2559     return false;
2560
2561   /* Check for floating-point loads and stores.  They can be done using
2562      ldc1 and sdc1 on MIPS II and above.  */
2563   if (mips_isa > 1)
2564     {
2565       if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2566         return false;
2567       if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2568         return false;
2569     }
2570   return true;
2571 }
2572
2573
2574 /* Split a 64-bit move from SRC to DEST assuming that
2575    mips_split_64bit_move_p holds.
2576
2577    Moves into and out of FPRs cause some difficulty here.  Such moves
2578    will always be DFmode, since paired FPRs are not allowed to store
2579    DImode values.  The most natural representation would be two separate
2580    32-bit moves, such as:
2581
2582         (set (reg:SI $f0) (mem:SI ...))
2583         (set (reg:SI $f1) (mem:SI ...))
2584
2585    However, the second insn is invalid because odd-numbered FPRs are
2586    not allowed to store independent values.  Use the patterns load_df_low,
2587    load_df_high and store_df_high instead.  */
2588
2589 void
2590 mips_split_64bit_move (rtx dest, rtx src)
2591 {
2592   if (FP_REG_RTX_P (dest))
2593     {
2594       /* Loading an FPR from memory or from GPRs.  */
2595       emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2596       emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2597                                    copy_rtx (dest)));
2598     }
2599   else if (FP_REG_RTX_P (src))
2600     {
2601       /* Storing an FPR into memory or GPRs.  */
2602       emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2603       emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2604     }
2605   else
2606     {
2607       /* The operation can be split into two normal moves.  Decide in
2608          which order to do them.  */
2609       rtx low_dest;
2610
2611       low_dest = mips_subword (dest, 0);
2612       if (GET_CODE (low_dest) == REG
2613           && reg_overlap_mentioned_p (low_dest, src))
2614         {
2615           emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2616           emit_move_insn (low_dest, mips_subword (src, 0));
2617         }
2618       else
2619         {
2620           emit_move_insn (low_dest, mips_subword (src, 0));
2621           emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2622         }
2623     }
2624 }
2625 \f
2626 /* Return the appropriate instructions to move SRC into DEST.  Assume
2627    that SRC is operand 1 and DEST is operand 0.  */
2628
2629 const char *
2630 mips_output_move (rtx dest, rtx src)
2631 {
2632   enum rtx_code dest_code, src_code;
2633   bool dbl_p;
2634
2635   dest_code = GET_CODE (dest);
2636   src_code = GET_CODE (src);
2637   dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2638
2639   if (dbl_p && mips_split_64bit_move_p (dest, src))
2640     return "#";
2641
2642   if ((src_code == REG && GP_REG_P (REGNO (src)))
2643       || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2644     {
2645       if (dest_code == REG)
2646         {
2647           if (GP_REG_P (REGNO (dest)))
2648             return "move\t%0,%z1";
2649
2650           if (MD_REG_P (REGNO (dest)))
2651             return "mt%0\t%z1";
2652
2653           if (FP_REG_P (REGNO (dest)))
2654             return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2655
2656           if (ALL_COP_REG_P (REGNO (dest)))
2657             {
2658               static char retval[] = "dmtc_\t%z1,%0";
2659
2660               retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2661               return (dbl_p ? retval : retval + 1);
2662             }
2663         }
2664       if (dest_code == MEM)
2665         return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2666     }
2667   if (dest_code == REG && GP_REG_P (REGNO (dest)))
2668     {
2669       if (src_code == REG)
2670         {
2671           if (MD_REG_P (REGNO (src)))
2672             return "mf%1\t%0";
2673
2674           if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2675             return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2676
2677           if (FP_REG_P (REGNO (src)))
2678             return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2679
2680           if (ALL_COP_REG_P (REGNO (src)))
2681             {
2682               static char retval[] = "dmfc_\t%0,%1";
2683
2684               retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2685               return (dbl_p ? retval : retval + 1);
2686             }
2687         }
2688
2689       if (src_code == MEM)
2690         return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2691
2692       if (src_code == CONST_INT)
2693         {
2694           /* Don't use the X format, because that will give out of
2695              range numbers for 64 bit hosts and 32 bit targets.  */
2696           if (!TARGET_MIPS16)
2697             return "li\t%0,%1\t\t\t# %X1";
2698
2699           if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2700             return "li\t%0,%1";
2701
2702           if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2703             return "li\t%0,%n1\n\tneg\t%0";
2704         }
2705
2706       if (src_code == HIGH)
2707         return "lui\t%0,%h1";
2708
2709       if (CONST_GP_P (src))
2710         return "move\t%0,%1";
2711
2712       if (symbolic_operand (src, VOIDmode))
2713         return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2714     }
2715   if (src_code == REG && FP_REG_P (REGNO (src)))
2716     {
2717       if (dest_code == REG && FP_REG_P (REGNO (dest)))
2718         return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2719
2720       if (dest_code == MEM)
2721         return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2722     }
2723   if (dest_code == REG && FP_REG_P (REGNO (dest)))
2724     {
2725       if (src_code == MEM)
2726         return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2727     }
2728   if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2729     {
2730       static char retval[] = "l_c_\t%0,%1";
2731
2732       retval[1] = (dbl_p ? 'd' : 'w');
2733       retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2734       return retval;
2735     }
2736   if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2737     {
2738       static char retval[] = "s_c_\t%1,%0";
2739
2740       retval[1] = (dbl_p ? 'd' : 'w');
2741       retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2742       return retval;
2743     }
2744   abort ();
2745 }
2746 \f
2747 /* Return an rtx for the gp save slot.  Valid only when using o32 or
2748    o64 abicalls.  */
2749
2750 rtx
2751 mips_gp_save_slot (void)
2752 {
2753   rtx loc;
2754
2755   if (!TARGET_ABICALLS || TARGET_NEWABI)
2756     abort ();
2757
2758   if (frame_pointer_needed)
2759     loc = hard_frame_pointer_rtx;
2760   else
2761     loc = stack_pointer_rtx;
2762   loc = plus_constant (loc, current_function_outgoing_args_size);
2763   loc = gen_rtx_MEM (Pmode, loc);
2764   RTX_UNCHANGING_P (loc) = 1;
2765   return loc;
2766 }
2767 \f
2768 /* Make normal rtx_code into something we can index from an array */
2769
2770 static enum internal_test
2771 map_test_to_internal_test (enum rtx_code test_code)
2772 {
2773   enum internal_test test = ITEST_MAX;
2774
2775   switch (test_code)
2776     {
2777     case EQ:  test = ITEST_EQ;  break;
2778     case NE:  test = ITEST_NE;  break;
2779     case GT:  test = ITEST_GT;  break;
2780     case GE:  test = ITEST_GE;  break;
2781     case LT:  test = ITEST_LT;  break;
2782     case LE:  test = ITEST_LE;  break;
2783     case GTU: test = ITEST_GTU; break;
2784     case GEU: test = ITEST_GEU; break;
2785     case LTU: test = ITEST_LTU; break;
2786     case LEU: test = ITEST_LEU; break;
2787     default:                    break;
2788     }
2789
2790   return test;
2791 }
2792
2793 \f
2794 /* Generate the code to compare two integer values.  The return value is:
2795    (reg:SI xx)          The pseudo register the comparison is in
2796    0                    No register, generate a simple branch.
2797
2798    ??? This is called with result nonzero by the Scond patterns in
2799    mips.md.  These patterns are called with a target in the mode of
2800    the Scond instruction pattern.  Since this must be a constant, we
2801    must use SImode.  This means that if RESULT is nonzero, it will
2802    always be an SImode register, even if TARGET_64BIT is true.  We
2803    cope with this by calling convert_move rather than emit_move_insn.
2804    This will sometimes lead to an unnecessary extension of the result;
2805    for example:
2806
2807    long long
2808    foo (long long i)
2809    {
2810      return i < 5;
2811    }
2812
2813    TEST_CODE is the rtx code for the comparison.
2814    CMP0 and CMP1 are the two operands to compare.
2815    RESULT is the register in which the result should be stored (null for
2816      branches).
2817    For branches, P_INVERT points to an integer that is nonzero on return
2818      if the branch should be inverted.  */
2819
2820 rtx
2821 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2822                     rtx cmp1, int *p_invert)
2823 {
2824   struct cmp_info
2825   {
2826     enum rtx_code test_code;    /* code to use in instruction (LT vs. LTU) */
2827     int const_low;              /* low bound of constant we can accept */
2828     int const_high;             /* high bound of constant we can accept */
2829     int const_add;              /* constant to add (convert LE -> LT) */
2830     int reverse_regs;           /* reverse registers in test */
2831     int invert_const;           /* != 0 if invert value if cmp1 is constant */
2832     int invert_reg;             /* != 0 if invert value if cmp1 is register */
2833     int unsignedp;              /* != 0 for unsigned comparisons.  */
2834   };
2835
2836   static const struct cmp_info info[ (int)ITEST_MAX ] = {
2837
2838     { XOR,       0,  65535,  0,  0,  0,  0, 0 },        /* EQ  */
2839     { XOR,       0,  65535,  0,  0,  1,  1, 0 },        /* NE  */
2840     { LT,   -32769,  32766,  1,  1,  1,  0, 0 },        /* GT  */
2841     { LT,   -32768,  32767,  0,  0,  1,  1, 0 },        /* GE  */
2842     { LT,   -32768,  32767,  0,  0,  0,  0, 0 },        /* LT  */
2843     { LT,   -32769,  32766,  1,  1,  0,  1, 0 },        /* LE  */
2844     { LTU,  -32769,  32766,  1,  1,  1,  0, 1 },        /* GTU */
2845     { LTU,  -32768,  32767,  0,  0,  1,  1, 1 },        /* GEU */
2846     { LTU,  -32768,  32767,  0,  0,  0,  0, 1 },        /* LTU */
2847     { LTU,  -32769,  32766,  1,  1,  0,  1, 1 },        /* LEU */
2848   };
2849
2850   enum internal_test test;
2851   enum machine_mode mode;
2852   const struct cmp_info *p_info;
2853   int branch_p;
2854   int eqne_p;
2855   int invert;
2856   rtx reg;
2857   rtx reg2;
2858
2859   test = map_test_to_internal_test (test_code);
2860   if (test == ITEST_MAX)
2861     abort ();
2862
2863   p_info = &info[(int) test];
2864   eqne_p = (p_info->test_code == XOR);
2865
2866   mode = GET_MODE (cmp0);
2867   if (mode == VOIDmode)
2868     mode = GET_MODE (cmp1);
2869
2870   /* Eliminate simple branches.  */
2871   branch_p = (result == 0);
2872   if (branch_p)
2873     {
2874       if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2875         {
2876           /* Comparisons against zero are simple branches.  */
2877           if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2878               && (! TARGET_MIPS16 || eqne_p))
2879             return 0;
2880
2881           /* Test for beq/bne.  */
2882           if (eqne_p && ! TARGET_MIPS16)
2883             return 0;
2884         }
2885
2886       /* Allocate a pseudo to calculate the value in.  */
2887       result = gen_reg_rtx (mode);
2888     }
2889
2890   /* Make sure we can handle any constants given to us.  */
2891   if (GET_CODE (cmp0) == CONST_INT)
2892     cmp0 = force_reg (mode, cmp0);
2893
2894   if (GET_CODE (cmp1) == CONST_INT)
2895     {
2896       HOST_WIDE_INT value = INTVAL (cmp1);
2897
2898       if (value < p_info->const_low
2899           || value > p_info->const_high
2900           /* ??? Why?  And why wasn't the similar code below modified too?  */
2901           || (TARGET_64BIT
2902               && HOST_BITS_PER_WIDE_INT < 64
2903               && p_info->const_add != 0
2904               && ((p_info->unsignedp
2905                    ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2906                       > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2907                    : (value + p_info->const_add) > INTVAL (cmp1))
2908                   != (p_info->const_add > 0))))
2909         cmp1 = force_reg (mode, cmp1);
2910     }
2911
2912   /* See if we need to invert the result.  */
2913   invert = (GET_CODE (cmp1) == CONST_INT
2914             ? p_info->invert_const : p_info->invert_reg);
2915
2916   if (p_invert != (int *)0)
2917     {
2918       *p_invert = invert;
2919       invert = 0;
2920     }
2921
2922   /* Comparison to constants, may involve adding 1 to change a LT into LE.
2923      Comparison between two registers, may involve switching operands.  */
2924   if (GET_CODE (cmp1) == CONST_INT)
2925     {
2926       if (p_info->const_add != 0)
2927         {
2928           HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2929
2930           /* If modification of cmp1 caused overflow,
2931              we would get the wrong answer if we follow the usual path;
2932              thus, x > 0xffffffffU would turn into x > 0U.  */
2933           if ((p_info->unsignedp
2934                ? (unsigned HOST_WIDE_INT) new >
2935                (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2936                : new > INTVAL (cmp1))
2937               != (p_info->const_add > 0))
2938             {
2939               /* This test is always true, but if INVERT is true then
2940                  the result of the test needs to be inverted so 0 should
2941                  be returned instead.  */
2942               emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2943               return result;
2944             }
2945           else
2946             cmp1 = GEN_INT (new);
2947         }
2948     }
2949
2950   else if (p_info->reverse_regs)
2951     {
2952       rtx temp = cmp0;
2953       cmp0 = cmp1;
2954       cmp1 = temp;
2955     }
2956
2957   if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2958     reg = cmp0;
2959   else
2960     {
2961       reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2962       convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
2963                                          mode, cmp0, cmp1), 0);
2964     }
2965
2966   if (test == ITEST_NE)
2967     {
2968       if (! TARGET_MIPS16)
2969         {
2970           convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
2971           if (p_invert != NULL)
2972             *p_invert = 0;
2973           invert = 0;
2974         }
2975       else
2976         {
2977           reg2 = invert ? gen_reg_rtx (mode) : result;
2978           convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2979           reg = reg2;
2980         }
2981     }
2982
2983   else if (test == ITEST_EQ)
2984     {
2985       reg2 = invert ? gen_reg_rtx (mode) : result;
2986       convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2987       reg = reg2;
2988     }
2989
2990   if (invert)
2991     {
2992       rtx one;
2993
2994       if (! TARGET_MIPS16)
2995         one = const1_rtx;
2996       else
2997         {
2998           /* The value is in $24.  Copy it to another register, so
2999              that reload doesn't think it needs to store the $24 and
3000              the input to the XOR in the same location.  */
3001           reg2 = gen_reg_rtx (mode);
3002           emit_move_insn (reg2, reg);
3003           reg = reg2;
3004           one = force_reg (mode, const1_rtx);
3005         }
3006       convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
3007     }
3008
3009   return result;
3010 }
3011 \f
3012 /* Work out how to check a floating-point condition.  We need a
3013    separate comparison instruction (C.cond.fmt), followed by a
3014    branch or conditional move.  Given that IN_CODE is the
3015    required condition, set *CMP_CODE to the C.cond.fmt code
3016    and *action_code to the branch or move code.  */
3017
3018 static void
3019 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
3020                          enum rtx_code *action_code)
3021 {
3022   switch (in_code)
3023     {
3024     case NE:
3025     case UNGE:
3026     case UNGT:
3027     case LTGT:
3028     case ORDERED:
3029       *cmp_code = reverse_condition_maybe_unordered (in_code);
3030       *action_code = EQ;
3031       break;
3032
3033     default:
3034       *cmp_code = in_code;
3035       *action_code = NE;
3036       break;
3037     }
3038 }
3039
3040 /* Emit the common code for doing conditional branches.
3041    operand[0] is the label to jump to.
3042    The comparison operands are saved away by cmp{si,di,sf,df}.  */
3043
3044 void
3045 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
3046 {
3047   enum cmp_type type = branch_type;
3048   rtx cmp0 = branch_cmp[0];
3049   rtx cmp1 = branch_cmp[1];
3050   enum machine_mode mode;
3051   enum rtx_code cmp_code;
3052   rtx reg;
3053   int invert;
3054   rtx label1, label2;
3055
3056   switch (type)
3057     {
3058     case CMP_SI:
3059     case CMP_DI:
3060       mode = type == CMP_SI ? SImode : DImode;
3061       invert = 0;
3062       reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3063
3064       if (reg)
3065         {
3066           cmp0 = reg;
3067           cmp1 = const0_rtx;
3068           test_code = NE;
3069         }
3070       else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3071         /* We don't want to build a comparison against a nonzero
3072            constant.  */
3073         cmp1 = force_reg (mode, cmp1);
3074
3075       break;
3076
3077     case CMP_SF:
3078     case CMP_DF:
3079       if (! ISA_HAS_8CC)
3080         reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3081       else
3082         reg = gen_reg_rtx (CCmode);
3083
3084       get_float_compare_codes (test_code, &cmp_code, &test_code);
3085       emit_insn (gen_rtx_SET (VOIDmode, reg,
3086                               gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
3087
3088       mode = CCmode;
3089       cmp0 = reg;
3090       cmp1 = const0_rtx;
3091       invert = 0;
3092       break;
3093
3094     default:
3095       fatal_insn ("bad test",
3096                   gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
3097     }
3098
3099   /* Generate the branch.  */
3100
3101   label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3102   label2 = pc_rtx;
3103
3104   if (invert)
3105     {
3106       label2 = label1;
3107       label1 = pc_rtx;
3108     }
3109
3110   emit_jump_insn
3111     (gen_rtx_SET (VOIDmode, pc_rtx,
3112                   gen_rtx_IF_THEN_ELSE (VOIDmode,
3113                                         gen_rtx_fmt_ee (test_code, mode,
3114                                                         cmp0, cmp1),
3115                                         label1, label2)));
3116 }
3117
3118 /* Emit the common code for conditional moves.  OPERANDS is the array
3119    of operands passed to the conditional move define_expand.  */
3120
3121 void
3122 gen_conditional_move (rtx *operands)
3123 {
3124   rtx op0 = branch_cmp[0];
3125   rtx op1 = branch_cmp[1];
3126   enum machine_mode mode = GET_MODE (branch_cmp[0]);
3127   enum rtx_code cmp_code = GET_CODE (operands[1]);
3128   enum rtx_code move_code = NE;
3129   enum machine_mode op_mode = GET_MODE (operands[0]);
3130   enum machine_mode cmp_mode;
3131   rtx cmp_reg;
3132
3133   if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3134     {
3135       switch (cmp_code)
3136         {
3137         case EQ:
3138           cmp_code = XOR;
3139           move_code = EQ;
3140           break;
3141         case NE:
3142           cmp_code = XOR;
3143           break;
3144         case LT:
3145           break;
3146         case GE:
3147           cmp_code = LT;
3148           move_code = EQ;
3149           break;
3150         case GT:
3151           cmp_code = LT;
3152           op0 = force_reg (mode, branch_cmp[1]);
3153           op1 = branch_cmp[0];
3154           break;
3155         case LE:
3156           cmp_code = LT;
3157           op0 = force_reg (mode, branch_cmp[1]);
3158           op1 = branch_cmp[0];
3159           move_code = EQ;
3160           break;
3161         case LTU:
3162           break;
3163         case GEU:
3164           cmp_code = LTU;
3165           move_code = EQ;
3166           break;
3167         case GTU:
3168           cmp_code = LTU;
3169           op0 = force_reg (mode, branch_cmp[1]);
3170           op1 = branch_cmp[0];
3171           break;
3172         case LEU:
3173           cmp_code = LTU;
3174           op0 = force_reg (mode, branch_cmp[1]);
3175           op1 = branch_cmp[0];
3176           move_code = EQ;
3177           break;
3178         default:
3179           abort ();
3180         }
3181     }
3182   else
3183     get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3184
3185   if (mode == SImode || mode == DImode)
3186     cmp_mode = mode;
3187   else if (mode == SFmode || mode == DFmode)
3188     cmp_mode = CCmode;
3189   else
3190     abort ();
3191
3192   cmp_reg = gen_reg_rtx (cmp_mode);
3193   emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3194                           gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
3195
3196   emit_insn (gen_rtx_SET (op_mode, operands[0],
3197                           gen_rtx_IF_THEN_ELSE (op_mode,
3198                                                 gen_rtx_fmt_ee (move_code,
3199                                                                 VOIDmode,
3200                                                                 cmp_reg,
3201                                                                 const0_rtx),
3202                                                 operands[2], operands[3])));
3203 }
3204
3205 /* Emit a conditional trap.  OPERANDS is the array of operands passed to
3206    the conditional_trap expander.  */
3207
3208 void
3209 mips_gen_conditional_trap (rtx *operands)
3210 {
3211   rtx op0, op1;
3212   enum rtx_code cmp_code = GET_CODE (operands[0]);
3213   enum machine_mode mode = GET_MODE (branch_cmp[0]);
3214
3215   /* MIPS conditional trap machine instructions don't have GT or LE
3216      flavors, so we must invert the comparison and convert to LT and
3217      GE, respectively.  */
3218   switch (cmp_code)
3219     {
3220     case GT: cmp_code = LT; break;
3221     case LE: cmp_code = GE; break;
3222     case GTU: cmp_code = LTU; break;
3223     case LEU: cmp_code = GEU; break;
3224     default: break;
3225     }
3226   if (cmp_code == GET_CODE (operands[0]))
3227     {
3228       op0 = force_reg (mode, branch_cmp[0]);
3229       op1 = branch_cmp[1];
3230     }
3231   else
3232     {
3233       op0 = force_reg (mode, branch_cmp[1]);
3234       op1 = branch_cmp[0];
3235     }
3236   if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3237     op1 = force_reg (mode, op1);
3238
3239   emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3240                               gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
3241                                               op0, op1),
3242                               operands[1]));
3243 }
3244 \f
3245 /* Load function address ADDR into register DEST.  SIBCALL_P is true
3246    if the address is needed for a sibling call.  */
3247
3248 static void
3249 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3250 {
3251   /* If we're generating PIC, and this call is to a global function,
3252      try to allow its address to be resolved lazily.  This isn't
3253      possible for NewABI sibcalls since the value of $gp on entry
3254      to the stub would be our caller's gp, not ours.  */
3255   if (TARGET_EXPLICIT_RELOCS
3256       && !(sibcall_p && TARGET_NEWABI)
3257       && global_got_operand (addr, VOIDmode))
3258     {
3259       rtx high, lo_sum_symbol;
3260
3261       high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3262                                       addr, SYMBOL_GOTOFF_CALL);
3263       lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3264       if (Pmode == SImode)
3265         emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3266       else
3267         emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3268     }
3269   else
3270     emit_move_insn (dest, addr);
3271 }
3272
3273
3274 /* Expand a call or call_value instruction.  RESULT is where the
3275    result will go (null for calls), ADDR is the address of the
3276    function, ARGS_SIZE is the size of the arguments and AUX is
3277    the value passed to us by mips_function_arg.  SIBCALL_P is true
3278    if we are expanding a sibling call, false if we're expanding
3279    a normal call.  */
3280
3281 void
3282 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3283 {
3284   rtx orig_addr, pattern, insn;
3285
3286   orig_addr = addr;
3287   if (!call_insn_operand (addr, VOIDmode))
3288     {
3289       addr = gen_reg_rtx (Pmode);
3290       mips_load_call_address (addr, orig_addr, sibcall_p);
3291     }
3292
3293   if (TARGET_MIPS16
3294       && mips16_hard_float
3295       && build_mips16_call_stub (result, addr, args_size,
3296                                  aux == 0 ? 0 : (int) GET_MODE (aux)))
3297     return;
3298
3299   if (result == 0)
3300     pattern = (sibcall_p
3301                ? gen_sibcall_internal (addr, args_size)
3302                : gen_call_internal (addr, args_size));
3303   else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3304     {
3305       rtx reg1, reg2;
3306
3307       reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3308       reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3309       pattern =
3310         (sibcall_p
3311          ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3312          : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3313     }
3314   else
3315     pattern = (sibcall_p
3316                ? gen_sibcall_value_internal (result, addr, args_size)
3317                : gen_call_value_internal (result, addr, args_size));
3318
3319   insn = emit_call_insn (pattern);
3320
3321   /* Lazy-binding stubs require $gp to be valid on entry.  */
3322   if (global_got_operand (orig_addr, VOIDmode))
3323     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3324 }
3325
3326
3327 /* We can handle any sibcall when TARGET_SIBCALLS is true.  */
3328
3329 static bool
3330 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3331                               tree exp ATTRIBUTE_UNUSED)
3332 {
3333   return TARGET_SIBCALLS;
3334 }
3335 \f
3336 /* Return true if operand OP is a condition code register.
3337    Only for use during or after reload.  */
3338
3339 int
3340 fcc_register_operand (rtx op, enum machine_mode mode)
3341 {
3342   return ((mode == VOIDmode || mode == GET_MODE (op))
3343           && (reload_in_progress || reload_completed)
3344           && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3345           && ST_REG_P (true_regnum (op)));
3346 }
3347
3348 /* Emit code to move general operand SRC into condition-code
3349    register DEST.  SCRATCH is a scratch TFmode float register.
3350    The sequence is:
3351
3352         FP1 = SRC
3353         FP2 = 0.0f
3354         DEST = FP2 < FP1
3355
3356    where FP1 and FP2 are single-precision float registers
3357    taken from SCRATCH.  */
3358
3359 void
3360 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3361 {
3362   rtx fp1, fp2;
3363
3364   /* Change the source to SFmode.  */
3365   if (GET_CODE (src) == MEM)
3366     src = adjust_address (src, SFmode, 0);
3367   else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3368     src = gen_rtx_REG (SFmode, true_regnum (src));
3369
3370   fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3371   fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3372
3373   emit_move_insn (copy_rtx (fp1), src);
3374   emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3375   emit_insn (gen_slt_sf (dest, fp2, fp1));
3376 }
3377 \f
3378 /* Emit code to change the current function's return address to
3379    ADDRESS.  SCRATCH is available as a scratch register, if needed.
3380    ADDRESS and SCRATCH are both word-mode GPRs.  */
3381
3382 void
3383 mips_set_return_address (rtx address, rtx scratch)
3384 {
3385   HOST_WIDE_INT gp_offset;
3386
3387   compute_frame_size (get_frame_size ());
3388   if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3389     abort ();
3390   gp_offset = cfun->machine->frame.gp_sp_offset;
3391
3392   /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH.  */
3393   if (gp_offset < 32768)
3394     scratch = plus_constant (stack_pointer_rtx, gp_offset);
3395   else
3396     {
3397       emit_move_insn (scratch, GEN_INT (gp_offset));
3398       if (Pmode == DImode)
3399         emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3400       else
3401         emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3402     }
3403
3404   emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3405 }
3406 \f
3407 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3408    Assume that the areas do not overlap.  */
3409
3410 static void
3411 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3412 {
3413   HOST_WIDE_INT offset, delta;
3414   unsigned HOST_WIDE_INT bits;
3415   int i;
3416   enum machine_mode mode;
3417   rtx *regs;
3418
3419   /* Work out how many bits to move at a time.  If both operands have
3420      half-word alignment, it is usually better to move in half words.
3421      For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3422      and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3423      Otherwise move word-sized chunks.  */
3424   if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3425       && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3426     bits = BITS_PER_WORD / 2;
3427   else
3428     bits = BITS_PER_WORD;
3429
3430   mode = mode_for_size (bits, MODE_INT, 0);
3431   delta = bits / BITS_PER_UNIT;
3432
3433   /* Allocate a buffer for the temporary registers.  */
3434   regs = alloca (sizeof (rtx) * length / delta);
3435
3436   /* Load as many BITS-sized chunks as possible.  Use a normal load if
3437      the source has enough alignment, otherwise use left/right pairs.  */
3438   for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3439     {
3440       rtx part;
3441
3442       regs[i] = gen_reg_rtx (mode);
3443       part = adjust_address (src, mode, offset);
3444       if (MEM_ALIGN (part) >= bits)
3445         emit_move_insn (regs[i], part);
3446       else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3447         abort ();
3448     }
3449
3450   /* Copy the chunks to the destination.  */
3451   for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3452     {
3453       rtx part;
3454
3455       part = adjust_address (dest, mode, offset);
3456       if (MEM_ALIGN (part) >= bits)
3457         emit_move_insn (part, regs[i]);
3458       else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3459         abort ();
3460     }
3461
3462   /* Mop up any left-over bytes.  */
3463   if (offset < length)
3464     {
3465       src = adjust_address (src, mode, offset);
3466       dest = adjust_address (dest, mode, offset);
3467       move_by_pieces (dest, src, length - offset,
3468                       MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3469     }
3470 }
3471 \f
3472 #define MAX_MOVE_REGS 4
3473 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3474
3475
3476 /* Helper function for doing a loop-based block operation on memory
3477    reference MEM.  Each iteration of the loop will operate on LENGTH
3478    bytes of MEM.
3479
3480    Create a new base register for use within the loop and point it to
3481    the start of MEM.  Create a new memory reference that uses this
3482    register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
3483
3484 static void
3485 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3486                        rtx *loop_reg, rtx *loop_mem)
3487 {
3488   *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3489
3490   /* Although the new mem does not refer to a known location,
3491      it does keep up to LENGTH bytes of alignment.  */
3492   *loop_mem = change_address (mem, BLKmode, *loop_reg);
3493   set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3494 }
3495
3496
3497 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3498    per iteration.  LENGTH must be at least MAX_MOVE_BYTES.  Assume that the
3499    memory regions do not overlap.  */
3500
3501 static void
3502 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3503 {
3504   rtx label, src_reg, dest_reg, final_src;
3505   HOST_WIDE_INT leftover;
3506
3507   leftover = length % MAX_MOVE_BYTES;
3508   length -= leftover;
3509
3510   /* Create registers and memory references for use within the loop.  */
3511   mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3512   mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3513
3514   /* Calculate the value that SRC_REG should have after the last iteration
3515      of the loop.  */
3516   final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3517                                    0, 0, OPTAB_WIDEN);
3518
3519   /* Emit the start of the loop.  */
3520   label = gen_label_rtx ();
3521   emit_label (label);
3522
3523   /* Emit the loop body.  */
3524   mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3525
3526   /* Move on to the next block.  */
3527   emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3528   emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3529
3530   /* Emit the loop condition.  */
3531   if (Pmode == DImode)
3532     emit_insn (gen_cmpdi (src_reg, final_src));
3533   else
3534     emit_insn (gen_cmpsi (src_reg, final_src));
3535   emit_jump_insn (gen_bne (label));
3536
3537   /* Mop up any left-over bytes.  */
3538   if (leftover)
3539     mips_block_move_straight (dest, src, leftover);
3540 }
3541 \f
3542 /* Expand a movstrsi instruction.  */
3543
3544 bool
3545 mips_expand_block_move (rtx dest, rtx src, rtx length)
3546 {
3547   if (GET_CODE (length) == CONST_INT)
3548     {
3549       if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3550         {
3551           mips_block_move_straight (dest, src, INTVAL (length));
3552           return true;
3553         }
3554       else if (optimize)
3555         {
3556           mips_block_move_loop (dest, src, INTVAL (length));
3557           return true;
3558         }
3559     }
3560   return false;
3561 }
3562 \f
3563 /* Argument support functions.  */
3564
3565 /* Initialize CUMULATIVE_ARGS for a function.  */
3566
3567 void
3568 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3569                       rtx libname ATTRIBUTE_UNUSED)
3570 {
3571   static CUMULATIVE_ARGS zero_cum;
3572   tree param, next_param;
3573
3574   *cum = zero_cum;
3575   cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3576
3577   /* Determine if this function has variable arguments.  This is
3578      indicated by the last argument being 'void_type_mode' if there
3579      are no variable arguments.  The standard MIPS calling sequence
3580      passes all arguments in the general purpose registers in this case.  */
3581
3582   for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3583        param != 0; param = next_param)
3584     {
3585       next_param = TREE_CHAIN (param);
3586       if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3587         cum->gp_reg_found = 1;
3588     }
3589 }
3590
3591
3592 /* Fill INFO with information about a single argument.  CUM is the
3593    cumulative state for earlier arguments.  MODE is the mode of this
3594    argument and TYPE is its type (if known).  NAMED is true if this
3595    is a named (fixed) argument rather than a variable one.  */
3596
3597 static void
3598 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3599                tree type, int named, struct mips_arg_info *info)
3600 {
3601   bool even_reg_p;
3602   unsigned int num_words, max_regs;
3603
3604   /* Decide whether this argument should go in a floating-point register,
3605      assuming one is free.  Later code checks for availability.  */
3606
3607   info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3608                  && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3609
3610   if (info->fpr_p)
3611     switch (mips_abi)
3612       {
3613       case ABI_32:
3614       case ABI_O64:
3615         info->fpr_p = (!cum->gp_reg_found
3616                        && cum->arg_number < 2
3617                        && (type == 0 || FLOAT_TYPE_P (type)));
3618         break;
3619
3620       case ABI_N32:
3621       case ABI_64:
3622         info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3623         break;
3624       }
3625
3626   /* Now decide whether the argument must go in an even-numbered register.  */
3627
3628   even_reg_p = false;
3629   if (info->fpr_p)
3630     {
3631       /* Under the O64 ABI, the second float argument goes in $f13 if it
3632          is a double, but $f14 if it is a single.  Otherwise, on a
3633          32-bit double-float machine, each FP argument must start in a
3634          new register pair.  */
3635       even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3636                     || (mips_abi == ABI_O64 && mode == SFmode)
3637                     || FP_INC > 1);
3638     }
3639   else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3640     {
3641       if (GET_MODE_CLASS (mode) == MODE_INT
3642           || GET_MODE_CLASS (mode) == MODE_FLOAT)
3643         even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3644
3645       else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3646         even_reg_p = true;
3647     }
3648
3649   if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3650     /* This argument must be passed on the stack.  Eat up all the
3651        remaining registers.  */
3652     info->reg_offset = MAX_ARGS_IN_REGISTERS;
3653   else
3654     {
3655       /* Set REG_OFFSET to the register count we're interested in.
3656          The EABI allocates the floating-point registers separately,
3657          but the other ABIs allocate them like integer registers.  */
3658       info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3659                           ? cum->num_fprs
3660                           : cum->num_gprs);
3661
3662       if (even_reg_p)
3663         info->reg_offset += info->reg_offset & 1;
3664     }
3665
3666   /* The alignment applied to registers is also applied to stack arguments.  */
3667   info->stack_offset = cum->stack_words;
3668   if (even_reg_p)
3669     info->stack_offset += info->stack_offset & 1;
3670
3671   if (mode == BLKmode)
3672     info->num_bytes = int_size_in_bytes (type);
3673   else
3674     info->num_bytes = GET_MODE_SIZE (mode);
3675
3676   num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3677   max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3678
3679   /* Partition the argument between registers and stack.  */
3680   info->reg_words = MIN (num_words, max_regs);
3681   info->stack_words = num_words - info->reg_words;
3682 }
3683
3684
3685 /* Implement FUNCTION_ARG_ADVANCE.  */
3686
3687 void
3688 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3689                       tree type, int named)
3690 {
3691   struct mips_arg_info info;
3692
3693   mips_arg_info (cum, mode, type, named, &info);
3694
3695   if (!info.fpr_p)
3696     cum->gp_reg_found = true;
3697
3698   /* See the comment above the cumulative args structure in mips.h
3699      for an explanation of what this code does.  It assumes the O32
3700      ABI, which passes at most 2 arguments in float registers.  */
3701   if (cum->arg_number < 2 && info.fpr_p)
3702     cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3703
3704   if (mips_abi != ABI_EABI || !info.fpr_p)
3705     cum->num_gprs = info.reg_offset + info.reg_words;
3706   else if (info.reg_words > 0)
3707     cum->num_fprs += FP_INC;
3708
3709   if (info.stack_words > 0)
3710     cum->stack_words = info.stack_offset + info.stack_words;
3711
3712   cum->arg_number++;
3713 }
3714
3715 /* Implement FUNCTION_ARG.  */
3716
3717 struct rtx_def *
3718 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3719               tree type, int named)
3720 {
3721   struct mips_arg_info info;
3722
3723   /* We will be called with a mode of VOIDmode after the last argument
3724      has been seen.  Whatever we return will be passed to the call
3725      insn.  If we need a mips16 fp_code, return a REG with the code
3726      stored as the mode.  */
3727   if (mode == VOIDmode)
3728     {
3729       if (TARGET_MIPS16 && cum->fp_code != 0)
3730         return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3731
3732       else
3733         return 0;
3734     }
3735
3736   mips_arg_info (cum, mode, type, named, &info);
3737
3738   /* Return straight away if the whole argument is passed on the stack.  */
3739   if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3740     return 0;
3741
3742   if (type != 0
3743       && TREE_CODE (type) == RECORD_TYPE
3744       && TARGET_NEWABI
3745       && TYPE_SIZE_UNIT (type)
3746       && host_integerp (TYPE_SIZE_UNIT (type), 1)
3747       && named)
3748     {
3749       /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3750          structure contains a double in its entirety, then that 64 bit
3751          chunk is passed in a floating point register.  */
3752       tree field;
3753
3754       /* First check to see if there is any such field.  */
3755       for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3756         if (TREE_CODE (field) == FIELD_DECL
3757             && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3758             && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3759             && host_integerp (bit_position (field), 0)
3760             && int_bit_position (field) % BITS_PER_WORD == 0)
3761           break;
3762
3763       if (field != 0)
3764         {
3765           /* Now handle the special case by returning a PARALLEL
3766              indicating where each 64 bit chunk goes.  INFO.REG_WORDS
3767              chunks are passed in registers.  */
3768           unsigned int i;
3769           HOST_WIDE_INT bitpos;
3770           rtx ret;
3771
3772           /* assign_parms checks the mode of ENTRY_PARM, so we must
3773              use the actual mode here.  */
3774           ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3775
3776           bitpos = 0;
3777           field = TYPE_FIELDS (type);
3778           for (i = 0; i < info.reg_words; i++)
3779             {
3780               rtx reg;
3781
3782               for (; field; field = TREE_CHAIN (field))
3783                 if (TREE_CODE (field) == FIELD_DECL
3784                     && int_bit_position (field) >= bitpos)
3785                   break;
3786
3787               if (field
3788                   && int_bit_position (field) == bitpos
3789                   && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3790                   && !TARGET_SOFT_FLOAT
3791                   && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3792                 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3793               else
3794                 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3795
3796               XVECEXP (ret, 0, i)
3797                 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3798                                      GEN_INT (bitpos / BITS_PER_UNIT));
3799
3800               bitpos += BITS_PER_WORD;
3801             }
3802           return ret;
3803         }
3804     }
3805
3806   if (info.fpr_p)
3807     return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3808   else
3809     return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3810 }
3811
3812
3813 /* Implement FUNCTION_ARG_PARTIAL_NREGS.  */
3814
3815 int
3816 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3817                             enum machine_mode mode, tree type, int named)
3818 {
3819   struct mips_arg_info info;
3820
3821   mips_arg_info (cum, mode, type, named, &info);
3822   return info.stack_words > 0 ? info.reg_words : 0;
3823 }
3824
3825
3826 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3827    upward rather than downward.  In other words, return true if the
3828    first byte of the stack slot has useful data, false if the last
3829    byte does.  */
3830
3831 bool
3832 mips_pad_arg_upward (enum machine_mode mode, tree type)
3833 {
3834   /* On little-endian targets, the first byte of every stack argument
3835      is passed in the first byte of the stack slot.  */
3836   if (!BYTES_BIG_ENDIAN)
3837     return true;
3838
3839   /* Otherwise, integral types are padded downward: the last byte of a
3840      stack argument is passed in the last byte of the stack slot.  */
3841   if (type != 0
3842       ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3843       : GET_MODE_CLASS (mode) == MODE_INT)
3844     return false;
3845
3846   /* Big-endian o64 pads floating-point arguments downward.  */
3847   if (mips_abi == ABI_O64)
3848     if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3849       return false;
3850
3851   /* Other types are padded upward for o32, o64, n32 and n64.  */
3852   if (mips_abi != ABI_EABI)
3853     return true;
3854
3855   /* Arguments smaller than a stack slot are padded downward.  */
3856   if (mode != BLKmode)
3857     return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3858   else
3859     return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3860 }
3861
3862
3863 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...).  Return !BYTES_BIG_ENDIAN
3864    if the least significant byte of the register has useful data.  Return
3865    the opposite if the most significant byte does.  */
3866
3867 bool
3868 mips_pad_reg_upward (enum machine_mode mode, tree type)
3869 {
3870   /* No shifting is required for floating-point arguments.  */
3871   if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3872     return !BYTES_BIG_ENDIAN;
3873
3874   /* Otherwise, apply the same padding to register arguments as we do
3875      to stack arguments.  */
3876   return mips_pad_arg_upward (mode, type);
3877 }
3878 \f
3879 static void
3880 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3881                              tree type, int *pretend_size, int no_rtl)
3882 {
3883   CUMULATIVE_ARGS local_cum;
3884   int gp_saved, fp_saved;
3885
3886   /* The caller has advanced CUM up to, but not beyond, the last named
3887      argument.  Advance a local copy of CUM past the last "real" named
3888      argument, to find out how many registers are left over.  */
3889
3890   local_cum = *cum;
3891   FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3892
3893   /* Found out how many registers we need to save.  */
3894   gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3895   fp_saved = (EABI_FLOAT_VARARGS_P
3896               ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3897               : 0);
3898
3899   if (!no_rtl)
3900     {
3901       if (gp_saved > 0)
3902         {
3903           rtx ptr, mem;
3904
3905           ptr = virtual_incoming_args_rtx;
3906           switch (mips_abi)
3907             {
3908             case ABI_32:
3909             case ABI_O64:
3910               ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3911               break;
3912
3913             case ABI_EABI:
3914               ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3915               break;
3916             }
3917           mem = gen_rtx_MEM (BLKmode, ptr);
3918           set_mem_alias_set (mem, get_varargs_alias_set ());
3919
3920           move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3921                                mem, gp_saved);
3922         }
3923       if (fp_saved > 0)
3924         {
3925           /* We can't use move_block_from_reg, because it will use
3926              the wrong mode.  */
3927           enum machine_mode mode;
3928           int off, i;
3929
3930           /* Set OFF to the offset from virtual_incoming_args_rtx of
3931              the first float register.   The FP save area lies below
3932              the integer one, and is aligned to UNITS_PER_FPVALUE bytes.  */
3933           off = -gp_saved * UNITS_PER_WORD;
3934           off &= ~(UNITS_PER_FPVALUE - 1);
3935           off -= fp_saved * UNITS_PER_FPREG;
3936
3937           mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3938
3939           for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3940             {
3941               rtx ptr, mem;
3942
3943               ptr = plus_constant (virtual_incoming_args_rtx, off);
3944               mem = gen_rtx_MEM (mode, ptr);
3945               set_mem_alias_set (mem, get_varargs_alias_set ());
3946               emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3947               off += UNITS_PER_HWFPVALUE;
3948             }
3949         }
3950     }
3951   if (TARGET_OLDABI)
3952     {
3953       /* No need for pretend arguments: the register parameter area was
3954          allocated by the caller.  */
3955       *pretend_size = 0;
3956       return;
3957     }
3958   *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3959 }
3960
3961 /* Create the va_list data type.
3962    We keep 3 pointers, and two offsets.
3963    Two pointers are to the overflow area, which starts at the CFA.
3964      One of these is constant, for addressing into the GPR save area below it.
3965      The other is advanced up the stack through the overflow region.
3966    The third pointer is to the GPR save area.  Since the FPR save area
3967      is just below it, we can address FPR slots off this pointer.
3968    We also keep two one-byte offsets, which are to be subtracted from the
3969      constant pointers to yield addresses in the GPR and FPR save areas.
3970      These are downcounted as float or non-float arguments are used,
3971      and when they get to zero, the argument must be obtained from the
3972      overflow region.
3973    If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3974      pointer is enough.  It's started at the GPR save area, and is
3975      advanced, period.
3976    Note that the GPR save area is not constant size, due to optimization
3977      in the prologue.  Hence, we can't use a design with two pointers
3978      and two offsets, although we could have designed this with two pointers
3979      and three offsets.  */
3980
3981 static tree
3982 mips_build_builtin_va_list (void)
3983 {
3984   if (EABI_FLOAT_VARARGS_P)
3985     {
3986       tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3987       tree array, index;
3988
3989       record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3990
3991       f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3992                           ptr_type_node);
3993       f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3994                           ptr_type_node);
3995       f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3996                           ptr_type_node);
3997       f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3998                           unsigned_char_type_node);
3999       f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4000                           unsigned_char_type_node);
4001       /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4002          warn on every user file.  */
4003       index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
4004       array = build_array_type (unsigned_char_type_node,
4005                                 build_index_type (index));
4006       f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4007
4008       DECL_FIELD_CONTEXT (f_ovfl) = record;
4009       DECL_FIELD_CONTEXT (f_gtop) = record;
4010       DECL_FIELD_CONTEXT (f_ftop) = record;
4011       DECL_FIELD_CONTEXT (f_goff) = record;
4012       DECL_FIELD_CONTEXT (f_foff) = record;
4013       DECL_FIELD_CONTEXT (f_res) = record;
4014
4015       TYPE_FIELDS (record) = f_ovfl;
4016       TREE_CHAIN (f_ovfl) = f_gtop;
4017       TREE_CHAIN (f_gtop) = f_ftop;
4018       TREE_CHAIN (f_ftop) = f_goff;
4019       TREE_CHAIN (f_goff) = f_foff;
4020       TREE_CHAIN (f_foff) = f_res;
4021
4022       layout_type (record);
4023       return record;
4024     }
4025   else if (TARGET_IRIX && !TARGET_IRIX5)
4026     /* On IRIX 6, this type is 'char *'.  */
4027     return build_pointer_type (char_type_node);
4028   else
4029     /* Otherwise, we use 'void *'.  */
4030     return ptr_type_node;
4031 }
4032
4033 /* Implement va_start.  */
4034
4035 void
4036 mips_va_start (tree valist, rtx nextarg)
4037 {
4038   const CUMULATIVE_ARGS *cum = &current_function_args_info;
4039
4040   /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4041      since the stack is aligned for a pair of argument-passing slots,
4042      and the beginning of a variable argument list may be an odd slot,
4043      we have to decrease its alignment.  */
4044   if (cfun && cfun->emit->regno_pointer_align)
4045     while (((current_function_pretend_args_size * BITS_PER_UNIT)
4046             & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4047       REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4048
4049   if (mips_abi == ABI_EABI)
4050     {
4051       int gpr_save_area_size;
4052
4053       gpr_save_area_size
4054         = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4055
4056       if (EABI_FLOAT_VARARGS_P)
4057         {
4058           tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4059           tree ovfl, gtop, ftop, goff, foff;
4060           tree t;
4061           int fpr_offset;
4062           int fpr_save_area_size;
4063
4064           f_ovfl = TYPE_FIELDS (va_list_type_node);
4065           f_gtop = TREE_CHAIN (f_ovfl);
4066           f_ftop = TREE_CHAIN (f_gtop);
4067           f_goff = TREE_CHAIN (f_ftop);
4068           f_foff = TREE_CHAIN (f_goff);
4069
4070           ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4071           gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4072           ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4073           goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4074           foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4075
4076           /* Emit code to initialize OVFL, which points to the next varargs
4077              stack argument.  CUM->STACK_WORDS gives the number of stack
4078              words used by named arguments.  */
4079           t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4080           if (cum->stack_words > 0)
4081             t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4082                        build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4083           t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4084           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4085
4086           /* Emit code to initialize GTOP, the top of the GPR save area.  */
4087           t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4088           t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4089           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4090
4091           /* Emit code to initialize FTOP, the top of the FPR save area.
4092              This address is gpr_save_area_bytes below GTOP, rounded
4093              down to the next fp-aligned boundary.  */
4094           t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4095           fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4096           fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4097           if (fpr_offset)
4098             t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4099                        build_int_2 (-fpr_offset, -1));
4100           t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4101           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4102
4103           /* Emit code to initialize GOFF, the offset from GTOP of the
4104              next GPR argument.  */
4105           t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4106                      build_int_2 (gpr_save_area_size, 0));
4107           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4108
4109           /* Likewise emit code to initialize FOFF, the offset from FTOP
4110              of the next FPR argument.  */
4111           fpr_save_area_size
4112             = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4113           t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4114                      build_int_2 (fpr_save_area_size, 0));
4115           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4116         }
4117       else
4118         {
4119           /* Everything is in the GPR save area, or in the overflow
4120              area which is contiguous with it.  */
4121           nextarg = plus_constant (nextarg, -gpr_save_area_size);
4122           std_expand_builtin_va_start (valist, nextarg);
4123         }
4124     }
4125   else
4126     std_expand_builtin_va_start (valist, nextarg);
4127 }
4128 \f
4129 /* Implement va_arg.  */
4130
4131 rtx
4132 mips_va_arg (tree valist, tree type)
4133 {
4134   HOST_WIDE_INT size, rsize;
4135   rtx addr_rtx;
4136   tree t;
4137
4138   size = int_size_in_bytes (type);
4139   rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4140
4141   if (mips_abi == ABI_EABI)
4142     {
4143       bool indirect;
4144       rtx r;
4145
4146       indirect
4147         = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4148
4149       if (indirect)
4150         {
4151           size = POINTER_SIZE / BITS_PER_UNIT;
4152           rsize = UNITS_PER_WORD;
4153         }
4154
4155       addr_rtx = gen_reg_rtx (Pmode);
4156
4157       if (!EABI_FLOAT_VARARGS_P)
4158         {
4159           /* Case of all args in a merged stack.  No need to check bounds,
4160              just advance valist along the stack.  */
4161
4162           tree gpr = valist;
4163           if (!indirect
4164               && !TARGET_64BIT
4165               && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4166             {
4167               /* Align the pointer using: ap = (ap + align - 1) & -align,
4168                  where align is 2 * UNITS_PER_WORD.  */
4169               t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4170                          build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4171               t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4172                          build_int_2 (-2 * UNITS_PER_WORD, -1));
4173               t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4174               expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4175             }
4176
4177           /* Emit code to set addr_rtx to the valist, and postincrement
4178              the valist by the size of the argument, rounded up to the
4179              next word.  */
4180           t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4181                      size_int (rsize));
4182           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4183           if (r != addr_rtx)
4184             emit_move_insn (addr_rtx, r);
4185
4186           /* Flush the POSTINCREMENT.  */
4187           emit_queue();
4188         }
4189       else
4190         {
4191           /* Not a simple merged stack.  */
4192
4193           tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4194           tree ovfl, top, off;
4195           rtx lab_over = NULL_RTX, lab_false;
4196           HOST_WIDE_INT osize;
4197
4198           f_ovfl = TYPE_FIELDS (va_list_type_node);
4199           f_gtop = TREE_CHAIN (f_ovfl);
4200           f_ftop = TREE_CHAIN (f_gtop);
4201           f_goff = TREE_CHAIN (f_ftop);
4202           f_foff = TREE_CHAIN (f_goff);
4203
4204           /* We maintain separate pointers and offsets for floating-point
4205              and integer arguments, but we need similar code in both cases.
4206              Let:
4207
4208                  TOP be the top of the register save area;
4209                  OFF be the offset from TOP of the next register;
4210                  ADDR_RTX be the address of the argument;
4211                  RSIZE be the number of bytes used to store the argument
4212                    when it's in the register save area;
4213                  OSIZE be the number of bytes used to store it when it's
4214                    in the stack overflow area; and
4215                  PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4216
4217              The code we want is:
4218
4219                   1: off &= -rsize;       // round down
4220                   2: if (off != 0)
4221                   3:   {
4222                   4:     addr_rtx = top - off;
4223                   5:     off -= rsize;
4224                   6:   }
4225                   7: else
4226                   8:   {
4227                   9:     ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4228                  10:     addr_rtx = ovfl + PADDING;
4229                  11:     ovfl += osize;
4230                  14:   }
4231
4232              [1] and [9] can sometimes be optimized away.  */
4233
4234           lab_false = gen_label_rtx ();
4235           lab_over = gen_label_rtx ();
4236
4237           ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4238           if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4239               && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4240             {
4241               top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4242               off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4243
4244               /* When floating-point registers are saved to the stack,
4245                  each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4246                  of the float's precision.  */
4247               rsize = UNITS_PER_HWFPVALUE;
4248             }
4249           else
4250             {
4251               top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4252               off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4253               if (rsize > UNITS_PER_WORD)
4254                 {
4255                   /* [1] Emit code for: off &= -rsize.  */
4256                   t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4257                              build_int_2 (-rsize, -1));
4258                   t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4259                   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4260                 }
4261             }
4262           /* Every overflow argument must take up at least UNITS_PER_WORD
4263              bytes (= PARM_BOUNDARY bits).  RSIZE can sometimes be smaller
4264              than that, such as in the combination -mgp64 -msingle-float
4265              -fshort-double.  Doubles passed in registers will then take
4266              up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4267              take up UNITS_PER_WORD bytes.  */
4268           osize = MAX (rsize, UNITS_PER_WORD);
4269
4270           /* [2] Emit code to branch if off == 0.  */
4271           r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4272                            EXPAND_NORMAL);
4273           emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4274                                    1, lab_false);
4275
4276           /* [4] Emit code for: addr_rtx = top - off.  */
4277           t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4278           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4279           if (r != addr_rtx)
4280             emit_move_insn (addr_rtx, r);
4281
4282           /* [5] Emit code for: off -= rsize.  */
4283           t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4284           t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4285           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4286
4287           /* [7] Emit code to jump over the else clause, then the label
4288              that starts it.  */
4289           emit_queue();
4290           emit_jump (lab_over);
4291           emit_barrier ();
4292           emit_label (lab_false);
4293
4294           if (osize > UNITS_PER_WORD)
4295             {
4296               /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize.  */
4297               t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4298                          build_int_2 (osize - 1, 0));
4299               t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4300                          build_int_2 (-osize, -1));
4301               t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4302               expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4303             }
4304
4305           /* [10, 11].  Emit code to store ovfl in addr_rtx, then
4306              post-increment ovfl by osize.  On big-endian machines,
4307              the argument has OSIZE - RSIZE bytes of leading padding.  */
4308           t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4309                      size_int (osize));
4310           if (BYTES_BIG_ENDIAN && osize > rsize)
4311             t = build (PLUS_EXPR, TREE_TYPE (t), t,
4312                        build_int_2 (osize - rsize, 0));
4313           r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4314           if (r != addr_rtx)
4315             emit_move_insn (addr_rtx, r);
4316
4317           emit_queue();
4318           emit_label (lab_over);
4319         }
4320       if (BYTES_BIG_ENDIAN && rsize != size)
4321         addr_rtx = plus_constant (addr_rtx, rsize - size);
4322       if (indirect)
4323         {
4324           addr_rtx = force_reg (Pmode, addr_rtx);
4325           r = gen_rtx_MEM (Pmode, addr_rtx);
4326           set_mem_alias_set (r, get_varargs_alias_set ());
4327           emit_move_insn (addr_rtx, r);
4328         }
4329       return addr_rtx;
4330     }
4331   else
4332     {
4333       /* Not EABI.  */
4334       int align;
4335       HOST_WIDE_INT min_offset;
4336
4337       /* ??? The original va-mips.h did always align, despite the fact
4338          that alignments <= UNITS_PER_WORD are preserved by the va_arg
4339          increment mechanism.  */
4340
4341       if (TARGET_NEWABI && TYPE_ALIGN (type) > 64)
4342         align = 16;
4343       else if (TARGET_64BIT)
4344         align = 8;
4345       else if (TYPE_ALIGN (type) > 32)
4346         align = 8;
4347       else
4348         align = 4;
4349
4350       t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4351                  build_int_2 (align - 1, 0));
4352       t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4353
4354       /* If arguments of type TYPE must be passed on the stack,
4355          set MIN_OFFSET to the offset of the first stack parameter.  */
4356       if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4357         min_offset = 0;
4358       else if (TARGET_NEWABI)
4359         min_offset = current_function_pretend_args_size;
4360       else
4361         min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4362
4363       /* Make sure the new address is at least MIN_OFFSET bytes from
4364          the incoming argument pointer.  */
4365       if (min_offset > 0)
4366         t = build (MAX_EXPR, TREE_TYPE (valist), t,
4367                    make_tree (TREE_TYPE (valist),
4368                               plus_constant (virtual_incoming_args_rtx,
4369                                              min_offset)));
4370
4371       t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4372       expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4373
4374       /* Everything past the alignment is standard.  */
4375       return std_expand_builtin_va_arg (valist, type);
4376     }
4377 }
4378 \f
4379 /* Return true if it is possible to use left/right accesses for a
4380    bitfield of WIDTH bits starting BITPOS bits into *OP.  When
4381    returning true, update *OP, *LEFT and *RIGHT as follows:
4382
4383    *OP is a BLKmode reference to the whole field.
4384
4385    *LEFT is a QImode reference to the first byte if big endian or
4386    the last byte if little endian.  This address can be used in the
4387    left-side instructions (lwl, swl, ldl, sdl).
4388
4389    *RIGHT is a QImode reference to the opposite end of the field and
4390    can be used in the parterning right-side instruction.  */
4391
4392 static bool
4393 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4394                         rtx *left, rtx *right)
4395 {
4396   rtx first, last;
4397
4398   /* Check that the operand really is a MEM.  Not all the extv and
4399      extzv predicates are checked.  */
4400   if (GET_CODE (*op) != MEM)
4401     return false;
4402
4403   /* Check that the size is valid.  */
4404   if (width != 32 && (!TARGET_64BIT || width != 64))
4405     return false;
4406
4407   /* We can only access byte-aligned values.  Since we are always passed
4408      a reference to the first byte of the field, it is not necessary to
4409      do anything with BITPOS after this check.  */
4410   if (bitpos % BITS_PER_UNIT != 0)
4411     return false;
4412
4413   /* Reject aligned bitfields: we want to use a normal load or store
4414      instead of a left/right pair.  */
4415   if (MEM_ALIGN (*op) >= width)
4416     return false;
4417
4418   /* Adjust *OP to refer to the whole field.  This also has the effect
4419      of legitimizing *OP's address for BLKmode, possibly simplifying it.  */
4420   *op = adjust_address (*op, BLKmode, 0);
4421   set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4422
4423   /* Get references to both ends of the field.  We deliberately don't
4424      use the original QImode *OP for FIRST since the new BLKmode one
4425      might have a simpler address.  */
4426   first = adjust_address (*op, QImode, 0);
4427   last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4428
4429   /* Allocate to LEFT and RIGHT according to endiannes.  LEFT should
4430      be the upper word and RIGHT the lower word.  */
4431   if (TARGET_BIG_ENDIAN)
4432     *left = first, *right = last;
4433   else
4434     *left = last, *right = first;
4435
4436   return true;
4437 }
4438
4439
4440 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4441    Return true on success.  We only handle cases where zero_extract is
4442    equivalent to sign_extract.  */
4443
4444 bool
4445 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4446 {
4447   rtx left, right;
4448
4449   /* If TARGET_64BIT, the destination of a 32-bit load will be a
4450      paradoxical word_mode subreg.  This is the only case in which
4451      we allow the destination to be larger than the source.  */
4452   if (GET_CODE (dest) == SUBREG
4453       && GET_MODE (dest) == DImode
4454       && SUBREG_BYTE (dest) == 0
4455       && GET_MODE (SUBREG_REG (dest)) == SImode)
4456     dest = SUBREG_REG (dest);
4457
4458   /* After the above adjustment, the destination must be the same
4459      width as the source.  */
4460   if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4461     return false;
4462
4463   if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4464     return false;
4465
4466   if (GET_MODE (dest) == DImode)
4467     {
4468       emit_insn (gen_mov_ldl (dest, src, left));
4469       emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
4470                               right, copy_rtx (dest)));
4471     }
4472   else
4473     {
4474       emit_insn (gen_mov_lwl (dest, src, left));
4475       emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
4476                               right, copy_rtx (dest)));
4477     }
4478   return true;
4479 }
4480
4481
4482 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC).  Return
4483    true on success.  */
4484
4485 bool
4486 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4487 {
4488   rtx left, right;
4489
4490   if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4491     return false;
4492
4493   src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4494
4495   if (GET_MODE (src) == DImode)
4496     {
4497       emit_insn (gen_mov_sdl (dest, src, left));
4498       emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4499     }
4500   else
4501     {
4502       emit_insn (gen_mov_swl (dest, src, left));
4503       emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4504     }
4505   return true;
4506 }
4507 \f
4508 /* Set up globals to generate code for the ISA or processor
4509    described by INFO.  */
4510
4511 static void
4512 mips_set_architecture (const struct mips_cpu_info *info)
4513 {
4514   if (info != 0)
4515     {
4516       mips_arch_info = info;
4517       mips_arch = info->cpu;
4518       mips_isa = info->isa;
4519     }
4520 }
4521
4522
4523 /* Likewise for tuning.  */
4524
4525 static void
4526 mips_set_tune (const struct mips_cpu_info *info)
4527 {
4528   if (info != 0)
4529     {
4530       mips_tune_info = info;
4531       mips_tune = info->cpu;
4532     }
4533 }
4534
4535
4536 /* Set up the threshold for data to go into the small data area, instead
4537    of the normal data area, and detect any conflicts in the switches.  */
4538
4539 void
4540 override_options (void)
4541 {
4542   int i, start, regno;
4543   enum machine_mode mode;
4544
4545   mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4546
4547   /* Interpret -mabi.  */
4548   mips_abi = MIPS_ABI_DEFAULT;
4549   if (mips_abi_string != 0)
4550     {
4551       if (strcmp (mips_abi_string, "32") == 0)
4552         mips_abi = ABI_32;
4553       else if (strcmp (mips_abi_string, "o64") == 0)
4554         mips_abi = ABI_O64;
4555       else if (strcmp (mips_abi_string, "n32") == 0)
4556         mips_abi = ABI_N32;
4557       else if (strcmp (mips_abi_string, "64") == 0)
4558         mips_abi = ABI_64;
4559       else if (strcmp (mips_abi_string, "eabi") == 0)
4560         mips_abi = ABI_EABI;
4561       else
4562         fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4563     }
4564
4565   /* The following code determines the architecture and register size.
4566      Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4567      The GAS and GCC code should be kept in sync as much as possible.  */
4568
4569   if (mips_arch_string != 0)
4570     mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4571
4572   if (mips_isa_string != 0)
4573     {
4574       /* Handle -mipsN.  */
4575       char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4576       const struct mips_cpu_info *isa_info;
4577
4578       isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4579       free (whole_isa_str);
4580
4581       /* -march takes precedence over -mipsN, since it is more descriptive.
4582          There's no harm in specifying both as long as the ISA levels
4583          are the same.  */
4584       if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4585         error ("-mips%s conflicts with the other architecture options, "
4586                "which specify a MIPS%d processor",
4587                mips_isa_string, mips_isa);
4588
4589       /* Set architecture based on the given option.  */
4590       mips_set_architecture (isa_info);
4591     }
4592
4593   if (mips_arch_info == 0)
4594     {
4595 #ifdef MIPS_CPU_STRING_DEFAULT
4596       mips_set_architecture (mips_parse_cpu ("default CPU",
4597                                              MIPS_CPU_STRING_DEFAULT));
4598 #else
4599       mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4600 #endif
4601     }
4602
4603   if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4604     error ("-march=%s is not compatible with the selected ABI",
4605            mips_arch_info->name);
4606
4607   /* Optimize for mips_arch, unless -mtune selects a different processor.  */
4608   if (mips_tune_string != 0)
4609     mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4610
4611   if (mips_tune_info == 0)
4612     mips_set_tune (mips_arch_info);
4613
4614   if ((target_flags_explicit & MASK_64BIT) != 0)
4615     {
4616       /* The user specified the size of the integer registers.  Make sure
4617          it agrees with the ABI and ISA.  */
4618       if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4619         error ("-mgp64 used with a 32-bit processor");
4620       else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4621         error ("-mgp32 used with a 64-bit ABI");
4622       else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4623         error ("-mgp64 used with a 32-bit ABI");
4624     }
4625   else
4626     {
4627       /* Infer the integer register size from the ABI and processor.
4628          Restrict ourselves to 32-bit registers if that's all the
4629          processor has, or if the ABI cannot handle 64-bit registers.  */
4630       if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4631         target_flags &= ~MASK_64BIT;
4632       else
4633         target_flags |= MASK_64BIT;
4634     }
4635
4636   if ((target_flags_explicit & MASK_FLOAT64) != 0)
4637     {
4638       /* Really, -mfp32 and -mfp64 are ornamental options.  There's
4639          only one right answer here.  */
4640       if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4641         error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4642       else if (!TARGET_64BIT && TARGET_FLOAT64)
4643         error ("unsupported combination: %s", "-mgp32 -mfp64");
4644       else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4645         error ("unsupported combination: %s", "-mfp64 -msingle-float");
4646     }
4647   else
4648     {
4649       /* -msingle-float selects 32-bit float registers.  Otherwise the
4650          float registers should be the same size as the integer ones.  */
4651       if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4652         target_flags |= MASK_FLOAT64;
4653       else
4654         target_flags &= ~MASK_FLOAT64;
4655     }
4656
4657   /* End of code shared with GAS.  */
4658
4659   if ((target_flags_explicit & MASK_LONG64) == 0)
4660     {
4661       /* If no type size setting options (-mlong64,-mint64,-mlong32)
4662          were used, then set the type sizes.  In the EABI in 64 bit mode,
4663          longs and pointers are 64 bits.  Likewise for the SGI Irix6 N64
4664          ABI.  */
4665       if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4666         target_flags |= MASK_LONG64;
4667       else
4668         target_flags &= ~MASK_LONG64;
4669     }
4670
4671   if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4672       && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4673     {
4674       /* For some configurations, it is useful to have -march control
4675          the default setting of MASK_SOFT_FLOAT.  */
4676       switch ((int) mips_arch)
4677         {
4678         case PROCESSOR_R4100:
4679         case PROCESSOR_R4111:
4680         case PROCESSOR_R4120:
4681           target_flags |= MASK_SOFT_FLOAT;
4682           break;
4683
4684         default:
4685           target_flags &= ~MASK_SOFT_FLOAT;
4686           break;
4687         }
4688     }
4689
4690   if (!TARGET_OLDABI)
4691     flag_pcc_struct_return = 0;
4692
4693 #if defined(USE_COLLECT2)
4694   /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4695      always defined when GNU as is not in use, but collect2 is only used
4696      for the O32 ABI, so override the toplev.c and target-def.h defaults
4697      for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4698      TARGET_HAVE_CTORS_DTORS.
4699
4700      Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4701      sections, constructor/destructor handling depends on the ABI in use.
4702
4703      Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4704      defaults for the N32/N64 ABIs.  */
4705   if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4706     {
4707       targetm.have_ctors_dtors = true;
4708       targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4709       targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4710     }
4711 #endif
4712
4713   /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers.  */
4714
4715   if (TARGET_SGI_O32_AS)
4716     {
4717       /* They don't recognize `.[248]byte'.  */
4718       targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4719       targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4720       /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4721          contrary to the documentation, so disable it.  */
4722       targetm.asm_out.unaligned_op.di = NULL;
4723
4724       /* They cannot handle named sections.  */
4725       targetm.have_named_sections = false;
4726       /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4727          collect2.  */
4728       targetm.terminate_dw2_eh_frame_info = true;
4729       targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4730
4731       /* They cannot handle debug information.  */
4732       if (write_symbols != NO_DEBUG)
4733         {
4734           /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4735              so -mabi=32 isn't usually specified.  */
4736           if (TARGET_IRIX5)
4737             inform ("-g is only supported using GNU as,");
4738           else
4739             inform ("-g is only supported using GNU as with -mabi=32,");
4740           inform ("-g option disabled");
4741           write_symbols = NO_DEBUG;
4742         }
4743     }
4744
4745   if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4746     {
4747       /* If neither -mbranch-likely nor -mno-branch-likely was given
4748          on the command line, set MASK_BRANCHLIKELY based on the target
4749          architecture.
4750
4751          By default, we enable use of Branch Likely instructions on
4752          all architectures which support them except for MIPS32 and MIPS64
4753          (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4754          implement them).
4755
4756          The MIPS32 and MIPS64 architecture specifications say "Software
4757          is strongly encouraged to avoid use of Branch Likely
4758          instructions, as they will be removed from a future revision
4759          of the [MIPS32 and MIPS64] architecture."  Therefore, we do not
4760          issue those instructions unless instructed to do so by
4761          -mbranch-likely.  */
4762       if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4763         target_flags |= MASK_BRANCHLIKELY;
4764       else
4765         target_flags &= ~MASK_BRANCHLIKELY;
4766     }
4767   if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4768     warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4769
4770   /* The effect of -mabicalls isn't defined for the EABI.  */
4771   if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4772     {
4773       error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4774       target_flags &= ~MASK_ABICALLS;
4775     }
4776
4777   /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
4778      to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
4779   /* ??? -non_shared turns off pic code generation, but this is not
4780      implemented.  */
4781   if (TARGET_ABICALLS)
4782     {
4783       flag_pic = 1;
4784       if (mips_section_threshold > 0)
4785         warning ("-G is incompatible with PIC code which is the default");
4786     }
4787
4788   /* The MIPS and SGI o32 assemblers expect small-data variables to
4789      be declared before they are used.  Although we once had code to
4790      do this, it was very invasive and fragile.  It no longer seems
4791      worth the effort.  */
4792   if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4793     mips_section_threshold = 0;
4794
4795   /* We switch to small data sections using ".section", which the native
4796      o32 irix assemblers don't understand.  Disable -G accordingly.
4797      We must do this regardless of command-line options since otherwise
4798      the compiler would abort.  */
4799   if (!targetm.have_named_sections)
4800     mips_section_threshold = 0;
4801
4802   /* -membedded-pic is a form of PIC code suitable for embedded
4803      systems.  All calls are made using PC relative addressing, and
4804      all data is addressed using the $gp register.  This requires gas,
4805      which does most of the work, and GNU ld, which automatically
4806      expands PC relative calls which are out of range into a longer
4807      instruction sequence.  All gcc really does differently is
4808      generate a different sequence for a switch.  */
4809   if (TARGET_EMBEDDED_PIC)
4810     {
4811       flag_pic = 1;
4812       if (TARGET_ABICALLS)
4813         warning ("-membedded-pic and -mabicalls are incompatible");
4814
4815       if (g_switch_set)
4816         warning ("-G and -membedded-pic are incompatible");
4817
4818       /* Setting mips_section_threshold is not required, because gas
4819          will force everything to be GP addressable anyhow, but
4820          setting it will cause gcc to make better estimates of the
4821          number of instructions required to access a particular data
4822          item.  */
4823       mips_section_threshold = 0x7fffffff;
4824     }
4825
4826   /* mips_split_addresses is a half-way house between explicit
4827      relocations and the traditional assembler macros.  It can
4828      split absolute 32-bit symbolic constants into a high/lo_sum
4829      pair but uses macros for other sorts of access.
4830
4831      Like explicit relocation support for REL targets, it relies
4832      on GNU extensions in the assembler and the linker.
4833
4834      Although this code should work for -O0, it has traditionally
4835      been treated as an optimization.  */
4836   if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4837       && optimize && !flag_pic
4838       && !ABI_HAS_64BIT_SYMBOLS)
4839     mips_split_addresses = 1;
4840   else
4841     mips_split_addresses = 0;
4842
4843   /* -mexplicit-relocs doesn't yet support non-PIC n64.  We don't know
4844      how to generate %highest/%higher/%hi/%lo sequences.  */
4845   if (mips_abi == ABI_64 && !TARGET_ABICALLS)
4846     {
4847       if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
4848         sorry ("non-PIC n64 with explicit relocations");
4849       target_flags &= ~MASK_EXPLICIT_RELOCS;
4850     }
4851
4852   /* Explicit relocations for "old" ABIs are a GNU extension.  Unless
4853      the user has said otherwise, assume that they are not available
4854      with assemblers other than gas.  */
4855   if (!TARGET_NEWABI && !TARGET_GAS
4856       && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4857     target_flags &= ~MASK_EXPLICIT_RELOCS;
4858
4859   /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4860      unless the user says otherwise.
4861
4862      There are two problems here:
4863
4864        (1) The value of an R_MIPS_GOT16 relocation depends on whether
4865            the symbol is local or global.  We therefore need to know
4866            a symbol's binding before refering to it using %got().
4867
4868        (2) R_MIPS_CALL16 can only be applied to global symbols.
4869
4870      When not using -funit-at-a-time, a symbol's binding may change
4871      after it has been used.  For example, the C++ front-end will
4872      initially assume that the typeinfo for an incomplete type will be
4873      comdat, on the basis that the type could be completed later in the
4874      file.  But if the type never is completed, the typeinfo will become
4875      local instead.  */
4876   if (!flag_unit_at_a_time
4877       && TARGET_ABICALLS
4878       && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4879     target_flags &= ~MASK_EXPLICIT_RELOCS;
4880
4881   /* -mrnames says to use the MIPS software convention for register
4882      names instead of the hardware names (ie, $a0 instead of $4).
4883      We do this by switching the names in mips_reg_names, which the
4884      reg_names points into via the REGISTER_NAMES macro.  */
4885
4886   if (TARGET_NAME_REGS)
4887     memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4888
4889   /* When compiling for the mips16, we can not use floating point.  We
4890      record the original hard float value in mips16_hard_float.  */
4891   if (TARGET_MIPS16)
4892     {
4893       if (TARGET_SOFT_FLOAT)
4894         mips16_hard_float = 0;
4895       else
4896         mips16_hard_float = 1;
4897       target_flags |= MASK_SOFT_FLOAT;
4898
4899       /* Don't run the scheduler before reload, since it tends to
4900          increase register pressure.  */
4901       flag_schedule_insns = 0;
4902
4903       /* Silently disable -mexplicit-relocs since it doesn't apply
4904          to mips16 code.  Even so, it would overly pedantic to warn
4905          about "-mips16 -mexplicit-relocs", especially given that
4906          we use a %gprel() operator.  */
4907       target_flags &= ~MASK_EXPLICIT_RELOCS;
4908     }
4909
4910   /* When using explicit relocs, we call dbr_schedule from within
4911      mips_reorg.  */
4912   if (TARGET_EXPLICIT_RELOCS)
4913     {
4914       mips_flag_delayed_branch = flag_delayed_branch;
4915       flag_delayed_branch = 0;
4916     }
4917
4918 #ifdef MIPS_TFMODE_FORMAT
4919   REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4920 #endif
4921
4922   mips_print_operand_punct['?'] = 1;
4923   mips_print_operand_punct['#'] = 1;
4924   mips_print_operand_punct['/'] = 1;
4925   mips_print_operand_punct['&'] = 1;
4926   mips_print_operand_punct['!'] = 1;
4927   mips_print_operand_punct['*'] = 1;
4928   mips_print_operand_punct['@'] = 1;
4929   mips_print_operand_punct['.'] = 1;
4930   mips_print_operand_punct['('] = 1;
4931   mips_print_operand_punct[')'] = 1;
4932   mips_print_operand_punct['['] = 1;
4933   mips_print_operand_punct[']'] = 1;
4934   mips_print_operand_punct['<'] = 1;
4935   mips_print_operand_punct['>'] = 1;
4936   mips_print_operand_punct['{'] = 1;
4937   mips_print_operand_punct['}'] = 1;
4938   mips_print_operand_punct['^'] = 1;
4939   mips_print_operand_punct['$'] = 1;
4940   mips_print_operand_punct['+'] = 1;
4941   mips_print_operand_punct['~'] = 1;
4942
4943   mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4944   mips_char_to_class['e'] = M16_NA_REGS;
4945   mips_char_to_class['t'] = T_REG;
4946   mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4947   mips_char_to_class['h'] = HI_REG;
4948   mips_char_to_class['l'] = LO_REG;
4949   mips_char_to_class['x'] = MD_REGS;
4950   mips_char_to_class['b'] = ALL_REGS;
4951   mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4952                              TARGET_MIPS16 ? M16_NA_REGS :
4953                              GR_REGS);
4954   mips_char_to_class['e'] = LEA_REGS;
4955   mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4956   mips_char_to_class['y'] = GR_REGS;
4957   mips_char_to_class['z'] = ST_REGS;
4958   mips_char_to_class['B'] = COP0_REGS;
4959   mips_char_to_class['C'] = COP2_REGS;
4960   mips_char_to_class['D'] = COP3_REGS;
4961
4962   /* Set up array to map GCC register number to debug register number.
4963      Ignore the special purpose register numbers.  */
4964
4965   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4966     mips_dbx_regno[i] = -1;
4967
4968   start = GP_DBX_FIRST - GP_REG_FIRST;
4969   for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4970     mips_dbx_regno[i] = i + start;
4971
4972   start = FP_DBX_FIRST - FP_REG_FIRST;
4973   for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4974     mips_dbx_regno[i] = i + start;
4975
4976   mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4977   mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4978
4979   /* Set up array giving whether a given register can hold a given mode.  */
4980
4981   for (mode = VOIDmode;
4982        mode != MAX_MACHINE_MODE;
4983        mode = (enum machine_mode) ((int)mode + 1))
4984     {
4985       register int size              = GET_MODE_SIZE (mode);
4986       register enum mode_class class = GET_MODE_CLASS (mode);
4987
4988       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4989         {
4990           register int temp;
4991
4992           if (mode == CCmode)
4993             {
4994               if (! ISA_HAS_8CC)
4995                 temp = (regno == FPSW_REGNUM);
4996               else
4997                 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4998                         || FP_REG_P (regno));
4999             }
5000
5001           else if (GP_REG_P (regno))
5002             temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5003
5004           else if (FP_REG_P (regno))
5005             temp = ((regno % FP_INC) == 0)
5006                     && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5007                          && size <= UNITS_PER_FPVALUE)
5008                         /* Allow integer modes that fit into a single
5009                            register.  We need to put integers into FPRs
5010                            when using instructions like cvt and trunc.  */
5011                         || (class == MODE_INT && size <= UNITS_PER_FPREG)
5012                         /* Allow TFmode for CCmode reloads.  */
5013                         || (ISA_HAS_8CC && mode == TFmode));
5014
5015           else if (MD_REG_P (regno))
5016             temp = (class == MODE_INT
5017                     && (size <= UNITS_PER_WORD
5018                         || (regno == MD_REG_FIRST
5019                             && size == 2 * UNITS_PER_WORD)));
5020
5021           else if (ALL_COP_REG_P (regno))
5022             temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5023           else
5024             temp = 0;
5025
5026           mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5027         }
5028     }
5029
5030   /* Save GPR registers in word_mode sized hunks.  word_mode hasn't been
5031      initialized yet, so we can't use that here.  */
5032   gpr_mode = TARGET_64BIT ? DImode : SImode;
5033
5034   /* Provide default values for align_* for 64-bit targets.  */
5035   if (TARGET_64BIT && !TARGET_MIPS16)
5036     {
5037       if (align_loops == 0)
5038         align_loops = 8;
5039       if (align_jumps == 0)
5040         align_jumps = 8;
5041       if (align_functions == 0)
5042         align_functions = 8;
5043     }
5044
5045   /* Function to allocate machine-dependent function status.  */
5046   init_machine_status = &mips_init_machine_status;
5047
5048   if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5049     {
5050       mips_split_p[SYMBOL_GENERAL] = true;
5051       mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5052       mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5053     }
5054
5055   if (TARGET_MIPS16)
5056     {
5057       /* The high part is provided by a pseudo copy of $gp.  */
5058       mips_split_p[SYMBOL_SMALL_DATA] = true;
5059       mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5060     }
5061
5062   if (TARGET_EXPLICIT_RELOCS)
5063     {
5064       /* Small data constants are kept whole until after reload,
5065          then lowered by mips_rewrite_small_data.  */
5066       mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5067
5068       mips_split_p[SYMBOL_GOT_LOCAL] = true;
5069       if (TARGET_NEWABI)
5070         {
5071           mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5072           mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5073         }
5074       else
5075         {
5076           mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5077           mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5078         }
5079
5080       if (TARGET_XGOT)
5081         {
5082           /* The HIGH and LO_SUM are matched by special .md patterns.  */
5083           mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5084
5085           mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5086           mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5087           mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5088
5089           mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5090           mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5091           mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5092         }
5093       else
5094         {
5095           if (TARGET_NEWABI)
5096             mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5097           else
5098             mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5099           mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5100         }
5101     }
5102
5103   if (TARGET_NEWABI)
5104     {
5105       mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5106       mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5107       mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5108     }
5109 }
5110
5111 /* Implement CONDITIONAL_REGISTER_USAGE.  */
5112
5113 void
5114 mips_conditional_register_usage (void)
5115 {
5116   if (!TARGET_HARD_FLOAT)
5117     {
5118       int regno;
5119
5120       for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5121         fixed_regs[regno] = call_used_regs[regno] = 1;
5122       for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5123         fixed_regs[regno] = call_used_regs[regno] = 1;
5124     }
5125   else if (! ISA_HAS_8CC)
5126     {
5127       int regno;
5128
5129       /* We only have a single condition code register.  We
5130          implement this by hiding all the condition code registers,
5131          and generating RTL that refers directly to ST_REG_FIRST.  */
5132       for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5133         fixed_regs[regno] = call_used_regs[regno] = 1;
5134     }
5135   /* In mips16 mode, we permit the $t temporary registers to be used
5136      for reload.  We prohibit the unused $s registers, since they
5137      are caller saved, and saving them via a mips16 register would
5138      probably waste more time than just reloading the value.  */
5139   if (TARGET_MIPS16)
5140     {
5141       fixed_regs[18] = call_used_regs[18] = 1;
5142       fixed_regs[19] = call_used_regs[19] = 1;
5143       fixed_regs[20] = call_used_regs[20] = 1;
5144       fixed_regs[21] = call_used_regs[21] = 1;
5145       fixed_regs[22] = call_used_regs[22] = 1;
5146       fixed_regs[23] = call_used_regs[23] = 1;
5147       fixed_regs[26] = call_used_regs[26] = 1;
5148       fixed_regs[27] = call_used_regs[27] = 1;
5149       fixed_regs[30] = call_used_regs[30] = 1;
5150     }
5151   /* fp20-23 are now caller saved.  */
5152   if (mips_abi == ABI_64)
5153     {
5154       int regno;
5155       for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5156         call_really_used_regs[regno] = call_used_regs[regno] = 1;
5157     }
5158   /* Odd registers from fp21 to fp31 are now caller saved.  */
5159   if (mips_abi == ABI_N32)
5160     {
5161       int regno;
5162       for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5163         call_really_used_regs[regno] = call_used_regs[regno] = 1;
5164     }
5165 }
5166
5167 /* Allocate a chunk of memory for per-function machine-dependent data.  */
5168 static struct machine_function *
5169 mips_init_machine_status (void)
5170 {
5171   return ((struct machine_function *)
5172           ggc_alloc_cleared (sizeof (struct machine_function)));
5173 }
5174
5175 /* On the mips16, we want to allocate $24 (T_REG) before other
5176    registers for instructions for which it is possible.  This helps
5177    avoid shuffling registers around in order to set up for an xor,
5178    encouraging the compiler to use a cmp instead.  */
5179
5180 void
5181 mips_order_regs_for_local_alloc (void)
5182 {
5183   register int i;
5184
5185   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5186     reg_alloc_order[i] = i;
5187
5188   if (TARGET_MIPS16)
5189     {
5190       /* It really doesn't matter where we put register 0, since it is
5191          a fixed register anyhow.  */
5192       reg_alloc_order[0] = 24;
5193       reg_alloc_order[24] = 0;
5194     }
5195 }
5196
5197 \f
5198 /* The MIPS debug format wants all automatic variables and arguments
5199    to be in terms of the virtual frame pointer (stack pointer before
5200    any adjustment in the function), while the MIPS 3.0 linker wants
5201    the frame pointer to be the stack pointer after the initial
5202    adjustment.  So, we do the adjustment here.  The arg pointer (which
5203    is eliminated) points to the virtual frame pointer, while the frame
5204    pointer (which may be eliminated) points to the stack pointer after
5205    the initial adjustments.  */
5206
5207 HOST_WIDE_INT
5208 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5209 {
5210   rtx offset2 = const0_rtx;
5211   rtx reg = eliminate_constant_term (addr, &offset2);
5212
5213   if (offset == 0)
5214     offset = INTVAL (offset2);
5215
5216   if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5217       || reg == hard_frame_pointer_rtx)
5218     {
5219       HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5220                                   ? compute_frame_size (get_frame_size ())
5221                                   : cfun->machine->frame.total_size;
5222
5223       /* MIPS16 frame is smaller */
5224       if (frame_pointer_needed && TARGET_MIPS16)
5225         frame_size -= cfun->machine->frame.args_size;
5226
5227       offset = offset - frame_size;
5228     }
5229
5230   /* sdbout_parms does not want this to crash for unrecognized cases.  */
5231 #if 0
5232   else if (reg != arg_pointer_rtx)
5233     fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5234                 addr);
5235 #endif
5236
5237   return offset;
5238 }
5239 \f
5240 /* Implement the PRINT_OPERAND macro.  The MIPS-specific operand codes are:
5241
5242    'X'  OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5243    'x'  OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5244    'h'  OP is HIGH, prints %hi(X),
5245    'd'  output integer constant in decimal,
5246    'z'  if the operand is 0, use $0 instead of normal operand.
5247    'D'  print second part of double-word register or memory operand.
5248    'L'  print low-order register of double-word register operand.
5249    'M'  print high-order register of double-word register operand.
5250    'C'  print part of opcode for a branch condition.
5251    'F'  print part of opcode for a floating-point branch condition.
5252    'N'  print part of opcode for a branch condition, inverted.
5253    'W'  print part of opcode for a floating-point branch condition, inverted.
5254    'S'  OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5255    'B'  print 'z' for EQ, 'n' for NE
5256    'b'  print 'n' for EQ, 'z' for NE
5257    'T'  print 'f' for EQ, 't' for NE
5258    't'  print 't' for EQ, 'f' for NE
5259    'Z'  print register and a comma, but print nothing for $fcc0
5260    'R'  print the reloc associated with LO_SUM
5261
5262    The punctuation characters are:
5263
5264    '('  Turn on .set noreorder
5265    ')'  Turn on .set reorder
5266    '['  Turn on .set noat
5267    ']'  Turn on .set at
5268    '<'  Turn on .set nomacro
5269    '>'  Turn on .set macro
5270    '{'  Turn on .set volatile (not GAS)
5271    '}'  Turn on .set novolatile (not GAS)
5272    '&'  Turn on .set noreorder if filling delay slots
5273    '*'  Turn on both .set noreorder and .set nomacro if filling delay slots
5274    '!'  Turn on .set nomacro if filling delay slots
5275    '#'  Print nop if in a .set noreorder section.
5276    '/'  Like '#', but does nothing within a delayed branch sequence
5277    '?'  Print 'l' if we are to use a branch likely instead of normal branch.
5278    '@'  Print the name of the assembler temporary register (at or $1).
5279    '.'  Print the name of the register with a hard-wired zero (zero or $0).
5280    '^'  Print the name of the pic call-through register (t9 or $25).
5281    '$'  Print the name of the stack pointer register (sp or $29).
5282    '+'  Print the name of the gp register (usually gp or $28).
5283    '~'  Output a branch alignment to LABEL_ALIGN(NULL).  */
5284
5285 void
5286 print_operand (FILE *file, rtx op, int letter)
5287 {
5288   register enum rtx_code code;
5289
5290   if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5291     {
5292       switch (letter)
5293         {
5294         case '?':
5295           if (mips_branch_likely)
5296             putc ('l', file);
5297           break;
5298
5299         case '@':
5300           fputs (reg_names [GP_REG_FIRST + 1], file);
5301           break;
5302
5303         case '^':
5304           fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5305           break;
5306
5307         case '.':
5308           fputs (reg_names [GP_REG_FIRST + 0], file);
5309           break;
5310
5311         case '$':
5312           fputs (reg_names[STACK_POINTER_REGNUM], file);
5313           break;
5314
5315         case '+':
5316           fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5317           break;
5318
5319         case '&':
5320           if (final_sequence != 0 && set_noreorder++ == 0)
5321             fputs (".set\tnoreorder\n\t", file);
5322           break;
5323
5324         case '*':
5325           if (final_sequence != 0)
5326             {
5327               if (set_noreorder++ == 0)
5328                 fputs (".set\tnoreorder\n\t", file);
5329
5330               if (set_nomacro++ == 0)
5331                 fputs (".set\tnomacro\n\t", file);
5332             }
5333           break;
5334
5335         case '!':
5336           if (final_sequence != 0 && set_nomacro++ == 0)
5337             fputs ("\n\t.set\tnomacro", file);
5338           break;
5339
5340         case '#':
5341           if (set_noreorder != 0)
5342             fputs ("\n\tnop", file);
5343           break;
5344
5345         case '/':
5346           /* Print an extra newline so that the delayed insn is separated
5347              from the following ones.  This looks neater and is consistent
5348              with non-nop delayed sequences.  */
5349           if (set_noreorder != 0 && final_sequence == 0)
5350             fputs ("\n\tnop\n", file);
5351           break;
5352
5353         case '(':
5354           if (set_noreorder++ == 0)
5355             fputs (".set\tnoreorder\n\t", file);
5356           break;
5357
5358         case ')':
5359           if (set_noreorder == 0)
5360             error ("internal error: %%) found without a %%( in assembler pattern");
5361
5362           else if (--set_noreorder == 0)
5363             fputs ("\n\t.set\treorder", file);
5364
5365           break;
5366
5367         case '[':
5368           if (set_noat++ == 0)
5369             fputs (".set\tnoat\n\t", file);
5370           break;
5371
5372         case ']':
5373           if (set_noat == 0)
5374             error ("internal error: %%] found without a %%[ in assembler pattern");
5375           else if (--set_noat == 0)
5376             fputs ("\n\t.set\tat", file);
5377
5378           break;
5379
5380         case '<':
5381           if (set_nomacro++ == 0)
5382             fputs (".set\tnomacro\n\t", file);
5383           break;
5384
5385         case '>':
5386           if (set_nomacro == 0)
5387             error ("internal error: %%> found without a %%< in assembler pattern");
5388           else if (--set_nomacro == 0)
5389             fputs ("\n\t.set\tmacro", file);
5390
5391           break;
5392
5393         case '{':
5394           if (set_volatile++ == 0)
5395             fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5396           break;
5397
5398         case '}':
5399           if (set_volatile == 0)
5400             error ("internal error: %%} found without a %%{ in assembler pattern");
5401           else if (--set_volatile == 0)
5402             fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5403
5404           break;
5405
5406         case '~':
5407           {
5408             if (align_labels_log > 0)
5409               ASM_OUTPUT_ALIGN (file, align_labels_log);
5410           }
5411         break;
5412
5413         default:
5414           error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5415           break;
5416         }
5417
5418       return;
5419     }
5420
5421   if (! op)
5422     {
5423       error ("PRINT_OPERAND null pointer");
5424       return;
5425     }
5426
5427   code = GET_CODE (op);
5428
5429   if (letter == 'C')
5430     switch (code)
5431       {
5432       case EQ:  fputs ("eq",  file); break;
5433       case NE:  fputs ("ne",  file); break;
5434       case GT:  fputs ("gt",  file); break;
5435       case GE:  fputs ("ge",  file); break;
5436       case LT:  fputs ("lt",  file); break;
5437       case LE:  fputs ("le",  file); break;
5438       case GTU: fputs ("gtu", file); break;
5439       case GEU: fputs ("geu", file); break;
5440       case LTU: fputs ("ltu", file); break;
5441       case LEU: fputs ("leu", file); break;
5442       default:
5443         fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5444       }
5445
5446   else if (letter == 'N')
5447     switch (code)
5448       {
5449       case EQ:  fputs ("ne",  file); break;
5450       case NE:  fputs ("eq",  file); break;
5451       case GT:  fputs ("le",  file); break;
5452       case GE:  fputs ("lt",  file); break;
5453       case LT:  fputs ("ge",  file); break;
5454       case LE:  fputs ("gt",  file); break;
5455       case GTU: fputs ("leu", file); break;
5456       case GEU: fputs ("ltu", file); break;
5457       case LTU: fputs ("geu", file); break;
5458       case LEU: fputs ("gtu", file); break;
5459       default:
5460         fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5461       }
5462
5463   else if (letter == 'F')
5464     switch (code)
5465       {
5466       case EQ: fputs ("c1f", file); break;
5467       case NE: fputs ("c1t", file); break;
5468       default:
5469         fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5470       }
5471
5472   else if (letter == 'W')
5473     switch (code)
5474       {
5475       case EQ: fputs ("c1t", file); break;
5476       case NE: fputs ("c1f", file); break;
5477       default:
5478         fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5479       }
5480
5481   else if (letter == 'h')
5482     {
5483       if (GET_CODE (op) == HIGH)
5484         op = XEXP (op, 0);
5485
5486       print_operand_reloc (file, op, mips_hi_relocs);
5487     }
5488
5489   else if (letter == 'R')
5490     print_operand_reloc (file, op, mips_lo_relocs);
5491
5492   else if (letter == 'S')
5493     {
5494       char buffer[100];
5495
5496       ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5497       assemble_name (file, buffer);
5498     }
5499
5500   else if (letter == 'Z')
5501     {
5502       register int regnum;
5503
5504       if (code != REG)
5505         abort ();
5506
5507       regnum = REGNO (op);
5508       if (! ST_REG_P (regnum))
5509         abort ();
5510
5511       if (regnum != ST_REG_FIRST)
5512         fprintf (file, "%s,", reg_names[regnum]);
5513     }
5514
5515   else if (code == REG || code == SUBREG)
5516     {
5517       register int regnum;
5518
5519       if (code == REG)
5520         regnum = REGNO (op);
5521       else
5522         regnum = true_regnum (op);
5523
5524       if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5525           || (letter == 'L' && WORDS_BIG_ENDIAN)
5526           || letter == 'D')
5527         regnum++;
5528
5529       fprintf (file, "%s", reg_names[regnum]);
5530     }
5531
5532   else if (code == MEM)
5533     {
5534       if (letter == 'D')
5535         output_address (plus_constant (XEXP (op, 0), 4));
5536       else
5537         output_address (XEXP (op, 0));
5538     }
5539
5540   else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5541     fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5542
5543   else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5544     fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5545
5546   else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5547     fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5548
5549   else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5550     fputs (reg_names[GP_REG_FIRST], file);
5551
5552   else if (letter == 'd' || letter == 'x' || letter == 'X')
5553     output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5554
5555   else if (letter == 'B')
5556     fputs (code == EQ ? "z" : "n", file);
5557   else if (letter == 'b')
5558     fputs (code == EQ ? "n" : "z", file);
5559   else if (letter == 'T')
5560     fputs (code == EQ ? "f" : "t", file);
5561   else if (letter == 't')
5562     fputs (code == EQ ? "t" : "f", file);
5563
5564   else if (CONST_GP_P (op))
5565     print_operand (file, XEXP (op, 0), letter);
5566
5567   else
5568     output_addr_const (file, op);
5569 }
5570
5571
5572 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5573    RELOCS is the array of relocations to use.  */
5574
5575 static void
5576 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5577 {
5578   enum mips_symbol_type symbol_type;
5579   const char *p;
5580   rtx base;
5581   HOST_WIDE_INT offset;
5582
5583   if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5584     fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5585
5586   /* If OP uses an UNSPEC address, we want to print the inner symbol.  */
5587   mips_split_const (op, &base, &offset);
5588   if (UNSPEC_ADDRESS_P (base))
5589     op = plus_constant (UNSPEC_ADDRESS (base), offset);
5590
5591   fputs (relocs[symbol_type], file);
5592   output_addr_const (file, op);
5593   for (p = relocs[symbol_type]; *p != 0; p++)
5594     if (*p == '(')
5595       fputc (')', file);
5596 }
5597 \f
5598 /* Output address operand X to FILE.  */
5599
5600 void
5601 print_operand_address (FILE *file, rtx x)
5602 {
5603   struct mips_address_info addr;
5604
5605   if (mips_classify_address (&addr, x, word_mode, true))
5606     switch (addr.type)
5607       {
5608       case ADDRESS_REG:
5609         print_operand (file, addr.offset, 0);
5610         fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5611         return;
5612
5613       case ADDRESS_LO_SUM:
5614         print_operand (file, addr.offset, 'R');
5615         fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5616         return;
5617
5618       case ADDRESS_CONST_INT:
5619       case ADDRESS_SYMBOLIC:
5620         output_addr_const (file, x);
5621         return;
5622       }
5623   abort ();
5624 }
5625 \f
5626 /* Target hook for assembling integer objects.  It appears that the Irix
5627    6 assembler can't handle 64-bit decimal integers, so avoid printing
5628    such an integer here.  */
5629
5630 static bool
5631 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5632 {
5633   if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5634     {
5635       fputs ("\t.dword\t", asm_out_file);
5636       if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5637         output_addr_const (asm_out_file, x);
5638       else
5639         print_operand (asm_out_file, x, 'X');
5640       fputc ('\n', asm_out_file);
5641       return true;
5642     }
5643   return default_assemble_integer (x, size, aligned_p);
5644 }
5645 \f
5646 /* When using assembler macros, keep track of all of small-data externs
5647    so that mips_file_end can emit the appropriate declarations for them.
5648
5649    In most cases it would be safe (though pointless) to emit .externs
5650    for other symbols too.  One exception is when an object is within
5651    the -G limit but declared by the user to be in a section other
5652    than .sbss or .sdata.  */
5653
5654 int
5655 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5656 {
5657   register struct extern_list *p;
5658
5659   if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5660     {
5661       p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5662       p->next = extern_head;
5663       p->name = name;
5664       p->size = int_size_in_bytes (TREE_TYPE (decl));
5665       extern_head = p;
5666     }
5667
5668   if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5669     {
5670       p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5671       p->next = extern_head;
5672       p->name = name;
5673       p->size = -1;
5674       extern_head = p;
5675     }
5676
5677   return 0;
5678 }
5679
5680 #if TARGET_IRIX
5681 void
5682 irix_output_external_libcall (rtx fun)
5683 {
5684   register struct extern_list *p;
5685
5686   if (mips_abi == ABI_32)
5687     {
5688       p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5689       p->next = extern_head;
5690       p->name = XSTR (fun, 0);
5691       p->size = -1;
5692       extern_head = p;
5693     }
5694 }
5695 #endif
5696 \f
5697 /* Emit a new filename to a stream.  If we are smuggling stabs, try to
5698    put out a MIPS ECOFF file and a stab.  */
5699
5700 void
5701 mips_output_filename (FILE *stream, const char *name)
5702 {
5703   char ltext_label_name[100];
5704
5705   /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5706      directives.  */
5707   if (write_symbols == DWARF2_DEBUG)
5708     return;
5709   else if (mips_output_filename_first_time)
5710     {
5711       mips_output_filename_first_time = 0;
5712       SET_FILE_NUMBER ();
5713       current_function_file = name;
5714       ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5715       /* This tells mips-tfile that stabs will follow.  */
5716       if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5717         fprintf (stream, "\t#@stabs\n");
5718     }
5719
5720   else if (write_symbols == DBX_DEBUG)
5721     {
5722       ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5723       fprintf (stream, "%s", ASM_STABS_OP);
5724       output_quoted_string (stream, name);
5725       fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
5726     }
5727
5728   else if (name != current_function_file
5729            && strcmp (name, current_function_file) != 0)
5730     {
5731       SET_FILE_NUMBER ();
5732       current_function_file = name;
5733       ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5734     }
5735 }
5736 \f
5737 /* Emit a linenumber.  For encapsulated stabs, we need to put out a stab
5738    as well as a .loc, since it is possible that MIPS ECOFF might not be
5739    able to represent the location for inlines that come from a different
5740    file.  */
5741
5742 void
5743 mips_output_lineno (FILE *stream, int line)
5744 {
5745   if (write_symbols == DBX_DEBUG)
5746     {
5747       ++sym_lineno;
5748       fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5749                LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5750                LOCAL_LABEL_PREFIX, sym_lineno);
5751     }
5752   else
5753     {
5754       fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5755       LABEL_AFTER_LOC (stream);
5756     }
5757 }
5758 \f
5759 /* Output an ASCII string, in a space-saving way.  PREFIX is the string
5760    that should be written before the opening quote, such as "\t.ascii\t"
5761    for real string data or "\t# " for a comment.  */
5762
5763 void
5764 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5765                    const char *prefix)
5766 {
5767   size_t i;
5768   int cur_pos = 17;
5769   register const unsigned char *string =
5770     (const unsigned char *)string_param;
5771
5772   fprintf (stream, "%s\"", prefix);
5773   for (i = 0; i < len; i++)
5774     {
5775       register int c = string[i];
5776
5777       switch (c)
5778         {
5779         case '\"':
5780         case '\\':
5781           putc ('\\', stream);
5782           putc (c, stream);
5783           cur_pos += 2;
5784           break;
5785
5786         case TARGET_NEWLINE:
5787           fputs ("\\n", stream);
5788           if (i+1 < len
5789               && (((c = string[i+1]) >= '\040' && c <= '~')
5790                   || c == TARGET_TAB))
5791             cur_pos = 32767;            /* break right here */
5792           else
5793             cur_pos += 2;
5794           break;
5795
5796         case TARGET_TAB:
5797           fputs ("\\t", stream);
5798           cur_pos += 2;
5799           break;
5800
5801         case TARGET_FF:
5802           fputs ("\\f", stream);
5803           cur_pos += 2;
5804           break;
5805
5806         case TARGET_BS:
5807           fputs ("\\b", stream);
5808           cur_pos += 2;
5809           break;
5810
5811         case TARGET_CR:
5812           fputs ("\\r", stream);
5813           cur_pos += 2;
5814           break;
5815
5816         default:
5817           if (c >= ' ' && c < 0177)
5818             {
5819               putc (c, stream);
5820               cur_pos++;
5821             }
5822           else
5823             {
5824               fprintf (stream, "\\%03o", c);
5825               cur_pos += 4;
5826             }
5827         }
5828
5829       if (cur_pos > 72 && i+1 < len)
5830         {
5831           cur_pos = 17;
5832           fprintf (stream, "\"\n%s\"", prefix);
5833         }
5834     }
5835   fprintf (stream, "\"\n");
5836 }
5837 \f
5838 /* Implement TARGET_ASM_FILE_START.  */
5839
5840 static void
5841 mips_file_start (void)
5842 {
5843   default_file_start ();
5844
5845   /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5846      inside of a .set noreorder section jumps to a label outside of the .set
5847      noreorder section.  Revision 2.20 just set nobopt silently rather than
5848      fixing the bug.  */
5849
5850   if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5851     fprintf (asm_out_file, "\t.set\tnobopt\n");
5852
5853   if (TARGET_GAS)
5854     {
5855 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5856       /* Generate a special section to describe the ABI switches used to
5857          produce the resultant binary.  This used to be done by the assembler
5858          setting bits in the ELF header's flags field, but we have run out of
5859          bits.  GDB needs this information in order to be able to correctly
5860          debug these binaries.  See the function mips_gdbarch_init() in
5861          gdb/mips-tdep.c.  This is unnecessary for the IRIX 5/6 ABIs and
5862          causes unnecessary IRIX 6 ld warnings.  */
5863       const char * abi_string = NULL;
5864
5865       switch (mips_abi)
5866         {
5867         case ABI_32:   abi_string = "abi32"; break;
5868         case ABI_N32:  abi_string = "abiN32"; break;
5869         case ABI_64:   abi_string = "abi64"; break;
5870         case ABI_O64:  abi_string = "abiO64"; break;
5871         case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5872         default:
5873           abort ();
5874         }
5875       /* Note - we use fprintf directly rather than called named_section()
5876          because in this way we can avoid creating an allocated section.  We
5877          do not want this section to take up any space in the running
5878          executable.  */
5879       fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5880
5881       /* Restore the default section.  */
5882       fprintf (asm_out_file, "\t.previous\n");
5883 #endif
5884     }
5885
5886   /* Generate the pseudo ops that System V.4 wants.  */
5887 #ifndef ABICALLS_ASM_OP
5888 #define ABICALLS_ASM_OP "\t.abicalls"
5889 #endif
5890   if (TARGET_ABICALLS)
5891     /* ??? but do not want this (or want pic0) if -non-shared? */
5892     fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5893
5894   if (TARGET_MIPS16)
5895     fprintf (asm_out_file, "\t.set\tmips16\n");
5896
5897   if (flag_verbose_asm)
5898     fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5899              ASM_COMMENT_START,
5900              mips_section_threshold, mips_arch_info->name, mips_isa);
5901 }
5902
5903 #ifdef BSS_SECTION_ASM_OP
5904 /* Implement ASM_OUTPUT_ALIGNED_BSS.  This differs from the default only
5905    in the use of sbss.  */
5906
5907 void
5908 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5909                          unsigned HOST_WIDE_INT size, int align)
5910 {
5911   extern tree last_assemble_variable_decl;
5912
5913   if (mips_in_small_data_p (decl))
5914     named_section (0, ".sbss", 0);
5915   else
5916     bss_section ();
5917   ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5918   last_assemble_variable_decl = decl;
5919   ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5920   ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5921 }
5922 #endif
5923 \f
5924 /* Implement TARGET_ASM_FILE_END.  When using assembler macros, emit
5925    .externs for any small-data variables that turned out to be external.  */
5926
5927 static void
5928 mips_file_end (void)
5929 {
5930   tree name_tree;
5931   struct extern_list *p;
5932
5933   if (extern_head)
5934     {
5935       fputs ("\n", asm_out_file);
5936
5937       for (p = extern_head; p != 0; p = p->next)
5938         {
5939           name_tree = get_identifier (p->name);
5940
5941           /* Positively ensure only one .extern for any given symbol.  */
5942           if (!TREE_ASM_WRITTEN (name_tree)
5943               && TREE_SYMBOL_REFERENCED (name_tree))
5944             {
5945               TREE_ASM_WRITTEN (name_tree) = 1;
5946               /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5947                  `.global name .text' directive for every used but
5948                  undefined function.  If we don't, the linker may perform
5949                  an optimization (skipping over the insns that set $gp)
5950                  when it is unsafe.  */
5951               if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5952                 {
5953                   fputs ("\t.globl ", asm_out_file);
5954                   assemble_name (asm_out_file, p->name);
5955                   fputs (" .text\n", asm_out_file);
5956                 }
5957               else
5958                 {
5959                   fputs ("\t.extern\t", asm_out_file);
5960                   assemble_name (asm_out_file, p->name);
5961                   fprintf (asm_out_file, ", %d\n", p->size);
5962                 }
5963             }
5964         }
5965     }
5966 }
5967
5968 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON.  This is usually the same as
5969    the elfos.h version, but we also need to handle -muninit-const-in-rodata
5970    and the limitations of the SGI o32 assembler.  */
5971
5972 void
5973 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5974                                  unsigned HOST_WIDE_INT size,
5975                                  unsigned int align)
5976 {
5977   /* If the target wants uninitialized const declarations in
5978      .rdata then don't put them in .comm.   */
5979   if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5980       && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5981       && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5982     {
5983       if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5984         targetm.asm_out.globalize_label (stream, name);
5985
5986       readonly_data_section ();
5987       ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5988       mips_declare_object (stream, name, "",
5989                            ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5990                            size);
5991     }
5992   else if (TARGET_SGI_O32_AS)
5993     {
5994       /* The SGI o32 assembler doesn't accept an alignment, so round up
5995          the size instead.  */
5996       size += (align / BITS_PER_UNIT) - 1;
5997       size -= size % (align / BITS_PER_UNIT);
5998       mips_declare_object (stream, name, "\n\t.comm\t",
5999                            "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6000     }
6001   else
6002     mips_declare_object (stream, name, "\n\t.comm\t",
6003                          "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6004                          size, align / BITS_PER_UNIT);
6005 }
6006
6007 /* Emit either a label, .comm, or .lcomm directive.  When using assembler
6008    macros, mark the symbol as written so that mips_file_end won't emit an
6009    .extern for it.  STREAM is the output file, NAME is the name of the
6010    symbol, INIT_STRING is the string that should be written before the
6011    symbol and FINAL_STRING is the string that shoulbe written after it.
6012    FINAL_STRING is a printf() format that consumes the remaining arguments.  */
6013
6014 void
6015 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6016                      const char *final_string, ...)
6017 {
6018   va_list ap;
6019
6020   fputs (init_string, stream);
6021   assemble_name (stream, name);
6022   va_start (ap, final_string);
6023   vfprintf (stream, final_string, ap);
6024   va_end (ap);
6025
6026   if (!TARGET_EXPLICIT_RELOCS)
6027     {
6028       tree name_tree = get_identifier (name);
6029       TREE_ASM_WRITTEN (name_tree) = 1;
6030     }
6031 }
6032
6033 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6034 extern int size_directive_output;
6035
6036 /* Implement ASM_DECLARE_OBJECT_NAME.  This is like most of the standard ELF
6037    definitions except that it uses mips_declare_object() to emit the label.  */
6038
6039 void
6040 mips_declare_object_name (FILE *stream, const char *name,
6041                           tree decl ATTRIBUTE_UNUSED)
6042 {
6043   if (!TARGET_SGI_O32_AS)
6044     {
6045 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6046       ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6047 #endif
6048
6049       size_directive_output = 0;
6050       if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6051         {
6052           HOST_WIDE_INT size;
6053
6054           size_directive_output = 1;
6055           size = int_size_in_bytes (TREE_TYPE (decl));
6056           ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6057         }
6058     }
6059
6060   mips_declare_object (stream, name, "", ":\n", 0);
6061 }
6062
6063 /* Implement ASM_FINISH_DECLARE_OBJECT.  This is generic ELF stuff.  */
6064
6065 void
6066 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6067 {
6068   const char *name;
6069
6070   name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6071   if (!TARGET_SGI_O32_AS
6072       && !flag_inhibit_size_directive
6073       && DECL_SIZE (decl) != 0
6074       && !at_end && top_level
6075       && DECL_INITIAL (decl) == error_mark_node
6076       && !size_directive_output)
6077     {
6078       HOST_WIDE_INT size;
6079
6080       size_directive_output = 1;
6081       size = int_size_in_bytes (TREE_TYPE (decl));
6082       ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6083     }
6084 }
6085 #endif
6086 \f
6087 /* Return true if X is a small data address that can be rewritten
6088    as a LO_SUM.  */
6089
6090 static bool
6091 mips_rewrite_small_data_p (rtx x)
6092 {
6093   enum mips_symbol_type symbol_type;
6094
6095   return (TARGET_EXPLICIT_RELOCS
6096           && mips_symbolic_constant_p (x, &symbol_type)
6097           && symbol_type == SYMBOL_SMALL_DATA);
6098 }
6099
6100
6101 /* A for_each_rtx callback for small_data_pattern.  */
6102
6103 static int
6104 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6105 {
6106   if (GET_CODE (*loc) == LO_SUM)
6107     return -1;
6108
6109   return mips_rewrite_small_data_p (*loc);
6110 }
6111
6112 /* Return true if OP refers to small data symbols directly, not through
6113    a LO_SUM.  */
6114
6115 int
6116 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6117 {
6118   return (GET_CODE (op) != SEQUENCE
6119           && for_each_rtx (&op, small_data_pattern_1, 0));
6120 }
6121 \f
6122 /* A for_each_rtx callback, used by mips_rewrite_small_data.  */
6123
6124 static int
6125 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6126 {
6127   if (mips_rewrite_small_data_p (*loc))
6128     *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6129
6130   if (GET_CODE (*loc) == LO_SUM)
6131     return -1;
6132
6133   return 0;
6134 }
6135
6136 /* If possible, rewrite OP so that it refers to small data using
6137    explicit relocations.  */
6138
6139 rtx
6140 mips_rewrite_small_data (rtx op)
6141 {
6142   op = copy_insn (op);
6143   for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6144   return op;
6145 }
6146 \f
6147 /* Return true if the current function has an insn that implicitly
6148    refers to $gp.  */
6149
6150 static bool
6151 mips_function_has_gp_insn (void)
6152 {
6153   /* Don't bother rechecking if we found one last time.  */
6154   if (!cfun->machine->has_gp_insn_p)
6155     {
6156       rtx insn;
6157
6158       push_topmost_sequence ();
6159       for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6160         if (INSN_P (insn)
6161             && GET_CODE (PATTERN (insn)) != USE
6162             && GET_CODE (PATTERN (insn)) != CLOBBER
6163             && (get_attr_got (insn) != GOT_UNSET
6164                 || small_data_pattern (PATTERN (insn), VOIDmode)))
6165           break;
6166       pop_topmost_sequence ();
6167
6168       cfun->machine->has_gp_insn_p = (insn != 0);
6169     }
6170   return cfun->machine->has_gp_insn_p;
6171 }
6172
6173
6174 /* Return the register that should be used as the global pointer
6175    within this function.  Return 0 if the function doesn't need
6176    a global pointer.  */
6177
6178 static unsigned int
6179 mips_global_pointer (void)
6180 {
6181   unsigned int regno;
6182
6183   /* $gp is always available in non-abicalls code.  */
6184   if (!TARGET_ABICALLS)
6185     return GLOBAL_POINTER_REGNUM;
6186
6187   /* We must always provide $gp when it is used implicitly.  */
6188   if (!TARGET_EXPLICIT_RELOCS)
6189     return GLOBAL_POINTER_REGNUM;
6190
6191   /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6192      a valid gp.  */
6193   if (current_function_profile)
6194     return GLOBAL_POINTER_REGNUM;
6195
6196   /* If the function has a nonlocal goto, $gp must hold the correct
6197      global pointer for the target function.  */
6198   if (current_function_has_nonlocal_goto)
6199     return GLOBAL_POINTER_REGNUM;
6200
6201   /* If the gp is never referenced, there's no need to initialize it.
6202      Note that reload can sometimes introduce constant pool references
6203      into a function that otherwise didn't need them.  For example,
6204      suppose we have an instruction like:
6205
6206           (set (reg:DF R1) (float:DF (reg:SI R2)))
6207
6208      If R2 turns out to be constant such as 1, the instruction may have a
6209      REG_EQUAL note saying that R1 == 1.0.  Reload then has the option of
6210      using this constant if R2 doesn't get allocated to a register.
6211
6212      In cases like these, reload will have added the constant to the pool
6213      but no instruction will yet refer to it.  */
6214   if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6215       && !current_function_uses_const_pool
6216       && !mips_function_has_gp_insn ())
6217     return 0;
6218
6219   /* We need a global pointer, but perhaps we can use a call-clobbered
6220      register instead of $gp.  */
6221   if (TARGET_NEWABI && current_function_is_leaf)
6222     for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6223       if (!regs_ever_live[regno]
6224           && call_used_regs[regno]
6225           && !fixed_regs[regno]
6226           && regno != PIC_FUNCTION_ADDR_REGNUM)
6227         return regno;
6228
6229   return GLOBAL_POINTER_REGNUM;
6230 }
6231
6232
6233 /* Return true if the current function must save REGNO.  */
6234
6235 static bool
6236 mips_save_reg_p (unsigned int regno)
6237 {
6238   /* We only need to save $gp for NewABI PIC.  */
6239   if (regno == GLOBAL_POINTER_REGNUM)
6240     return (TARGET_ABICALLS && TARGET_NEWABI
6241             && cfun->machine->global_pointer == regno);
6242
6243   /* Check call-saved registers.  */
6244   if (regs_ever_live[regno] && !call_used_regs[regno])
6245     return true;
6246
6247   /* We need to save the old frame pointer before setting up a new one.  */
6248   if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6249     return true;
6250
6251   /* We need to save the incoming return address if it is ever clobbered
6252      within the function.  */
6253   if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6254     return true;
6255
6256   if (TARGET_MIPS16)
6257     {
6258       tree return_type;
6259
6260       return_type = DECL_RESULT (current_function_decl);
6261
6262       /* $18 is a special case in mips16 code.  It may be used to call
6263          a function which returns a floating point value, but it is
6264          marked in call_used_regs.  */
6265       if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6266         return true;
6267
6268       /* $31 is also a special case.  It will be used to copy a return
6269          value into the floating point registers if the return value is
6270          floating point.  */
6271       if (regno == GP_REG_FIRST + 31
6272           && mips16_hard_float
6273           && !aggregate_value_p (return_type, current_function_decl)
6274           && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6275           && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6276         return true;
6277     }
6278
6279   return false;
6280 }
6281
6282
6283 /* Return the bytes needed to compute the frame pointer from the current
6284    stack pointer.  SIZE is the size (in bytes) of the local variables.
6285
6286    Mips stack frames look like:
6287
6288              Before call                        After call
6289         +-----------------------+       +-----------------------+
6290    high |                       |       |                       |
6291    mem. |                       |       |                       |
6292         |  caller's temps.      |       |  caller's temps.      |
6293         |                       |       |                       |
6294         +-----------------------+       +-----------------------+
6295         |                       |       |                       |
6296         |  arguments on stack.  |       |  arguments on stack.  |
6297         |                       |       |                       |
6298         +-----------------------+       +-----------------------+
6299         |  4 words to save      |       |  4 words to save      |
6300         |  arguments passed     |       |  arguments passed     |
6301         |  in registers, even   |       |  in registers, even   |
6302     SP->|  if not passed.       |  VFP->|  if not passed.       |
6303         +-----------------------+       +-----------------------+
6304                                         |                       |
6305                                         |  fp register save     |
6306                                         |                       |
6307                                         +-----------------------+
6308                                         |                       |
6309                                         |  gp register save     |
6310                                         |                       |
6311                                         +-----------------------+
6312                                         |                       |
6313                                         |  local variables      |
6314                                         |                       |
6315                                         +-----------------------+
6316                                         |                       |
6317                                         |  alloca allocations   |
6318                                         |                       |
6319                                         +-----------------------+
6320                                         |                       |
6321                                         |  GP save for V.4 abi  |
6322                                         |                       |
6323                                         +-----------------------+
6324                                         |                       |
6325                                         |  arguments on stack   |
6326                                         |                       |
6327                                         +-----------------------+
6328                                         |  4 words to save      |
6329                                         |  arguments passed     |
6330                                         |  in registers, even   |
6331    low                              SP->|  if not passed.       |
6332    memory                               +-----------------------+
6333
6334 */
6335
6336 HOST_WIDE_INT
6337 compute_frame_size (HOST_WIDE_INT size)
6338 {
6339   unsigned int regno;
6340   HOST_WIDE_INT total_size;     /* # bytes that the entire frame takes up */
6341   HOST_WIDE_INT var_size;       /* # bytes that variables take up */
6342   HOST_WIDE_INT args_size;      /* # bytes that outgoing arguments take up */
6343   HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6344   HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6345   HOST_WIDE_INT gp_reg_size;    /* # bytes needed to store gp regs */
6346   HOST_WIDE_INT fp_reg_size;    /* # bytes needed to store fp regs */
6347   unsigned int mask;            /* mask of saved gp registers */
6348   unsigned int fmask;           /* mask of saved fp registers */
6349
6350   cfun->machine->global_pointer = mips_global_pointer ();
6351
6352   gp_reg_size = 0;
6353   fp_reg_size = 0;
6354   mask = 0;
6355   fmask = 0;
6356   var_size = MIPS_STACK_ALIGN (size);
6357   args_size = current_function_outgoing_args_size;
6358   cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6359
6360   /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6361      functions.  If the function has local variables, we're committed
6362      to allocating it anyway.  Otherwise reclaim it here.  */
6363   if (var_size == 0 && current_function_is_leaf)
6364     cprestore_size = args_size = 0;
6365
6366   /* The MIPS 3.0 linker does not like functions that dynamically
6367      allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6368      looks like we are trying to create a second frame pointer to the
6369      function, so allocate some stack space to make it happy.  */
6370
6371   if (args_size == 0 && current_function_calls_alloca)
6372     args_size = 4 * UNITS_PER_WORD;
6373
6374   total_size = var_size + args_size + cprestore_size;
6375
6376   /* Calculate space needed for gp registers.  */
6377   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6378     if (mips_save_reg_p (regno))
6379       {
6380         gp_reg_size += GET_MODE_SIZE (gpr_mode);
6381         mask |= 1 << (regno - GP_REG_FIRST);
6382       }
6383
6384   /* We need to restore these for the handler.  */
6385   if (current_function_calls_eh_return)
6386     {
6387       unsigned int i;
6388       for (i = 0; ; ++i)
6389         {
6390           regno = EH_RETURN_DATA_REGNO (i);
6391           if (regno == INVALID_REGNUM)
6392             break;
6393           gp_reg_size += GET_MODE_SIZE (gpr_mode);
6394           mask |= 1 << (regno - GP_REG_FIRST);
6395         }
6396     }
6397
6398   /* This loop must iterate over the same space as its companion in
6399      save_restore_insns.  */
6400   for (regno = (FP_REG_LAST - FP_INC + 1);
6401        regno >= FP_REG_FIRST;
6402        regno -= FP_INC)
6403     {
6404       if (mips_save_reg_p (regno))
6405         {
6406           fp_reg_size += FP_INC * UNITS_PER_FPREG;
6407           fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6408         }
6409     }
6410
6411   gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6412   total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6413
6414   /* Add in space reserved on the stack by the callee for storing arguments
6415      passed in registers.  */
6416   if (!TARGET_OLDABI)
6417     total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6418
6419   /* Save other computed information.  */
6420   cfun->machine->frame.total_size = total_size;
6421   cfun->machine->frame.var_size = var_size;
6422   cfun->machine->frame.args_size = args_size;
6423   cfun->machine->frame.cprestore_size = cprestore_size;
6424   cfun->machine->frame.gp_reg_size = gp_reg_size;
6425   cfun->machine->frame.fp_reg_size = fp_reg_size;
6426   cfun->machine->frame.mask = mask;
6427   cfun->machine->frame.fmask = fmask;
6428   cfun->machine->frame.initialized = reload_completed;
6429   cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6430   cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6431
6432   if (mask)
6433     {
6434       HOST_WIDE_INT offset;
6435
6436       offset = (args_size + cprestore_size + var_size
6437                 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6438       cfun->machine->frame.gp_sp_offset = offset;
6439       cfun->machine->frame.gp_save_offset = offset - total_size;
6440     }
6441   else
6442     {
6443       cfun->machine->frame.gp_sp_offset = 0;
6444       cfun->machine->frame.gp_save_offset = 0;
6445     }
6446
6447   if (fmask)
6448     {
6449       HOST_WIDE_INT offset;
6450
6451       offset = (args_size + cprestore_size + var_size
6452                 + gp_reg_rounded + fp_reg_size
6453                 - FP_INC * UNITS_PER_FPREG);
6454       cfun->machine->frame.fp_sp_offset = offset;
6455       cfun->machine->frame.fp_save_offset = offset - total_size;
6456     }
6457   else
6458     {
6459       cfun->machine->frame.fp_sp_offset = 0;
6460       cfun->machine->frame.fp_save_offset = 0;
6461     }
6462
6463   /* Ok, we're done.  */
6464   return total_size;
6465 }
6466 \f
6467 /* Implement INITIAL_ELIMINATION_OFFSET.  FROM is either the frame
6468    pointer or argument pointer.  TO is either the stack pointer or
6469    hard frame pointer.  */
6470
6471 HOST_WIDE_INT
6472 mips_initial_elimination_offset (int from, int to)
6473 {
6474   HOST_WIDE_INT offset;
6475
6476   compute_frame_size (get_frame_size ());
6477
6478   /* Set OFFSET to the offset from the stack pointer.  */
6479   switch (from)
6480     {
6481     case FRAME_POINTER_REGNUM:
6482       offset = 0;
6483       break;
6484
6485     case ARG_POINTER_REGNUM:
6486       offset = cfun->machine->frame.total_size;
6487       if (TARGET_NEWABI)
6488         offset -= current_function_pretend_args_size;
6489       break;
6490
6491     default:
6492       abort ();
6493     }
6494
6495   if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6496     offset -= cfun->machine->frame.args_size;
6497
6498   return offset;
6499 }
6500 \f
6501 /* Implement RETURN_ADDR_RTX.  Note, we do not support moving
6502    back to a previous frame.  */
6503 rtx
6504 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6505 {
6506   if (count != 0)
6507     return const0_rtx;
6508
6509   return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6510 }
6511 \f
6512 /* Use FN to save or restore register REGNO.  MODE is the register's
6513    mode and OFFSET is the offset of its save slot from the current
6514    stack pointer.  */
6515
6516 static void
6517 mips_save_restore_reg (enum machine_mode mode, int regno,
6518                        HOST_WIDE_INT offset, mips_save_restore_fn fn)
6519 {
6520   rtx mem;
6521
6522   mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6523   if (!current_function_calls_eh_return)
6524     RTX_UNCHANGING_P (mem) = 1;
6525
6526   fn (gen_rtx_REG (mode, regno), mem);
6527 }
6528
6529
6530 /* Call FN for each register that is saved by the current function.
6531    SP_OFFSET is the offset of the current stack pointer from the start
6532    of the frame.  */
6533
6534 static void
6535 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6536 {
6537 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6538
6539   enum machine_mode fpr_mode;
6540   HOST_WIDE_INT offset;
6541   int regno;
6542
6543   /* Save registers starting from high to low.  The debuggers prefer at least
6544      the return register be stored at func+4, and also it allows us not to
6545      need a nop in the epilog if at least one register is reloaded in
6546      addition to return address.  */
6547   offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6548   for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6549     if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6550       {
6551         mips_save_restore_reg (gpr_mode, regno, offset, fn);
6552         offset -= GET_MODE_SIZE (gpr_mode);
6553       }
6554
6555   /* This loop must iterate over the same space as its companion in
6556      compute_frame_size.  */
6557   offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6558   fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6559   for (regno = (FP_REG_LAST - FP_INC + 1);
6560        regno >= FP_REG_FIRST;
6561        regno -= FP_INC)
6562     if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6563       {
6564         mips_save_restore_reg (fpr_mode, regno, offset, fn);
6565         offset -= GET_MODE_SIZE (fpr_mode);
6566       }
6567 #undef BITSET_P
6568 }
6569 \f
6570 /* If we're generating n32 or n64 abicalls, and the current function
6571    does not use $28 as its global pointer, emit a cplocal directive.
6572    Use pic_offset_table_rtx as the argument to the directive.  */
6573
6574 static void
6575 mips_output_cplocal (void)
6576 {
6577   if (!TARGET_EXPLICIT_RELOCS
6578       && cfun->machine->global_pointer > 0
6579       && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6580     output_asm_insn (".cplocal %+", 0);
6581 }
6582
6583 /* If we're generating n32 or n64 abicalls, emit instructions
6584    to set up the global pointer.  */
6585
6586 static void
6587 mips_emit_loadgp (void)
6588 {
6589   if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6590     {
6591       rtx addr, offset, incoming_address;
6592
6593       addr = XEXP (DECL_RTL (current_function_decl), 0);
6594       offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6595       incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6596       emit_insn (gen_loadgp (offset, incoming_address));
6597       if (!TARGET_EXPLICIT_RELOCS)
6598         emit_insn (gen_loadgp_blockage ());
6599     }
6600 }
6601
6602 /* Set up the stack and frame (if desired) for the function.  */
6603
6604 static void
6605 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6606 {
6607   const char *fnname;
6608   HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6609
6610   /* ??? When is this really needed?  At least the GNU assembler does not
6611      need the source filename more than once in the file, beyond what is
6612      emitted by the debug information.  */
6613   if (!TARGET_GAS)
6614     ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6615
6616 #ifdef SDB_DEBUGGING_INFO
6617   if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6618     ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6619 #endif
6620
6621   /* In mips16 mode, we may need to generate a 32 bit to handle
6622      floating point arguments.  The linker will arrange for any 32 bit
6623      functions to call this stub, which will then jump to the 16 bit
6624      function proper.  */
6625   if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6626       && current_function_args_info.fp_code != 0)
6627     build_mips16_function_stub (file);
6628
6629   if (!FUNCTION_NAME_ALREADY_DECLARED)
6630     {
6631       /* Get the function name the same way that toplev.c does before calling
6632          assemble_start_function.  This is needed so that the name used here
6633          exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
6634       fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6635
6636       if (!flag_inhibit_size_directive)
6637         {
6638           fputs ("\t.ent\t", file);
6639           assemble_name (file, fnname);
6640           fputs ("\n", file);
6641         }
6642
6643       assemble_name (file, fnname);
6644       fputs (":\n", file);
6645     }
6646
6647   if (!flag_inhibit_size_directive)
6648     {
6649       /* .frame FRAMEREG, FRAMESIZE, RETREG */
6650       fprintf (file,
6651                "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6652                "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6653                ", args= " HOST_WIDE_INT_PRINT_DEC
6654                ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6655                (reg_names[(frame_pointer_needed)
6656                           ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6657                ((frame_pointer_needed && TARGET_MIPS16)
6658                 ? tsize - cfun->machine->frame.args_size
6659                 : tsize),
6660                reg_names[GP_REG_FIRST + 31],
6661                cfun->machine->frame.var_size,
6662                cfun->machine->frame.num_gp,
6663                cfun->machine->frame.num_fp,
6664                cfun->machine->frame.args_size,
6665                cfun->machine->frame.cprestore_size);
6666
6667       /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6668       fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6669                cfun->machine->frame.mask,
6670                cfun->machine->frame.gp_save_offset);
6671       fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6672                cfun->machine->frame.fmask,
6673                cfun->machine->frame.fp_save_offset);
6674
6675       /* Require:
6676          OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6677          HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs.  */
6678     }
6679
6680   if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6681     {
6682       /* Handle the initialization of $gp for SVR4 PIC.  */
6683       if (!cfun->machine->all_noreorder_p)
6684         output_asm_insn ("%(.cpload\t%^%)", 0);
6685       else
6686         output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6687     }
6688   else if (cfun->machine->all_noreorder_p)
6689     output_asm_insn ("%(%<", 0);
6690
6691   /* Tell the assembler which register we're using as the global
6692      pointer.  This is needed for thunks, since they can use either
6693      explicit relocs or assembler macros.  */
6694   mips_output_cplocal ();
6695 }
6696 \f
6697 /* Make the last instruction frame related and note that it performs
6698    the operation described by FRAME_PATTERN.  */
6699
6700 static void
6701 mips_set_frame_expr (rtx frame_pattern)
6702 {
6703   rtx insn;
6704
6705   insn = get_last_insn ();
6706   RTX_FRAME_RELATED_P (insn) = 1;
6707   REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6708                                       frame_pattern,
6709                                       REG_NOTES (insn));
6710 }
6711
6712
6713 /* Return a frame-related rtx that stores REG at MEM.
6714    REG must be a single register.  */
6715
6716 static rtx
6717 mips_frame_set (rtx mem, rtx reg)
6718 {
6719   rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6720   RTX_FRAME_RELATED_P (set) = 1;
6721   return set;
6722 }
6723
6724
6725 /* Save register REG to MEM.  Make the instruction frame-related.  */
6726
6727 static void
6728 mips_save_reg (rtx reg, rtx mem)
6729 {
6730   if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6731     {
6732       rtx x1, x2;
6733
6734       if (mips_split_64bit_move_p (mem, reg))
6735         mips_split_64bit_move (mem, reg);
6736       else
6737         emit_move_insn (mem, reg);
6738
6739       x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6740       x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6741       mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6742     }
6743   else
6744     {
6745       if (TARGET_MIPS16
6746           && REGNO (reg) != GP_REG_FIRST + 31
6747           && !M16_REG_P (REGNO (reg)))
6748         {
6749           /* Save a non-mips16 register by moving it through a temporary.
6750              We don't need to do this for $31 since there's a special
6751              instruction for it.  */
6752           emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6753           emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6754         }
6755       else
6756         emit_move_insn (mem, reg);
6757
6758       mips_set_frame_expr (mips_frame_set (mem, reg));
6759     }
6760 }
6761
6762
6763 /* Expand the prologue into a bunch of separate insns.  */
6764
6765 void
6766 mips_expand_prologue (void)
6767 {
6768   HOST_WIDE_INT size;
6769
6770   if (cfun->machine->global_pointer > 0)
6771     REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6772
6773   size = compute_frame_size (get_frame_size ());
6774
6775   /* Save the registers.  Allocate up to MIPS_MAX_FIRST_STACK_STEP
6776      bytes beforehand; this is enough to cover the register save area
6777      without going out of range.  */
6778   if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6779     {
6780       HOST_WIDE_INT step1;
6781
6782       step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6783       RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6784                                                      stack_pointer_rtx,
6785                                                      GEN_INT (-step1)))) = 1;
6786       size -= step1;
6787       mips_for_each_saved_reg (size, mips_save_reg);
6788     }
6789
6790   /* Allocate the rest of the frame.  */
6791   if (size > 0)
6792     {
6793       if (SMALL_OPERAND (-size))
6794         RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6795                                                        stack_pointer_rtx,
6796                                                        GEN_INT (-size)))) = 1;
6797       else
6798         {
6799           emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6800           if (TARGET_MIPS16)
6801             {
6802               /* There are no instructions to add or subtract registers
6803                  from the stack pointer, so use the frame pointer as a
6804                  temporary.  We should always be using a frame pointer
6805                  in this case anyway.  */
6806               if (!frame_pointer_needed)
6807                 abort ();
6808
6809               emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6810               emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6811                                         hard_frame_pointer_rtx,
6812                                         MIPS_PROLOGUE_TEMP (Pmode)));
6813               emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6814             }
6815           else
6816             emit_insn (gen_sub3_insn (stack_pointer_rtx,
6817                                       stack_pointer_rtx,
6818                                       MIPS_PROLOGUE_TEMP (Pmode)));
6819
6820           /* Describe the combined effect of the previous instructions.  */
6821           mips_set_frame_expr
6822             (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6823                           plus_constant (stack_pointer_rtx, -size)));
6824         }
6825     }
6826
6827   /* Set up the frame pointer, if we're using one.  In mips16 code,
6828      we point the frame pointer ahead of the outgoing argument area.
6829      This should allow more variables & incoming arguments to be
6830      accessed with unextended instructions.  */
6831   if (frame_pointer_needed)
6832     {
6833       if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6834         {
6835           rtx offset = GEN_INT (cfun->machine->frame.args_size);
6836           RTX_FRAME_RELATED_P
6837             (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6838                                        stack_pointer_rtx,
6839                                        offset))) = 1;
6840         }
6841       else
6842         RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6843                                              stack_pointer_rtx)) = 1;
6844     }
6845
6846   /* If generating o32/o64 abicalls, save $gp on the stack.  */
6847   if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6848     emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6849
6850   mips_emit_loadgp ();
6851
6852   /* If we are profiling, make sure no instructions are scheduled before
6853      the call to mcount.  */
6854
6855   if (current_function_profile)
6856     emit_insn (gen_blockage ());
6857 }
6858 \f
6859 /* Do any necessary cleanup after a function to restore stack, frame,
6860    and regs.  */
6861
6862 #define RA_MASK BITMASK_HIGH    /* 1 << 31 */
6863
6864 static void
6865 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6866                                HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6867 {
6868   rtx string;
6869
6870   /* Reinstate the normal $gp.  */
6871   REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6872   mips_output_cplocal ();
6873
6874   if (cfun->machine->all_noreorder_p)
6875     {
6876       /* Avoid using %>%) since it adds excess whitespace.  */
6877       output_asm_insn (".set\tmacro", 0);
6878       output_asm_insn (".set\treorder", 0);
6879       set_noreorder = set_nomacro = 0;
6880     }
6881
6882   if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6883     {
6884       const char *fnname;
6885
6886       /* Get the function name the same way that toplev.c does before calling
6887          assemble_start_function.  This is needed so that the name used here
6888          exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
6889       fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6890       fputs ("\t.end\t", file);
6891       assemble_name (file, fnname);
6892       fputs ("\n", file);
6893     }
6894
6895   while (string_constants != NULL)
6896     {
6897       struct string_constant *next;
6898
6899       next = string_constants->next;
6900       free (string_constants);
6901       string_constants = next;
6902     }
6903
6904   /* If any following function uses the same strings as this one, force
6905      them to refer those strings indirectly.  Nearby functions could
6906      refer them using pc-relative addressing, but it isn't safe in
6907      general.  For instance, some functions may be placed in sections
6908      other than .text, and we don't know whether they be close enough
6909      to this one.  In large files, even other .text functions can be
6910      too far away.  */
6911   for (string = mips16_strings; string != 0; string = XEXP (string, 1))
6912     SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
6913   free_EXPR_LIST_list (&mips16_strings);
6914 }
6915 \f
6916 /* Emit instructions to restore register REG from slot MEM.  */
6917
6918 static void
6919 mips_restore_reg (rtx reg, rtx mem)
6920 {
6921   /* There's no mips16 instruction to load $31 directly.  Load into
6922      $7 instead and adjust the return insn appropriately.  */
6923   if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6924     reg = gen_rtx_REG (GET_MODE (reg), 7);
6925
6926   if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6927     {
6928       /* Can't restore directly; move through a temporary.  */
6929       emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6930       emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6931     }
6932   else
6933     emit_move_insn (reg, mem);
6934 }
6935
6936
6937 /* Expand the epilogue into a bunch of separate insns.  SIBCALL_P is true
6938    if this epilogue precedes a sibling call, false if it is for a normal
6939    "epilogue" pattern.  */
6940
6941 void
6942 mips_expand_epilogue (int sibcall_p)
6943 {
6944   HOST_WIDE_INT step1, step2;
6945   rtx base, target;
6946
6947   if (!sibcall_p && mips_can_use_return_insn ())
6948     {
6949       emit_jump_insn (gen_return ());
6950       return;
6951     }
6952
6953   /* Split the frame into two.  STEP1 is the amount of stack we should
6954      deallocate before restoring the registers.  STEP2 is the amount we
6955      should deallocate afterwards.
6956
6957      Start off by assuming that no registers need to be restored.  */
6958   step1 = cfun->machine->frame.total_size;
6959   step2 = 0;
6960
6961   /* Work out which register holds the frame address.  Account for the
6962      frame pointer offset used by mips16 code.  */
6963   if (!frame_pointer_needed)
6964     base = stack_pointer_rtx;
6965   else
6966     {
6967       base = hard_frame_pointer_rtx;
6968       if (TARGET_MIPS16)
6969         step1 -= cfun->machine->frame.args_size;
6970     }
6971
6972   /* If we need to restore registers, deallocate as much stack as
6973      possible in the second step without going out of range.  */
6974   if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6975     {
6976       step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6977       step1 -= step2;
6978     }
6979
6980   /* Set TARGET to BASE + STEP1.  */
6981   target = base;
6982   if (step1 > 0)
6983     {
6984       rtx adjust;
6985
6986       /* Get an rtx for STEP1 that we can add to BASE.  */
6987       adjust = GEN_INT (step1);
6988       if (!SMALL_OPERAND (step1))
6989         {
6990           emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6991           adjust = MIPS_EPILOGUE_TEMP (Pmode);
6992         }
6993
6994       /* Normal mode code can copy the result straight into $sp.  */
6995       if (!TARGET_MIPS16)
6996         target = stack_pointer_rtx;
6997
6998       emit_insn (gen_add3_insn (target, base, adjust));
6999     }
7000
7001   /* Copy TARGET into the stack pointer.  */
7002   if (target != stack_pointer_rtx)
7003     emit_move_insn (stack_pointer_rtx, target);
7004
7005   /* If we're using addressing macros for n32/n64 abicalls, $gp is
7006      implicitly used by all SYMBOL_REFs.  We must emit a blockage
7007      insn before restoring it.  */
7008   if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7009     emit_insn (gen_blockage ());
7010
7011   /* Restore the registers.  */
7012   mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7013                            mips_restore_reg);
7014
7015   /* Deallocate the final bit of the frame.  */
7016   if (step2 > 0)
7017     emit_insn (gen_add3_insn (stack_pointer_rtx,
7018                               stack_pointer_rtx,
7019                               GEN_INT (step2)));
7020
7021   /* Add in the __builtin_eh_return stack adjustment.   We need to
7022      use a temporary in mips16 code.  */
7023   if (current_function_calls_eh_return)
7024     {
7025       if (TARGET_MIPS16)
7026         {
7027           emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7028           emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7029                                     MIPS_EPILOGUE_TEMP (Pmode),
7030                                     EH_RETURN_STACKADJ_RTX));
7031           emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7032         }
7033       else
7034         emit_insn (gen_add3_insn (stack_pointer_rtx,
7035                                   stack_pointer_rtx,
7036                                   EH_RETURN_STACKADJ_RTX));
7037     }
7038
7039   if (!sibcall_p)
7040     {
7041       /* The mips16 loads the return address into $7, not $31.  */
7042       if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7043         emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7044                                                           GP_REG_FIRST + 7)));
7045       else
7046         emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7047                                                           GP_REG_FIRST + 31)));
7048     }
7049 }
7050 \f
7051 /* Return nonzero if this function is known to have a null epilogue.
7052    This allows the optimizer to omit jumps to jumps if no stack
7053    was created.  */
7054
7055 int
7056 mips_can_use_return_insn (void)
7057 {
7058   tree return_type;
7059
7060   if (! reload_completed)
7061     return 0;
7062
7063   if (regs_ever_live[31] || current_function_profile)
7064     return 0;
7065
7066   return_type = DECL_RESULT (current_function_decl);
7067
7068   /* In mips16 mode, a function which returns a floating point value
7069      needs to arrange to copy the return value into the floating point
7070      registers.  */
7071   if (TARGET_MIPS16
7072       && mips16_hard_float
7073       && ! aggregate_value_p (return_type, current_function_decl)
7074       && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7075       && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7076     return 0;
7077
7078   if (cfun->machine->frame.initialized)
7079     return cfun->machine->frame.total_size == 0;
7080
7081   return compute_frame_size (get_frame_size ()) == 0;
7082 }
7083 \f
7084 /* Implement TARGET_ASM_OUTPUT_MI_THUNK.  Generate rtl rather than asm text
7085    in order to avoid duplicating too much logic from elsewhere.  */
7086
7087 static void
7088 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7089                       HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7090                       tree function)
7091 {
7092   rtx this, temp1, temp2, insn, fnaddr;
7093
7094   /* Pretend to be a post-reload pass while generating rtl.  */
7095   no_new_pseudos = 1;
7096   reload_completed = 1;
7097
7098   /* Pick a global pointer for -mabicalls.  Use $15 rather than $28
7099      for TARGET_NEWABI since the latter is a call-saved register.  */
7100   if (TARGET_ABICALLS)
7101     cfun->machine->global_pointer
7102       = REGNO (pic_offset_table_rtx)
7103       = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7104
7105   /* Set up the global pointer for n32 or n64 abicalls.  */
7106   mips_emit_loadgp ();
7107
7108   /* We need two temporary registers in some cases.  */
7109   temp1 = gen_rtx_REG (Pmode, 2);
7110   temp2 = gen_rtx_REG (Pmode, 3);
7111
7112   /* Find out which register contains the "this" pointer.  */
7113   if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7114     this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7115   else
7116     this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7117
7118   /* Add DELTA to THIS.  */
7119   if (delta != 0)
7120     {
7121       rtx offset = GEN_INT (delta);
7122       if (!SMALL_OPERAND (delta))
7123         {
7124           emit_move_insn (temp1, offset);
7125           offset = temp1;
7126         }
7127       emit_insn (gen_add3_insn (this, this, offset));
7128     }
7129
7130   /* If needed, add *(*THIS + VCALL_OFFSET) to THIS.  */
7131   if (vcall_offset != 0)
7132     {
7133       rtx addr;
7134
7135       /* Set TEMP1 to *THIS.  */
7136       emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7137
7138       /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET.  */
7139       if (SMALL_OPERAND (vcall_offset))
7140         addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
7141       else if (TARGET_MIPS16)
7142         {
7143           /* Load the full offset into a register so that we can use
7144              an unextended instruction for the load itself.  */
7145           emit_move_insn (temp2, GEN_INT (vcall_offset));
7146           emit_insn (gen_add3_insn (temp1, temp1, temp2));
7147           addr = temp1;
7148         }
7149       else
7150         {
7151           /* Load the high part of the offset into a register and
7152              leave the low part for the address.  */
7153           emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
7154           emit_insn (gen_add3_insn (temp1, temp1, temp2));
7155           addr = gen_rtx_PLUS (Pmode, temp1,
7156                                GEN_INT (CONST_LOW_PART (vcall_offset)));
7157         }
7158
7159       /* Load the offset and add it to THIS.  */
7160       emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7161       emit_insn (gen_add3_insn (this, this, temp1));
7162     }
7163
7164   /* Jump to the target function.  Use a sibcall if direct jumps are
7165      allowed, otherwise load the address into a register first.  */
7166   fnaddr = XEXP (DECL_RTL (function), 0);
7167   if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7168     {
7169       /* This is messy.  gas treats "la $25,foo" as part of a call
7170          sequence and may allow a global "foo" to be lazily bound.
7171          The general move patterns therefore reject this combination.
7172
7173          In this context, lazy binding would actually be OK for o32 and o64,
7174          but it's still wrong for n32 and n64; see mips_load_call_address.
7175          We must therefore load the address via a temporary register if
7176          mips_dangerous_for_la25_p.
7177
7178          If we jump to the temporary register rather than $25, the assembler
7179          can use the move insn to fill the jump's delay slot.  */
7180       if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7181         temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7182       mips_load_call_address (temp1, fnaddr, true);
7183
7184       if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7185         emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7186       emit_jump_insn (gen_indirect_jump (temp1));
7187     }
7188   else
7189     {
7190       insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7191       SIBLING_CALL_P (insn) = 1;
7192     }
7193
7194   /* Run just enough of rest_of_compilation.  This sequence was
7195      "borrowed" from alpha.c.  */
7196   insn = get_insns ();
7197   insn_locators_initialize ();
7198   split_all_insns_noflow ();
7199   shorten_branches (insn);
7200   final_start_function (insn, file, 1);
7201   final (insn, file, 1, 0);
7202   final_end_function ();
7203
7204   /* Clean up the vars set above.  Note that final_end_function resets
7205      the global pointer for us.  */
7206   reload_completed = 0;
7207   no_new_pseudos = 0;
7208 }
7209 \f
7210 /* Returns nonzero if X contains a SYMBOL_REF.  */
7211
7212 static int
7213 symbolic_expression_p (rtx x)
7214 {
7215   if (GET_CODE (x) == SYMBOL_REF)
7216     return 1;
7217
7218   if (GET_CODE (x) == CONST)
7219     return symbolic_expression_p (XEXP (x, 0));
7220
7221   if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7222     return symbolic_expression_p (XEXP (x, 0));
7223
7224   if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7225       || GET_RTX_CLASS (GET_CODE (x)) == '2')
7226     return (symbolic_expression_p (XEXP (x, 0))
7227             || symbolic_expression_p (XEXP (x, 1)));
7228
7229   return 0;
7230 }
7231
7232 /* Choose the section to use for the constant rtx expression X that has
7233    mode MODE.  */
7234
7235 static void
7236 mips_select_rtx_section (enum machine_mode mode, rtx x,
7237                          unsigned HOST_WIDE_INT align)
7238 {
7239   if (TARGET_MIPS16)
7240     {
7241       /* In mips16 mode, the constant table always goes in the same section
7242          as the function, so that constants can be loaded using PC relative
7243          addressing.  */
7244       function_section (current_function_decl);
7245     }
7246   else if (TARGET_EMBEDDED_DATA)
7247     {
7248       /* For embedded applications, always put constants in read-only data,
7249          in order to reduce RAM usage.  */
7250       mergeable_constant_section (mode, align, 0);
7251     }
7252   else
7253     {
7254       /* For hosted applications, always put constants in small data if
7255          possible, as this gives the best performance.  */
7256       /* ??? Consider using mergeable small data sections.  */
7257
7258       if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7259           && mips_section_threshold > 0)
7260         named_section (0, ".sdata", 0);
7261       else if (flag_pic && symbolic_expression_p (x))
7262         {
7263           if (targetm.have_named_sections)
7264             named_section (0, ".data.rel.ro", 3);
7265           else
7266             data_section ();
7267         }
7268       else
7269         mergeable_constant_section (mode, align, 0);
7270     }
7271 }
7272
7273 /* Choose the section to use for DECL.  RELOC is true if its value contains
7274    any relocatable expression.  */
7275
7276 static void
7277 mips_select_section (tree decl, int reloc,
7278                      unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7279 {
7280   if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7281       && TREE_CODE (decl) == STRING_CST
7282       && !flag_writable_strings)
7283     /* For embedded position independent code, put constant strings in the
7284        text section, because the data section is limited to 64K in size.
7285        For mips16 code, put strings in the text section so that a PC
7286        relative load instruction can be used to get their address.  */
7287     text_section ();
7288   else if (targetm.have_named_sections)
7289     default_elf_select_section (decl, reloc, align);
7290   else
7291     /* The native irix o32 assembler doesn't support named sections.  */
7292     default_select_section (decl, reloc, align);
7293 }
7294
7295
7296 /* Implement TARGET_IN_SMALL_DATA_P.  Return true if it would be safe to
7297    access DECL using %gp_rel(...)($gp).  */
7298
7299 static bool
7300 mips_in_small_data_p (tree decl)
7301 {
7302   HOST_WIDE_INT size;
7303
7304   if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7305     return false;
7306
7307   if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7308     {
7309       const char *name;
7310
7311       /* Reject anything that isn't in a known small-data section.  */
7312       name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7313       if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7314         return false;
7315
7316       /* If a symbol is defined externally, the assembler will use the
7317          usual -G rules when deciding how to implement macros.  */
7318       if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7319         return true;
7320     }
7321   else if (TARGET_EMBEDDED_DATA)
7322     {
7323       /* Don't put constants into the small data section: we want them
7324          to be in ROM rather than RAM.  */
7325       if (TREE_CODE (decl) != VAR_DECL)
7326         return false;
7327
7328       if (TREE_READONLY (decl)
7329           && !TREE_SIDE_EFFECTS (decl)
7330           && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7331         return false;
7332     }
7333
7334   size = int_size_in_bytes (TREE_TYPE (decl));
7335   return (size > 0 && size <= mips_section_threshold);
7336 }
7337
7338
7339 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7340    symbols which are not in the .text section.
7341
7342    When generating mips16 code, SYMBOL_REF_FLAG is set for string
7343    constants which are put in the .text section.  We also record the
7344    total length of all such strings; this total is used to decide
7345    whether we need to split the constant table, and need not be
7346    precisely correct.  */
7347
7348 static void
7349 mips_encode_section_info (tree decl, rtx rtl, int first)
7350 {
7351   rtx symbol;
7352
7353   if (GET_CODE (rtl) != MEM)
7354     return;
7355
7356   symbol = XEXP (rtl, 0);
7357
7358   if (GET_CODE (symbol) != SYMBOL_REF)
7359     return;
7360
7361   if (TARGET_MIPS16)
7362     {
7363       if (first && TREE_CODE (decl) == STRING_CST
7364           && ! flag_writable_strings
7365           /* If this string is from a function, and the function will
7366              go in a gnu linkonce section, then we can't directly
7367              access the string.  This gets an assembler error
7368              "unsupported PC relative reference to different section".
7369              If we modify SELECT_SECTION to put it in function_section
7370              instead of text_section, it still fails because
7371              DECL_SECTION_NAME isn't set until assemble_start_function.
7372              If we fix that, it still fails because strings are shared
7373              among multiple functions, and we have cross section
7374              references again.  We force it to work by putting string
7375              addresses in the constant pool and indirecting.  */
7376           && (! current_function_decl
7377               || ! DECL_ONE_ONLY (current_function_decl)))
7378         {
7379           mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
7380           SYMBOL_REF_FLAG (symbol) = 1;
7381           mips_string_length += TREE_STRING_LENGTH (decl);
7382         }
7383     }
7384
7385   if (TARGET_EMBEDDED_PIC)
7386     {
7387       if (TREE_CODE (decl) == VAR_DECL)
7388         SYMBOL_REF_FLAG (symbol) = 1;
7389       else if (TREE_CODE (decl) == FUNCTION_DECL)
7390         SYMBOL_REF_FLAG (symbol) = 0;
7391       else if (TREE_CODE (decl) == STRING_CST
7392                && ! flag_writable_strings)
7393         SYMBOL_REF_FLAG (symbol) = 0;
7394       else
7395         SYMBOL_REF_FLAG (symbol) = 1;
7396     }
7397
7398   default_encode_section_info (decl, rtl, first);
7399 }
7400 \f
7401 /* See whether VALTYPE is a record whose fields should be returned in
7402    floating-point registers.  If so, return the number of fields and
7403    list them in FIELDS (which should have two elements).  Return 0
7404    otherwise.
7405
7406    For n32 & n64, a structure with one or two fields is returned in
7407    floating-point registers as long as every field has a floating-point
7408    type.  */
7409
7410 static int
7411 mips_fpr_return_fields (tree valtype, tree *fields)
7412 {
7413   tree field;
7414   int i;
7415
7416   if (!TARGET_NEWABI)
7417     return 0;
7418
7419   if (TREE_CODE (valtype) != RECORD_TYPE)
7420     return 0;
7421
7422   i = 0;
7423   for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7424     {
7425       if (TREE_CODE (field) != FIELD_DECL)
7426         continue;
7427
7428       if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7429         return 0;
7430
7431       if (i == 2)
7432         return 0;
7433
7434       fields[i++] = field;
7435     }
7436   return i;
7437 }
7438
7439
7440 /* Implement TARGET_RETURN_IN_MSB.  For n32 & n64, we should return
7441    a value in the most significant part of $2/$3 if:
7442
7443       - the target is big-endian;
7444
7445       - the value has a structure or union type (we generalize this to
7446         cover aggregates from other languages too); and
7447
7448       - the structure is not returned in floating-point registers.  */
7449
7450 static bool
7451 mips_return_in_msb (tree valtype)
7452 {
7453   tree fields[2];
7454
7455   return (TARGET_NEWABI
7456           && TARGET_BIG_ENDIAN
7457           && AGGREGATE_TYPE_P (valtype)
7458           && mips_fpr_return_fields (valtype, fields) == 0);
7459 }
7460
7461
7462 /* Return a composite value in a pair of floating-point registers.
7463    MODE1 and OFFSET1 are the mode and byte offset for the first value,
7464    likewise MODE2 and OFFSET2 for the second.  MODE is the mode of the
7465    complete value.
7466
7467    For n32 & n64, $f0 always holds the first value and $f2 the second.
7468    Otherwise the values are packed together as closely as possible.  */
7469
7470 static rtx
7471 mips_return_fpr_pair (enum machine_mode mode,
7472                       enum machine_mode mode1, HOST_WIDE_INT offset1,
7473                       enum machine_mode mode2, HOST_WIDE_INT offset2)
7474 {
7475   int inc;
7476
7477   inc = (TARGET_NEWABI ? 2 : FP_INC);
7478   return gen_rtx_PARALLEL
7479     (mode,
7480      gen_rtvec (2,
7481                 gen_rtx_EXPR_LIST (VOIDmode,
7482                                    gen_rtx_REG (mode1, FP_RETURN),
7483                                    GEN_INT (offset1)),
7484                 gen_rtx_EXPR_LIST (VOIDmode,
7485                                    gen_rtx_REG (mode2, FP_RETURN + inc),
7486                                    GEN_INT (offset2))));
7487
7488 }
7489
7490
7491 /* Implement FUNCTION_VALUE and LIBCALL_VALUE.  For normal calls,
7492    VALTYPE is the return type and MODE is VOIDmode.  For libcalls,
7493    VALTYPE is null and MODE is the mode of the return value.  */
7494
7495 rtx
7496 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7497                      enum machine_mode mode)
7498 {
7499   if (valtype)
7500     {
7501       tree fields[2];
7502       int unsignedp;
7503
7504       mode = TYPE_MODE (valtype);
7505       unsignedp = TREE_UNSIGNED (valtype);
7506
7507       /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7508          true, we must promote the mode just as PROMOTE_MODE does.  */
7509       mode = promote_mode (valtype, mode, &unsignedp, 1);
7510
7511       /* Handle structures whose fields are returned in $f0/$f2.  */
7512       switch (mips_fpr_return_fields (valtype, fields))
7513         {
7514         case 1:
7515           return gen_rtx_REG (mode, FP_RETURN);
7516
7517         case 2:
7518           return mips_return_fpr_pair (mode,
7519                                        TYPE_MODE (TREE_TYPE (fields[0])),
7520                                        int_byte_position (fields[0]),
7521                                        TYPE_MODE (TREE_TYPE (fields[1])),
7522                                        int_byte_position (fields[1]));
7523         }
7524
7525       /* If a value is passed in the most significant part of a register, see
7526          whether we have to round the mode up to a whole number of words.  */
7527       if (mips_return_in_msb (valtype))
7528         {
7529           HOST_WIDE_INT size = int_size_in_bytes (valtype);
7530           if (size % UNITS_PER_WORD != 0)
7531             {
7532               size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7533               mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7534             }
7535         }
7536     }
7537
7538   if (GET_MODE_CLASS (mode) == MODE_FLOAT
7539       && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7540     return gen_rtx_REG (mode, FP_RETURN);
7541
7542   /* Handle long doubles for n32 & n64.  */
7543   if (mode == TFmode)
7544     return mips_return_fpr_pair (mode,
7545                                  DImode, 0,
7546                                  DImode, GET_MODE_SIZE (mode) / 2);
7547
7548   if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7549       && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7550     return mips_return_fpr_pair (mode,
7551                                  GET_MODE_INNER (mode), 0,
7552                                  GET_MODE_INNER (mode),
7553                                  GET_MODE_SIZE (mode) / 2);
7554
7555   return gen_rtx_REG (mode, GP_RETURN);
7556 }
7557
7558 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE.  Return
7559    nonzero when an argument must be passed by reference.  */
7560
7561 int
7562 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7563                                 enum machine_mode mode, tree type,
7564                                 int named ATTRIBUTE_UNUSED)
7565 {
7566   int size;
7567
7568   /* The EABI is the only one to pass args by reference.  */
7569   if (mips_abi != ABI_EABI)
7570     return 0;
7571
7572   /* ??? How should SCmode be handled?  */
7573   if (type == NULL_TREE || mode == DImode || mode == DFmode)
7574     return 0;
7575
7576   size = int_size_in_bytes (type);
7577   return size == -1 || size > UNITS_PER_WORD;
7578 }
7579
7580 /* Return the class of registers for which a mode change from FROM to TO
7581    is invalid.
7582
7583    In little-endian mode, the hi-lo registers are numbered backwards,
7584    so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7585    word as intended.
7586
7587    Similarly, when using paired floating-point registers, the first
7588    register holds the low word, regardless of endianness.  So in big
7589    endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7590    as intended.
7591
7592    Also, loading a 32-bit value into a 64-bit floating-point register
7593    will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7594    We can't allow 64-bit float registers to change from a 32-bit
7595    mode to a 64-bit mode.  */
7596
7597 bool
7598 mips_cannot_change_mode_class (enum machine_mode from,
7599                                enum machine_mode to, enum reg_class class)
7600 {
7601   if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7602     {
7603       if (TARGET_BIG_ENDIAN)
7604         return reg_classes_intersect_p (FP_REGS, class);
7605       if (TARGET_FLOAT64)
7606         return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7607       return reg_classes_intersect_p (HI_REG, class);
7608     }
7609   return false;
7610 }
7611
7612 /* Return true if X should not be moved directly into register $25.
7613    We need this because many versions of GAS will treat "la $25,foo" as
7614    part of a call sequence and so allow a global "foo" to be lazily bound.  */
7615
7616 bool
7617 mips_dangerous_for_la25_p (rtx x)
7618 {
7619   HOST_WIDE_INT offset;
7620
7621   if (TARGET_EXPLICIT_RELOCS)
7622     return false;
7623
7624   mips_split_const (x, &x, &offset);
7625   return global_got_operand (x, VOIDmode);
7626 }
7627
7628 /* Implement PREFERRED_RELOAD_CLASS.  */
7629
7630 enum reg_class
7631 mips_preferred_reload_class (rtx x, enum reg_class class)
7632 {
7633   if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7634     return LEA_REGS;
7635
7636   if (TARGET_HARD_FLOAT
7637       && FLOAT_MODE_P (GET_MODE (x))
7638       && reg_class_subset_p (FP_REGS, class))
7639     return FP_REGS;
7640
7641   if (reg_class_subset_p (GR_REGS, class))
7642     class = GR_REGS;
7643
7644   if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7645     class = M16_REGS;
7646
7647   return class;
7648 }
7649
7650 /* This function returns the register class required for a secondary
7651    register when copying between one of the registers in CLASS, and X,
7652    using MODE.  If IN_P is nonzero, the copy is going from X to the
7653    register, otherwise the register is the source.  A return value of
7654    NO_REGS means that no secondary register is required.  */
7655
7656 enum reg_class
7657 mips_secondary_reload_class (enum reg_class class,
7658                              enum machine_mode mode, rtx x, int in_p)
7659 {
7660   enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7661   int regno = -1;
7662   int gp_reg_p;
7663
7664   if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7665     regno = true_regnum (x);
7666
7667   gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7668
7669   if (mips_dangerous_for_la25_p (x))
7670     {
7671       gr_regs = LEA_REGS;
7672       if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7673         return gr_regs;
7674     }
7675
7676   /* Copying from HI or LO to anywhere other than a general register
7677      requires a general register.  */
7678   if (class == HI_REG || class == LO_REG || class == MD_REGS)
7679     {
7680       if (TARGET_MIPS16 && in_p)
7681         {
7682           /* We can't really copy to HI or LO at all in mips16 mode.  */
7683           return M16_REGS;
7684         }
7685       return gp_reg_p ? NO_REGS : gr_regs;
7686     }
7687   if (MD_REG_P (regno))
7688     {
7689       if (TARGET_MIPS16 && ! in_p)
7690         {
7691           /* We can't really copy to HI or LO at all in mips16 mode.  */
7692           return M16_REGS;
7693         }
7694       return class == gr_regs ? NO_REGS : gr_regs;
7695     }
7696
7697   /* We can only copy a value to a condition code register from a
7698      floating point register, and even then we require a scratch
7699      floating point register.  We can only copy a value out of a
7700      condition code register into a general register.  */
7701   if (class == ST_REGS)
7702     {
7703       if (in_p)
7704         return FP_REGS;
7705       return gp_reg_p ? NO_REGS : gr_regs;
7706     }
7707   if (ST_REG_P (regno))
7708     {
7709       if (! in_p)
7710         return FP_REGS;
7711       return class == gr_regs ? NO_REGS : gr_regs;
7712     }
7713
7714   if (class == FP_REGS)
7715     {
7716       if (GET_CODE (x) == MEM)
7717         {
7718           /* In this case we can use lwc1, swc1, ldc1 or sdc1.  */
7719           return NO_REGS;
7720         }
7721       else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7722         {
7723           /* We can use the l.s and l.d macros to load floating-point
7724              constants.  ??? For l.s, we could probably get better
7725              code by returning GR_REGS here.  */
7726           return NO_REGS;
7727         }
7728       else if (gp_reg_p || x == CONST0_RTX (mode))
7729         {
7730           /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1.  */
7731           return NO_REGS;
7732         }
7733       else if (FP_REG_P (regno))
7734         {
7735           /* In this case we can use mov.s or mov.d.  */
7736           return NO_REGS;
7737         }
7738       else
7739         {
7740           /* Otherwise, we need to reload through an integer register.  */
7741           return gr_regs;
7742         }
7743     }
7744
7745   /* In mips16 mode, going between memory and anything but M16_REGS
7746      requires an M16_REG.  */
7747   if (TARGET_MIPS16)
7748     {
7749       if (class != M16_REGS && class != M16_NA_REGS)
7750         {
7751           if (gp_reg_p)
7752             return NO_REGS;
7753           return M16_REGS;
7754         }
7755       if (! gp_reg_p)
7756         {
7757           if (class == M16_REGS || class == M16_NA_REGS)
7758             return NO_REGS;
7759           return M16_REGS;
7760         }
7761     }
7762
7763   return NO_REGS;
7764 }
7765
7766 /* Implement CLASS_MAX_NREGS.
7767
7768    Usually all registers are word-sized.  The only supported exception
7769    is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7770    registers.  A word-based calculation is correct even in that case,
7771    since -msingle-float disallows multi-FPR values.  */
7772
7773 int
7774 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7775                       enum machine_mode mode)
7776 {
7777   return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7778 }
7779
7780 bool
7781 mips_valid_pointer_mode (enum machine_mode mode)
7782 {
7783   return (mode == SImode || (TARGET_64BIT && mode == DImode));
7784 }
7785
7786 \f
7787 /* If we can access small data directly (using gp-relative relocation
7788    operators) return the small data pointer, otherwise return null.
7789
7790    For each mips16 function which refers to GP relative symbols, we
7791    use a pseudo register, initialized at the start of the function, to
7792    hold the $gp value.  */
7793
7794 static rtx
7795 mips16_gp_pseudo_reg (void)
7796 {
7797   if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7798     {
7799       rtx const_gp;
7800       rtx insn, scan;
7801
7802       cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7803       RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7804
7805       /* We want to initialize this to a value which gcc will believe
7806          is constant.  */
7807       const_gp = gen_rtx_CONST (Pmode, pic_offset_table_rtx);
7808       start_sequence ();
7809       emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7810                       const_gp);
7811       insn = get_insns ();
7812       end_sequence ();
7813
7814       push_topmost_sequence ();
7815       /* We need to emit the initialization after the FUNCTION_BEG
7816          note, so that it will be integrated.  */
7817       for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7818         if (GET_CODE (scan) == NOTE
7819             && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7820           break;
7821       if (scan == NULL_RTX)
7822         scan = get_insns ();
7823       insn = emit_insn_after (insn, scan);
7824       pop_topmost_sequence ();
7825     }
7826
7827   return cfun->machine->mips16_gp_pseudo_rtx;
7828 }
7829
7830 /* Write out code to move floating point arguments in or out of
7831    general registers.  Output the instructions to FILE.  FP_CODE is
7832    the code describing which arguments are present (see the comment at
7833    the definition of CUMULATIVE_ARGS in mips.h).  FROM_FP_P is nonzero if
7834    we are copying from the floating point registers.  */
7835
7836 static void
7837 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7838 {
7839   const char *s;
7840   int gparg, fparg;
7841   unsigned int f;
7842
7843   /* This code only works for the original 32 bit ABI and the O64 ABI.  */
7844   if (!TARGET_OLDABI)
7845     abort ();
7846
7847   if (from_fp_p)
7848     s = "mfc1";
7849   else
7850     s = "mtc1";
7851   gparg = GP_ARG_FIRST;
7852   fparg = FP_ARG_FIRST;
7853   for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7854     {
7855       if ((f & 3) == 1)
7856         {
7857           if ((fparg & 1) != 0)
7858             ++fparg;
7859           fprintf (file, "\t%s\t%s,%s\n", s,
7860                    reg_names[gparg], reg_names[fparg]);
7861         }
7862       else if ((f & 3) == 2)
7863         {
7864           if (TARGET_64BIT)
7865             fprintf (file, "\td%s\t%s,%s\n", s,
7866                      reg_names[gparg], reg_names[fparg]);
7867           else
7868             {
7869               if ((fparg & 1) != 0)
7870                 ++fparg;
7871               if (TARGET_BIG_ENDIAN)
7872                 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7873                          reg_names[gparg], reg_names[fparg + 1], s,
7874                          reg_names[gparg + 1], reg_names[fparg]);
7875               else
7876                 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7877                          reg_names[gparg], reg_names[fparg], s,
7878                          reg_names[gparg + 1], reg_names[fparg + 1]);
7879               ++gparg;
7880               ++fparg;
7881             }
7882         }
7883       else
7884         abort ();
7885
7886       ++gparg;
7887       ++fparg;
7888     }
7889 }
7890
7891 /* Build a mips16 function stub.  This is used for functions which
7892    take arguments in the floating point registers.  It is 32 bit code
7893    that moves the floating point args into the general registers, and
7894    then jumps to the 16 bit code.  */
7895
7896 static void
7897 build_mips16_function_stub (FILE *file)
7898 {
7899   const char *fnname;
7900   char *secname, *stubname;
7901   tree stubid, stubdecl;
7902   int need_comma;
7903   unsigned int f;
7904
7905   fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7906   secname = (char *) alloca (strlen (fnname) + 20);
7907   sprintf (secname, ".mips16.fn.%s", fnname);
7908   stubname = (char *) alloca (strlen (fnname) + 20);
7909   sprintf (stubname, "__fn_stub_%s", fnname);
7910   stubid = get_identifier (stubname);
7911   stubdecl = build_decl (FUNCTION_DECL, stubid,
7912                          build_function_type (void_type_node, NULL_TREE));
7913   DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7914
7915   fprintf (file, "\t# Stub function for %s (", current_function_name ());
7916   need_comma = 0;
7917   for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7918     {
7919       fprintf (file, "%s%s",
7920                need_comma ? ", " : "",
7921                (f & 3) == 1 ? "float" : "double");
7922       need_comma = 1;
7923     }
7924   fprintf (file, ")\n");
7925
7926   fprintf (file, "\t.set\tnomips16\n");
7927   function_section (stubdecl);
7928   ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7929
7930   /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7931      within a .ent, and we can not emit another .ent.  */
7932   if (!FUNCTION_NAME_ALREADY_DECLARED)
7933     {
7934       fputs ("\t.ent\t", file);
7935       assemble_name (file, stubname);
7936       fputs ("\n", file);
7937     }
7938
7939   assemble_name (file, stubname);
7940   fputs (":\n", file);
7941
7942   /* We don't want the assembler to insert any nops here.  */
7943   fprintf (file, "\t.set\tnoreorder\n");
7944
7945   mips16_fp_args (file, current_function_args_info.fp_code, 1);
7946
7947   fprintf (asm_out_file, "\t.set\tnoat\n");
7948   fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7949   assemble_name (file, fnname);
7950   fprintf (file, "\n");
7951   fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7952   fprintf (asm_out_file, "\t.set\tat\n");
7953
7954   /* Unfortunately, we can't fill the jump delay slot.  We can't fill
7955      with one of the mfc1 instructions, because the result is not
7956      available for one instruction, so if the very first instruction
7957      in the function refers to the register, it will see the wrong
7958      value.  */
7959   fprintf (file, "\tnop\n");
7960
7961   fprintf (file, "\t.set\treorder\n");
7962
7963   if (!FUNCTION_NAME_ALREADY_DECLARED)
7964     {
7965       fputs ("\t.end\t", file);
7966       assemble_name (file, stubname);
7967       fputs ("\n", file);
7968     }
7969
7970   fprintf (file, "\t.set\tmips16\n");
7971
7972   function_section (current_function_decl);
7973 }
7974
7975 /* We keep a list of functions for which we have already built stubs
7976    in build_mips16_call_stub.  */
7977
7978 struct mips16_stub
7979 {
7980   struct mips16_stub *next;
7981   char *name;
7982   int fpret;
7983 };
7984
7985 static struct mips16_stub *mips16_stubs;
7986
7987 /* Build a call stub for a mips16 call.  A stub is needed if we are
7988    passing any floating point values which should go into the floating
7989    point registers.  If we are, and the call turns out to be to a 32
7990    bit function, the stub will be used to move the values into the
7991    floating point registers before calling the 32 bit function.  The
7992    linker will magically adjust the function call to either the 16 bit
7993    function or the 32 bit stub, depending upon where the function call
7994    is actually defined.
7995
7996    Similarly, we need a stub if the return value might come back in a
7997    floating point register.
7998
7999    RETVAL is the location of the return value, or null if this is
8000    a call rather than a call_value.  FN is the address of the
8001    function and ARG_SIZE is the size of the arguments.  FP_CODE
8002    is the code built by function_arg.  This function returns a nonzero
8003    value if it builds the call instruction itself.  */
8004
8005 int
8006 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8007 {
8008   int fpret;
8009   const char *fnname;
8010   char *secname, *stubname;
8011   struct mips16_stub *l;
8012   tree stubid, stubdecl;
8013   int need_comma;
8014   unsigned int f;
8015
8016   /* We don't need to do anything if we aren't in mips16 mode, or if
8017      we were invoked with the -msoft-float option.  */
8018   if (! TARGET_MIPS16 || ! mips16_hard_float)
8019     return 0;
8020
8021   /* Figure out whether the value might come back in a floating point
8022      register.  */
8023   fpret = (retval != 0
8024            && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8025            && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8026
8027   /* We don't need to do anything if there were no floating point
8028      arguments and the value will not be returned in a floating point
8029      register.  */
8030   if (fp_code == 0 && ! fpret)
8031     return 0;
8032
8033   /* We don't need to do anything if this is a call to a special
8034      mips16 support function.  */
8035   if (GET_CODE (fn) == SYMBOL_REF
8036       && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8037     return 0;
8038
8039   /* This code will only work for o32 and o64 abis.  The other ABI's
8040      require more sophisticated support.  */
8041   if (!TARGET_OLDABI)
8042     abort ();
8043
8044   /* We can only handle SFmode and DFmode floating point return
8045      values.  */
8046   if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8047     abort ();
8048
8049   /* If we're calling via a function pointer, then we must always call
8050      via a stub.  There are magic stubs provided in libgcc.a for each
8051      of the required cases.  Each of them expects the function address
8052      to arrive in register $2.  */
8053
8054   if (GET_CODE (fn) != SYMBOL_REF)
8055     {
8056       char buf[30];
8057       tree id;
8058       rtx stub_fn, insn;
8059
8060       /* ??? If this code is modified to support other ABI's, we need
8061          to handle PARALLEL return values here.  */
8062
8063       sprintf (buf, "__mips16_call_stub_%s%d",
8064                (fpret
8065                 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8066                 : ""),
8067                fp_code);
8068       id = get_identifier (buf);
8069       stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8070
8071       emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8072
8073       if (retval == NULL_RTX)
8074         insn = gen_call_internal (stub_fn, arg_size);
8075       else
8076         insn = gen_call_value_internal (retval, stub_fn, arg_size);
8077       insn = emit_call_insn (insn);
8078
8079       /* Put the register usage information on the CALL.  */
8080       if (GET_CODE (insn) != CALL_INSN)
8081         abort ();
8082       CALL_INSN_FUNCTION_USAGE (insn) =
8083         gen_rtx_EXPR_LIST (VOIDmode,
8084                            gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8085                            CALL_INSN_FUNCTION_USAGE (insn));
8086
8087       /* If we are handling a floating point return value, we need to
8088          save $18 in the function prologue.  Putting a note on the
8089          call will mean that regs_ever_live[$18] will be true if the
8090          call is not eliminated, and we can check that in the prologue
8091          code.  */
8092       if (fpret)
8093         CALL_INSN_FUNCTION_USAGE (insn) =
8094           gen_rtx_EXPR_LIST (VOIDmode,
8095                              gen_rtx_USE (VOIDmode,
8096                                           gen_rtx_REG (word_mode, 18)),
8097                              CALL_INSN_FUNCTION_USAGE (insn));
8098
8099       /* Return 1 to tell the caller that we've generated the call
8100          insn.  */
8101       return 1;
8102     }
8103
8104   /* We know the function we are going to call.  If we have already
8105      built a stub, we don't need to do anything further.  */
8106
8107   fnname = XSTR (fn, 0);
8108   for (l = mips16_stubs; l != NULL; l = l->next)
8109     if (strcmp (l->name, fnname) == 0)
8110       break;
8111
8112   if (l == NULL)
8113     {
8114       /* Build a special purpose stub.  When the linker sees a
8115          function call in mips16 code, it will check where the target
8116          is defined.  If the target is a 32 bit call, the linker will
8117          search for the section defined here.  It can tell which
8118          symbol this section is associated with by looking at the
8119          relocation information (the name is unreliable, since this
8120          might be a static function).  If such a section is found, the
8121          linker will redirect the call to the start of the magic
8122          section.
8123
8124          If the function does not return a floating point value, the
8125          special stub section is named
8126              .mips16.call.FNNAME
8127
8128          If the function does return a floating point value, the stub
8129          section is named
8130              .mips16.call.fp.FNNAME
8131          */
8132
8133       secname = (char *) alloca (strlen (fnname) + 40);
8134       sprintf (secname, ".mips16.call.%s%s",
8135                fpret ? "fp." : "",
8136                fnname);
8137       stubname = (char *) alloca (strlen (fnname) + 20);
8138       sprintf (stubname, "__call_stub_%s%s",
8139                fpret ? "fp_" : "",
8140                fnname);
8141       stubid = get_identifier (stubname);
8142       stubdecl = build_decl (FUNCTION_DECL, stubid,
8143                              build_function_type (void_type_node, NULL_TREE));
8144       DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8145
8146       fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8147                (fpret
8148                 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8149                 : ""),
8150                fnname);
8151       need_comma = 0;
8152       for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8153         {
8154           fprintf (asm_out_file, "%s%s",
8155                    need_comma ? ", " : "",
8156                    (f & 3) == 1 ? "float" : "double");
8157           need_comma = 1;
8158         }
8159       fprintf (asm_out_file, ")\n");
8160
8161       fprintf (asm_out_file, "\t.set\tnomips16\n");
8162       assemble_start_function (stubdecl, stubname);
8163
8164       if (!FUNCTION_NAME_ALREADY_DECLARED)
8165         {
8166           fputs ("\t.ent\t", asm_out_file);
8167           assemble_name (asm_out_file, stubname);
8168           fputs ("\n", asm_out_file);
8169
8170           assemble_name (asm_out_file, stubname);
8171           fputs (":\n", asm_out_file);
8172         }
8173
8174       /* We build the stub code by hand.  That's the only way we can
8175          do it, since we can't generate 32 bit code during a 16 bit
8176          compilation.  */
8177
8178       /* We don't want the assembler to insert any nops here.  */
8179       fprintf (asm_out_file, "\t.set\tnoreorder\n");
8180
8181       mips16_fp_args (asm_out_file, fp_code, 0);
8182
8183       if (! fpret)
8184         {
8185           fprintf (asm_out_file, "\t.set\tnoat\n");
8186           fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8187                    fnname);
8188           fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8189           fprintf (asm_out_file, "\t.set\tat\n");
8190           /* Unfortunately, we can't fill the jump delay slot.  We
8191              can't fill with one of the mtc1 instructions, because the
8192              result is not available for one instruction, so if the
8193              very first instruction in the function refers to the
8194              register, it will see the wrong value.  */
8195           fprintf (asm_out_file, "\tnop\n");
8196         }
8197       else
8198         {
8199           fprintf (asm_out_file, "\tmove\t%s,%s\n",
8200                    reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8201           fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8202           /* As above, we can't fill the delay slot.  */
8203           fprintf (asm_out_file, "\tnop\n");
8204           if (GET_MODE (retval) == SFmode)
8205             fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8206                      reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8207           else
8208             {
8209               if (TARGET_BIG_ENDIAN)
8210                 {
8211                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8212                            reg_names[GP_REG_FIRST + 2],
8213                            reg_names[FP_REG_FIRST + 1]);
8214                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8215                            reg_names[GP_REG_FIRST + 3],
8216                            reg_names[FP_REG_FIRST + 0]);
8217                 }
8218               else
8219                 {
8220                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8221                            reg_names[GP_REG_FIRST + 2],
8222                            reg_names[FP_REG_FIRST + 0]);
8223                   fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8224                            reg_names[GP_REG_FIRST + 3],
8225                            reg_names[FP_REG_FIRST + 1]);
8226                 }
8227             }
8228           fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8229           /* As above, we can't fill the delay slot.  */
8230           fprintf (asm_out_file, "\tnop\n");
8231         }
8232
8233       fprintf (asm_out_file, "\t.set\treorder\n");
8234
8235 #ifdef ASM_DECLARE_FUNCTION_SIZE
8236       ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8237 #endif
8238
8239       if (!FUNCTION_NAME_ALREADY_DECLARED)
8240         {
8241           fputs ("\t.end\t", asm_out_file);
8242           assemble_name (asm_out_file, stubname);
8243           fputs ("\n", asm_out_file);
8244         }
8245
8246       fprintf (asm_out_file, "\t.set\tmips16\n");
8247
8248       /* Record this stub.  */
8249       l = (struct mips16_stub *) xmalloc (sizeof *l);
8250       l->name = xstrdup (fnname);
8251       l->fpret = fpret;
8252       l->next = mips16_stubs;
8253       mips16_stubs = l;
8254     }
8255
8256   /* If we expect a floating point return value, but we've built a
8257      stub which does not expect one, then we're in trouble.  We can't
8258      use the existing stub, because it won't handle the floating point
8259      value.  We can't build a new stub, because the linker won't know
8260      which stub to use for the various calls in this object file.
8261      Fortunately, this case is illegal, since it means that a function
8262      was declared in two different ways in a single compilation.  */
8263   if (fpret && ! l->fpret)
8264     error ("can not handle inconsistent calls to `%s'", fnname);
8265
8266   /* If we are calling a stub which handles a floating point return
8267      value, we need to arrange to save $18 in the prologue.  We do
8268      this by marking the function call as using the register.  The
8269      prologue will later see that it is used, and emit code to save
8270      it.  */
8271
8272   if (l->fpret)
8273     {
8274       rtx insn;
8275
8276       if (retval == NULL_RTX)
8277         insn = gen_call_internal (fn, arg_size);
8278       else
8279         insn = gen_call_value_internal (retval, fn, arg_size);
8280       insn = emit_call_insn (insn);
8281
8282       if (GET_CODE (insn) != CALL_INSN)
8283         abort ();
8284
8285       CALL_INSN_FUNCTION_USAGE (insn) =
8286         gen_rtx_EXPR_LIST (VOIDmode,
8287                            gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8288                            CALL_INSN_FUNCTION_USAGE (insn));
8289
8290       /* Return 1 to tell the caller that we've generated the call
8291          insn.  */
8292       return 1;
8293     }
8294
8295   /* Return 0 to let the caller generate the call insn.  */
8296   return 0;
8297 }
8298
8299 /* We keep a list of constants we which we have to add to internal
8300    constant tables in the middle of large functions.  */
8301
8302 struct constant
8303 {
8304   struct constant *next;
8305   rtx value;
8306   rtx label;
8307   enum machine_mode mode;
8308 };
8309
8310 /* Add a constant to the list in *PCONSTANTS.  */
8311
8312 static rtx
8313 add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
8314 {
8315   struct constant *c;
8316
8317   for (c = *pconstants; c != NULL; c = c->next)
8318     if (mode == c->mode && rtx_equal_p (val, c->value))
8319       return c->label;
8320
8321   c = (struct constant *) xmalloc (sizeof *c);
8322   c->value = val;
8323   c->mode = mode;
8324   c->label = gen_label_rtx ();
8325   c->next = *pconstants;
8326   *pconstants = c;
8327   return c->label;
8328 }
8329
8330 /* Dump out the constants in CONSTANTS after INSN.  */
8331
8332 static void
8333 dump_constants (struct constant *constants, rtx insn)
8334 {
8335   struct constant *c;
8336   int align;
8337
8338   c = constants;
8339   align = 0;
8340   while (c != NULL)
8341     {
8342       rtx r;
8343       struct constant *next;
8344
8345       switch (GET_MODE_SIZE (c->mode))
8346         {
8347         case 1:
8348           align = 0;
8349           break;
8350         case 2:
8351           if (align < 1)
8352             insn = emit_insn_after (gen_align_2 (), insn);
8353           align = 1;
8354           break;
8355         case 4:
8356           if (align < 2)
8357             insn = emit_insn_after (gen_align_4 (), insn);
8358           align = 2;
8359           break;
8360         default:
8361           if (align < 3)
8362             insn = emit_insn_after (gen_align_8 (), insn);
8363           align = 3;
8364           break;
8365         }
8366
8367       insn = emit_label_after (c->label, insn);
8368
8369       switch (c->mode)
8370         {
8371         case QImode:
8372           r = gen_consttable_qi (c->value);
8373           break;
8374         case HImode:
8375           r = gen_consttable_hi (c->value);
8376           break;
8377         case SImode:
8378           r = gen_consttable_si (c->value);
8379           break;
8380         case SFmode:
8381           r = gen_consttable_sf (c->value);
8382           break;
8383         case DImode:
8384           r = gen_consttable_di (c->value);
8385           break;
8386         case DFmode:
8387           r = gen_consttable_df (c->value);
8388           break;
8389         default:
8390           abort ();
8391         }
8392
8393       insn = emit_insn_after (r, insn);
8394
8395       next = c->next;
8396       free (c);
8397       c = next;
8398     }
8399
8400   emit_barrier_after (insn);
8401 }
8402
8403 /* Find the symbol in an address expression.  */
8404
8405 static rtx
8406 mips_find_symbol (rtx addr)
8407 {
8408   if (GET_CODE (addr) == MEM)
8409     addr = XEXP (addr, 0);
8410   while (GET_CODE (addr) == CONST)
8411     addr = XEXP (addr, 0);
8412   if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8413     return addr;
8414   if (GET_CODE (addr) == PLUS)
8415     {
8416       rtx l1, l2;
8417
8418       l1 = mips_find_symbol (XEXP (addr, 0));
8419       l2 = mips_find_symbol (XEXP (addr, 1));
8420       if (l1 != NULL_RTX && l2 == NULL_RTX)
8421         return l1;
8422       else if (l1 == NULL_RTX && l2 != NULL_RTX)
8423         return l2;
8424     }
8425   return NULL_RTX;
8426 }
8427
8428 /* In mips16 mode, we need to look through the function to check for
8429    PC relative loads that are out of range.  */
8430
8431 static void
8432 mips16_lay_out_constants (void)
8433 {
8434   int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8435   rtx first, insn;
8436   struct constant *constants;
8437
8438   first = get_insns ();
8439
8440   /* Scan the function looking for PC relative loads which may be out
8441      of range.  All such loads will either be from the constant table,
8442      or be getting the address of a constant string.  If the size of
8443      the function plus the size of the constant table is less than
8444      0x8000, then all loads are in range.  */
8445
8446   insns_len = 0;
8447   for (insn = first; insn; insn = NEXT_INSN (insn))
8448     {
8449       insns_len += get_attr_length (insn);
8450
8451       /* ??? We put switch tables in .text, but we don't define
8452          JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8453          compute their lengths correctly.  */
8454       if (GET_CODE (insn) == JUMP_INSN)
8455         {
8456           rtx body;
8457
8458           body = PATTERN (insn);
8459           if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8460             insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8461                           * GET_MODE_SIZE (GET_MODE (body)));
8462           insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8463         }
8464     }
8465
8466   /* Store the original value of insns_len in cfun->machine, so
8467      that m16_usym8_4 and m16_usym5_4 can look at it.  */
8468   cfun->machine->insns_len = insns_len;
8469
8470   pool_size = get_pool_size ();
8471   if (insns_len + pool_size + mips_string_length < 0x8000)
8472     return;
8473
8474   /* Loop over the insns and figure out what the maximum internal pool
8475      size could be.  */
8476   max_internal_pool_size = 0;
8477   for (insn = first; insn; insn = NEXT_INSN (insn))
8478     {
8479       if (GET_CODE (insn) == INSN
8480           && GET_CODE (PATTERN (insn)) == SET)
8481         {
8482           rtx src;
8483
8484           src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8485           if (src == NULL_RTX)
8486             continue;
8487           if (CONSTANT_POOL_ADDRESS_P (src))
8488             max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8489           else if (SYMBOL_REF_FLAG (src))
8490             max_internal_pool_size += GET_MODE_SIZE (Pmode);
8491         }
8492     }
8493
8494   constants = NULL;
8495   addr = 0;
8496   first_constant_ref = -1;
8497
8498   for (insn = first; insn; insn = NEXT_INSN (insn))
8499     {
8500       if (GET_CODE (insn) == INSN
8501           && GET_CODE (PATTERN (insn)) == SET)
8502         {
8503           rtx val, src;
8504           enum machine_mode mode = VOIDmode;
8505
8506           val = NULL_RTX;
8507           src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8508           if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8509             {
8510               /* ??? This is very conservative, which means that we
8511                  will generate too many copies of the constant table.
8512                  The only solution would seem to be some form of
8513                  relaxing.  */
8514               if (((insns_len - addr)
8515                    + max_internal_pool_size
8516                    + get_pool_offset (src))
8517                   >= 0x8000)
8518                 {
8519                   val = get_pool_constant (src);
8520                   mode = get_pool_mode (src);
8521                 }
8522               max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8523             }
8524           else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8525             {
8526               /* Including all of mips_string_length is conservative,
8527                  and so is including all of max_internal_pool_size.  */
8528               if (((insns_len - addr)
8529                    + max_internal_pool_size
8530                    + pool_size
8531                    + mips_string_length)
8532                   >= 0x8000)
8533                 {
8534                   val = src;
8535                   mode = Pmode;
8536                 }
8537               max_internal_pool_size -= Pmode;
8538             }
8539
8540           if (val != NULL_RTX)
8541             {
8542               rtx lab, newsrc;
8543
8544               /* This PC relative load is out of range.  ??? In the
8545                  case of a string constant, we are only guessing that
8546                  it is range, since we don't know the offset of a
8547                  particular string constant.  */
8548
8549               lab = add_constant (&constants, val, mode);
8550               newsrc = gen_rtx_MEM (mode,
8551                                     gen_rtx_LABEL_REF (VOIDmode, lab));
8552               RTX_UNCHANGING_P (newsrc) = 1;
8553               PATTERN (insn) = gen_rtx_SET (VOIDmode,
8554                                             SET_DEST (PATTERN (insn)),
8555                                             newsrc);
8556               INSN_CODE (insn) = -1;
8557
8558               if (first_constant_ref < 0)
8559                 first_constant_ref = addr;
8560             }
8561         }
8562
8563       addr += get_attr_length (insn);
8564
8565       /* ??? We put switch tables in .text, but we don't define
8566          JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8567          compute their lengths correctly.  */
8568       if (GET_CODE (insn) == JUMP_INSN)
8569         {
8570           rtx body;
8571
8572           body = PATTERN (insn);
8573           if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8574             addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8575                           * GET_MODE_SIZE (GET_MODE (body)));
8576           addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8577         }
8578
8579       if (GET_CODE (insn) == BARRIER)
8580         {
8581           /* Output any constants we have accumulated.  Note that we
8582              don't need to change ADDR, since its only use is
8583              subtraction from INSNS_LEN, and both would be changed by
8584              the same amount.
8585              ??? If the instructions up to the next barrier reuse a
8586              constant, it would often be better to continue
8587              accumulating.  */
8588           if (constants != NULL)
8589             dump_constants (constants, insn);
8590           constants = NULL;
8591           first_constant_ref = -1;
8592         }
8593
8594       if (constants != NULL
8595                && (NEXT_INSN (insn) == NULL
8596                    || (first_constant_ref >= 0
8597                        && (((addr - first_constant_ref)
8598                             + 2 /* for alignment */
8599                             + 2 /* for a short jump insn */
8600                             + pool_size)
8601                            >= 0x8000))))
8602         {
8603           /* If we haven't had a barrier within 0x8000 bytes of a
8604              constant reference or we are at the end of the function,
8605              emit a barrier now.  */
8606
8607           rtx label, jump, barrier;
8608
8609           label = gen_label_rtx ();
8610           jump = emit_jump_insn_after (gen_jump (label), insn);
8611           JUMP_LABEL (jump) = label;
8612           LABEL_NUSES (label) = 1;
8613           barrier = emit_barrier_after (jump);
8614           emit_label_after (label, barrier);
8615           first_constant_ref = -1;
8616         }
8617      }
8618
8619   /* ??? If we output all references to a constant in internal
8620      constants table, we don't need to output the constant in the real
8621      constant table, but we have no way to prevent that.  */
8622 }
8623
8624
8625 /* Subroutine of mips_reorg.  If there is a hazard between INSN
8626    and a previous instruction, avoid it by inserting nops after
8627    instruction AFTER.
8628
8629    *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8630    this point.  If *DELAYED_REG is non-null, INSN must wait a cycle
8631    before using the value of that register.  *HILO_DELAY counts the
8632    number of instructions since the last hilo hazard (that is,
8633    the number of instructions since the last mflo or mfhi).
8634
8635    After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8636    for the next instruction.
8637
8638    LO_REG is an rtx for the LO register, used in dependence checking.  */
8639
8640 static void
8641 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8642                    rtx *delayed_reg, rtx lo_reg)
8643 {
8644   rtx pattern, set;
8645   int nops, ninsns;
8646
8647   if (!INSN_P (insn))
8648     return;
8649
8650   pattern = PATTERN (insn);
8651
8652   /* Do not put the whole function in .set noreorder if it contains
8653      an asm statement.  We don't know whether there will be hazards
8654      between the asm statement and the gcc-generated code.  */
8655   if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8656     cfun->machine->all_noreorder_p = false;
8657
8658   /* Ignore zero-length instructions (barriers and the like).  */
8659   ninsns = get_attr_length (insn) / 4;
8660   if (ninsns == 0)
8661     return;
8662
8663   /* Work out how many nops are needed.  Note that we only care about
8664      registers that are explicitly mentioned in the instruction's pattern.
8665      It doesn't matter that calls use the argument registers or that they
8666      clobber hi and lo.  */
8667   if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8668     nops = 2 - *hilo_delay;
8669   else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8670     nops = 1;
8671   else
8672     nops = 0;
8673
8674   /* Insert the nops between this instruction and the previous one.
8675      Each new nop takes us further from the last hilo hazard.  */
8676   *hilo_delay += nops;
8677   while (nops-- > 0)
8678     emit_insn_after (gen_hazard_nop (), after);
8679
8680   /* Set up the state for the next instruction.  */
8681   *hilo_delay += ninsns;
8682   *delayed_reg = 0;
8683   if (INSN_CODE (insn) >= 0)
8684     switch (get_attr_hazard (insn))
8685       {
8686       case HAZARD_NONE:
8687         break;
8688
8689       case HAZARD_HILO:
8690         *hilo_delay = 0;
8691         break;
8692
8693       case HAZARD_DELAY:
8694         set = single_set (insn);
8695         if (set == 0)
8696           abort ();
8697         *delayed_reg = SET_DEST (set);
8698         break;
8699       }
8700 }
8701
8702
8703 /* Go through the instruction stream and insert nops where necessary.
8704    See if the whole function can then be put into .set noreorder &
8705    .set nomacro.  */
8706
8707 static void
8708 mips_avoid_hazards (void)
8709 {
8710   rtx insn, last_insn, lo_reg, delayed_reg;
8711   int hilo_delay, i;
8712
8713   /* Recalculate instruction lengths without taking nops into account.  */
8714   cfun->machine->ignore_hazard_length_p = true;
8715   shorten_branches (get_insns ());
8716
8717   /* The profiler code uses assembler macros.  */
8718   cfun->machine->all_noreorder_p = !current_function_profile;
8719
8720   last_insn = 0;
8721   hilo_delay = 2;
8722   delayed_reg = 0;
8723   lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8724
8725   for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8726     if (INSN_P (insn))
8727       {
8728         if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8729           for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8730             mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8731                                &hilo_delay, &delayed_reg, lo_reg);
8732         else
8733           mips_avoid_hazard (last_insn, insn, &hilo_delay,
8734                              &delayed_reg, lo_reg);
8735
8736         last_insn = insn;
8737       }
8738 }
8739
8740
8741 /* Implement TARGET_MACHINE_DEPENDENT_REORG.  */
8742
8743 static void
8744 mips_reorg (void)
8745 {
8746   if (TARGET_MIPS16)
8747     mips16_lay_out_constants ();
8748   else if (TARGET_EXPLICIT_RELOCS)
8749     {
8750       if (mips_flag_delayed_branch)
8751         dbr_schedule (get_insns (), rtl_dump_file);
8752       mips_avoid_hazards ();
8753     }
8754 }
8755
8756 /* We need to use a special set of functions to handle hard floating
8757    point code in mips16 mode.  Also, allow for --enable-gofast.  */
8758
8759 #include "config/gofast.h"
8760
8761 static void
8762 mips_init_libfuncs (void)
8763 {
8764   if (TARGET_MIPS16 && mips16_hard_float)
8765     {
8766       set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8767       set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8768       set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8769       set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8770
8771       set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8772       set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8773       set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8774       set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8775       set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8776       set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8777
8778       set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fixsfsi");
8779       set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8780
8781       if (TARGET_DOUBLE_FLOAT)
8782         {
8783           set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8784           set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8785           set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8786           set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8787
8788           set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8789           set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8790           set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8791           set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8792           set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8793           set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8794
8795           set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8796           set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8797
8798           set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fixdfsi");
8799           set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8800         }
8801     }
8802   else
8803     gofast_maybe_init_libfuncs ();
8804 }
8805
8806 /* Return a number assessing the cost of moving a register in class
8807    FROM to class TO.  The classes are expressed using the enumeration
8808    values such as `GENERAL_REGS'.  A value of 2 is the default; other
8809    values are interpreted relative to that.
8810
8811    It is not required that the cost always equal 2 when FROM is the
8812    same as TO; on some machines it is expensive to move between
8813    registers if they are not general registers.
8814
8815    If reload sees an insn consisting of a single `set' between two
8816    hard registers, and if `REGISTER_MOVE_COST' applied to their
8817    classes returns a value of 2, reload does not check to ensure that
8818    the constraints of the insn are met.  Setting a cost of other than
8819    2 will allow reload to verify that the constraints are met.  You
8820    should do this if the `movM' pattern's constraints do not allow
8821    such copying.
8822
8823    ??? We make the cost of moving from HI/LO into general
8824    registers the same as for one of moving general registers to
8825    HI/LO for TARGET_MIPS16 in order to prevent allocating a
8826    pseudo to HI/LO.  This might hurt optimizations though, it
8827    isn't clear if it is wise.  And it might not work in all cases.  We
8828    could solve the DImode LO reg problem by using a multiply, just
8829    like reload_{in,out}si.  We could solve the SImode/HImode HI reg
8830    problem by using divide instructions.  divu puts the remainder in
8831    the HI reg, so doing a divide by -1 will move the value in the HI
8832    reg for all values except -1.  We could handle that case by using a
8833    signed divide, e.g.  -1 / 2 (or maybe 1 / -2?).  We'd have to emit
8834    a compare/branch to test the input value to see which instruction
8835    we need to use.  This gets pretty messy, but it is feasible.  */
8836
8837 int
8838 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8839                          enum reg_class to, enum reg_class from)
8840 {
8841   if (from == M16_REGS && GR_REG_CLASS_P (to))
8842     return 2;
8843   else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8844     return 2;
8845   else if (GR_REG_CLASS_P (from))
8846     {
8847       if (to == M16_REGS)
8848         return 2;
8849       else if (to == M16_NA_REGS)
8850         return 2;
8851       else if (GR_REG_CLASS_P (to))
8852         {
8853           if (TARGET_MIPS16)
8854             return 4;
8855           else
8856             return 2;
8857         }
8858       else if (to == FP_REGS)
8859         return 4;
8860       else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8861         {
8862           if (TARGET_MIPS16)
8863             return 12;
8864           else
8865             return 6;
8866         }
8867       else if (COP_REG_CLASS_P (to))
8868         {
8869           return 5;
8870         }
8871     }  /* GR_REG_CLASS_P (from) */
8872   else if (from == FP_REGS)
8873     {
8874       if (GR_REG_CLASS_P (to))
8875         return 4;
8876       else if (to == FP_REGS)
8877         return 2;
8878       else if (to == ST_REGS)
8879         return 8;
8880     }  /* from == FP_REGS */
8881   else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8882     {
8883       if (GR_REG_CLASS_P (to))
8884         {
8885           if (TARGET_MIPS16)
8886             return 12;
8887           else
8888             return 6;
8889         }
8890     }  /* from == HI_REG, etc.  */
8891   else if (from == ST_REGS && GR_REG_CLASS_P (to))
8892     return 4;
8893   else if (COP_REG_CLASS_P (from))
8894     {
8895       return 5;
8896     }  /* COP_REG_CLASS_P (from) */
8897
8898   /* Fall through.  */
8899
8900   return 12;
8901 }
8902
8903 /* Return the length of INSN.  LENGTH is the initial length computed by
8904    attributes in the machine-description file.  */
8905
8906 int
8907 mips_adjust_insn_length (rtx insn, int length)
8908 {
8909   /* A unconditional jump has an unfilled delay slot if it is not part
8910      of a sequence.  A conditional jump normally has a delay slot, but
8911      does not on MIPS16.  */
8912   if (simplejump_p (insn)
8913       || (!TARGET_MIPS16  && (GET_CODE (insn) == JUMP_INSN
8914                               || GET_CODE (insn) == CALL_INSN)))
8915     length += 4;
8916
8917   /* See how many nops might be needed to avoid hardware hazards.  */
8918   if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8919     switch (get_attr_hazard (insn))
8920       {
8921       case HAZARD_NONE:
8922         break;
8923
8924       case HAZARD_DELAY:
8925         length += 4;
8926         break;
8927
8928       case HAZARD_HILO:
8929         length += 8;
8930         break;
8931       }
8932
8933   /* All MIPS16 instructions are a measly two bytes.  */
8934   if (TARGET_MIPS16)
8935     length /= 2;
8936
8937   return length;
8938 }
8939
8940
8941 /* Return an asm sequence to start a noat block and load the address
8942    of a label into $1.  */
8943
8944 const char *
8945 mips_output_load_label (void)
8946 {
8947   if (TARGET_EXPLICIT_RELOCS)
8948     switch (mips_abi)
8949       {
8950       case ABI_N32:
8951         return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8952
8953       case ABI_64:
8954         return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8955
8956       default:
8957         if (ISA_HAS_LOAD_DELAY)
8958           return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8959         return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8960       }
8961   else
8962     {
8963       if (Pmode == DImode)
8964         return "%[dla\t%@,%0";
8965       else
8966         return "%[la\t%@,%0";
8967     }
8968 }
8969
8970
8971 /* Output assembly instructions to peform a conditional branch.
8972
8973    INSN is the branch instruction.  OPERANDS[0] is the condition.
8974    OPERANDS[1] is the target of the branch.  OPERANDS[2] is the target
8975    of the first operand to the condition.  If TWO_OPERANDS_P is
8976    nonzero the comparison takes two operands; OPERANDS[3] will be the
8977    second operand.
8978
8979    If INVERTED_P is nonzero we are to branch if the condition does
8980    not hold.  If FLOAT_P is nonzero this is a floating-point comparison.
8981
8982    LENGTH is the length (in bytes) of the sequence we are to generate.
8983    That tells us whether to generate a simple conditional branch, or a
8984    reversed conditional branch around a `jr' instruction.  */
8985 const char *
8986 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8987                                 int float_p, int inverted_p, int length)
8988 {
8989   static char buffer[200];
8990   /* The kind of comparison we are doing.  */
8991   enum rtx_code code = GET_CODE (operands[0]);
8992   /* Nonzero if the opcode for the comparison needs a `z' indicating
8993      that it is a comparison against zero.  */
8994   int need_z_p;
8995   /* A string to use in the assembly output to represent the first
8996      operand.  */
8997   const char *op1 = "%z2";
8998   /* A string to use in the assembly output to represent the second
8999      operand.  Use the hard-wired zero register if there's no second
9000      operand.  */
9001   const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9002   /* The operand-printing string for the comparison.  */
9003   const char *const comp = (float_p ? "%F0" : "%C0");
9004   /* The operand-printing string for the inverted comparison.  */
9005   const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9006
9007   /* The MIPS processors (for levels of the ISA at least two), have
9008      "likely" variants of each branch instruction.  These instructions
9009      annul the instruction in the delay slot if the branch is not
9010      taken.  */
9011   mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9012
9013   if (!two_operands_p)
9014     {
9015       /* To compute whether than A > B, for example, we normally
9016          subtract B from A and then look at the sign bit.  But, if we
9017          are doing an unsigned comparison, and B is zero, we don't
9018          have to do the subtraction.  Instead, we can just check to
9019          see if A is nonzero.  Thus, we change the CODE here to
9020          reflect the simpler comparison operation.  */
9021       switch (code)
9022         {
9023         case GTU:
9024           code = NE;
9025           break;
9026
9027         case LEU:
9028           code = EQ;
9029           break;
9030
9031         case GEU:
9032           /* A condition which will always be true.  */
9033           code = EQ;
9034           op1 = "%.";
9035           break;
9036
9037         case LTU:
9038           /* A condition which will always be false.  */
9039           code = NE;
9040           op1 = "%.";
9041           break;
9042
9043         default:
9044           /* Not a special case.  */
9045           break;
9046         }
9047     }
9048
9049   /* Relative comparisons are always done against zero.  But
9050      equality comparisons are done between two operands, and therefore
9051      do not require a `z' in the assembly language output.  */
9052   need_z_p = (!float_p && code != EQ && code != NE);
9053   /* For comparisons against zero, the zero is not provided
9054      explicitly.  */
9055   if (need_z_p)
9056     op2 = "";
9057
9058   /* Begin by terminating the buffer.  That way we can always use
9059      strcat to add to it.  */
9060   buffer[0] = '\0';
9061
9062   switch (length)
9063     {
9064     case 4:
9065     case 8:
9066       /* Just a simple conditional branch.  */
9067       if (float_p)
9068         sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9069                  inverted_p ? inverted_comp : comp);
9070       else
9071         sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9072                  inverted_p ? inverted_comp : comp,
9073                  need_z_p ? "z" : "",
9074                  op1,
9075                  op2);
9076       return buffer;
9077
9078     case 12:
9079     case 16:
9080     case 24:
9081     case 28:
9082       {
9083         /* Generate a reversed conditional branch around ` j'
9084            instruction:
9085
9086                 .set noreorder
9087                 .set nomacro
9088                 bc    l
9089                 delay_slot or #nop
9090                 j     target
9091                 #nop
9092              l:
9093                 .set macro
9094                 .set reorder
9095
9096            If the original branch was a likely branch, the delay slot
9097            must be executed only if the branch is taken, so generate:
9098
9099                 .set noreorder
9100                 .set nomacro
9101                 bc    l
9102                 #nop
9103                 j     target
9104                 delay slot or #nop
9105              l:
9106                 .set macro
9107                 .set reorder
9108
9109            When generating non-embedded PIC, instead of:
9110
9111                 j     target
9112
9113            we emit:
9114
9115                 .set noat
9116                 la    $at, target
9117                 jr    $at
9118                 .set at
9119         */
9120
9121         rtx orig_target;
9122         rtx target = gen_label_rtx ();
9123
9124         orig_target = operands[1];
9125         operands[1] = target;
9126         /* Generate the reversed comparison.  This takes four
9127            bytes.  */
9128         if (float_p)
9129           sprintf (buffer, "%%*b%s\t%%Z2%%1",
9130                    inverted_p ? comp : inverted_comp);
9131         else
9132           sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9133                    inverted_p ? comp : inverted_comp,
9134                    need_z_p ? "z" : "",
9135                    op1,
9136                    op2);
9137         output_asm_insn (buffer, operands);
9138
9139         if (length != 16 && length != 28 && ! mips_branch_likely)
9140           {
9141             /* Output delay slot instruction.  */
9142             rtx insn = final_sequence;
9143             final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9144                              optimize, 0, 1, NULL);
9145             INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9146           }
9147         else
9148           output_asm_insn ("%#", 0);
9149
9150         if (length <= 16)
9151           output_asm_insn ("j\t%0", &orig_target);
9152         else
9153           {
9154             output_asm_insn (mips_output_load_label (), &orig_target);
9155             output_asm_insn ("jr\t%@%]", 0);
9156           }
9157
9158         if (length != 16 && length != 28 && mips_branch_likely)
9159           {
9160             /* Output delay slot instruction.  */
9161             rtx insn = final_sequence;
9162             final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9163                              optimize, 0, 1, NULL);
9164             INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9165           }
9166         else
9167           output_asm_insn ("%#", 0);
9168
9169         (*targetm.asm_out.internal_label) (asm_out_file, "L",
9170                                    CODE_LABEL_NUMBER (target));
9171
9172         return "";
9173       }
9174
9175     default:
9176       abort ();
9177     }
9178
9179   /* NOTREACHED */
9180   return 0;
9181 }
9182 \f
9183 /* Used to output div or ddiv instruction DIVISION, which has the
9184    operands given by OPERANDS.  If we need a divide-by-zero check,
9185    output the instruction and return an asm string that traps if
9186    operand 2 is zero.  Otherwise just return DIVISION itself.  */
9187
9188 const char *
9189 mips_output_division (const char *division, rtx *operands)
9190 {
9191   if (TARGET_CHECK_ZERO_DIV)
9192     {
9193       output_asm_insn (division, operands);
9194
9195       if (TARGET_MIPS16)
9196         return "bnez\t%2,1f\n\tbreak\t7\n1:";
9197       else
9198         return "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
9199     }
9200   return division;
9201 }
9202 \f
9203 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9204    with a final "000" replaced by "k".  Ignore case.
9205
9206    Note: this function is shared between GCC and GAS.  */
9207
9208 static bool
9209 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9210 {
9211   while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9212     given++, canonical++;
9213
9214   return ((*given == 0 && *canonical == 0)
9215           || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9216 }
9217
9218
9219 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9220    CPU name.  We've traditionally allowed a lot of variation here.
9221
9222    Note: this function is shared between GCC and GAS.  */
9223
9224 static bool
9225 mips_matching_cpu_name_p (const char *canonical, const char *given)
9226 {
9227   /* First see if the name matches exactly, or with a final "000"
9228      turned into "k".  */
9229   if (mips_strict_matching_cpu_name_p (canonical, given))
9230     return true;
9231
9232   /* If not, try comparing based on numerical designation alone.
9233      See if GIVEN is an unadorned number, or 'r' followed by a number.  */
9234   if (TOLOWER (*given) == 'r')
9235     given++;
9236   if (!ISDIGIT (*given))
9237     return false;
9238
9239   /* Skip over some well-known prefixes in the canonical name,
9240      hoping to find a number there too.  */
9241   if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9242     canonical += 2;
9243   else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9244     canonical += 2;
9245   else if (TOLOWER (canonical[0]) == 'r')
9246     canonical += 1;
9247
9248   return mips_strict_matching_cpu_name_p (canonical, given);
9249 }
9250
9251
9252 /* Parse an option that takes the name of a processor as its argument.
9253    OPTION is the name of the option and CPU_STRING is the argument.
9254    Return the corresponding processor enumeration if the CPU_STRING is
9255    recognized, otherwise report an error and return null.
9256
9257    A similar function exists in GAS.  */
9258
9259 static const struct mips_cpu_info *
9260 mips_parse_cpu (const char *option, const char *cpu_string)
9261 {
9262   const struct mips_cpu_info *p;
9263   const char *s;
9264
9265   /* In the past, we allowed upper-case CPU names, but it doesn't
9266      work well with the multilib machinery.  */
9267   for (s = cpu_string; *s != 0; s++)
9268     if (ISUPPER (*s))
9269       {
9270         warning ("the cpu name must be lower case");
9271         break;
9272       }
9273
9274   /* 'from-abi' selects the most compatible architecture for the given
9275      ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs.  For the
9276      EABIs, we have to decide whether we're using the 32-bit or 64-bit
9277      version.  Look first at the -mgp options, if given, otherwise base
9278      the choice on MASK_64BIT in TARGET_DEFAULT.  */
9279   if (strcasecmp (cpu_string, "from-abi") == 0)
9280     return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9281                                    : ABI_NEEDS_64BIT_REGS ? 3
9282                                    : (TARGET_64BIT ? 3 : 1));
9283
9284   /* 'default' has traditionally been a no-op.  Probably not very useful.  */
9285   if (strcasecmp (cpu_string, "default") == 0)
9286     return 0;
9287
9288   for (p = mips_cpu_info_table; p->name != 0; p++)
9289     if (mips_matching_cpu_name_p (p->name, cpu_string))
9290       return p;
9291
9292   error ("bad value (%s) for %s", cpu_string, option);
9293   return 0;
9294 }
9295
9296
9297 /* Return the processor associated with the given ISA level, or null
9298    if the ISA isn't valid.  */
9299
9300 static const struct mips_cpu_info *
9301 mips_cpu_info_from_isa (int isa)
9302 {
9303   const struct mips_cpu_info *p;
9304
9305   for (p = mips_cpu_info_table; p->name != 0; p++)
9306     if (p->isa == isa)
9307       return p;
9308
9309   return 0;
9310 }
9311 \f
9312 /* Adjust the cost of INSN based on the relationship between INSN that
9313    is dependent on DEP_INSN through the dependence LINK.  The default
9314    is to make no adjustment to COST.
9315
9316    On the MIPS, ignore the cost of anti- and output-dependencies.  */
9317 static int
9318 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9319                   rtx dep ATTRIBUTE_UNUSED, int cost)
9320 {
9321   if (REG_NOTE_KIND (link) != 0)
9322     return 0;   /* Anti or output dependence.  */
9323   return cost;
9324 }
9325
9326 /* Implement HARD_REGNO_NREGS.  The size of FP registers are controlled
9327    by UNITS_PER_FPREG.  All other registers are word sized.  */
9328
9329 unsigned int
9330 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9331 {
9332   if (! FP_REG_P (regno))
9333     return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9334   else
9335     return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9336 }
9337
9338 /* Implement TARGET_RETURN_IN_MEMORY.  Under the old (i.e., 32 and O64 ABIs)
9339    all BLKmode objects are returned in memory.  Under the new (N32 and
9340    64-bit MIPS ABIs) small structures are returned in a register.
9341    Objects with varying size must still be returned in memory, of
9342    course.  */
9343
9344 static bool
9345 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9346 {
9347   if (TARGET_OLDABI)
9348     return (TYPE_MODE (type) == BLKmode);
9349   else
9350     return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9351             || (int_size_in_bytes (type) == -1));
9352 }
9353
9354 static bool
9355 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9356 {
9357   return !TARGET_OLDABI;
9358 }
9359
9360 static int
9361 mips_issue_rate (void)
9362 {
9363   switch (mips_tune)
9364     {
9365     case PROCESSOR_R5400:
9366     case PROCESSOR_R5500:
9367     case PROCESSOR_R7000:
9368     case PROCESSOR_R9000:
9369       return 2;
9370
9371     default:
9372       return 1;
9373     }
9374
9375   abort ();
9376
9377 }
9378
9379 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE.  Return true for
9380    processors that have a DFA pipeline description.  */
9381
9382 static int
9383 mips_use_dfa_pipeline_interface (void)
9384 {
9385   switch (mips_tune)
9386     {
9387     case PROCESSOR_R5400:
9388     case PROCESSOR_R5500:
9389     case PROCESSOR_R7000:
9390     case PROCESSOR_R9000:
9391     case PROCESSOR_SR71000:
9392       return true;
9393
9394     default:
9395       return false;
9396     }
9397 }
9398
9399
9400 const char *
9401 mips_emit_prefetch (rtx *operands)
9402 {
9403   int write = INTVAL (operands[1]);
9404   int locality = INTVAL (operands[2]);
9405   int indexed = GET_CODE (operands[3]) == REG;
9406   int code;
9407   char buffer[30];
9408
9409   if (locality <= 0)
9410     code = (write ? 5 : 4);     /* store_streamed / load_streamed.  */
9411   else if (locality <= 2)
9412     code = (write ? 1 : 0);     /* store / load.  */
9413   else
9414     code = (write ? 7 : 6);     /* store_retained / load_retained.  */
9415
9416   sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9417   output_asm_insn (buffer, operands);
9418   return "";
9419 }
9420
9421
9422 \f
9423 #if TARGET_IRIX
9424 /* Output assembly to switch to section NAME with attribute FLAGS.  */
9425
9426 static void
9427 irix_asm_named_section_1 (const char *name, unsigned int flags,
9428                            unsigned int align)
9429 {
9430   unsigned int sh_type, sh_flags, sh_entsize;
9431
9432   sh_flags = 0;
9433   if (!(flags & SECTION_DEBUG))
9434     sh_flags |= 2; /* SHF_ALLOC */
9435   if (flags & SECTION_WRITE)
9436     sh_flags |= 1; /* SHF_WRITE */
9437   if (flags & SECTION_CODE)
9438     sh_flags |= 4; /* SHF_EXECINSTR */
9439   if (flags & SECTION_SMALL)
9440     sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9441   if (strcmp (name, ".debug_frame") == 0)
9442     sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9443   if (flags & SECTION_DEBUG)
9444     sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9445   else if (flags & SECTION_BSS)
9446     sh_type = 8; /* SHT_NOBITS */
9447   else
9448     sh_type = 1; /* SHT_PROGBITS */
9449
9450   if (flags & SECTION_CODE)
9451     sh_entsize = 4;
9452   else
9453     sh_entsize = 0;
9454
9455   fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9456            name, sh_type, sh_flags, sh_entsize, align);
9457 }
9458
9459 static void
9460 irix_asm_named_section (const char *name, unsigned int flags)
9461 {
9462   if (TARGET_SGI_O32_AS)
9463     default_no_named_section (name, flags);
9464   else if (mips_abi == ABI_32 && TARGET_GAS)
9465     default_elf_asm_named_section (name, flags);
9466   else
9467     irix_asm_named_section_1 (name, flags, 0);
9468 }
9469
9470 /* In addition to emitting a .align directive, record the maximum
9471    alignment requested for the current section.  */
9472
9473 struct GTY (()) irix_section_align_entry
9474 {
9475   const char *name;
9476   unsigned int log;
9477   unsigned int flags;
9478 };
9479
9480 static htab_t irix_section_align_htab;
9481 static FILE *irix_orig_asm_out_file;
9482
9483 static int
9484 irix_section_align_entry_eq (const void *p1, const void *p2)
9485 {
9486   const struct irix_section_align_entry *old = p1;
9487   const char *new = p2;
9488
9489   return strcmp (old->name, new) == 0;
9490 }
9491
9492 static hashval_t
9493 irix_section_align_entry_hash (const void *p)
9494 {
9495   const struct irix_section_align_entry *old = p;
9496   return htab_hash_string (old->name);
9497 }
9498
9499 void
9500 irix_asm_output_align (FILE *file, unsigned int log)
9501 {
9502   const char *section = current_section_name ();
9503   struct irix_section_align_entry **slot, *entry;
9504
9505   if (mips_abi != ABI_32)
9506     {
9507       if (! section)
9508         abort ();
9509
9510       slot = (struct irix_section_align_entry **)
9511         htab_find_slot_with_hash (irix_section_align_htab, section,
9512                                   htab_hash_string (section), INSERT);
9513       entry = *slot;
9514       if (! entry)
9515         {
9516           entry = (struct irix_section_align_entry *)
9517             xmalloc (sizeof (struct irix_section_align_entry));
9518           *slot = entry;
9519           entry->name = section;
9520           entry->log = log;
9521           entry->flags = current_section_flags ();
9522         }
9523       else if (entry->log < log)
9524         entry->log = log;
9525     }
9526
9527   fprintf (file, "\t.align\t%u\n", log);
9528 }
9529
9530 /* The IRIX assembler does not record alignment from .align directives,
9531    but takes it from the first .section directive seen.  Play file
9532    switching games so that we can emit a .section directive at the
9533    beginning of the file with the proper alignment attached.  */
9534
9535 static void
9536 irix_file_start (void)
9537 {
9538   mips_file_start ();
9539
9540   if (mips_abi == ABI_32)
9541     return;
9542
9543   irix_orig_asm_out_file = asm_out_file;
9544   asm_out_file = tmpfile ();
9545
9546   irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9547                                          irix_section_align_entry_eq, NULL);
9548 }
9549
9550 static int
9551 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9552 {
9553   const struct irix_section_align_entry *entry
9554     = *(const struct irix_section_align_entry **) slot;
9555
9556   irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9557   return 1;
9558 }
9559
9560 static void
9561 copy_file_data (FILE *to, FILE *from)
9562 {
9563   char buffer[8192];
9564   size_t len;
9565   rewind (from);
9566   if (ferror (from))
9567     fatal_error ("can't rewind temp file: %m");
9568
9569   while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9570     if (fwrite (buffer, 1, len, to) != len)
9571       fatal_error ("can't write to output file: %m");
9572
9573   if (ferror (from))
9574     fatal_error ("can't read from temp file: %m");
9575
9576   if (fclose (from))
9577     fatal_error ("can't close temp file: %m");
9578 }
9579
9580 static void
9581 irix_file_end (void)
9582 {
9583   if (mips_abi != ABI_32)
9584     {
9585       /* Emit section directives with the proper alignment at the top of the
9586          real output file.  */
9587       FILE *temp = asm_out_file;
9588       asm_out_file = irix_orig_asm_out_file;
9589       htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9590
9591       /* Copy the data emitted to the temp file to the real output file.  */
9592       copy_file_data (asm_out_file, temp);
9593     }
9594
9595   mips_file_end ();
9596 }
9597
9598
9599 /* Implement TARGET_SECTION_TYPE_FLAGS.  Make sure that .sdata and
9600    .sbss sections get the SECTION_SMALL flag: this isn't set by the
9601    default code.  */
9602
9603 static unsigned int
9604 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9605 {
9606   unsigned int flags;
9607
9608   flags = default_section_type_flags (decl, section, relocs_p);
9609
9610   if (strcmp (section, ".sdata") == 0
9611       || strcmp (section, ".sbss") == 0
9612       || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9613       || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9614     flags |= SECTION_SMALL;
9615
9616   return flags;
9617 }
9618
9619 #endif /* TARGET_IRIX */
9620
9621 #include "gt-mips.h"