1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
39 #include "double-int.h"
46 #include "fold-const.h"
48 #include "stringpool.h"
49 #include "stor-layout.h"
54 #include "statistics.h"
56 #include "fixed-value.h"
63 #include "insn-codes.h"
70 #include "hash-table.h"
73 #include "target-def.h"
74 #include "common/common-target.h"
75 #include "langhooks.h"
76 #include "dominance.h"
82 #include "cfgcleanup.h"
84 #include "basic-block.h"
85 #include "sched-int.h"
86 #include "tree-ssa-alias.h"
87 #include "internal-fn.h"
88 #include "gimple-fold.h"
90 #include "gimple-expr.h"
95 #include "diagnostic.h"
96 #include "target-globals.h"
98 #include "tree-pass.h"
100 #include "hash-map.h"
101 #include "plugin-api.h"
104 #include "builtins.h"
105 #include "rtl-iter.h"
107 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
108 #define UNSPEC_ADDRESS_P(X) \
109 (GET_CODE (X) == UNSPEC \
110 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
111 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
113 /* Extract the symbol or label from UNSPEC wrapper X. */
114 #define UNSPEC_ADDRESS(X) \
117 /* Extract the symbol type from UNSPEC wrapper X. */
118 #define UNSPEC_ADDRESS_TYPE(X) \
119 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
121 /* The maximum distance between the top of the stack frame and the
122 value $sp has when we save and restore registers.
124 The value for normal-mode code must be a SMALL_OPERAND and must
125 preserve the maximum stack alignment. We therefore use a value
126 of 0x7ff0 in this case.
128 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
129 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
131 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
132 up to 0x7f8 bytes and can usually save or restore all the registers
133 that we need to save or restore. (Note that we can only use these
134 instructions for o32, for which the stack alignment is 8 bytes.)
136 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
137 RESTORE are not available. We can then use unextended instructions
138 to save and restore registers, and to allocate and deallocate the top
139 part of the frame. */
140 #define MIPS_MAX_FIRST_STACK_STEP \
141 (!TARGET_COMPRESSION ? 0x7ff0 \
142 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
143 : TARGET_64BIT ? 0x100 : 0x400)
145 /* True if INSN is a mips.md pattern or asm statement. */
146 /* ??? This test exists through the compiler, perhaps it should be
148 #define USEFUL_INSN_P(INSN) \
149 (NONDEBUG_INSN_P (INSN) \
150 && GET_CODE (PATTERN (INSN)) != USE \
151 && GET_CODE (PATTERN (INSN)) != CLOBBER)
153 /* If INSN is a delayed branch sequence, return the first instruction
154 in the sequence, otherwise return INSN itself. */
155 #define SEQ_BEGIN(INSN) \
156 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
157 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
160 /* Likewise for the last instruction in a delayed branch sequence. */
161 #define SEQ_END(INSN) \
162 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
163 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
165 XVECLEN (PATTERN (INSN), 0) - 1)) \
168 /* Execute the following loop body with SUBINSN set to each instruction
169 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
170 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
171 for ((SUBINSN) = SEQ_BEGIN (INSN); \
172 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
173 (SUBINSN) = NEXT_INSN (SUBINSN))
175 /* True if bit BIT is set in VALUE. */
176 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
178 /* Return the opcode for a ptr_mode load of the form:
180 l[wd] DEST, OFFSET(BASE). */
181 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
182 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
187 /* Return the opcode to move register SRC into register DEST. */
188 #define MIPS_MOVE(DEST, SRC) \
189 ((TARGET_64BIT ? 0x2d : 0x21) \
193 /* Return the opcode for:
196 #define MIPS_LUI(DEST, VALUE) \
197 ((0xf << 26) | ((DEST) << 16) | (VALUE))
199 /* Return the opcode to jump to register DEST. When the JR opcode is not
200 available use JALR $0, DEST. */
201 #define MIPS_JR(DEST) \
202 (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9))
204 /* Return the opcode for:
206 bal . + (1 + OFFSET) * 4. */
207 #define MIPS_BAL(OFFSET) \
208 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
210 /* Return the usual opcode for a nop. */
213 /* Classifies an address.
216 A natural register + offset address. The register satisfies
217 mips_valid_base_register_p and the offset is a const_arith_operand.
220 A LO_SUM rtx. The first operand is a valid base register and
221 the second operand is a symbolic address.
224 A signed 16-bit constant address.
227 A constant symbolic address. */
228 enum mips_address_type
{
235 /* Macros to create an enumeration identifier for a function prototype. */
236 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
237 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
238 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
239 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
241 /* Classifies the prototype of a built-in function. */
242 enum mips_function_type
{
243 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
244 #include "config/mips/mips-ftypes.def"
245 #undef DEF_MIPS_FTYPE
249 /* Specifies how a built-in function should be converted into rtl. */
250 enum mips_builtin_type
{
251 /* The function corresponds directly to an .md pattern. The return
252 value is mapped to operand 0 and the arguments are mapped to
253 operands 1 and above. */
256 /* The function corresponds directly to an .md pattern. There is no return
257 value and the arguments are mapped to operands 0 and above. */
258 MIPS_BUILTIN_DIRECT_NO_TARGET
,
260 /* The function corresponds to a comparison instruction followed by
261 a mips_cond_move_tf_ps pattern. The first two arguments are the
262 values to compare and the second two arguments are the vector
263 operands for the movt.ps or movf.ps instruction (in assembly order). */
267 /* The function corresponds to a V2SF comparison instruction. Operand 0
268 of this instruction is the result of the comparison, which has mode
269 CCV2 or CCV4. The function arguments are mapped to operands 1 and
270 above. The function's return value is an SImode boolean that is
271 true under the following conditions:
273 MIPS_BUILTIN_CMP_ANY: one of the registers is true
274 MIPS_BUILTIN_CMP_ALL: all of the registers are true
275 MIPS_BUILTIN_CMP_LOWER: the first register is true
276 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
277 MIPS_BUILTIN_CMP_ANY
,
278 MIPS_BUILTIN_CMP_ALL
,
279 MIPS_BUILTIN_CMP_UPPER
,
280 MIPS_BUILTIN_CMP_LOWER
,
282 /* As above, but the instruction only sets a single $fcc register. */
283 MIPS_BUILTIN_CMP_SINGLE
,
285 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
286 MIPS_BUILTIN_BPOSGE32
289 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
290 #define MIPS_FP_CONDITIONS(MACRO) \
308 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
309 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
310 enum mips_fp_condition
{
311 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
313 #undef DECLARE_MIPS_COND
315 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
316 #define STRINGIFY(X) #X
317 static const char *const mips_fp_conditions
[] = {
318 MIPS_FP_CONDITIONS (STRINGIFY
)
322 /* A class used to control a comdat-style stub that we output in each
323 translation unit that needs it. */
324 class mips_one_only_stub
{
326 virtual ~mips_one_only_stub () {}
328 /* Return the name of the stub. */
329 virtual const char *get_name () = 0;
331 /* Output the body of the function to asm_out_file. */
332 virtual void output_body () = 0;
335 /* Tuning information that is automatically derived from other sources
336 (such as the scheduler). */
338 /* The architecture and tuning settings that this structure describes. */
342 /* True if this structure describes MIPS16 settings. */
345 /* True if the structure has been initialized. */
348 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
349 when optimizing for speed. */
350 bool fast_mult_zero_zero_p
;
353 /* Information about a function's frame layout. */
354 struct GTY(()) mips_frame_info
{
355 /* The size of the frame in bytes. */
356 HOST_WIDE_INT total_size
;
358 /* The number of bytes allocated to variables. */
359 HOST_WIDE_INT var_size
;
361 /* The number of bytes allocated to outgoing function arguments. */
362 HOST_WIDE_INT args_size
;
364 /* The number of bytes allocated to the .cprestore slot, or 0 if there
366 HOST_WIDE_INT cprestore_size
;
368 /* Bit X is set if the function saves or restores GPR X. */
371 /* Likewise FPR X. */
374 /* Likewise doubleword accumulator X ($acX). */
375 unsigned int acc_mask
;
377 /* The number of GPRs, FPRs, doubleword accumulators and COP0
381 unsigned int num_acc
;
382 unsigned int num_cop0_regs
;
384 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
385 save slots from the top of the frame, or zero if no such slots are
387 HOST_WIDE_INT gp_save_offset
;
388 HOST_WIDE_INT fp_save_offset
;
389 HOST_WIDE_INT acc_save_offset
;
390 HOST_WIDE_INT cop0_save_offset
;
392 /* Likewise, but giving offsets from the bottom of the frame. */
393 HOST_WIDE_INT gp_sp_offset
;
394 HOST_WIDE_INT fp_sp_offset
;
395 HOST_WIDE_INT acc_sp_offset
;
396 HOST_WIDE_INT cop0_sp_offset
;
398 /* Similar, but the value passed to _mcount. */
399 HOST_WIDE_INT ra_fp_offset
;
401 /* The offset of arg_pointer_rtx from the bottom of the frame. */
402 HOST_WIDE_INT arg_pointer_offset
;
404 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
405 HOST_WIDE_INT hard_frame_pointer_offset
;
408 struct GTY(()) machine_function
{
409 /* The next floating-point condition-code register to allocate
410 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
411 unsigned int next_fcc
;
413 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
414 rtx mips16_gp_pseudo_rtx
;
416 /* The number of extra stack bytes taken up by register varargs.
417 This area is allocated by the callee at the very top of the frame. */
420 /* The current frame information, calculated by mips_compute_frame_info. */
421 struct mips_frame_info frame
;
423 /* The register to use as the function's global pointer, or INVALID_REGNUM
424 if the function doesn't need one. */
425 unsigned int global_pointer
;
427 /* How many instructions it takes to load a label into $AT, or 0 if
428 this property hasn't yet been calculated. */
429 unsigned int load_label_num_insns
;
431 /* True if mips_adjust_insn_length should ignore an instruction's
433 bool ignore_hazard_length_p
;
435 /* True if the whole function is suitable for .set noreorder and
437 bool all_noreorder_p
;
439 /* True if the function has "inflexible" and "flexible" references
440 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
441 and mips_cfun_has_flexible_gp_ref_p for details. */
442 bool has_inflexible_gp_insn_p
;
443 bool has_flexible_gp_insn_p
;
445 /* True if the function's prologue must load the global pointer
446 value into pic_offset_table_rtx and store the same value in
447 the function's cprestore slot (if any). Even if this value
448 is currently false, we may decide to set it to true later;
449 see mips_must_initialize_gp_p () for details. */
450 bool must_initialize_gp_p
;
452 /* True if the current function must restore $gp after any potential
453 clobber. This value is only meaningful during the first post-epilogue
454 split_insns pass; see mips_must_initialize_gp_p () for details. */
455 bool must_restore_gp_when_clobbered_p
;
457 /* True if this is an interrupt handler. */
458 bool interrupt_handler_p
;
460 /* True if this is an interrupt handler that uses shadow registers. */
461 bool use_shadow_register_set_p
;
463 /* True if this is an interrupt handler that should keep interrupts
465 bool keep_interrupts_masked_p
;
467 /* True if this is an interrupt handler that should use DERET
469 bool use_debug_exception_return_p
;
472 /* Information about a single argument. */
473 struct mips_arg_info
{
474 /* True if the argument is passed in a floating-point register, or
475 would have been if we hadn't run out of registers. */
478 /* The number of words passed in registers, rounded up. */
479 unsigned int reg_words
;
481 /* For EABI, the offset of the first register from GP_ARG_FIRST or
482 FP_ARG_FIRST. For other ABIs, the offset of the first register from
483 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
484 comment for details).
486 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
488 unsigned int reg_offset
;
490 /* The number of words that must be passed on the stack, rounded up. */
491 unsigned int stack_words
;
493 /* The offset from the start of the stack overflow area of the argument's
494 first stack word. Only meaningful when STACK_WORDS is nonzero. */
495 unsigned int stack_offset
;
498 /* Information about an address described by mips_address_type.
504 REG is the base register and OFFSET is the constant offset.
507 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
508 is the type of symbol it references.
511 SYMBOL_TYPE is the type of symbol that the address references. */
512 struct mips_address_info
{
513 enum mips_address_type type
;
516 enum mips_symbol_type symbol_type
;
519 /* One stage in a constant building sequence. These sequences have
523 A = A CODE[1] VALUE[1]
524 A = A CODE[2] VALUE[2]
527 where A is an accumulator, each CODE[i] is a binary rtl operation
528 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
529 struct mips_integer_op
{
531 unsigned HOST_WIDE_INT value
;
534 /* The largest number of operations needed to load an integer constant.
535 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
536 When the lowest bit is clear, we can try, but reject a sequence with
537 an extra SLL at the end. */
538 #define MIPS_MAX_INTEGER_OPS 7
540 /* Information about a MIPS16e SAVE or RESTORE instruction. */
541 struct mips16e_save_restore_info
{
542 /* The number of argument registers saved by a SAVE instruction.
543 0 for RESTORE instructions. */
546 /* Bit X is set if the instruction saves or restores GPR X. */
549 /* The total number of bytes to allocate. */
553 /* Costs of various operations on the different architectures. */
555 struct mips_rtx_cost_data
557 unsigned short fp_add
;
558 unsigned short fp_mult_sf
;
559 unsigned short fp_mult_df
;
560 unsigned short fp_div_sf
;
561 unsigned short fp_div_df
;
562 unsigned short int_mult_si
;
563 unsigned short int_mult_di
;
564 unsigned short int_div_si
;
565 unsigned short int_div_di
;
566 unsigned short branch_cost
;
567 unsigned short memory_latency
;
570 /* Global variables for machine-dependent things. */
572 /* The -G setting, or the configuration's default small-data limit if
573 no -G option is given. */
574 static unsigned int mips_small_data_threshold
;
576 /* The number of file directives written by mips_output_filename. */
577 int num_source_filenames
;
579 /* The name that appeared in the last .file directive written by
580 mips_output_filename, or "" if mips_output_filename hasn't
581 written anything yet. */
582 const char *current_function_file
= "";
584 /* Arrays that map GCC register numbers to debugger register numbers. */
585 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
586 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
588 /* Information about the current function's epilogue, used only while
591 /* A list of queued REG_CFA_RESTORE notes. */
594 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
596 HOST_WIDE_INT cfa_offset
;
598 /* The offset of the CFA from the stack pointer while restoring
600 HOST_WIDE_INT cfa_restore_sp_offset
;
603 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
604 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
605 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
606 struct mips_asm_switch mips_noat
= { "at", 0 };
608 /* True if we're writing out a branch-likely instruction rather than a
610 static bool mips_branch_likely
;
612 /* The current instruction-set architecture. */
613 enum processor mips_arch
;
614 const struct mips_cpu_info
*mips_arch_info
;
616 /* The processor that we should tune the code for. */
617 enum processor mips_tune
;
618 const struct mips_cpu_info
*mips_tune_info
;
620 /* The ISA level associated with mips_arch. */
623 /* The ISA revision level. This is 0 for MIPS I to V and N for
627 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
628 static const struct mips_cpu_info
*mips_isa_option_info
;
630 /* Which cost information to use. */
631 static const struct mips_rtx_cost_data
*mips_cost
;
633 /* The ambient target flags, excluding MASK_MIPS16. */
634 static int mips_base_target_flags
;
636 /* The default compression mode. */
637 unsigned int mips_base_compression_flags
;
639 /* The ambient values of other global variables. */
640 static int mips_base_schedule_insns
; /* flag_schedule_insns */
641 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
642 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
643 static int mips_base_align_loops
; /* align_loops */
644 static int mips_base_align_jumps
; /* align_jumps */
645 static int mips_base_align_functions
; /* align_functions */
647 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
648 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
650 /* Index C is true if character C is a valid PRINT_OPERAND punctation
652 static bool mips_print_operand_punct
[256];
654 static GTY (()) int mips_output_filename_first_time
= 1;
656 /* mips_split_p[X] is true if symbols of type X can be split by
657 mips_split_symbol. */
658 bool mips_split_p
[NUM_SYMBOL_TYPES
];
660 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
661 can be split by mips_split_symbol. */
662 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
664 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
665 forced into a PC-relative constant pool. */
666 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
668 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
669 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
670 if they are matched by a special .md file pattern. */
671 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
673 /* Likewise for HIGHs. */
674 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
676 /* Target state for MIPS16. */
677 struct target_globals
*mips16_globals
;
679 /* Target state for MICROMIPS. */
680 struct target_globals
*micromips_globals
;
682 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
683 and returned from mips_sched_reorder2. */
684 static int cached_can_issue_more
;
686 /* The stubs for various MIPS16 support functions, if used. */
687 static mips_one_only_stub
*mips16_rdhwr_stub
;
688 static mips_one_only_stub
*mips16_get_fcsr_stub
;
689 static mips_one_only_stub
*mips16_set_fcsr_stub
;
691 /* Index R is the smallest register class that contains register R. */
692 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
693 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
694 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
695 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
696 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
697 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
698 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
699 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
700 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
702 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
703 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
704 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
705 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
706 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
707 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
708 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
709 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
710 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
711 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
712 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
713 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
714 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
715 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
716 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
717 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
718 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
719 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
720 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
721 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
722 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
723 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
724 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
725 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
726 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
727 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
728 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
729 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
730 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
731 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
732 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
733 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
734 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
735 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
736 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
737 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
738 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
739 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
740 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
743 /* The value of TARGET_ATTRIBUTE_TABLE. */
744 static const struct attribute_spec mips_attribute_table
[] = {
745 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
747 { "long_call", 0, 0, false, true, true, NULL
, false },
748 { "far", 0, 0, false, true, true, NULL
, false },
749 { "near", 0, 0, false, true, true, NULL
, false },
750 /* We would really like to treat "mips16" and "nomips16" as type
751 attributes, but GCC doesn't provide the hooks we need to support
752 the right conversion rules. As declaration attributes, they affect
753 code generation but don't carry other semantics. */
754 { "mips16", 0, 0, true, false, false, NULL
, false },
755 { "nomips16", 0, 0, true, false, false, NULL
, false },
756 { "micromips", 0, 0, true, false, false, NULL
, false },
757 { "nomicromips", 0, 0, true, false, false, NULL
, false },
758 { "nocompression", 0, 0, true, false, false, NULL
, false },
759 /* Allow functions to be specified as interrupt handlers */
760 { "interrupt", 0, 0, false, true, true, NULL
, false },
761 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
762 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
763 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
764 { NULL
, 0, 0, false, false, false, NULL
, false }
767 /* A table describing all the processors GCC knows about; see
768 mips-cpus.def for details. */
769 static const struct mips_cpu_info mips_cpu_info_table
[] = {
770 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
771 { NAME, CPU, ISA, FLAGS },
772 #include "mips-cpus.def"
776 /* Default costs. If these are used for a processor we should look
777 up the actual costs. */
778 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
779 COSTS_N_INSNS (7), /* fp_mult_sf */ \
780 COSTS_N_INSNS (8), /* fp_mult_df */ \
781 COSTS_N_INSNS (23), /* fp_div_sf */ \
782 COSTS_N_INSNS (36), /* fp_div_df */ \
783 COSTS_N_INSNS (10), /* int_mult_si */ \
784 COSTS_N_INSNS (10), /* int_mult_di */ \
785 COSTS_N_INSNS (69), /* int_div_si */ \
786 COSTS_N_INSNS (69), /* int_div_di */ \
787 2, /* branch_cost */ \
788 4 /* memory_latency */
790 /* Floating-point costs for processors without an FPU. Just assume that
791 all floating-point libcalls are very expensive. */
792 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
793 COSTS_N_INSNS (256), /* fp_mult_sf */ \
794 COSTS_N_INSNS (256), /* fp_mult_df */ \
795 COSTS_N_INSNS (256), /* fp_div_sf */ \
796 COSTS_N_INSNS (256) /* fp_div_df */
798 /* Costs to use when optimizing for size. */
799 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
800 COSTS_N_INSNS (1), /* fp_add */
801 COSTS_N_INSNS (1), /* fp_mult_sf */
802 COSTS_N_INSNS (1), /* fp_mult_df */
803 COSTS_N_INSNS (1), /* fp_div_sf */
804 COSTS_N_INSNS (1), /* fp_div_df */
805 COSTS_N_INSNS (1), /* int_mult_si */
806 COSTS_N_INSNS (1), /* int_mult_di */
807 COSTS_N_INSNS (1), /* int_div_si */
808 COSTS_N_INSNS (1), /* int_div_di */
810 4 /* memory_latency */
813 /* Costs to use when optimizing for speed, indexed by processor. */
814 static const struct mips_rtx_cost_data
815 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
817 COSTS_N_INSNS (2), /* fp_add */
818 COSTS_N_INSNS (4), /* fp_mult_sf */
819 COSTS_N_INSNS (5), /* fp_mult_df */
820 COSTS_N_INSNS (12), /* fp_div_sf */
821 COSTS_N_INSNS (19), /* fp_div_df */
822 COSTS_N_INSNS (12), /* int_mult_si */
823 COSTS_N_INSNS (12), /* int_mult_di */
824 COSTS_N_INSNS (35), /* int_div_si */
825 COSTS_N_INSNS (35), /* int_div_di */
827 4 /* memory_latency */
831 COSTS_N_INSNS (6), /* int_mult_si */
832 COSTS_N_INSNS (6), /* int_mult_di */
833 COSTS_N_INSNS (36), /* int_div_si */
834 COSTS_N_INSNS (36), /* int_div_di */
836 4 /* memory_latency */
840 COSTS_N_INSNS (36), /* int_mult_si */
841 COSTS_N_INSNS (36), /* int_mult_di */
842 COSTS_N_INSNS (37), /* int_div_si */
843 COSTS_N_INSNS (37), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (4), /* int_mult_si */
850 COSTS_N_INSNS (11), /* int_mult_di */
851 COSTS_N_INSNS (36), /* int_div_si */
852 COSTS_N_INSNS (68), /* int_div_di */
854 4 /* memory_latency */
857 COSTS_N_INSNS (4), /* fp_add */
858 COSTS_N_INSNS (4), /* fp_mult_sf */
859 COSTS_N_INSNS (5), /* fp_mult_df */
860 COSTS_N_INSNS (17), /* fp_div_sf */
861 COSTS_N_INSNS (32), /* fp_div_df */
862 COSTS_N_INSNS (4), /* int_mult_si */
863 COSTS_N_INSNS (11), /* int_mult_di */
864 COSTS_N_INSNS (36), /* int_div_si */
865 COSTS_N_INSNS (68), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (4), /* fp_add */
871 COSTS_N_INSNS (4), /* fp_mult_sf */
872 COSTS_N_INSNS (5), /* fp_mult_df */
873 COSTS_N_INSNS (17), /* fp_div_sf */
874 COSTS_N_INSNS (32), /* fp_div_df */
875 COSTS_N_INSNS (4), /* int_mult_si */
876 COSTS_N_INSNS (7), /* int_mult_di */
877 COSTS_N_INSNS (42), /* int_div_si */
878 COSTS_N_INSNS (72), /* int_div_di */
880 4 /* memory_latency */
884 COSTS_N_INSNS (5), /* int_mult_si */
885 COSTS_N_INSNS (5), /* int_mult_di */
886 COSTS_N_INSNS (41), /* int_div_si */
887 COSTS_N_INSNS (41), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (8), /* fp_add */
893 COSTS_N_INSNS (8), /* fp_mult_sf */
894 COSTS_N_INSNS (10), /* fp_mult_df */
895 COSTS_N_INSNS (34), /* fp_div_sf */
896 COSTS_N_INSNS (64), /* fp_div_df */
897 COSTS_N_INSNS (5), /* int_mult_si */
898 COSTS_N_INSNS (5), /* int_mult_di */
899 COSTS_N_INSNS (41), /* int_div_si */
900 COSTS_N_INSNS (41), /* int_div_di */
902 4 /* memory_latency */
905 COSTS_N_INSNS (4), /* fp_add */
906 COSTS_N_INSNS (4), /* fp_mult_sf */
907 COSTS_N_INSNS (5), /* fp_mult_df */
908 COSTS_N_INSNS (17), /* fp_div_sf */
909 COSTS_N_INSNS (32), /* fp_div_df */
910 COSTS_N_INSNS (5), /* int_mult_si */
911 COSTS_N_INSNS (5), /* int_mult_di */
912 COSTS_N_INSNS (41), /* int_div_si */
913 COSTS_N_INSNS (41), /* int_div_di */
915 4 /* memory_latency */
919 COSTS_N_INSNS (5), /* int_mult_si */
920 COSTS_N_INSNS (5), /* int_mult_di */
921 COSTS_N_INSNS (41), /* int_div_si */
922 COSTS_N_INSNS (41), /* int_div_di */
924 4 /* memory_latency */
927 COSTS_N_INSNS (8), /* fp_add */
928 COSTS_N_INSNS (8), /* fp_mult_sf */
929 COSTS_N_INSNS (10), /* fp_mult_df */
930 COSTS_N_INSNS (34), /* fp_div_sf */
931 COSTS_N_INSNS (64), /* fp_div_df */
932 COSTS_N_INSNS (5), /* int_mult_si */
933 COSTS_N_INSNS (5), /* int_mult_di */
934 COSTS_N_INSNS (41), /* int_div_si */
935 COSTS_N_INSNS (41), /* int_div_di */
937 4 /* memory_latency */
940 COSTS_N_INSNS (4), /* fp_add */
941 COSTS_N_INSNS (4), /* fp_mult_sf */
942 COSTS_N_INSNS (5), /* fp_mult_df */
943 COSTS_N_INSNS (17), /* fp_div_sf */
944 COSTS_N_INSNS (32), /* fp_div_df */
945 COSTS_N_INSNS (5), /* int_mult_si */
946 COSTS_N_INSNS (5), /* int_mult_di */
947 COSTS_N_INSNS (41), /* int_div_si */
948 COSTS_N_INSNS (41), /* int_div_di */
950 4 /* memory_latency */
953 COSTS_N_INSNS (6), /* fp_add */
954 COSTS_N_INSNS (6), /* fp_mult_sf */
955 COSTS_N_INSNS (7), /* fp_mult_df */
956 COSTS_N_INSNS (25), /* fp_div_sf */
957 COSTS_N_INSNS (48), /* fp_div_df */
958 COSTS_N_INSNS (5), /* int_mult_si */
959 COSTS_N_INSNS (5), /* int_mult_di */
960 COSTS_N_INSNS (41), /* int_div_si */
961 COSTS_N_INSNS (41), /* int_div_di */
963 4 /* memory_latency */
980 COSTS_N_INSNS (5), /* int_mult_si */
981 COSTS_N_INSNS (5), /* int_mult_di */
982 COSTS_N_INSNS (72), /* int_div_si */
983 COSTS_N_INSNS (72), /* int_div_di */
985 4 /* memory_latency */
990 COSTS_N_INSNS (6), /* int_mult_si */
991 COSTS_N_INSNS (6), /* int_mult_di */
992 COSTS_N_INSNS (18), /* int_div_si */
993 COSTS_N_INSNS (35), /* int_div_di */
995 4 /* memory_latency */
999 COSTS_N_INSNS (6), /* fp_add */
1000 COSTS_N_INSNS (6), /* fp_mult_sf */
1001 COSTS_N_INSNS (7), /* fp_mult_df */
1002 COSTS_N_INSNS (25), /* fp_div_sf */
1003 COSTS_N_INSNS (48), /* fp_div_df */
1004 COSTS_N_INSNS (6), /* int_mult_si */
1005 COSTS_N_INSNS (6), /* int_mult_di */
1006 COSTS_N_INSNS (18), /* int_div_si */
1007 COSTS_N_INSNS (35), /* int_div_di */
1008 4, /* branch_cost */
1009 4 /* memory_latency */
1012 COSTS_N_INSNS (2), /* fp_add */
1013 COSTS_N_INSNS (4), /* fp_mult_sf */
1014 COSTS_N_INSNS (5), /* fp_mult_df */
1015 COSTS_N_INSNS (12), /* fp_div_sf */
1016 COSTS_N_INSNS (19), /* fp_div_df */
1017 COSTS_N_INSNS (2), /* int_mult_si */
1018 COSTS_N_INSNS (2), /* int_mult_di */
1019 COSTS_N_INSNS (35), /* int_div_si */
1020 COSTS_N_INSNS (35), /* int_div_di */
1021 1, /* branch_cost */
1022 4 /* memory_latency */
1025 COSTS_N_INSNS (3), /* fp_add */
1026 COSTS_N_INSNS (5), /* fp_mult_sf */
1027 COSTS_N_INSNS (6), /* fp_mult_df */
1028 COSTS_N_INSNS (15), /* fp_div_sf */
1029 COSTS_N_INSNS (16), /* fp_div_df */
1030 COSTS_N_INSNS (17), /* int_mult_si */
1031 COSTS_N_INSNS (17), /* int_mult_di */
1032 COSTS_N_INSNS (38), /* int_div_si */
1033 COSTS_N_INSNS (38), /* int_div_di */
1034 2, /* branch_cost */
1035 6 /* memory_latency */
1038 COSTS_N_INSNS (6), /* fp_add */
1039 COSTS_N_INSNS (7), /* fp_mult_sf */
1040 COSTS_N_INSNS (8), /* fp_mult_df */
1041 COSTS_N_INSNS (23), /* fp_div_sf */
1042 COSTS_N_INSNS (36), /* fp_div_df */
1043 COSTS_N_INSNS (10), /* int_mult_si */
1044 COSTS_N_INSNS (10), /* int_mult_di */
1045 COSTS_N_INSNS (69), /* int_div_si */
1046 COSTS_N_INSNS (69), /* int_div_di */
1047 2, /* branch_cost */
1048 6 /* memory_latency */
1060 /* The only costs that appear to be updated here are
1061 integer multiplication. */
1063 COSTS_N_INSNS (4), /* int_mult_si */
1064 COSTS_N_INSNS (6), /* int_mult_di */
1065 COSTS_N_INSNS (69), /* int_div_si */
1066 COSTS_N_INSNS (69), /* int_div_di */
1067 1, /* branch_cost */
1068 4 /* memory_latency */
1083 COSTS_N_INSNS (6), /* fp_add */
1084 COSTS_N_INSNS (4), /* fp_mult_sf */
1085 COSTS_N_INSNS (5), /* fp_mult_df */
1086 COSTS_N_INSNS (23), /* fp_div_sf */
1087 COSTS_N_INSNS (36), /* fp_div_df */
1088 COSTS_N_INSNS (5), /* int_mult_si */
1089 COSTS_N_INSNS (5), /* int_mult_di */
1090 COSTS_N_INSNS (36), /* int_div_si */
1091 COSTS_N_INSNS (36), /* int_div_di */
1092 1, /* branch_cost */
1093 4 /* memory_latency */
1096 COSTS_N_INSNS (6), /* fp_add */
1097 COSTS_N_INSNS (5), /* fp_mult_sf */
1098 COSTS_N_INSNS (6), /* fp_mult_df */
1099 COSTS_N_INSNS (30), /* fp_div_sf */
1100 COSTS_N_INSNS (59), /* fp_div_df */
1101 COSTS_N_INSNS (3), /* int_mult_si */
1102 COSTS_N_INSNS (4), /* int_mult_di */
1103 COSTS_N_INSNS (42), /* int_div_si */
1104 COSTS_N_INSNS (74), /* int_div_di */
1105 1, /* branch_cost */
1106 4 /* memory_latency */
1109 COSTS_N_INSNS (6), /* fp_add */
1110 COSTS_N_INSNS (5), /* fp_mult_sf */
1111 COSTS_N_INSNS (6), /* fp_mult_df */
1112 COSTS_N_INSNS (30), /* fp_div_sf */
1113 COSTS_N_INSNS (59), /* fp_div_df */
1114 COSTS_N_INSNS (5), /* int_mult_si */
1115 COSTS_N_INSNS (9), /* int_mult_di */
1116 COSTS_N_INSNS (42), /* int_div_si */
1117 COSTS_N_INSNS (74), /* int_div_di */
1118 1, /* branch_cost */
1119 4 /* memory_latency */
1122 COSTS_N_INSNS (4), /* fp_add */
1123 COSTS_N_INSNS (4), /* fp_mult_sf */
1124 COSTS_N_INSNS (256), /* fp_mult_df */
1125 COSTS_N_INSNS (8), /* fp_div_sf */
1126 COSTS_N_INSNS (256), /* fp_div_df */
1127 COSTS_N_INSNS (4), /* int_mult_si */
1128 COSTS_N_INSNS (256), /* int_mult_di */
1129 COSTS_N_INSNS (37), /* int_div_si */
1130 COSTS_N_INSNS (256), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1135 /* The only costs that are changed here are
1136 integer multiplication. */
1137 COSTS_N_INSNS (6), /* fp_add */
1138 COSTS_N_INSNS (7), /* fp_mult_sf */
1139 COSTS_N_INSNS (8), /* fp_mult_df */
1140 COSTS_N_INSNS (23), /* fp_div_sf */
1141 COSTS_N_INSNS (36), /* fp_div_df */
1142 COSTS_N_INSNS (5), /* int_mult_si */
1143 COSTS_N_INSNS (9), /* int_mult_di */
1144 COSTS_N_INSNS (69), /* int_div_si */
1145 COSTS_N_INSNS (69), /* int_div_di */
1146 1, /* branch_cost */
1147 4 /* memory_latency */
1153 /* The only costs that are changed here are
1154 integer multiplication. */
1155 COSTS_N_INSNS (6), /* fp_add */
1156 COSTS_N_INSNS (7), /* fp_mult_sf */
1157 COSTS_N_INSNS (8), /* fp_mult_df */
1158 COSTS_N_INSNS (23), /* fp_div_sf */
1159 COSTS_N_INSNS (36), /* fp_div_df */
1160 COSTS_N_INSNS (3), /* int_mult_si */
1161 COSTS_N_INSNS (8), /* int_mult_di */
1162 COSTS_N_INSNS (69), /* int_div_si */
1163 COSTS_N_INSNS (69), /* int_div_di */
1164 1, /* branch_cost */
1165 4 /* memory_latency */
1168 COSTS_N_INSNS (2), /* fp_add */
1169 COSTS_N_INSNS (2), /* fp_mult_sf */
1170 COSTS_N_INSNS (2), /* fp_mult_df */
1171 COSTS_N_INSNS (12), /* fp_div_sf */
1172 COSTS_N_INSNS (19), /* fp_div_df */
1173 COSTS_N_INSNS (5), /* int_mult_si */
1174 COSTS_N_INSNS (9), /* int_mult_di */
1175 COSTS_N_INSNS (34), /* int_div_si */
1176 COSTS_N_INSNS (66), /* int_div_di */
1177 1, /* branch_cost */
1178 4 /* memory_latency */
1181 /* These costs are the same as the SB-1A below. */
1182 COSTS_N_INSNS (4), /* fp_add */
1183 COSTS_N_INSNS (4), /* fp_mult_sf */
1184 COSTS_N_INSNS (4), /* fp_mult_df */
1185 COSTS_N_INSNS (24), /* fp_div_sf */
1186 COSTS_N_INSNS (32), /* fp_div_df */
1187 COSTS_N_INSNS (3), /* int_mult_si */
1188 COSTS_N_INSNS (4), /* int_mult_di */
1189 COSTS_N_INSNS (36), /* int_div_si */
1190 COSTS_N_INSNS (68), /* int_div_di */
1191 1, /* branch_cost */
1192 4 /* memory_latency */
1195 /* These costs are the same as the SB-1 above. */
1196 COSTS_N_INSNS (4), /* fp_add */
1197 COSTS_N_INSNS (4), /* fp_mult_sf */
1198 COSTS_N_INSNS (4), /* fp_mult_df */
1199 COSTS_N_INSNS (24), /* fp_div_sf */
1200 COSTS_N_INSNS (32), /* fp_div_df */
1201 COSTS_N_INSNS (3), /* int_mult_si */
1202 COSTS_N_INSNS (4), /* int_mult_di */
1203 COSTS_N_INSNS (36), /* int_div_si */
1204 COSTS_N_INSNS (68), /* int_div_di */
1205 1, /* branch_cost */
1206 4 /* memory_latency */
1213 COSTS_N_INSNS (8), /* int_mult_si */
1214 COSTS_N_INSNS (8), /* int_mult_di */
1215 COSTS_N_INSNS (72), /* int_div_si */
1216 COSTS_N_INSNS (72), /* int_div_di */
1217 1, /* branch_cost */
1218 4 /* memory_latency */
1221 /* These costs are the same as 5KF above. */
1222 COSTS_N_INSNS (4), /* fp_add */
1223 COSTS_N_INSNS (4), /* fp_mult_sf */
1224 COSTS_N_INSNS (5), /* fp_mult_df */
1225 COSTS_N_INSNS (17), /* fp_div_sf */
1226 COSTS_N_INSNS (32), /* fp_div_df */
1227 COSTS_N_INSNS (4), /* int_mult_si */
1228 COSTS_N_INSNS (11), /* int_mult_di */
1229 COSTS_N_INSNS (36), /* int_div_si */
1230 COSTS_N_INSNS (68), /* int_div_di */
1231 1, /* branch_cost */
1232 4 /* memory_latency */
1235 COSTS_N_INSNS (4), /* fp_add */
1236 COSTS_N_INSNS (5), /* fp_mult_sf */
1237 COSTS_N_INSNS (5), /* fp_mult_df */
1238 COSTS_N_INSNS (17), /* fp_div_sf */
1239 COSTS_N_INSNS (17), /* fp_div_df */
1240 COSTS_N_INSNS (5), /* int_mult_si */
1241 COSTS_N_INSNS (5), /* int_mult_di */
1242 COSTS_N_INSNS (8), /* int_div_si */
1243 COSTS_N_INSNS (8), /* int_div_di */
1244 2, /* branch_cost */
1245 4 /* memory_latency */
1248 COSTS_N_INSNS (4), /* fp_add */
1249 COSTS_N_INSNS (4), /* fp_mult_sf */
1250 COSTS_N_INSNS (5), /* fp_mult_df */
1251 COSTS_N_INSNS (17), /* fp_div_sf */
1252 COSTS_N_INSNS (32), /* fp_div_df */
1253 COSTS_N_INSNS (5), /* int_mult_si */
1254 COSTS_N_INSNS (5), /* int_mult_di */
1255 COSTS_N_INSNS (41), /* int_div_si */
1256 COSTS_N_INSNS (41), /* int_div_di */
1257 1, /* branch_cost */
1258 4 /* memory_latency */
1261 COSTS_N_INSNS (4), /* fp_add */
1262 COSTS_N_INSNS (4), /* fp_mult_sf */
1263 COSTS_N_INSNS (5), /* fp_mult_df */
1264 COSTS_N_INSNS (17), /* fp_div_sf */
1265 COSTS_N_INSNS (32), /* fp_div_df */
1266 COSTS_N_INSNS (5), /* int_mult_si */
1267 COSTS_N_INSNS (5), /* int_mult_di */
1268 COSTS_N_INSNS (41), /* int_div_si */
1269 COSTS_N_INSNS (41), /* int_div_di */
1270 1, /* branch_cost */
1271 4 /* memory_latency */
1275 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1276 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1278 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1279 static machine_mode
mips_get_reg_raw_mode (int regno
);
1281 struct mips16_flip_traits
: default_hashmap_traits
1283 static hashval_t
hash (const char *s
) { return htab_hash_string (s
); }
1285 equal_keys (const char *a
, const char *b
)
1287 return !strcmp (a
, b
);
1291 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1292 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1293 static GTY (()) hash_map
<const char *, bool, mips16_flip_traits
> *
1296 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1297 mode, false if it should next add an attribute for the opposite mode. */
1298 static GTY(()) bool mips16_flipper
;
1300 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1301 for -mflip-mips16. Return true if it should use "mips16" and false if
1302 it should use "nomips16". */
1305 mflip_mips16_use_mips16_p (tree decl
)
1308 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1310 /* Use the opposite of the command-line setting for anonymous decls. */
1311 if (!DECL_NAME (decl
))
1312 return !base_is_mips16
;
1314 if (!mflip_mips16_htab
)
1316 = hash_map
<const char *, bool, mips16_flip_traits
>::create_ggc (37);
1318 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1321 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1324 mips16_flipper
= !mips16_flipper
;
1325 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1330 /* Predicates to test for presence of "near" and "far"/"long_call"
1331 attributes on the given TYPE. */
1334 mips_near_type_p (const_tree type
)
1336 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1340 mips_far_type_p (const_tree type
)
1342 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1343 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1347 /* Check if the interrupt attribute is set for a function. */
1350 mips_interrupt_type_p (tree type
)
1352 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1355 /* Check if the attribute to use shadow register set is set for a function. */
1358 mips_use_shadow_register_set_p (tree type
)
1360 return lookup_attribute ("use_shadow_register_set",
1361 TYPE_ATTRIBUTES (type
)) != NULL
;
1364 /* Check if the attribute to keep interrupts masked is set for a function. */
1367 mips_keep_interrupts_masked_p (tree type
)
1369 return lookup_attribute ("keep_interrupts_masked",
1370 TYPE_ATTRIBUTES (type
)) != NULL
;
1373 /* Check if the attribute to use debug exception return is set for
1377 mips_use_debug_exception_return_p (tree type
)
1379 return lookup_attribute ("use_debug_exception_return",
1380 TYPE_ATTRIBUTES (type
)) != NULL
;
1383 /* Return the set of compression modes that are explicitly required
1384 by the attributes in ATTRIBUTES. */
1387 mips_get_compress_on_flags (tree attributes
)
1389 unsigned int flags
= 0;
1391 if (lookup_attribute ("mips16", attributes
) != NULL
)
1392 flags
|= MASK_MIPS16
;
1394 if (lookup_attribute ("micromips", attributes
) != NULL
)
1395 flags
|= MASK_MICROMIPS
;
1400 /* Return the set of compression modes that are explicitly forbidden
1401 by the attributes in ATTRIBUTES. */
1404 mips_get_compress_off_flags (tree attributes
)
1406 unsigned int flags
= 0;
1408 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1409 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1411 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1412 flags
|= MASK_MIPS16
;
1414 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1415 flags
|= MASK_MICROMIPS
;
1420 /* Return the compression mode that should be used for function DECL.
1421 Return the ambient setting if DECL is null. */
1424 mips_get_compress_mode (tree decl
)
1426 unsigned int flags
, force_on
;
1428 flags
= mips_base_compression_flags
;
1431 /* Nested functions must use the same frame pointer as their
1432 parent and must therefore use the same ISA mode. */
1433 tree parent
= decl_function_context (decl
);
1436 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1439 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1444 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1448 mips_get_compress_on_name (unsigned int flags
)
1450 if (flags
== MASK_MIPS16
)
1455 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1459 mips_get_compress_off_name (unsigned int flags
)
1461 if (flags
== MASK_MIPS16
)
1463 if (flags
== MASK_MICROMIPS
)
1464 return "nomicromips";
1465 return "nocompression";
1468 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1471 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1473 /* Disallow mixed near/far attributes. */
1474 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1476 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1481 /* Implement TARGET_INSERT_ATTRIBUTES. */
1484 mips_insert_attributes (tree decl
, tree
*attributes
)
1487 unsigned int compression_flags
, nocompression_flags
;
1489 /* Check for "mips16" and "nomips16" attributes. */
1490 compression_flags
= mips_get_compress_on_flags (*attributes
);
1491 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1493 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1495 if (nocompression_flags
)
1496 error ("%qs attribute only applies to functions",
1497 mips_get_compress_off_name (nocompression_flags
));
1499 if (compression_flags
)
1500 error ("%qs attribute only applies to functions",
1501 mips_get_compress_on_name (nocompression_flags
));
1505 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1506 nocompression_flags
|=
1507 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1509 if (compression_flags
&& nocompression_flags
)
1510 error ("%qE cannot have both %qs and %qs attributes",
1511 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1512 mips_get_compress_off_name (nocompression_flags
));
1514 if (compression_flags
& MASK_MIPS16
1515 && compression_flags
& MASK_MICROMIPS
)
1516 error ("%qE cannot have both %qs and %qs attributes",
1517 DECL_NAME (decl
), "mips16", "micromips");
1519 if (TARGET_FLIP_MIPS16
1520 && !DECL_ARTIFICIAL (decl
)
1521 && compression_flags
== 0
1522 && nocompression_flags
== 0)
1524 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1525 "mips16" attribute, arbitrarily pick one. We must pick the same
1526 setting for duplicate declarations of a function. */
1527 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1528 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1529 name
= "nomicromips";
1530 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1535 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1538 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1542 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1543 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1545 error ("%qE redeclared with conflicting %qs attributes",
1546 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1548 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1549 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1551 error ("%qE redeclared with conflicting %qs attributes",
1552 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1554 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1555 DECL_ATTRIBUTES (newdecl
));
1558 /* Implement TARGET_CAN_INLINE_P. */
1561 mips_can_inline_p (tree caller
, tree callee
)
1563 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1565 return default_target_can_inline_p (caller
, callee
);
1568 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1569 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1572 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1574 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1576 *base_ptr
= XEXP (x
, 0);
1577 *offset_ptr
= INTVAL (XEXP (x
, 1));
1586 static unsigned int mips_build_integer (struct mips_integer_op
*,
1587 unsigned HOST_WIDE_INT
);
1589 /* A subroutine of mips_build_integer, with the same interface.
1590 Assume that the final action in the sequence should be a left shift. */
1593 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1595 unsigned int i
, shift
;
1597 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1598 since signed numbers are easier to load than unsigned ones. */
1600 while ((value
& 1) == 0)
1601 value
/= 2, shift
++;
1603 i
= mips_build_integer (codes
, value
);
1604 codes
[i
].code
= ASHIFT
;
1605 codes
[i
].value
= shift
;
1609 /* As for mips_build_shift, but assume that the final action will be
1610 an IOR or PLUS operation. */
1613 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1615 unsigned HOST_WIDE_INT high
;
1618 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1619 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1621 /* The constant is too complex to load with a simple LUI/ORI pair,
1622 so we want to give the recursive call as many trailing zeros as
1623 possible. In this case, we know bit 16 is set and that the
1624 low 16 bits form a negative number. If we subtract that number
1625 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1626 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1627 codes
[i
].code
= PLUS
;
1628 codes
[i
].value
= CONST_LOW_PART (value
);
1632 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1633 bits gives a value with at least 17 trailing zeros. */
1634 i
= mips_build_integer (codes
, high
);
1635 codes
[i
].code
= IOR
;
1636 codes
[i
].value
= value
& 0xffff;
1641 /* Fill CODES with a sequence of rtl operations to load VALUE.
1642 Return the number of operations needed. */
1645 mips_build_integer (struct mips_integer_op
*codes
,
1646 unsigned HOST_WIDE_INT value
)
1648 if (SMALL_OPERAND (value
)
1649 || SMALL_OPERAND_UNSIGNED (value
)
1650 || LUI_OPERAND (value
))
1652 /* The value can be loaded with a single instruction. */
1653 codes
[0].code
= UNKNOWN
;
1654 codes
[0].value
= value
;
1657 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1659 /* Either the constant is a simple LUI/ORI combination or its
1660 lowest bit is set. We don't want to shift in this case. */
1661 return mips_build_lower (codes
, value
);
1663 else if ((value
& 0xffff) == 0)
1665 /* The constant will need at least three actions. The lowest
1666 16 bits are clear, so the final action will be a shift. */
1667 return mips_build_shift (codes
, value
);
1671 /* The final action could be a shift, add or inclusive OR.
1672 Rather than use a complex condition to select the best
1673 approach, try both mips_build_shift and mips_build_lower
1674 and pick the one that gives the shortest sequence.
1675 Note that this case is only used once per constant. */
1676 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1677 unsigned int cost
, alt_cost
;
1679 cost
= mips_build_shift (codes
, value
);
1680 alt_cost
= mips_build_lower (alt_codes
, value
);
1681 if (alt_cost
< cost
)
1683 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1690 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1693 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1695 return mips_const_insns (x
) > 0;
1698 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1701 mips16_stub_function (const char *name
)
1705 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1706 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1710 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1711 support function. */
1714 mips16_stub_call_address (mips_one_only_stub
*stub
)
1716 rtx fn
= mips16_stub_function (stub
->get_name ());
1717 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1718 if (!call_insn_operand (fn
, VOIDmode
))
1719 fn
= force_reg (Pmode
, fn
);
1723 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1725 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1727 virtual const char *get_name ();
1728 virtual void output_body ();
1732 mips16_rdhwr_one_only_stub::get_name ()
1734 return "__mips16_rdhwr";
1738 mips16_rdhwr_one_only_stub::output_body ()
1740 fprintf (asm_out_file
,
1742 "\t.set\tmips32r2\n"
1743 "\t.set\tnoreorder\n"
1749 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1750 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1752 virtual const char *get_name ();
1753 virtual void output_body ();
1757 mips16_get_fcsr_one_only_stub::get_name ()
1759 return "__mips16_get_fcsr";
1763 mips16_get_fcsr_one_only_stub::output_body ()
1765 fprintf (asm_out_file
,
1767 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1770 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1771 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1773 virtual const char *get_name ();
1774 virtual void output_body ();
1778 mips16_set_fcsr_one_only_stub::get_name ()
1780 return "__mips16_set_fcsr";
1784 mips16_set_fcsr_one_only_stub::output_body ()
1786 fprintf (asm_out_file
,
1788 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1791 /* Return true if symbols of type TYPE require a GOT access. */
1794 mips_got_symbol_type_p (enum mips_symbol_type type
)
1798 case SYMBOL_GOT_PAGE_OFST
:
1799 case SYMBOL_GOT_DISP
:
1807 /* Return true if X is a thread-local symbol. */
1810 mips_tls_symbol_p (rtx x
)
1812 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1815 /* Return true if SYMBOL_REF X is associated with a global symbol
1816 (in the STB_GLOBAL sense). */
1819 mips_global_symbol_p (const_rtx x
)
1821 const_tree decl
= SYMBOL_REF_DECL (x
);
1824 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1826 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1827 or weak symbols. Relocations in the object file will be against
1828 the target symbol, so it's that symbol's binding that matters here. */
1829 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1832 /* Return true if function X is a libgcc MIPS16 stub function. */
1835 mips16_stub_function_p (const_rtx x
)
1837 return (GET_CODE (x
) == SYMBOL_REF
1838 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1841 /* Return true if function X is a locally-defined and locally-binding
1845 mips16_local_function_p (const_rtx x
)
1847 return (GET_CODE (x
) == SYMBOL_REF
1848 && SYMBOL_REF_LOCAL_P (x
)
1849 && !SYMBOL_REF_EXTERNAL_P (x
)
1850 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1853 /* Return true if SYMBOL_REF X binds locally. */
1856 mips_symbol_binds_local_p (const_rtx x
)
1858 return (SYMBOL_REF_DECL (x
)
1859 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1860 : SYMBOL_REF_LOCAL_P (x
));
1863 /* Return true if rtx constants of mode MODE should be put into a small
1867 mips_rtx_constant_in_small_data_p (machine_mode mode
)
1869 return (!TARGET_EMBEDDED_DATA
1870 && TARGET_LOCAL_SDATA
1871 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1874 /* Return true if X should not be moved directly into register $25.
1875 We need this because many versions of GAS will treat "la $25,foo" as
1876 part of a call sequence and so allow a global "foo" to be lazily bound. */
1879 mips_dangerous_for_la25_p (rtx x
)
1881 return (!TARGET_EXPLICIT_RELOCS
1883 && GET_CODE (x
) == SYMBOL_REF
1884 && mips_global_symbol_p (x
));
1887 /* Return true if calls to X might need $25 to be valid on entry. */
1890 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1892 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1895 /* MIPS16 stub functions are guaranteed not to use $25. */
1896 if (mips16_stub_function_p (x
))
1899 if (GET_CODE (x
) == SYMBOL_REF
)
1901 /* If PLTs and copy relocations are available, the static linker
1902 will make sure that $25 is valid on entry to the target function. */
1903 if (TARGET_ABICALLS_PIC0
)
1906 /* Locally-defined functions use absolute accesses to set up
1907 the global pointer. */
1908 if (TARGET_ABSOLUTE_ABICALLS
1909 && mips_symbol_binds_local_p (x
)
1910 && !SYMBOL_REF_EXTERNAL_P (x
))
1917 /* Return the method that should be used to access SYMBOL_REF or
1918 LABEL_REF X in context CONTEXT. */
1920 static enum mips_symbol_type
1921 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1924 return SYMBOL_GOT_DISP
;
1926 if (GET_CODE (x
) == LABEL_REF
)
1928 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1929 code and if we know that the label is in the current function's
1930 text section. LABEL_REFs are used for jump tables as well as
1931 text labels, so we must check whether jump tables live in the
1933 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1934 && !LABEL_REF_NONLOCAL_P (x
))
1935 return SYMBOL_PC_RELATIVE
;
1937 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1938 return SYMBOL_GOT_PAGE_OFST
;
1940 return SYMBOL_ABSOLUTE
;
1943 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1945 if (SYMBOL_REF_TLS_MODEL (x
))
1948 if (CONSTANT_POOL_ADDRESS_P (x
))
1950 if (TARGET_MIPS16_TEXT_LOADS
)
1951 return SYMBOL_PC_RELATIVE
;
1953 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1954 return SYMBOL_PC_RELATIVE
;
1956 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1957 return SYMBOL_GP_RELATIVE
;
1960 /* Do not use small-data accesses for weak symbols; they may end up
1962 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1963 return SYMBOL_GP_RELATIVE
;
1965 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1967 if (TARGET_ABICALLS_PIC2
1968 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1970 /* There are three cases to consider:
1972 - o32 PIC (either with or without explicit relocs)
1973 - n32/n64 PIC without explicit relocs
1974 - n32/n64 PIC with explicit relocs
1976 In the first case, both local and global accesses will use an
1977 R_MIPS_GOT16 relocation. We must correctly predict which of
1978 the two semantics (local or global) the assembler and linker
1979 will apply. The choice depends on the symbol's binding rather
1980 than its visibility.
1982 In the second case, the assembler will not use R_MIPS_GOT16
1983 relocations, but it chooses between local and global accesses
1984 in the same way as for o32 PIC.
1986 In the third case we have more freedom since both forms of
1987 access will work for any kind of symbol. However, there seems
1988 little point in doing things differently. */
1989 if (mips_global_symbol_p (x
))
1990 return SYMBOL_GOT_DISP
;
1992 return SYMBOL_GOT_PAGE_OFST
;
1995 return SYMBOL_ABSOLUTE
;
1998 /* Classify the base of symbolic expression X, given that X appears in
2001 static enum mips_symbol_type
2002 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
2006 split_const (x
, &x
, &offset
);
2007 if (UNSPEC_ADDRESS_P (x
))
2008 return UNSPEC_ADDRESS_TYPE (x
);
2010 return mips_classify_symbol (x
, context
);
2013 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
2014 is the alignment in bytes of SYMBOL_REF X. */
2017 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
2019 HOST_WIDE_INT align
;
2021 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
2022 return IN_RANGE (offset
, 0, align
- 1);
2025 /* Return true if X is a symbolic constant that can be used in context
2026 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2029 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
2030 enum mips_symbol_type
*symbol_type
)
2034 split_const (x
, &x
, &offset
);
2035 if (UNSPEC_ADDRESS_P (x
))
2037 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2038 x
= UNSPEC_ADDRESS (x
);
2040 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2042 *symbol_type
= mips_classify_symbol (x
, context
);
2043 if (*symbol_type
== SYMBOL_TLS
)
2049 if (offset
== const0_rtx
)
2052 /* Check whether a nonzero offset is valid for the underlying
2054 switch (*symbol_type
)
2056 case SYMBOL_ABSOLUTE
:
2057 case SYMBOL_64_HIGH
:
2060 /* If the target has 64-bit pointers and the object file only
2061 supports 32-bit symbols, the values of those symbols will be
2062 sign-extended. In this case we can't allow an arbitrary offset
2063 in case the 32-bit value X + OFFSET has a different sign from X. */
2064 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2065 return offset_within_block_p (x
, INTVAL (offset
));
2067 /* In other cases the relocations can handle any offset. */
2070 case SYMBOL_PC_RELATIVE
:
2071 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2072 In this case, we no longer have access to the underlying constant,
2073 but the original symbol-based access was known to be valid. */
2074 if (GET_CODE (x
) == LABEL_REF
)
2079 case SYMBOL_GP_RELATIVE
:
2080 /* Make sure that the offset refers to something within the
2081 same object block. This should guarantee that the final
2082 PC- or GP-relative offset is within the 16-bit limit. */
2083 return offset_within_block_p (x
, INTVAL (offset
));
2085 case SYMBOL_GOT_PAGE_OFST
:
2086 case SYMBOL_GOTOFF_PAGE
:
2087 /* If the symbol is global, the GOT entry will contain the symbol's
2088 address, and we will apply a 16-bit offset after loading it.
2089 If the symbol is local, the linker should provide enough local
2090 GOT entries for a 16-bit offset, but larger offsets may lead
2092 return SMALL_INT (offset
);
2096 /* There is no carry between the HI and LO REL relocations, so the
2097 offset is only valid if we know it won't lead to such a carry. */
2098 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2100 case SYMBOL_GOT_DISP
:
2101 case SYMBOL_GOTOFF_DISP
:
2102 case SYMBOL_GOTOFF_CALL
:
2103 case SYMBOL_GOTOFF_LOADGP
:
2106 case SYMBOL_GOTTPREL
:
2114 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2115 single instruction. We rely on the fact that, in the worst case,
2116 all instructions involved in a MIPS16 address calculation are usually
2120 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2122 if (mips_use_pcrel_pool_p
[(int) type
])
2124 if (mode
== MAX_MACHINE_MODE
)
2125 /* LEAs will be converted into constant-pool references by
2127 type
= SYMBOL_PC_RELATIVE
;
2129 /* The constant must be loaded and then dereferenced. */
2135 case SYMBOL_ABSOLUTE
:
2136 /* When using 64-bit symbols, we need 5 preparatory instructions,
2139 lui $at,%highest(symbol)
2140 daddiu $at,$at,%higher(symbol)
2142 daddiu $at,$at,%hi(symbol)
2145 The final address is then $at + %lo(symbol). With 32-bit
2146 symbols we just need a preparatory LUI for normal mode and
2147 a preparatory LI and SLL for MIPS16. */
2148 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2150 case SYMBOL_GP_RELATIVE
:
2151 /* Treat GP-relative accesses as taking a single instruction on
2152 MIPS16 too; the copy of $gp can often be shared. */
2155 case SYMBOL_PC_RELATIVE
:
2156 /* PC-relative constants can be only be used with ADDIUPC,
2157 DADDIUPC, LWPC and LDPC. */
2158 if (mode
== MAX_MACHINE_MODE
2159 || GET_MODE_SIZE (mode
) == 4
2160 || GET_MODE_SIZE (mode
) == 8)
2163 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2166 case SYMBOL_GOT_DISP
:
2167 /* The constant will have to be loaded from the GOT before it
2168 is used in an address. */
2169 if (mode
!= MAX_MACHINE_MODE
)
2174 case SYMBOL_GOT_PAGE_OFST
:
2175 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2176 local/global classification is accurate. The worst cases are:
2178 (1) For local symbols when generating o32 or o64 code. The assembler
2184 ...and the final address will be $at + %lo(symbol).
2186 (2) For global symbols when -mxgot. The assembler will use:
2188 lui $at,%got_hi(symbol)
2191 ...and the final address will be $at + %got_lo(symbol). */
2194 case SYMBOL_GOTOFF_PAGE
:
2195 case SYMBOL_GOTOFF_DISP
:
2196 case SYMBOL_GOTOFF_CALL
:
2197 case SYMBOL_GOTOFF_LOADGP
:
2198 case SYMBOL_64_HIGH
:
2204 case SYMBOL_GOTTPREL
:
2207 /* A 16-bit constant formed by a single relocation, or a 32-bit
2208 constant formed from a high 16-bit relocation and a low 16-bit
2209 relocation. Use mips_split_p to determine which. 32-bit
2210 constants need an "lui; addiu" sequence for normal mode and
2211 an "li; sll; addiu" sequence for MIPS16 mode. */
2212 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2215 /* We don't treat a bare TLS symbol as a constant. */
2221 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2222 to load symbols of type TYPE into a register. Return 0 if the given
2223 type of symbol cannot be used as an immediate operand.
2225 Otherwise, return the number of instructions needed to load or store
2226 values of mode MODE to or from addresses of type TYPE. Return 0 if
2227 the given type of symbol is not valid in addresses.
2229 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2232 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2234 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2237 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2240 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2242 enum mips_symbol_type type
;
2245 /* There is no assembler syntax for expressing an address-sized
2247 if (GET_CODE (x
) == HIGH
)
2250 /* As an optimization, reject constants that mips_legitimize_move
2253 Suppose we have a multi-instruction sequence that loads constant C
2254 into register R. If R does not get allocated a hard register, and
2255 R is used in an operand that allows both registers and memory
2256 references, reload will consider forcing C into memory and using
2257 one of the instruction's memory alternatives. Returning false
2258 here will force it to use an input reload instead. */
2259 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2262 split_const (x
, &base
, &offset
);
2263 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2265 /* See whether we explicitly want these symbols in the pool. */
2266 if (mips_use_pcrel_pool_p
[(int) type
])
2269 /* The same optimization as for CONST_INT. */
2270 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2273 /* If MIPS16 constant pools live in the text section, they should
2274 not refer to anything that might need run-time relocation. */
2275 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2279 /* TLS symbols must be computed by mips_legitimize_move. */
2280 if (tls_referenced_p (x
))
2286 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2287 constants when we're using a per-function constant pool. */
2290 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2291 const_rtx x ATTRIBUTE_UNUSED
)
2293 return !TARGET_MIPS16_PCREL_LOADS
;
2296 /* Return true if register REGNO is a valid base register for mode MODE.
2297 STRICT_P is true if REG_OK_STRICT is in effect. */
2300 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2303 if (!HARD_REGISTER_NUM_P (regno
))
2307 regno
= reg_renumber
[regno
];
2310 /* These fake registers will be eliminated to either the stack or
2311 hard frame pointer, both of which are usually valid base registers.
2312 Reload deals with the cases where the eliminated form isn't valid. */
2313 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2316 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2317 values, nothing smaller. */
2318 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2319 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2321 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2324 /* Return true if X is a valid base register for mode MODE.
2325 STRICT_P is true if REG_OK_STRICT is in effect. */
2328 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2330 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2334 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2337 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2338 can address a value of mode MODE. */
2341 mips_valid_offset_p (rtx x
, machine_mode mode
)
2343 /* Check that X is a signed 16-bit number. */
2344 if (!const_arith_operand (x
, Pmode
))
2347 /* We may need to split multiword moves, so make sure that every word
2349 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2350 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2356 /* Return true if a LO_SUM can address a value of mode MODE when the
2357 LO_SUM symbol has type SYMBOL_TYPE. */
2360 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2362 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2364 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2367 /* Check that there is a known low-part relocation. */
2368 if (mips_lo_relocs
[symbol_type
] == NULL
)
2371 /* We may need to split multiword moves, so make sure that each word
2372 can be accessed without inducing a carry. This is mainly needed
2373 for o64, which has historically only guaranteed 64-bit alignment
2374 for 128-bit types. */
2375 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2376 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2382 /* Return true if X is a valid address for machine mode MODE. If it is,
2383 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2387 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2388 machine_mode mode
, bool strict_p
)
2390 switch (GET_CODE (x
))
2394 info
->type
= ADDRESS_REG
;
2396 info
->offset
= const0_rtx
;
2397 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2400 info
->type
= ADDRESS_REG
;
2401 info
->reg
= XEXP (x
, 0);
2402 info
->offset
= XEXP (x
, 1);
2403 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2404 && mips_valid_offset_p (info
->offset
, mode
));
2407 info
->type
= ADDRESS_LO_SUM
;
2408 info
->reg
= XEXP (x
, 0);
2409 info
->offset
= XEXP (x
, 1);
2410 /* We have to trust the creator of the LO_SUM to do something vaguely
2411 sane. Target-independent code that creates a LO_SUM should also
2412 create and verify the matching HIGH. Target-independent code that
2413 adds an offset to a LO_SUM must prove that the offset will not
2414 induce a carry. Failure to do either of these things would be
2415 a bug, and we are not required to check for it here. The MIPS
2416 backend itself should only create LO_SUMs for valid symbolic
2417 constants, with the high part being either a HIGH or a copy
2420 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2421 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2422 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2425 /* Small-integer addresses don't occur very often, but they
2426 are legitimate if $0 is a valid base register. */
2427 info
->type
= ADDRESS_CONST_INT
;
2428 return !TARGET_MIPS16
&& SMALL_INT (x
);
2433 info
->type
= ADDRESS_SYMBOLIC
;
2434 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2436 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2437 && !mips_split_p
[info
->symbol_type
]);
2444 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2447 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2449 struct mips_address_info addr
;
2451 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2454 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2457 mips_stack_address_p (rtx x
, machine_mode mode
)
2459 struct mips_address_info addr
;
2461 return (mips_classify_address (&addr
, x
, mode
, false)
2462 && addr
.type
== ADDRESS_REG
2463 && addr
.reg
== stack_pointer_rtx
);
2466 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2467 address instruction. Note that such addresses are not considered
2468 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2469 is so restricted. */
2472 mips_lwxs_address_p (rtx addr
)
2475 && GET_CODE (addr
) == PLUS
2476 && REG_P (XEXP (addr
, 1)))
2478 rtx offset
= XEXP (addr
, 0);
2479 if (GET_CODE (offset
) == MULT
2480 && REG_P (XEXP (offset
, 0))
2481 && CONST_INT_P (XEXP (offset
, 1))
2482 && INTVAL (XEXP (offset
, 1)) == 4)
2488 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2489 indexed address instruction. Note that such addresses are
2490 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2491 sense, because their use is so restricted. */
2494 mips_lx_address_p (rtx addr
, machine_mode mode
)
2496 if (GET_CODE (addr
) != PLUS
2497 || !REG_P (XEXP (addr
, 0))
2498 || !REG_P (XEXP (addr
, 1)))
2500 if (ISA_HAS_LBX
&& mode
== QImode
)
2502 if (ISA_HAS_LHX
&& mode
== HImode
)
2504 if (ISA_HAS_LWX
&& mode
== SImode
)
2506 if (ISA_HAS_LDX
&& mode
== DImode
)
2511 /* Return true if a value at OFFSET bytes from base register BASE can be
2512 accessed using an unextended MIPS16 instruction. MODE is the mode of
2515 Usually the offset in an unextended instruction is a 5-bit field.
2516 The offset is unsigned and shifted left once for LH and SH, twice
2517 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2518 an 8-bit immediate field that's shifted left twice. */
2521 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2522 unsigned HOST_WIDE_INT offset
)
2524 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2526 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2527 return offset
< 256U * GET_MODE_SIZE (mode
);
2528 return offset
< 32U * GET_MODE_SIZE (mode
);
2533 /* Return the number of instructions needed to load or store a value
2534 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2535 length of one instruction. Return 0 if X isn't valid for MODE.
2536 Assume that multiword moves may need to be split into word moves
2537 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2541 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2543 struct mips_address_info addr
;
2546 /* BLKmode is used for single unaligned loads and stores and should
2547 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2548 meaningless, so we have to single it out as a special case one way
2550 if (mode
!= BLKmode
&& might_split_p
)
2551 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2555 if (mips_classify_address (&addr
, x
, mode
, false))
2560 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2561 UINTVAL (addr
.offset
)))
2565 case ADDRESS_LO_SUM
:
2566 return TARGET_MIPS16
? factor
* 2 : factor
;
2568 case ADDRESS_CONST_INT
:
2571 case ADDRESS_SYMBOLIC
:
2572 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2577 /* Return true if X fits within an unsigned field of BITS bits that is
2578 shifted left SHIFT bits before being used. */
2581 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2583 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2586 /* Return true if X fits within a signed field of BITS bits that is
2587 shifted left SHIFT bits before being used. */
2590 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2592 x
+= 1 << (bits
+ shift
- 1);
2593 return mips_unsigned_immediate_p (x
, bits
, shift
);
2596 /* Return true if X is legitimate for accessing values of mode MODE,
2597 if it is based on a MIPS16 register, and if the offset satisfies
2598 OFFSET_PREDICATE. */
2601 m16_based_address_p (rtx x
, machine_mode mode
,
2602 insn_operand_predicate_fn offset_predicate
)
2604 struct mips_address_info addr
;
2606 return (mips_classify_address (&addr
, x
, mode
, false)
2607 && addr
.type
== ADDRESS_REG
2608 && M16_REG_P (REGNO (addr
.reg
))
2609 && offset_predicate (addr
.offset
, mode
));
2612 /* Return true if X is a legitimate address that conforms to the requirements
2613 for a microMIPS LWSP or SWSP insn. */
2616 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2618 struct mips_address_info addr
;
2620 return (mips_classify_address (&addr
, x
, mode
, false)
2621 && addr
.type
== ADDRESS_REG
2622 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2623 && uw5_operand (addr
.offset
, mode
));
2626 /* Return true if X is a legitimate address with a 12-bit offset.
2627 MODE is the mode of the value being accessed. */
2630 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2632 struct mips_address_info addr
;
2634 return (mips_classify_address (&addr
, x
, mode
, false)
2635 && addr
.type
== ADDRESS_REG
2636 && CONST_INT_P (addr
.offset
)
2637 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2640 /* Return true if X is a legitimate address with a 9-bit offset.
2641 MODE is the mode of the value being accessed. */
2644 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2646 struct mips_address_info addr
;
2648 return (mips_classify_address (&addr
, x
, mode
, false)
2649 && addr
.type
== ADDRESS_REG
2650 && CONST_INT_P (addr
.offset
)
2651 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2654 /* Return the number of instructions needed to load constant X,
2655 assuming that BASE_INSN_LENGTH is the length of one instruction.
2656 Return 0 if X isn't a valid constant. */
2659 mips_const_insns (rtx x
)
2661 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2662 enum mips_symbol_type symbol_type
;
2665 switch (GET_CODE (x
))
2668 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2670 || !mips_split_p
[symbol_type
])
2673 /* This is simply an LUI for normal mode. It is an extended
2674 LI followed by an extended SLL for MIPS16. */
2675 return TARGET_MIPS16
? 4 : 1;
2679 /* Unsigned 8-bit constants can be loaded using an unextended
2680 LI instruction. Unsigned 16-bit constants can be loaded
2681 using an extended LI. Negative constants must be loaded
2682 using LI and then negated. */
2683 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2684 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2685 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2686 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2689 return mips_build_integer (codes
, INTVAL (x
));
2693 /* Allow zeros for normal mode, where we can use $0. */
2694 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2700 /* See if we can refer to X directly. */
2701 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2702 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2704 /* Otherwise try splitting the constant into a base and offset.
2705 If the offset is a 16-bit value, we can load the base address
2706 into a register and then use (D)ADDIU to add in the offset.
2707 If the offset is larger, we can load the base and offset
2708 into separate registers and add them together with (D)ADDU.
2709 However, the latter is only possible before reload; during
2710 and after reload, we must have the option of forcing the
2711 constant into the pool instead. */
2712 split_const (x
, &x
, &offset
);
2715 int n
= mips_const_insns (x
);
2718 if (SMALL_INT (offset
))
2720 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2721 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2728 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2736 /* X is a doubleword constant that can be handled by splitting it into
2737 two words and loading each word separately. Return the number of
2738 instructions required to do this, assuming that BASE_INSN_LENGTH
2739 is the length of one instruction. */
2742 mips_split_const_insns (rtx x
)
2744 unsigned int low
, high
;
2746 low
= mips_const_insns (mips_subword (x
, false));
2747 high
= mips_const_insns (mips_subword (x
, true));
2748 gcc_assert (low
> 0 && high
> 0);
2752 /* Return the number of instructions needed to implement INSN,
2753 given that it loads from or stores to MEM. Assume that
2754 BASE_INSN_LENGTH is the length of one instruction. */
2757 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2763 gcc_assert (MEM_P (mem
));
2764 mode
= GET_MODE (mem
);
2766 /* Try to prove that INSN does not need to be split. */
2767 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2770 set
= single_set (insn
);
2771 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2772 might_split_p
= false;
2775 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2778 /* Return the number of instructions needed for an integer division,
2779 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2782 mips_idiv_insns (void)
2787 if (TARGET_CHECK_ZERO_DIV
)
2789 if (GENERATE_DIVIDE_TRAPS
)
2795 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2800 /* Emit a move from SRC to DEST. Assume that the move expanders can
2801 handle all moves if !can_create_pseudo_p (). The distinction is
2802 important because, unlike emit_move_insn, the move expanders know
2803 how to force Pmode objects into the constant pool even when the
2804 constant pool address is not itself legitimate. */
2807 mips_emit_move (rtx dest
, rtx src
)
2809 return (can_create_pseudo_p ()
2810 ? emit_move_insn (dest
, src
)
2811 : emit_move_insn_1 (dest
, src
));
2814 /* Emit a move from SRC to DEST, splitting compound moves into individual
2815 instructions. SPLIT_TYPE is the type of split to perform. */
2818 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2820 if (mips_split_move_p (dest
, src
, split_type
))
2821 mips_split_move (dest
, src
, split_type
);
2823 mips_emit_move (dest
, src
);
2826 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2829 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2831 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2834 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2835 Return that new register. */
2838 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
2842 reg
= gen_reg_rtx (mode
);
2843 mips_emit_unary (code
, reg
, op0
);
2847 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2850 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2852 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
2856 /* Compute (CODE OP0 OP1) and store the result in a new register
2857 of mode MODE. Return that new register. */
2860 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2864 reg
= gen_reg_rtx (mode
);
2865 mips_emit_binary (code
, reg
, op0
, op1
);
2869 /* Copy VALUE to a register and return that register. If new pseudos
2870 are allowed, copy it into a new register, otherwise use DEST. */
2873 mips_force_temporary (rtx dest
, rtx value
)
2875 if (can_create_pseudo_p ())
2876 return force_reg (Pmode
, value
);
2879 mips_emit_move (dest
, value
);
2884 /* Emit a call sequence with call pattern PATTERN and return the call
2885 instruction itself (which is not necessarily the last instruction
2886 emitted). ORIG_ADDR is the original, unlegitimized address,
2887 ADDR is the legitimized form, and LAZY_P is true if the call
2888 address is lazily-bound. */
2891 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2896 insn
= emit_call_insn (pattern
);
2898 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2900 /* MIPS16 JALRs only take MIPS16 registers. If the target
2901 function requires $25 to be valid on entry, we must copy it
2902 there separately. The move instruction can be put in the
2903 call's delay slot. */
2904 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2905 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2906 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2910 /* Lazy-binding stubs require $gp to be valid on entry. */
2911 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2915 /* See the comment above load_call<mode> for details. */
2916 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2917 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2918 emit_insn (gen_update_got_version ());
2922 && TARGET_EXPLICIT_RELOCS
2923 && TARGET_CALL_CLOBBERED_GP
)
2925 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
2926 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
2932 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2933 then add CONST_INT OFFSET to the result. */
2936 mips_unspec_address_offset (rtx base
, rtx offset
,
2937 enum mips_symbol_type symbol_type
)
2939 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2940 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2941 if (offset
!= const0_rtx
)
2942 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2943 return gen_rtx_CONST (Pmode
, base
);
2946 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2947 type SYMBOL_TYPE. */
2950 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2954 split_const (address
, &base
, &offset
);
2955 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2958 /* If OP is an UNSPEC address, return the address to which it refers,
2959 otherwise return OP itself. */
2962 mips_strip_unspec_address (rtx op
)
2966 split_const (op
, &base
, &offset
);
2967 if (UNSPEC_ADDRESS_P (base
))
2968 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2972 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2973 high part to BASE and return the result. Just return BASE otherwise.
2974 TEMP is as for mips_force_temporary.
2976 The returned expression can be used as the first operand to a LO_SUM. */
2979 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2980 enum mips_symbol_type symbol_type
)
2982 if (mips_split_p
[symbol_type
])
2984 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2985 addr
= mips_force_temporary (temp
, addr
);
2986 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2991 /* Return an instruction that copies $gp into register REG. We want
2992 GCC to treat the register's value as constant, so that its value
2993 can be rematerialized on demand. */
2996 gen_load_const_gp (rtx reg
)
2998 return PMODE_INSN (gen_load_const_gp
, (reg
));
3001 /* Return a pseudo register that contains the value of $gp throughout
3002 the current function. Such registers are needed by MIPS16 functions,
3003 for which $gp itself is not a valid base register or addition operand. */
3006 mips16_gp_pseudo_reg (void)
3008 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
3012 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
3014 push_topmost_sequence ();
3016 scan
= get_insns ();
3017 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
3018 scan
= NEXT_INSN (scan
);
3020 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
3021 rtx_insn
*insn
= emit_insn_after (set
, scan
);
3022 INSN_LOCATION (insn
) = 0;
3024 pop_topmost_sequence ();
3027 return cfun
->machine
->mips16_gp_pseudo_rtx
;
3030 /* Return a base register that holds pic_offset_table_rtx.
3031 TEMP, if nonnull, is a scratch Pmode base register. */
3034 mips_pic_base_register (rtx temp
)
3037 return pic_offset_table_rtx
;
3039 if (currently_expanding_to_rtl
)
3040 return mips16_gp_pseudo_reg ();
3042 if (can_create_pseudo_p ())
3043 temp
= gen_reg_rtx (Pmode
);
3046 /* The first post-reload split exposes all references to $gp
3047 (both uses and definitions). All references must remain
3048 explicit after that point.
3050 It is safe to introduce uses of $gp at any time, so for
3051 simplicity, we do that before the split too. */
3052 mips_emit_move (temp
, pic_offset_table_rtx
);
3054 emit_insn (gen_load_const_gp (temp
));
3058 /* Return the RHS of a load_call<mode> insn. */
3061 mips_unspec_call (rtx reg
, rtx symbol
)
3065 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3066 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3069 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3070 reference. Return NULL_RTX otherwise. */
3073 mips_strip_unspec_call (rtx src
)
3075 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3076 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3080 /* Create and return a GOT reference of type TYPE for address ADDR.
3081 TEMP, if nonnull, is a scratch Pmode base register. */
3084 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3086 rtx base
, high
, lo_sum_symbol
;
3088 base
= mips_pic_base_register (temp
);
3090 /* If we used the temporary register to load $gp, we can't use
3091 it for the high part as well. */
3092 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3095 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3096 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3098 if (type
== SYMBOL_GOTOFF_CALL
)
3099 return mips_unspec_call (high
, lo_sum_symbol
);
3101 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3104 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3105 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3106 constant in that context and can be split into high and low parts.
3107 If so, and if LOW_OUT is nonnull, emit the high part and store the
3108 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3110 TEMP is as for mips_force_temporary and is used to load the high
3111 part into a register.
3113 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3114 a legitimize SET_SRC for an .md pattern, otherwise the low part
3115 is guaranteed to be a legitimate address for mode MODE. */
3118 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3120 enum mips_symbol_context context
;
3121 enum mips_symbol_type symbol_type
;
3124 context
= (mode
== MAX_MACHINE_MODE
3125 ? SYMBOL_CONTEXT_LEA
3126 : SYMBOL_CONTEXT_MEM
);
3127 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3129 addr
= XEXP (addr
, 0);
3130 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3131 && mips_symbol_insns (symbol_type
, mode
) > 0
3132 && mips_split_hi_p
[symbol_type
])
3135 switch (symbol_type
)
3137 case SYMBOL_GOT_PAGE_OFST
:
3138 /* The high part of a page/ofst pair is loaded from the GOT. */
3139 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3150 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3151 && mips_symbol_insns (symbol_type
, mode
) > 0
3152 && mips_split_p
[symbol_type
])
3155 switch (symbol_type
)
3157 case SYMBOL_GOT_DISP
:
3158 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3159 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3162 case SYMBOL_GP_RELATIVE
:
3163 high
= mips_pic_base_register (temp
);
3164 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3168 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3169 high
= mips_force_temporary (temp
, high
);
3170 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3179 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3180 mips_force_temporary; it is only needed when OFFSET is not a
3184 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3186 if (!SMALL_OPERAND (offset
))
3192 /* Load the full offset into a register so that we can use
3193 an unextended instruction for the address itself. */
3194 high
= GEN_INT (offset
);
3199 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3200 The addition inside the macro CONST_HIGH_PART may cause an
3201 overflow, so we need to force a sign-extension check. */
3202 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3203 offset
= CONST_LOW_PART (offset
);
3205 high
= mips_force_temporary (temp
, high
);
3206 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3208 return plus_constant (Pmode
, reg
, offset
);
3211 /* The __tls_get_attr symbol. */
3212 static GTY(()) rtx mips_tls_symbol
;
3214 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3215 the TLS symbol we are referencing and TYPE is the symbol type to use
3216 (either global dynamic or local dynamic). V0 is an RTX for the
3217 return value location. */
3220 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3224 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3226 if (!mips_tls_symbol
)
3227 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3229 loc
= mips_unspec_address (sym
, type
);
3233 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3235 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3236 const0_rtx
, NULL_RTX
, false);
3237 RTL_CONST_CALL_P (insn
) = 1;
3238 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3239 insn
= get_insns ();
3246 /* Return a pseudo register that contains the current thread pointer. */
3249 mips_expand_thread_pointer (rtx tp
)
3255 if (!mips16_rdhwr_stub
)
3256 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3257 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3258 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3261 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3268 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3271 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3272 its address. The return value will be both a valid address and a valid
3273 SET_SRC (either a REG or a LO_SUM). */
3276 mips_legitimize_tls_address (rtx loc
)
3278 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3279 enum tls_model model
;
3281 model
= SYMBOL_REF_TLS_MODEL (loc
);
3282 /* Only TARGET_ABICALLS code can have more than one module; other
3283 code must be be static and should not use a GOT. All TLS models
3284 reduce to local exec in this situation. */
3285 if (!TARGET_ABICALLS
)
3286 model
= TLS_MODEL_LOCAL_EXEC
;
3290 case TLS_MODEL_GLOBAL_DYNAMIC
:
3291 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3292 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3293 dest
= gen_reg_rtx (Pmode
);
3294 emit_libcall_block (insn
, dest
, v0
, loc
);
3297 case TLS_MODEL_LOCAL_DYNAMIC
:
3298 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3299 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3300 tmp1
= gen_reg_rtx (Pmode
);
3302 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3303 share the LDM result with other LD model accesses. */
3304 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3306 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3308 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3309 if (mips_split_p
[SYMBOL_DTPREL
])
3311 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3312 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3315 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3316 0, 0, OPTAB_DIRECT
);
3319 case TLS_MODEL_INITIAL_EXEC
:
3320 tp
= mips_get_tp ();
3321 tmp1
= gen_reg_rtx (Pmode
);
3322 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3323 if (Pmode
== DImode
)
3324 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3326 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3327 dest
= gen_reg_rtx (Pmode
);
3328 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3331 case TLS_MODEL_LOCAL_EXEC
:
3332 tmp1
= mips_get_tp ();
3333 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3334 if (mips_split_p
[SYMBOL_TPREL
])
3336 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3337 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3340 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3341 0, 0, OPTAB_DIRECT
);
3350 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3354 mips16_expand_get_fcsr (rtx target
)
3356 if (!mips16_get_fcsr_stub
)
3357 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3358 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3359 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3360 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3363 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3366 mips16_expand_set_fcsr (rtx newval
)
3368 if (!mips16_set_fcsr_stub
)
3369 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3370 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3371 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3372 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3375 /* If X is not a valid address for mode MODE, force it into a register. */
3378 mips_force_address (rtx x
, machine_mode mode
)
3380 if (!mips_legitimate_address_p (mode
, x
, false))
3381 x
= force_reg (Pmode
, x
);
3385 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3386 be legitimized in a way that the generic machinery might not expect,
3387 return a new address, otherwise return NULL. MODE is the mode of
3388 the memory being accessed. */
3391 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3395 HOST_WIDE_INT offset
;
3397 if (mips_tls_symbol_p (x
))
3398 return mips_legitimize_tls_address (x
);
3400 /* See if the address can split into a high part and a LO_SUM. */
3401 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3402 return mips_force_address (addr
, mode
);
3404 /* Handle BASE + OFFSET using mips_add_offset. */
3405 mips_split_plus (x
, &base
, &offset
);
3408 if (!mips_valid_base_register_p (base
, mode
, false))
3409 base
= copy_to_mode_reg (Pmode
, base
);
3410 addr
= mips_add_offset (NULL
, base
, offset
);
3411 return mips_force_address (addr
, mode
);
3417 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3420 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3422 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3424 unsigned int i
, num_ops
;
3427 mode
= GET_MODE (dest
);
3428 num_ops
= mips_build_integer (codes
, value
);
3430 /* Apply each binary operation to X. Invariant: X is a legitimate
3431 source operand for a SET pattern. */
3432 x
= GEN_INT (codes
[0].value
);
3433 for (i
= 1; i
< num_ops
; i
++)
3435 if (!can_create_pseudo_p ())
3437 emit_insn (gen_rtx_SET (temp
, x
));
3441 x
= force_reg (mode
, x
);
3442 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3445 emit_insn (gen_rtx_SET (dest
, x
));
3448 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3449 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3453 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3457 /* Split moves of big integers into smaller pieces. */
3458 if (splittable_const_int_operand (src
, mode
))
3460 mips_move_integer (dest
, dest
, INTVAL (src
));
3464 /* Split moves of symbolic constants into high/low pairs. */
3465 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3467 emit_insn (gen_rtx_SET (dest
, src
));
3471 /* Generate the appropriate access sequences for TLS symbols. */
3472 if (mips_tls_symbol_p (src
))
3474 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3478 /* If we have (const (plus symbol offset)), and that expression cannot
3479 be forced into memory, load the symbol first and add in the offset.
3480 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3481 forced into memory, as it usually produces better code. */
3482 split_const (src
, &base
, &offset
);
3483 if (offset
!= const0_rtx
3484 && (targetm
.cannot_force_const_mem (mode
, src
)
3485 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3487 base
= mips_force_temporary (dest
, base
);
3488 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3492 src
= force_const_mem (mode
, src
);
3494 /* When using explicit relocs, constant pool references are sometimes
3495 not legitimate addresses. */
3496 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3497 mips_emit_move (dest
, src
);
3500 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3501 sequence that is valid. */
3504 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3506 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3508 mips_emit_move (dest
, force_reg (mode
, src
));
3512 /* We need to deal with constants that would be legitimate
3513 immediate_operands but aren't legitimate move_operands. */
3514 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3516 mips_legitimize_const_move (mode
, dest
, src
);
3517 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3523 /* Return true if value X in context CONTEXT is a small-data address
3524 that can be rewritten as a LO_SUM. */
3527 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3529 enum mips_symbol_type symbol_type
;
3531 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3532 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3533 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3534 && symbol_type
== SYMBOL_GP_RELATIVE
);
3537 /* Return true if OP refers to small data symbols directly, not through
3538 a LO_SUM. CONTEXT is the context in which X appears. */
3541 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3543 subrtx_var_iterator::array_type array
;
3544 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3548 /* Ignore things like "g" constraints in asms. We make no particular
3549 guarantee about which symbolic constants are acceptable as asm operands
3550 versus which must be forced into a GPR. */
3551 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3552 iter
.skip_subrtxes ();
3555 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3557 iter
.skip_subrtxes ();
3559 else if (mips_rewrite_small_data_p (x
, context
))
3565 /* Return true if OP refers to small data symbols directly, not through
3569 mips_small_data_pattern_p (rtx op
)
3571 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3574 /* Rewrite *LOC so that it refers to small data using explicit
3575 relocations. CONTEXT is the context in which *LOC appears. */
3578 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3580 subrtx_ptr_iterator::array_type array
;
3581 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3586 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3587 iter
.skip_subrtxes ();
3589 else if (mips_rewrite_small_data_p (*loc
, context
))
3591 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3592 iter
.skip_subrtxes ();
3594 else if (GET_CODE (*loc
) == LO_SUM
)
3595 iter
.skip_subrtxes ();
3599 /* Rewrite instruction pattern PATTERN so that it refers to small data
3600 using explicit relocations. */
3603 mips_rewrite_small_data (rtx pattern
)
3605 pattern
= copy_insn (pattern
);
3606 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3610 /* The cost of loading values from the constant pool. It should be
3611 larger than the cost of any constant we want to synthesize inline. */
3612 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3614 /* Return the cost of X when used as an operand to the MIPS16 instruction
3615 that implements CODE. Return -1 if there is no such instruction, or if
3616 X is not a valid immediate operand for it. */
3619 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3626 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3627 other shifts are extended. The shift patterns truncate the shift
3628 count to the right size, so there are no out-of-range values. */
3629 if (IN_RANGE (x
, 1, 8))
3631 return COSTS_N_INSNS (1);
3634 if (IN_RANGE (x
, -128, 127))
3636 if (SMALL_OPERAND (x
))
3637 return COSTS_N_INSNS (1);
3641 /* Like LE, but reject the always-true case. */
3645 /* We add 1 to the immediate and use SLT. */
3648 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3651 if (IN_RANGE (x
, 0, 255))
3653 if (SMALL_OPERAND_UNSIGNED (x
))
3654 return COSTS_N_INSNS (1);
3659 /* Equality comparisons with 0 are cheap. */
3669 /* Return true if there is a non-MIPS16 instruction that implements CODE
3670 and if that instruction accepts X as an immediate operand. */
3673 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3680 /* All shift counts are truncated to a valid constant. */
3685 /* Likewise rotates, if the target supports rotates at all. */
3691 /* These instructions take 16-bit unsigned immediates. */
3692 return SMALL_OPERAND_UNSIGNED (x
);
3697 /* These instructions take 16-bit signed immediates. */
3698 return SMALL_OPERAND (x
);
3704 /* The "immediate" forms of these instructions are really
3705 implemented as comparisons with register 0. */
3710 /* Likewise, meaning that the only valid immediate operand is 1. */
3714 /* We add 1 to the immediate and use SLT. */
3715 return SMALL_OPERAND (x
+ 1);
3718 /* Likewise SLTU, but reject the always-true case. */
3719 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3723 /* The bit position and size are immediate operands. */
3724 return ISA_HAS_EXT_INS
;
3727 /* By default assume that $0 can be used for 0. */
3732 /* Return the cost of binary operation X, given that the instruction
3733 sequence for a word-sized or smaller operation has cost SINGLE_COST
3734 and that the sequence of a double-word operation has cost DOUBLE_COST.
3735 If SPEED is true, optimize for speed otherwise optimize for size. */
3738 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3742 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3747 + set_src_cost (XEXP (x
, 0), speed
)
3748 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3751 /* Return the cost of floating-point multiplications of mode MODE. */
3754 mips_fp_mult_cost (machine_mode mode
)
3756 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3759 /* Return the cost of floating-point divisions of mode MODE. */
3762 mips_fp_div_cost (machine_mode mode
)
3764 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3767 /* Return the cost of sign-extending OP to mode MODE, not including the
3768 cost of OP itself. */
3771 mips_sign_extend_cost (machine_mode mode
, rtx op
)
3774 /* Extended loads are as cheap as unextended ones. */
3777 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3778 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3781 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3782 /* We can use SEB or SEH. */
3783 return COSTS_N_INSNS (1);
3785 /* We need to use a shift left and a shift right. */
3786 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3789 /* Return the cost of zero-extending OP to mode MODE, not including the
3790 cost of OP itself. */
3793 mips_zero_extend_cost (machine_mode mode
, rtx op
)
3796 /* Extended loads are as cheap as unextended ones. */
3799 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3800 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3801 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3803 if (GENERATE_MIPS16E
)
3804 /* We can use ZEB or ZEH. */
3805 return COSTS_N_INSNS (1);
3808 /* We need to load 0xff or 0xffff into a register and use AND. */
3809 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3811 /* We can use ANDI. */
3812 return COSTS_N_INSNS (1);
3815 /* Return the cost of moving between two registers of mode MODE,
3816 assuming that the move will be in pieces of at most UNITS bytes. */
3819 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
3821 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3824 /* Return the cost of moving between two registers of mode MODE. */
3827 mips_set_reg_reg_cost (machine_mode mode
)
3829 switch (GET_MODE_CLASS (mode
))
3832 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3835 case MODE_COMPLEX_FLOAT
:
3836 case MODE_VECTOR_FLOAT
:
3837 if (TARGET_HARD_FLOAT
)
3838 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3842 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3846 /* Implement TARGET_RTX_COSTS. */
3849 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3850 int *total
, bool speed
)
3852 machine_mode mode
= GET_MODE (x
);
3853 bool float_mode_p
= FLOAT_MODE_P (mode
);
3857 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3858 appear in the instruction stream, and the cost of a comparison is
3859 really the cost of the branch or scc condition. At the time of
3860 writing, GCC only uses an explicit outer COMPARE code when optabs
3861 is testing whether a constant is expensive enough to force into a
3862 register. We want optabs to pass such constants through the MIPS
3863 expanders instead, so make all constants very cheap here. */
3864 if (outer_code
== COMPARE
)
3866 gcc_assert (CONSTANT_P (x
));
3874 /* Treat *clear_upper32-style ANDs as having zero cost in the
3875 second operand. The cost is entirely in the first operand.
3877 ??? This is needed because we would otherwise try to CSE
3878 the constant operand. Although that's the right thing for
3879 instructions that continue to be a register operation throughout
3880 compilation, it is disastrous for instructions that could
3881 later be converted into a memory operation. */
3883 && outer_code
== AND
3884 && UINTVAL (x
) == 0xffffffff)
3892 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3901 /* When not optimizing for size, we care more about the cost
3902 of hot code, and hot code is often in a loop. If a constant
3903 operand needs to be forced into a register, we will often be
3904 able to hoist the constant load out of the loop, so the load
3905 should not contribute to the cost. */
3906 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3918 if (force_to_mem_operand (x
, VOIDmode
))
3920 *total
= COSTS_N_INSNS (1);
3923 cost
= mips_const_insns (x
);
3926 /* If the constant is likely to be stored in a GPR, SETs of
3927 single-insn constants are as cheap as register sets; we
3928 never want to CSE them.
3930 Don't reduce the cost of storing a floating-point zero in
3931 FPRs. If we have a zero in an FPR for other reasons, we
3932 can get better cfg-cleanup and delayed-branch results by
3933 using it consistently, rather than using $0 sometimes and
3934 an FPR at other times. Also, moves between floating-point
3935 registers are sometimes cheaper than (D)MTC1 $0. */
3937 && outer_code
== SET
3938 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3940 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3941 want to CSE the constant itself. It is usually better to
3942 have N copies of the last operation in the sequence and one
3943 shared copy of the other operations. (Note that this is
3944 not true for MIPS16 code, where the final operation in the
3945 sequence is often an extended instruction.)
3947 Also, if we have a CONST_INT, we don't know whether it is
3948 for a word or doubleword operation, so we cannot rely on
3949 the result of mips_build_integer. */
3950 else if (!TARGET_MIPS16
3951 && (outer_code
== SET
|| mode
== VOIDmode
))
3953 *total
= COSTS_N_INSNS (cost
);
3956 /* The value will need to be fetched from the constant pool. */
3957 *total
= CONSTANT_POOL_COST
;
3961 /* If the address is legitimate, return the number of
3962 instructions it needs. */
3964 cost
= mips_address_insns (addr
, mode
, true);
3967 *total
= COSTS_N_INSNS (cost
+ 1);
3970 /* Check for a scaled indexed address. */
3971 if (mips_lwxs_address_p (addr
)
3972 || mips_lx_address_p (addr
, mode
))
3974 *total
= COSTS_N_INSNS (2);
3977 /* Otherwise use the default handling. */
3981 *total
= COSTS_N_INSNS (6);
3985 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3989 /* Check for a *clear_upper32 pattern and treat it like a zero
3990 extension. See the pattern's comment for details. */
3993 && CONST_INT_P (XEXP (x
, 1))
3994 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3996 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3997 + set_src_cost (XEXP (x
, 0), speed
));
4000 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
4002 rtx op
= XEXP (x
, 0);
4003 if (GET_CODE (op
) == ASHIFT
4004 && CONST_INT_P (XEXP (op
, 1))
4005 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
4007 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
4011 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
4012 a single instruction. */
4014 && GET_CODE (XEXP (x
, 0)) == NOT
4015 && GET_CODE (XEXP (x
, 1)) == NOT
)
4017 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
4018 *total
= (COSTS_N_INSNS (cost
)
4019 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
4020 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
4028 /* Double-word operations use two single-word operations. */
4029 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4038 if (CONSTANT_P (XEXP (x
, 1)))
4039 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4042 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4048 *total
= mips_cost
->fp_add
;
4050 *total
= COSTS_N_INSNS (4);
4054 /* Low-part immediates need an extended MIPS16 instruction. */
4055 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4056 + set_src_cost (XEXP (x
, 0), speed
));
4071 /* Branch comparisons have VOIDmode, so use the first operand's
4073 mode
= GET_MODE (XEXP (x
, 0));
4074 if (FLOAT_MODE_P (mode
))
4076 *total
= mips_cost
->fp_add
;
4079 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4085 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4086 && TARGET_FUSED_MADD
4087 && !HONOR_NANS (mode
)
4088 && !HONOR_SIGNED_ZEROS (mode
))
4090 /* See if we can use NMADD or NMSUB. See mips.md for the
4091 associated patterns. */
4092 rtx op0
= XEXP (x
, 0);
4093 rtx op1
= XEXP (x
, 1);
4094 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4096 *total
= (mips_fp_mult_cost (mode
)
4097 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
4098 + set_src_cost (XEXP (op0
, 1), speed
)
4099 + set_src_cost (op1
, speed
));
4102 if (GET_CODE (op1
) == MULT
)
4104 *total
= (mips_fp_mult_cost (mode
)
4105 + set_src_cost (op0
, speed
)
4106 + set_src_cost (XEXP (op1
, 0), speed
)
4107 + set_src_cost (XEXP (op1
, 1), speed
));
4116 /* If this is part of a MADD or MSUB, treat the PLUS as
4118 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
4119 && TARGET_FUSED_MADD
4120 && GET_CODE (XEXP (x
, 0)) == MULT
)
4123 *total
= mips_cost
->fp_add
;
4127 /* If it's an add + mult (which is equivalent to shift left) and
4128 it's immediate operand satisfies const_immlsa_operand predicate. */
4129 if (((ISA_HAS_LSA
&& mode
== SImode
)
4130 || (ISA_HAS_DLSA
&& mode
== DImode
))
4131 && GET_CODE (XEXP (x
, 0)) == MULT
)
4133 rtx op2
= XEXP (XEXP (x
, 0), 1);
4134 if (const_immlsa_operand (op2
, mode
))
4136 *total
= (COSTS_N_INSNS (1)
4137 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
4138 + set_src_cost (XEXP (x
, 1), speed
));
4143 /* Double-word operations require three single-word operations and
4144 an SLTU. The MIPS16 version then needs to move the result of
4145 the SLTU from $24 to a MIPS16 register. */
4146 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4147 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4153 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
4154 && TARGET_FUSED_MADD
4155 && !HONOR_NANS (mode
)
4156 && HONOR_SIGNED_ZEROS (mode
))
4158 /* See if we can use NMADD or NMSUB. See mips.md for the
4159 associated patterns. */
4160 rtx op
= XEXP (x
, 0);
4161 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4162 && GET_CODE (XEXP (op
, 0)) == MULT
)
4164 *total
= (mips_fp_mult_cost (mode
)
4165 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
4166 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
4167 + set_src_cost (XEXP (op
, 1), speed
));
4173 *total
= mips_cost
->fp_add
;
4175 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4179 if (ISA_HAS_FP_MADDF_MSUBF
)
4180 *total
= mips_fp_mult_cost (mode
);
4185 *total
= mips_fp_mult_cost (mode
);
4186 else if (mode
== DImode
&& !TARGET_64BIT
)
4187 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4188 where the mulsidi3 always includes an MFHI and an MFLO. */
4190 ? mips_cost
->int_mult_si
* 3 + 6
4191 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4193 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4194 else if (mode
== DImode
)
4195 *total
= mips_cost
->int_mult_di
;
4197 *total
= mips_cost
->int_mult_si
;
4201 /* Check for a reciprocal. */
4203 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4204 && flag_unsafe_math_optimizations
4205 && XEXP (x
, 0) == CONST1_RTX (mode
))
4207 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4208 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4209 division as being free. */
4210 *total
= set_src_cost (XEXP (x
, 1), speed
);
4212 *total
= (mips_fp_div_cost (mode
)
4213 + set_src_cost (XEXP (x
, 1), speed
));
4222 *total
= mips_fp_div_cost (mode
);
4231 /* It is our responsibility to make division by a power of 2
4232 as cheap as 2 register additions if we want the division
4233 expanders to be used for such operations; see the setting
4234 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4235 should always produce shorter code than using
4236 expand_sdiv2_pow2. */
4238 && CONST_INT_P (XEXP (x
, 1))
4239 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4241 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4244 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4246 else if (mode
== DImode
)
4247 *total
= mips_cost
->int_div_di
;
4249 *total
= mips_cost
->int_div_si
;
4253 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4257 if (outer_code
== SET
4259 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4260 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4261 && GET_MODE (XEXP (x
, 0)) == QImode
4262 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4264 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4267 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4270 /* Costings for highpart multiplies. Matching patterns of the form:
4272 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4273 (sign_extend:DI (...))
4277 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4278 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4279 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4280 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4281 && GET_MODE (XEXP (x
, 0)) == DImode
)
4283 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4284 && GET_MODE (XEXP (x
, 0)) == TImode
))
4285 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4286 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4287 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4288 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4289 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4293 *total
= COSTS_N_INSNS (1) + 1;
4294 else if (mode
== DImode
)
4295 *total
= mips_cost
->int_mult_di
;
4297 *total
= mips_cost
->int_mult_si
;
4299 /* Sign extension is free, zero extension costs for DImode when
4300 on a 64bit core / when DMUL is present. */
4301 for (int i
= 0; i
< 2; ++i
)
4303 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4305 && GET_CODE (op
) == ZERO_EXTEND
4306 && GET_MODE (op
) == DImode
)
4307 *total
+= rtx_cost (op
, MULT
, i
, speed
);
4309 *total
+= rtx_cost (XEXP (op
, 0), GET_CODE (op
), 0, speed
);
4317 case UNSIGNED_FLOAT
:
4320 case FLOAT_TRUNCATE
:
4321 *total
= mips_cost
->fp_add
;
4325 if (register_operand (SET_DEST (x
), VOIDmode
)
4326 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4328 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4338 /* Implement TARGET_ADDRESS_COST. */
4341 mips_address_cost (rtx addr
, machine_mode mode
,
4342 addr_space_t as ATTRIBUTE_UNUSED
,
4343 bool speed ATTRIBUTE_UNUSED
)
4345 return mips_address_insns (addr
, mode
, false);
4348 /* Information about a single instruction in a multi-instruction
4350 struct mips_multi_member
{
4351 /* True if this is a label, false if it is code. */
4354 /* The output_asm_insn format of the instruction. */
4357 /* The operands to the instruction. */
4358 rtx operands
[MAX_RECOG_OPERANDS
];
4360 typedef struct mips_multi_member mips_multi_member
;
4362 /* The instructions that make up the current multi-insn sequence. */
4363 static vec
<mips_multi_member
> mips_multi_members
;
4365 /* How many instructions (as opposed to labels) are in the current
4366 multi-insn sequence. */
4367 static unsigned int mips_multi_num_insns
;
4369 /* Start a new multi-insn sequence. */
4372 mips_multi_start (void)
4374 mips_multi_members
.truncate (0);
4375 mips_multi_num_insns
= 0;
4378 /* Add a new, uninitialized member to the current multi-insn sequence. */
4380 static struct mips_multi_member
*
4381 mips_multi_add (void)
4383 mips_multi_member empty
;
4384 return mips_multi_members
.safe_push (empty
);
4387 /* Add a normal insn with the given asm format to the current multi-insn
4388 sequence. The other arguments are a null-terminated list of operands. */
4391 mips_multi_add_insn (const char *format
, ...)
4393 struct mips_multi_member
*member
;
4398 member
= mips_multi_add ();
4399 member
->is_label_p
= false;
4400 member
->format
= format
;
4401 va_start (ap
, format
);
4403 while ((op
= va_arg (ap
, rtx
)))
4404 member
->operands
[i
++] = op
;
4406 mips_multi_num_insns
++;
4409 /* Add the given label definition to the current multi-insn sequence.
4410 The definition should include the colon. */
4413 mips_multi_add_label (const char *label
)
4415 struct mips_multi_member
*member
;
4417 member
= mips_multi_add ();
4418 member
->is_label_p
= true;
4419 member
->format
= label
;
4422 /* Return the index of the last member of the current multi-insn sequence. */
4425 mips_multi_last_index (void)
4427 return mips_multi_members
.length () - 1;
4430 /* Add a copy of an existing instruction to the current multi-insn
4431 sequence. I is the index of the instruction that should be copied. */
4434 mips_multi_copy_insn (unsigned int i
)
4436 struct mips_multi_member
*member
;
4438 member
= mips_multi_add ();
4439 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4440 gcc_assert (!member
->is_label_p
);
4443 /* Change the operand of an existing instruction in the current
4444 multi-insn sequence. I is the index of the instruction,
4445 OP is the index of the operand, and X is the new value. */
4448 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4450 mips_multi_members
[i
].operands
[op
] = x
;
4453 /* Write out the asm code for the current multi-insn sequence. */
4456 mips_multi_write (void)
4458 struct mips_multi_member
*member
;
4461 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4462 if (member
->is_label_p
)
4463 fprintf (asm_out_file
, "%s\n", member
->format
);
4465 output_asm_insn (member
->format
, member
->operands
);
4468 /* Return one word of double-word value OP, taking into account the fixed
4469 endianness of certain registers. HIGH_P is true to select the high part,
4470 false to select the low part. */
4473 mips_subword (rtx op
, bool high_p
)
4475 unsigned int byte
, offset
;
4478 mode
= GET_MODE (op
);
4479 if (mode
== VOIDmode
)
4480 mode
= TARGET_64BIT
? TImode
: DImode
;
4482 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4483 byte
= UNITS_PER_WORD
;
4487 if (FP_REG_RTX_P (op
))
4489 /* Paired FPRs are always ordered little-endian. */
4490 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4491 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4495 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4497 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4500 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4501 SPLIT_TYPE is the condition under which moves should be split. */
4504 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4506 return ((split_type
!= SPLIT_FOR_SPEED
4507 || mips_tuning_info
.fast_mult_zero_zero_p
)
4508 && src
== const0_rtx
4510 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4511 && (ISA_HAS_DSP_MULT
4512 ? ACC_REG_P (REGNO (dest
))
4513 : MD_REG_P (REGNO (dest
))));
4516 /* Return true if a move from SRC to DEST should be split into two.
4517 SPLIT_TYPE describes the split condition. */
4520 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4522 /* Check whether the move can be done using some variant of MULT $0,$0. */
4523 if (mips_mult_move_p (dest
, src
, split_type
))
4526 /* FPR-to-FPR moves can be done in a single instruction, if they're
4528 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4529 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4532 /* Check for floating-point loads and stores. */
4533 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4535 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4537 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4541 /* Otherwise split all multiword moves. */
4542 return size
> UNITS_PER_WORD
;
4545 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4546 SPLIT_TYPE describes the split condition. */
4549 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4553 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4554 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4556 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4557 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4558 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4559 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4560 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4561 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4562 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4563 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4564 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4565 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4566 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4567 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4568 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4569 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4573 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4575 low_dest
= mips_subword (dest
, false);
4576 mips_emit_move (low_dest
, mips_subword (src
, false));
4578 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4580 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4582 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4584 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4586 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4588 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4592 /* The operation can be split into two normal moves. Decide in
4593 which order to do them. */
4594 low_dest
= mips_subword (dest
, false);
4595 if (REG_P (low_dest
)
4596 && reg_overlap_mentioned_p (low_dest
, src
))
4598 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4599 mips_emit_move (low_dest
, mips_subword (src
, false));
4603 mips_emit_move (low_dest
, mips_subword (src
, false));
4604 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4609 /* Return the split type for instruction INSN. */
4611 static enum mips_split_type
4612 mips_insn_split_type (rtx insn
)
4614 basic_block bb
= BLOCK_FOR_INSN (insn
);
4617 if (optimize_bb_for_speed_p (bb
))
4618 return SPLIT_FOR_SPEED
;
4620 return SPLIT_FOR_SIZE
;
4622 /* Once CFG information has been removed, we should trust the optimization
4623 decisions made by previous passes and only split where necessary. */
4624 return SPLIT_IF_NECESSARY
;
4627 /* Return true if a move from SRC to DEST in INSN should be split. */
4630 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4632 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4635 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4639 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4641 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4644 /* Return the appropriate instructions to move SRC into DEST. Assume
4645 that SRC is operand 1 and DEST is operand 0. */
4648 mips_output_move (rtx dest
, rtx src
)
4650 enum rtx_code dest_code
, src_code
;
4652 enum mips_symbol_type symbol_type
;
4655 dest_code
= GET_CODE (dest
);
4656 src_code
= GET_CODE (src
);
4657 mode
= GET_MODE (dest
);
4658 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4660 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4663 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4664 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4666 if (dest_code
== REG
)
4668 if (GP_REG_P (REGNO (dest
)))
4669 return "move\t%0,%z1";
4671 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4673 if (ISA_HAS_DSP_MULT
)
4674 return "mult\t%q0,%.,%.";
4676 return "mult\t%.,%.";
4679 /* Moves to HI are handled by special .md insns. */
4680 if (REGNO (dest
) == LO_REGNUM
)
4683 if (DSP_ACC_REG_P (REGNO (dest
)))
4685 static char retval
[] = "mt__\t%z1,%q0";
4687 retval
[2] = reg_names
[REGNO (dest
)][4];
4688 retval
[3] = reg_names
[REGNO (dest
)][5];
4692 if (FP_REG_P (REGNO (dest
)))
4693 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4695 if (ALL_COP_REG_P (REGNO (dest
)))
4697 static char retval
[] = "dmtc_\t%z1,%0";
4699 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4700 return dbl_p
? retval
: retval
+ 1;
4703 if (dest_code
== MEM
)
4704 switch (GET_MODE_SIZE (mode
))
4706 case 1: return "sb\t%z1,%0";
4707 case 2: return "sh\t%z1,%0";
4708 case 4: return "sw\t%z1,%0";
4709 case 8: return "sd\t%z1,%0";
4712 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4714 if (src_code
== REG
)
4716 /* Moves from HI are handled by special .md insns. */
4717 if (REGNO (src
) == LO_REGNUM
)
4719 /* When generating VR4120 or VR4130 code, we use MACC and
4720 DMACC instead of MFLO. This avoids both the normal
4721 MIPS III HI/LO hazards and the errata related to
4724 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4728 if (DSP_ACC_REG_P (REGNO (src
)))
4730 static char retval
[] = "mf__\t%0,%q1";
4732 retval
[2] = reg_names
[REGNO (src
)][4];
4733 retval
[3] = reg_names
[REGNO (src
)][5];
4737 if (FP_REG_P (REGNO (src
)))
4738 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4740 if (ALL_COP_REG_P (REGNO (src
)))
4742 static char retval
[] = "dmfc_\t%0,%1";
4744 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4745 return dbl_p
? retval
: retval
+ 1;
4749 if (src_code
== MEM
)
4750 switch (GET_MODE_SIZE (mode
))
4752 case 1: return "lbu\t%0,%1";
4753 case 2: return "lhu\t%0,%1";
4754 case 4: return "lw\t%0,%1";
4755 case 8: return "ld\t%0,%1";
4758 if (src_code
== CONST_INT
)
4760 /* Don't use the X format for the operand itself, because that
4761 will give out-of-range numbers for 64-bit hosts and 32-bit
4764 return "li\t%0,%1\t\t\t# %X1";
4766 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4769 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4773 if (src_code
== HIGH
)
4774 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4776 if (CONST_GP_P (src
))
4777 return "move\t%0,%1";
4779 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4780 && mips_lo_relocs
[symbol_type
] != 0)
4782 /* A signed 16-bit constant formed by applying a relocation
4783 operator to a symbolic address. */
4784 gcc_assert (!mips_split_p
[symbol_type
]);
4785 return "li\t%0,%R1";
4788 if (symbolic_operand (src
, VOIDmode
))
4790 gcc_assert (TARGET_MIPS16
4791 ? TARGET_MIPS16_TEXT_LOADS
4792 : !TARGET_EXPLICIT_RELOCS
);
4793 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4796 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4798 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4800 if (GET_MODE (dest
) == V2SFmode
)
4801 return "mov.ps\t%0,%1";
4803 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4806 if (dest_code
== MEM
)
4807 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4809 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4811 if (src_code
== MEM
)
4812 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4814 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4816 static char retval
[] = "l_c_\t%0,%1";
4818 retval
[1] = (dbl_p
? 'd' : 'w');
4819 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4822 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4824 static char retval
[] = "s_c_\t%1,%0";
4826 retval
[1] = (dbl_p
? 'd' : 'w');
4827 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4833 /* Return true if CMP1 is a suitable second operand for integer ordering
4834 test CODE. See also the *sCC patterns in mips.md. */
4837 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4843 return reg_or_0_operand (cmp1
, VOIDmode
);
4847 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4851 return arith_operand (cmp1
, VOIDmode
);
4854 return sle_operand (cmp1
, VOIDmode
);
4857 return sleu_operand (cmp1
, VOIDmode
);
4864 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4865 integer ordering test *CODE, or if an equivalent combination can
4866 be formed by adjusting *CODE and *CMP1. When returning true, update
4867 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4871 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4874 HOST_WIDE_INT plus_one
;
4876 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4879 if (CONST_INT_P (*cmp1
))
4883 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4884 if (INTVAL (*cmp1
) < plus_one
)
4887 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4893 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4897 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4908 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4909 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4910 is nonnull, it's OK to set TARGET to the inverse of the result and
4911 flip *INVERT_PTR instead. */
4914 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4915 rtx target
, rtx cmp0
, rtx cmp1
)
4919 /* First see if there is a MIPS instruction that can do this operation.
4920 If not, try doing the same for the inverse operation. If that also
4921 fails, force CMP1 into a register and try again. */
4922 mode
= GET_MODE (cmp0
);
4923 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4924 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4927 enum rtx_code inv_code
= reverse_condition (code
);
4928 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4930 cmp1
= force_reg (mode
, cmp1
);
4931 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4933 else if (invert_ptr
== 0)
4937 inv_target
= mips_force_binary (GET_MODE (target
),
4938 inv_code
, cmp0
, cmp1
);
4939 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4943 *invert_ptr
= !*invert_ptr
;
4944 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4949 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4950 The register will have the same mode as CMP0. */
4953 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4955 if (cmp1
== const0_rtx
)
4958 if (uns_arith_operand (cmp1
, VOIDmode
))
4959 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4960 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4962 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4963 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4966 /* Convert *CODE into a code that can be used in a floating-point
4967 scc instruction (C.cond.fmt). Return true if the values of
4968 the condition code registers will be inverted, with 0 indicating
4969 that the condition holds. */
4972 mips_reversed_fp_cond (enum rtx_code
*code
)
4979 *code
= reverse_condition_maybe_unordered (*code
);
4987 /* Allocate a floating-point condition-code register of mode MODE.
4989 These condition code registers are used for certain kinds
4990 of compound operation, such as compare and branches, vconds,
4991 and built-in functions. At expand time, their use is entirely
4992 controlled by MIPS-specific code and is entirely internal
4993 to these compound operations.
4995 We could (and did in the past) expose condition-code values
4996 as pseudo registers and leave the register allocator to pick
4997 appropriate registers. The problem is that it is not practically
4998 possible for the rtl optimizers to guarantee that no spills will
4999 be needed, even when AVOID_CCMODE_COPIES is defined. We would
5000 therefore need spill and reload sequences to handle the worst case.
5002 Although such sequences do exist, they are very expensive and are
5003 not something we'd want to use. This is especially true of CCV2 and
5004 CCV4, where all the shuffling would greatly outweigh whatever benefit
5005 the vectorization itself provides.
5007 The main benefit of having more than one condition-code register
5008 is to allow the pipelining of operations, especially those involving
5009 comparisons and conditional moves. We don't really expect the
5010 registers to be live for long periods, and certainly never want
5011 them to be live across calls.
5013 Also, there should be no penalty attached to using all the available
5014 registers. They are simply bits in the same underlying FPU control
5017 We therefore expose the hardware registers from the outset and use
5018 a simple round-robin allocation scheme. */
5021 mips_allocate_fcc (machine_mode mode
)
5023 unsigned int regno
, count
;
5025 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
5029 else if (mode
== CCV2mode
)
5031 else if (mode
== CCV4mode
)
5036 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
5037 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
5038 cfun
->machine
->next_fcc
= 0;
5039 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
5040 cfun
->machine
->next_fcc
+= count
;
5041 return gen_rtx_REG (mode
, regno
);
5044 /* Convert a comparison into something that can be used in a branch or
5045 conditional move. On entry, *OP0 and *OP1 are the values being
5046 compared and *CODE is the code used to compare them.
5048 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5049 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5050 otherwise any standard branch condition can be used. The standard branch
5053 - EQ or NE between two registers.
5054 - any comparison between a register and zero. */
5057 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5062 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5064 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5066 else if (*code
== EQ
|| *code
== NE
)
5070 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5074 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5078 /* The comparison needs a separate scc instruction. Store the
5079 result of the scc in *OP0 and compare it against zero. */
5080 bool invert
= false;
5081 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5082 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5083 *code
= (invert
? EQ
: NE
);
5087 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5089 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5090 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5096 enum rtx_code cmp_code
;
5098 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5099 comparison to set a register. The branch or conditional move will
5100 then compare that register against zero.
5102 Set CMP_CODE to the code of the comparison instruction and
5103 *CODE to the code that the branch or move should use. */
5107 /* All FP conditions can be implemented directly with CMP.cond.fmt
5108 or by reversing the operands. */
5110 *op0
= gen_reg_rtx (CCFmode
);
5114 /* Three FP conditions cannot be implemented by reversing the
5115 operands for C.cond.fmt, instead a reversed condition code is
5116 required and a test for false. */
5117 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5119 *op0
= mips_allocate_fcc (CCmode
);
5121 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5125 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5129 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5130 and OPERAND[3]. Store the result in OPERANDS[0].
5132 On 64-bit targets, the mode of the comparison and target will always be
5133 SImode, thus possibly narrower than that of the comparison's operands. */
5136 mips_expand_scc (rtx operands
[])
5138 rtx target
= operands
[0];
5139 enum rtx_code code
= GET_CODE (operands
[1]);
5140 rtx op0
= operands
[2];
5141 rtx op1
= operands
[3];
5143 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5145 if (code
== EQ
|| code
== NE
)
5148 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5149 mips_emit_binary (code
, target
, op0
, op1
);
5152 rtx zie
= mips_zero_if_equal (op0
, op1
);
5153 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5157 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5160 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5161 CODE and jump to OPERANDS[3] if the condition holds. */
5164 mips_expand_conditional_branch (rtx
*operands
)
5166 enum rtx_code code
= GET_CODE (operands
[0]);
5167 rtx op0
= operands
[1];
5168 rtx op1
= operands
[2];
5171 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5172 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5173 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5178 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5179 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5182 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5183 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5188 reversed_p
= mips_reversed_fp_cond (&cond
);
5189 cmp_result
= mips_allocate_fcc (CCV2mode
);
5190 emit_insn (gen_scc_ps (cmp_result
,
5191 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5193 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5196 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5200 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5201 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5204 mips_expand_conditional_move (rtx
*operands
)
5207 enum rtx_code code
= GET_CODE (operands
[1]);
5208 rtx op0
= XEXP (operands
[1], 0);
5209 rtx op1
= XEXP (operands
[1], 1);
5211 mips_emit_compare (&code
, &op0
, &op1
, true);
5212 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5214 /* There is no direct support for general conditional GP move involving
5215 two registers using SEL. */
5217 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5218 && register_operand (operands
[2], VOIDmode
)
5219 && register_operand (operands
[3], VOIDmode
))
5221 machine_mode mode
= GET_MODE (operands
[0]);
5222 rtx temp
= gen_reg_rtx (mode
);
5223 rtx temp2
= gen_reg_rtx (mode
);
5225 emit_insn (gen_rtx_SET (temp
,
5226 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5227 operands
[2], const0_rtx
)));
5229 /* Flip the test for the second operand. */
5230 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5232 emit_insn (gen_rtx_SET (temp2
,
5233 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5234 operands
[3], const0_rtx
)));
5236 /* Merge the two results, at least one is guaranteed to be zero. */
5237 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5241 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5243 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5244 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5247 emit_insn (gen_rtx_SET (operands
[0],
5248 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5249 operands
[2], operands
[3])));
5253 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5256 mips_expand_conditional_trap (rtx comparison
)
5262 /* MIPS conditional trap instructions don't have GT or LE flavors,
5263 so we must swap the operands and convert to LT and GE respectively. */
5264 code
= GET_CODE (comparison
);
5271 code
= swap_condition (code
);
5272 op0
= XEXP (comparison
, 1);
5273 op1
= XEXP (comparison
, 0);
5277 op0
= XEXP (comparison
, 0);
5278 op1
= XEXP (comparison
, 1);
5282 mode
= GET_MODE (XEXP (comparison
, 0));
5283 op0
= force_reg (mode
, op0
);
5284 if (!(ISA_HAS_COND_TRAPI
5285 ? arith_operand (op1
, mode
)
5286 : reg_or_0_operand (op1
, mode
)))
5287 op1
= force_reg (mode
, op1
);
5289 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5290 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5294 /* Initialize *CUM for a call to a function of type FNTYPE. */
5297 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5299 memset (cum
, 0, sizeof (*cum
));
5300 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5301 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5304 /* Fill INFO with information about a single argument. CUM is the
5305 cumulative state for earlier arguments. MODE is the mode of this
5306 argument and TYPE is its type (if known). NAMED is true if this
5307 is a named (fixed) argument rather than a variable one. */
5310 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5311 machine_mode mode
, const_tree type
, bool named
)
5313 bool doubleword_aligned_p
;
5314 unsigned int num_bytes
, num_words
, max_regs
;
5316 /* Work out the size of the argument. */
5317 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5318 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5320 /* Decide whether it should go in a floating-point register, assuming
5321 one is free. Later code checks for availability.
5323 The checks against UNITS_PER_FPVALUE handle the soft-float and
5324 single-float cases. */
5328 /* The EABI conventions have traditionally been defined in terms
5329 of TYPE_MODE, regardless of the actual type. */
5330 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5331 || mode
== V2SFmode
)
5332 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5337 /* Only leading floating-point scalars are passed in
5338 floating-point registers. We also handle vector floats the same
5339 say, which is OK because they are not covered by the standard ABI. */
5340 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5341 info
->fpr_p
= (!cum
->gp_reg_found
5342 && cum
->arg_number
< 2
5344 || SCALAR_FLOAT_TYPE_P (type
)
5345 || VECTOR_FLOAT_TYPE_P (type
))
5346 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5347 || mode
== V2SFmode
)
5348 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5353 /* Scalar, complex and vector floating-point types are passed in
5354 floating-point registers, as long as this is a named rather
5355 than a variable argument. */
5356 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5357 info
->fpr_p
= (named
5358 && (type
== 0 || FLOAT_TYPE_P (type
))
5359 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5360 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5361 || mode
== V2SFmode
)
5362 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5364 /* ??? According to the ABI documentation, the real and imaginary
5365 parts of complex floats should be passed in individual registers.
5366 The real and imaginary parts of stack arguments are supposed
5367 to be contiguous and there should be an extra word of padding
5370 This has two problems. First, it makes it impossible to use a
5371 single "void *" va_list type, since register and stack arguments
5372 are passed differently. (At the time of writing, MIPSpro cannot
5373 handle complex float varargs correctly.) Second, it's unclear
5374 what should happen when there is only one register free.
5376 For now, we assume that named complex floats should go into FPRs
5377 if there are two FPRs free, otherwise they should be passed in the
5378 same way as a struct containing two floats. */
5380 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5381 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5383 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5384 info
->fpr_p
= false;
5394 /* See whether the argument has doubleword alignment. */
5395 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5398 /* Set REG_OFFSET to the register count we're interested in.
5399 The EABI allocates the floating-point registers separately,
5400 but the other ABIs allocate them like integer registers. */
5401 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5405 /* Advance to an even register if the argument is doubleword-aligned. */
5406 if (doubleword_aligned_p
)
5407 info
->reg_offset
+= info
->reg_offset
& 1;
5409 /* Work out the offset of a stack argument. */
5410 info
->stack_offset
= cum
->stack_words
;
5411 if (doubleword_aligned_p
)
5412 info
->stack_offset
+= info
->stack_offset
& 1;
5414 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5416 /* Partition the argument between registers and stack. */
5417 info
->reg_words
= MIN (num_words
, max_regs
);
5418 info
->stack_words
= num_words
- info
->reg_words
;
5421 /* INFO describes a register argument that has the normal format for the
5422 argument's mode. Return the register it uses, assuming that FPRs are
5423 available if HARD_FLOAT_P. */
5426 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5428 if (!info
->fpr_p
|| !hard_float_p
)
5429 return GP_ARG_FIRST
+ info
->reg_offset
;
5430 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5431 /* In o32, the second argument is always passed in $f14
5432 for TARGET_DOUBLE_FLOAT, regardless of whether the
5433 first argument was a word or doubleword. */
5434 return FP_ARG_FIRST
+ 2;
5436 return FP_ARG_FIRST
+ info
->reg_offset
;
5439 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5442 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5444 return !TARGET_OLDABI
;
5447 /* Implement TARGET_FUNCTION_ARG. */
5450 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5451 const_tree type
, bool named
)
5453 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5454 struct mips_arg_info info
;
5456 /* We will be called with a mode of VOIDmode after the last argument
5457 has been seen. Whatever we return will be passed to the call expander.
5458 If we need a MIPS16 fp_code, return a REG with the code stored as
5460 if (mode
== VOIDmode
)
5462 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5463 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5468 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5470 /* Return straight away if the whole argument is passed on the stack. */
5471 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5474 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5475 contains a double in its entirety, then that 64-bit chunk is passed
5476 in a floating-point register. */
5478 && TARGET_HARD_FLOAT
5481 && TREE_CODE (type
) == RECORD_TYPE
5482 && TYPE_SIZE_UNIT (type
)
5483 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5487 /* First check to see if there is any such field. */
5488 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5489 if (TREE_CODE (field
) == FIELD_DECL
5490 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5491 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5492 && tree_fits_shwi_p (bit_position (field
))
5493 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5498 /* Now handle the special case by returning a PARALLEL
5499 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5500 chunks are passed in registers. */
5502 HOST_WIDE_INT bitpos
;
5505 /* assign_parms checks the mode of ENTRY_PARM, so we must
5506 use the actual mode here. */
5507 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5510 field
= TYPE_FIELDS (type
);
5511 for (i
= 0; i
< info
.reg_words
; i
++)
5515 for (; field
; field
= DECL_CHAIN (field
))
5516 if (TREE_CODE (field
) == FIELD_DECL
5517 && int_bit_position (field
) >= bitpos
)
5521 && int_bit_position (field
) == bitpos
5522 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5523 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5524 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5526 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5529 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5530 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5532 bitpos
+= BITS_PER_WORD
;
5538 /* Handle the n32/n64 conventions for passing complex floating-point
5539 arguments in FPR pairs. The real part goes in the lower register
5540 and the imaginary part goes in the upper register. */
5543 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5549 inner
= GET_MODE_INNER (mode
);
5550 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5551 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5553 /* Real part in registers, imaginary part on stack. */
5554 gcc_assert (info
.stack_words
== info
.reg_words
);
5555 return gen_rtx_REG (inner
, regno
);
5559 gcc_assert (info
.stack_words
== 0);
5560 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5561 gen_rtx_REG (inner
, regno
),
5563 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5565 regno
+ info
.reg_words
/ 2),
5566 GEN_INT (GET_MODE_SIZE (inner
)));
5567 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5571 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5574 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5577 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
5578 const_tree type
, bool named
)
5580 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5581 struct mips_arg_info info
;
5583 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5586 cum
->gp_reg_found
= true;
5588 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5589 an explanation of what this code does. It assumes that we're using
5590 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5592 if (cum
->arg_number
< 2 && info
.fpr_p
)
5593 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5595 /* Advance the register count. This has the effect of setting
5596 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5597 argument required us to skip the final GPR and pass the whole
5598 argument on the stack. */
5599 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5600 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5601 else if (info
.reg_words
> 0)
5602 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5604 /* Advance the stack word count. */
5605 if (info
.stack_words
> 0)
5606 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5611 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5614 mips_arg_partial_bytes (cumulative_args_t cum
,
5615 machine_mode mode
, tree type
, bool named
)
5617 struct mips_arg_info info
;
5619 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5620 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5623 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5624 least PARM_BOUNDARY bits of alignment, but will be given anything up
5625 to STACK_BOUNDARY bits if the type requires it. */
5628 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
5630 unsigned int alignment
;
5632 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5633 if (alignment
< PARM_BOUNDARY
)
5634 alignment
= PARM_BOUNDARY
;
5635 if (alignment
> STACK_BOUNDARY
)
5636 alignment
= STACK_BOUNDARY
;
5640 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
5643 mips_get_reg_raw_mode (int regno
)
5645 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
5647 return default_get_reg_raw_mode (regno
);
5650 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5651 upward rather than downward. In other words, return true if the
5652 first byte of the stack slot has useful data, false if the last
5656 mips_pad_arg_upward (machine_mode mode
, const_tree type
)
5658 /* On little-endian targets, the first byte of every stack argument
5659 is passed in the first byte of the stack slot. */
5660 if (!BYTES_BIG_ENDIAN
)
5663 /* Otherwise, integral types are padded downward: the last byte of a
5664 stack argument is passed in the last byte of the stack slot. */
5666 ? (INTEGRAL_TYPE_P (type
)
5667 || POINTER_TYPE_P (type
)
5668 || FIXED_POINT_TYPE_P (type
))
5669 : (SCALAR_INT_MODE_P (mode
)
5670 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5673 /* Big-endian o64 pads floating-point arguments downward. */
5674 if (mips_abi
== ABI_O64
)
5675 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5678 /* Other types are padded upward for o32, o64, n32 and n64. */
5679 if (mips_abi
!= ABI_EABI
)
5682 /* Arguments smaller than a stack slot are padded downward. */
5683 if (mode
!= BLKmode
)
5684 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5686 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5689 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5690 if the least significant byte of the register has useful data. Return
5691 the opposite if the most significant byte does. */
5694 mips_pad_reg_upward (machine_mode mode
, tree type
)
5696 /* No shifting is required for floating-point arguments. */
5697 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5698 return !BYTES_BIG_ENDIAN
;
5700 /* Otherwise, apply the same padding to register arguments as we do
5701 to stack arguments. */
5702 return mips_pad_arg_upward (mode
, type
);
5705 /* Return nonzero when an argument must be passed by reference. */
5708 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5709 machine_mode mode
, const_tree type
,
5710 bool named ATTRIBUTE_UNUSED
)
5712 if (mips_abi
== ABI_EABI
)
5716 /* ??? How should SCmode be handled? */
5717 if (mode
== DImode
|| mode
== DFmode
5718 || mode
== DQmode
|| mode
== UDQmode
5719 || mode
== DAmode
|| mode
== UDAmode
)
5722 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5723 return size
== -1 || size
> UNITS_PER_WORD
;
5727 /* If we have a variable-sized parameter, we have no choice. */
5728 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5732 /* Implement TARGET_CALLEE_COPIES. */
5735 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5736 machine_mode mode ATTRIBUTE_UNUSED
,
5737 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5739 return mips_abi
== ABI_EABI
&& named
;
5742 /* See whether VALTYPE is a record whose fields should be returned in
5743 floating-point registers. If so, return the number of fields and
5744 list them in FIELDS (which should have two elements). Return 0
5747 For n32 & n64, a structure with one or two fields is returned in
5748 floating-point registers as long as every field has a floating-point
5752 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5760 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5764 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5766 if (TREE_CODE (field
) != FIELD_DECL
)
5769 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5775 fields
[i
++] = field
;
5780 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5781 a value in the most significant part of $2/$3 if:
5783 - the target is big-endian;
5785 - the value has a structure or union type (we generalize this to
5786 cover aggregates from other languages too); and
5788 - the structure is not returned in floating-point registers. */
5791 mips_return_in_msb (const_tree valtype
)
5795 return (TARGET_NEWABI
5796 && TARGET_BIG_ENDIAN
5797 && AGGREGATE_TYPE_P (valtype
)
5798 && mips_fpr_return_fields (valtype
, fields
) == 0);
5801 /* Return true if the function return value MODE will get returned in a
5802 floating-point register. */
5805 mips_return_mode_in_fpr_p (machine_mode mode
)
5807 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5808 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5810 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5811 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5814 /* Return the representation of an FPR return register when the
5815 value being returned in FP_RETURN has mode VALUE_MODE and the
5816 return type itself has mode TYPE_MODE. On NewABI targets,
5817 the two modes may be different for structures like:
5819 struct __attribute__((packed)) foo { float f; }
5821 where we return the SFmode value of "f" in FP_RETURN, but where
5822 the structure itself has mode BLKmode. */
5825 mips_return_fpr_single (machine_mode type_mode
,
5826 machine_mode value_mode
)
5830 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5831 if (type_mode
!= value_mode
)
5833 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5834 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5839 /* Return a composite value in a pair of floating-point registers.
5840 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5841 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5844 For n32 & n64, $f0 always holds the first value and $f2 the second.
5845 Otherwise the values are packed together as closely as possible. */
5848 mips_return_fpr_pair (machine_mode mode
,
5849 machine_mode mode1
, HOST_WIDE_INT offset1
,
5850 machine_mode mode2
, HOST_WIDE_INT offset2
)
5854 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
5855 return gen_rtx_PARALLEL
5858 gen_rtx_EXPR_LIST (VOIDmode
,
5859 gen_rtx_REG (mode1
, FP_RETURN
),
5861 gen_rtx_EXPR_LIST (VOIDmode
,
5862 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5863 GEN_INT (offset2
))));
5867 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5868 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5869 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5872 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5881 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5882 func
= fn_decl_or_type
;
5886 mode
= TYPE_MODE (valtype
);
5887 unsigned_p
= TYPE_UNSIGNED (valtype
);
5889 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5890 return values, promote the mode here too. */
5891 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5893 /* Handle structures whose fields are returned in $f0/$f2. */
5894 switch (mips_fpr_return_fields (valtype
, fields
))
5897 return mips_return_fpr_single (mode
,
5898 TYPE_MODE (TREE_TYPE (fields
[0])));
5901 return mips_return_fpr_pair (mode
,
5902 TYPE_MODE (TREE_TYPE (fields
[0])),
5903 int_byte_position (fields
[0]),
5904 TYPE_MODE (TREE_TYPE (fields
[1])),
5905 int_byte_position (fields
[1]));
5908 /* If a value is passed in the most significant part of a register, see
5909 whether we have to round the mode up to a whole number of words. */
5910 if (mips_return_in_msb (valtype
))
5912 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5913 if (size
% UNITS_PER_WORD
!= 0)
5915 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5916 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5920 /* For EABI, the class of return register depends entirely on MODE.
5921 For example, "struct { some_type x; }" and "union { some_type x; }"
5922 are returned in the same way as a bare "some_type" would be.
5923 Other ABIs only use FPRs for scalar, complex or vector types. */
5924 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5925 return gen_rtx_REG (mode
, GP_RETURN
);
5930 /* Handle long doubles for n32 & n64. */
5932 return mips_return_fpr_pair (mode
,
5934 DImode
, GET_MODE_SIZE (mode
) / 2);
5936 if (mips_return_mode_in_fpr_p (mode
))
5938 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5939 return mips_return_fpr_pair (mode
,
5940 GET_MODE_INNER (mode
), 0,
5941 GET_MODE_INNER (mode
),
5942 GET_MODE_SIZE (mode
) / 2);
5944 return gen_rtx_REG (mode
, FP_RETURN
);
5948 return gen_rtx_REG (mode
, GP_RETURN
);
5951 /* Implement TARGET_FUNCTION_VALUE. */
5954 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5955 bool outgoing ATTRIBUTE_UNUSED
)
5957 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5960 /* Implement TARGET_LIBCALL_VALUE. */
5963 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5965 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5968 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5970 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
5973 mips_function_value_regno_p (const unsigned int regno
)
5975 /* Most types only require one GPR or one FPR for return values but for
5976 hard-float two FPRs can be used for _Complex types (for all ABIs)
5977 and long doubles (for n64). */
5978 if (regno
== GP_RETURN
5979 || regno
== FP_RETURN
5980 || (FP_RETURN
!= GP_RETURN
5981 && regno
== FP_RETURN
+ 2))
5984 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
5985 This does not apply to o32 FPXX as floating-point function argument and
5986 return registers are described as 64-bit even though floating-point
5987 registers are primarily described as 32-bit internally.
5988 See: mips_get_reg_raw_mode. */
5989 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
5990 && FP_RETURN
!= GP_RETURN
5991 && (regno
== FP_RETURN
+ 1
5992 || regno
== FP_RETURN
+ 3))
5998 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5999 all BLKmode objects are returned in memory. Under the n32, n64
6000 and embedded ABIs, small structures are returned in a register.
6001 Objects with varying size must still be returned in memory, of
6005 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
6007 return (TARGET_OLDABI
6008 ? TYPE_MODE (type
) == BLKmode
6009 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
6012 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6015 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
6016 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6019 CUMULATIVE_ARGS local_cum
;
6020 int gp_saved
, fp_saved
;
6022 /* The caller has advanced CUM up to, but not beyond, the last named
6023 argument. Advance a local copy of CUM past the last "real" named
6024 argument, to find out how many registers are left over. */
6025 local_cum
= *get_cumulative_args (cum
);
6026 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
6029 /* Found out how many registers we need to save. */
6030 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
6031 fp_saved
= (EABI_FLOAT_VARARGS_P
6032 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
6041 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
6042 REG_PARM_STACK_SPACE (cfun
->decl
)
6043 - gp_saved
* UNITS_PER_WORD
);
6044 mem
= gen_frame_mem (BLKmode
, ptr
);
6045 set_mem_alias_set (mem
, get_varargs_alias_set ());
6047 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6052 /* We can't use move_block_from_reg, because it will use
6057 /* Set OFF to the offset from virtual_incoming_args_rtx of
6058 the first float register. The FP save area lies below
6059 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6060 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
6061 off
-= fp_saved
* UNITS_PER_FPREG
;
6063 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6065 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6066 i
+= MAX_FPRS_PER_FMT
)
6070 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6071 mem
= gen_frame_mem (mode
, ptr
);
6072 set_mem_alias_set (mem
, get_varargs_alias_set ());
6073 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6074 off
+= UNITS_PER_HWFPVALUE
;
6078 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6079 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6080 + fp_saved
* UNITS_PER_FPREG
);
6083 /* Implement TARGET_BUILTIN_VA_LIST. */
6086 mips_build_builtin_va_list (void)
6088 if (EABI_FLOAT_VARARGS_P
)
6090 /* We keep 3 pointers, and two offsets.
6092 Two pointers are to the overflow area, which starts at the CFA.
6093 One of these is constant, for addressing into the GPR save area
6094 below it. The other is advanced up the stack through the
6097 The third pointer is to the bottom of the GPR save area.
6098 Since the FPR save area is just below it, we can address
6099 FPR slots off this pointer.
6101 We also keep two one-byte offsets, which are to be subtracted
6102 from the constant pointers to yield addresses in the GPR and
6103 FPR save areas. These are downcounted as float or non-float
6104 arguments are used, and when they get to zero, the argument
6105 must be obtained from the overflow region. */
6106 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6109 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6111 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6112 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6114 f_gtop
= build_decl (BUILTINS_LOCATION
,
6115 FIELD_DECL
, get_identifier ("__gpr_top"),
6117 f_ftop
= build_decl (BUILTINS_LOCATION
,
6118 FIELD_DECL
, get_identifier ("__fpr_top"),
6120 f_goff
= build_decl (BUILTINS_LOCATION
,
6121 FIELD_DECL
, get_identifier ("__gpr_offset"),
6122 unsigned_char_type_node
);
6123 f_foff
= build_decl (BUILTINS_LOCATION
,
6124 FIELD_DECL
, get_identifier ("__fpr_offset"),
6125 unsigned_char_type_node
);
6126 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6127 warn on every user file. */
6128 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6129 array
= build_array_type (unsigned_char_type_node
,
6130 build_index_type (index
));
6131 f_res
= build_decl (BUILTINS_LOCATION
,
6132 FIELD_DECL
, get_identifier ("__reserved"), array
);
6134 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6135 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6136 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6137 DECL_FIELD_CONTEXT (f_goff
) = record
;
6138 DECL_FIELD_CONTEXT (f_foff
) = record
;
6139 DECL_FIELD_CONTEXT (f_res
) = record
;
6141 TYPE_FIELDS (record
) = f_ovfl
;
6142 DECL_CHAIN (f_ovfl
) = f_gtop
;
6143 DECL_CHAIN (f_gtop
) = f_ftop
;
6144 DECL_CHAIN (f_ftop
) = f_goff
;
6145 DECL_CHAIN (f_goff
) = f_foff
;
6146 DECL_CHAIN (f_foff
) = f_res
;
6148 layout_type (record
);
6152 /* Otherwise, we use 'void *'. */
6153 return ptr_type_node
;
6156 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6159 mips_va_start (tree valist
, rtx nextarg
)
6161 if (EABI_FLOAT_VARARGS_P
)
6163 const CUMULATIVE_ARGS
*cum
;
6164 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6165 tree ovfl
, gtop
, ftop
, goff
, foff
;
6167 int gpr_save_area_size
;
6168 int fpr_save_area_size
;
6171 cum
= &crtl
->args
.info
;
6173 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6175 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6177 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6178 f_gtop
= DECL_CHAIN (f_ovfl
);
6179 f_ftop
= DECL_CHAIN (f_gtop
);
6180 f_goff
= DECL_CHAIN (f_ftop
);
6181 f_foff
= DECL_CHAIN (f_goff
);
6183 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6185 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6187 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6189 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6191 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6194 /* Emit code to initialize OVFL, which points to the next varargs
6195 stack argument. CUM->STACK_WORDS gives the number of stack
6196 words used by named arguments. */
6197 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6198 if (cum
->stack_words
> 0)
6199 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6200 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6201 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6203 /* Emit code to initialize GTOP, the top of the GPR save area. */
6204 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6205 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6206 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6208 /* Emit code to initialize FTOP, the top of the FPR save area.
6209 This address is gpr_save_area_bytes below GTOP, rounded
6210 down to the next fp-aligned boundary. */
6211 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6212 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6213 fpr_offset
&= -UNITS_PER_FPVALUE
;
6215 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6216 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6217 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6219 /* Emit code to initialize GOFF, the offset from GTOP of the
6220 next GPR argument. */
6221 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6222 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6223 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6225 /* Likewise emit code to initialize FOFF, the offset from FTOP
6226 of the next FPR argument. */
6227 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6228 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6229 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6233 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6234 std_expand_builtin_va_start (valist
, nextarg
);
6238 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6242 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6245 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6246 unsigned HOST_WIDE_INT align
, boundary
;
6249 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6251 type
= build_pointer_type (type
);
6253 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6254 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6256 /* When we align parameter on stack for caller, if the parameter
6257 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6258 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6259 here with caller. */
6260 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6261 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6263 boundary
/= BITS_PER_UNIT
;
6265 /* Hoist the valist value into a temporary for the moment. */
6266 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6268 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6269 requires greater alignment, we must perform dynamic alignment. */
6270 if (boundary
> align
)
6272 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6273 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6274 gimplify_and_add (t
, pre_p
);
6276 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6277 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6279 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6280 gimplify_and_add (t
, pre_p
);
6285 /* If the actual alignment is less than the alignment of the type,
6286 adjust the type accordingly so that we don't assume strict alignment
6287 when dereferencing the pointer. */
6288 boundary
*= BITS_PER_UNIT
;
6289 if (boundary
< TYPE_ALIGN (type
))
6291 type
= build_variant_type_copy (type
);
6292 TYPE_ALIGN (type
) = boundary
;
6295 /* Compute the rounded size of the type. */
6296 type_size
= size_in_bytes (type
);
6297 rounded_size
= round_up (type_size
, align
);
6299 /* Reduce rounded_size so it's sharable with the postqueue. */
6300 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6304 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6306 /* Small args are padded downward. */
6307 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6308 rounded_size
, size_int (align
));
6309 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6310 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6311 addr
= fold_build_pointer_plus (addr
, t
);
6314 /* Compute new value for AP. */
6315 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6316 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6317 gimplify_and_add (t
, pre_p
);
6319 addr
= fold_convert (build_pointer_type (type
), addr
);
6322 addr
= build_va_arg_indirect_ref (addr
);
6324 return build_va_arg_indirect_ref (addr
);
6327 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6330 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6336 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6338 type
= build_pointer_type (type
);
6340 if (!EABI_FLOAT_VARARGS_P
)
6341 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6344 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6345 tree ovfl
, top
, off
, align
;
6346 HOST_WIDE_INT size
, rsize
, osize
;
6349 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6350 f_gtop
= DECL_CHAIN (f_ovfl
);
6351 f_ftop
= DECL_CHAIN (f_gtop
);
6352 f_goff
= DECL_CHAIN (f_ftop
);
6353 f_foff
= DECL_CHAIN (f_goff
);
6357 TOP be the top of the GPR or FPR save area;
6358 OFF be the offset from TOP of the next register;
6359 ADDR_RTX be the address of the argument;
6360 SIZE be the number of bytes in the argument type;
6361 RSIZE be the number of bytes used to store the argument
6362 when it's in the register save area; and
6363 OSIZE be the number of bytes used to store it when it's
6364 in the stack overflow area.
6366 The code we want is:
6368 1: off &= -rsize; // round down
6371 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6376 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6377 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6381 [1] and [9] can sometimes be optimized away. */
6383 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6385 size
= int_size_in_bytes (type
);
6387 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6388 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6390 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6391 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6392 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6393 unshare_expr (valist
), f_foff
, NULL_TREE
);
6395 /* When va_start saves FPR arguments to the stack, each slot
6396 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6397 argument's precision. */
6398 rsize
= UNITS_PER_HWFPVALUE
;
6400 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6401 (= PARM_BOUNDARY bits). This can be different from RSIZE
6404 (1) On 32-bit targets when TYPE is a structure such as:
6406 struct s { float f; };
6408 Such structures are passed in paired FPRs, so RSIZE
6409 will be 8 bytes. However, the structure only takes
6410 up 4 bytes of memory, so OSIZE will only be 4.
6412 (2) In combinations such as -mgp64 -msingle-float
6413 -fshort-double. Doubles passed in registers will then take
6414 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6415 stack take up UNITS_PER_WORD bytes. */
6416 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6420 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6421 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6422 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6423 unshare_expr (valist
), f_goff
, NULL_TREE
);
6424 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6425 if (rsize
> UNITS_PER_WORD
)
6427 /* [1] Emit code for: off &= -rsize. */
6428 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6429 build_int_cst (TREE_TYPE (off
), -rsize
));
6430 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6435 /* [2] Emit code to branch if off == 0. */
6436 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6437 build_int_cst (TREE_TYPE (off
), 0));
6438 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6440 /* [5] Emit code for: off -= rsize. We do this as a form of
6441 post-decrement not available to C. */
6442 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6443 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6445 /* [4] Emit code for:
6446 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6447 t
= fold_convert (sizetype
, t
);
6448 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6449 t
= fold_build_pointer_plus (top
, t
);
6450 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6451 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6452 COND_EXPR_THEN (addr
) = t
;
6454 if (osize
> UNITS_PER_WORD
)
6456 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6457 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6458 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6459 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6460 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6461 unshare_expr (ovfl
), t
);
6466 /* [10, 11] Emit code for:
6467 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6469 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6470 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6471 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6472 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6474 /* String [9] and [10, 11] together. */
6476 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6477 COND_EXPR_ELSE (addr
) = t
;
6479 addr
= fold_convert (build_pointer_type (type
), addr
);
6480 addr
= build_va_arg_indirect_ref (addr
);
6484 addr
= build_va_arg_indirect_ref (addr
);
6489 /* Declare a unique, locally-binding function called NAME, then start
6493 mips_start_unique_function (const char *name
)
6497 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6498 get_identifier (name
),
6499 build_function_type_list (void_type_node
, NULL_TREE
));
6500 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6501 NULL_TREE
, void_type_node
);
6502 TREE_PUBLIC (decl
) = 1;
6503 TREE_STATIC (decl
) = 1;
6505 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6507 targetm
.asm_out
.unique_section (decl
, 0);
6508 switch_to_section (get_named_section (decl
, NULL
, 0));
6510 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6511 fputs ("\t.hidden\t", asm_out_file
);
6512 assemble_name (asm_out_file
, name
);
6513 putc ('\n', asm_out_file
);
6516 /* Start a definition of function NAME. MIPS16_P indicates whether the
6517 function contains MIPS16 code. */
6520 mips_start_function_definition (const char *name
, bool mips16_p
)
6523 fprintf (asm_out_file
, "\t.set\tmips16\n");
6525 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6527 if (TARGET_MICROMIPS
)
6528 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6529 #ifdef HAVE_GAS_MICROMIPS
6531 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6534 if (!flag_inhibit_size_directive
)
6536 fputs ("\t.ent\t", asm_out_file
);
6537 assemble_name (asm_out_file
, name
);
6538 fputs ("\n", asm_out_file
);
6541 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6543 /* Start the definition proper. */
6544 assemble_name (asm_out_file
, name
);
6545 fputs (":\n", asm_out_file
);
6548 /* End a function definition started by mips_start_function_definition. */
6551 mips_end_function_definition (const char *name
)
6553 if (!flag_inhibit_size_directive
)
6555 fputs ("\t.end\t", asm_out_file
);
6556 assemble_name (asm_out_file
, name
);
6557 fputs ("\n", asm_out_file
);
6561 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6562 then free *STUB_PTR. */
6565 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6567 mips_one_only_stub
*stub
= *stub_ptr
;
6571 const char *name
= stub
->get_name ();
6572 mips_start_unique_function (name
);
6573 mips_start_function_definition (name
, false);
6574 stub
->output_body ();
6575 mips_end_function_definition (name
);
6580 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6583 mips_ok_for_lazy_binding_p (rtx x
)
6585 return (TARGET_USE_GOT
6586 && GET_CODE (x
) == SYMBOL_REF
6587 && !SYMBOL_REF_BIND_NOW_P (x
)
6588 && !mips_symbol_binds_local_p (x
));
6591 /* Load function address ADDR into register DEST. TYPE is as for
6592 mips_expand_call. Return true if we used an explicit lazy-binding
6596 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6598 /* If we're generating PIC, and this call is to a global function,
6599 try to allow its address to be resolved lazily. This isn't
6600 possible for sibcalls when $gp is call-saved because the value
6601 of $gp on entry to the stub would be our caller's gp, not ours. */
6602 if (TARGET_EXPLICIT_RELOCS
6603 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6604 && mips_ok_for_lazy_binding_p (addr
))
6606 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6607 emit_insn (gen_rtx_SET (dest
, addr
));
6612 mips_emit_move (dest
, addr
);
6617 struct local_alias_traits
: default_hashmap_traits
6619 static hashval_t
hash (rtx
);
6620 static bool equal_keys (rtx
, rtx
);
6623 /* Each locally-defined hard-float MIPS16 function has a local symbol
6624 associated with it. This hash table maps the function symbol (FUNC)
6625 to the local symbol (LOCAL). */
6626 static GTY (()) hash_map
<rtx
, rtx
, local_alias_traits
> *mips16_local_aliases
;
6628 /* Hash table callbacks for mips16_local_aliases. */
6631 local_alias_traits::hash (rtx func
)
6633 return htab_hash_string (XSTR (func
, 0));
6637 local_alias_traits::equal_keys (rtx func1
, rtx func2
)
6639 return rtx_equal_p (func1
, func2
);
6642 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6643 Return a local alias for it, creating a new one if necessary. */
6646 mips16_local_alias (rtx func
)
6648 /* Create the hash table if this is the first call. */
6649 if (mips16_local_aliases
== NULL
)
6650 mips16_local_aliases
6651 = hash_map
<rtx
, rtx
, local_alias_traits
>::create_ggc (37);
6653 /* Look up the function symbol, creating a new entry if need be. */
6655 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func
, &existed
);
6656 gcc_assert (slot
!= NULL
);
6660 const char *func_name
, *local_name
;
6663 /* Create a new SYMBOL_REF for the local symbol. The choice of
6664 __fn_local_* is based on the __fn_stub_* names that we've
6665 traditionally used for the non-MIPS16 stub. */
6666 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6667 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6668 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6669 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6671 /* Create a new structure to represent the mapping. */
6677 /* A chained list of functions for which mips16_build_call_stub has already
6678 generated a stub. NAME is the name of the function and FP_RET_P is true
6679 if the function returns a value in floating-point registers. */
6680 struct mips16_stub
{
6681 struct mips16_stub
*next
;
6685 static struct mips16_stub
*mips16_stubs
;
6687 /* Return the two-character string that identifies floating-point
6688 return mode MODE in the name of a MIPS16 function stub. */
6691 mips16_call_stub_mode_suffix (machine_mode mode
)
6695 else if (mode
== DFmode
)
6697 else if (mode
== SCmode
)
6699 else if (mode
== DCmode
)
6701 else if (mode
== V2SFmode
)
6703 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
6710 /* Write instructions to move a 32-bit value between general register
6711 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6712 from GPREG to FPREG and 'f' to move in the opposite direction. */
6715 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6717 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6718 reg_names
[gpreg
], reg_names
[fpreg
]);
6721 /* Likewise for 64-bit values. */
6724 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6727 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6728 reg_names
[gpreg
], reg_names
[fpreg
]);
6729 else if (ISA_HAS_MXHC1
)
6731 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6732 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6733 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6734 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6736 else if (TARGET_FLOATXX
&& direction
== 't')
6738 /* Use the argument save area to move via memory. */
6739 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
6740 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6741 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6743 else if (TARGET_FLOATXX
&& direction
== 'f')
6745 /* Use the argument save area to move via memory. */
6746 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6747 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
6748 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6752 /* Move the least-significant word. */
6753 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6754 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6755 /* ...then the most significant word. */
6756 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6757 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6761 /* Write out code to move floating-point arguments into or out of
6762 general registers. FP_CODE is the code describing which arguments
6763 are present (see the comment above the definition of CUMULATIVE_ARGS
6764 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6767 mips_output_args_xfer (int fp_code
, char direction
)
6769 unsigned int gparg
, fparg
, f
;
6770 CUMULATIVE_ARGS cum
;
6772 /* This code only works for o32 and o64. */
6773 gcc_assert (TARGET_OLDABI
);
6775 mips_init_cumulative_args (&cum
, NULL
);
6777 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6780 struct mips_arg_info info
;
6784 else if ((f
& 3) == 2)
6789 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6790 gparg
= mips_arg_regno (&info
, false);
6791 fparg
= mips_arg_regno (&info
, true);
6794 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6796 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6798 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6802 /* Write a MIPS16 stub for the current function. This stub is used
6803 for functions which take arguments in the floating-point registers.
6804 It is normal-mode code that moves the floating-point arguments
6805 into the general registers and then jumps to the MIPS16 code. */
6808 mips16_build_function_stub (void)
6810 const char *fnname
, *alias_name
, *separator
;
6811 char *secname
, *stubname
;
6816 /* Create the name of the stub, and its unique section. */
6817 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6818 alias
= mips16_local_alias (symbol
);
6820 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6821 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6822 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6823 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6825 /* Build a decl for the stub. */
6826 stubdecl
= build_decl (BUILTINS_LOCATION
,
6827 FUNCTION_DECL
, get_identifier (stubname
),
6828 build_function_type_list (void_type_node
, NULL_TREE
));
6829 set_decl_section_name (stubdecl
, secname
);
6830 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6831 RESULT_DECL
, NULL_TREE
, void_type_node
);
6833 /* Output a comment. */
6834 fprintf (asm_out_file
, "\t# Stub function for %s (",
6835 current_function_name ());
6837 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6839 fprintf (asm_out_file
, "%s%s", separator
,
6840 (f
& 3) == 1 ? "float" : "double");
6843 fprintf (asm_out_file
, ")\n");
6845 /* Start the function definition. */
6846 assemble_start_function (stubdecl
, stubname
);
6847 mips_start_function_definition (stubname
, false);
6849 /* If generating pic2 code, either set up the global pointer or
6851 if (TARGET_ABICALLS_PIC2
)
6853 if (TARGET_ABSOLUTE_ABICALLS
)
6854 fprintf (asm_out_file
, "\t.option\tpic0\n");
6857 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6858 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6859 target function is. Use a local GOT access when loading the
6860 symbol, to cut down on the number of unnecessary GOT entries
6861 for stubs that aren't needed. */
6862 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6867 /* Load the address of the MIPS16 function into $25. Do this first so
6868 that targets with coprocessor interlocks can use an MFC1 to fill the
6870 output_asm_insn ("la\t%^,%0", &symbol
);
6872 /* Move the arguments from floating-point registers to general registers. */
6873 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6875 /* Jump to the MIPS16 function. */
6876 output_asm_insn ("jr\t%^", NULL
);
6878 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6879 fprintf (asm_out_file
, "\t.option\tpic2\n");
6881 mips_end_function_definition (stubname
);
6883 /* If the linker needs to create a dynamic symbol for the target
6884 function, it will associate the symbol with the stub (which,
6885 unlike the target function, follows the proper calling conventions).
6886 It is therefore useful to have a local alias for the target function,
6887 so that it can still be identified as MIPS16 code. As an optimization,
6888 this symbol can also be used for indirect MIPS16 references from
6889 within this file. */
6890 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6892 switch_to_section (function_section (current_function_decl
));
6895 /* The current function is a MIPS16 function that returns a value in an FPR.
6896 Copy the return value from its soft-float to its hard-float location.
6897 libgcc2 has special non-MIPS16 helper functions for each case. */
6900 mips16_copy_fpr_return_value (void)
6902 rtx fn
, insn
, retval
;
6904 machine_mode return_mode
;
6907 return_type
= DECL_RESULT (current_function_decl
);
6908 return_mode
= DECL_MODE (return_type
);
6910 name
= ACONCAT (("__mips16_ret_",
6911 mips16_call_stub_mode_suffix (return_mode
),
6913 fn
= mips16_stub_function (name
);
6915 /* The function takes arguments in $2 (and possibly $3), so calls
6916 to it cannot be lazily bound. */
6917 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6919 /* Model the call as something that takes the GPR return value as
6920 argument and returns an "updated" value. */
6921 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6922 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6923 const0_rtx
, NULL_RTX
, false);
6924 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6927 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6928 RETVAL is the location of the return value, or null if this is
6929 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6930 arguments and FP_CODE is the code built by mips_function_arg;
6931 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6933 There are three alternatives:
6935 - If a stub was needed, emit the call and return the call insn itself.
6937 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6938 to the new target and return null.
6940 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6943 A stub is needed for calls to functions that, in normal mode,
6944 receive arguments in FPRs or return values in FPRs. The stub
6945 copies the arguments from their soft-float positions to their
6946 hard-float positions, calls the real function, then copies the
6947 return value from its hard-float position to its soft-float
6950 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6951 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6952 automatically redirects the JAL to the stub, otherwise the JAL
6953 continues to call FN directly. */
6956 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6960 struct mips16_stub
*l
;
6964 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6965 we were invoked with the -msoft-float option. */
6966 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6969 /* Figure out whether the value might come back in a floating-point
6971 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6973 /* We don't need to do anything if there were no floating-point
6974 arguments and the value will not be returned in a floating-point
6976 if (fp_code
== 0 && !fp_ret_p
)
6979 /* We don't need to do anything if this is a call to a special
6980 MIPS16 support function. */
6982 if (mips16_stub_function_p (fn
))
6985 /* If we're calling a locally-defined MIPS16 function, we know that
6986 it will return values in both the "soft-float" and "hard-float"
6987 registers. There is no need to use a stub to move the latter
6989 if (fp_code
== 0 && mips16_local_function_p (fn
))
6992 /* This code will only work for o32 and o64 abis. The other ABI's
6993 require more sophisticated support. */
6994 gcc_assert (TARGET_OLDABI
);
6996 /* If we're calling via a function pointer, use one of the magic
6997 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6998 Each stub expects the function address to arrive in register $2. */
6999 if (GET_CODE (fn
) != SYMBOL_REF
7000 || !call_insn_operand (fn
, VOIDmode
))
7007 /* If this is a locally-defined and locally-binding function,
7008 avoid the stub by calling the local alias directly. */
7009 if (mips16_local_function_p (fn
))
7011 *fn_ptr
= mips16_local_alias (fn
);
7015 /* Create a SYMBOL_REF for the libgcc.a function. */
7017 sprintf (buf
, "__mips16_call_stub_%s_%d",
7018 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
7021 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
7022 stub_fn
= mips16_stub_function (buf
);
7024 /* The function uses $2 as an argument, so calls to it
7025 cannot be lazily bound. */
7026 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
7028 /* Load the target function into $2. */
7029 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
7030 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
7032 /* Emit the call. */
7033 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
7034 args_size
, NULL_RTX
, lazy_p
);
7036 /* Tell GCC that this call does indeed use the value of $2. */
7037 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
7039 /* If we are handling a floating-point return value, we need to
7040 save $18 in the function prologue. Putting a note on the
7041 call will mean that df_regs_ever_live_p ($18) will be true if the
7042 call is not eliminated, and we can check that in the prologue
7045 CALL_INSN_FUNCTION_USAGE (insn
) =
7046 gen_rtx_EXPR_LIST (VOIDmode
,
7047 gen_rtx_CLOBBER (VOIDmode
,
7048 gen_rtx_REG (word_mode
, 18)),
7049 CALL_INSN_FUNCTION_USAGE (insn
));
7054 /* We know the function we are going to call. If we have already
7055 built a stub, we don't need to do anything further. */
7056 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
7057 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
7058 if (strcmp (l
->name
, fnname
) == 0)
7063 const char *separator
;
7064 char *secname
, *stubname
;
7065 tree stubid
, stubdecl
;
7068 /* If the function does not return in FPRs, the special stub
7072 If the function does return in FPRs, the stub section is named
7073 .mips16.call.fp.FNNAME
7075 Build a decl for the stub. */
7076 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7078 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7080 stubid
= get_identifier (stubname
);
7081 stubdecl
= build_decl (BUILTINS_LOCATION
,
7082 FUNCTION_DECL
, stubid
,
7083 build_function_type_list (void_type_node
,
7085 set_decl_section_name (stubdecl
, secname
);
7086 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7087 RESULT_DECL
, NULL_TREE
,
7090 /* Output a comment. */
7091 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7093 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7097 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7099 fprintf (asm_out_file
, "%s%s", separator
,
7100 (f
& 3) == 1 ? "float" : "double");
7103 fprintf (asm_out_file
, ")\n");
7105 /* Start the function definition. */
7106 assemble_start_function (stubdecl
, stubname
);
7107 mips_start_function_definition (stubname
, false);
7111 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7113 /* Create a fake CFA 4 bytes below the stack pointer.
7114 This works around unwinders (like libgcc's) that expect
7115 the CFA for non-signal frames to be unique. */
7116 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7118 /* "Save" $sp in itself so we don't use the fake CFA.
7119 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7120 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7122 /* Save the return address in $18. The stub's caller knows
7123 that $18 might be clobbered, even though $18 is usually
7124 a call-saved register.
7126 Do it early on in case the last move to a floating-point
7127 register can be scheduled into the delay slot of the
7128 call we are about to make. */
7129 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7130 reg_names
[GP_REG_FIRST
+ 18],
7131 reg_names
[RETURN_ADDR_REGNUM
]);
7135 /* Load the address of the MIPS16 function into $25. Do this
7136 first so that targets with coprocessor interlocks can use
7137 an MFC1 to fill the delay slot. */
7138 if (TARGET_EXPLICIT_RELOCS
)
7140 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7141 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7144 output_asm_insn ("la\t%^,%0", &fn
);
7147 /* Move the arguments from general registers to floating-point
7149 mips_output_args_xfer (fp_code
, 't');
7153 /* Now call the non-MIPS16 function. */
7154 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
7155 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7157 /* Move the result from floating-point registers to
7158 general registers. */
7159 switch (GET_MODE (retval
))
7162 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7166 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7167 TARGET_LITTLE_ENDIAN
7170 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7172 /* On 64-bit targets, complex floats are returned in
7173 a single GPR, such that "sd" on a suitably-aligned
7174 target would store the value correctly. */
7175 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7176 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7177 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7178 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7179 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7180 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7181 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7182 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7183 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7184 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7185 reg_names
[GP_RETURN
],
7186 reg_names
[GP_RETURN
],
7187 reg_names
[GP_RETURN
+ 1]);
7192 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7196 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7201 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7202 || GET_MODE (retval
) != V2SFmode
);
7203 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7209 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7210 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7214 /* Jump to the previously-loaded address. */
7215 output_asm_insn ("jr\t%^", NULL
);
7218 #ifdef ASM_DECLARE_FUNCTION_SIZE
7219 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7222 mips_end_function_definition (stubname
);
7224 /* Record this stub. */
7225 l
= XNEW (struct mips16_stub
);
7226 l
->name
= xstrdup (fnname
);
7227 l
->fp_ret_p
= fp_ret_p
;
7228 l
->next
= mips16_stubs
;
7232 /* If we expect a floating-point return value, but we've built a
7233 stub which does not expect one, then we're in trouble. We can't
7234 use the existing stub, because it won't handle the floating-point
7235 value. We can't build a new stub, because the linker won't know
7236 which stub to use for the various calls in this object file.
7237 Fortunately, this case is illegal, since it means that a function
7238 was declared in two different ways in a single compilation. */
7239 if (fp_ret_p
&& !l
->fp_ret_p
)
7240 error ("cannot handle inconsistent calls to %qs", fnname
);
7242 if (retval
== NULL_RTX
)
7243 pattern
= gen_call_internal_direct (fn
, args_size
);
7245 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7246 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7248 /* If we are calling a stub which handles a floating-point return
7249 value, we need to arrange to save $18 in the prologue. We do this
7250 by marking the function call as using the register. The prologue
7251 will later see that it is used, and emit code to save it. */
7253 CALL_INSN_FUNCTION_USAGE (insn
) =
7254 gen_rtx_EXPR_LIST (VOIDmode
,
7255 gen_rtx_CLOBBER (VOIDmode
,
7256 gen_rtx_REG (word_mode
, 18)),
7257 CALL_INSN_FUNCTION_USAGE (insn
));
7262 /* Expand a call of type TYPE. RESULT is where the result will go (null
7263 for "call"s and "sibcall"s), ADDR is the address of the function,
7264 ARGS_SIZE is the size of the arguments and AUX is the value passed
7265 to us by mips_function_arg. LAZY_P is true if this call already
7266 involves a lazily-bound function address (such as when calling
7267 functions through a MIPS16 hard-float stub).
7269 Return the call itself. */
7272 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7273 rtx args_size
, rtx aux
, bool lazy_p
)
7275 rtx orig_addr
, pattern
;
7279 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7280 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7283 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7288 if (!call_insn_operand (addr
, VOIDmode
))
7290 if (type
== MIPS_CALL_EPILOGUE
)
7291 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7293 addr
= gen_reg_rtx (Pmode
);
7294 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7299 rtx (*fn
) (rtx
, rtx
);
7301 if (type
== MIPS_CALL_SIBCALL
)
7302 fn
= gen_sibcall_internal
;
7304 fn
= gen_call_internal
;
7306 pattern
= fn (addr
, args_size
);
7308 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7310 /* Handle return values created by mips_return_fpr_pair. */
7311 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7314 if (type
== MIPS_CALL_SIBCALL
)
7315 fn
= gen_sibcall_value_multiple_internal
;
7317 fn
= gen_call_value_multiple_internal
;
7319 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7320 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7321 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7325 rtx (*fn
) (rtx
, rtx
, rtx
);
7327 if (type
== MIPS_CALL_SIBCALL
)
7328 fn
= gen_sibcall_value_internal
;
7330 fn
= gen_call_value_internal
;
7332 /* Handle return values created by mips_return_fpr_single. */
7333 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7334 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7335 pattern
= fn (result
, addr
, args_size
);
7338 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7341 /* Split call instruction INSN into a $gp-clobbering call and
7342 (where necessary) an instruction to restore $gp from its save slot.
7343 CALL_PATTERN is the pattern of the new call. */
7346 mips_split_call (rtx insn
, rtx call_pattern
)
7348 emit_call_insn (call_pattern
);
7349 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7350 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7351 POST_CALL_TMP_REG
));
7354 /* Return true if a call to DECL may need to use JALX. */
7357 mips_call_may_need_jalx_p (tree decl
)
7359 /* If the current translation unit would use a different mode for DECL,
7360 assume that the call needs JALX. */
7361 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7364 /* mips_get_compress_mode is always accurate for locally-binding
7365 functions in the current translation unit. */
7366 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7369 /* When -minterlink-compressed is in effect, assume that functions
7370 could use a different encoding mode unless an attribute explicitly
7371 tells us otherwise. */
7372 if (TARGET_INTERLINK_COMPRESSED
)
7374 if (!TARGET_COMPRESSION
7375 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7377 if (TARGET_COMPRESSION
7378 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7385 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7388 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7390 if (!TARGET_SIBCALLS
)
7393 /* Interrupt handlers need special epilogue code and therefore can't
7395 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7398 /* Direct Js are only possible to functions that use the same ISA encoding.
7399 There is no JX counterpoart of JALX. */
7401 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7402 && mips_call_may_need_jalx_p (decl
))
7405 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7406 require $gp to be valid on entry, so sibcalls can only use stubs
7407 if $gp is call-clobbered. */
7409 && TARGET_CALL_SAVED_GP
7410 && !TARGET_ABICALLS_PIC0
7411 && !targetm
.binds_local_p (decl
))
7418 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7421 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7423 enum by_pieces_operation op
,
7426 if (op
== STORE_BY_PIECES
)
7427 return mips_store_by_pieces_p (size
, align
);
7428 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7430 /* movmemsi is meant to generate code that is at least as good as
7431 move_by_pieces. However, movmemsi effectively uses a by-pieces
7432 implementation both for moves smaller than a word and for
7433 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7434 bytes. We should allow the tree-level optimisers to do such
7435 moves by pieces, as it often exposes other optimization
7436 opportunities. We might as well continue to use movmemsi at
7437 the rtl level though, as it produces better code when
7438 scheduling is disabled (such as at -O). */
7439 if (currently_expanding_to_rtl
)
7441 if (align
< BITS_PER_WORD
)
7442 return size
< UNITS_PER_WORD
;
7443 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7446 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7449 /* Implement a handler for STORE_BY_PIECES operations
7450 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7453 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7455 /* Storing by pieces involves moving constants into registers
7456 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7457 We need to decide whether it is cheaper to load the address of
7458 constant data into a register and use a block move instead. */
7460 /* If the data is only byte aligned, then:
7462 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7463 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7466 (a2) A block move of 4 bytes from aligned source data can use an
7467 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7468 4 SBs that we would generate when storing by pieces. */
7469 if (align
<= BITS_PER_UNIT
)
7472 /* If the data is 2-byte aligned, then:
7474 (b1) A block move of less than 4 bytes would use a combination of LBs,
7475 LHs, SBs and SHs. We get better code by using single-instruction
7476 LIs, SBs and SHs instead.
7478 (b2) A block move of 4 bytes from aligned source data would again use
7479 an LW/SWL/SWR sequence. In most cases, loading the address of
7480 the source data would require at least one extra instruction.
7481 It is often more efficient to use 2 single-instruction LIs and
7484 (b3) A block move of up to 3 additional bytes would be like (b1).
7486 (b4) A block move of 8 bytes from aligned source data can use two
7487 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7488 sequences are better than the 4 LIs and 4 SHs that we'd generate
7489 when storing by pieces.
7491 The reasoning for higher alignments is similar:
7493 (c1) A block move of less than 4 bytes would be the same as (b1).
7495 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7496 loading the address of the source data would typically require
7497 at least one extra instruction. It is generally better to use
7500 (c3) A block move of up to 3 additional bytes would be like (b1).
7502 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7503 LD/SD sequence, and in these cases we've traditionally preferred
7504 the memory copy over the more bulky constant moves. */
7508 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7509 Assume that the areas do not overlap. */
7512 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7514 HOST_WIDE_INT offset
, delta
;
7515 unsigned HOST_WIDE_INT bits
;
7520 /* Work out how many bits to move at a time. If both operands have
7521 half-word alignment, it is usually better to move in half words.
7522 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7523 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7524 Otherwise move word-sized chunks. */
7525 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7526 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7527 bits
= BITS_PER_WORD
/ 2;
7529 bits
= BITS_PER_WORD
;
7531 mode
= mode_for_size (bits
, MODE_INT
, 0);
7532 delta
= bits
/ BITS_PER_UNIT
;
7534 /* Allocate a buffer for the temporary registers. */
7535 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7537 /* Load as many BITS-sized chunks as possible. Use a normal load if
7538 the source has enough alignment, otherwise use left/right pairs. */
7539 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7541 regs
[i
] = gen_reg_rtx (mode
);
7542 if (MEM_ALIGN (src
) >= bits
)
7543 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7546 rtx part
= adjust_address (src
, BLKmode
, offset
);
7547 set_mem_size (part
, delta
);
7548 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7553 /* Copy the chunks to the destination. */
7554 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7555 if (MEM_ALIGN (dest
) >= bits
)
7556 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7559 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7560 set_mem_size (part
, delta
);
7561 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7565 /* Mop up any left-over bytes. */
7566 if (offset
< length
)
7568 src
= adjust_address (src
, BLKmode
, offset
);
7569 dest
= adjust_address (dest
, BLKmode
, offset
);
7570 move_by_pieces (dest
, src
, length
- offset
,
7571 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7575 /* Helper function for doing a loop-based block operation on memory
7576 reference MEM. Each iteration of the loop will operate on LENGTH
7579 Create a new base register for use within the loop and point it to
7580 the start of MEM. Create a new memory reference that uses this
7581 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7584 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7585 rtx
*loop_reg
, rtx
*loop_mem
)
7587 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7589 /* Although the new mem does not refer to a known location,
7590 it does keep up to LENGTH bytes of alignment. */
7591 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7592 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7595 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7596 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7597 the memory regions do not overlap. */
7600 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7601 HOST_WIDE_INT bytes_per_iter
)
7603 rtx_code_label
*label
;
7604 rtx src_reg
, dest_reg
, final_src
, test
;
7605 HOST_WIDE_INT leftover
;
7607 leftover
= length
% bytes_per_iter
;
7610 /* Create registers and memory references for use within the loop. */
7611 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7612 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7614 /* Calculate the value that SRC_REG should have after the last iteration
7616 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7619 /* Emit the start of the loop. */
7620 label
= gen_label_rtx ();
7623 /* Emit the loop body. */
7624 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7626 /* Move on to the next block. */
7627 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7628 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7630 /* Emit the loop condition. */
7631 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7632 if (Pmode
== DImode
)
7633 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7635 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7637 /* Mop up any left-over bytes. */
7639 mips_block_move_straight (dest
, src
, leftover
);
7642 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7643 memory reference SRC to memory reference DEST. */
7646 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7648 /* Disable entirely for R6 initially. */
7649 if (!ISA_HAS_LWL_LWR
)
7652 if (CONST_INT_P (length
))
7654 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7656 mips_block_move_straight (dest
, src
, INTVAL (length
));
7661 mips_block_move_loop (dest
, src
, INTVAL (length
),
7662 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7669 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7672 mips_expand_synci_loop (rtx begin
, rtx end
)
7674 rtx inc
, cmp_result
, mask
, length
;
7675 rtx_code_label
*label
, *end_label
;
7677 /* Create end_label. */
7678 end_label
= gen_label_rtx ();
7680 /* Check if begin equals end. */
7681 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7682 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7684 /* Load INC with the cache line size (rdhwr INC,$1). */
7685 inc
= gen_reg_rtx (Pmode
);
7686 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7688 /* Check if inc is 0. */
7689 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7690 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7692 /* Calculate mask. */
7693 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7695 /* Mask out begin by mask. */
7696 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7698 /* Calculate length. */
7699 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7701 /* Loop back to here. */
7702 label
= gen_label_rtx ();
7705 emit_insn (gen_synci (begin
));
7707 /* Update length. */
7708 mips_emit_binary (MINUS
, length
, length
, inc
);
7711 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7713 /* Check if length is greater than 0. */
7714 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7715 emit_jump_insn (gen_condjump (cmp_result
, label
));
7717 emit_label (end_label
);
7720 /* Expand a QI or HI mode atomic memory operation.
7722 GENERATOR contains a pointer to the gen_* function that generates
7723 the SI mode underlying atomic operation using masks that we
7726 RESULT is the return register for the operation. Its value is NULL
7729 MEM is the location of the atomic access.
7731 OLDVAL is the first operand for the operation.
7733 NEWVAL is the optional second operand for the operation. Its value
7734 is NULL if unused. */
7737 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7738 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7740 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7741 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7745 mode
= GET_MODE (mem
);
7747 /* Compute the address of the containing SImode value. */
7748 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7749 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7750 force_reg (Pmode
, GEN_INT (-4)));
7752 /* Create a memory reference for it. */
7753 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7754 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7755 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7757 /* Work out the byte offset of the QImode or HImode value,
7758 counting from the least significant byte. */
7759 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7760 if (TARGET_BIG_ENDIAN
)
7761 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7763 /* Multiply by eight to convert the shift value from bytes to bits. */
7764 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7766 /* Make the final shift an SImode value, so that it can be used in
7767 SImode operations. */
7768 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7770 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7771 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7772 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7773 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7775 /* Compute the equivalent exclusive mask. */
7776 inverted_mask
= gen_reg_rtx (SImode
);
7777 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
7779 /* Shift the old value into place. */
7780 if (oldval
!= const0_rtx
)
7782 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7783 oldval
= force_reg (SImode
, oldval
);
7784 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7787 /* Do the same for the new value. */
7788 if (newval
&& newval
!= const0_rtx
)
7790 newval
= convert_modes (SImode
, mode
, newval
, true);
7791 newval
= force_reg (SImode
, newval
);
7792 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7795 /* Do the SImode atomic access. */
7797 res
= gen_reg_rtx (SImode
);
7799 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7801 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7803 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7809 /* Shift and convert the result. */
7810 mips_emit_binary (AND
, res
, res
, mask
);
7811 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7812 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7816 /* Return true if it is possible to use left/right accesses for a
7817 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7818 When returning true, update *LEFT and *RIGHT as follows:
7820 *LEFT is a QImode reference to the first byte if big endian or
7821 the last byte if little endian. This address can be used in the
7822 left-side instructions (LWL, SWL, LDL, SDL).
7824 *RIGHT is a QImode reference to the opposite end of the field and
7825 can be used in the patterning right-side instruction. */
7828 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7829 rtx
*left
, rtx
*right
)
7833 /* Check that the size is valid. */
7834 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7837 /* We can only access byte-aligned values. Since we are always passed
7838 a reference to the first byte of the field, it is not necessary to
7839 do anything with BITPOS after this check. */
7840 if (bitpos
% BITS_PER_UNIT
!= 0)
7843 /* Reject aligned bitfields: we want to use a normal load or store
7844 instead of a left/right pair. */
7845 if (MEM_ALIGN (op
) >= width
)
7848 /* Get references to both ends of the field. */
7849 first
= adjust_address (op
, QImode
, 0);
7850 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7852 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7853 correspond to the MSB and RIGHT to the LSB. */
7854 if (TARGET_BIG_ENDIAN
)
7855 *left
= first
, *right
= last
;
7857 *left
= last
, *right
= first
;
7862 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7863 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7864 the operation is the equivalent of:
7866 (set DEST (*_extract SRC WIDTH BITPOS))
7868 Return true on success. */
7871 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7872 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7874 rtx left
, right
, temp
;
7875 rtx dest1
= NULL_RTX
;
7877 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7878 be a DImode, create a new temp and emit a zero extend at the end. */
7879 if (GET_MODE (dest
) == DImode
7881 && GET_MODE_BITSIZE (SImode
) == width
)
7884 dest
= gen_reg_rtx (SImode
);
7887 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7890 temp
= gen_reg_rtx (GET_MODE (dest
));
7891 if (GET_MODE (dest
) == DImode
)
7893 emit_insn (gen_mov_ldl (temp
, src
, left
));
7894 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7898 emit_insn (gen_mov_lwl (temp
, src
, left
));
7899 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7902 /* If we were loading 32bits and the original register was DI then
7903 sign/zero extend into the orignal dest. */
7907 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7909 emit_insn (gen_extendsidi2 (dest1
, dest
));
7914 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7915 BITPOS and SRC are the operands passed to the expander; the operation
7916 is the equivalent of:
7918 (set (zero_extract DEST WIDTH BITPOS) SRC)
7920 Return true on success. */
7923 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7924 HOST_WIDE_INT bitpos
)
7929 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7932 mode
= mode_for_size (width
, MODE_INT
, 0);
7933 src
= gen_lowpart (mode
, src
);
7936 emit_insn (gen_mov_sdl (dest
, src
, left
));
7937 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7941 emit_insn (gen_mov_swl (dest
, src
, left
));
7942 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7947 /* Return true if X is a MEM with the same size as MODE. */
7950 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
7953 && MEM_SIZE_KNOWN_P (x
)
7954 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7957 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7958 source of an "ext" instruction or the destination of an "ins"
7959 instruction. OP must be a register operand and the following
7960 conditions must hold:
7962 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7963 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7964 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7966 Also reject lengths equal to a word as they are better handled
7967 by the move patterns. */
7970 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7972 if (!ISA_HAS_EXT_INS
7973 || !register_operand (op
, VOIDmode
)
7974 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7977 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7980 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7986 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7987 operation if MAXLEN is the maxium length of consecutive bits that
7988 can make up MASK. MODE is the mode of the operation. See
7989 mask_low_and_shift_len for the actual definition. */
7992 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7994 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7997 /* Return true iff OP1 and OP2 are valid operands together for the
7998 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7999 see the table in the comment before the pattern. */
8002 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
8004 return (memory_operand (op1
, mode
)
8005 ? and_load_operand (op2
, mode
)
8006 : and_reg_operand (op2
, mode
));
8009 /* The canonical form of a mask-low-and-shift-left operation is
8010 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8011 cleared. Thus we need to shift MASK to the right before checking if it
8012 is a valid mask value. MODE is the mode of the operation. If true
8013 return the length of the mask, otherwise return -1. */
8016 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
8018 HOST_WIDE_INT shval
;
8020 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
8021 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
8024 /* Return true if -msplit-addresses is selected and should be honored.
8026 -msplit-addresses is a half-way house between explicit relocations
8027 and the traditional assembler macros. It can split absolute 32-bit
8028 symbolic constants into a high/lo_sum pair but uses macros for other
8031 Like explicit relocation support for REL targets, it relies
8032 on GNU extensions in the assembler and the linker.
8034 Although this code should work for -O0, it has traditionally
8035 been treated as an optimization. */
8038 mips_split_addresses_p (void)
8040 return (TARGET_SPLIT_ADDRESSES
8044 && !ABI_HAS_64BIT_SYMBOLS
);
8047 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8050 mips_init_relocs (void)
8052 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
8053 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
8054 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
8055 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
8056 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
8058 if (TARGET_MIPS16_PCREL_LOADS
)
8059 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
8062 if (ABI_HAS_64BIT_SYMBOLS
)
8064 if (TARGET_EXPLICIT_RELOCS
)
8066 mips_split_p
[SYMBOL_64_HIGH
] = true;
8067 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8068 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8070 mips_split_p
[SYMBOL_64_MID
] = true;
8071 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8072 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8074 mips_split_p
[SYMBOL_64_LOW
] = true;
8075 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8076 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8078 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8079 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8084 if (TARGET_EXPLICIT_RELOCS
8085 || mips_split_addresses_p ()
8088 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8089 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8090 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8097 /* The high part is provided by a pseudo copy of $gp. */
8098 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8099 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8101 else if (TARGET_EXPLICIT_RELOCS
)
8102 /* Small data constants are kept whole until after reload,
8103 then lowered by mips_rewrite_small_data. */
8104 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8106 if (TARGET_EXPLICIT_RELOCS
)
8108 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8111 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8112 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8116 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8117 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8120 /* Expose the use of $28 as soon as possible. */
8121 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8125 /* The HIGH and LO_SUM are matched by special .md patterns. */
8126 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8128 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8129 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8130 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8132 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8133 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8134 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8139 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8141 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8142 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8144 /* Expose the use of $28 as soon as possible. */
8145 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8151 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8152 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8153 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8156 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8157 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8159 if (TARGET_MIPS16_PCREL_LOADS
)
8161 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8162 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8166 mips_split_p
[SYMBOL_DTPREL
] = true;
8167 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8168 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8170 mips_split_p
[SYMBOL_TPREL
] = true;
8171 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8172 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8175 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8176 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8179 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8180 in context CONTEXT. RELOCS is the array of relocations to use. */
8183 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8184 const char **relocs
)
8186 enum mips_symbol_type symbol_type
;
8189 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8190 gcc_assert (relocs
[symbol_type
]);
8192 fputs (relocs
[symbol_type
], file
);
8193 output_addr_const (file
, mips_strip_unspec_address (op
));
8194 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8199 /* Start a new block with the given asm switch enabled. If we need
8200 to print a directive, emit PREFIX before it and SUFFIX after it. */
8203 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8204 const char *prefix
, const char *suffix
)
8206 if (asm_switch
->nesting_level
== 0)
8207 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8208 asm_switch
->nesting_level
++;
8211 /* Likewise, but end a block. */
8214 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8215 const char *prefix
, const char *suffix
)
8217 gcc_assert (asm_switch
->nesting_level
);
8218 asm_switch
->nesting_level
--;
8219 if (asm_switch
->nesting_level
== 0)
8220 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8223 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8224 that either print a complete line or print nothing. */
8227 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8229 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8233 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8235 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8238 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8239 The punctuation characters are:
8241 '(' Start a nested ".set noreorder" block.
8242 ')' End a nested ".set noreorder" block.
8243 '[' Start a nested ".set noat" block.
8244 ']' End a nested ".set noat" block.
8245 '<' Start a nested ".set nomacro" block.
8246 '>' End a nested ".set nomacro" block.
8247 '*' Behave like %(%< if generating a delayed-branch sequence.
8248 '#' Print a nop if in a ".set noreorder" block.
8249 '/' Like '#', but do nothing within a delayed-branch sequence.
8250 '?' Print "l" if mips_branch_likely is true
8251 '~' Print a nop if mips_branch_likely is true
8252 '.' Print the name of the register with a hard-wired zero (zero or $0).
8253 '@' Print the name of the assembler temporary register (at or $1).
8254 '^' Print the name of the pic call-through register (t9 or $25).
8255 '+' Print the name of the gp register (usually gp or $28).
8256 '$' Print the name of the stack pointer register (sp or $29).
8257 ':' Print "c" to use the compact version if the delay slot is a nop.
8258 '!' Print "s" to use the short version if the delay slot contains a
8261 See also mips_init_print_operand_pucnt. */
8264 mips_print_operand_punctuation (FILE *file
, int ch
)
8269 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8273 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8277 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8281 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8285 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8289 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8293 if (final_sequence
!= 0)
8295 mips_print_operand_punctuation (file
, '(');
8296 mips_print_operand_punctuation (file
, '<');
8301 if (mips_noreorder
.nesting_level
> 0)
8302 fputs ("\n\tnop", file
);
8306 /* Print an extra newline so that the delayed insn is separated
8307 from the following ones. This looks neater and is consistent
8308 with non-nop delayed sequences. */
8309 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8310 fputs ("\n\tnop\n", file
);
8314 if (mips_branch_likely
)
8319 if (mips_branch_likely
)
8320 fputs ("\n\tnop", file
);
8324 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8328 fputs (reg_names
[AT_REGNUM
], file
);
8332 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8336 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8340 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8344 /* When final_sequence is 0, the delay slot will be a nop. We can
8345 use the compact version for microMIPS. */
8346 if (final_sequence
== 0)
8351 /* If the delay slot instruction is short, then use the
8353 if (final_sequence
== 0
8354 || get_attr_length (final_sequence
->insn (1)) == 2)
8364 /* Initialize mips_print_operand_punct. */
8367 mips_init_print_operand_punct (void)
8371 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8372 mips_print_operand_punct
[(unsigned char) *p
] = true;
8375 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8376 associated with condition CODE. Print the condition part of the
8380 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8394 /* Conveniently, the MIPS names for these conditions are the same
8395 as their RTL equivalents. */
8396 fputs (GET_RTX_NAME (code
), file
);
8400 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8405 /* Likewise floating-point branches. */
8408 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8414 fputs ("c1eqz", file
);
8416 fputs ("c1f", file
);
8421 fputs ("c1nez", file
);
8423 fputs ("c1t", file
);
8427 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8432 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8435 mips_print_operand_punct_valid_p (unsigned char code
)
8437 return mips_print_operand_punct
[code
];
8440 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8442 'X' Print CONST_INT OP in hexadecimal format.
8443 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8444 'd' Print CONST_INT OP in decimal.
8445 'm' Print one less than CONST_INT OP in decimal.
8446 'h' Print the high-part relocation associated with OP, after stripping
8448 'R' Print the low-part relocation associated with OP.
8449 'C' Print the integer branch condition for comparison OP.
8450 'N' Print the inverse of the integer branch condition for comparison OP.
8451 'F' Print the FPU branch condition for comparison OP.
8452 'W' Print the inverse of the FPU branch condition for comparison OP.
8453 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8454 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8455 't' Like 'T', but with the EQ/NE cases reversed
8456 'Y' Print mips_fp_conditions[INTVAL (OP)]
8457 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8458 'q' Print a DSP accumulator register.
8459 'D' Print the second part of a double-word register or memory operand.
8460 'L' Print the low-order register in a double-word register operand.
8461 'M' Print high-order register in a double-word register operand.
8462 'z' Print $0 if OP is zero, otherwise print OP normally.
8463 'b' Print the address of a memory operand, without offset. */
8466 mips_print_operand (FILE *file
, rtx op
, int letter
)
8470 if (mips_print_operand_punct_valid_p (letter
))
8472 mips_print_operand_punctuation (file
, letter
);
8477 code
= GET_CODE (op
);
8482 if (CONST_INT_P (op
))
8483 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8485 output_operand_lossage ("invalid use of '%%%c'", letter
);
8489 if (CONST_INT_P (op
))
8490 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8492 output_operand_lossage ("invalid use of '%%%c'", letter
);
8496 if (CONST_INT_P (op
))
8497 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8499 output_operand_lossage ("invalid use of '%%%c'", letter
);
8503 if (CONST_INT_P (op
))
8504 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8506 output_operand_lossage ("invalid use of '%%%c'", letter
);
8512 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8516 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8520 mips_print_int_branch_condition (file
, code
, letter
);
8524 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8528 mips_print_float_branch_condition (file
, code
, letter
);
8532 mips_print_float_branch_condition (file
, reverse_condition (code
),
8539 int truth
= (code
== NE
) == (letter
== 'T');
8540 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8545 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8546 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8548 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8553 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
8555 mips_print_operand (file
, op
, 0);
8561 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8562 fprintf (file
, "$ac0");
8563 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8564 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8566 output_operand_lossage ("invalid use of '%%%c'", letter
);
8574 unsigned int regno
= REGNO (op
);
8575 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8576 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8579 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8580 output_operand_lossage ("invalid use of '%%%c'", letter
);
8581 /* We need to print $0 .. $31 for COP0 registers. */
8582 if (COP0_REG_P (regno
))
8583 fprintf (file
, "$%s", ®_names
[regno
][4]);
8585 fprintf (file
, "%s", reg_names
[regno
]);
8591 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8592 else if (letter
== 'b')
8594 gcc_assert (REG_P (XEXP (op
, 0)));
8595 mips_print_operand (file
, XEXP (op
, 0), 0);
8597 else if (letter
&& letter
!= 'z')
8598 output_operand_lossage ("invalid use of '%%%c'", letter
);
8600 output_address (XEXP (op
, 0));
8604 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8605 fputs (reg_names
[GP_REG_FIRST
], file
);
8606 else if (letter
&& letter
!= 'z')
8607 output_operand_lossage ("invalid use of '%%%c'", letter
);
8608 else if (CONST_GP_P (op
))
8609 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8611 output_addr_const (file
, mips_strip_unspec_address (op
));
8617 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8620 mips_print_operand_address (FILE *file
, rtx x
)
8622 struct mips_address_info addr
;
8624 if (mips_classify_address (&addr
, x
, word_mode
, true))
8628 mips_print_operand (file
, addr
.offset
, 0);
8629 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8632 case ADDRESS_LO_SUM
:
8633 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8635 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8638 case ADDRESS_CONST_INT
:
8639 output_addr_const (file
, x
);
8640 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8643 case ADDRESS_SYMBOLIC
:
8644 output_addr_const (file
, mips_strip_unspec_address (x
));
8650 /* Implement TARGET_ENCODE_SECTION_INFO. */
8653 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8655 default_encode_section_info (decl
, rtl
, first
);
8657 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8659 rtx symbol
= XEXP (rtl
, 0);
8660 tree type
= TREE_TYPE (decl
);
8662 /* Encode whether the symbol is short or long. */
8663 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8664 || mips_far_type_p (type
))
8665 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8669 /* Implement TARGET_SELECT_RTX_SECTION. */
8672 mips_select_rtx_section (machine_mode mode
, rtx x
,
8673 unsigned HOST_WIDE_INT align
)
8675 /* ??? Consider using mergeable small data sections. */
8676 if (mips_rtx_constant_in_small_data_p (mode
))
8677 return get_named_section (NULL
, ".sdata", 0);
8679 return default_elf_select_rtx_section (mode
, x
, align
);
8682 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8684 The complication here is that, with the combination TARGET_ABICALLS
8685 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8686 absolute addresses, and should therefore not be included in the
8687 read-only part of a DSO. Handle such cases by selecting a normal
8688 data section instead of a read-only one. The logic apes that in
8689 default_function_rodata_section. */
8692 mips_function_rodata_section (tree decl
)
8694 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8695 return default_function_rodata_section (decl
);
8697 if (decl
&& DECL_SECTION_NAME (decl
))
8699 const char *name
= DECL_SECTION_NAME (decl
);
8700 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8702 char *rname
= ASTRDUP (name
);
8704 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8706 else if (flag_function_sections
8707 && flag_data_sections
8708 && strncmp (name
, ".text.", 6) == 0)
8710 char *rname
= ASTRDUP (name
);
8711 memcpy (rname
+ 1, "data", 4);
8712 return get_section (rname
, SECTION_WRITE
, decl
);
8715 return data_section
;
8718 /* Implement TARGET_IN_SMALL_DATA_P. */
8721 mips_in_small_data_p (const_tree decl
)
8723 unsigned HOST_WIDE_INT size
;
8725 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8728 /* We don't yet generate small-data references for -mabicalls
8729 or VxWorks RTP code. See the related -G handling in
8730 mips_option_override. */
8731 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8734 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8738 /* Reject anything that isn't in a known small-data section. */
8739 name
= DECL_SECTION_NAME (decl
);
8740 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8743 /* If a symbol is defined externally, the assembler will use the
8744 usual -G rules when deciding how to implement macros. */
8745 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8748 else if (TARGET_EMBEDDED_DATA
)
8750 /* Don't put constants into the small data section: we want them
8751 to be in ROM rather than RAM. */
8752 if (TREE_CODE (decl
) != VAR_DECL
)
8755 if (TREE_READONLY (decl
)
8756 && !TREE_SIDE_EFFECTS (decl
)
8757 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8761 /* Enforce -mlocal-sdata. */
8762 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8765 /* Enforce -mextern-sdata. */
8766 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8768 if (DECL_EXTERNAL (decl
))
8770 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8774 /* We have traditionally not treated zero-sized objects as small data,
8775 so this is now effectively part of the ABI. */
8776 size
= int_size_in_bytes (TREE_TYPE (decl
));
8777 return size
> 0 && size
<= mips_small_data_threshold
;
8780 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8781 anchors for small data: the GP register acts as an anchor in that
8782 case. We also don't want to use them for PC-relative accesses,
8783 where the PC acts as an anchor. */
8786 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8788 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8790 case SYMBOL_PC_RELATIVE
:
8791 case SYMBOL_GP_RELATIVE
:
8795 return default_use_anchors_for_symbol_p (symbol
);
8799 /* The MIPS debug format wants all automatic variables and arguments
8800 to be in terms of the virtual frame pointer (stack pointer before
8801 any adjustment in the function), while the MIPS 3.0 linker wants
8802 the frame pointer to be the stack pointer after the initial
8803 adjustment. So, we do the adjustment here. The arg pointer (which
8804 is eliminated) points to the virtual frame pointer, while the frame
8805 pointer (which may be eliminated) points to the stack pointer after
8806 the initial adjustments. */
8809 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8811 rtx offset2
= const0_rtx
;
8812 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8815 offset
= INTVAL (offset2
);
8817 if (reg
== stack_pointer_rtx
8818 || reg
== frame_pointer_rtx
8819 || reg
== hard_frame_pointer_rtx
)
8821 offset
-= cfun
->machine
->frame
.total_size
;
8822 if (reg
== hard_frame_pointer_rtx
)
8823 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8829 /* Implement ASM_OUTPUT_EXTERNAL. */
8832 mips_output_external (FILE *file
, tree decl
, const char *name
)
8834 default_elf_asm_output_external (file
, decl
, name
);
8836 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8837 set in order to avoid putting out names that are never really
8839 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8841 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8843 /* When using assembler macros, emit .extern directives for
8844 all small-data externs so that the assembler knows how
8847 In most cases it would be safe (though pointless) to emit
8848 .externs for other symbols too. One exception is when an
8849 object is within the -G limit but declared by the user to
8850 be in a section other than .sbss or .sdata. */
8851 fputs ("\t.extern\t", file
);
8852 assemble_name (file
, name
);
8853 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8854 int_size_in_bytes (TREE_TYPE (decl
)));
8859 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8862 mips_output_filename (FILE *stream
, const char *name
)
8864 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8866 if (write_symbols
== DWARF2_DEBUG
)
8868 else if (mips_output_filename_first_time
)
8870 mips_output_filename_first_time
= 0;
8871 num_source_filenames
+= 1;
8872 current_function_file
= name
;
8873 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8874 output_quoted_string (stream
, name
);
8875 putc ('\n', stream
);
8877 /* If we are emitting stabs, let dbxout.c handle this (except for
8878 the mips_output_filename_first_time case). */
8879 else if (write_symbols
== DBX_DEBUG
)
8881 else if (name
!= current_function_file
8882 && strcmp (name
, current_function_file
) != 0)
8884 num_source_filenames
+= 1;
8885 current_function_file
= name
;
8886 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8887 output_quoted_string (stream
, name
);
8888 putc ('\n', stream
);
8892 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8894 static void ATTRIBUTE_UNUSED
8895 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8900 fputs ("\t.dtprelword\t", file
);
8904 fputs ("\t.dtpreldword\t", file
);
8910 output_addr_const (file
, x
);
8911 fputs ("+0x8000", file
);
8914 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8917 mips_dwarf_register_span (rtx reg
)
8922 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
8923 ensures that double-precision registers are treated as if they were
8924 64-bit physical registers. The code will run correctly with 32-bit or
8925 64-bit registers which means that dwarf information cannot be precise
8926 for all scenarios. We choose to state that the 64-bit values are stored
8927 in a single 64-bit 'piece'. This slightly unusual construct can then be
8928 interpreted as either a pair of registers if the registers are 32-bit or
8929 a single 64-bit register depending on hardware. */
8930 mode
= GET_MODE (reg
);
8931 if (FP_REG_P (REGNO (reg
))
8933 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8935 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
8937 /* By default, GCC maps increasing register numbers to increasing
8938 memory locations, but paired FPRs are always little-endian,
8939 regardless of the prevailing endianness. */
8940 else if (FP_REG_P (REGNO (reg
))
8941 && TARGET_BIG_ENDIAN
8942 && MAX_FPRS_PER_FMT
> 1
8943 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8945 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8946 high
= mips_subword (reg
, true);
8947 low
= mips_subword (reg
, false);
8948 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8954 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
8957 mips_dwarf_frame_reg_mode (int regno
)
8959 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
8961 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
8967 /* DSP ALU can bypass data with no delays for the following pairs. */
8968 enum insn_code dspalu_bypass_table
[][2] =
8970 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8971 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8972 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8973 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8974 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8975 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8976 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8977 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8981 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8984 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8985 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8986 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8988 for (i
= 0; i
< num_bypass
; i
++)
8990 if (out_icode
== dspalu_bypass_table
[i
][0]
8991 && in_icode
== dspalu_bypass_table
[i
][1])
8997 /* Implement ASM_OUTPUT_ASCII. */
9000 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
9006 fprintf (stream
, "\t.ascii\t\"");
9007 for (i
= 0; i
< len
; i
++)
9011 c
= (unsigned char) string
[i
];
9014 if (c
== '\\' || c
== '\"')
9016 putc ('\\', stream
);
9024 fprintf (stream
, "\\%03o", c
);
9028 if (cur_pos
> 72 && i
+1 < len
)
9031 fprintf (stream
, "\"\n\t.ascii\t\"");
9034 fprintf (stream
, "\"\n");
9037 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9038 Update *ADDR with the operand that should be printed. */
9041 mips_output_tls_reloc_directive (rtx
*addr
)
9043 enum mips_symbol_type type
;
9045 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
9046 *addr
= mips_strip_unspec_address (*addr
);
9050 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
9053 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
9060 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9061 macros, mark the symbol as written so that mips_asm_output_external
9062 won't emit an .extern for it. STREAM is the output file, NAME is the
9063 name of the symbol, INIT_STRING is the string that should be written
9064 before the symbol and FINAL_STRING is the string that should be
9065 written after it. FINAL_STRING is a printf format that consumes the
9066 remaining arguments. */
9069 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9070 const char *final_string
, ...)
9074 fputs (init_string
, stream
);
9075 assemble_name (stream
, name
);
9076 va_start (ap
, final_string
);
9077 vfprintf (stream
, final_string
, ap
);
9080 if (!TARGET_EXPLICIT_RELOCS
)
9082 tree name_tree
= get_identifier (name
);
9083 TREE_ASM_WRITTEN (name_tree
) = 1;
9087 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9088 NAME is the name of the object and ALIGN is the required alignment
9089 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9090 alignment argument. */
9093 mips_declare_common_object (FILE *stream
, const char *name
,
9094 const char *init_string
,
9095 unsigned HOST_WIDE_INT size
,
9096 unsigned int align
, bool takes_alignment_p
)
9098 if (!takes_alignment_p
)
9100 size
+= (align
/ BITS_PER_UNIT
) - 1;
9101 size
-= size
% (align
/ BITS_PER_UNIT
);
9102 mips_declare_object (stream
, name
, init_string
,
9103 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9106 mips_declare_object (stream
, name
, init_string
,
9107 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9108 size
, align
/ BITS_PER_UNIT
);
9111 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9112 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9115 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9116 unsigned HOST_WIDE_INT size
,
9119 /* If the target wants uninitialized const declarations in
9120 .rdata then don't put them in .comm. */
9121 if (TARGET_EMBEDDED_DATA
9122 && TARGET_UNINIT_CONST_IN_RODATA
9123 && TREE_CODE (decl
) == VAR_DECL
9124 && TREE_READONLY (decl
)
9125 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9127 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9128 targetm
.asm_out
.globalize_label (stream
, name
);
9130 switch_to_section (readonly_data_section
);
9131 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9132 mips_declare_object (stream
, name
, "",
9133 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9137 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9141 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9142 extern int size_directive_output
;
9144 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9145 definitions except that it uses mips_declare_object to emit the label. */
9148 mips_declare_object_name (FILE *stream
, const char *name
,
9149 tree decl ATTRIBUTE_UNUSED
)
9151 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9152 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9155 size_directive_output
= 0;
9156 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9160 size_directive_output
= 1;
9161 size
= int_size_in_bytes (TREE_TYPE (decl
));
9162 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9165 mips_declare_object (stream
, name
, "", ":\n");
9168 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9171 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9175 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9176 if (!flag_inhibit_size_directive
9177 && DECL_SIZE (decl
) != 0
9180 && DECL_INITIAL (decl
) == error_mark_node
9181 && !size_directive_output
)
9185 size_directive_output
= 1;
9186 size
= int_size_in_bytes (TREE_TYPE (decl
));
9187 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9192 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9193 with the current ABI. */
9196 mips_mdebug_abi_name (void)
9209 return TARGET_64BIT
? "eabi64" : "eabi32";
9215 /* Implement TARGET_ASM_FILE_START. */
9218 mips_file_start (void)
9220 default_file_start ();
9222 /* Generate a special section to describe the ABI switches used to
9223 produce the resultant binary. */
9225 /* Record the ABI itself. Modern versions of binutils encode
9226 this information in the ELF header flags, but GDB needs the
9227 information in order to correctly debug binaries produced by
9228 older binutils. See the function mips_gdbarch_init in
9230 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9231 mips_mdebug_abi_name ());
9233 /* There is no ELF header flag to distinguish long32 forms of the
9234 EABI from long64 forms. Emit a special section to help tools
9235 such as GDB. Do the same for o64, which is sometimes used with
9237 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9238 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9239 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9241 /* Record the NaN encoding. */
9242 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9243 fprintf (asm_out_file
, "\t.nan\t%s\n",
9244 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9246 #ifdef HAVE_AS_DOT_MODULE
9247 /* Record the FP ABI. See below for comments. */
9248 if (TARGET_NO_FLOAT
)
9249 #ifdef HAVE_AS_GNU_ATTRIBUTE
9250 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9254 else if (!TARGET_HARD_FLOAT_ABI
)
9255 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9256 else if (!TARGET_DOUBLE_FLOAT
)
9257 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9258 else if (TARGET_FLOATXX
)
9259 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9260 else if (TARGET_FLOAT64
)
9261 fputs ("\t.module\tfp=64\n", asm_out_file
);
9263 fputs ("\t.module\tfp=32\n", asm_out_file
);
9265 if (TARGET_ODD_SPREG
)
9266 fputs ("\t.module\toddspreg\n", asm_out_file
);
9268 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9271 #ifdef HAVE_AS_GNU_ATTRIBUTE
9275 /* No floating-point operations, -mno-float. */
9276 if (TARGET_NO_FLOAT
)
9278 /* Soft-float code, -msoft-float. */
9279 else if (!TARGET_HARD_FLOAT_ABI
)
9281 /* Single-float code, -msingle-float. */
9282 else if (!TARGET_DOUBLE_FLOAT
)
9284 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9286 This case used 12 callee-saved double-precision registers
9287 and is deprecated. */
9288 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9289 else if (TARGET_FLOATXX
)
9291 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9292 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9294 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9295 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9297 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9301 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9306 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9307 if (TARGET_ABICALLS
)
9309 fprintf (asm_out_file
, "\t.abicalls\n");
9310 if (TARGET_ABICALLS_PIC0
)
9311 fprintf (asm_out_file
, "\t.option\tpic0\n");
9314 if (flag_verbose_asm
)
9315 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9317 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9320 /* Implement TARGET_ASM_CODE_END. */
9323 mips_code_end (void)
9325 mips_finish_stub (&mips16_rdhwr_stub
);
9326 mips_finish_stub (&mips16_get_fcsr_stub
);
9327 mips_finish_stub (&mips16_set_fcsr_stub
);
9330 /* Make the last instruction frame-related and note that it performs
9331 the operation described by FRAME_PATTERN. */
9334 mips_set_frame_expr (rtx frame_pattern
)
9338 insn
= get_last_insn ();
9339 RTX_FRAME_RELATED_P (insn
) = 1;
9340 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9345 /* Return a frame-related rtx that stores REG at MEM.
9346 REG must be a single register. */
9349 mips_frame_set (rtx mem
, rtx reg
)
9353 set
= gen_rtx_SET (mem
, reg
);
9354 RTX_FRAME_RELATED_P (set
) = 1;
9359 /* Record that the epilogue has restored call-saved register REG. */
9362 mips_add_cfa_restore (rtx reg
)
9364 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9365 mips_epilogue
.cfa_restores
);
9368 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9369 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9370 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9371 static const unsigned char mips16e_s2_s8_regs
[] = {
9372 30, 23, 22, 21, 20, 19, 18
9374 static const unsigned char mips16e_a0_a3_regs
[] = {
9378 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9379 ordered from the uppermost in memory to the lowest in memory. */
9380 static const unsigned char mips16e_save_restore_regs
[] = {
9381 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9384 /* Return the index of the lowest X in the range [0, SIZE) for which
9385 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9388 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9393 for (i
= 0; i
< size
; i
++)
9394 if (BITSET_P (mask
, regs
[i
]))
9400 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9401 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9402 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9403 is true for all indexes (X, SIZE). */
9406 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9407 unsigned int size
, unsigned int *num_regs_ptr
)
9411 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9412 for (i
++; i
< size
; i
++)
9413 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9416 *mask_ptr
|= 1 << regs
[i
];
9420 /* Return a simplified form of X using the register values in REG_VALUES.
9421 REG_VALUES[R] is the last value assigned to hard register R, or null
9422 if R has not been modified.
9424 This function is rather limited, but is good enough for our purposes. */
9427 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9429 x
= avoid_constant_pool_reference (x
);
9433 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9434 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9435 x0
, GET_MODE (XEXP (x
, 0)));
9438 if (ARITHMETIC_P (x
))
9440 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9441 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9442 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9446 && reg_values
[REGNO (x
)]
9447 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9448 return reg_values
[REGNO (x
)];
9453 /* Return true if (set DEST SRC) stores an argument register into its
9454 caller-allocated save slot, storing the number of that argument
9455 register in *REGNO_PTR if so. REG_VALUES is as for
9456 mips16e_collect_propagate_value. */
9459 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9460 unsigned int *regno_ptr
)
9462 unsigned int argno
, regno
;
9463 HOST_WIDE_INT offset
, required_offset
;
9466 /* Check that this is a word-mode store. */
9467 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9470 /* Check that the register being saved is an unmodified argument
9472 regno
= REGNO (src
);
9473 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9475 argno
= regno
- GP_ARG_FIRST
;
9477 /* Check whether the address is an appropriate stack-pointer or
9478 frame-pointer access. */
9479 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9480 mips_split_plus (addr
, &base
, &offset
);
9481 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9482 if (base
== hard_frame_pointer_rtx
)
9483 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9484 else if (base
!= stack_pointer_rtx
)
9486 if (offset
!= required_offset
)
9493 /* A subroutine of mips_expand_prologue, called only when generating
9494 MIPS16e SAVE instructions. Search the start of the function for any
9495 instructions that save argument registers into their caller-allocated
9496 save slots. Delete such instructions and return a value N such that
9497 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9498 instructions redundant. */
9501 mips16e_collect_argument_saves (void)
9503 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9504 rtx_insn
*insn
, *next
;
9506 unsigned int nargs
, regno
;
9508 push_topmost_sequence ();
9510 memset (reg_values
, 0, sizeof (reg_values
));
9511 for (insn
= get_insns (); insn
; insn
= next
)
9513 next
= NEXT_INSN (insn
);
9514 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9520 set
= PATTERN (insn
);
9521 if (GET_CODE (set
) != SET
)
9524 dest
= SET_DEST (set
);
9525 src
= SET_SRC (set
);
9526 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9528 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9531 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9534 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9535 reg_values
[REGNO (dest
)]
9536 = mips16e_collect_propagate_value (src
, reg_values
);
9540 pop_topmost_sequence ();
9545 /* Return a move between register REGNO and memory location SP + OFFSET.
9546 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9547 Make the move a load if RESTORE_P, otherwise make it a store. */
9550 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9551 HOST_WIDE_INT offset
, unsigned int regno
)
9555 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9557 reg
= gen_rtx_REG (SImode
, regno
);
9560 mips_add_cfa_restore (reg
);
9561 return gen_rtx_SET (reg
, mem
);
9564 return gen_rtx_SET (mem
, reg
);
9565 return mips_frame_set (mem
, reg
);
9568 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9569 The instruction must:
9571 - Allocate or deallocate SIZE bytes in total; SIZE is known
9574 - Save or restore as many registers in *MASK_PTR as possible.
9575 The instruction saves the first registers at the top of the
9576 allocated area, with the other registers below it.
9578 - Save NARGS argument registers above the allocated area.
9580 (NARGS is always zero if RESTORE_P.)
9582 The SAVE and RESTORE instructions cannot save and restore all general
9583 registers, so there may be some registers left over for the caller to
9584 handle. Destructively modify *MASK_PTR so that it contains the registers
9585 that still need to be saved or restored. The caller can save these
9586 registers in the memory immediately below *OFFSET_PTR, which is a
9587 byte offset from the bottom of the allocated stack area. */
9590 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9591 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9595 HOST_WIDE_INT offset
, top_offset
;
9596 unsigned int i
, regno
;
9599 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9601 /* Calculate the number of elements in the PARALLEL. We need one element
9602 for the stack adjustment, one for each argument register save, and one
9603 for each additional register move. */
9605 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9606 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9609 /* Create the final PARALLEL. */
9610 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9613 /* Add the stack pointer adjustment. */
9614 set
= gen_rtx_SET (stack_pointer_rtx
,
9615 plus_constant (Pmode
, stack_pointer_rtx
,
9616 restore_p
? size
: -size
));
9617 RTX_FRAME_RELATED_P (set
) = 1;
9618 XVECEXP (pattern
, 0, n
++) = set
;
9620 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9621 top_offset
= restore_p
? size
: 0;
9623 /* Save the arguments. */
9624 for (i
= 0; i
< nargs
; i
++)
9626 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9627 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9629 XVECEXP (pattern
, 0, n
++) = set
;
9632 /* Then fill in the other register moves. */
9633 offset
= top_offset
;
9634 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9636 regno
= mips16e_save_restore_regs
[i
];
9637 if (BITSET_P (*mask_ptr
, regno
))
9639 offset
-= UNITS_PER_WORD
;
9640 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9641 XVECEXP (pattern
, 0, n
++) = set
;
9642 *mask_ptr
&= ~(1 << regno
);
9646 /* Tell the caller what offset it should use for the remaining registers. */
9647 *offset_ptr
= size
+ (offset
- top_offset
);
9649 gcc_assert (n
== XVECLEN (pattern
, 0));
9654 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9655 pointer. Return true if PATTERN matches the kind of instruction
9656 generated by mips16e_build_save_restore. If INFO is nonnull,
9657 initialize it when returning true. */
9660 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9661 struct mips16e_save_restore_info
*info
)
9663 unsigned int i
, nargs
, mask
, extra
;
9664 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9665 rtx set
, reg
, mem
, base
;
9668 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9671 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9672 top_offset
= adjust
> 0 ? adjust
: 0;
9674 /* Interpret all other members of the PARALLEL. */
9675 save_offset
= top_offset
- UNITS_PER_WORD
;
9679 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9681 /* Check that we have a SET. */
9682 set
= XVECEXP (pattern
, 0, n
);
9683 if (GET_CODE (set
) != SET
)
9686 /* Check that the SET is a load (if restoring) or a store
9688 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9692 /* Check that the address is the sum of the stack pointer and a
9693 possibly-zero constant offset. */
9694 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9695 if (base
!= stack_pointer_rtx
)
9698 /* Check that SET's other operand is a register. */
9699 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9703 /* Check for argument saves. */
9704 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9705 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9707 else if (offset
== save_offset
)
9709 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9710 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9713 mask
|= 1 << REGNO (reg
);
9714 save_offset
-= UNITS_PER_WORD
;
9720 /* Check that the restrictions on register ranges are met. */
9722 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9723 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9724 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9725 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9729 /* Make sure that the topmost argument register is not saved twice.
9730 The checks above ensure that the same is then true for the other
9731 argument registers. */
9732 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9735 /* Pass back information, if requested. */
9738 info
->nargs
= nargs
;
9740 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9746 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9747 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9748 the null terminator. */
9751 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9752 unsigned int max_reg
)
9754 if (min_reg
!= max_reg
)
9755 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9757 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9761 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9762 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9765 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9767 static char buffer
[300];
9769 struct mips16e_save_restore_info info
;
9770 unsigned int i
, end
;
9773 /* Parse the pattern. */
9774 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9777 /* Add the mnemonic. */
9778 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9781 /* Save the arguments. */
9783 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9784 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9785 else if (info
.nargs
== 1)
9786 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9788 /* Emit the amount of stack space to allocate or deallocate. */
9789 s
+= sprintf (s
, "%d", (int) info
.size
);
9791 /* Save or restore $16. */
9792 if (BITSET_P (info
.mask
, 16))
9793 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9795 /* Save or restore $17. */
9796 if (BITSET_P (info
.mask
, 17))
9797 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9799 /* Save or restore registers in the range $s2...$s8, which
9800 mips16e_s2_s8_regs lists in decreasing order. Note that this
9801 is a software register range; the hardware registers are not
9802 numbered consecutively. */
9803 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9804 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9806 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9807 mips16e_s2_s8_regs
[i
]);
9809 /* Save or restore registers in the range $a0...$a3. */
9810 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9811 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9813 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9814 mips16e_a0_a3_regs
[end
- 1]);
9816 /* Save or restore $31. */
9817 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9818 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9823 /* Return true if the current function returns its value in a floating-point
9824 register in MIPS16 mode. */
9827 mips16_cfun_returns_in_fpr_p (void)
9829 tree return_type
= DECL_RESULT (current_function_decl
);
9830 return (TARGET_MIPS16
9831 && TARGET_HARD_FLOAT_ABI
9832 && !aggregate_value_p (return_type
, current_function_decl
)
9833 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9836 /* Return true if predicate PRED is true for at least one instruction.
9837 Cache the result in *CACHE, and assume that the result is true
9838 if *CACHE is already true. */
9841 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
9847 push_topmost_sequence ();
9848 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9849 if (USEFUL_INSN_P (insn
) && pred (insn
))
9854 pop_topmost_sequence ();
9859 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9860 See mips_cfun_has_inflexible_gp_ref_p for details. */
9863 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
9865 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9866 indicate that the target could be a traditional MIPS
9867 lazily-binding stub. */
9868 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9871 /* Return true if the current function refers to the global pointer
9872 in a way that forces $28 to be valid. This means that we can't
9873 change the choice of global pointer, even for NewABI code.
9875 One example of this (and one which needs several checks) is that
9876 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9877 (This restriction does not apply to PLTs.) */
9880 mips_cfun_has_inflexible_gp_ref_p (void)
9882 /* If the function has a nonlocal goto, $28 must hold the correct
9883 global pointer for the target function. That is, the target
9884 of the goto implicitly uses $28. */
9885 if (crtl
->has_nonlocal_goto
)
9888 if (TARGET_ABICALLS_PIC2
)
9890 /* Symbolic accesses implicitly use the global pointer unless
9891 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9892 might go to traditional MIPS lazy-binding stubs. */
9893 if (!TARGET_EXPLICIT_RELOCS
)
9896 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9897 can be lazily-bound. */
9901 /* MIPS16 functions that return in FPRs need to call an
9902 external libgcc routine. This call is only made explict
9903 during mips_expand_epilogue, and it too might be lazily bound. */
9904 if (mips16_cfun_returns_in_fpr_p ())
9908 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9909 mips_insn_has_inflexible_gp_ref_p
);
9912 /* Return true if INSN refers to the global pointer in a "flexible" way.
9913 See mips_cfun_has_flexible_gp_ref_p for details. */
9916 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
9918 return (get_attr_got (insn
) != GOT_UNSET
9919 || mips_small_data_pattern_p (PATTERN (insn
))
9920 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9923 /* Return true if the current function references the global pointer,
9924 but if those references do not inherently require the global pointer
9925 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9928 mips_cfun_has_flexible_gp_ref_p (void)
9930 /* Reload can sometimes introduce constant pool references
9931 into a function that otherwise didn't need them. For example,
9932 suppose we have an instruction like:
9934 (set (reg:DF R1) (float:DF (reg:SI R2)))
9936 If R2 turns out to be a constant such as 1, the instruction may
9937 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9938 the option of using this constant if R2 doesn't get allocated
9941 In cases like these, reload will have added the constant to the
9942 pool but no instruction will yet refer to it. */
9943 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9946 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9947 mips_insn_has_flexible_gp_ref_p
);
9950 /* Return the register that should be used as the global pointer
9951 within this function. Return INVALID_REGNUM if the function
9952 doesn't need a global pointer. */
9955 mips_global_pointer (void)
9959 /* $gp is always available unless we're using a GOT. */
9960 if (!TARGET_USE_GOT
)
9961 return GLOBAL_POINTER_REGNUM
;
9963 /* If there are inflexible references to $gp, we must use the
9964 standard register. */
9965 if (mips_cfun_has_inflexible_gp_ref_p ())
9966 return GLOBAL_POINTER_REGNUM
;
9968 /* If there are no current references to $gp, then the only uses
9969 we can introduce later are those involved in long branches. */
9970 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9971 return INVALID_REGNUM
;
9973 /* If the global pointer is call-saved, try to use a call-clobbered
9975 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9976 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9977 if (!df_regs_ever_live_p (regno
)
9978 && call_really_used_regs
[regno
]
9979 && !fixed_regs
[regno
]
9980 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9983 return GLOBAL_POINTER_REGNUM
;
9986 /* Return true if the current function's prologue must load the global
9987 pointer value into pic_offset_table_rtx and store the same value in
9988 the function's cprestore slot (if any).
9990 One problem we have to deal with is that, when emitting GOT-based
9991 position independent code, long-branch sequences will need to load
9992 the address of the branch target from the GOT. We don't know until
9993 the very end of compilation whether (and where) the function needs
9994 long branches, so we must ensure that _any_ branch can access the
9995 global pointer in some form. However, we do not want to pessimize
9996 the usual case in which all branches are short.
9998 We handle this as follows:
10000 (1) During reload, we set cfun->machine->global_pointer to
10001 INVALID_REGNUM if we _know_ that the current function
10002 doesn't need a global pointer. This is only valid if
10003 long branches don't need the GOT.
10005 Otherwise, we assume that we might need a global pointer
10006 and pick an appropriate register.
10008 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10009 we ensure that the global pointer is available at every
10010 block boundary bar entry and exit. We do this in one of two ways:
10012 - If the function has a cprestore slot, we ensure that this
10013 slot is valid at every branch. However, as explained in
10014 point (6) below, there is no guarantee that pic_offset_table_rtx
10015 itself is valid if new uses of the global pointer are introduced
10016 after the first post-epilogue split.
10018 We guarantee that the cprestore slot is valid by loading it
10019 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10020 this register live at every block boundary bar function entry
10021 and exit. It is then invalid to move the load (and thus the
10022 preceding store) across a block boundary.
10024 - If the function has no cprestore slot, we guarantee that
10025 pic_offset_table_rtx itself is valid at every branch.
10027 See mips_eh_uses for the handling of the register liveness.
10029 (3) During prologue and epilogue generation, we emit "ghost"
10030 placeholder instructions to manipulate the global pointer.
10032 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10033 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10034 that the function needs a global pointer. (There is no need to set
10035 them earlier than this, and doing it as late as possible leads to
10036 fewer false positives.)
10038 (5) If cfun->machine->must_initialize_gp_p is true during a
10039 split_insns pass, we split the ghost instructions into real
10040 instructions. These split instructions can then be optimized in
10041 the usual way. Otherwise, we keep the ghost instructions intact,
10042 and optimize for the case where they aren't needed. We still
10043 have the option of splitting them later, if we need to introduce
10044 new uses of the global pointer.
10046 For example, the scheduler ignores a ghost instruction that
10047 stores $28 to the stack, but it handles the split form of
10048 the ghost instruction as an ordinary store.
10050 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10051 is true during the first post-epilogue split_insns pass, we split
10052 calls and restore_gp patterns into instructions that explicitly
10053 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10054 we split these patterns into instructions that _don't_ load from
10055 the cprestore slot.
10057 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10058 time of the split, then any instructions that exist at that time
10059 can make free use of pic_offset_table_rtx. However, if we want
10060 to introduce new uses of the global pointer after the split,
10061 we must explicitly load the value from the cprestore slot, since
10062 pic_offset_table_rtx itself might not be valid at a given point
10065 The idea is that we want to be able to delete redundant
10066 loads from the cprestore slot in the usual case where no
10067 long branches are needed.
10069 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10070 of md_reorg, we decide whether the global pointer is needed for
10071 long branches. If so, we set cfun->machine->must_initialize_gp_p
10072 to true and split the ghost instructions into real instructions
10075 Note that the ghost instructions must have a zero length for three reasons:
10077 - Giving the length of the underlying $gp sequence might cause
10078 us to use long branches in cases where they aren't really needed.
10080 - They would perturb things like alignment calculations.
10082 - More importantly, the hazard detection in md_reorg relies on
10083 empty instructions having a zero length.
10085 If we find a long branch and split the ghost instructions at the
10086 end of md_reorg, the split could introduce more long branches.
10087 That isn't a problem though, because we still do the split before
10088 the final shorten_branches pass.
10090 This is extremely ugly, but it seems like the best compromise between
10091 correctness and efficiency. */
10094 mips_must_initialize_gp_p (void)
10096 return cfun
->machine
->must_initialize_gp_p
;
10099 /* Return true if REGNO is a register that is ordinarily call-clobbered
10100 but must nevertheless be preserved by an interrupt handler. */
10103 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10105 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10106 && MD_REG_P (regno
))
10109 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10112 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
10114 /* $0 is hard-wired. */
10115 if (regno
== GP_REG_FIRST
)
10118 /* The interrupt handler can treat kernel registers as
10119 scratch registers. */
10120 if (KERNEL_REG_P (regno
))
10123 /* The function will return the stack pointer to its original value
10125 if (regno
== STACK_POINTER_REGNUM
)
10128 /* Otherwise, return true for registers that aren't ordinarily
10130 return call_really_used_regs
[regno
];
10136 /* Return true if the current function should treat register REGNO
10140 mips_cfun_call_saved_reg_p (unsigned int regno
)
10142 /* If the user makes an ordinarily-call-saved register global,
10143 that register is no longer call-saved. */
10144 if (global_regs
[regno
])
10147 /* Interrupt handlers need to save extra registers. */
10148 if (cfun
->machine
->interrupt_handler_p
10149 && mips_interrupt_extra_call_saved_reg_p (regno
))
10152 /* call_insns preserve $28 unless they explicitly say otherwise,
10153 so call_really_used_regs[] treats $28 as call-saved. However,
10154 we want the ABI property rather than the default call_insn
10156 return (regno
== GLOBAL_POINTER_REGNUM
10157 ? TARGET_CALL_SAVED_GP
10158 : !call_really_used_regs
[regno
]);
10161 /* Return true if the function body might clobber register REGNO.
10162 We know that REGNO is call-saved. */
10165 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10167 /* Some functions should be treated as clobbering all call-saved
10169 if (crtl
->saves_all_registers
)
10172 /* DF handles cases where a register is explicitly referenced in
10173 the rtl. Incoming values are passed in call-clobbered registers,
10174 so we can assume that any live call-saved register is set within
10176 if (df_regs_ever_live_p (regno
))
10179 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10180 These clobbers are not explicit in the rtl. */
10181 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10184 /* If we're using a call-saved global pointer, the function's
10185 prologue will need to set it up. */
10186 if (cfun
->machine
->global_pointer
== regno
)
10189 /* The function's prologue will need to set the frame pointer if
10190 frame_pointer_needed. */
10191 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10194 /* If a MIPS16 function returns a value in FPRs, its epilogue
10195 will need to call an external libgcc routine. This yet-to-be
10196 generated call_insn will clobber $31. */
10197 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10200 /* If REGNO is ordinarily call-clobbered, we must assume that any
10201 called function could modify it. */
10202 if (cfun
->machine
->interrupt_handler_p
10204 && mips_interrupt_extra_call_saved_reg_p (regno
))
10210 /* Return true if the current function must save register REGNO. */
10213 mips_save_reg_p (unsigned int regno
)
10215 if (mips_cfun_call_saved_reg_p (regno
))
10217 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10220 /* Save both registers in an FPR pair if either one is used. This is
10221 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10222 register to be used without the even register. */
10223 if (FP_REG_P (regno
)
10224 && MAX_FPRS_PER_FMT
== 2
10225 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10229 /* We need to save the incoming return address if __builtin_eh_return
10230 is being used to set a different return address. */
10231 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10237 /* Populate the current function's mips_frame_info structure.
10239 MIPS stack frames look like:
10241 +-------------------------------+
10243 | incoming stack arguments |
10245 +-------------------------------+
10247 | caller-allocated save area |
10248 A | for register arguments |
10250 +-------------------------------+ <-- incoming stack pointer
10252 | callee-allocated save area |
10253 B | for arguments that are |
10254 | split between registers and |
10257 +-------------------------------+ <-- arg_pointer_rtx
10259 C | callee-allocated save area |
10260 | for register varargs |
10262 +-------------------------------+ <-- frame_pointer_rtx
10263 | | + cop0_sp_offset
10264 | COP0 reg save area | + UNITS_PER_WORD
10266 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10267 | | + UNITS_PER_WORD
10268 | accumulator save area |
10270 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10271 | | + UNITS_PER_HWFPVALUE
10274 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10275 | | + UNITS_PER_WORD
10278 +-------------------------------+ <-- frame_pointer_rtx with
10279 | | \ -fstack-protector
10280 | local variables | | var_size
10282 +-------------------------------+
10284 | $gp save area | | cprestore_size
10286 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10288 | outgoing stack arguments | |
10290 +-------------------------------+ | args_size
10292 | caller-allocated save area | |
10293 | for register arguments | |
10295 +-------------------------------+ <-- stack_pointer_rtx
10296 frame_pointer_rtx without
10298 hard_frame_pointer_rtx for
10301 At least two of A, B and C will be empty.
10303 Dynamic stack allocations such as alloca insert data at point P.
10304 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10305 hard_frame_pointer_rtx unchanged. */
10308 mips_compute_frame_info (void)
10310 struct mips_frame_info
*frame
;
10311 HOST_WIDE_INT offset
, size
;
10312 unsigned int regno
, i
;
10314 /* Set this function's interrupt properties. */
10315 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10317 if (mips_isa_rev
< 2)
10318 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10319 else if (TARGET_HARD_FLOAT
)
10320 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10321 else if (TARGET_MIPS16
)
10322 error ("interrupt handlers cannot be MIPS16 functions");
10325 cfun
->machine
->interrupt_handler_p
= true;
10326 cfun
->machine
->use_shadow_register_set_p
=
10327 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10328 cfun
->machine
->keep_interrupts_masked_p
=
10329 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10330 cfun
->machine
->use_debug_exception_return_p
=
10331 mips_use_debug_exception_return_p (TREE_TYPE
10332 (current_function_decl
));
10336 frame
= &cfun
->machine
->frame
;
10337 memset (frame
, 0, sizeof (*frame
));
10338 size
= get_frame_size ();
10340 cfun
->machine
->global_pointer
= mips_global_pointer ();
10342 /* The first two blocks contain the outgoing argument area and the $gp save
10343 slot. This area isn't needed in leaf functions, but if the
10344 target-independent frame size is nonzero, we have already committed to
10345 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10346 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10348 /* The MIPS 3.0 linker does not like functions that dynamically
10349 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10350 looks like we are trying to create a second frame pointer to the
10351 function, so allocate some stack space to make it happy. */
10352 if (cfun
->calls_alloca
)
10353 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10355 frame
->args_size
= 0;
10356 frame
->cprestore_size
= 0;
10360 frame
->args_size
= crtl
->outgoing_args_size
;
10361 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10363 offset
= frame
->args_size
+ frame
->cprestore_size
;
10365 /* Move above the local variables. */
10366 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10367 offset
+= frame
->var_size
;
10369 /* Find out which GPRs we need to save. */
10370 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10371 if (mips_save_reg_p (regno
))
10374 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10377 /* If this function calls eh_return, we must also save and restore the
10378 EH data registers. */
10379 if (crtl
->calls_eh_return
)
10380 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10383 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10386 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10387 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10388 save all later registers too. */
10389 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10391 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10392 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10393 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10394 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10397 /* Move above the GPR save area. */
10398 if (frame
->num_gp
> 0)
10400 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10401 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10404 /* Find out which FPRs we need to save. This loop must iterate over
10405 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10406 if (TARGET_HARD_FLOAT
)
10407 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10408 if (mips_save_reg_p (regno
))
10410 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10411 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10414 /* Move above the FPR save area. */
10415 if (frame
->num_fp
> 0)
10417 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10418 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10421 /* Add in space for the interrupt context information. */
10422 if (cfun
->machine
->interrupt_handler_p
)
10425 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10428 frame
->acc_mask
|= (1 << 0);
10431 /* Check accumulators 1, 2, 3. */
10432 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10433 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10436 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10439 /* All interrupt context functions need space to preserve STATUS. */
10440 frame
->num_cop0_regs
++;
10442 /* If we don't keep interrupts masked, we need to save EPC. */
10443 if (!cfun
->machine
->keep_interrupts_masked_p
)
10444 frame
->num_cop0_regs
++;
10447 /* Move above the accumulator save area. */
10448 if (frame
->num_acc
> 0)
10450 /* Each accumulator needs 2 words. */
10451 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10452 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10455 /* Move above the COP0 register save area. */
10456 if (frame
->num_cop0_regs
> 0)
10458 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10459 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10462 /* Move above the callee-allocated varargs save area. */
10463 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10464 frame
->arg_pointer_offset
= offset
;
10466 /* Move above the callee-allocated area for pretend stack arguments. */
10467 offset
+= crtl
->args
.pretend_args_size
;
10468 frame
->total_size
= offset
;
10470 /* Work out the offsets of the save areas from the top of the frame. */
10471 if (frame
->gp_sp_offset
> 0)
10472 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10473 if (frame
->fp_sp_offset
> 0)
10474 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10475 if (frame
->acc_sp_offset
> 0)
10476 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10477 if (frame
->num_cop0_regs
> 0)
10478 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10480 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10481 arguments. This tends to increase the chances of using unextended
10482 instructions for local variables and incoming arguments. */
10484 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10487 /* Return the style of GP load sequence that is being used for the
10488 current function. */
10490 enum mips_loadgp_style
10491 mips_current_loadgp_style (void)
10493 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10494 return LOADGP_NONE
;
10496 if (TARGET_RTP_PIC
)
10499 if (TARGET_ABSOLUTE_ABICALLS
)
10500 return LOADGP_ABSOLUTE
;
10502 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10505 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10508 mips_frame_pointer_required (void)
10510 /* If the function contains dynamic stack allocations, we need to
10511 use the frame pointer to access the static parts of the frame. */
10512 if (cfun
->calls_alloca
)
10515 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10516 reload may be unable to compute the address of a local variable,
10517 since there is no way to add a large constant to the stack pointer
10518 without using a second temporary register. */
10521 mips_compute_frame_info ();
10522 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10529 /* Make sure that we're not trying to eliminate to the wrong hard frame
10533 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10535 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10538 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10539 or argument pointer. TO is either the stack pointer or hard frame
10543 mips_initial_elimination_offset (int from
, int to
)
10545 HOST_WIDE_INT offset
;
10547 mips_compute_frame_info ();
10549 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10552 case FRAME_POINTER_REGNUM
:
10553 if (FRAME_GROWS_DOWNWARD
)
10554 offset
= (cfun
->machine
->frame
.args_size
10555 + cfun
->machine
->frame
.cprestore_size
10556 + cfun
->machine
->frame
.var_size
);
10561 case ARG_POINTER_REGNUM
:
10562 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10566 gcc_unreachable ();
10569 if (to
== HARD_FRAME_POINTER_REGNUM
)
10570 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10575 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10578 mips_extra_live_on_entry (bitmap regs
)
10580 if (TARGET_USE_GOT
)
10582 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10583 the global pointer. */
10584 if (!TARGET_ABSOLUTE_ABICALLS
)
10585 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10587 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10588 the global pointer. */
10590 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10592 /* See the comment above load_call<mode> for details. */
10593 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10597 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10601 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10606 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10609 /* Emit code to change the current function's return address to
10610 ADDRESS. SCRATCH is available as a scratch register, if needed.
10611 ADDRESS and SCRATCH are both word-mode GPRs. */
10614 mips_set_return_address (rtx address
, rtx scratch
)
10618 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10619 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10620 cfun
->machine
->frame
.gp_sp_offset
);
10621 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10624 /* Return true if the current function has a cprestore slot. */
10627 mips_cfun_has_cprestore_slot_p (void)
10629 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10630 && cfun
->machine
->frame
.cprestore_size
> 0);
10633 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10634 cprestore slot. LOAD_P is true if the caller wants to load from
10635 the cprestore slot; it is false if the caller wants to store to
10639 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10642 const struct mips_frame_info
*frame
;
10644 frame
= &cfun
->machine
->frame
;
10645 /* .cprestore always uses the stack pointer instead of the frame pointer.
10646 We have a free choice for direct stores for non-MIPS16 functions,
10647 and for MIPS16 functions whose cprestore slot is in range of the
10648 stack pointer. Using the stack pointer would sometimes give more
10649 (early) scheduling freedom, but using the frame pointer would
10650 sometimes give more (late) scheduling freedom. It's hard to
10651 predict which applies to a given function, so let's keep things
10654 Loads must always use the frame pointer in functions that call
10655 alloca, and there's little benefit to using the stack pointer
10657 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10659 *base
= hard_frame_pointer_rtx
;
10660 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10664 *base
= stack_pointer_rtx
;
10665 *offset
= frame
->args_size
;
10669 /* Return true if X is the load or store address of the cprestore slot;
10670 LOAD_P says which. */
10673 mips_cprestore_address_p (rtx x
, bool load_p
)
10675 rtx given_base
, required_base
;
10676 HOST_WIDE_INT given_offset
, required_offset
;
10678 mips_split_plus (x
, &given_base
, &given_offset
);
10679 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10680 return given_base
== required_base
&& given_offset
== required_offset
;
10683 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10684 going to load from it, false if we are going to store to it.
10685 Use TEMP as a temporary register if need be. */
10688 mips_cprestore_slot (rtx temp
, bool load_p
)
10691 HOST_WIDE_INT offset
;
10693 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10694 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10697 /* Emit instructions to save global pointer value GP into cprestore
10698 slot MEM. OFFSET is the offset that MEM applies to the base register.
10700 MEM may not be a legitimate address. If it isn't, TEMP is a
10701 temporary register that can be used, otherwise it is a SCRATCH. */
10704 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10706 if (TARGET_CPRESTORE_DIRECTIVE
)
10708 gcc_assert (gp
== pic_offset_table_rtx
);
10709 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10712 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10715 /* Restore $gp from its save slot, using TEMP as a temporary base register
10716 if need be. This function is for o32 and o64 abicalls only.
10718 See mips_must_initialize_gp_p for details about how we manage the
10722 mips_restore_gp_from_cprestore_slot (rtx temp
)
10724 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10726 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10728 emit_note (NOTE_INSN_DELETED
);
10734 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10735 mips_emit_move (pic_offset_table_rtx
, temp
);
10738 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10739 if (!TARGET_EXPLICIT_RELOCS
)
10740 emit_insn (gen_blockage ());
10743 /* A function to save or store a register. The first argument is the
10744 register and the second is the stack slot. */
10745 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10747 /* Use FN to save or restore register REGNO. MODE is the register's
10748 mode and OFFSET is the offset of its save slot from the current
10752 mips_save_restore_reg (machine_mode mode
, int regno
,
10753 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10757 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10759 fn (gen_rtx_REG (mode
, regno
), mem
);
10762 /* Call FN for each accumlator that is saved by the current function.
10763 SP_OFFSET is the offset of the current stack pointer from the start
10767 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10769 HOST_WIDE_INT offset
;
10772 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10773 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10775 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10776 offset
-= UNITS_PER_WORD
;
10777 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10778 offset
-= UNITS_PER_WORD
;
10781 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10782 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10783 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10785 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10786 offset
-= UNITS_PER_WORD
;
10790 /* Save register REG to MEM. Make the instruction frame-related. */
10793 mips_save_reg (rtx reg
, rtx mem
)
10795 if (GET_MODE (reg
) == DFmode
10796 && (!TARGET_FLOAT64
10797 || mips_abi
== ABI_32
))
10801 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10803 x1
= mips_frame_set (mips_subword (mem
, false),
10804 mips_subword (reg
, false));
10805 x2
= mips_frame_set (mips_subword (mem
, true),
10806 mips_subword (reg
, true));
10807 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10810 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10813 /* Capture the register combinations that are allowed in a SWM or LWM
10814 instruction. The entries are ordered by number of registers set in
10815 the mask. We also ignore the single register encodings because a
10816 normal SW/LW is preferred. */
10818 static const unsigned int umips_swm_mask
[17] = {
10819 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10820 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10821 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10822 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10826 static const unsigned int umips_swm_encoding
[17] = {
10827 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10830 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10831 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10832 stack pointer of the topmost save slot.
10834 Remove from *MASK all registers that were handled using LWM and SWM.
10835 Update *OFFSET so that it points to the first unused save slot. */
10838 umips_build_save_restore (mips_save_restore_fn fn
,
10839 unsigned *mask
, HOST_WIDE_INT
*offset
)
10843 rtx pattern
, set
, reg
, mem
;
10844 HOST_WIDE_INT this_offset
;
10847 /* Try matching $16 to $31 (s0 to ra). */
10848 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10849 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10852 if (i
== ARRAY_SIZE (umips_swm_mask
))
10855 /* Get the offset of the lowest save slot. */
10856 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10857 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10859 /* LWM/SWM can only support offsets from -2048 to 2047. */
10860 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10863 /* Create the final PARALLEL. */
10864 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10865 this_base
= stack_pointer_rtx
;
10867 /* For registers $16-$23 and $30. */
10868 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10870 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10871 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10872 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10873 *mask
&= ~(1 << regno
);
10874 reg
= gen_rtx_REG (SImode
, regno
);
10875 if (fn
== mips_save_reg
)
10876 set
= mips_frame_set (mem
, reg
);
10879 set
= gen_rtx_SET (reg
, mem
);
10880 mips_add_cfa_restore (reg
);
10882 XVECEXP (pattern
, 0, j
) = set
;
10885 /* For register $31. */
10886 if (umips_swm_encoding
[i
] >> 4)
10888 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10889 *mask
&= ~(1 << 31);
10890 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10891 reg
= gen_rtx_REG (SImode
, 31);
10892 if (fn
== mips_save_reg
)
10893 set
= mips_frame_set (mem
, reg
);
10896 set
= gen_rtx_SET (reg
, mem
);
10897 mips_add_cfa_restore (reg
);
10899 XVECEXP (pattern
, 0, j
) = set
;
10902 pattern
= emit_insn (pattern
);
10903 if (fn
== mips_save_reg
)
10904 RTX_FRAME_RELATED_P (pattern
) = 1;
10906 /* Adjust the last offset. */
10907 *offset
-= UNITS_PER_WORD
* nregs
;
10912 /* Call FN for each register that is saved by the current function.
10913 SP_OFFSET is the offset of the current stack pointer from the start
10917 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10918 mips_save_restore_fn fn
)
10920 machine_mode fpr_mode
;
10922 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10923 HOST_WIDE_INT offset
;
10926 /* Save registers starting from high to low. The debuggers prefer at least
10927 the return register be stored at func+4, and also it allows us not to
10928 need a nop in the epilogue if at least one register is reloaded in
10929 addition to return address. */
10930 offset
= frame
->gp_sp_offset
- sp_offset
;
10931 mask
= frame
->mask
;
10933 if (TARGET_MICROMIPS
)
10934 umips_build_save_restore (fn
, &mask
, &offset
);
10936 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10937 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10939 /* Record the ra offset for use by mips_function_profiler. */
10940 if (regno
== RETURN_ADDR_REGNUM
)
10941 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10942 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10943 offset
-= UNITS_PER_WORD
;
10946 /* This loop must iterate over the same space as its companion in
10947 mips_compute_frame_info. */
10948 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10949 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10950 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10951 regno
>= FP_REG_FIRST
;
10952 regno
-= MAX_FPRS_PER_FMT
)
10953 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10955 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
10956 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
10958 if (fixed_regs
[regno
])
10959 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
10961 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
10964 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10965 offset
-= GET_MODE_SIZE (fpr_mode
);
10969 /* Return true if a move between register REGNO and its save slot (MEM)
10970 can be done in a single move. LOAD_P is true if we are loading
10971 from the slot, false if we are storing to it. */
10974 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10976 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10977 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10980 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10981 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10984 /* Emit a move from SRC to DEST, given that one of them is a register
10985 save slot and that the other is a register. TEMP is a temporary
10986 GPR of the same mode that is available if need be. */
10989 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10991 unsigned int regno
;
10996 regno
= REGNO (src
);
11001 regno
= REGNO (dest
);
11005 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
11007 /* We don't yet know whether we'll need this instruction or not.
11008 Postpone the decision by emitting a ghost move. This move
11009 is specifically not frame-related; only the split version is. */
11011 emit_insn (gen_move_gpdi (dest
, src
));
11013 emit_insn (gen_move_gpsi (dest
, src
));
11017 if (regno
== HI_REGNUM
)
11021 mips_emit_move (temp
, src
);
11023 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
11024 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
11026 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
11027 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
11032 emit_insn (gen_mfhidi_ti (temp
,
11033 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
11035 emit_insn (gen_mfhisi_di (temp
,
11036 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
11037 mips_emit_move (dest
, temp
);
11040 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
11041 mips_emit_move (dest
, src
);
11044 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
11045 mips_emit_move (temp
, src
);
11046 mips_emit_move (dest
, temp
);
11049 mips_set_frame_expr (mips_frame_set (dest
, src
));
11052 /* If we're generating n32 or n64 abicalls, and the current function
11053 does not use $28 as its global pointer, emit a cplocal directive.
11054 Use pic_offset_table_rtx as the argument to the directive. */
11057 mips_output_cplocal (void)
11059 if (!TARGET_EXPLICIT_RELOCS
11060 && mips_must_initialize_gp_p ()
11061 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
11062 output_asm_insn (".cplocal %+", 0);
11065 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11068 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11070 const char *fnname
;
11072 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11073 floating-point arguments. */
11075 && TARGET_HARD_FLOAT_ABI
11076 && crtl
->args
.info
.fp_code
!= 0)
11077 mips16_build_function_stub ();
11079 /* Get the function name the same way that toplev.c does before calling
11080 assemble_start_function. This is needed so that the name used here
11081 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11082 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11083 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11085 /* Output MIPS-specific frame information. */
11086 if (!flag_inhibit_size_directive
)
11088 const struct mips_frame_info
*frame
;
11090 frame
= &cfun
->machine
->frame
;
11092 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11094 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11095 "# vars= " HOST_WIDE_INT_PRINT_DEC
11097 ", args= " HOST_WIDE_INT_PRINT_DEC
11098 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11099 reg_names
[frame_pointer_needed
11100 ? HARD_FRAME_POINTER_REGNUM
11101 : STACK_POINTER_REGNUM
],
11102 (frame_pointer_needed
11103 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11104 : frame
->total_size
),
11105 reg_names
[RETURN_ADDR_REGNUM
],
11107 frame
->num_gp
, frame
->num_fp
,
11109 frame
->cprestore_size
);
11111 /* .mask MASK, OFFSET. */
11112 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11113 frame
->mask
, frame
->gp_save_offset
);
11115 /* .fmask MASK, OFFSET. */
11116 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11117 frame
->fmask
, frame
->fp_save_offset
);
11120 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11121 Also emit the ".set noreorder; .set nomacro" sequence for functions
11123 if (mips_must_initialize_gp_p ()
11124 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11128 /* This is a fixed-form sequence. The position of the
11129 first two instructions is important because of the
11130 way _gp_disp is defined. */
11131 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11132 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11133 output_asm_insn ("sll\t$2,16", 0);
11134 output_asm_insn ("addu\t$2,$3", 0);
11138 /* .cpload must be in a .set noreorder but not a
11139 .set nomacro block. */
11140 mips_push_asm_switch (&mips_noreorder
);
11141 output_asm_insn (".cpload\t%^", 0);
11142 if (!cfun
->machine
->all_noreorder_p
)
11143 mips_pop_asm_switch (&mips_noreorder
);
11145 mips_push_asm_switch (&mips_nomacro
);
11148 else if (cfun
->machine
->all_noreorder_p
)
11150 mips_push_asm_switch (&mips_noreorder
);
11151 mips_push_asm_switch (&mips_nomacro
);
11154 /* Tell the assembler which register we're using as the global
11155 pointer. This is needed for thunks, since they can use either
11156 explicit relocs or assembler macros. */
11157 mips_output_cplocal ();
11160 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11163 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
11164 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11166 const char *fnname
;
11168 /* Reinstate the normal $gp. */
11169 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11170 mips_output_cplocal ();
11172 if (cfun
->machine
->all_noreorder_p
)
11174 mips_pop_asm_switch (&mips_nomacro
);
11175 mips_pop_asm_switch (&mips_noreorder
);
11178 /* Get the function name the same way that toplev.c does before calling
11179 assemble_start_function. This is needed so that the name used here
11180 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11181 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11182 mips_end_function_definition (fnname
);
11185 /* Emit an optimisation barrier for accesses to the current frame. */
11188 mips_frame_barrier (void)
11190 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11194 /* The __gnu_local_gp symbol. */
11196 static GTY(()) rtx mips_gnu_local_gp
;
11198 /* If we're generating n32 or n64 abicalls, emit instructions
11199 to set up the global pointer. */
11202 mips_emit_loadgp (void)
11204 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11206 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11207 switch (mips_current_loadgp_style ())
11209 case LOADGP_ABSOLUTE
:
11210 if (mips_gnu_local_gp
== NULL
)
11212 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11213 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11215 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11216 (pic_reg
, mips_gnu_local_gp
)));
11219 case LOADGP_OLDABI
:
11220 /* Added by mips_output_function_prologue. */
11223 case LOADGP_NEWABI
:
11224 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11225 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11226 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11227 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11228 (pic_reg
, offset
, incoming_address
)));
11232 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11233 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11234 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11242 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11243 (pic_offset_table_rtx
, pic_reg
)));
11245 /* Emit a blockage if there are implicit uses of the GP register.
11246 This includes profiled functions, because FUNCTION_PROFILE uses
11248 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11249 emit_insn (gen_loadgp_blockage ());
11252 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11254 #if PROBE_INTERVAL > 32768
11255 #error Cannot use indexed addressing mode for stack probing
11258 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11259 inclusive. These are offsets from the current stack pointer. */
11262 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11265 sorry ("-fstack-check=specific not implemented for MIPS16");
11267 /* See if we have a constant small number of probes to generate. If so,
11268 that's the easy case. */
11269 if (first
+ size
<= 32768)
11273 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11274 it exceeds SIZE. If only one probe is needed, this will not
11275 generate any code. Then probe at FIRST + SIZE. */
11276 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11277 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11280 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11284 /* Otherwise, do the same as above, but in a loop. Note that we must be
11285 extra careful with variables wrapping around because we might be at
11286 the very top (or the very bottom) of the address space and we have
11287 to be able to handle this case properly; in particular, we use an
11288 equality test for the loop condition. */
11291 HOST_WIDE_INT rounded_size
;
11292 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11293 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11295 /* Sanity check for the addressing mode we're going to use. */
11296 gcc_assert (first
<= 32768);
11299 /* Step 1: round SIZE to the previous multiple of the interval. */
11301 rounded_size
= size
& -PROBE_INTERVAL
;
11304 /* Step 2: compute initial and final value of the loop counter. */
11306 /* TEST_ADDR = SP + FIRST. */
11307 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11310 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11311 if (rounded_size
> 32768)
11313 emit_move_insn (r12
, GEN_INT (rounded_size
));
11314 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
11317 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
11321 /* Step 3: the loop
11323 while (TEST_ADDR != LAST_ADDR)
11325 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11329 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11330 until it is equal to ROUNDED_SIZE. */
11332 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11335 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11336 that SIZE is equal to ROUNDED_SIZE. */
11338 if (size
!= rounded_size
)
11339 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11342 /* Make sure nothing is scheduled before we are done. */
11343 emit_insn (gen_blockage ());
11346 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11347 absolute addresses. */
11350 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11352 static int labelno
= 0;
11353 char loop_lab
[32], end_lab
[32], tmp
[64];
11356 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11357 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11359 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11361 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11364 strcpy (tmp
, "%(%<beq\t%0,%1,");
11365 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11367 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11368 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11369 if (TARGET_64BIT
&& TARGET_LONG64
)
11370 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11372 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11374 /* Probe at TEST_ADDR and branch. */
11375 fprintf (asm_out_file
, "\tb\t");
11376 assemble_name_raw (asm_out_file
, loop_lab
);
11377 fputc ('\n', asm_out_file
);
11379 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11381 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11383 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11388 /* Return true if X contains a kernel register. */
11391 mips_refers_to_kernel_reg_p (const_rtx x
)
11393 subrtx_iterator::array_type array
;
11394 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
11395 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
11400 /* Expand the "prologue" pattern. */
11403 mips_expand_prologue (void)
11405 const struct mips_frame_info
*frame
;
11406 HOST_WIDE_INT size
;
11407 unsigned int nargs
;
11409 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11411 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11412 or implicitly. If so, we can commit to using a global pointer
11413 straight away, otherwise we need to defer the decision. */
11414 if (mips_cfun_has_inflexible_gp_ref_p ()
11415 || mips_cfun_has_flexible_gp_ref_p ())
11417 cfun
->machine
->must_initialize_gp_p
= true;
11418 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11421 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11424 frame
= &cfun
->machine
->frame
;
11425 size
= frame
->total_size
;
11427 if (flag_stack_usage_info
)
11428 current_function_static_stack_size
= size
;
11430 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11432 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11434 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11435 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11436 size
- STACK_CHECK_PROTECT
);
11439 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11442 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11443 bytes beforehand; this is enough to cover the register save area
11444 without going out of range. */
11445 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11446 || frame
->num_cop0_regs
> 0)
11448 HOST_WIDE_INT step1
;
11450 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11451 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11453 HOST_WIDE_INT offset
;
11454 unsigned int mask
, regno
;
11456 /* Try to merge argument stores into the save instruction. */
11457 nargs
= mips16e_collect_argument_saves ();
11459 /* Build the save instruction. */
11460 mask
= frame
->mask
;
11461 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11463 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11464 mips_frame_barrier ();
11467 /* Check if we need to save other registers. */
11468 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11469 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11471 offset
-= UNITS_PER_WORD
;
11472 mips_save_restore_reg (word_mode
, regno
,
11473 offset
, mips_save_reg
);
11478 if (cfun
->machine
->interrupt_handler_p
)
11480 HOST_WIDE_INT offset
;
11483 /* If this interrupt is using a shadow register set, we need to
11484 get the stack pointer from the previous register set. */
11485 if (cfun
->machine
->use_shadow_register_set_p
)
11486 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11487 stack_pointer_rtx
));
11489 if (!cfun
->machine
->keep_interrupts_masked_p
)
11491 /* Move from COP0 Cause to K0. */
11492 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11493 gen_rtx_REG (SImode
,
11494 COP0_CAUSE_REG_NUM
)));
11495 /* Move from COP0 EPC to K1. */
11496 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11497 gen_rtx_REG (SImode
,
11498 COP0_EPC_REG_NUM
)));
11501 /* Allocate the first part of the frame. */
11502 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11504 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11505 mips_frame_barrier ();
11508 /* Start at the uppermost location for saving. */
11509 offset
= frame
->cop0_sp_offset
- size
;
11510 if (!cfun
->machine
->keep_interrupts_masked_p
)
11512 /* Push EPC into its stack slot. */
11513 mem
= gen_frame_mem (word_mode
,
11514 plus_constant (Pmode
, stack_pointer_rtx
,
11516 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11517 offset
-= UNITS_PER_WORD
;
11520 /* Move from COP0 Status to K1. */
11521 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11522 gen_rtx_REG (SImode
,
11523 COP0_STATUS_REG_NUM
)));
11525 /* Right justify the RIPL in k0. */
11526 if (!cfun
->machine
->keep_interrupts_masked_p
)
11527 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11528 gen_rtx_REG (SImode
, K0_REG_NUM
),
11529 GEN_INT (CAUSE_IPL
)));
11531 /* Push Status into its stack slot. */
11532 mem
= gen_frame_mem (word_mode
,
11533 plus_constant (Pmode
, stack_pointer_rtx
,
11535 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11536 offset
-= UNITS_PER_WORD
;
11538 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11539 if (!cfun
->machine
->keep_interrupts_masked_p
)
11540 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11543 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11545 if (!cfun
->machine
->keep_interrupts_masked_p
)
11546 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11547 IE is already the correct value, so we don't have to do
11548 anything explicit. */
11549 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11552 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11554 /* Disable interrupts by clearing the KSU, ERL, EXL,
11556 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11559 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11563 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
11566 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11567 mips_frame_barrier ();
11570 mips_for_each_saved_acc (size
, mips_save_reg
);
11571 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11575 /* Allocate the rest of the frame. */
11578 if (SMALL_OPERAND (-size
))
11579 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11581 GEN_INT (-size
)))) = 1;
11584 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11587 /* There are no instructions to add or subtract registers
11588 from the stack pointer, so use the frame pointer as a
11589 temporary. We should always be using a frame pointer
11590 in this case anyway. */
11591 gcc_assert (frame_pointer_needed
);
11592 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11593 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11594 hard_frame_pointer_rtx
,
11595 MIPS_PROLOGUE_TEMP (Pmode
)));
11596 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11599 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11601 MIPS_PROLOGUE_TEMP (Pmode
)));
11603 /* Describe the combined effect of the previous instructions. */
11604 mips_set_frame_expr
11605 (gen_rtx_SET (stack_pointer_rtx
,
11606 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11608 mips_frame_barrier ();
11611 /* Set up the frame pointer, if we're using one. */
11612 if (frame_pointer_needed
)
11614 HOST_WIDE_INT offset
;
11616 offset
= frame
->hard_frame_pointer_offset
;
11619 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11620 RTX_FRAME_RELATED_P (insn
) = 1;
11622 else if (SMALL_OPERAND (offset
))
11624 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11625 stack_pointer_rtx
, GEN_INT (offset
));
11626 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11630 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11631 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11632 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11633 hard_frame_pointer_rtx
,
11634 MIPS_PROLOGUE_TEMP (Pmode
)));
11635 mips_set_frame_expr
11636 (gen_rtx_SET (hard_frame_pointer_rtx
,
11637 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11641 mips_emit_loadgp ();
11643 /* Initialize the $gp save slot. */
11644 if (mips_cfun_has_cprestore_slot_p ())
11646 rtx base
, mem
, gp
, temp
;
11647 HOST_WIDE_INT offset
;
11649 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11650 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11651 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11652 temp
= (SMALL_OPERAND (offset
)
11653 ? gen_rtx_SCRATCH (Pmode
)
11654 : MIPS_PROLOGUE_TEMP (Pmode
));
11655 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11656 (mem
, GEN_INT (offset
), gp
, temp
)));
11658 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11659 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11660 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11663 /* We need to search back to the last use of K0 or K1. */
11664 if (cfun
->machine
->interrupt_handler_p
)
11667 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11669 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11671 /* Emit a move from K1 to COP0 Status after insn. */
11672 gcc_assert (insn
!= NULL_RTX
);
11673 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11674 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11678 /* If we are profiling, make sure no instructions are scheduled before
11679 the call to mcount. */
11681 emit_insn (gen_blockage ());
11684 /* Attach all pending register saves to the previous instruction.
11685 Return that instruction. */
11688 mips_epilogue_emit_cfa_restores (void)
11692 insn
= get_last_insn ();
11693 gcc_assert (insn
&& !REG_NOTES (insn
));
11694 if (mips_epilogue
.cfa_restores
)
11696 RTX_FRAME_RELATED_P (insn
) = 1;
11697 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11698 mips_epilogue
.cfa_restores
= 0;
11703 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11704 now at REG + OFFSET. */
11707 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11711 insn
= mips_epilogue_emit_cfa_restores ();
11712 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11714 RTX_FRAME_RELATED_P (insn
) = 1;
11715 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11716 plus_constant (Pmode
, reg
, offset
),
11718 mips_epilogue
.cfa_reg
= reg
;
11719 mips_epilogue
.cfa_offset
= offset
;
11723 /* Emit instructions to restore register REG from slot MEM. Also update
11724 the cfa_restores list. */
11727 mips_restore_reg (rtx reg
, rtx mem
)
11729 /* There's no MIPS16 instruction to load $31 directly. Load into
11730 $7 instead and adjust the return insn appropriately. */
11731 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11732 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11733 else if (GET_MODE (reg
) == DFmode
11734 && (!TARGET_FLOAT64
11735 || mips_abi
== ABI_32
))
11737 mips_add_cfa_restore (mips_subword (reg
, true));
11738 mips_add_cfa_restore (mips_subword (reg
, false));
11741 mips_add_cfa_restore (reg
);
11743 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11744 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11745 /* The CFA is currently defined in terms of the register whose
11746 value we have just restored. Redefine the CFA in terms of
11747 the stack pointer. */
11748 mips_epilogue_set_cfa (stack_pointer_rtx
,
11749 mips_epilogue
.cfa_restore_sp_offset
);
11752 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11753 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11754 BASE, if not the stack pointer, is available as a temporary. */
11757 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11759 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11762 mips_frame_barrier ();
11763 if (offset
== const0_rtx
)
11765 emit_move_insn (stack_pointer_rtx
, base
);
11766 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11768 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11770 emit_insn (gen_add3_insn (base
, base
, offset
));
11771 mips_epilogue_set_cfa (base
, new_frame_size
);
11772 emit_move_insn (stack_pointer_rtx
, base
);
11776 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11777 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11781 /* Emit any instructions needed before a return. */
11784 mips_expand_before_return (void)
11786 /* When using a call-clobbered gp, we start out with unified call
11787 insns that include instructions to restore the gp. We then split
11788 these unified calls after reload. These split calls explicitly
11789 clobber gp, so there is no need to define
11790 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11792 For consistency, we should also insert an explicit clobber of $28
11793 before return insns, so that the post-reload optimizers know that
11794 the register is not live on exit. */
11795 if (TARGET_CALL_CLOBBERED_GP
)
11796 emit_clobber (pic_offset_table_rtx
);
11799 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11803 mips_expand_epilogue (bool sibcall_p
)
11805 const struct mips_frame_info
*frame
;
11806 HOST_WIDE_INT step1
, step2
;
11809 bool use_jraddiusp_p
= false;
11811 if (!sibcall_p
&& mips_can_use_return_insn ())
11813 emit_jump_insn (gen_return ());
11817 /* In MIPS16 mode, if the return value should go into a floating-point
11818 register, we need to call a helper routine to copy it over. */
11819 if (mips16_cfun_returns_in_fpr_p ())
11820 mips16_copy_fpr_return_value ();
11822 /* Split the frame into two. STEP1 is the amount of stack we should
11823 deallocate before restoring the registers. STEP2 is the amount we
11824 should deallocate afterwards.
11826 Start off by assuming that no registers need to be restored. */
11827 frame
= &cfun
->machine
->frame
;
11828 step1
= frame
->total_size
;
11831 /* Work out which register holds the frame address. */
11832 if (!frame_pointer_needed
)
11833 base
= stack_pointer_rtx
;
11836 base
= hard_frame_pointer_rtx
;
11837 step1
-= frame
->hard_frame_pointer_offset
;
11839 mips_epilogue
.cfa_reg
= base
;
11840 mips_epilogue
.cfa_offset
= step1
;
11841 mips_epilogue
.cfa_restores
= NULL_RTX
;
11843 /* If we need to restore registers, deallocate as much stack as
11844 possible in the second step without going out of range. */
11845 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11846 || frame
->num_cop0_regs
> 0)
11848 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11852 /* Get an rtx for STEP1 that we can add to BASE. */
11853 adjust
= GEN_INT (step1
);
11854 if (!SMALL_OPERAND (step1
))
11856 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11857 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11859 mips_deallocate_stack (base
, adjust
, step2
);
11861 /* If we're using addressing macros, $gp is implicitly used by all
11862 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11864 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11865 emit_insn (gen_blockage ());
11867 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11868 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11870 unsigned int regno
, mask
;
11871 HOST_WIDE_INT offset
;
11874 /* Generate the restore instruction. */
11875 mask
= frame
->mask
;
11876 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11878 /* Restore any other registers manually. */
11879 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11880 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11882 offset
-= UNITS_PER_WORD
;
11883 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11886 /* Restore the remaining registers and deallocate the final bit
11888 mips_frame_barrier ();
11889 emit_insn (restore
);
11890 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11894 /* Restore the registers. */
11895 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11896 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11899 if (cfun
->machine
->interrupt_handler_p
)
11901 HOST_WIDE_INT offset
;
11904 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11905 if (!cfun
->machine
->keep_interrupts_masked_p
)
11907 /* Restore the original EPC. */
11908 mem
= gen_frame_mem (word_mode
,
11909 plus_constant (Pmode
, stack_pointer_rtx
,
11911 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11912 offset
-= UNITS_PER_WORD
;
11914 /* Move to COP0 EPC. */
11915 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11916 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11919 /* Restore the original Status. */
11920 mem
= gen_frame_mem (word_mode
,
11921 plus_constant (Pmode
, stack_pointer_rtx
,
11923 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11924 offset
-= UNITS_PER_WORD
;
11926 /* If we don't use shadow register set, we need to update SP. */
11927 if (!cfun
->machine
->use_shadow_register_set_p
)
11928 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11930 /* The choice of position is somewhat arbitrary in this case. */
11931 mips_epilogue_emit_cfa_restores ();
11933 /* Move to COP0 Status. */
11934 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11935 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11937 else if (TARGET_MICROMIPS
11938 && !crtl
->calls_eh_return
11941 && mips_unsigned_immediate_p (step2
, 5, 2))
11942 use_jraddiusp_p
= true;
11944 /* Deallocate the final bit of the frame. */
11945 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11948 if (!use_jraddiusp_p
)
11949 gcc_assert (!mips_epilogue
.cfa_restores
);
11951 /* Add in the __builtin_eh_return stack adjustment. We need to
11952 use a temporary in MIPS16 code. */
11953 if (crtl
->calls_eh_return
)
11957 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11958 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11959 MIPS_EPILOGUE_TEMP (Pmode
),
11960 EH_RETURN_STACKADJ_RTX
));
11961 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11964 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11966 EH_RETURN_STACKADJ_RTX
));
11971 mips_expand_before_return ();
11972 if (cfun
->machine
->interrupt_handler_p
)
11974 /* Interrupt handlers generate eret or deret. */
11975 if (cfun
->machine
->use_debug_exception_return_p
)
11976 emit_jump_insn (gen_mips_deret ());
11978 emit_jump_insn (gen_mips_eret ());
11984 /* When generating MIPS16 code, the normal
11985 mips_for_each_saved_gpr_and_fpr path will restore the return
11986 address into $7 rather than $31. */
11988 && !GENERATE_MIPS16E_SAVE_RESTORE
11989 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11991 /* simple_returns cannot rely on values that are only available
11992 on paths through the epilogue (because return paths that do
11993 not pass through the epilogue may nevertheless reuse a
11994 simple_return that occurs at the end of the epilogue).
11995 Use a normal return here instead. */
11996 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11997 pat
= gen_return_internal (reg
);
11999 else if (use_jraddiusp_p
)
12000 pat
= gen_jraddiusp (GEN_INT (step2
));
12003 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
12004 pat
= gen_simple_return_internal (reg
);
12006 emit_jump_insn (pat
);
12007 if (use_jraddiusp_p
)
12008 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
12012 /* Search from the beginning to the first use of K0 or K1. */
12013 if (cfun
->machine
->interrupt_handler_p
12014 && !cfun
->machine
->keep_interrupts_masked_p
)
12016 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12018 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12020 gcc_assert (insn
!= NULL_RTX
);
12021 /* Insert disable interrupts before the first use of K0 or K1. */
12022 emit_insn_before (gen_mips_di (), insn
);
12023 emit_insn_before (gen_mips_ehb (), insn
);
12027 /* Return nonzero if this function is known to have a null epilogue.
12028 This allows the optimizer to omit jumps to jumps if no stack
12032 mips_can_use_return_insn (void)
12034 /* Interrupt handlers need to go through the epilogue. */
12035 if (cfun
->machine
->interrupt_handler_p
)
12038 if (!reload_completed
)
12044 /* In MIPS16 mode, a function that returns a floating-point value
12045 needs to arrange to copy the return value into the floating-point
12047 if (mips16_cfun_returns_in_fpr_p ())
12050 return cfun
->machine
->frame
.total_size
== 0;
12053 /* Return true if register REGNO can store a value of mode MODE.
12054 The result of this function is cached in mips_hard_regno_mode_ok. */
12057 mips_hard_regno_mode_ok_p (unsigned int regno
, machine_mode mode
)
12060 enum mode_class mclass
;
12062 if (mode
== CCV2mode
)
12063 return (ISA_HAS_8CC
12064 && ST_REG_P (regno
)
12065 && (regno
- ST_REG_FIRST
) % 2 == 0);
12067 if (mode
== CCV4mode
)
12068 return (ISA_HAS_8CC
12069 && ST_REG_P (regno
)
12070 && (regno
- ST_REG_FIRST
) % 4 == 0);
12072 if (mode
== CCmode
)
12073 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12075 size
= GET_MODE_SIZE (mode
);
12076 mclass
= GET_MODE_CLASS (mode
);
12078 if (GP_REG_P (regno
) && mode
!= CCFmode
)
12079 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12081 if (FP_REG_P (regno
)
12082 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12083 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12085 /* Deny use of odd-numbered registers for 32-bit data for
12086 the o32 FP64A ABI. */
12087 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12090 /* The FPXX ABI requires double-precision values to be placed in
12091 even-numbered registers. Disallow odd-numbered registers with
12092 CCFmode because CCFmode double-precision compares will write a
12093 64-bit value to a register. */
12094 if (mode
== CCFmode
)
12095 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12097 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12098 if (TARGET_LOONGSON_VECTORS
12099 && (mode
== V2SImode
12100 || mode
== V4HImode
12101 || mode
== V8QImode
12102 || mode
== DImode
))
12105 if (mclass
== MODE_FLOAT
12106 || mclass
== MODE_COMPLEX_FLOAT
12107 || mclass
== MODE_VECTOR_FLOAT
)
12108 return size
<= UNITS_PER_FPVALUE
;
12110 /* Allow integer modes that fit into a single register. We need
12111 to put integers into FPRs when using instructions like CVT
12112 and TRUNC. There's no point allowing sizes smaller than a word,
12113 because the FPU has no appropriate load/store instructions. */
12114 if (mclass
== MODE_INT
)
12115 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12118 /* Don't allow vector modes in accumulators. */
12119 if (ACC_REG_P (regno
)
12120 && !VECTOR_MODE_P (mode
)
12121 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12123 if (MD_REG_P (regno
))
12125 /* After a multiplication or division, clobbering HI makes
12126 the value of LO unpredictable, and vice versa. This means
12127 that, for all interesting cases, HI and LO are effectively
12130 We model this by requiring that any value that uses HI
12132 if (size
<= UNITS_PER_WORD
* 2)
12133 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12137 /* DSP accumulators do not have the same restrictions as
12138 HI and LO, so we can treat them as normal doubleword
12140 if (size
<= UNITS_PER_WORD
)
12143 if (size
<= UNITS_PER_WORD
* 2
12144 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12149 if (ALL_COP_REG_P (regno
))
12150 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12152 if (regno
== GOT_VERSION_REGNUM
)
12153 return mode
== SImode
;
12158 /* Implement HARD_REGNO_NREGS. */
12161 mips_hard_regno_nregs (int regno
, machine_mode mode
)
12163 if (ST_REG_P (regno
))
12164 /* The size of FP status registers is always 4, because they only hold
12165 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12166 return (GET_MODE_SIZE (mode
) + 3) / 4;
12168 if (FP_REG_P (regno
))
12169 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12171 /* All other registers are word-sized. */
12172 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12175 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12176 in mips_hard_regno_nregs. */
12179 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12185 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12186 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12188 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
12189 size
= MIN (size
, 4);
12190 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12192 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12194 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
12195 size
= MIN (size
, UNITS_PER_FPREG
);
12196 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12198 if (!hard_reg_set_empty_p (left
))
12199 size
= MIN (size
, UNITS_PER_WORD
);
12200 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12203 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12206 mips_cannot_change_mode_class (machine_mode from
,
12208 enum reg_class rclass
)
12210 /* Allow conversions between different Loongson integer vectors,
12211 and between those vectors and DImode. */
12212 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12213 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12216 /* Otherwise, there are several problems with changing the modes of
12217 values in floating-point registers:
12219 - When a multi-word value is stored in paired floating-point
12220 registers, the first register always holds the low word. We
12221 therefore can't allow FPRs to change between single-word and
12222 multi-word modes on big-endian targets.
12224 - GCC assumes that each word of a multiword register can be
12225 accessed individually using SUBREGs. This is not true for
12226 floating-point registers if they are bigger than a word.
12228 - Loading a 32-bit value into a 64-bit floating-point register
12229 will not sign-extend the value, despite what LOAD_EXTEND_OP
12230 says. We can't allow FPRs to change from SImode to a wider
12231 mode on 64-bit targets.
12233 - If the FPU has already interpreted a value in one format, we
12234 must not ask it to treat the value as having a different
12237 We therefore disallow all mode changes involving FPRs. */
12239 return reg_classes_intersect_p (FP_REGS
, rclass
);
12242 /* Implement target hook small_register_classes_for_mode_p. */
12245 mips_small_register_classes_for_mode_p (machine_mode mode
12248 return TARGET_MIPS16
;
12251 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
12254 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
12260 return TARGET_HARD_FLOAT
;
12263 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
12266 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
12273 /* Implement MODES_TIEABLE_P. */
12276 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12278 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12279 prefer to put one of them in FPRs. */
12280 return (mode1
== mode2
12281 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
12282 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
12285 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12288 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
12290 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
12293 if (reg_class_subset_p (FP_REGS
, rclass
)
12294 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
12297 if (reg_class_subset_p (GR_REGS
, rclass
))
12300 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
12306 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12307 Return a "canonical" class to represent it in later calculations. */
12310 mips_canonicalize_move_class (reg_class_t rclass
)
12312 /* All moves involving accumulator registers have the same cost. */
12313 if (reg_class_subset_p (rclass
, ACC_REGS
))
12316 /* Likewise promote subclasses of general registers to the most
12317 interesting containing class. */
12318 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
12320 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
12321 rclass
= GENERAL_REGS
;
12326 /* Return the cost of moving a value from a register of class FROM to a GPR.
12327 Return 0 for classes that are unions of other classes handled by this
12331 mips_move_to_gpr_cost (reg_class_t from
)
12337 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12341 /* MFLO and MFHI. */
12351 /* This choice of value is historical. */
12359 /* Return the cost of moving a value from a GPR to a register of class TO.
12360 Return 0 for classes that are unions of other classes handled by this
12364 mips_move_from_gpr_cost (reg_class_t to
)
12370 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12374 /* MTLO and MTHI. */
12384 /* This choice of value is historical. */
12392 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12393 maximum of the move costs for subclasses; regclass will work out
12394 the maximum for us. */
12397 mips_register_move_cost (machine_mode mode
,
12398 reg_class_t from
, reg_class_t to
)
12403 from
= mips_canonicalize_move_class (from
);
12404 to
= mips_canonicalize_move_class (to
);
12406 /* Handle moves that can be done without using general-purpose registers. */
12407 if (from
== FP_REGS
)
12409 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12414 /* Handle cases in which only one class deviates from the ideal. */
12415 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12417 return mips_move_from_gpr_cost (to
);
12419 return mips_move_to_gpr_cost (from
);
12421 /* Handles cases that require a GPR temporary. */
12422 cost1
= mips_move_to_gpr_cost (from
);
12425 cost2
= mips_move_from_gpr_cost (to
);
12427 return cost1
+ cost2
;
12433 /* Implement TARGET_REGISTER_PRIORITY. */
12436 mips_register_priority (int hard_regno
)
12438 /* Treat MIPS16 registers with higher priority than other regs. */
12440 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
12445 /* Implement TARGET_MEMORY_MOVE_COST. */
12448 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
12450 return (mips_cost
->memory_latency
12451 + memory_move_secondary_cost (mode
, rclass
, in
));
12454 /* Implement SECONDARY_MEMORY_NEEDED. */
12457 mips_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
12460 /* Ignore spilled pseudos. */
12461 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
12464 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
12465 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
12466 || TARGET_O32_FP64A_ABI
)
12467 && GET_MODE_SIZE (mode
) >= 8)
12473 /* Return the register class required for a secondary register when
12474 copying between one of the registers in RCLASS and value X, which
12475 has mode MODE. X is the source of the move if IN_P, otherwise it
12476 is the destination. Return NO_REGS if no secondary register is
12480 mips_secondary_reload_class (enum reg_class rclass
,
12481 machine_mode mode
, rtx x
, bool)
12485 /* If X is a constant that cannot be loaded into $25, it must be loaded
12486 into some other GPR. No other register class allows a direct move. */
12487 if (mips_dangerous_for_la25_p (x
))
12488 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12490 regno
= true_regnum (x
);
12493 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12494 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12500 /* Copying from accumulator registers to anywhere other than a general
12501 register requires a temporary general register. */
12502 if (reg_class_subset_p (rclass
, ACC_REGS
))
12503 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12504 if (ACC_REG_P (regno
))
12505 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12507 if (reg_class_subset_p (rclass
, FP_REGS
))
12511 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
12512 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12513 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12516 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12517 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12520 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12521 /* We can force the constant to memory and use lwc1
12522 and ldc1. As above, we will use pairs of lwc1s if
12523 ldc1 is not supported. */
12526 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12527 /* In this case we can use mov.fmt. */
12530 /* Otherwise, we need to reload through an integer register. */
12533 if (FP_REG_P (regno
))
12534 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12539 /* Implement TARGET_MODE_REP_EXTENDED. */
12542 mips_mode_rep_extended (machine_mode mode
, machine_mode mode_rep
)
12544 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12545 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12546 return SIGN_EXTEND
;
12551 /* Implement TARGET_VALID_POINTER_MODE. */
12554 mips_valid_pointer_mode (machine_mode mode
)
12556 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12559 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12562 mips_vector_mode_supported_p (machine_mode mode
)
12567 return TARGET_PAIRED_SINGLE_FLOAT
;
12582 return TARGET_LOONGSON_VECTORS
;
12589 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12592 mips_scalar_mode_supported_p (machine_mode mode
)
12594 if (ALL_FIXED_POINT_MODE_P (mode
)
12595 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12598 return default_scalar_mode_supported_p (mode
);
12601 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12603 static machine_mode
12604 mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED
)
12606 if (TARGET_PAIRED_SINGLE_FLOAT
12612 /* Implement TARGET_INIT_LIBFUNCS. */
12615 mips_init_libfuncs (void)
12617 if (TARGET_FIX_VR4120
)
12619 /* Register the special divsi3 and modsi3 functions needed to work
12620 around VR4120 division errata. */
12621 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12622 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12625 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12627 /* Register the MIPS16 -mhard-float stubs. */
12628 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12629 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12630 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12631 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12633 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12634 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12635 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12636 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12637 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12638 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12639 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12641 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12642 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12643 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12645 if (TARGET_DOUBLE_FLOAT
)
12647 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12648 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12649 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12650 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12652 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12653 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12654 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12655 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12656 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12657 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12658 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12660 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12661 "__mips16_extendsfdf2");
12662 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12663 "__mips16_truncdfsf2");
12664 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12665 "__mips16_fix_truncdfsi");
12666 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12667 "__mips16_floatsidf");
12668 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12669 "__mips16_floatunsidf");
12673 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12674 on an external non-MIPS16 routine to implement __sync_synchronize.
12675 Similarly for the rest of the ll/sc libfuncs. */
12678 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12679 init_sync_libfuncs (UNITS_PER_WORD
);
12683 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12686 mips_process_load_label (rtx target
)
12688 rtx base
, gp
, intop
;
12689 HOST_WIDE_INT offset
;
12691 mips_multi_start ();
12695 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12696 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12700 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12701 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12705 gp
= pic_offset_table_rtx
;
12706 if (mips_cfun_has_cprestore_slot_p ())
12708 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12709 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12710 if (!SMALL_OPERAND (offset
))
12712 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12713 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12714 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12717 offset
= CONST_LOW_PART (offset
);
12719 intop
= GEN_INT (offset
);
12720 if (ISA_HAS_LOAD_DELAY
)
12721 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12723 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12725 if (ISA_HAS_LOAD_DELAY
)
12726 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12728 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12729 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12734 /* Return the number of instructions needed to load a label into $AT. */
12736 static unsigned int
12737 mips_load_label_num_insns (void)
12739 if (cfun
->machine
->load_label_num_insns
== 0)
12741 mips_process_load_label (pc_rtx
);
12742 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12744 return cfun
->machine
->load_label_num_insns
;
12747 /* Emit an asm sequence to start a noat block and load the address
12748 of a label into $1. */
12751 mips_output_load_label (rtx target
)
12753 mips_push_asm_switch (&mips_noat
);
12754 if (TARGET_EXPLICIT_RELOCS
)
12756 mips_process_load_label (target
);
12757 mips_multi_write ();
12761 if (Pmode
== DImode
)
12762 output_asm_insn ("dla\t%@,%0", &target
);
12764 output_asm_insn ("la\t%@,%0", &target
);
12768 /* Return the length of INSN. LENGTH is the initial length computed by
12769 attributes in the machine-description file. */
12772 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
12774 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12775 of a PIC long-branch sequence. Substitute the correct value. */
12776 if (length
== MAX_PIC_BRANCH_LENGTH
12778 && INSN_CODE (insn
) >= 0
12779 && get_attr_type (insn
) == TYPE_BRANCH
)
12781 /* Add the branch-over instruction and its delay slot, if this
12782 is a conditional branch. */
12783 length
= simplejump_p (insn
) ? 0 : 8;
12785 /* Add the size of a load into $AT. */
12786 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12788 /* Add the length of an indirect jump, ignoring the delay slot. */
12789 length
+= TARGET_COMPRESSION
? 2 : 4;
12792 /* A unconditional jump has an unfilled delay slot if it is not part
12793 of a sequence. A conditional jump normally has a delay slot, but
12794 does not on MIPS16. */
12795 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12796 length
+= TARGET_MIPS16
? 2 : 4;
12798 /* See how many nops might be needed to avoid hardware hazards. */
12799 if (!cfun
->machine
->ignore_hazard_length_p
12801 && INSN_CODE (insn
) >= 0)
12802 switch (get_attr_hazard (insn
))
12808 length
+= NOP_INSN_LENGTH
;
12812 length
+= NOP_INSN_LENGTH
* 2;
12819 /* Return the assembly code for INSN, which has the operands given by
12820 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12821 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12822 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12823 version of BRANCH_IF_TRUE. */
12826 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
12827 const char *branch_if_true
,
12828 const char *branch_if_false
)
12830 unsigned int length
;
12833 gcc_assert (LABEL_P (operands
[0]));
12835 length
= get_attr_length (insn
);
12838 /* Just a simple conditional branch. */
12839 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12840 return branch_if_true
;
12843 /* Generate a reversed branch around a direct jump. This fallback does
12844 not use branch-likely instructions. */
12845 mips_branch_likely
= false;
12846 rtx_code_label
*not_taken
= gen_label_rtx ();
12847 taken
= operands
[0];
12849 /* Generate the reversed branch to NOT_TAKEN. */
12850 operands
[0] = not_taken
;
12851 output_asm_insn (branch_if_false
, operands
);
12853 /* If INSN has a delay slot, we must provide delay slots for both the
12854 branch to NOT_TAKEN and the conditional jump. We must also ensure
12855 that INSN's delay slot is executed in the appropriate cases. */
12856 if (final_sequence
)
12858 /* This first delay slot will always be executed, so use INSN's
12859 delay slot if is not annulled. */
12860 if (!INSN_ANNULLED_BRANCH_P (insn
))
12862 final_scan_insn (final_sequence
->insn (1),
12863 asm_out_file
, optimize
, 1, NULL
);
12864 final_sequence
->insn (1)->set_deleted ();
12867 output_asm_insn ("nop", 0);
12868 fprintf (asm_out_file
, "\n");
12871 /* Output the unconditional branch to TAKEN. */
12872 if (TARGET_ABSOLUTE_JUMPS
)
12873 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12876 mips_output_load_label (taken
);
12877 output_asm_insn ("jr\t%@%]%/", 0);
12880 /* Now deal with its delay slot; see above. */
12881 if (final_sequence
)
12883 /* This delay slot will only be executed if the branch is taken.
12884 Use INSN's delay slot if is annulled. */
12885 if (INSN_ANNULLED_BRANCH_P (insn
))
12887 final_scan_insn (final_sequence
->insn (1),
12888 asm_out_file
, optimize
, 1, NULL
);
12889 final_sequence
->insn (1)->set_deleted ();
12892 output_asm_insn ("nop", 0);
12893 fprintf (asm_out_file
, "\n");
12896 /* Output NOT_TAKEN. */
12897 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12898 CODE_LABEL_NUMBER (not_taken
));
12902 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12903 if some ordering condition is true. The condition is given by
12904 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12905 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12906 its second is always zero. */
12909 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
, bool inverted_p
)
12911 const char *branch
[2];
12913 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12914 Make BRANCH[0] branch on the inverse condition. */
12915 switch (GET_CODE (operands
[1]))
12917 /* These cases are equivalent to comparisons against zero. */
12919 inverted_p
= !inverted_p
;
12920 /* Fall through. */
12922 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12923 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12926 /* These cases are always true or always false. */
12928 inverted_p
= !inverted_p
;
12929 /* Fall through. */
12931 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12932 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12936 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12937 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12940 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12943 /* Start a block of code that needs access to the LL, SC and SYNC
12947 mips_start_ll_sc_sync_block (void)
12949 if (!ISA_HAS_LL_SC
)
12951 output_asm_insn (".set\tpush", 0);
12953 output_asm_insn (".set\tmips3", 0);
12955 output_asm_insn (".set\tmips2", 0);
12959 /* End a block started by mips_start_ll_sc_sync_block. */
12962 mips_end_ll_sc_sync_block (void)
12964 if (!ISA_HAS_LL_SC
)
12965 output_asm_insn (".set\tpop", 0);
12968 /* Output and/or return the asm template for a sync instruction. */
12971 mips_output_sync (void)
12973 mips_start_ll_sc_sync_block ();
12974 output_asm_insn ("sync", 0);
12975 mips_end_ll_sc_sync_block ();
12979 /* Return the asm template associated with sync_insn1 value TYPE.
12980 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12982 static const char *
12983 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12987 case SYNC_INSN1_MOVE
:
12988 return "move\t%0,%z2";
12989 case SYNC_INSN1_LI
:
12990 return "li\t%0,%2";
12991 case SYNC_INSN1_ADDU
:
12992 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12993 case SYNC_INSN1_ADDIU
:
12994 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12995 case SYNC_INSN1_SUBU
:
12996 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12997 case SYNC_INSN1_AND
:
12998 return "and\t%0,%1,%z2";
12999 case SYNC_INSN1_ANDI
:
13000 return "andi\t%0,%1,%2";
13001 case SYNC_INSN1_OR
:
13002 return "or\t%0,%1,%z2";
13003 case SYNC_INSN1_ORI
:
13004 return "ori\t%0,%1,%2";
13005 case SYNC_INSN1_XOR
:
13006 return "xor\t%0,%1,%z2";
13007 case SYNC_INSN1_XORI
:
13008 return "xori\t%0,%1,%2";
13010 gcc_unreachable ();
13013 /* Return the asm template associated with sync_insn2 value TYPE. */
13015 static const char *
13016 mips_sync_insn2_template (enum attr_sync_insn2 type
)
13020 case SYNC_INSN2_NOP
:
13021 gcc_unreachable ();
13022 case SYNC_INSN2_AND
:
13023 return "and\t%0,%1,%z2";
13024 case SYNC_INSN2_XOR
:
13025 return "xor\t%0,%1,%z2";
13026 case SYNC_INSN2_NOT
:
13027 return "nor\t%0,%1,%.";
13029 gcc_unreachable ();
13032 /* OPERANDS are the operands to a sync loop instruction and INDEX is
13033 the value of the one of the sync_* attributes. Return the operand
13034 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
13035 have the associated attribute. */
13038 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
13041 default_value
= operands
[index
- 1];
13042 return default_value
;
13045 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
13046 sequence for it. */
13049 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
13051 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
13052 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
13053 unsigned int tmp3_insn
;
13054 enum attr_sync_insn1 insn1
;
13055 enum attr_sync_insn2 insn2
;
13058 enum memmodel model
;
13060 /* Read an operand from the sync_WHAT attribute and store it in
13061 variable WHAT. DEFAULT is the default value if no attribute
13063 #define READ_OPERAND(WHAT, DEFAULT) \
13064 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
13067 /* Read the memory. */
13068 READ_OPERAND (mem
, 0);
13070 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
13072 /* Read the other attributes. */
13073 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
13074 READ_OPERAND (oldval
, at
);
13075 READ_OPERAND (cmp
, 0);
13076 READ_OPERAND (newval
, at
);
13077 READ_OPERAND (inclusive_mask
, 0);
13078 READ_OPERAND (exclusive_mask
, 0);
13079 READ_OPERAND (required_oldval
, 0);
13080 READ_OPERAND (insn1_op2
, 0);
13081 insn1
= get_attr_sync_insn1 (insn
);
13082 insn2
= get_attr_sync_insn2 (insn
);
13084 /* Don't bother setting CMP result that is never used. */
13085 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
13088 memmodel_attr
= get_attr_sync_memmodel (insn
);
13089 switch (memmodel_attr
)
13092 model
= MEMMODEL_ACQ_REL
;
13095 model
= MEMMODEL_ACQUIRE
;
13098 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
13101 mips_multi_start ();
13103 /* Output the release side of the memory barrier. */
13104 if (need_atomic_barrier_p (model
, true))
13106 if (required_oldval
== 0 && TARGET_OCTEON
)
13108 /* Octeon doesn't reorder reads, so a full barrier can be
13109 created by using SYNCW to order writes combined with the
13110 write from the following SC. When the SC successfully
13111 completes, we know that all preceding writes are also
13112 committed to the coherent memory system. It is possible
13113 for a single SYNCW to fail, but a pair of them will never
13114 fail, so we use two. */
13115 mips_multi_add_insn ("syncw", NULL
);
13116 mips_multi_add_insn ("syncw", NULL
);
13119 mips_multi_add_insn ("sync", NULL
);
13122 /* Output the branch-back label. */
13123 mips_multi_add_label ("1:");
13125 /* OLDVAL = *MEM. */
13126 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
13127 oldval
, mem
, NULL
);
13129 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
13130 if (required_oldval
)
13132 if (inclusive_mask
== 0)
13136 gcc_assert (oldval
!= at
);
13137 mips_multi_add_insn ("and\t%0,%1,%2",
13138 at
, oldval
, inclusive_mask
, NULL
);
13141 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
13143 /* CMP = 0 [delay slot]. */
13145 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
13148 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
13149 if (exclusive_mask
== 0)
13153 gcc_assert (oldval
!= at
);
13154 mips_multi_add_insn ("and\t%0,%1,%z2",
13155 at
, oldval
, exclusive_mask
, NULL
);
13159 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
13161 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
13162 at least one instruction in that case. */
13163 if (insn1
== SYNC_INSN1_MOVE
13164 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
13168 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
13169 newval
, oldval
, insn1_op2
, NULL
);
13173 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
13174 if (insn2
== SYNC_INSN2_NOP
)
13178 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
13179 newval
, tmp2
, inclusive_mask
, NULL
);
13182 tmp3_insn
= mips_multi_last_index ();
13184 /* $AT = $TMP1 | $TMP3. */
13185 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
13187 mips_multi_set_operand (tmp3_insn
, 0, at
);
13192 gcc_assert (tmp1
!= tmp3
);
13193 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
13196 /* if (!commit (*MEM = $AT)) goto 1.
13198 This will sometimes be a delayed branch; see the write code below
13200 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
13202 /* When using branch likely (-mfix-r10000), the delay slot instruction
13203 will be annulled on false. The normal delay slot instructions
13204 calculate the overall result of the atomic operation and must not
13205 be annulled. To ensure this behaviour unconditionally use a NOP
13206 in the delay slot for the branch likely case. */
13208 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
13210 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
13211 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
13213 mips_multi_copy_insn (tmp3_insn
);
13214 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
13216 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
13217 mips_multi_add_insn ("nop", NULL
);
13219 /* CMP = 1 -- either standalone or in a delay slot. */
13220 if (required_oldval
&& cmp
)
13221 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
13223 /* Output the acquire side of the memory barrier. */
13224 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
13225 mips_multi_add_insn ("sync", NULL
);
13227 /* Output the exit label, if needed. */
13228 if (required_oldval
)
13229 mips_multi_add_label ("2:");
13231 #undef READ_OPERAND
13234 /* Output and/or return the asm template for sync loop INSN, which has
13235 the operands given by OPERANDS. */
13238 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
13240 /* Use branch-likely instructions to work around the LL/SC R10000
13242 mips_branch_likely
= TARGET_FIX_R10000
;
13244 mips_process_sync_loop (insn
, operands
);
13246 mips_push_asm_switch (&mips_noreorder
);
13247 mips_push_asm_switch (&mips_nomacro
);
13248 mips_push_asm_switch (&mips_noat
);
13249 mips_start_ll_sc_sync_block ();
13251 mips_multi_write ();
13253 mips_end_ll_sc_sync_block ();
13254 mips_pop_asm_switch (&mips_noat
);
13255 mips_pop_asm_switch (&mips_nomacro
);
13256 mips_pop_asm_switch (&mips_noreorder
);
13261 /* Return the number of individual instructions in sync loop INSN,
13262 which has the operands given by OPERANDS. */
13265 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
13267 /* Use branch-likely instructions to work around the LL/SC R10000
13269 mips_branch_likely
= TARGET_FIX_R10000
;
13270 mips_process_sync_loop (insn
, operands
);
13271 return mips_multi_num_insns
;
13274 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13275 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
13277 When working around R4000 and R4400 errata, we need to make sure that
13278 the division is not immediately followed by a shift[1][2]. We also
13279 need to stop the division from being put into a branch delay slot[3].
13280 The easiest way to avoid both problems is to add a nop after the
13281 division. When a divide-by-zero check is needed, this nop can be
13282 used to fill the branch delay slot.
13284 [1] If a double-word or a variable shift executes immediately
13285 after starting an integer division, the shift may give an
13286 incorrect result. See quotations of errata #16 and #28 from
13287 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13288 in mips.md for details.
13290 [2] A similar bug to [1] exists for all revisions of the
13291 R4000 and the R4400 when run in an MC configuration.
13292 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
13294 "19. In this following sequence:
13296 ddiv (or ddivu or div or divu)
13297 dsll32 (or dsrl32, dsra32)
13299 if an MPT stall occurs, while the divide is slipping the cpu
13300 pipeline, then the following double shift would end up with an
13303 Workaround: The compiler needs to avoid generating any
13304 sequence with divide followed by extended double shift."
13306 This erratum is also present in "MIPS R4400MC Errata, Processor
13307 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
13308 & 3.0" as errata #10 and #4, respectively.
13310 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13311 (also valid for MIPS R4000MC processors):
13313 "52. R4000SC: This bug does not apply for the R4000PC.
13315 There are two flavors of this bug:
13317 1) If the instruction just after divide takes an RF exception
13318 (tlb-refill, tlb-invalid) and gets an instruction cache
13319 miss (both primary and secondary) and the line which is
13320 currently in secondary cache at this index had the first
13321 data word, where the bits 5..2 are set, then R4000 would
13322 get a wrong result for the div.
13327 ------------------- # end-of page. -tlb-refill
13332 ------------------- # end-of page. -tlb-invalid
13335 2) If the divide is in the taken branch delay slot, where the
13336 target takes RF exception and gets an I-cache miss for the
13337 exception vector or where I-cache miss occurs for the
13338 target address, under the above mentioned scenarios, the
13339 div would get wrong results.
13342 j r2 # to next page mapped or unmapped
13343 div r8,r9 # this bug would be there as long
13344 # as there is an ICache miss and
13345 nop # the "data pattern" is present
13348 beq r0, r0, NextPage # to Next page
13352 This bug is present for div, divu, ddiv, and ddivu
13355 Workaround: For item 1), OS could make sure that the next page
13356 after the divide instruction is also mapped. For item 2), the
13357 compiler could make sure that the divide instruction is not in
13358 the branch delay slot."
13360 These processors have PRId values of 0x00004220 and 0x00004300 for
13361 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13364 mips_output_division (const char *division
, rtx
*operands
)
13369 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
13371 output_asm_insn (s
, operands
);
13374 if (TARGET_CHECK_ZERO_DIV
)
13378 output_asm_insn (s
, operands
);
13379 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13381 else if (GENERATE_DIVIDE_TRAPS
)
13383 /* Avoid long replay penalty on load miss by putting the trap before
13386 output_asm_insn ("teq\t%2,%.,7", operands
);
13389 output_asm_insn (s
, operands
);
13390 s
= "teq\t%2,%.,7";
13395 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13396 output_asm_insn (s
, operands
);
13397 s
= "break\t7%)\n1:";
13403 /* Return true if destination of IN_INSN is used as add source in
13404 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13405 madd.s dst, x, y, z
13406 madd.s a, dst, b, c */
13409 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13411 int dst_reg
, src_reg
;
13413 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
13414 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
13416 extract_insn (in_insn
);
13417 dst_reg
= REG_P (recog_data
.operand
[0]);
13419 extract_insn (out_insn
);
13420 src_reg
= REG_P (recog_data
.operand
[1]);
13422 if (dst_reg
== src_reg
)
13428 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13429 instruction and if OUT_INSN assigns to the accumulator operand. */
13432 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13434 enum attr_accum_in accum_in
;
13435 int accum_in_opnum
;
13438 if (recog_memoized (in_insn
) < 0)
13441 accum_in
= get_attr_accum_in (in_insn
);
13442 if (accum_in
== ACCUM_IN_NONE
)
13445 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13447 extract_insn (in_insn
);
13448 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13449 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13451 return reg_set_p (accum_in_op
, out_insn
);
13454 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13455 data rather than the address. We need this because the cprestore
13456 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13457 which causes the default routine to abort. We just return false
13461 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13463 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13466 return !store_data_bypass_p (out_insn
, in_insn
);
13470 /* Variables and flags used in scheduler hooks when tuning for
13474 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13477 /* If true, then next ALU1/2 instruction will go to ALU1. */
13480 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13483 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13484 int alu1_core_unit_code
;
13485 int alu2_core_unit_code
;
13486 int falu1_core_unit_code
;
13487 int falu2_core_unit_code
;
13489 /* True if current cycle has a multi instruction.
13490 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13491 bool cycle_has_multi_p
;
13493 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13494 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13496 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13497 instruction to go ALU1. */
13498 rtx_insn
*alu1_turn_enabled_insn
;
13499 rtx_insn
*alu2_turn_enabled_insn
;
13500 rtx_insn
*falu1_turn_enabled_insn
;
13501 rtx_insn
*falu2_turn_enabled_insn
;
13504 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13505 dependencies have no cost, except on the 20Kc where output-dependence
13506 is treated like input-dependence. */
13509 mips_adjust_cost (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx link
,
13510 rtx_insn
*dep ATTRIBUTE_UNUSED
, int cost
)
13512 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13515 if (REG_NOTE_KIND (link
) != 0)
13520 /* Return the number of instructions that can be issued per cycle. */
13523 mips_issue_rate (void)
13527 case PROCESSOR_74KC
:
13528 case PROCESSOR_74KF2_1
:
13529 case PROCESSOR_74KF1_1
:
13530 case PROCESSOR_74KF3_2
:
13531 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13532 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13533 but in reality only a maximum of 3 insns can be issued as
13534 floating-point loads and stores also require a slot in the
13536 case PROCESSOR_R10000
:
13537 /* All R10K Processors are quad-issue (being the first MIPS
13538 processors to support this feature). */
13541 case PROCESSOR_20KC
:
13542 case PROCESSOR_R4130
:
13543 case PROCESSOR_R5400
:
13544 case PROCESSOR_R5500
:
13545 case PROCESSOR_R5900
:
13546 case PROCESSOR_R7000
:
13547 case PROCESSOR_R9000
:
13548 case PROCESSOR_OCTEON
:
13549 case PROCESSOR_OCTEON2
:
13550 case PROCESSOR_OCTEON3
:
13553 case PROCESSOR_SB1
:
13554 case PROCESSOR_SB1A
:
13555 /* This is actually 4, but we get better performance if we claim 3.
13556 This is partly because of unwanted speculative code motion with the
13557 larger number, and partly because in most common cases we can't
13558 reach the theoretical max of 4. */
13561 case PROCESSOR_LOONGSON_2E
:
13562 case PROCESSOR_LOONGSON_2F
:
13563 case PROCESSOR_LOONGSON_3A
:
13564 case PROCESSOR_P5600
:
13567 case PROCESSOR_XLP
:
13568 return (reload_completed
? 4 : 3);
13575 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13578 mips_ls2_init_dfa_post_cycle_insn (void)
13581 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13582 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13586 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13587 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13591 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13592 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13596 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13597 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13600 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13601 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13602 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13603 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13606 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13607 Init data used in mips_dfa_post_advance_cycle. */
13610 mips_init_dfa_post_cycle_insn (void)
13612 if (TUNE_LOONGSON_2EF
)
13613 mips_ls2_init_dfa_post_cycle_insn ();
13616 /* Initialize STATE when scheduling for Loongson 2E/2F.
13617 Support round-robin dispatch scheme by enabling only one of
13618 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13622 mips_ls2_dfa_post_advance_cycle (state_t state
)
13624 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13626 /* Though there are no non-pipelined ALU1 insns,
13627 we can get an instruction of type 'multi' before reload. */
13628 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13629 mips_ls2
.alu1_turn_p
= false;
13632 mips_ls2
.cycle_has_multi_p
= false;
13634 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13635 /* We have a non-pipelined alu instruction in the core,
13636 adjust round-robin counter. */
13637 mips_ls2
.alu1_turn_p
= true;
13639 if (mips_ls2
.alu1_turn_p
)
13641 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13642 gcc_unreachable ();
13646 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13647 gcc_unreachable ();
13650 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13652 /* There are no non-pipelined FALU1 insns. */
13653 gcc_unreachable ();
13654 mips_ls2
.falu1_turn_p
= false;
13657 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13658 /* We have a non-pipelined falu instruction in the core,
13659 adjust round-robin counter. */
13660 mips_ls2
.falu1_turn_p
= true;
13662 if (mips_ls2
.falu1_turn_p
)
13664 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13665 gcc_unreachable ();
13669 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13670 gcc_unreachable ();
13674 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13675 This hook is being called at the start of each cycle. */
13678 mips_dfa_post_advance_cycle (void)
13680 if (TUNE_LOONGSON_2EF
)
13681 mips_ls2_dfa_post_advance_cycle (curr_state
);
13684 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13685 be as wide as the scheduling freedom in the DFA. */
13688 mips_multipass_dfa_lookahead (void)
13690 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13694 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13706 /* Remove the instruction at index LOWER from ready queue READY and
13707 reinsert it in front of the instruction at index HIGHER. LOWER must
13711 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
13713 rtx_insn
*new_head
;
13716 new_head
= ready
[lower
];
13717 for (i
= lower
; i
< higher
; i
++)
13718 ready
[i
] = ready
[i
+ 1];
13719 ready
[i
] = new_head
;
13722 /* If the priority of the instruction at POS2 in the ready queue READY
13723 is within LIMIT units of that of the instruction at POS1, swap the
13724 instructions if POS2 is not already less than POS1. */
13727 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
13730 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13734 temp
= ready
[pos1
];
13735 ready
[pos1
] = ready
[pos2
];
13736 ready
[pos2
] = temp
;
13740 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13741 that may clobber hi or lo. */
13742 static rtx_insn
*mips_macc_chains_last_hilo
;
13744 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13745 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13748 mips_macc_chains_record (rtx_insn
*insn
)
13750 if (get_attr_may_clobber_hilo (insn
))
13751 mips_macc_chains_last_hilo
= insn
;
13754 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13755 has NREADY elements, looking for a multiply-add or multiply-subtract
13756 instruction that is cumulative with mips_macc_chains_last_hilo.
13757 If there is one, promote it ahead of anything else that might
13758 clobber hi or lo. */
13761 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
13765 if (mips_macc_chains_last_hilo
!= 0)
13766 for (i
= nready
- 1; i
>= 0; i
--)
13767 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13769 for (j
= nready
- 1; j
> i
; j
--)
13770 if (recog_memoized (ready
[j
]) >= 0
13771 && get_attr_may_clobber_hilo (ready
[j
]))
13773 mips_promote_ready (ready
, i
, j
);
13780 /* The last instruction to be scheduled. */
13781 static rtx_insn
*vr4130_last_insn
;
13783 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13784 points to an rtx that is initially an instruction. Nullify the rtx
13785 if the instruction uses the value of register X. */
13788 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13793 insn_ptr
= (rtx
*) data
;
13796 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13800 /* Return true if there is true register dependence between vr4130_last_insn
13804 vr4130_true_reg_dependence_p (rtx insn
)
13806 note_stores (PATTERN (vr4130_last_insn
),
13807 vr4130_true_reg_dependence_p_1
, &insn
);
13811 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13812 the ready queue and that INSN2 is the instruction after it, return
13813 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13814 in which INSN1 and INSN2 can probably issue in parallel, but for
13815 which (INSN2, INSN1) should be less sensitive to instruction
13816 alignment than (INSN1, INSN2). See 4130.md for more details. */
13819 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
13821 sd_iterator_def sd_it
;
13824 /* Check for the following case:
13826 1) there is some other instruction X with an anti dependence on INSN1;
13827 2) X has a higher priority than INSN2; and
13828 3) X is an arithmetic instruction (and thus has no unit restrictions).
13830 If INSN1 is the last instruction blocking X, it would better to
13831 choose (INSN1, X) over (INSN2, INSN1). */
13832 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13833 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13834 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13835 && recog_memoized (DEP_CON (dep
)) >= 0
13836 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13839 if (vr4130_last_insn
!= 0
13840 && recog_memoized (insn1
) >= 0
13841 && recog_memoized (insn2
) >= 0)
13843 /* See whether INSN1 and INSN2 use different execution units,
13844 or if they are both ALU-type instructions. If so, they can
13845 probably execute in parallel. */
13846 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13847 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13848 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13850 /* If only one of the instructions has a dependence on
13851 vr4130_last_insn, prefer to schedule the other one first. */
13852 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13853 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13854 if (dep1_p
!= dep2_p
)
13857 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13858 is not an ALU-type instruction and if INSN1 uses the same
13859 execution unit. (Note that if this condition holds, we already
13860 know that INSN2 uses a different execution unit.) */
13861 if (class1
!= VR4130_CLASS_ALU
13862 && recog_memoized (vr4130_last_insn
) >= 0
13863 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13870 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13871 queue with at least two instructions. Swap the first two if
13872 vr4130_swap_insns_p says that it could be worthwhile. */
13875 vr4130_reorder (rtx_insn
**ready
, int nready
)
13877 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13878 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13881 /* Record whether last 74k AGEN instruction was a load or store. */
13882 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13884 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13885 resets to TYPE_UNKNOWN state. */
13888 mips_74k_agen_init (rtx_insn
*insn
)
13890 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13891 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13894 enum attr_type type
= get_attr_type (insn
);
13895 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13896 mips_last_74k_agen_insn
= type
;
13900 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13901 loads to be grouped together, and multiple stores to be grouped
13902 together. Swap things around in the ready queue to make this happen. */
13905 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
13908 int store_pos
, load_pos
;
13913 for (i
= nready
- 1; i
>= 0; i
--)
13915 rtx_insn
*insn
= ready
[i
];
13916 if (USEFUL_INSN_P (insn
))
13917 switch (get_attr_type (insn
))
13920 if (store_pos
== -1)
13925 if (load_pos
== -1)
13934 if (load_pos
== -1 || store_pos
== -1)
13937 switch (mips_last_74k_agen_insn
)
13940 /* Prefer to schedule loads since they have a higher latency. */
13942 /* Swap loads to the front of the queue. */
13943 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13946 /* Swap stores to the front of the queue. */
13947 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13954 /* Implement TARGET_SCHED_INIT. */
13957 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13958 int max_ready ATTRIBUTE_UNUSED
)
13960 mips_macc_chains_last_hilo
= 0;
13961 vr4130_last_insn
= 0;
13962 mips_74k_agen_init (NULL
);
13964 /* When scheduling for Loongson2, branch instructions go to ALU1,
13965 therefore basic block is most likely to start with round-robin counter
13966 pointed to ALU2. */
13967 mips_ls2
.alu1_turn_p
= false;
13968 mips_ls2
.falu1_turn_p
= true;
13971 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13974 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13975 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13977 if (!reload_completed
13978 && TUNE_MACC_CHAINS
13980 mips_macc_chains_reorder (ready
, *nreadyp
);
13982 if (reload_completed
13984 && !TARGET_VR4130_ALIGN
13986 vr4130_reorder (ready
, *nreadyp
);
13989 mips_74k_agen_reorder (ready
, *nreadyp
);
13992 /* Implement TARGET_SCHED_REORDER. */
13995 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13996 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13998 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13999 return mips_issue_rate ();
14002 /* Implement TARGET_SCHED_REORDER2. */
14005 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14006 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
14008 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
14009 return cached_can_issue_more
;
14012 /* Update round-robin counters for ALU1/2 and FALU1/2. */
14015 mips_ls2_variable_issue (rtx_insn
*insn
)
14017 if (mips_ls2
.alu1_turn_p
)
14019 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
14020 mips_ls2
.alu1_turn_p
= false;
14024 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
14025 mips_ls2
.alu1_turn_p
= true;
14028 if (mips_ls2
.falu1_turn_p
)
14030 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
14031 mips_ls2
.falu1_turn_p
= false;
14035 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
14036 mips_ls2
.falu1_turn_p
= true;
14039 if (recog_memoized (insn
) >= 0)
14040 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
14043 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
14046 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14047 rtx_insn
*insn
, int more
)
14049 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
14050 if (USEFUL_INSN_P (insn
))
14052 if (get_attr_type (insn
) != TYPE_GHOST
)
14054 if (!reload_completed
&& TUNE_MACC_CHAINS
)
14055 mips_macc_chains_record (insn
);
14056 vr4130_last_insn
= insn
;
14058 mips_74k_agen_init (insn
);
14059 else if (TUNE_LOONGSON_2EF
)
14060 mips_ls2_variable_issue (insn
);
14063 /* Instructions of type 'multi' should all be split before
14064 the second scheduling pass. */
14065 gcc_assert (!reload_completed
14066 || recog_memoized (insn
) < 0
14067 || get_attr_type (insn
) != TYPE_MULTI
);
14069 cached_can_issue_more
= more
;
14073 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
14074 return the first operand of the associated PREF or PREFX insn. */
14077 mips_prefetch_cookie (rtx write
, rtx locality
)
14079 /* store_streamed / load_streamed. */
14080 if (INTVAL (locality
) <= 0)
14081 return GEN_INT (INTVAL (write
) + 4);
14083 /* store / load. */
14084 if (INTVAL (locality
) <= 2)
14087 /* store_retained / load_retained. */
14088 return GEN_INT (INTVAL (write
) + 6);
14091 /* Flags that indicate when a built-in function is available.
14093 BUILTIN_AVAIL_NON_MIPS16
14094 The function is available on the current target if !TARGET_MIPS16.
14096 BUILTIN_AVAIL_MIPS16
14097 The function is available on the current target if TARGET_MIPS16. */
14098 #define BUILTIN_AVAIL_NON_MIPS16 1
14099 #define BUILTIN_AVAIL_MIPS16 2
14101 /* Declare an availability predicate for built-in functions that
14102 require non-MIPS16 mode and also require COND to be true.
14103 NAME is the main part of the predicate's name. */
14104 #define AVAIL_NON_MIPS16(NAME, COND) \
14105 static unsigned int \
14106 mips_builtin_avail_##NAME (void) \
14108 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
14111 /* Declare an availability predicate for built-in functions that
14112 support both MIPS16 and non-MIPS16 code and also require COND
14113 to be true. NAME is the main part of the predicate's name. */
14114 #define AVAIL_ALL(NAME, COND) \
14115 static unsigned int \
14116 mips_builtin_avail_##NAME (void) \
14118 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
14121 /* This structure describes a single built-in function. */
14122 struct mips_builtin_description
{
14123 /* The code of the main .md file instruction. See mips_builtin_type
14124 for more information. */
14125 enum insn_code icode
;
14127 /* The floating-point comparison code to use with ICODE, if any. */
14128 enum mips_fp_condition cond
;
14130 /* The name of the built-in function. */
14133 /* Specifies how the function should be expanded. */
14134 enum mips_builtin_type builtin_type
;
14136 /* The function's prototype. */
14137 enum mips_function_type function_type
;
14139 /* Whether the function is available. */
14140 unsigned int (*avail
) (void);
14143 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
14144 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
14145 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
14146 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
14147 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
14148 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
14149 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
14150 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
14151 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
14152 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
14153 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
14155 /* Construct a mips_builtin_description from the given arguments.
14157 INSN is the name of the associated instruction pattern, without the
14158 leading CODE_FOR_mips_.
14160 CODE is the floating-point condition code associated with the
14161 function. It can be 'f' if the field is not applicable.
14163 NAME is the name of the function itself, without the leading
14166 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
14168 AVAIL is the name of the availability predicate, without the leading
14169 mips_builtin_avail_. */
14170 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
14171 FUNCTION_TYPE, AVAIL) \
14172 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
14173 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
14174 mips_builtin_avail_ ## AVAIL }
14176 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
14177 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
14178 are as for MIPS_BUILTIN. */
14179 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14180 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
14182 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
14183 are subject to mips_builtin_avail_<AVAIL>. */
14184 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
14185 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
14186 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
14187 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
14188 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
14190 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
14191 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
14192 while the any and all forms are subject to mips_builtin_avail_mips3d. */
14193 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
14194 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
14195 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
14197 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
14198 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
14200 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
14201 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
14203 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
14204 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
14207 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
14208 are subject to mips_builtin_avail_mips3d. */
14209 #define CMP_4S_BUILTINS(INSN, COND) \
14210 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
14211 MIPS_BUILTIN_CMP_ANY, \
14212 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
14213 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
14214 MIPS_BUILTIN_CMP_ALL, \
14215 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
14217 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
14218 instruction requires mips_builtin_avail_<AVAIL>. */
14219 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
14220 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
14221 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14223 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
14224 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14227 /* Define all the built-in functions related to C.cond.fmt condition COND. */
14228 #define CMP_BUILTINS(COND) \
14229 MOVTF_BUILTINS (c, COND, paired_single), \
14230 MOVTF_BUILTINS (cabs, COND, mips3d), \
14231 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
14232 CMP_PS_BUILTINS (c, COND, paired_single), \
14233 CMP_PS_BUILTINS (cabs, COND, mips3d), \
14234 CMP_4S_BUILTINS (c, COND), \
14235 CMP_4S_BUILTINS (cabs, COND)
14237 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14238 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
14239 and AVAIL are as for MIPS_BUILTIN. */
14240 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14241 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
14242 FUNCTION_TYPE, AVAIL)
14244 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
14245 branch instruction. AVAIL is as for MIPS_BUILTIN. */
14246 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
14247 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
14248 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
14250 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
14251 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14252 builtin_description field. */
14253 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
14254 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
14255 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
14256 FUNCTION_TYPE, mips_builtin_avail_loongson }
14258 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
14259 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14260 builtin_description field. */
14261 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
14262 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
14264 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
14265 We use functions of this form when the same insn can be usefully applied
14266 to more than one datatype. */
14267 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
14268 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
14270 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
14271 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
14272 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
14273 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
14274 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
14275 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
14276 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
14277 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
14279 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
14280 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
14281 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
14282 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
14283 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
14284 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
14285 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
14286 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
14287 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
14288 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
14289 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
14290 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
14291 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
14292 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
14293 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
14294 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
14295 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
14296 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
14297 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
14298 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
14299 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
14300 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
14301 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
14302 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
14303 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
14304 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
14305 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
14306 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
14307 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
14308 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
14310 static const struct mips_builtin_description mips_builtins
[] = {
14311 #define MIPS_GET_FCSR 0
14312 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
14313 #define MIPS_SET_FCSR 1
14314 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
14316 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14317 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14318 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14319 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14320 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
14321 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14322 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14323 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
14325 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
14326 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14327 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14328 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14329 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14331 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14332 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14333 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14334 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14335 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14336 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14338 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14339 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14340 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14341 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14342 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14343 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14345 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
14347 /* Built-in functions for the SB-1 processor. */
14348 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
14350 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14351 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14352 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14353 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14354 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14355 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14356 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14357 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14358 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14359 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14360 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14361 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14362 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14363 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14364 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
14365 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
14366 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
14367 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14368 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14369 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14370 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14371 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
14372 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
14373 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14374 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14375 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14376 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14377 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14378 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14379 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14380 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14381 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14382 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14383 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14384 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14385 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14386 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14387 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14388 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14389 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14390 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14391 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14392 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14393 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14394 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14395 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14396 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14397 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14398 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14399 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14400 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14401 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14402 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14403 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14404 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14405 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14406 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14407 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14408 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14409 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14410 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14411 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14412 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14413 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14414 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14415 BPOSGE_BUILTIN (32, dsp
),
14417 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14418 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14419 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14420 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14421 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14422 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14423 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14424 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14425 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14426 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14427 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14428 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14429 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14430 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14431 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14432 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14433 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14434 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14435 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14436 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14437 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14438 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14439 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14440 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14441 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14442 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14443 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14444 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14445 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14446 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14447 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14448 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14449 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14450 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14451 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14453 /* Built-in functions for the DSP ASE (32-bit only). */
14454 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14455 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14456 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14457 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14458 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14459 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14460 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14461 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14462 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14463 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14464 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14465 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14466 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14467 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14468 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14469 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14470 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14471 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14472 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14473 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14474 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14475 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14476 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14477 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14478 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14479 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14480 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14482 /* Built-in functions for the DSP ASE (64-bit only). */
14483 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14485 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14486 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14487 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14488 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14489 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14490 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14491 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14492 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14493 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14494 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14496 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14497 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14498 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14499 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14500 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14501 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14502 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14503 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14504 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14505 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14506 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14507 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14508 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14509 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14510 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14511 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14512 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14513 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14514 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14515 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14516 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14517 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14518 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14519 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14520 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14521 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14522 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14523 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14524 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14525 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14526 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14527 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14528 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14529 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14530 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14531 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14532 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14533 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14534 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14535 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14536 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14537 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14538 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14539 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14540 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14541 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14542 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14543 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14544 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14545 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14546 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14547 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14548 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14549 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14550 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14551 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14552 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14553 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14554 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14555 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14556 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14557 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14558 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14559 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14560 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14561 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14562 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14563 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14564 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14565 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14566 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14567 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14568 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14569 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14570 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14571 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14572 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14573 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14574 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14575 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14576 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14577 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14578 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14579 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14580 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14581 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14582 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14583 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14584 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14585 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14586 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14587 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14588 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14589 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14590 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14591 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14592 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14593 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14594 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14595 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14597 /* Sundry other built-in functions. */
14598 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14601 /* Index I is the function declaration for mips_builtins[I], or null if the
14602 function isn't defined on this target. */
14603 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14605 /* MODE is a vector mode whose elements have type TYPE. Return the type
14606 of the vector itself. */
14609 mips_builtin_vector_type (tree type
, machine_mode mode
)
14611 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14614 mode_index
= (int) mode
;
14616 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14617 mode_index
+= MAX_MACHINE_MODE
;
14619 if (types
[mode_index
] == NULL_TREE
)
14620 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14621 return types
[mode_index
];
14624 /* Return a type for 'const volatile void *'. */
14627 mips_build_cvpointer_type (void)
14631 if (cache
== NULL_TREE
)
14632 cache
= build_pointer_type (build_qualified_type
14634 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14638 /* Source-level argument types. */
14639 #define MIPS_ATYPE_VOID void_type_node
14640 #define MIPS_ATYPE_INT integer_type_node
14641 #define MIPS_ATYPE_POINTER ptr_type_node
14642 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14644 /* Standard mode-based argument types. */
14645 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14646 #define MIPS_ATYPE_SI intSI_type_node
14647 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14648 #define MIPS_ATYPE_DI intDI_type_node
14649 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14650 #define MIPS_ATYPE_SF float_type_node
14651 #define MIPS_ATYPE_DF double_type_node
14653 /* Vector argument types. */
14654 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14655 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14656 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14657 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14658 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14659 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14660 #define MIPS_ATYPE_UV2SI \
14661 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14662 #define MIPS_ATYPE_UV4HI \
14663 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14664 #define MIPS_ATYPE_UV8QI \
14665 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14667 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14668 their associated MIPS_ATYPEs. */
14669 #define MIPS_FTYPE_ATYPES1(A, B) \
14670 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14672 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14673 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14675 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14676 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14678 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14679 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14682 /* Return the function type associated with function prototype TYPE. */
14685 mips_build_function_type (enum mips_function_type type
)
14687 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14689 if (types
[(int) type
] == NULL_TREE
)
14692 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14693 case MIPS_FTYPE_NAME##NUM ARGS: \
14694 types[(int) type] \
14695 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14698 #include "config/mips/mips-ftypes.def"
14699 #undef DEF_MIPS_FTYPE
14701 gcc_unreachable ();
14704 return types
[(int) type
];
14707 /* Implement TARGET_INIT_BUILTINS. */
14710 mips_init_builtins (void)
14712 const struct mips_builtin_description
*d
;
14715 /* Iterate through all of the bdesc arrays, initializing all of the
14716 builtin functions. */
14717 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14719 d
= &mips_builtins
[i
];
14721 mips_builtin_decls
[i
]
14722 = add_builtin_function (d
->name
,
14723 mips_build_function_type (d
->function_type
),
14724 i
, BUILT_IN_MD
, NULL
, NULL
);
14728 /* Implement TARGET_BUILTIN_DECL. */
14731 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14733 if (code
>= ARRAY_SIZE (mips_builtins
))
14734 return error_mark_node
;
14735 return mips_builtin_decls
[code
];
14738 /* Take argument ARGNO from EXP's argument list and convert it into
14739 an expand operand. Store the operand in *OP. */
14742 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14743 unsigned int argno
)
14748 arg
= CALL_EXPR_ARG (exp
, argno
);
14749 value
= expand_normal (arg
);
14750 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14753 /* Expand instruction ICODE as part of a built-in function sequence.
14754 Use the first NOPS elements of OPS as the instruction's operands.
14755 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14756 instruction has no target.
14758 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14761 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14762 struct expand_operand
*ops
, bool has_target_p
)
14764 if (!maybe_expand_insn (icode
, nops
, ops
))
14766 error ("invalid argument to built-in function");
14767 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14769 return has_target_p
? ops
[0].value
: const0_rtx
;
14772 /* Expand a floating-point comparison for built-in function call EXP.
14773 The first NARGS arguments are the values to be compared. ICODE is
14774 the .md pattern that does the comparison and COND is the condition
14775 that is being tested. Return an rtx for the result. */
14778 mips_expand_builtin_compare_1 (enum insn_code icode
,
14779 enum mips_fp_condition cond
,
14780 tree exp
, int nargs
)
14782 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14786 /* The instruction should have a target operand, an operand for each
14787 argument, and an operand for COND. */
14788 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14790 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14792 create_fixed_operand (&ops
[opno
++], output
);
14793 for (argno
= 0; argno
< nargs
; argno
++)
14794 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14795 create_integer_operand (&ops
[opno
++], (int) cond
);
14796 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14799 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14800 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14801 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14802 suggests a good place to put the result. */
14805 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14808 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14811 /* Map any target to operand 0. */
14814 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14816 /* Map the arguments to the other operands. */
14817 gcc_assert (opno
+ call_expr_nargs (exp
)
14818 == insn_data
[icode
].n_generator_args
);
14819 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14820 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14822 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14825 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14826 function; TYPE says which. EXP is the CALL_EXPR that calls the
14827 function, ICODE is the instruction that should be used to compare
14828 the first two arguments, and COND is the condition it should test.
14829 TARGET, if nonnull, suggests a good place to put the result. */
14832 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14833 enum insn_code icode
, enum mips_fp_condition cond
,
14834 rtx target
, tree exp
)
14836 struct expand_operand ops
[4];
14839 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14840 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14841 if (type
== MIPS_BUILTIN_MOVT
)
14843 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14844 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14848 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14849 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14851 create_fixed_operand (&ops
[3], cmp_result
);
14852 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14856 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14857 into TARGET otherwise. Return TARGET. */
14860 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14861 rtx value_if_true
, rtx value_if_false
)
14863 rtx_code_label
*true_label
, *done_label
;
14865 true_label
= gen_label_rtx ();
14866 done_label
= gen_label_rtx ();
14868 /* First assume that CONDITION is false. */
14869 mips_emit_move (target
, value_if_false
);
14871 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14872 emit_jump_insn (gen_condjump (condition
, true_label
));
14873 emit_jump_insn (gen_jump (done_label
));
14876 /* Fix TARGET if CONDITION is true. */
14877 emit_label (true_label
);
14878 mips_emit_move (target
, value_if_true
);
14880 emit_label (done_label
);
14884 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14885 the CALL_EXPR that calls the function, ICODE is the code of the
14886 comparison instruction, and COND is the condition it should test.
14887 TARGET, if nonnull, suggests a good place to put the boolean result. */
14890 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14891 enum insn_code icode
, enum mips_fp_condition cond
,
14892 rtx target
, tree exp
)
14894 rtx offset
, condition
, cmp_result
;
14896 if (target
== 0 || GET_MODE (target
) != SImode
)
14897 target
= gen_reg_rtx (SImode
);
14898 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14899 call_expr_nargs (exp
));
14901 /* If the comparison sets more than one register, we define the result
14902 to be 0 if all registers are false and -1 if all registers are true.
14903 The value of the complete result is indeterminate otherwise. */
14904 switch (builtin_type
)
14906 case MIPS_BUILTIN_CMP_ALL
:
14907 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14908 return mips_builtin_branch_and_move (condition
, target
,
14909 const0_rtx
, const1_rtx
);
14911 case MIPS_BUILTIN_CMP_UPPER
:
14912 case MIPS_BUILTIN_CMP_LOWER
:
14913 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14914 condition
= gen_single_cc (cmp_result
, offset
);
14915 return mips_builtin_branch_and_move (condition
, target
,
14916 const1_rtx
, const0_rtx
);
14919 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14920 return mips_builtin_branch_and_move (condition
, target
,
14921 const1_rtx
, const0_rtx
);
14925 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14926 if nonnull, suggests a good place to put the boolean result. */
14929 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14931 rtx condition
, cmp_result
;
14934 if (target
== 0 || GET_MODE (target
) != SImode
)
14935 target
= gen_reg_rtx (SImode
);
14937 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14939 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14944 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14945 return mips_builtin_branch_and_move (condition
, target
,
14946 const1_rtx
, const0_rtx
);
14949 /* Implement TARGET_EXPAND_BUILTIN. */
14952 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14953 machine_mode mode
, int ignore
)
14956 unsigned int fcode
, avail
;
14957 const struct mips_builtin_description
*d
;
14959 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14960 fcode
= DECL_FUNCTION_CODE (fndecl
);
14961 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14962 d
= &mips_builtins
[fcode
];
14963 avail
= d
->avail ();
14964 gcc_assert (avail
!= 0);
14965 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14967 error ("built-in function %qE not supported for MIPS16",
14968 DECL_NAME (fndecl
));
14969 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14971 switch (d
->builtin_type
)
14973 case MIPS_BUILTIN_DIRECT
:
14974 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14976 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14977 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14979 case MIPS_BUILTIN_MOVT
:
14980 case MIPS_BUILTIN_MOVF
:
14981 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14982 d
->cond
, target
, exp
);
14984 case MIPS_BUILTIN_CMP_ANY
:
14985 case MIPS_BUILTIN_CMP_ALL
:
14986 case MIPS_BUILTIN_CMP_UPPER
:
14987 case MIPS_BUILTIN_CMP_LOWER
:
14988 case MIPS_BUILTIN_CMP_SINGLE
:
14989 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14990 d
->cond
, target
, exp
);
14992 case MIPS_BUILTIN_BPOSGE32
:
14993 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14995 gcc_unreachable ();
14998 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14999 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
15000 struct mips16_constant
{
15001 struct mips16_constant
*next
;
15003 rtx_code_label
*label
;
15007 /* Information about an incomplete MIPS16 constant pool. FIRST is the
15008 first constant, HIGHEST_ADDRESS is the highest address that the first
15009 byte of the pool can have, and INSN_ADDRESS is the current instruction
15011 struct mips16_constant_pool
{
15012 struct mips16_constant
*first
;
15013 int highest_address
;
15017 /* Add constant VALUE to POOL and return its label. MODE is the
15018 value's mode (used for CONST_INTs, etc.). */
15020 static rtx_code_label
*
15021 mips16_add_constant (struct mips16_constant_pool
*pool
,
15022 rtx value
, machine_mode mode
)
15024 struct mips16_constant
**p
, *c
;
15025 bool first_of_size_p
;
15027 /* See whether the constant is already in the pool. If so, return the
15028 existing label, otherwise leave P pointing to the place where the
15029 constant should be added.
15031 Keep the pool sorted in increasing order of mode size so that we can
15032 reduce the number of alignments needed. */
15033 first_of_size_p
= true;
15034 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
15036 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
15037 return (*p
)->label
;
15038 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
15040 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
15041 first_of_size_p
= false;
15044 /* In the worst case, the constant needed by the earliest instruction
15045 will end up at the end of the pool. The entire pool must then be
15046 accessible from that instruction.
15048 When adding the first constant, set the pool's highest address to
15049 the address of the first out-of-range byte. Adjust this address
15050 downwards each time a new constant is added. */
15051 if (pool
->first
== 0)
15052 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
15053 of the instruction with the lowest two bits clear. The base PC
15054 value for LDPC has the lowest three bits clear. Assume the worst
15055 case here; namely that the PC-relative instruction occupies the
15056 last 2 bytes in an aligned word. */
15057 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
15058 pool
->highest_address
-= GET_MODE_SIZE (mode
);
15059 if (first_of_size_p
)
15060 /* Take into account the worst possible padding due to alignment. */
15061 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
15063 /* Create a new entry. */
15064 c
= XNEW (struct mips16_constant
);
15067 c
->label
= gen_label_rtx ();
15074 /* Output constant VALUE after instruction INSN and return the last
15075 instruction emitted. MODE is the mode of the constant. */
15078 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
15080 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
15082 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
15083 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
15086 if (SCALAR_FLOAT_MODE_P (mode
))
15087 return emit_insn_after (gen_consttable_float (value
), insn
);
15089 if (VECTOR_MODE_P (mode
))
15093 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
15094 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
15095 CONST_VECTOR_ELT (value
, i
), insn
);
15099 gcc_unreachable ();
15102 /* Dump out the constants in CONSTANTS after INSN. */
15105 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
15107 struct mips16_constant
*c
, *next
;
15111 for (c
= constants
; c
!= NULL
; c
= next
)
15113 /* If necessary, increase the alignment of PC. */
15114 if (align
< GET_MODE_SIZE (c
->mode
))
15116 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
15117 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
15119 align
= GET_MODE_SIZE (c
->mode
);
15121 insn
= emit_label_after (c
->label
, insn
);
15122 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
15128 emit_barrier_after (insn
);
15131 /* Return the length of instruction INSN. */
15134 mips16_insn_length (rtx_insn
*insn
)
15136 if (JUMP_TABLE_DATA_P (insn
))
15138 rtx body
= PATTERN (insn
);
15139 if (GET_CODE (body
) == ADDR_VEC
)
15140 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
15141 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
15142 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
15144 gcc_unreachable ();
15146 return get_attr_length (insn
);
15149 /* If *X is a symbolic constant that refers to the constant pool, add
15150 the constant to POOL and rewrite *X to use the constant's label. */
15153 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
15156 rtx_code_label
*label
;
15158 split_const (*x
, &base
, &offset
);
15159 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
15161 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
15162 get_pool_mode (base
));
15163 base
= gen_rtx_LABEL_REF (Pmode
, label
);
15164 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
15168 /* Rewrite INSN so that constant pool references refer to the constant's
15172 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
15174 subrtx_ptr_iterator::array_type array
;
15175 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
15179 if (force_to_mem_operand (*loc
, Pmode
))
15181 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
15182 validate_change (insn
, loc
, mem
, false);
15187 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
15188 iter
.skip_subrtxes ();
15192 if (TARGET_MIPS16_TEXT_LOADS
)
15193 mips16_rewrite_pool_constant (pool
, loc
);
15194 if (GET_CODE (*loc
) == CONST
15195 /* Don't rewrite the __mips16_rdwr symbol. */
15196 || (GET_CODE (*loc
) == UNSPEC
15197 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
15198 iter
.skip_subrtxes ();
15203 /* Return whether CFG is used in mips_reorg. */
15206 mips_cfg_in_reorg (void)
15208 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15209 || TARGET_RELAX_PIC_CALLS
);
15212 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
15213 otherwise assume that they are already split. */
15216 mips16_lay_out_constants (bool split_p
)
15218 struct mips16_constant_pool pool
;
15219 rtx_insn
*insn
, *barrier
;
15221 if (!TARGET_MIPS16_PCREL_LOADS
)
15226 if (mips_cfg_in_reorg ())
15227 split_all_insns ();
15229 split_all_insns_noflow ();
15232 memset (&pool
, 0, sizeof (pool
));
15233 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15235 /* Rewrite constant pool references in INSN. */
15236 if (USEFUL_INSN_P (insn
))
15237 mips16_rewrite_pool_refs (insn
, &pool
);
15239 pool
.insn_address
+= mips16_insn_length (insn
);
15241 if (pool
.first
!= NULL
)
15243 /* If there are no natural barriers between the first user of
15244 the pool and the highest acceptable address, we'll need to
15245 create a new instruction to jump around the constant pool.
15246 In the worst case, this instruction will be 4 bytes long.
15248 If it's too late to do this transformation after INSN,
15249 do it immediately before INSN. */
15250 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
15252 rtx_code_label
*label
;
15255 label
= gen_label_rtx ();
15257 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
15258 JUMP_LABEL (jump
) = label
;
15259 LABEL_NUSES (label
) = 1;
15260 barrier
= emit_barrier_after (jump
);
15262 emit_label_after (label
, barrier
);
15263 pool
.insn_address
+= 4;
15266 /* See whether the constant pool is now out of range of the first
15267 user. If so, output the constants after the previous barrier.
15268 Note that any instructions between BARRIER and INSN (inclusive)
15269 will use negative offsets to refer to the pool. */
15270 if (pool
.insn_address
> pool
.highest_address
)
15272 mips16_emit_constants (pool
.first
, barrier
);
15276 else if (BARRIER_P (insn
))
15280 mips16_emit_constants (pool
.first
, get_last_insn ());
15283 /* Return true if it is worth r10k_simplify_address's while replacing
15284 an address with X. We are looking for constants, and for addresses
15285 at a known offset from the incoming stack pointer. */
15288 r10k_simplified_address_p (rtx x
)
15290 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
15292 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
15295 /* X is an expression that appears in INSN. Try to use the UD chains
15296 to simplify it, returning the simplified form on success and the
15297 original form otherwise. Replace the incoming value of $sp with
15298 virtual_incoming_args_rtx (which should never occur in X otherwise). */
15301 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
15303 rtx newx
, op0
, op1
, set
, note
;
15304 rtx_insn
*def_insn
;
15306 struct df_link
*defs
;
15311 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15312 if (op0
!= XEXP (x
, 0))
15313 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
15314 op0
, GET_MODE (XEXP (x
, 0)));
15316 else if (BINARY_P (x
))
15318 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15319 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
15320 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
15321 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
15323 else if (GET_CODE (x
) == LO_SUM
)
15325 /* LO_SUMs can be offset from HIGHs, if we know they won't
15326 overflow. See mips_classify_address for the rationale behind
15328 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15329 if (GET_CODE (op0
) == HIGH
)
15330 newx
= XEXP (x
, 1);
15332 else if (REG_P (x
))
15334 /* Uses are recorded by regno_reg_rtx, not X itself. */
15335 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
15337 defs
= DF_REF_CHAIN (use
);
15339 /* Require a single definition. */
15340 if (defs
&& defs
->next
== NULL
)
15343 if (DF_REF_IS_ARTIFICIAL (def
))
15345 /* Replace the incoming value of $sp with
15346 virtual_incoming_args_rtx. */
15347 if (x
== stack_pointer_rtx
15348 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
15349 newx
= virtual_incoming_args_rtx
;
15351 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
15354 /* Make sure that DEF_INSN is a single set of REG. */
15355 def_insn
= DF_REF_INSN (def
);
15356 if (NONJUMP_INSN_P (def_insn
))
15358 set
= single_set (def_insn
);
15359 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
15361 /* Prefer to use notes, since the def-use chains
15362 are often shorter. */
15363 note
= find_reg_equal_equiv_note (def_insn
);
15365 newx
= XEXP (note
, 0);
15367 newx
= SET_SRC (set
);
15368 newx
= r10k_simplify_address (newx
, def_insn
);
15374 if (newx
&& r10k_simplified_address_p (newx
))
15379 /* Return true if ADDRESS is known to be an uncached address
15380 on R10K systems. */
15383 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15385 unsigned HOST_WIDE_INT upper
;
15387 /* Check for KSEG1. */
15388 if (address
+ 0x60000000 < 0x20000000)
15391 /* Check for uncached XKPHYS addresses. */
15392 if (Pmode
== DImode
)
15394 upper
= (address
>> 40) & 0xf9ffff;
15395 if (upper
== 0x900000 || upper
== 0xb80000)
15401 /* Return true if we can prove that an access to address X in instruction
15402 INSN would be safe from R10K speculation. This X is a general
15403 expression; it might not be a legitimate address. */
15406 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
15409 HOST_WIDE_INT offset_val
;
15411 x
= r10k_simplify_address (x
, insn
);
15413 /* Check for references to the stack frame. It doesn't really matter
15414 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15415 allows us to assume that accesses to any part of the eventual frame
15416 is safe from speculation at any point in the function. */
15417 mips_split_plus (x
, &base
, &offset_val
);
15418 if (base
== virtual_incoming_args_rtx
15419 && offset_val
>= -cfun
->machine
->frame
.total_size
15420 && offset_val
< cfun
->machine
->frame
.args_size
)
15423 /* Check for uncached addresses. */
15424 if (CONST_INT_P (x
))
15425 return r10k_uncached_address_p (INTVAL (x
));
15427 /* Check for accesses to a static object. */
15428 split_const (x
, &base
, &offset
);
15429 return offset_within_block_p (base
, INTVAL (offset
));
15432 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15433 an in-range access to an automatic variable, or to an object with
15434 a link-time-constant address. */
15437 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15439 HOST_WIDE_INT bitoffset
, bitsize
;
15440 tree inner
, var_offset
;
15442 int unsigned_p
, volatile_p
;
15444 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15445 &unsigned_p
, &volatile_p
, false);
15446 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15449 offset
+= bitoffset
/ BITS_PER_UNIT
;
15450 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15453 /* Return true if X contains a MEM that is not safe from R10K speculation.
15454 INSN is the instruction that contains X. */
15457 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
15459 subrtx_var_iterator::array_type array
;
15460 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
15465 if ((MEM_EXPR (mem
)
15466 && MEM_OFFSET_KNOWN_P (mem
)
15467 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15468 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
15469 iter
.skip_subrtxes ();
15477 /* A note_stores callback for which DATA points to an instruction pointer.
15478 If *DATA is nonnull, make it null if it X contains a MEM that is not
15479 safe from R10K speculation. */
15482 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15485 rtx_insn
**insn_ptr
;
15487 insn_ptr
= (rtx_insn
**) data
;
15488 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
15492 /* X is the pattern of a call instruction. Return true if the call is
15493 not to a declared function. */
15496 r10k_needs_protection_p_call (const_rtx x
)
15498 subrtx_iterator::array_type array
;
15499 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
15501 const_rtx mem
= *iter
;
15504 const_rtx addr
= XEXP (mem
, 0);
15505 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
15506 iter
.skip_subrtxes ();
15514 /* Return true if instruction INSN needs to be protected by an R10K
15518 r10k_needs_protection_p (rtx_insn
*insn
)
15521 return r10k_needs_protection_p_call (PATTERN (insn
));
15523 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15525 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15526 return insn
== NULL_RTX
;
15529 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
15532 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15533 edge is unconditional. */
15536 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15541 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15542 if (!single_succ_p (e
->src
)
15543 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15544 || (e
->flags
& EDGE_COMPLEX
) != 0)
15549 /* Implement -mr10k-cache-barrier= for the current function. */
15552 r10k_insert_cache_barriers (void)
15554 int *rev_post_order
;
15557 sbitmap protected_bbs
;
15558 rtx_insn
*insn
, *end
;
15559 rtx unprotected_region
;
15563 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15567 /* Calculate dominators. */
15568 calculate_dominance_info (CDI_DOMINATORS
);
15570 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15571 X is protected by a cache barrier. */
15572 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15573 bitmap_clear (protected_bbs
);
15575 /* Iterate over the basic blocks in reverse post-order. */
15576 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15577 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15578 for (i
= 0; i
< n
; i
++)
15580 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15582 /* If this block is only reached by unconditional edges, and if the
15583 source of every edge is protected, the beginning of the block is
15585 if (r10k_protected_bb_p (bb
, protected_bbs
))
15586 unprotected_region
= NULL_RTX
;
15588 unprotected_region
= pc_rtx
;
15589 end
= NEXT_INSN (BB_END (bb
));
15591 /* UNPROTECTED_REGION is:
15593 - null if we are processing a protected region,
15594 - pc_rtx if we are processing an unprotected region but have
15595 not yet found the first instruction in it
15596 - the first instruction in an unprotected region otherwise. */
15597 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15599 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15601 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15602 /* This CACHE instruction protects the following code. */
15603 unprotected_region
= NULL_RTX
;
15606 /* See if INSN is the first instruction in this
15607 unprotected region. */
15608 if (unprotected_region
== pc_rtx
)
15609 unprotected_region
= insn
;
15611 /* See if INSN needs to be protected. If so,
15612 we must insert a cache barrier somewhere between
15613 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15614 clear which position is better performance-wise,
15615 but as a tie-breaker, we assume that it is better
15616 to allow delay slots to be back-filled where
15617 possible, and that it is better not to insert
15618 barriers in the middle of already-scheduled code.
15619 We therefore insert the barrier at the beginning
15621 if (r10k_needs_protection_p (insn
))
15623 emit_insn_before (gen_r10k_cache_barrier (),
15624 unprotected_region
);
15625 unprotected_region
= NULL_RTX
;
15631 /* The called function is not required to protect the exit path.
15632 The code that follows a call is therefore unprotected. */
15633 unprotected_region
= pc_rtx
;
15636 /* Record whether the end of this block is protected. */
15637 if (unprotected_region
== NULL_RTX
)
15638 bitmap_set_bit (protected_bbs
, bb
->index
);
15640 XDELETEVEC (rev_post_order
);
15642 sbitmap_free (protected_bbs
);
15644 free_dominance_info (CDI_DOMINATORS
);
15647 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15648 otherwise. If INSN has two call rtx, then store the second one in
15652 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
15657 if (!CALL_P (insn
))
15660 x
= PATTERN (insn
);
15661 if (GET_CODE (x
) == PARALLEL
)
15663 /* Calls returning complex values have two CALL rtx. Look for the second
15664 one here, and return it via the SECOND_CALL arg. */
15665 x2
= XVECEXP (x
, 0, 1);
15666 if (GET_CODE (x2
) == SET
)
15668 if (GET_CODE (x2
) == CALL
)
15671 x
= XVECEXP (x
, 0, 0);
15673 if (GET_CODE (x
) == SET
)
15675 gcc_assert (GET_CODE (x
) == CALL
);
15680 /* REG is set in DEF. See if the definition is one of the ways we load a
15681 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15682 If it is, return the symbol reference of the function, otherwise return
15685 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15686 the values of source registers, otherwise treat such registers as
15687 having an unknown value. */
15690 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15692 rtx_insn
*def_insn
;
15695 if (DF_REF_IS_ARTIFICIAL (def
))
15698 def_insn
= DF_REF_INSN (def
);
15699 set
= single_set (def_insn
);
15700 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15702 rtx note
, src
, symbol
;
15704 /* First see whether the source is a plain symbol. This is used
15705 when calling symbols that are not lazily bound. */
15706 src
= SET_SRC (set
);
15707 if (GET_CODE (src
) == SYMBOL_REF
)
15710 /* Handle %call16 references. */
15711 symbol
= mips_strip_unspec_call (src
);
15714 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15718 /* If we have something more complicated, look for a
15719 REG_EQUAL or REG_EQUIV note. */
15720 note
= find_reg_equal_equiv_note (def_insn
);
15721 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15722 return XEXP (note
, 0);
15724 /* Follow at most one simple register copy. Such copies are
15725 interesting in cases like:
15729 locally_binding_fn (...);
15734 locally_binding_fn (...);
15736 locally_binding_fn (...);
15738 where the load of locally_binding_fn can legitimately be
15739 hoisted or shared. However, we do not expect to see complex
15740 chains of copies, so a full worklist solution to the problem
15741 would probably be overkill. */
15742 if (recurse_p
&& REG_P (src
))
15743 return mips_find_pic_call_symbol (def_insn
, src
, false);
15749 /* Find the definition of the use of REG in INSN. See if the definition
15750 is one of the ways we load a register with a symbol address for a
15751 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15752 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15753 mips_pic_call_symbol_from_set. */
15756 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
15759 struct df_link
*defs
;
15762 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15765 defs
= DF_REF_CHAIN (use
);
15768 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15772 /* If we have more than one definition, they need to be identical. */
15773 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15777 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15778 if (!rtx_equal_p (symbol
, other
))
15785 /* Replace the args_size operand of the call expression CALL with the
15786 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15789 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15793 args_size
= XEXP (call
, 1);
15794 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15795 gen_rtvec (2, args_size
, symbol
),
15799 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15800 if instead of the arg_size argument it contains the call attributes. If
15801 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15802 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15806 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15808 rtx args_size
, symbol
;
15810 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15813 args_size
= operands
[args_size_opno
];
15814 if (GET_CODE (args_size
) != UNSPEC
)
15816 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15818 symbol
= XVECEXP (args_size
, 0, 1);
15819 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15821 operands
[args_size_opno
] = symbol
;
15825 /* Use DF to annotate PIC indirect calls with the function symbol they
15829 mips_annotate_pic_calls (void)
15834 FOR_EACH_BB_FN (bb
, cfun
)
15835 FOR_BB_INSNS (bb
, insn
)
15837 rtx call
, reg
, symbol
, second_call
;
15840 call
= mips_call_expr_from_insn (insn
, &second_call
);
15843 gcc_assert (MEM_P (XEXP (call
, 0)));
15844 reg
= XEXP (XEXP (call
, 0), 0);
15848 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15851 mips_annotate_pic_call_expr (call
, symbol
);
15853 mips_annotate_pic_call_expr (second_call
, symbol
);
15858 /* A temporary variable used by note_uses callbacks, etc. */
15859 static rtx_insn
*mips_sim_insn
;
15861 /* A structure representing the state of the processor pipeline.
15862 Used by the mips_sim_* family of functions. */
15864 /* The maximum number of instructions that can be issued in a cycle.
15865 (Caches mips_issue_rate.) */
15866 unsigned int issue_rate
;
15868 /* The current simulation time. */
15871 /* How many more instructions can be issued in the current cycle. */
15872 unsigned int insns_left
;
15874 /* LAST_SET[X].INSN is the last instruction to set register X.
15875 LAST_SET[X].TIME is the time at which that instruction was issued.
15876 INSN is null if no instruction has yet set register X. */
15880 } last_set
[FIRST_PSEUDO_REGISTER
];
15882 /* The pipeline's current DFA state. */
15886 /* Reset STATE to the initial simulation state. */
15889 mips_sim_reset (struct mips_sim
*state
)
15891 curr_state
= state
->dfa_state
;
15894 state
->insns_left
= state
->issue_rate
;
15895 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15896 state_reset (curr_state
);
15898 targetm
.sched
.init (0, false, 0);
15899 advance_state (curr_state
);
15902 /* Initialize STATE before its first use. DFA_STATE points to an
15903 allocated but uninitialized DFA state. */
15906 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15908 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15909 targetm
.sched
.init_dfa_pre_cycle_insn ();
15911 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15912 targetm
.sched
.init_dfa_post_cycle_insn ();
15914 state
->issue_rate
= mips_issue_rate ();
15915 state
->dfa_state
= dfa_state
;
15916 mips_sim_reset (state
);
15919 /* Advance STATE by one clock cycle. */
15922 mips_sim_next_cycle (struct mips_sim
*state
)
15924 curr_state
= state
->dfa_state
;
15927 state
->insns_left
= state
->issue_rate
;
15928 advance_state (curr_state
);
15931 /* Advance simulation state STATE until instruction INSN can read
15935 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
15937 unsigned int regno
, end_regno
;
15939 end_regno
= END_REGNO (reg
);
15940 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15941 if (state
->last_set
[regno
].insn
!= 0)
15945 t
= (state
->last_set
[regno
].time
15946 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15947 while (state
->time
< t
)
15948 mips_sim_next_cycle (state
);
15952 /* A note_uses callback. For each register in *X, advance simulation
15953 state DATA until mips_sim_insn can read the register's value. */
15956 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15958 subrtx_var_iterator::array_type array
;
15959 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
15961 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
15964 /* Advance simulation state STATE until all of INSN's register
15965 dependencies are satisfied. */
15968 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
15970 mips_sim_insn
= insn
;
15971 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15974 /* Advance simulation state STATE until the units required by
15975 instruction INSN are available. */
15978 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
15982 tmp_state
= alloca (state_size ());
15983 while (state
->insns_left
== 0
15984 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15985 state_transition (tmp_state
, insn
) >= 0))
15986 mips_sim_next_cycle (state
);
15989 /* Advance simulation state STATE until INSN is ready to issue. */
15992 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15994 mips_sim_wait_regs (state
, insn
);
15995 mips_sim_wait_units (state
, insn
);
15998 /* mips_sim_insn has just set X. Update the LAST_SET array
15999 in simulation state DATA. */
16002 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
16004 struct mips_sim
*state
;
16006 state
= (struct mips_sim
*) data
;
16009 unsigned int regno
, end_regno
;
16011 end_regno
= END_REGNO (x
);
16012 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
16014 state
->last_set
[regno
].insn
= mips_sim_insn
;
16015 state
->last_set
[regno
].time
= state
->time
;
16020 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
16021 can issue immediately (i.e., that mips_sim_wait_insn has already
16025 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
16027 curr_state
= state
->dfa_state
;
16029 state_transition (curr_state
, insn
);
16030 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
16031 state
->insns_left
);
16033 mips_sim_insn
= insn
;
16034 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
16037 /* Simulate issuing a NOP in state STATE. */
16040 mips_sim_issue_nop (struct mips_sim
*state
)
16042 if (state
->insns_left
== 0)
16043 mips_sim_next_cycle (state
);
16044 state
->insns_left
--;
16047 /* Update simulation state STATE so that it's ready to accept the instruction
16048 after INSN. INSN should be part of the main rtl chain, not a member of a
16052 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
16054 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
16056 mips_sim_issue_nop (state
);
16058 switch (GET_CODE (SEQ_BEGIN (insn
)))
16062 /* We can't predict the processor state after a call or label. */
16063 mips_sim_reset (state
);
16067 /* The delay slots of branch likely instructions are only executed
16068 when the branch is taken. Therefore, if the caller has simulated
16069 the delay slot instruction, STATE does not really reflect the state
16070 of the pipeline for the instruction after the delay slot. Also,
16071 branch likely instructions tend to incur a penalty when not taken,
16072 so there will probably be an extra delay between the branch and
16073 the instruction after the delay slot. */
16074 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
16075 mips_sim_reset (state
);
16083 /* Use simulator state STATE to calculate the execution time of
16084 instruction sequence SEQ. */
16086 static unsigned int
16087 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
16089 mips_sim_reset (state
);
16090 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
16092 mips_sim_wait_insn (state
, insn
);
16093 mips_sim_issue_insn (state
, insn
);
16095 return state
->time
;
16098 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
16099 setting SETTING, using STATE to simulate instruction sequences. */
16101 static unsigned int
16102 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
16104 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
16107 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
16108 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
16109 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
16111 /* If the target provides mulsidi3_32bit then that's the most likely
16112 consumer of the result. Test for bypasses. */
16113 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
16115 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
16116 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
16119 unsigned int time
= mips_seq_time (state
, get_insns ());
16124 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
16125 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
16126 Prefer MULT -- which is shorter -- in the event of a tie. */
16129 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
16131 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
16132 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
16133 registers then there is no reason to zero them, arbitrarily choose to
16134 say that "MULT $0,$0" would be faster. */
16135 mips_tuning_info
.fast_mult_zero_zero_p
= true;
16138 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
16139 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
16140 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
16144 /* Set up costs based on the current architecture and tuning settings. */
16147 mips_set_tuning_info (void)
16149 if (mips_tuning_info
.initialized_p
16150 && mips_tuning_info
.arch
== mips_arch
16151 && mips_tuning_info
.tune
== mips_tune
16152 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
16155 mips_tuning_info
.arch
= mips_arch
;
16156 mips_tuning_info
.tune
= mips_tune
;
16157 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
16158 mips_tuning_info
.initialized_p
= true;
16162 struct mips_sim state
;
16163 mips_sim_init (&state
, alloca (state_size ()));
16165 mips_set_fast_mult_zero_zero_p (&state
);
16170 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
16173 mips_expand_to_rtl_hook (void)
16175 /* We need to call this at a point where we can safely create sequences
16176 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
16177 need to call it at a point where the DFA infrastructure is not
16178 already in use, so we can't just call it lazily on demand.
16180 At present, mips_tuning_info is only needed during post-expand
16181 RTL passes such as split_insns, so this hook should be early enough.
16182 We may need to move the call elsewhere if mips_tuning_info starts
16183 to be used for other things (such as rtx_costs, or expanders that
16184 could be called during gimple optimization). */
16185 mips_set_tuning_info ();
16188 /* The VR4130 pipeline issues aligned pairs of instructions together,
16189 but it stalls the second instruction if it depends on the first.
16190 In order to cut down the amount of logic required, this dependence
16191 check is not based on a full instruction decode. Instead, any non-SPECIAL
16192 instruction is assumed to modify the register specified by bits 20-16
16193 (which is usually the "rt" field).
16195 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
16196 input, so we can end up with a false dependence between the branch
16197 and its delay slot. If this situation occurs in instruction INSN,
16198 try to avoid it by swapping rs and rt. */
16201 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
16203 rtx_insn
*first
, *second
;
16205 first
= SEQ_BEGIN (insn
);
16206 second
= SEQ_END (insn
);
16208 && NONJUMP_INSN_P (second
)
16209 && GET_CODE (PATTERN (first
)) == SET
16210 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
16211 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
16213 /* Check for the right kind of condition. */
16214 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
16215 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
16216 && REG_P (XEXP (cond
, 0))
16217 && REG_P (XEXP (cond
, 1))
16218 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
16219 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
16221 /* SECOND mentions the rt register but not the rs register. */
16222 rtx tmp
= XEXP (cond
, 0);
16223 XEXP (cond
, 0) = XEXP (cond
, 1);
16224 XEXP (cond
, 1) = tmp
;
16229 /* Implement -mvr4130-align. Go through each basic block and simulate the
16230 processor pipeline. If we find that a pair of instructions could execute
16231 in parallel, and the first of those instructions is not 8-byte aligned,
16232 insert a nop to make it aligned. */
16235 vr4130_align_insns (void)
16237 struct mips_sim state
;
16238 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
16243 /* LAST is the last instruction before INSN to have a nonzero length.
16244 LAST2 is the last such instruction before LAST. */
16248 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
16251 mips_sim_init (&state
, alloca (state_size ()));
16252 for (insn
= get_insns (); insn
!= 0; insn
= next
)
16254 unsigned int length
;
16256 next
= NEXT_INSN (insn
);
16258 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
16259 This isn't really related to the alignment pass, but we do it on
16260 the fly to avoid a separate instruction walk. */
16261 vr4130_avoid_branch_rt_conflict (insn
);
16263 length
= get_attr_length (insn
);
16264 if (length
> 0 && USEFUL_INSN_P (insn
))
16265 FOR_EACH_SUBINSN (subinsn
, insn
)
16267 mips_sim_wait_insn (&state
, subinsn
);
16269 /* If we want this instruction to issue in parallel with the
16270 previous one, make sure that the previous instruction is
16271 aligned. There are several reasons why this isn't worthwhile
16272 when the second instruction is a call:
16274 - Calls are less likely to be performance critical,
16275 - There's a good chance that the delay slot can execute
16276 in parallel with the call.
16277 - The return address would then be unaligned.
16279 In general, if we're going to insert a nop between instructions
16280 X and Y, it's better to insert it immediately after X. That
16281 way, if the nop makes Y aligned, it will also align any labels
16282 between X and Y. */
16283 if (state
.insns_left
!= state
.issue_rate
16284 && !CALL_P (subinsn
))
16286 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
16288 /* SUBINSN is the first instruction in INSN and INSN is
16289 aligned. We want to align the previous instruction
16290 instead, so insert a nop between LAST2 and LAST.
16292 Note that LAST could be either a single instruction
16293 or a branch with a delay slot. In the latter case,
16294 LAST, like INSN, is already aligned, but the delay
16295 slot must have some extra delay that stops it from
16296 issuing at the same time as the branch. We therefore
16297 insert a nop before the branch in order to align its
16299 gcc_assert (last2
);
16300 emit_insn_after (gen_nop (), last2
);
16303 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
16305 /* SUBINSN is the delay slot of INSN, but INSN is
16306 currently unaligned. Insert a nop between
16307 LAST and INSN to align it. */
16309 emit_insn_after (gen_nop (), last
);
16313 mips_sim_issue_insn (&state
, subinsn
);
16315 mips_sim_finish_insn (&state
, insn
);
16317 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16318 length
= get_attr_length (insn
);
16321 /* If the instruction is an asm statement or multi-instruction
16322 mips.md patern, the length is only an estimate. Insert an
16323 8 byte alignment after it so that the following instructions
16324 can be handled correctly. */
16325 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
16326 && (recog_memoized (insn
) < 0 || length
>= 8))
16328 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
16329 next
= NEXT_INSN (next
);
16330 mips_sim_next_cycle (&state
);
16333 else if (length
& 4)
16334 aligned_p
= !aligned_p
;
16339 /* See whether INSN is an aligned label. */
16340 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
16346 /* This structure records that the current function has a LO_SUM
16347 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16348 the largest offset applied to BASE by all such LO_SUMs. */
16349 struct mips_lo_sum_offset
{
16351 HOST_WIDE_INT offset
;
16354 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16357 mips_hash_base (rtx base
)
16359 int do_not_record_p
;
16361 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
16364 /* Hashtable helpers. */
16366 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
16368 typedef mips_lo_sum_offset
*value_type
;
16369 typedef rtx_def
*compare_type
;
16370 static inline hashval_t
hash (const mips_lo_sum_offset
*);
16371 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
16374 /* Hash-table callbacks for mips_lo_sum_offsets. */
16377 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
16379 return mips_hash_base (entry
->base
);
16383 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
16384 const rtx_def
*value
)
16386 return rtx_equal_p (entry
->base
, value
);
16389 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16391 /* Look up symbolic constant X in HTAB, which is a hash table of
16392 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16393 paired with a recorded LO_SUM, otherwise record X in the table. */
16396 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
16397 enum insert_option option
)
16400 mips_lo_sum_offset
**slot
;
16401 struct mips_lo_sum_offset
*entry
;
16403 /* Split X into a base and offset. */
16404 split_const (x
, &base
, &offset
);
16405 if (UNSPEC_ADDRESS_P (base
))
16406 base
= UNSPEC_ADDRESS (base
);
16408 /* Look up the base in the hash table. */
16409 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
16413 entry
= (struct mips_lo_sum_offset
*) *slot
;
16414 if (option
== INSERT
)
16418 entry
= XNEW (struct mips_lo_sum_offset
);
16419 entry
->base
= base
;
16420 entry
->offset
= INTVAL (offset
);
16425 if (INTVAL (offset
) > entry
->offset
)
16426 entry
->offset
= INTVAL (offset
);
16429 return INTVAL (offset
) <= entry
->offset
;
16432 /* Search X for LO_SUMs and record them in HTAB. */
16435 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
16437 subrtx_iterator::array_type array
;
16438 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
16439 if (GET_CODE (*iter
) == LO_SUM
)
16440 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
16443 /* Return true if INSN is a SET of an orphaned high-part relocation.
16444 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16445 LO_SUMs in the current function. */
16448 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
16450 enum mips_symbol_type type
;
16453 set
= single_set (insn
);
16456 /* Check for %his. */
16458 if (GET_CODE (x
) == HIGH
16459 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16460 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16462 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16463 if (GET_CODE (x
) == UNSPEC
16464 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16465 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16466 SYMBOL_CONTEXT_LEA
, &type
)
16467 && type
== SYMBOL_GOTOFF_PAGE
)
16468 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16473 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16474 INSN and a previous instruction, avoid it by inserting nops after
16477 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16478 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16479 before using the value of that register. *HILO_DELAY counts the
16480 number of instructions since the last hilo hazard (that is,
16481 the number of instructions since the last MFLO or MFHI).
16483 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16484 for the next instruction.
16486 LO_REG is an rtx for the LO register, used in dependence checking. */
16489 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
16490 rtx
*delayed_reg
, rtx lo_reg
)
16495 pattern
= PATTERN (insn
);
16497 /* Do not put the whole function in .set noreorder if it contains
16498 an asm statement. We don't know whether there will be hazards
16499 between the asm statement and the gcc-generated code. */
16500 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16501 cfun
->machine
->all_noreorder_p
= false;
16503 /* Ignore zero-length instructions (barriers and the like). */
16504 ninsns
= get_attr_length (insn
) / 4;
16508 /* Work out how many nops are needed. Note that we only care about
16509 registers that are explicitly mentioned in the instruction's pattern.
16510 It doesn't matter that calls use the argument registers or that they
16511 clobber hi and lo. */
16512 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16513 nops
= 2 - *hilo_delay
;
16514 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16519 /* Insert the nops between this instruction and the previous one.
16520 Each new nop takes us further from the last hilo hazard. */
16521 *hilo_delay
+= nops
;
16523 emit_insn_after (gen_hazard_nop (), after
);
16525 /* Set up the state for the next instruction. */
16526 *hilo_delay
+= ninsns
;
16528 if (INSN_CODE (insn
) >= 0)
16529 switch (get_attr_hazard (insn
))
16539 set
= single_set (insn
);
16541 *delayed_reg
= SET_DEST (set
);
16546 /* Go through the instruction stream and insert nops where necessary.
16547 Also delete any high-part relocations whose partnering low parts
16548 are now all dead. See if the whole function can then be put into
16549 .set noreorder and .set nomacro. */
16552 mips_reorg_process_insns (void)
16554 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
16555 rtx lo_reg
, delayed_reg
;
16558 /* Force all instructions to be split into their final form. */
16559 split_all_insns_noflow ();
16561 /* Recalculate instruction lengths without taking nops into account. */
16562 cfun
->machine
->ignore_hazard_length_p
= true;
16563 shorten_branches (get_insns ());
16565 cfun
->machine
->all_noreorder_p
= true;
16567 /* We don't track MIPS16 PC-relative offsets closely enough to make
16568 a good job of "set .noreorder" code in MIPS16 mode. */
16570 cfun
->machine
->all_noreorder_p
= false;
16572 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16573 if (!TARGET_EXPLICIT_RELOCS
)
16574 cfun
->machine
->all_noreorder_p
= false;
16576 /* Profiled functions can't be all noreorder because the profiler
16577 support uses assembler macros. */
16579 cfun
->machine
->all_noreorder_p
= false;
16581 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16582 all noreorder because we rely on the assembler to work around some
16583 errata. The R5900 too has several bugs. */
16584 if (TARGET_FIX_VR4120
16585 || TARGET_FIX_RM7000
16587 || TARGET_MIPS5900
)
16588 cfun
->machine
->all_noreorder_p
= false;
16590 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16591 MFHI instructions. Note that we avoid using MFLO and MFHI if
16592 the VR4130 MACC and DMACC instructions are available instead;
16593 see the *mfhilo_{si,di}_macc patterns. */
16594 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16595 cfun
->machine
->all_noreorder_p
= false;
16597 mips_offset_table
htab (37);
16599 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16600 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16601 FOR_EACH_SUBINSN (subinsn
, insn
)
16602 if (USEFUL_INSN_P (subinsn
))
16604 rtx body
= PATTERN (insn
);
16605 int noperands
= asm_noperands (body
);
16606 if (noperands
>= 0)
16608 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16609 bool *used
= XALLOCAVEC (bool, noperands
);
16610 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16612 get_referenced_operands (string
, used
, noperands
);
16613 for (int i
= 0; i
< noperands
; ++i
)
16615 mips_record_lo_sums (ops
[i
], &htab
);
16618 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
16624 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16626 /* Make a second pass over the instructions. Delete orphaned
16627 high-part relocations or turn them into NOPs. Avoid hazards
16628 by inserting NOPs. */
16629 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16631 next_insn
= NEXT_INSN (insn
);
16632 if (USEFUL_INSN_P (insn
))
16634 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16636 /* If we find an orphaned high-part relocation in a delay
16637 slot, it's easier to turn that instruction into a NOP than
16638 to delete it. The delay slot will be a NOP either way. */
16639 FOR_EACH_SUBINSN (subinsn
, insn
)
16640 if (INSN_P (subinsn
))
16642 if (mips_orphaned_high_part_p (&htab
, subinsn
))
16644 PATTERN (subinsn
) = gen_nop ();
16645 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16647 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16648 &delayed_reg
, lo_reg
);
16654 /* INSN is a single instruction. Delete it if it's an
16655 orphaned high-part relocation. */
16656 if (mips_orphaned_high_part_p (&htab
, insn
))
16657 delete_insn (insn
);
16658 /* Also delete cache barriers if the last instruction
16659 was an annulled branch. INSN will not be speculatively
16661 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16663 && JUMP_P (SEQ_BEGIN (last_insn
))
16664 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16665 delete_insn (insn
);
16668 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16669 &delayed_reg
, lo_reg
);
16677 /* Return true if the function has a long branch instruction. */
16680 mips_has_long_branch_p (void)
16682 rtx_insn
*insn
, *subinsn
;
16685 /* We need up-to-date instruction lengths. */
16686 shorten_branches (get_insns ());
16688 /* Look for a branch that is longer than normal. The normal length for
16689 non-MIPS16 branches is 8, because the length includes the delay slot.
16690 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16691 but they have no delay slot. */
16692 normal_length
= (TARGET_MIPS16
? 4 : 8);
16693 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16694 FOR_EACH_SUBINSN (subinsn
, insn
)
16695 if (JUMP_P (subinsn
)
16696 && get_attr_length (subinsn
) > normal_length
16697 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16703 /* If we are using a GOT, but have not decided to use a global pointer yet,
16704 see whether we need one to implement long branches. Convert the ghost
16705 global-pointer instructions into real ones if so. */
16708 mips_expand_ghost_gp_insns (void)
16710 /* Quick exit if we already know that we will or won't need a
16712 if (!TARGET_USE_GOT
16713 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16714 || mips_must_initialize_gp_p ())
16717 /* Run a full check for long branches. */
16718 if (!mips_has_long_branch_p ())
16721 /* We've now established that we need $gp. */
16722 cfun
->machine
->must_initialize_gp_p
= true;
16723 split_all_insns_noflow ();
16728 /* Subroutine of mips_reorg to manage passes that require DF. */
16731 mips_df_reorg (void)
16733 /* Create def-use chains. */
16734 df_set_flags (DF_EQ_NOTES
);
16735 df_chain_add_problem (DF_UD_CHAIN
);
16738 if (TARGET_RELAX_PIC_CALLS
)
16739 mips_annotate_pic_calls ();
16741 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16742 r10k_insert_cache_barriers ();
16744 df_finish_pass (false);
16747 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16748 called very late in mips_reorg, but the caller is required to run
16749 mips16_lay_out_constants on the result. */
16752 mips16_load_branch_target (rtx dest
, rtx src
)
16754 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16758 if (mips_cfun_has_cprestore_slot_p ())
16759 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16761 mips_emit_move (dest
, pic_offset_table_rtx
);
16762 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16763 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16764 emit_insn (gen_rtx_SET (dest
,
16765 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16766 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16770 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16771 mips_emit_move (dest
, src
);
16775 /* If we're compiling a MIPS16 function, look for and split any long branches.
16776 This must be called after all other instruction modifications in
16780 mips16_split_long_branches (void)
16782 bool something_changed
;
16784 if (!TARGET_MIPS16
)
16787 /* Loop until the alignments for all targets are sufficient. */
16792 shorten_branches (get_insns ());
16793 something_changed
= false;
16794 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16796 && get_attr_length (insn
) > 4
16797 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16799 rtx old_label
, temp
, saved_temp
;
16800 rtx_code_label
*new_label
;
16802 rtx_insn
*jump
, *jump_sequence
;
16806 /* Free up a MIPS16 register by saving it in $1. */
16807 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16808 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16809 emit_move_insn (saved_temp
, temp
);
16811 /* Load the branch target into TEMP. */
16812 old_label
= JUMP_LABEL (insn
);
16813 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16814 mips16_load_branch_target (temp
, target
);
16816 /* Jump to the target and restore the register's
16818 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16819 (temp
, temp
, saved_temp
)));
16820 JUMP_LABEL (jump
) = old_label
;
16821 LABEL_NUSES (old_label
)++;
16823 /* Rewrite any symbolic references that are supposed to use
16824 a PC-relative constant pool. */
16825 mips16_lay_out_constants (false);
16827 if (simplejump_p (insn
))
16828 /* We're going to replace INSN with a longer form. */
16832 /* Create a branch-around label for the original
16834 new_label
= gen_label_rtx ();
16835 emit_label (new_label
);
16838 jump_sequence
= get_insns ();
16841 emit_insn_after (jump_sequence
, insn
);
16843 invert_jump (insn
, new_label
, false);
16845 delete_insn (insn
);
16846 something_changed
= true;
16849 while (something_changed
);
16852 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16857 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16858 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16859 to date if the CFG is available. */
16860 if (mips_cfg_in_reorg ())
16861 compute_bb_for_insn ();
16862 mips16_lay_out_constants (true);
16863 if (mips_cfg_in_reorg ())
16866 free_bb_for_insn ();
16870 /* We use a machine specific pass to do a second machine dependent reorg
16871 pass after delay branch scheduling. */
16873 static unsigned int
16874 mips_machine_reorg2 (void)
16876 mips_reorg_process_insns ();
16878 && TARGET_EXPLICIT_RELOCS
16880 && TARGET_VR4130_ALIGN
)
16881 vr4130_align_insns ();
16882 if (mips_expand_ghost_gp_insns ())
16883 /* The expansion could invalidate some of the VR4130 alignment
16884 optimizations, but this should be an extremely rare case anyhow. */
16885 mips_reorg_process_insns ();
16886 mips16_split_long_branches ();
16892 const pass_data pass_data_mips_machine_reorg2
=
16894 RTL_PASS
, /* type */
16895 "mach2", /* name */
16896 OPTGROUP_NONE
, /* optinfo_flags */
16897 TV_MACH_DEP
, /* tv_id */
16898 0, /* properties_required */
16899 0, /* properties_provided */
16900 0, /* properties_destroyed */
16901 0, /* todo_flags_start */
16902 0, /* todo_flags_finish */
16905 class pass_mips_machine_reorg2
: public rtl_opt_pass
16908 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16909 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16912 /* opt_pass methods: */
16913 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
16915 }; // class pass_mips_machine_reorg2
16917 } // anon namespace
16920 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16922 return new pass_mips_machine_reorg2 (ctxt
);
16926 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16927 in order to avoid duplicating too much logic from elsewhere. */
16930 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16931 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16934 rtx this_rtx
, temp1
, temp2
, fnaddr
;
16936 bool use_sibcall_p
;
16938 /* Pretend to be a post-reload pass while generating rtl. */
16939 reload_completed
= 1;
16941 /* Mark the end of the (empty) prologue. */
16942 emit_note (NOTE_INSN_PROLOGUE_END
);
16944 /* Determine if we can use a sibcall to call FUNCTION directly. */
16945 fnaddr
= XEXP (DECL_RTL (function
), 0);
16946 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16947 && const_call_insn_operand (fnaddr
, Pmode
));
16949 /* Determine if we need to load FNADDR from the GOT. */
16951 && (mips_got_symbol_type_p
16952 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16954 /* Pick a global pointer. Use a call-clobbered register if
16955 TARGET_CALL_SAVED_GP. */
16956 cfun
->machine
->global_pointer
16957 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16958 cfun
->machine
->must_initialize_gp_p
= true;
16959 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16961 /* Set up the global pointer for n32 or n64 abicalls. */
16962 mips_emit_loadgp ();
16965 /* We need two temporary registers in some cases. */
16966 temp1
= gen_rtx_REG (Pmode
, 2);
16967 temp2
= gen_rtx_REG (Pmode
, 3);
16969 /* Find out which register contains the "this" pointer. */
16970 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16971 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16973 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16975 /* Add DELTA to THIS_RTX. */
16978 rtx offset
= GEN_INT (delta
);
16979 if (!SMALL_OPERAND (delta
))
16981 mips_emit_move (temp1
, offset
);
16984 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16987 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16988 if (vcall_offset
!= 0)
16992 /* Set TEMP1 to *THIS_RTX. */
16993 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16995 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16996 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16998 /* Load the offset and add it to THIS_RTX. */
16999 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
17000 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
17003 /* Jump to the target function. Use a sibcall if direct jumps are
17004 allowed, otherwise load the address into a register first. */
17007 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
17008 SIBLING_CALL_P (insn
) = 1;
17012 /* This is messy. GAS treats "la $25,foo" as part of a call
17013 sequence and may allow a global "foo" to be lazily bound.
17014 The general move patterns therefore reject this combination.
17016 In this context, lazy binding would actually be OK
17017 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
17018 TARGET_CALL_SAVED_GP; see mips_load_call_address.
17019 We must therefore load the address via a temporary
17020 register if mips_dangerous_for_la25_p.
17022 If we jump to the temporary register rather than $25,
17023 the assembler can use the move insn to fill the jump's
17026 We can use the same technique for MIPS16 code, where $25
17027 is not a valid JR register. */
17028 if (TARGET_USE_PIC_FN_ADDR_REG
17030 && !mips_dangerous_for_la25_p (fnaddr
))
17031 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
17032 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
17034 if (TARGET_USE_PIC_FN_ADDR_REG
17035 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
17036 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
17037 emit_jump_insn (gen_indirect_jump (temp1
));
17040 /* Run just enough of rest_of_compilation. This sequence was
17041 "borrowed" from alpha.c. */
17042 insn
= get_insns ();
17043 split_all_insns_noflow ();
17044 mips16_lay_out_constants (true);
17045 shorten_branches (insn
);
17046 final_start_function (insn
, file
, 1);
17047 final (insn
, file
, 1);
17048 final_end_function ();
17050 /* Clean up the vars set above. Note that final_end_function resets
17051 the global pointer for us. */
17052 reload_completed
= 0;
17056 /* The last argument passed to mips_set_compression_mode,
17057 or negative if the function hasn't been called yet. */
17058 static unsigned int old_compression_mode
= -1;
17060 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
17061 which is either MASK_MIPS16 or MASK_MICROMIPS. */
17064 mips_set_compression_mode (unsigned int compression_mode
)
17067 if (compression_mode
== old_compression_mode
)
17070 /* Restore base settings of various flags. */
17071 target_flags
= mips_base_target_flags
;
17072 flag_schedule_insns
= mips_base_schedule_insns
;
17073 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
17074 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
17075 align_loops
= mips_base_align_loops
;
17076 align_jumps
= mips_base_align_jumps
;
17077 align_functions
= mips_base_align_functions
;
17078 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
17079 target_flags
|= compression_mode
;
17081 if (compression_mode
& MASK_MIPS16
)
17083 /* Switch to MIPS16 mode. */
17084 target_flags
|= MASK_MIPS16
;
17086 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
17087 target_flags
&= ~MASK_SYNCI
;
17089 /* Don't run the scheduler before reload, since it tends to
17090 increase register pressure. */
17091 flag_schedule_insns
= 0;
17093 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
17094 the whole function to be in a single section. */
17095 flag_reorder_blocks_and_partition
= 0;
17097 /* Don't move loop invariants, because it tends to increase
17098 register pressure. It also introduces an extra move in cases
17099 where the constant is the first operand in a two-operand binary
17100 instruction, or when it forms a register argument to a functon
17102 flag_move_loop_invariants
= 0;
17104 target_flags
|= MASK_EXPLICIT_RELOCS
;
17106 /* Experiments suggest we get the best overall section-anchor
17107 results from using the range of an unextended LW or SW. Code
17108 that makes heavy use of byte or short accesses can do better
17109 with ranges of 0...31 and 0...63 respectively, but most code is
17110 sensitive to the range of LW and SW instead. */
17111 targetm
.min_anchor_offset
= 0;
17112 targetm
.max_anchor_offset
= 127;
17114 targetm
.const_anchor
= 0;
17116 /* MIPS16 has no BAL instruction. */
17117 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17119 /* The R4000 errata don't apply to any known MIPS16 cores.
17120 It's simpler to make the R4000 fixes and MIPS16 mode
17121 mutually exclusive. */
17122 target_flags
&= ~MASK_FIX_R4000
;
17124 if (flag_pic
&& !TARGET_OLDABI
)
17125 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
17128 sorry ("MIPS16 -mxgot code");
17130 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
17131 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
17135 /* Switch to microMIPS or the standard encoding. */
17137 if (TARGET_MICROMIPS
)
17138 /* Avoid branch likely. */
17139 target_flags
&= ~MASK_BRANCHLIKELY
;
17141 /* Provide default values for align_* for 64-bit targets. */
17144 if (align_loops
== 0)
17146 if (align_jumps
== 0)
17148 if (align_functions
== 0)
17149 align_functions
= 8;
17152 targetm
.min_anchor_offset
= -32768;
17153 targetm
.max_anchor_offset
= 32767;
17155 targetm
.const_anchor
= 0x8000;
17158 /* (Re)initialize MIPS target internals for new ISA. */
17159 mips_init_relocs ();
17161 if (compression_mode
& MASK_MIPS16
)
17163 if (!mips16_globals
)
17164 mips16_globals
= save_target_globals_default_opts ();
17166 restore_target_globals (mips16_globals
);
17168 else if (compression_mode
& MASK_MICROMIPS
)
17170 if (!micromips_globals
)
17171 micromips_globals
= save_target_globals_default_opts ();
17173 restore_target_globals (micromips_globals
);
17176 restore_target_globals (&default_target_globals
);
17178 old_compression_mode
= compression_mode
;
17181 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
17182 function should use the MIPS16 or microMIPS ISA and switch modes
17186 mips_set_current_function (tree fndecl
)
17188 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
17191 /* Allocate a chunk of memory for per-function machine-dependent data. */
17193 static struct machine_function
*
17194 mips_init_machine_status (void)
17196 return ggc_cleared_alloc
<machine_function
> ();
17199 /* Return the processor associated with the given ISA level, or null
17200 if the ISA isn't valid. */
17202 static const struct mips_cpu_info
*
17203 mips_cpu_info_from_isa (int isa
)
17207 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17208 if (mips_cpu_info_table
[i
].isa
== isa
)
17209 return mips_cpu_info_table
+ i
;
17214 /* Return a mips_cpu_info entry determined by an option valued
17217 static const struct mips_cpu_info
*
17218 mips_cpu_info_from_opt (int opt
)
17222 case MIPS_ARCH_OPTION_FROM_ABI
:
17223 /* 'from-abi' selects the most compatible architecture for the
17224 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
17225 ABIs. For the EABIs, we have to decide whether we're using
17226 the 32-bit or 64-bit version. */
17227 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
17228 : ABI_NEEDS_64BIT_REGS
? 3
17229 : (TARGET_64BIT
? 3 : 1));
17231 case MIPS_ARCH_OPTION_NATIVE
:
17232 gcc_unreachable ();
17235 return &mips_cpu_info_table
[opt
];
17239 /* Return a default mips_cpu_info entry, given that no -march= option
17240 was explicitly specified. */
17242 static const struct mips_cpu_info
*
17243 mips_default_arch (void)
17245 #if defined (MIPS_CPU_STRING_DEFAULT)
17247 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17248 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
17249 return mips_cpu_info_table
+ i
;
17250 gcc_unreachable ();
17251 #elif defined (MIPS_ISA_DEFAULT)
17252 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
17254 /* 'from-abi' makes a good default: you get whatever the ABI
17256 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
17260 /* Set up globals to generate code for the ISA or processor
17261 described by INFO. */
17264 mips_set_architecture (const struct mips_cpu_info
*info
)
17268 mips_arch_info
= info
;
17269 mips_arch
= info
->cpu
;
17270 mips_isa
= info
->isa
;
17274 mips_isa_rev
= (mips_isa
& 31) + 1;
17278 /* Likewise for tuning. */
17281 mips_set_tune (const struct mips_cpu_info
*info
)
17285 mips_tune_info
= info
;
17286 mips_tune
= info
->cpu
;
17290 /* Implement TARGET_OPTION_OVERRIDE. */
17293 mips_option_override (void)
17295 int i
, start
, regno
, mode
;
17297 if (global_options_set
.x_mips_isa_option
)
17298 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
17300 #ifdef SUBTARGET_OVERRIDE_OPTIONS
17301 SUBTARGET_OVERRIDE_OPTIONS
;
17304 /* MIPS16 and microMIPS cannot coexist. */
17305 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
17306 error ("unsupported combination: %s", "-mips16 -mmicromips");
17308 /* Save the base compression state and process flags as though we
17309 were generating uncompressed code. */
17310 mips_base_compression_flags
= TARGET_COMPRESSION
;
17311 target_flags
&= ~TARGET_COMPRESSION
;
17313 /* -mno-float overrides -mhard-float and -msoft-float. */
17314 if (TARGET_NO_FLOAT
)
17316 target_flags
|= MASK_SOFT_FLOAT_ABI
;
17317 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
17320 if (TARGET_FLIP_MIPS16
)
17321 TARGET_INTERLINK_COMPRESSED
= 1;
17323 /* Set the small data limit. */
17324 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
17326 : MIPS_DEFAULT_GVALUE
);
17328 /* The following code determines the architecture and register size.
17329 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17330 The GAS and GCC code should be kept in sync as much as possible. */
17332 if (global_options_set
.x_mips_arch_option
)
17333 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
17335 if (mips_isa_option_info
!= 0)
17337 if (mips_arch_info
== 0)
17338 mips_set_architecture (mips_isa_option_info
);
17339 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
17340 error ("%<-%s%> conflicts with the other architecture options, "
17341 "which specify a %s processor",
17342 mips_isa_option_info
->name
,
17343 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
17346 if (mips_arch_info
== 0)
17347 mips_set_architecture (mips_default_arch ());
17349 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
17350 error ("%<-march=%s%> is not compatible with the selected ABI",
17351 mips_arch_info
->name
);
17353 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17354 if (global_options_set
.x_mips_tune_option
)
17355 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
17357 if (mips_tune_info
== 0)
17358 mips_set_tune (mips_arch_info
);
17360 if ((target_flags_explicit
& MASK_64BIT
) != 0)
17362 /* The user specified the size of the integer registers. Make sure
17363 it agrees with the ABI and ISA. */
17364 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
17365 error ("%<-mgp64%> used with a 32-bit processor");
17366 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
17367 error ("%<-mgp32%> used with a 64-bit ABI");
17368 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
17369 error ("%<-mgp64%> used with a 32-bit ABI");
17373 /* Infer the integer register size from the ABI and processor.
17374 Restrict ourselves to 32-bit registers if that's all the
17375 processor has, or if the ABI cannot handle 64-bit registers. */
17376 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
17377 target_flags
&= ~MASK_64BIT
;
17379 target_flags
|= MASK_64BIT
;
17382 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
17384 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
17385 error ("the %qs architecture does not support %<-mfp32%>",
17386 mips_arch_info
->name
);
17387 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
17388 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17389 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17390 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17391 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17393 if (!ISA_HAS_MXHC1
)
17394 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17395 " the target supports the mfhc1 and mthc1 instructions");
17396 else if (mips_abi
!= ABI_32
)
17397 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17403 /* -msingle-float selects 32-bit float registers. On r6 and later,
17404 -mdouble-float selects 64-bit float registers, since the old paired
17405 register model is not supported. In other cases the float registers
17406 should be the same size as the integer ones. */
17407 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
17408 target_flags
|= MASK_FLOAT64
;
17409 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17410 target_flags
|= MASK_FLOAT64
;
17412 target_flags
&= ~MASK_FLOAT64
;
17415 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
17416 error ("%<-mfpxx%> can only be used with the o32 ABI");
17417 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
17418 error ("unsupported combination: %s", "-mfp64 -mfpxx");
17419 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
17420 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
17421 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
17422 error ("%<-mfpxx%> requires %<-mlra%>");
17424 /* End of code shared with GAS. */
17426 /* The R5900 FPU only supports single precision. */
17427 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17428 error ("unsupported combination: %s",
17429 "-march=r5900 -mhard-float -mdouble-float");
17431 /* If a -mlong* option was given, check that it matches the ABI,
17432 otherwise infer the -mlong* setting from the other options. */
17433 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17437 if (mips_abi
== ABI_N32
)
17438 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17439 else if (mips_abi
== ABI_32
)
17440 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17441 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17442 /* We have traditionally allowed non-abicalls code to use
17443 an LP64 form of o64. However, it would take a bit more
17444 effort to support the combination of 32-bit GOT entries
17445 and 64-bit pointers, so we treat the abicalls case as
17447 error ("the combination of %qs and %qs is incompatible with %qs",
17448 "-mabi=o64", "-mabicalls", "-mlong64");
17452 if (mips_abi
== ABI_64
)
17453 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17458 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17459 target_flags
|= MASK_LONG64
;
17461 target_flags
&= ~MASK_LONG64
;
17464 if (!TARGET_OLDABI
)
17465 flag_pcc_struct_return
= 0;
17467 /* Decide which rtx_costs structure to use. */
17469 mips_cost
= &mips_rtx_cost_optimize_size
;
17471 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17473 /* If the user hasn't specified a branch cost, use the processor's
17475 if (mips_branch_cost
== 0)
17476 mips_branch_cost
= mips_cost
->branch_cost
;
17478 /* If neither -mbranch-likely nor -mno-branch-likely was given
17479 on the command line, set MASK_BRANCHLIKELY based on the target
17480 architecture and tuning flags. Annulled delay slots are a
17481 size win, so we only consider the processor-specific tuning
17482 for !optimize_size. */
17483 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17485 if (ISA_HAS_BRANCHLIKELY
17487 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17488 target_flags
|= MASK_BRANCHLIKELY
;
17490 target_flags
&= ~MASK_BRANCHLIKELY
;
17492 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17493 warning (0, "the %qs architecture does not support branch-likely"
17494 " instructions", mips_arch_info
->name
);
17496 /* If the user hasn't specified -mimadd or -mno-imadd set
17497 MASK_IMADD based on the target architecture and tuning
17499 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17501 if (ISA_HAS_MADD_MSUB
&&
17502 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17503 target_flags
|= MASK_IMADD
;
17505 target_flags
&= ~MASK_IMADD
;
17507 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17508 warning (0, "the %qs architecture does not support madd or msub"
17509 " instructions", mips_arch_info
->name
);
17511 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
17512 line, set MASK_ODD_SPREG based on the ISA and ABI. */
17513 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
17515 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
17516 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
17517 target_flags
&= ~MASK_ODD_SPREG
;
17519 target_flags
|= MASK_ODD_SPREG
;
17521 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
17522 warning (0, "the %qs architecture does not support odd single-precision"
17523 " registers", mips_arch_info
->name
);
17525 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
17527 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
17528 /* Allow compilation to continue further even though invalid output
17529 will be produced. */
17530 target_flags
|= MASK_ODD_SPREG
;
17533 /* The effect of -mabicalls isn't defined for the EABI. */
17534 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17536 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17537 target_flags
&= ~MASK_ABICALLS
;
17540 /* PIC requires -mabicalls. */
17543 if (mips_abi
== ABI_EABI
)
17544 error ("cannot generate position-independent code for %qs",
17546 else if (!TARGET_ABICALLS
)
17547 error ("position-independent code requires %qs", "-mabicalls");
17550 if (TARGET_ABICALLS_PIC2
)
17551 /* We need to set flag_pic for executables as well as DSOs
17552 because we may reference symbols that are not defined in
17553 the final executable. (MIPS does not use things like
17554 copy relocs, for example.)
17556 There is a body of code that uses __PIC__ to distinguish
17557 between -mabicalls and -mno-abicalls code. The non-__PIC__
17558 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17559 long as any indirect jumps use $25. */
17562 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17563 faster code, but at the expense of more nops. Enable it at -O3 and
17565 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17566 target_flags
|= MASK_VR4130_ALIGN
;
17568 /* Prefer a call to memcpy over inline code when optimizing for size,
17569 though see MOVE_RATIO in mips.h. */
17570 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17571 target_flags
|= MASK_MEMCPY
;
17573 /* If we have a nonzero small-data limit, check that the -mgpopt
17574 setting is consistent with the other target flags. */
17575 if (mips_small_data_threshold
> 0)
17579 if (!TARGET_EXPLICIT_RELOCS
)
17580 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17582 TARGET_LOCAL_SDATA
= false;
17583 TARGET_EXTERN_SDATA
= false;
17587 if (TARGET_VXWORKS_RTP
)
17588 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17590 if (TARGET_ABICALLS
)
17591 warning (0, "cannot use small-data accesses for %qs",
17596 /* Set NaN and ABS defaults. */
17597 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17598 mips_nan
= MIPS_IEEE_754_2008
;
17599 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17600 mips_abs
= MIPS_IEEE_754_2008
;
17602 /* Check for IEEE 754 legacy/2008 support. */
17603 if ((mips_nan
== MIPS_IEEE_754_LEGACY
17604 || mips_abs
== MIPS_IEEE_754_LEGACY
)
17605 && !ISA_HAS_IEEE_754_LEGACY
)
17606 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
17607 mips_arch_info
->name
,
17608 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
17610 if ((mips_nan
== MIPS_IEEE_754_2008
17611 || mips_abs
== MIPS_IEEE_754_2008
)
17612 && !ISA_HAS_IEEE_754_2008
)
17613 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
17614 mips_arch_info
->name
,
17615 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
17617 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17618 for all its floating point. */
17619 if (mips_nan
!= MIPS_IEEE_754_2008
)
17621 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17622 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17623 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17626 /* Make sure that the user didn't turn off paired single support when
17627 MIPS-3D support is requested. */
17629 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17630 && !TARGET_PAIRED_SINGLE_FLOAT
)
17631 error ("%<-mips3d%> requires %<-mpaired-single%>");
17633 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17635 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17637 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17638 and TARGET_HARD_FLOAT_ABI are both true. */
17639 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17641 error ("%qs must be used with %qs",
17642 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17643 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17644 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17648 /* Make sure that -mpaired-single is only used on ISAs that support it.
17649 We must disable it otherwise since it relies on other ISA properties
17650 like ISA_HAS_8CC having their normal values. */
17651 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17653 error ("the %qs architecture does not support paired-single"
17654 " instructions", mips_arch_info
->name
);
17655 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17659 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17660 && !TARGET_CACHE_BUILTIN
)
17662 error ("%qs requires a target that provides the %qs instruction",
17663 "-mr10k-cache-barrier", "cache");
17664 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17667 /* If TARGET_DSPR2, enable TARGET_DSP. */
17671 if (TARGET_DSP
&& mips_isa_rev
>= 6)
17673 error ("the %qs architecture does not support DSP instructions",
17674 mips_arch_info
->name
);
17675 TARGET_DSP
= false;
17676 TARGET_DSPR2
= false;
17679 /* .eh_frame addresses should be the same width as a C pointer.
17680 Most MIPS ABIs support only one pointer size, so the assembler
17681 will usually know exactly how big an .eh_frame address is.
17683 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17684 originally defined to use 64-bit pointers (i.e. it is LP64), and
17685 this is still the default mode. However, we also support an n32-like
17686 ILP32 mode, which is selected by -mlong32. The problem is that the
17687 assembler has traditionally not had an -mlong option, so it has
17688 traditionally not known whether we're using the ILP32 or LP64 form.
17690 As it happens, gas versions up to and including 2.19 use _32-bit_
17691 addresses for EABI64 .cfi_* directives. This is wrong for the
17692 default LP64 mode, so we can't use the directives by default.
17693 Moreover, since gas's current behavior is at odds with gcc's
17694 default behavior, it seems unwise to rely on future versions
17695 of gas behaving the same way. We therefore avoid using .cfi
17696 directives for -mlong32 as well. */
17697 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17698 flag_dwarf2_cfi_asm
= 0;
17700 /* .cfi_* directives generate a read-only section, so fall back on
17701 manual .eh_frame creation if we need the section to be writable. */
17702 if (TARGET_WRITABLE_EH_FRAME
)
17703 flag_dwarf2_cfi_asm
= 0;
17705 mips_init_print_operand_punct ();
17707 /* Set up array to map GCC register number to debug register number.
17708 Ignore the special purpose register numbers. */
17710 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17712 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17713 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17714 mips_dwarf_regno
[i
] = i
;
17716 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17719 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17720 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17721 mips_dbx_regno
[i
] = i
+ start
;
17723 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17724 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17725 mips_dbx_regno
[i
] = i
+ start
;
17727 /* Accumulator debug registers use big-endian ordering. */
17728 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17729 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17730 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17731 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17732 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17734 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17735 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17738 /* Set up mips_hard_regno_mode_ok. */
17739 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17740 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17741 mips_hard_regno_mode_ok
[mode
][regno
]
17742 = mips_hard_regno_mode_ok_p (regno
, (machine_mode
) mode
);
17744 /* Function to allocate machine-dependent function status. */
17745 init_machine_status
= &mips_init_machine_status
;
17747 /* Default to working around R4000 errata only if the processor
17748 was selected explicitly. */
17749 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17750 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17751 target_flags
|= MASK_FIX_R4000
;
17753 /* Default to working around R4400 errata only if the processor
17754 was selected explicitly. */
17755 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17756 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17757 target_flags
|= MASK_FIX_R4400
;
17759 /* Default to working around R10000 errata only if the processor
17760 was selected explicitly. */
17761 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17762 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17763 target_flags
|= MASK_FIX_R10000
;
17765 /* Make sure that branch-likely instructions available when using
17766 -mfix-r10000. The instructions are not available if either:
17768 1. -mno-branch-likely was passed.
17769 2. The selected ISA does not support branch-likely and
17770 the command line does not include -mbranch-likely. */
17771 if (TARGET_FIX_R10000
17772 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17773 ? !ISA_HAS_BRANCHLIKELY
17774 : !TARGET_BRANCHLIKELY
))
17775 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17777 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17779 warning (0, "the %qs architecture does not support the synci "
17780 "instruction", mips_arch_info
->name
);
17781 target_flags
&= ~MASK_SYNCI
;
17784 /* Only optimize PIC indirect calls if they are actually required. */
17785 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17786 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17788 /* Save base state of options. */
17789 mips_base_target_flags
= target_flags
;
17790 mips_base_schedule_insns
= flag_schedule_insns
;
17791 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17792 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17793 mips_base_align_loops
= align_loops
;
17794 mips_base_align_jumps
= align_jumps
;
17795 mips_base_align_functions
= align_functions
;
17797 /* Now select the ISA mode.
17799 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17800 later if required. */
17801 mips_set_compression_mode (0);
17803 /* We register a second machine specific reorg pass after delay slot
17804 filling. Registering the pass must be done at start up. It's
17805 convenient to do it here. */
17806 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17807 struct register_pass_info insert_pass_mips_machine_reorg2
=
17809 new_pass
, /* pass */
17810 "dbr", /* reference_pass_name */
17811 1, /* ref_pass_instance_number */
17812 PASS_POS_INSERT_AFTER
/* po_op */
17814 register_pass (&insert_pass_mips_machine_reorg2
);
17816 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17817 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17820 /* Swap the register information for registers I and I + 1, which
17821 currently have the wrong endianness. Note that the registers'
17822 fixedness and call-clobberedness might have been set on the
17826 mips_swap_registers (unsigned int i
)
17831 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17832 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17834 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17835 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17836 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17837 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17843 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17846 mips_conditional_register_usage (void)
17851 /* These DSP control register fields are global. */
17852 global_regs
[CCDSP_PO_REGNUM
] = 1;
17853 global_regs
[CCDSP_SC_REGNUM
] = 1;
17856 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17857 reg_class_contents
[(int) DSP_ACC_REGS
]);
17860 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17861 reg_class_contents
[(int) MD_REGS
]);
17863 if (!TARGET_HARD_FLOAT
)
17865 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17866 reg_class_contents
[(int) FP_REGS
]);
17867 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17868 reg_class_contents
[(int) ST_REGS
]);
17870 else if (!ISA_HAS_8CC
)
17872 /* We only have a single condition-code register. We implement
17873 this by fixing all the condition-code registers and generating
17874 RTL that refers directly to ST_REG_FIRST. */
17875 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17876 reg_class_contents
[(int) ST_REGS
]);
17878 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17879 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17883 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17884 are call-saved, and saving them via a MIPS16 register would
17885 probably waste more time than just reloading the value.
17887 We permit the $t temporary registers when optimizing for speed
17888 but not when optimizing for space because using them results in
17889 code that is larger (but faster) then not using them. We do
17890 allow $24 (t8) because it is used in CMP and CMPI instructions
17891 and $25 (t9) because it is used as the function call address in
17894 fixed_regs
[18] = call_used_regs
[18] = 1;
17895 fixed_regs
[19] = call_used_regs
[19] = 1;
17896 fixed_regs
[20] = call_used_regs
[20] = 1;
17897 fixed_regs
[21] = call_used_regs
[21] = 1;
17898 fixed_regs
[22] = call_used_regs
[22] = 1;
17899 fixed_regs
[23] = call_used_regs
[23] = 1;
17900 fixed_regs
[26] = call_used_regs
[26] = 1;
17901 fixed_regs
[27] = call_used_regs
[27] = 1;
17902 fixed_regs
[30] = call_used_regs
[30] = 1;
17905 fixed_regs
[8] = call_used_regs
[8] = 1;
17906 fixed_regs
[9] = call_used_regs
[9] = 1;
17907 fixed_regs
[10] = call_used_regs
[10] = 1;
17908 fixed_regs
[11] = call_used_regs
[11] = 1;
17909 fixed_regs
[12] = call_used_regs
[12] = 1;
17910 fixed_regs
[13] = call_used_regs
[13] = 1;
17911 fixed_regs
[14] = call_used_regs
[14] = 1;
17912 fixed_regs
[15] = call_used_regs
[15] = 1;
17915 /* Do not allow HI and LO to be treated as register operands.
17916 There are no MTHI or MTLO instructions (or any real need
17917 for them) and one-way registers cannot easily be reloaded. */
17918 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17919 reg_class_contents
[(int) MD_REGS
]);
17921 /* $f20-$f23 are call-clobbered for n64. */
17922 if (mips_abi
== ABI_64
)
17925 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17926 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17928 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17929 for n32 and o32 FP64. */
17930 if (mips_abi
== ABI_N32
17931 || (mips_abi
== ABI_32
17932 && TARGET_FLOAT64
))
17935 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17936 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17938 /* Make sure that double-register accumulator values are correctly
17939 ordered for the current endianness. */
17940 if (TARGET_LITTLE_ENDIAN
)
17942 unsigned int regno
;
17944 mips_swap_registers (MD_REG_FIRST
);
17945 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17946 mips_swap_registers (regno
);
17950 /* Implement EH_USES. */
17953 mips_eh_uses (unsigned int regno
)
17955 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17957 /* We need to force certain registers to be live in order to handle
17958 PIC long branches correctly. See mips_must_initialize_gp_p for
17960 if (mips_cfun_has_cprestore_slot_p ())
17962 if (regno
== CPRESTORE_SLOT_REGNUM
)
17967 if (cfun
->machine
->global_pointer
== regno
)
17975 /* Implement EPILOGUE_USES. */
17978 mips_epilogue_uses (unsigned int regno
)
17980 /* Say that the epilogue uses the return address register. Note that
17981 in the case of sibcalls, the values "used by the epilogue" are
17982 considered live at the start of the called function. */
17983 if (regno
== RETURN_ADDR_REGNUM
)
17986 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17987 See the comment above load_call<mode> for details. */
17988 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17991 /* An interrupt handler must preserve some registers that are
17992 ordinarily call-clobbered. */
17993 if (cfun
->machine
->interrupt_handler_p
17994 && mips_interrupt_extra_call_saved_reg_p (regno
))
18000 /* Return true if INSN needs to be wrapped in ".set noat".
18001 INSN has NOPERANDS operands, stored in OPVEC. */
18004 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
18006 if (recog_memoized (insn
) >= 0)
18008 subrtx_iterator::array_type array
;
18009 for (int i
= 0; i
< noperands
; i
++)
18010 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
18011 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
18017 /* Implement FINAL_PRESCAN_INSN. */
18020 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
18022 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
18023 mips_push_asm_switch (&mips_noat
);
18026 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
18029 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
18030 rtx
*opvec
, int noperands
)
18032 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
18033 mips_pop_asm_switch (&mips_noat
);
18036 /* Return the function that is used to expand the <u>mulsidi3 pattern.
18037 EXT_CODE is the code of the extension used. Return NULL if widening
18038 multiplication shouldn't be used. */
18041 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
18045 signed_p
= ext_code
== SIGN_EXTEND
;
18048 /* Don't use widening multiplication with MULT when we have DMUL. Even
18049 with the extension of its input operands DMUL is faster. Note that
18050 the extension is not needed for signed multiplication. In order to
18051 ensure that we always remove the redundant sign-extension in this
18052 case we still expand mulsidi3 for DMUL. */
18053 if (ISA_HAS_R6DMUL
)
18054 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
18056 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
18059 ? gen_mulsidi3_64bit_mips16
18060 : gen_umulsidi3_64bit_mips16
);
18061 if (TARGET_FIX_R4000
)
18063 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
18068 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
18071 ? gen_mulsidi3_32bit_mips16
18072 : gen_umulsidi3_32bit_mips16
);
18073 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
18074 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
18075 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
18079 /* Return true if PATTERN matches the kind of instruction generated by
18080 umips_build_save_restore. SAVE_P is true for store. */
18083 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
18087 HOST_WIDE_INT first_offset
= 0;
18088 rtx first_base
= 0;
18089 unsigned int regmask
= 0;
18091 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
18093 rtx set
, reg
, mem
, this_base
;
18094 HOST_WIDE_INT this_offset
;
18096 /* Check that we have a SET. */
18097 set
= XVECEXP (pattern
, 0, n
);
18098 if (GET_CODE (set
) != SET
)
18101 /* Check that the SET is a load (if restoring) or a store
18103 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18104 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
18107 /* Check that the address is the sum of base and a possibly-zero
18108 constant offset. Determine if the offset is in range. */
18109 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
18110 if (!REG_P (this_base
))
18115 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
18117 first_base
= this_base
;
18118 first_offset
= this_offset
;
18122 /* Check that the save slots are consecutive. */
18123 if (REGNO (this_base
) != REGNO (first_base
)
18124 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
18128 /* Check that SET's other operand is a register. */
18129 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
18133 regmask
|= 1 << REGNO (reg
);
18136 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
18137 if (regmask
== umips_swm_mask
[i
])
18143 /* Return the assembly instruction for microMIPS LWM or SWM.
18144 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
18147 umips_output_save_restore (bool save_p
, rtx pattern
)
18149 static char buffer
[300];
18152 HOST_WIDE_INT offset
;
18153 rtx base
, mem
, set
, last_set
, last_reg
;
18155 /* Parse the pattern. */
18156 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
18158 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
18160 n
= XVECLEN (pattern
, 0);
18162 set
= XVECEXP (pattern
, 0, 0);
18163 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18164 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
18166 last_set
= XVECEXP (pattern
, 0, n
- 1);
18167 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
18169 if (REGNO (last_reg
) == 31)
18172 gcc_assert (n
<= 9);
18176 s
+= sprintf (s
, "%s,", reg_names
[16]);
18178 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
18180 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
18183 if (REGNO (last_reg
) == 31)
18184 s
+= sprintf (s
, "%s,", reg_names
[31]);
18186 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
18190 /* Return true if MEM1 and MEM2 use the same base register, and the
18191 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
18192 register into (from) which the contents of MEM1 will be loaded
18193 (stored), depending on the value of LOAD_P.
18194 SWAP_P is true when the 1st and 2nd instructions are swapped. */
18197 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
18198 rtx first_reg
, rtx mem1
, rtx mem2
)
18201 HOST_WIDE_INT offset1
, offset2
;
18203 if (!MEM_P (mem1
) || !MEM_P (mem2
))
18206 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18207 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18209 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18212 /* Avoid invalid load pair instructions. */
18213 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
18216 /* We must avoid this case for anti-dependence.
18219 first_reg is $2, but the base is $3. */
18222 && REGNO (first_reg
) + 1 == REGNO (base1
))
18225 if (offset2
!= offset1
+ 4)
18228 if (!UMIPS_12BIT_OFFSET_P (offset1
))
18235 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
18237 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
18238 enum reg_class rc1
, rc2
;
18239 HOST_WIDE_INT offset1
, offset2
;
18243 reg1
= operands
[0];
18244 reg2
= operands
[2];
18245 mem1
= operands
[1];
18246 mem2
= operands
[3];
18250 reg1
= operands
[1];
18251 reg2
= operands
[3];
18252 mem1
= operands
[0];
18253 mem2
= operands
[2];
18256 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
18257 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
18260 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18261 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18263 /* Base regs do not match. */
18264 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18267 /* Either of the loads is clobbering base register. It is legitimate to bond
18268 loads if second load clobbers base register. However, hardware does not
18269 support such bonding. */
18271 && (REGNO (reg1
) == REGNO (base1
)
18272 || (REGNO (reg2
) == REGNO (base1
))))
18275 /* Loading in same registers. */
18277 && REGNO (reg1
) == REGNO (reg2
))
18280 /* The loads/stores are not of same type. */
18281 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
18282 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
18284 && !reg_class_subset_p (rc1
, rc2
)
18285 && !reg_class_subset_p (rc2
, rc1
))
18288 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
18294 /* OPERANDS describes the operands to a pair of SETs, in the order
18295 dest1, src1, dest2, src2. Return true if the operands can be used
18296 in an LWP or SWP instruction; LOAD_P says which. */
18299 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
18301 rtx reg1
, reg2
, mem1
, mem2
;
18305 reg1
= operands
[0];
18306 reg2
= operands
[2];
18307 mem1
= operands
[1];
18308 mem2
= operands
[3];
18312 reg1
= operands
[1];
18313 reg2
= operands
[3];
18314 mem1
= operands
[0];
18315 mem2
= operands
[2];
18318 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18319 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
18321 if (REGNO (reg1
) == REGNO (reg2
) + 1)
18322 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
18327 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18328 the first register is REG and the first memory slot is MEM.
18329 LOAD_P is true for LWP. */
18332 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
18334 rtx ops
[] = {reg
, mem
};
18337 output_asm_insn ("lwp\t%0,%1", ops
);
18339 output_asm_insn ("swp\t%0,%1", ops
);
18342 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
18343 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
18346 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
18348 rtx reg1
, reg2
, mem1
, mem2
;
18351 reg1
= operands
[0];
18352 reg2
= operands
[2];
18353 mem1
= operands
[1];
18354 mem2
= operands
[3];
18358 reg1
= operands
[1];
18359 reg2
= operands
[3];
18360 mem1
= operands
[0];
18361 mem2
= operands
[2];
18364 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18366 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
18370 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
18371 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
18374 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
18377 umips_movep_target_p (rtx reg1
, rtx reg2
)
18379 int regno1
, regno2
, pair
;
18381 static const int match
[8] = {
18382 0x00000060, /* 5, 6 */
18383 0x000000a0, /* 5, 7 */
18384 0x000000c0, /* 6, 7 */
18385 0x00200010, /* 4, 21 */
18386 0x00400010, /* 4, 22 */
18387 0x00000030, /* 4, 5 */
18388 0x00000050, /* 4, 6 */
18389 0x00000090 /* 4, 7 */
18392 if (!REG_P (reg1
) || !REG_P (reg2
))
18395 regno1
= REGNO (reg1
);
18396 regno2
= REGNO (reg2
);
18398 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
18401 pair
= (1 << regno1
) | (1 << regno2
);
18403 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
18404 if (pair
== match
[i
])
18410 /* Return the size in bytes of the trampoline code, padded to
18411 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
18412 function address immediately follow. */
18415 mips_trampoline_code_size (void)
18417 if (TARGET_USE_PIC_FN_ADDR_REG
)
18419 else if (ptr_mode
== DImode
)
18421 else if (ISA_HAS_LOAD_DELAY
)
18427 /* Implement TARGET_TRAMPOLINE_INIT. */
18430 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
18432 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
18435 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
18437 /* Work out the offsets of the pointers from the start of the
18438 trampoline code. */
18439 end_addr_offset
= mips_trampoline_code_size ();
18440 static_chain_offset
= end_addr_offset
;
18441 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
18443 /* Get pointers to the beginning and end of the code block. */
18444 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
18445 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
18447 #define OP(X) gen_int_mode (X, SImode)
18449 /* Build up the code in TRAMPOLINE. */
18451 if (TARGET_USE_PIC_FN_ADDR_REG
)
18453 /* $25 contains the address of the trampoline. Emit code of the form:
18455 l[wd] $1, target_function_offset($25)
18456 l[wd] $static_chain, static_chain_offset($25)
18459 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
18460 target_function_offset
,
18461 PIC_FUNCTION_ADDR_REGNUM
));
18462 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18463 static_chain_offset
,
18464 PIC_FUNCTION_ADDR_REGNUM
));
18465 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
18466 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
18468 else if (ptr_mode
== DImode
)
18470 /* It's too cumbersome to create the full 64-bit address, so let's
18476 1: l[wd] $25, target_function_offset - 12($31)
18477 l[wd] $static_chain, static_chain_offset - 12($31)
18481 where 12 is the offset of "1:" from the start of the code block. */
18482 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
18483 trampoline
[i
++] = OP (MIPS_BAL (1));
18484 trampoline
[i
++] = OP (MIPS_NOP
);
18485 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18486 target_function_offset
- 12,
18487 RETURN_ADDR_REGNUM
));
18488 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18489 static_chain_offset
- 12,
18490 RETURN_ADDR_REGNUM
));
18491 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18492 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
18496 /* If the target has load delays, emit:
18498 lui $1, %hi(end_addr)
18499 lw $25, %lo(end_addr + ...)($1)
18500 lw $static_chain, %lo(end_addr + ...)($1)
18506 lui $1, %hi(end_addr)
18507 lw $25, %lo(end_addr + ...)($1)
18509 lw $static_chain, %lo(end_addr + ...)($1). */
18511 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18512 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18513 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
18514 NULL
, false, OPTAB_WIDEN
);
18515 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
18516 NULL
, false, OPTAB_WIDEN
);
18517 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
18519 /* Emit the LUI. */
18520 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
18521 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
18522 NULL
, false, OPTAB_WIDEN
);
18524 /* Emit the load of the target function. */
18525 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18526 target_function_offset
- end_addr_offset
,
18528 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18529 NULL
, false, OPTAB_WIDEN
);
18531 /* Emit the JR here, if we can. */
18532 if (!ISA_HAS_LOAD_DELAY
)
18533 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18535 /* Emit the load of the static chain register. */
18536 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18537 static_chain_offset
- end_addr_offset
,
18539 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18540 NULL
, false, OPTAB_WIDEN
);
18542 /* Emit the JR, if we couldn't above. */
18543 if (ISA_HAS_LOAD_DELAY
)
18545 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18546 trampoline
[i
++] = OP (MIPS_NOP
);
18552 /* Copy the trampoline code. Leave any padding uninitialized. */
18553 for (j
= 0; j
< i
; j
++)
18555 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18556 mips_emit_move (mem
, trampoline
[j
]);
18559 /* Set up the static chain pointer field. */
18560 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18561 mips_emit_move (mem
, chain_value
);
18563 /* Set up the target function field. */
18564 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18565 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18567 /* Flush the code part of the trampoline. */
18568 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18569 emit_insn (gen_clear_cache (addr
, end_addr
));
18572 /* Implement FUNCTION_PROFILER. */
18574 void mips_function_profiler (FILE *file
)
18577 sorry ("mips16 function profiling");
18578 if (TARGET_LONG_CALLS
)
18580 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18581 if (Pmode
== DImode
)
18582 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18584 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18586 mips_push_asm_switch (&mips_noat
);
18587 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18588 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18589 /* _mcount treats $2 as the static chain register. */
18590 if (cfun
->static_chain_decl
!= NULL
)
18591 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18592 reg_names
[STATIC_CHAIN_REGNUM
]);
18593 if (TARGET_MCOUNT_RA_ADDRESS
)
18595 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18596 ra save location. */
18597 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18598 /* ra not saved, pass zero. */
18599 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18601 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18602 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18603 cfun
->machine
->frame
.ra_fp_offset
,
18604 reg_names
[STACK_POINTER_REGNUM
]);
18606 if (!TARGET_NEWABI
)
18608 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18609 TARGET_64BIT
? "dsubu" : "subu",
18610 reg_names
[STACK_POINTER_REGNUM
],
18611 reg_names
[STACK_POINTER_REGNUM
],
18612 Pmode
== DImode
? 16 : 8);
18614 if (TARGET_LONG_CALLS
)
18615 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18617 fprintf (file
, "\tjal\t_mcount\n");
18618 mips_pop_asm_switch (&mips_noat
);
18619 /* _mcount treats $2 as the static chain register. */
18620 if (cfun
->static_chain_decl
!= NULL
)
18621 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18625 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18626 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18627 when TARGET_LOONGSON_VECTORS is true. */
18629 static unsigned HOST_WIDE_INT
18630 mips_shift_truncation_mask (machine_mode mode
)
18632 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18635 return GET_MODE_BITSIZE (mode
) - 1;
18638 /* Implement TARGET_PREPARE_PCH_SAVE. */
18641 mips_prepare_pch_save (void)
18643 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18644 setting should be irrelevant. The question then is: which setting
18645 makes most sense at load time?
18647 The PCH is loaded before the first token is read. We should never
18648 have switched into MIPS16 mode by that point, and thus should not
18649 have populated mips16_globals. Nor can we load the entire contents
18650 of mips16_globals from the PCH file, because mips16_globals contains
18651 a combination of GGC and non-GGC data.
18653 There is therefore no point in trying save the GGC part of
18654 mips16_globals to the PCH file, or to preserve MIPS16ness across
18655 the PCH save and load. The loading compiler would not have access
18656 to the non-GGC parts of mips16_globals (either from the PCH file,
18657 or from a copy that the loading compiler generated itself) and would
18658 have to call target_reinit anyway.
18660 It therefore seems best to switch back to non-MIPS16 mode at
18661 save time, and to ensure that mips16_globals remains null after
18663 mips_set_compression_mode (0);
18664 mips16_globals
= 0;
18667 /* Generate or test for an insn that supports a constant permutation. */
18669 #define MAX_VECT_LEN 8
18671 struct expand_vec_perm_d
18673 rtx target
, op0
, op1
;
18674 unsigned char perm
[MAX_VECT_LEN
];
18675 machine_mode vmode
;
18676 unsigned char nelt
;
18681 /* Construct (set target (vec_select op0 (parallel perm))) and
18682 return true if that's a valid instruction in the active ISA. */
18685 mips_expand_vselect (rtx target
, rtx op0
,
18686 const unsigned char *perm
, unsigned nelt
)
18688 rtx rperm
[MAX_VECT_LEN
], x
;
18692 for (i
= 0; i
< nelt
; ++i
)
18693 rperm
[i
] = GEN_INT (perm
[i
]);
18695 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18696 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18697 x
= gen_rtx_SET (target
, x
);
18699 insn
= emit_insn (x
);
18700 if (recog_memoized (insn
) < 0)
18702 remove_insn (insn
);
18708 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18711 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18712 const unsigned char *perm
, unsigned nelt
)
18714 machine_mode v2mode
;
18717 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18718 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18719 return mips_expand_vselect (target
, x
, perm
, nelt
);
18722 /* Recognize patterns for even-odd extraction. */
18725 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18727 unsigned i
, odd
, nelt
= d
->nelt
;
18728 rtx t0
, t1
, t2
, t3
;
18730 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18732 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18739 for (i
= 1; i
< nelt
; ++i
)
18740 if (d
->perm
[i
] != i
* 2 + odd
)
18746 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18747 t0
= gen_reg_rtx (d
->vmode
);
18748 t1
= gen_reg_rtx (d
->vmode
);
18752 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18753 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18755 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18757 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18761 t2
= gen_reg_rtx (d
->vmode
);
18762 t3
= gen_reg_rtx (d
->vmode
);
18763 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18764 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18765 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18766 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18768 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18770 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18774 gcc_unreachable ();
18779 /* Recognize patterns for the Loongson PSHUFH instruction. */
18782 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18787 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18789 if (d
->vmode
!= V4HImode
)
18794 /* Convert the selector into the packed 8-bit form for pshufh. */
18795 /* Recall that loongson is little-endian only. No big-endian
18796 adjustment required. */
18797 for (i
= mask
= 0; i
< 4; i
++)
18798 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18799 rmask
= force_reg (SImode
, GEN_INT (mask
));
18801 if (d
->one_vector_p
)
18802 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18805 rtx t0
, t1
, x
, merge
, rmerge
[4];
18807 t0
= gen_reg_rtx (V4HImode
);
18808 t1
= gen_reg_rtx (V4HImode
);
18809 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18810 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18812 for (i
= 0; i
< 4; ++i
)
18813 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18814 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18815 merge
= force_reg (V4HImode
, merge
);
18817 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18818 emit_insn (gen_rtx_SET (t1
, x
));
18820 x
= gen_rtx_NOT (V4HImode
, merge
);
18821 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18822 emit_insn (gen_rtx_SET (t0
, x
));
18824 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18825 emit_insn (gen_rtx_SET (d
->target
, x
));
18831 /* Recognize broadcast patterns for the Loongson. */
18834 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18839 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18841 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18842 if (d
->vmode
!= V8QImode
)
18844 if (!d
->one_vector_p
)
18848 for (i
= 1; i
< 8; ++i
)
18849 if (d
->perm
[i
] != elt
)
18855 /* With one interleave we put two of the desired element adjacent. */
18856 t0
= gen_reg_rtx (V8QImode
);
18858 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18860 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18862 /* Shuffle that one HImode element into all locations. */
18865 t1
= gen_reg_rtx (V4HImode
);
18866 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18867 force_reg (SImode
, GEN_INT (elt
))));
18869 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18874 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18876 unsigned int i
, nelt
= d
->nelt
;
18877 unsigned char perm2
[MAX_VECT_LEN
];
18879 if (d
->one_vector_p
)
18881 /* Try interleave with alternating operands. */
18882 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18883 for (i
= 1; i
< nelt
; i
+= 2)
18885 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18890 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18894 /* Try again with swapped operands. */
18895 for (i
= 0; i
< nelt
; ++i
)
18896 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18897 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18901 if (mips_expand_vpc_loongson_even_odd (d
))
18903 if (mips_expand_vpc_loongson_pshufh (d
))
18905 if (mips_expand_vpc_loongson_bcast (d
))
18910 /* Expand a vec_perm_const pattern. */
18913 mips_expand_vec_perm_const (rtx operands
[4])
18915 struct expand_vec_perm_d d
;
18916 int i
, nelt
, which
;
18917 unsigned char orig_perm
[MAX_VECT_LEN
];
18921 d
.target
= operands
[0];
18922 d
.op0
= operands
[1];
18923 d
.op1
= operands
[2];
18926 d
.vmode
= GET_MODE (d
.target
);
18927 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18928 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18929 d
.testing_p
= false;
18931 for (i
= which
= 0; i
< nelt
; ++i
)
18933 rtx e
= XVECEXP (sel
, 0, i
);
18934 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18935 which
|= (ei
< nelt
? 1 : 2);
18938 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18946 d
.one_vector_p
= false;
18947 if (!rtx_equal_p (d
.op0
, d
.op1
))
18952 for (i
= 0; i
< nelt
; ++i
)
18953 d
.perm
[i
] &= nelt
- 1;
18955 d
.one_vector_p
= true;
18960 d
.one_vector_p
= true;
18964 ok
= mips_expand_vec_perm_const_1 (&d
);
18966 /* If we were given a two-vector permutation which just happened to
18967 have both input vectors equal, we folded this into a one-vector
18968 permutation. There are several loongson patterns that are matched
18969 via direct vec_select+vec_concat expansion, but we do not have
18970 support in mips_expand_vec_perm_const_1 to guess the adjustment
18971 that should be made for a single operand. Just try again with
18972 the original permutation. */
18973 if (!ok
&& which
== 3)
18975 d
.op0
= operands
[1];
18976 d
.op1
= operands
[2];
18977 d
.one_vector_p
= false;
18978 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18979 ok
= mips_expand_vec_perm_const_1 (&d
);
18985 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18988 mips_vectorize_vec_perm_const_ok (machine_mode vmode
,
18989 const unsigned char *sel
)
18991 struct expand_vec_perm_d d
;
18992 unsigned int i
, nelt
, which
;
18996 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18997 d
.testing_p
= true;
18998 memcpy (d
.perm
, sel
, nelt
);
19000 /* Categorize the set of elements in the selector. */
19001 for (i
= which
= 0; i
< nelt
; ++i
)
19003 unsigned char e
= d
.perm
[i
];
19004 gcc_assert (e
< 2 * nelt
);
19005 which
|= (e
< nelt
? 1 : 2);
19008 /* For all elements from second vector, fold the elements to first. */
19010 for (i
= 0; i
< nelt
; ++i
)
19013 /* Check whether the mask can be applied to the vector type. */
19014 d
.one_vector_p
= (which
!= 3);
19016 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
19017 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
19018 if (!d
.one_vector_p
)
19019 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
19022 ret
= mips_expand_vec_perm_const_1 (&d
);
19028 /* Expand an integral vector unpack operation. */
19031 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
19033 machine_mode imode
= GET_MODE (operands
[1]);
19034 rtx (*unpack
) (rtx
, rtx
, rtx
);
19035 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
19036 rtx tmp
, dest
, zero
;
19042 unpack
= gen_loongson_punpckhbh
;
19044 unpack
= gen_loongson_punpcklbh
;
19045 cmpgt
= gen_loongson_pcmpgtb
;
19049 unpack
= gen_loongson_punpckhhw
;
19051 unpack
= gen_loongson_punpcklhw
;
19052 cmpgt
= gen_loongson_pcmpgth
;
19055 gcc_unreachable ();
19058 zero
= force_reg (imode
, CONST0_RTX (imode
));
19063 tmp
= gen_reg_rtx (imode
);
19064 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
19067 dest
= gen_reg_rtx (imode
);
19068 emit_insn (unpack (dest
, operands
[1], tmp
));
19070 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
19073 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
19076 mips_constant_elt_p (rtx x
)
19078 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
19081 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
19084 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
19086 struct expand_vec_perm_d d
;
19090 if (elt
!= const0_rtx
)
19091 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
19093 elt
= gen_lowpart (DImode
, elt
);
19095 t1
= gen_reg_rtx (vmode
);
19099 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
19102 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
19105 gcc_unreachable ();
19108 memset (&d
, 0, sizeof (d
));
19113 d
.nelt
= GET_MODE_NUNITS (vmode
);
19114 d
.one_vector_p
= true;
19116 ok
= mips_expand_vec_perm_const_1 (&d
);
19120 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
19121 elements of VALS with zeros, copy the constant vector to TARGET. */
19124 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
19125 rtx target
, rtx vals
)
19127 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
19130 for (i
= 0; i
< nelt
; ++i
)
19132 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
19133 RTVEC_ELT (vec
, i
) = const0_rtx
;
19136 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
19140 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
19143 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
19145 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
19147 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
19148 GEN_INT (one_var
)));
19151 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
19154 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
19155 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
19157 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
19158 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
19161 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
19163 for (i
= 0; i
< nelt
; ++i
)
19165 rtx x
= XVECEXP (vals
, 0, i
);
19166 if (!mips_constant_elt_p (x
))
19167 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
19170 emit_move_insn (target
, mem
);
19173 /* Expand a vector initialization. */
19176 mips_expand_vector_init (rtx target
, rtx vals
)
19178 machine_mode vmode
= GET_MODE (target
);
19179 machine_mode imode
= GET_MODE_INNER (vmode
);
19180 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
19181 unsigned nvar
= 0, one_var
= -1u;
19182 bool all_same
= true;
19185 for (i
= 0; i
< nelt
; ++i
)
19187 x
= XVECEXP (vals
, 0, i
);
19188 if (!mips_constant_elt_p (x
))
19189 nvar
++, one_var
= i
;
19190 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
19194 /* Load constants from the pool, or whatever's handy. */
19197 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
19201 /* For two-part initialization, always use CONCAT. */
19204 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
19205 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
19206 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
19207 emit_insn (gen_rtx_SET (target
, x
));
19211 /* Loongson is the only cpu with vectors with more elements. */
19212 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
19214 /* If all values are identical, broadcast the value. */
19217 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
19221 /* If we've only got one non-variable V4HImode, use PINSRH. */
19222 if (nvar
== 1 && vmode
== V4HImode
)
19224 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
19228 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
19231 /* Expand a vector reduction. */
19234 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
19236 machine_mode vmode
= GET_MODE (in
);
19237 unsigned char perm2
[2];
19238 rtx last
, next
, fold
, x
;
19242 fold
= gen_reg_rtx (vmode
);
19246 /* Use PUL/PLU to produce { L, H } op { H, L }.
19247 By reversing the pair order, rather than a pure interleave high,
19248 we avoid erroneous exceptional conditions that we might otherwise
19249 produce from the computation of H op H. */
19252 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
19257 /* Use interleave to produce { H, L } op { H, H }. */
19258 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
19262 /* Perform the first reduction with interleave,
19263 and subsequent reductions with shifts. */
19264 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
19266 next
= gen_reg_rtx (vmode
);
19267 emit_insn (gen (next
, last
, fold
));
19270 fold
= gen_reg_rtx (vmode
);
19271 x
= force_reg (SImode
, GEN_INT (16));
19272 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
19276 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
19278 next
= gen_reg_rtx (vmode
);
19279 emit_insn (gen (next
, last
, fold
));
19282 fold
= gen_reg_rtx (vmode
);
19283 x
= force_reg (SImode
, GEN_INT (16));
19284 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19286 next
= gen_reg_rtx (vmode
);
19287 emit_insn (gen (next
, last
, fold
));
19290 fold
= gen_reg_rtx (vmode
);
19291 x
= force_reg (SImode
, GEN_INT (8));
19292 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19296 gcc_unreachable ();
19299 emit_insn (gen (target
, last
, fold
));
19302 /* Expand a vector minimum/maximum. */
19305 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
19306 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
19308 machine_mode vmode
= GET_MODE (target
);
19311 tc
= gen_reg_rtx (vmode
);
19312 t0
= gen_reg_rtx (vmode
);
19313 t1
= gen_reg_rtx (vmode
);
19316 emit_insn (cmp (tc
, op0
, op1
));
19318 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
19319 emit_insn (gen_rtx_SET (t0
, x
));
19321 x
= gen_rtx_NOT (vmode
, tc
);
19322 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
19323 emit_insn (gen_rtx_SET (t1
, x
));
19325 x
= gen_rtx_IOR (vmode
, t0
, t1
);
19326 emit_insn (gen_rtx_SET (target
, x
));
19329 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
19332 mips_hard_regno_caller_save_mode (unsigned int regno
,
19333 unsigned int nregs
,
19336 /* For performance, avoid saving/restoring upper parts of a register
19337 by returning MODE as save mode when the mode is known. */
19338 if (mode
== VOIDmode
)
19339 return choose_hard_reg_mode (regno
, nregs
, false);
19344 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
19347 mips_case_values_threshold (void)
19349 /* In MIPS16 mode using a larger case threshold generates smaller code. */
19350 if (TARGET_MIPS16
&& optimize_size
)
19353 return default_case_values_threshold ();
19356 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
19359 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
19361 if (!TARGET_HARD_FLOAT_ABI
)
19363 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
);
19364 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
);
19365 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
);
19366 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
19367 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
19368 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
19369 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19370 fcsr_orig_var
, get_fcsr_hold_call
);
19371 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
19372 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
19373 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19374 fcsr_mod_var
, hold_mod_val
);
19375 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19376 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
19377 hold_assign_orig
, hold_assign_mod
);
19378 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
19379 set_fcsr_hold_call
);
19381 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19383 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
19384 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19385 exceptions_var
, get_fcsr_update_call
);
19386 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
19387 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19388 set_fcsr_update_call
);
19389 tree atomic_feraiseexcept
19390 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
19391 tree int_exceptions_var
= fold_convert (integer_type_node
,
19393 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
19394 1, int_exceptions_var
);
19395 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19396 atomic_feraiseexcept_call
);
19399 /* Implement TARGET_SPILL_CLASS. */
19402 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
19403 machine_mode mode ATTRIBUTE_UNUSED
)
19410 /* Implement TARGET_LRA_P. */
19415 return mips_lra_flag
;
19418 /* Initialize the GCC target structure. */
19419 #undef TARGET_ASM_ALIGNED_HI_OP
19420 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
19421 #undef TARGET_ASM_ALIGNED_SI_OP
19422 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
19423 #undef TARGET_ASM_ALIGNED_DI_OP
19424 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
19426 #undef TARGET_OPTION_OVERRIDE
19427 #define TARGET_OPTION_OVERRIDE mips_option_override
19429 #undef TARGET_LEGITIMIZE_ADDRESS
19430 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
19432 #undef TARGET_ASM_FUNCTION_PROLOGUE
19433 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
19434 #undef TARGET_ASM_FUNCTION_EPILOGUE
19435 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
19436 #undef TARGET_ASM_SELECT_RTX_SECTION
19437 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
19438 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
19439 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
19441 #undef TARGET_SCHED_INIT
19442 #define TARGET_SCHED_INIT mips_sched_init
19443 #undef TARGET_SCHED_REORDER
19444 #define TARGET_SCHED_REORDER mips_sched_reorder
19445 #undef TARGET_SCHED_REORDER2
19446 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
19447 #undef TARGET_SCHED_VARIABLE_ISSUE
19448 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
19449 #undef TARGET_SCHED_ADJUST_COST
19450 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
19451 #undef TARGET_SCHED_ISSUE_RATE
19452 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
19453 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
19454 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
19455 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
19456 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
19457 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
19458 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
19459 mips_multipass_dfa_lookahead
19460 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
19461 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
19462 mips_small_register_classes_for_mode_p
19464 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
19465 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
19467 #undef TARGET_INSERT_ATTRIBUTES
19468 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
19469 #undef TARGET_MERGE_DECL_ATTRIBUTES
19470 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
19471 #undef TARGET_CAN_INLINE_P
19472 #define TARGET_CAN_INLINE_P mips_can_inline_p
19473 #undef TARGET_SET_CURRENT_FUNCTION
19474 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
19476 #undef TARGET_VALID_POINTER_MODE
19477 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
19478 #undef TARGET_REGISTER_MOVE_COST
19479 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
19480 #undef TARGET_REGISTER_PRIORITY
19481 #define TARGET_REGISTER_PRIORITY mips_register_priority
19482 #undef TARGET_MEMORY_MOVE_COST
19483 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
19484 #undef TARGET_RTX_COSTS
19485 #define TARGET_RTX_COSTS mips_rtx_costs
19486 #undef TARGET_ADDRESS_COST
19487 #define TARGET_ADDRESS_COST mips_address_cost
19489 #undef TARGET_IN_SMALL_DATA_P
19490 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
19492 #undef TARGET_MACHINE_DEPENDENT_REORG
19493 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
19495 #undef TARGET_PREFERRED_RELOAD_CLASS
19496 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
19498 #undef TARGET_EXPAND_TO_RTL_HOOK
19499 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
19500 #undef TARGET_ASM_FILE_START
19501 #define TARGET_ASM_FILE_START mips_file_start
19502 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
19503 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
19504 #undef TARGET_ASM_CODE_END
19505 #define TARGET_ASM_CODE_END mips_code_end
19507 #undef TARGET_INIT_LIBFUNCS
19508 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
19510 #undef TARGET_BUILD_BUILTIN_VA_LIST
19511 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
19512 #undef TARGET_EXPAND_BUILTIN_VA_START
19513 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19514 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19515 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19517 #undef TARGET_PROMOTE_FUNCTION_MODE
19518 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19519 #undef TARGET_PROMOTE_PROTOTYPES
19520 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19522 #undef TARGET_FUNCTION_VALUE
19523 #define TARGET_FUNCTION_VALUE mips_function_value
19524 #undef TARGET_LIBCALL_VALUE
19525 #define TARGET_LIBCALL_VALUE mips_libcall_value
19526 #undef TARGET_FUNCTION_VALUE_REGNO_P
19527 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19528 #undef TARGET_RETURN_IN_MEMORY
19529 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19530 #undef TARGET_RETURN_IN_MSB
19531 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19533 #undef TARGET_ASM_OUTPUT_MI_THUNK
19534 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19535 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19536 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19538 #undef TARGET_PRINT_OPERAND
19539 #define TARGET_PRINT_OPERAND mips_print_operand
19540 #undef TARGET_PRINT_OPERAND_ADDRESS
19541 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19542 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19543 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19545 #undef TARGET_SETUP_INCOMING_VARARGS
19546 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19547 #undef TARGET_STRICT_ARGUMENT_NAMING
19548 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19549 #undef TARGET_MUST_PASS_IN_STACK
19550 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19551 #undef TARGET_PASS_BY_REFERENCE
19552 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19553 #undef TARGET_CALLEE_COPIES
19554 #define TARGET_CALLEE_COPIES mips_callee_copies
19555 #undef TARGET_ARG_PARTIAL_BYTES
19556 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19557 #undef TARGET_FUNCTION_ARG
19558 #define TARGET_FUNCTION_ARG mips_function_arg
19559 #undef TARGET_FUNCTION_ARG_ADVANCE
19560 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19561 #undef TARGET_FUNCTION_ARG_BOUNDARY
19562 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19563 #undef TARGET_GET_RAW_RESULT_MODE
19564 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
19565 #undef TARGET_GET_RAW_ARG_MODE
19566 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
19568 #undef TARGET_MODE_REP_EXTENDED
19569 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19571 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19572 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19574 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19575 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19577 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19578 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19580 #undef TARGET_INIT_BUILTINS
19581 #define TARGET_INIT_BUILTINS mips_init_builtins
19582 #undef TARGET_BUILTIN_DECL
19583 #define TARGET_BUILTIN_DECL mips_builtin_decl
19584 #undef TARGET_EXPAND_BUILTIN
19585 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19587 #undef TARGET_HAVE_TLS
19588 #define TARGET_HAVE_TLS HAVE_AS_TLS
19590 #undef TARGET_CANNOT_FORCE_CONST_MEM
19591 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19593 #undef TARGET_LEGITIMATE_CONSTANT_P
19594 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19596 #undef TARGET_ENCODE_SECTION_INFO
19597 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19599 #undef TARGET_ATTRIBUTE_TABLE
19600 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19601 /* All our function attributes are related to how out-of-line copies should
19602 be compiled or called. They don't in themselves prevent inlining. */
19603 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19604 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19606 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19607 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19609 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19610 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19611 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19612 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19614 #undef TARGET_COMP_TYPE_ATTRIBUTES
19615 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19617 #ifdef HAVE_AS_DTPRELWORD
19618 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19619 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19621 #undef TARGET_DWARF_REGISTER_SPAN
19622 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19623 #undef TARGET_DWARF_FRAME_REG_MODE
19624 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
19626 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19627 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19629 #undef TARGET_LEGITIMATE_ADDRESS_P
19630 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19632 #undef TARGET_FRAME_POINTER_REQUIRED
19633 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19635 #undef TARGET_CAN_ELIMINATE
19636 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19638 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19639 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19641 #undef TARGET_TRAMPOLINE_INIT
19642 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19644 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19645 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19647 #undef TARGET_SHIFT_TRUNCATION_MASK
19648 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19650 #undef TARGET_PREPARE_PCH_SAVE
19651 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19653 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19654 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19656 #undef TARGET_CASE_VALUES_THRESHOLD
19657 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19659 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19660 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19662 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19663 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19665 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
19666 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
19667 mips_use_by_pieces_infrastructure_p
19669 #undef TARGET_SPILL_CLASS
19670 #define TARGET_SPILL_CLASS mips_spill_class
19671 #undef TARGET_LRA_P
19672 #define TARGET_LRA_P mips_lra_p
19674 struct gcc_target targetm
= TARGET_INITIALIZER
;
19676 #include "gt-mips.h"