1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
260 "$fcc5","$fcc6","$fcc7","$rap"
263 /* Mips software names for the registers, used to overwrite the
264 mips_reg_names array. */
266 char mips_sw_reg_names
[][8] =
268 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
269 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
270 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
271 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
272 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
273 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
274 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
275 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
276 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
277 "$fcc5","$fcc6","$fcc7","$rap"
280 /* Map hard register number to register class */
281 enum reg_class mips_regno_to_class
[] =
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
300 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
301 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
304 /* Map register constraint character to register class. */
305 enum reg_class mips_char_to_class
[256] =
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
374 /* Return truth value of whether OP can be used as an operands
375 where a register or 16 bit unsigned integer is needed. */
378 uns_arith_operand (op
, mode
)
380 enum machine_mode mode
;
382 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
385 return register_operand (op
, mode
);
388 /* Return truth value of whether OP can be used as an operands
389 where a 16 bit integer is needed */
392 arith_operand (op
, mode
)
394 enum machine_mode mode
;
396 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
399 return register_operand (op
, mode
);
402 /* Return truth value of whether OP can be used as an operand in a two
403 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
406 arith32_operand (op
, mode
)
408 enum machine_mode mode
;
410 if (GET_CODE (op
) == CONST_INT
)
413 return register_operand (op
, mode
);
416 /* Return truth value of whether OP is a integer which fits in 16 bits */
421 enum machine_mode mode
;
423 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
426 /* Return truth value of whether OP is a 32 bit integer which is too big to
427 be loaded with one instruction. */
432 enum machine_mode mode
;
436 if (GET_CODE (op
) != CONST_INT
)
440 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
443 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
446 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
452 /* Return truth value of whether OP is a register or the constant 0. */
455 reg_or_0_operand (op
, mode
)
457 enum machine_mode mode
;
459 switch (GET_CODE (op
))
465 return (INTVAL (op
) == 0);
468 if (op
!= CONST0_RTX (mode
))
475 return register_operand (op
, mode
);
481 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
484 mips_const_double_ok (op
, mode
)
486 enum machine_mode mode
;
490 if (GET_CODE (op
) != CONST_DOUBLE
)
493 if (mode
== VOIDmode
)
496 if (mode
!= SFmode
&& mode
!= DFmode
)
499 if (op
== CONST0_RTX (mode
))
502 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
503 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
506 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
508 if (REAL_VALUE_ISNAN (d
))
511 if (REAL_VALUE_NEGATIVE (d
))
512 d
= REAL_VALUE_NEGATE (d
);
516 if (REAL_VALUES_LESS (d
, dfhigh
)
517 && REAL_VALUES_LESS (dflow
, d
))
522 if (REAL_VALUES_LESS (d
, sfhigh
)
523 && REAL_VALUES_LESS (sflow
, d
))
530 /* Accept the floating point constant 1 in the appropriate mode. */
533 const_float_1_operand (op
, mode
)
535 enum machine_mode mode
;
538 static REAL_VALUE_TYPE onedf
;
539 static REAL_VALUE_TYPE onesf
;
540 static int one_initialized
;
542 if (GET_CODE (op
) != CONST_DOUBLE
543 || mode
!= GET_MODE (op
)
544 || (mode
!= DFmode
&& mode
!= SFmode
))
547 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
549 /* We only initialize these values if we need them, since we will
550 never get called unless mips_isa >= 4. */
551 if (! one_initialized
)
553 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
554 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
555 one_initialized
= TRUE
;
559 return REAL_VALUES_EQUAL (d
, onedf
);
561 return REAL_VALUES_EQUAL (d
, onesf
);
564 /* Return truth value if a memory operand fits in a single instruction
565 (ie, register + small offset). */
568 simple_memory_operand (op
, mode
)
570 enum machine_mode mode
;
572 rtx addr
, plus0
, plus1
;
574 /* Eliminate non-memory operations */
575 if (GET_CODE (op
) != MEM
)
578 /* dword operations really put out 2 instructions, so eliminate them. */
579 /* ??? This isn't strictly correct. It is OK to accept multiword modes
580 here, since the length attributes are being set correctly, but only
581 if the address is offsettable. LO_SUM is not offsettable. */
582 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
585 /* Decode the address now. */
587 switch (GET_CODE (addr
))
597 return SMALL_INT (op
);
600 plus0
= XEXP (addr
, 0);
601 plus1
= XEXP (addr
, 1);
602 if (GET_CODE (plus0
) == REG
603 && GET_CODE (plus1
) == CONST_INT
604 && SMALL_INT (plus1
))
607 else if (GET_CODE (plus1
) == REG
608 && GET_CODE (plus0
) == CONST_INT
609 && SMALL_INT (plus0
))
616 /* We used to allow small symbol refs here (ie, stuff in .sdata
617 or .sbss), but this causes some bugs in G++. Also, it won't
618 interfere if the MIPS linker rewrites the store instruction
619 because the function is PIC. */
621 case LABEL_REF
: /* never gp relative */
625 /* If -G 0, we can never have a GP relative memory operation.
626 Also, save some time if not optimizing. */
631 rtx offset
= const0_rtx
;
632 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
633 if (GET_CODE (op
) != SYMBOL_REF
)
636 /* let's be paranoid.... */
637 if (! SMALL_INT (offset
))
643 return SYMBOL_REF_FLAG (addr
);
650 /* Return true if the code of this rtx pattern is EQ or NE. */
653 equality_op (op
, mode
)
655 enum machine_mode mode
;
657 if (mode
!= GET_MODE (op
))
660 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
663 /* Return true if the code is a relational operations (EQ, LE, etc.) */
668 enum machine_mode mode
;
670 if (mode
!= GET_MODE (op
))
673 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
676 /* Return true if the operand is either the PC or a label_ref. */
679 pc_or_label_operand (op
, mode
)
681 enum machine_mode mode
;
686 if (GET_CODE (op
) == LABEL_REF
)
692 /* Test for a valid operand for a call instruction.
693 Don't allow the arg pointer register or virtual regs
694 since they may change into reg + const, which the patterns
698 call_insn_operand (op
, mode
)
700 enum machine_mode mode
;
702 if (CONSTANT_ADDRESS_P (op
)
703 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
704 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
705 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
710 /* Return true if OPERAND is valid as a source operand for a move
714 move_operand (op
, mode
)
716 enum machine_mode mode
;
718 return (general_operand (op
, mode
)
719 && ! (mips_split_addresses
&& mips_check_split (op
, mode
)));
722 /* Return true if OPERAND is valid as a source operand for movdi.
723 This accepts not only general_operand, but also sign extended
724 constants and registers. We need to accept sign extended constants
725 in case a sign extended register which is used in an expression,
726 and is equivalent to a constant, is spilled. */
729 movdi_operand (op
, mode
)
731 enum machine_mode mode
;
735 && GET_CODE (op
) == SIGN_EXTEND
736 && GET_MODE (op
) == DImode
737 && (GET_MODE (XEXP (op
, 0)) == SImode
738 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
739 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
740 && (register_operand (XEXP (op
, 0), SImode
)
741 || immediate_operand (XEXP (op
, 0), SImode
)))
744 return general_operand (op
, mode
);
747 /* Like register_operand, but when in 64 bit mode also accept a sign
748 extend of a 32 bit register, since the value is known to be already
752 se_register_operand (op
, mode
)
754 enum machine_mode mode
;
758 && GET_CODE (op
) == SIGN_EXTEND
759 && GET_MODE (op
) == DImode
760 && GET_MODE (XEXP (op
, 0)) == SImode
761 && register_operand (XEXP (op
, 0), SImode
))
764 return register_operand (op
, mode
);
767 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
768 extend of a 32 bit register, since the value is known to be already
772 se_reg_or_0_operand (op
, mode
)
774 enum machine_mode mode
;
778 && GET_CODE (op
) == SIGN_EXTEND
779 && GET_MODE (op
) == DImode
780 && GET_MODE (XEXP (op
, 0)) == SImode
781 && register_operand (XEXP (op
, 0), SImode
))
784 return reg_or_0_operand (op
, mode
);
787 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
788 extend of a 32 bit register, since the value is known to be already
792 se_uns_arith_operand (op
, mode
)
794 enum machine_mode mode
;
798 && GET_CODE (op
) == SIGN_EXTEND
799 && GET_MODE (op
) == DImode
800 && GET_MODE (XEXP (op
, 0)) == SImode
801 && register_operand (XEXP (op
, 0), SImode
))
804 return uns_arith_operand (op
, mode
);
807 /* Like arith_operand, but when in 64 bit mode also accept a sign
808 extend of a 32 bit register, since the value is known to be already
812 se_arith_operand (op
, mode
)
814 enum machine_mode mode
;
818 && GET_CODE (op
) == SIGN_EXTEND
819 && GET_MODE (op
) == DImode
820 && GET_MODE (XEXP (op
, 0)) == SImode
821 && register_operand (XEXP (op
, 0), SImode
))
824 return arith_operand (op
, mode
);
827 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
828 extend of a 32 bit register, since the value is known to be already
832 se_nonmemory_operand (op
, mode
)
834 enum machine_mode mode
;
838 && GET_CODE (op
) == SIGN_EXTEND
839 && GET_MODE (op
) == DImode
840 && GET_MODE (XEXP (op
, 0)) == SImode
841 && register_operand (XEXP (op
, 0), SImode
))
844 return nonmemory_operand (op
, mode
);
847 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
848 sign extend of a 32 bit register, since the value is known to be
849 already sign extended. */
852 se_nonimmediate_operand (op
, mode
)
854 enum machine_mode mode
;
858 && GET_CODE (op
) == SIGN_EXTEND
859 && GET_MODE (op
) == DImode
860 && GET_MODE (XEXP (op
, 0)) == SImode
861 && register_operand (XEXP (op
, 0), SImode
))
864 return nonimmediate_operand (op
, mode
);
867 /* Return true if we split the address into high and low parts. */
869 /* ??? We should also handle reg+array somewhere. We get four
870 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
871 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
872 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
873 out of the address, then we have 4 instructions to combine. Perhaps
874 add a 3->2 define_split for combine. */
876 /* ??? We could also split a CONST_INT here if it is a large_int().
877 However, it doesn't seem to be very useful to have %hi(constant).
878 We would be better off by doing the masking ourselves and then putting
879 the explicit high part of the constant in the RTL. This will give better
880 optimization. Also, %hi(constant) needs assembler changes to work.
881 There is already a define_split that does this. */
884 mips_check_split (address
, mode
)
886 enum machine_mode mode
;
888 /* ??? This is the same check used in simple_memory_operand.
889 We use it here because LO_SUM is not offsettable. */
890 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
893 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
894 || (GET_CODE (address
) == CONST
895 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
896 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
897 || GET_CODE (address
) == LABEL_REF
)
903 /* Returns an operand string for the given instruction's delay slot,
904 after updating filled delay slot statistics.
906 We assume that operands[0] is the target register that is set.
908 In order to check the next insn, most of this functionality is moved
909 to FINAL_PRESCAN_INSN, and we just set the global variables that
912 /* ??? This function no longer does anything useful, because final_prescan_insn
913 now will never emit a nop. */
916 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
917 char *ret
; /* normal string to return */
918 enum delay_type type
; /* type of delay */
919 rtx operands
[]; /* operands to use */
920 rtx cur_insn
; /* current insn */
922 register rtx set_reg
;
923 register enum machine_mode mode
;
924 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
925 register int num_nops
;
927 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
930 else if (type
== DELAY_HILO
)
936 /* Make sure that we don't put nop's after labels. */
937 next_insn
= NEXT_INSN (cur_insn
);
938 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
939 next_insn
= NEXT_INSN (next_insn
);
941 dslots_load_total
+= num_nops
;
942 if (TARGET_DEBUG_F_MODE
944 || type
== DELAY_NONE
945 || operands
== (rtx
*)0
946 || cur_insn
== (rtx
)0
947 || next_insn
== (rtx
)0
948 || GET_CODE (next_insn
) == CODE_LABEL
949 || (set_reg
= operands
[0]) == (rtx
)0)
951 dslots_number_nops
= 0;
952 mips_load_reg
= (rtx
)0;
953 mips_load_reg2
= (rtx
)0;
954 mips_load_reg3
= (rtx
)0;
955 mips_load_reg4
= (rtx
)0;
959 set_reg
= operands
[0];
960 if (set_reg
== (rtx
)0)
963 while (GET_CODE (set_reg
) == SUBREG
)
964 set_reg
= SUBREG_REG (set_reg
);
966 mode
= GET_MODE (set_reg
);
967 dslots_number_nops
= num_nops
;
968 mips_load_reg
= set_reg
;
969 if (GET_MODE_SIZE (mode
)
970 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
971 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
975 if (type
== DELAY_HILO
)
977 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
978 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
990 /* Determine whether a memory reference takes one (based off of the GP pointer),
991 two (normal), or three (label + reg) instructions, and bump the appropriate
992 counter for -mstats. */
995 mips_count_memory_refs (op
, num
)
1001 rtx addr
, plus0
, plus1
;
1002 enum rtx_code code0
, code1
;
1005 if (TARGET_DEBUG_B_MODE
)
1007 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1011 /* Skip MEM if passed, otherwise handle movsi of address. */
1012 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1014 /* Loop, going through the address RTL */
1018 switch (GET_CODE (addr
))
1029 plus0
= XEXP (addr
, 0);
1030 plus1
= XEXP (addr
, 1);
1031 code0
= GET_CODE (plus0
);
1032 code1
= GET_CODE (plus1
);
1042 if (code0
== CONST_INT
)
1057 if (code1
== CONST_INT
)
1064 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1071 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1081 n_words
= 2; /* always 2 words */
1085 addr
= XEXP (addr
, 0);
1090 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1099 n_words
+= additional
;
1103 num_refs
[n_words
-1] += num
;
1107 /* Return RTL for the offset from the current function to the
1111 embedded_pic_offset (x
)
1114 if (embedded_pic_fnaddr_rtx
== NULL
)
1118 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1120 /* Output code at function start to initialize the pseudo-reg. */
1121 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1122 inline functions, because it is called after RTL for the function
1123 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1124 does not get copied, and ends up not matching the rest of the RTL.
1125 This solution works, but means that we get unnecessary code to
1126 initialize this value every time a function is inlined into another
1129 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1130 XEXP (DECL_RTL (current_function_decl
), 0)));
1131 seq
= gen_sequence ();
1133 push_topmost_sequence ();
1134 emit_insn_after (seq
, get_insns ());
1135 pop_topmost_sequence ();
1138 return gen_rtx (CONST
, Pmode
,
1139 gen_rtx (MINUS
, Pmode
, x
,
1140 XEXP (DECL_RTL (current_function_decl
), 0)));
1143 /* Return the appropriate instructions to move one operand to another. */
1146 mips_move_1word (operands
, insn
, unsignedp
)
1152 rtx op0
= operands
[0];
1153 rtx op1
= operands
[1];
1154 enum rtx_code code0
= GET_CODE (op0
);
1155 enum rtx_code code1
= GET_CODE (op1
);
1156 enum machine_mode mode
= GET_MODE (op0
);
1157 int subreg_word0
= 0;
1158 int subreg_word1
= 0;
1159 enum delay_type delay
= DELAY_NONE
;
1161 while (code0
== SUBREG
)
1163 subreg_word0
+= SUBREG_WORD (op0
);
1164 op0
= SUBREG_REG (op0
);
1165 code0
= GET_CODE (op0
);
1168 while (code1
== SUBREG
)
1170 subreg_word1
+= SUBREG_WORD (op1
);
1171 op1
= SUBREG_REG (op1
);
1172 code1
= GET_CODE (op1
);
1175 /* For our purposes, a condition code mode is the same as SImode. */
1181 int regno0
= REGNO (op0
) + subreg_word0
;
1185 int regno1
= REGNO (op1
) + subreg_word1
;
1187 /* Just in case, don't do anything for assigning a register
1188 to itself, unless we are filling a delay slot. */
1189 if (regno0
== regno1
&& set_nomacro
== 0)
1192 else if (GP_REG_P (regno0
))
1194 if (GP_REG_P (regno1
))
1195 ret
= "move\t%0,%1";
1197 else if (MD_REG_P (regno1
))
1200 if (regno1
!= HILO_REGNUM
)
1206 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1207 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1212 if (FP_REG_P (regno1
))
1213 ret
= "mfc1\t%0,%1";
1215 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1216 ret
= "cfc1\t%0,$31";
1220 else if (FP_REG_P (regno0
))
1222 if (GP_REG_P (regno1
))
1225 ret
= "mtc1\t%1,%0";
1228 if (FP_REG_P (regno1
))
1229 ret
= "mov.s\t%0,%1";
1232 else if (MD_REG_P (regno0
))
1234 if (GP_REG_P (regno1
))
1237 if (regno0
!= HILO_REGNUM
)
1242 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1244 if (GP_REG_P (regno1
))
1247 ret
= "ctc1\t%0,$31";
1252 else if (code1
== MEM
)
1257 mips_count_memory_refs (op1
, 1);
1259 if (GP_REG_P (regno0
))
1261 /* For loads, use the mode of the memory item, instead of the
1262 target, so zero/sign extend can use this code as well. */
1263 switch (GET_MODE (op1
))
1272 ret
= ((unsignedp
&& TARGET_64BIT
)
1277 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1280 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1285 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1288 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1290 int i
= strlen (ret
);
1291 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1294 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1295 ret
= volatile_buffer
;
1299 else if (code1
== CONST_INT
1300 || (code1
== CONST_DOUBLE
1301 && GET_MODE (op1
) == VOIDmode
))
1303 if (code1
== CONST_DOUBLE
)
1305 /* This can happen when storing constants into long long
1306 bitfields. Just store the least significant word of
1308 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1311 if (INTVAL (op1
) == 0)
1313 if (GP_REG_P (regno0
))
1314 ret
= "move\t%0,%z1";
1316 else if (FP_REG_P (regno0
))
1319 ret
= "mtc1\t%z1,%0";
1322 else if (MD_REG_P (regno0
))
1329 else if (GP_REG_P (regno0
))
1330 /* Don't use X format, because that will give out of range
1331 numbers for 64 bit host and 32 bit target. */
1332 ret
= "li\t%0,%1\t\t\t# %X1";
1335 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1337 if (op1
== CONST0_RTX (SFmode
))
1339 if (GP_REG_P (regno0
))
1340 ret
= "move\t%0,%.";
1342 else if (FP_REG_P (regno0
))
1345 ret
= "mtc1\t%.,%0";
1352 ret
= "li.s\t%0,%1";
1356 else if (code1
== LABEL_REF
)
1359 mips_count_memory_refs (op1
, 1);
1364 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1366 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1368 rtx offset
= const0_rtx
;
1370 if (GET_CODE (op1
) == CONST
)
1371 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1373 if (GET_CODE (op1
) == SYMBOL_REF
)
1375 operands
[2] = HALF_PIC_PTR (op1
);
1378 mips_count_memory_refs (operands
[2], 1);
1380 if (INTVAL (offset
) == 0)
1383 ret
= (unsignedp
&& TARGET_64BIT
1389 dslots_load_total
++;
1390 operands
[3] = offset
;
1391 if (unsignedp
&& TARGET_64BIT
)
1392 ret
= (SMALL_INT (offset
))
1393 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1394 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1396 ret
= (SMALL_INT (offset
))
1397 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1398 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1405 mips_count_memory_refs (op1
, 1);
1411 else if (code1
== PLUS
)
1413 rtx add_op0
= XEXP (op1
, 0);
1414 rtx add_op1
= XEXP (op1
, 1);
1416 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1418 add_op0
= XEXP (op1
, 1); /* reverse operands */
1419 add_op1
= XEXP (op1
, 0);
1422 operands
[2] = add_op0
;
1423 operands
[3] = add_op1
;
1424 ret
= "add%:\t%0,%2,%3";
1427 else if (code1
== HIGH
)
1429 operands
[1] = XEXP (op1
, 0);
1430 ret
= "lui\t%0,%%hi(%1)";
1434 else if (code0
== MEM
)
1437 mips_count_memory_refs (op0
, 1);
1441 int regno1
= REGNO (op1
) + subreg_word1
;
1443 if (GP_REG_P (regno1
))
1448 case SFmode
: ret
= "sw\t%1,%0"; break;
1449 case SImode
: ret
= "sw\t%1,%0"; break;
1450 case HImode
: ret
= "sh\t%1,%0"; break;
1451 case QImode
: ret
= "sb\t%1,%0"; break;
1455 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1459 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1464 case SFmode
: ret
= "sw\t%z1,%0"; break;
1465 case SImode
: ret
= "sw\t%z1,%0"; break;
1466 case HImode
: ret
= "sh\t%z1,%0"; break;
1467 case QImode
: ret
= "sb\t%z1,%0"; break;
1471 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1476 case SFmode
: ret
= "sw\t%.,%0"; break;
1477 case SImode
: ret
= "sw\t%.,%0"; break;
1478 case HImode
: ret
= "sh\t%.,%0"; break;
1479 case QImode
: ret
= "sb\t%.,%0"; break;
1483 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1485 int i
= strlen (ret
);
1486 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1489 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1490 ret
= volatile_buffer
;
1494 if (ret
== (char *)0)
1496 abort_with_insn (insn
, "Bad move");
1500 if (delay
!= DELAY_NONE
)
1501 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1507 /* Return the appropriate instructions to move 2 words */
1510 mips_move_2words (operands
, insn
)
1515 rtx op0
= operands
[0];
1516 rtx op1
= operands
[1];
1517 enum rtx_code code0
= GET_CODE (operands
[0]);
1518 enum rtx_code code1
= GET_CODE (operands
[1]);
1519 int subreg_word0
= 0;
1520 int subreg_word1
= 0;
1521 enum delay_type delay
= DELAY_NONE
;
1523 while (code0
== SUBREG
)
1525 subreg_word0
+= SUBREG_WORD (op0
);
1526 op0
= SUBREG_REG (op0
);
1527 code0
= GET_CODE (op0
);
1530 if (code1
== SIGN_EXTEND
)
1532 op1
= XEXP (op1
, 0);
1533 code1
= GET_CODE (op1
);
1536 while (code1
== SUBREG
)
1538 subreg_word1
+= SUBREG_WORD (op1
);
1539 op1
= SUBREG_REG (op1
);
1540 code1
= GET_CODE (op1
);
1544 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1546 && code1
!= CONST_INT
)
1551 int regno0
= REGNO (op0
) + subreg_word0
;
1555 int regno1
= REGNO (op1
) + subreg_word1
;
1557 /* Just in case, don't do anything for assigning a register
1558 to itself, unless we are filling a delay slot. */
1559 if (regno0
== regno1
&& set_nomacro
== 0)
1562 else if (FP_REG_P (regno0
))
1564 if (FP_REG_P (regno1
))
1565 ret
= "mov.d\t%0,%1";
1573 abort_with_insn (insn
, "Bad move");
1574 #ifdef TARGET_FP_CALL_32
1575 if (FP_CALL_GP_REG_P (regno1
))
1576 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1579 ret
= "dmtc1\t%1,%0";
1582 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1586 else if (FP_REG_P (regno1
))
1592 abort_with_insn (insn
, "Bad move");
1593 #ifdef TARGET_FP_CALL_32
1594 if (FP_CALL_GP_REG_P (regno0
))
1595 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1598 ret
= "dmfc1\t%0,%1";
1601 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1604 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1609 if (regno0
!= HILO_REGNUM
)
1611 else if (regno1
== 0)
1612 ret
= "mtlo\t%.\n\tmthi\t%.";
1615 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1618 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1623 if (regno1
!= HILO_REGNUM
)
1627 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1630 else if (TARGET_64BIT
)
1631 ret
= "move\t%0,%1";
1633 else if (regno0
!= (regno1
+1))
1634 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1637 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1640 else if (code1
== CONST_DOUBLE
)
1642 /* Move zero from $0 unless !TARGET_64BIT and recipient
1643 is 64-bit fp reg, in which case generate a constant. */
1644 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1645 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1647 if (GET_MODE (op1
) == DFmode
)
1650 #ifdef TARGET_FP_CALL_32
1651 if (FP_CALL_GP_REG_P (regno0
))
1653 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1655 split_double (op1
, operands
+ 2, operands
+ 3);
1656 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1659 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1663 ret
= "li.d\t%0,%1";
1666 else if (TARGET_64BIT
)
1671 split_double (op1
, operands
+ 2, operands
+ 3);
1672 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1678 if (GP_REG_P (regno0
))
1680 #ifdef TARGET_FP_CALL_32
1681 && ! FP_CALL_GP_REG_P (regno0
)
1685 : "move\t%0,%.\n\tmove\t%D0,%.";
1687 else if (FP_REG_P (regno0
))
1690 ret
= (TARGET_64BIT
)
1692 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1697 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1699 if (GP_REG_P (regno0
))
1700 ret
= (TARGET_64BIT
)
1702 : "move\t%0,%.\n\tmove\t%D0,%.";
1704 else if (FP_REG_P (regno0
))
1707 ret
= (TARGET_64BIT
)
1711 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1713 else if (MD_REG_P (regno0
))
1716 if (regno0
!= HILO_REGNUM
)
1719 ret
= "mtlo\t%.\n\tmthi\t%.";
1723 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1727 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1728 ret
= "li\t%0,%1\t\t# %X1";
1729 else if (HOST_BITS_PER_WIDE_INT
< 64)
1730 /* We can't use 'X' for negative numbers, because then we won't
1731 get the right value for the upper 32 bits. */
1732 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1733 : "dli\t%0,%X1\t\t# %1");
1735 /* We must use 'X', because otherwise LONG_MIN will print as
1736 a number that the assembler won't accept. */
1737 ret
= "dli\t%0,%X1\t\t# %1";
1739 else if (HOST_BITS_PER_WIDE_INT
< 64)
1741 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1742 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1746 /* We use multiple shifts here, to avoid warnings about out
1747 of range shifts on 32 bit hosts. */
1748 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1749 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1750 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1754 else if (code1
== MEM
)
1759 mips_count_memory_refs (op1
, 2);
1761 if (FP_REG_P (regno0
))
1764 else if (TARGET_64BIT
)
1766 #ifdef TARGET_FP_CALL_32
1767 if (FP_CALL_GP_REG_P (regno0
))
1769 if (offsettable_address_p (FALSE
, SImode
, op1
))
1770 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1772 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1779 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1781 operands
[2] = adj_offsettable_operand (op1
, 4);
1782 if (reg_mentioned_p (op0
, op1
))
1783 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1785 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1788 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1790 int i
= strlen (ret
);
1791 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1794 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1795 ret
= volatile_buffer
;
1799 else if (code1
== LABEL_REF
1800 || code1
== SYMBOL_REF
1804 mips_count_memory_refs (op1
, 2);
1806 ret
= "dla\t%0,%a1";
1810 else if (code0
== MEM
)
1814 int regno1
= REGNO (op1
) + subreg_word1
;
1816 if (FP_REG_P (regno1
))
1819 else if (TARGET_64BIT
)
1821 #ifdef TARGET_FP_CALL_32
1822 if (FP_CALL_GP_REG_P (regno1
))
1823 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1829 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1831 operands
[2] = adj_offsettable_operand (op0
, 4);
1832 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1836 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1837 || (code1
== CONST_DOUBLE
1838 && op1
== CONST0_RTX (GET_MODE (op1
))))
1840 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1846 operands
[2] = adj_offsettable_operand (op0
, 4);
1847 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1852 mips_count_memory_refs (op0
, 2);
1854 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1856 int i
= strlen (ret
);
1857 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1860 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1861 ret
= volatile_buffer
;
1865 if (ret
== (char *)0)
1867 abort_with_insn (insn
, "Bad move");
1871 if (delay
!= DELAY_NONE
)
1872 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1878 /* Provide the costs of an addressing mode that contains ADDR.
1879 If ADDR is not a valid address, its cost is irrelevant. */
1882 mips_address_cost (addr
)
1885 switch (GET_CODE (addr
))
1898 rtx offset
= const0_rtx
;
1899 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1900 if (GET_CODE (addr
) == LABEL_REF
)
1903 if (GET_CODE (addr
) != SYMBOL_REF
)
1906 if (! SMALL_INT (offset
))
1912 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1916 register rtx plus0
= XEXP (addr
, 0);
1917 register rtx plus1
= XEXP (addr
, 1);
1919 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1921 plus0
= XEXP (addr
, 1);
1922 plus1
= XEXP (addr
, 0);
1925 if (GET_CODE (plus0
) != REG
)
1928 switch (GET_CODE (plus1
))
1934 return (SMALL_INT (plus1
) ? 1 : 2);
1941 return mips_address_cost (plus1
) + 1;
1949 /* Return true if X is an address which needs a temporary register when
1950 reloaded while generating PIC code. */
1953 pic_address_needs_scratch (x
)
1956 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1957 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1958 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1959 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1960 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1966 /* Make normal rtx_code into something we can index from an array */
1968 static enum internal_test
1969 map_test_to_internal_test (test_code
)
1970 enum rtx_code test_code
;
1972 enum internal_test test
= ITEST_MAX
;
1977 case EQ
: test
= ITEST_EQ
; break;
1978 case NE
: test
= ITEST_NE
; break;
1979 case GT
: test
= ITEST_GT
; break;
1980 case GE
: test
= ITEST_GE
; break;
1981 case LT
: test
= ITEST_LT
; break;
1982 case LE
: test
= ITEST_LE
; break;
1983 case GTU
: test
= ITEST_GTU
; break;
1984 case GEU
: test
= ITEST_GEU
; break;
1985 case LTU
: test
= ITEST_LTU
; break;
1986 case LEU
: test
= ITEST_LEU
; break;
1993 /* Generate the code to compare two integer values. The return value is:
1994 (reg:SI xx) The pseudo register the comparison is in
1995 (rtx)0 No register, generate a simple branch.
1997 ??? This is called with result nonzero by the Scond patterns in
1998 mips.md. These patterns are called with a target in the mode of
1999 the Scond instruction pattern. Since this must be a constant, we
2000 must use SImode. This means that if RESULT is non-zero, it will
2001 always be an SImode register, even if TARGET_64BIT is true. We
2002 cope with this by calling convert_move rather than emit_move_insn.
2003 This will sometimes lead to an unnecessary extension of the result;
2015 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2016 enum rtx_code test_code
; /* relational test (EQ, etc) */
2017 rtx result
; /* result to store comp. or 0 if branch */
2018 rtx cmp0
; /* first operand to compare */
2019 rtx cmp1
; /* second operand to compare */
2020 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2021 /* to reverse its test */
2024 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2025 int const_low
; /* low bound of constant we can accept */
2026 int const_high
; /* high bound of constant we can accept */
2027 int const_add
; /* constant to add (convert LE -> LT) */
2028 int reverse_regs
; /* reverse registers in test */
2029 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2030 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2031 int unsignedp
; /* != 0 for unsigned comparisons. */
2034 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2036 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2037 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2038 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2039 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2040 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2041 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2042 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2043 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2044 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2045 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2048 enum internal_test test
;
2049 enum machine_mode mode
;
2050 struct cmp_info
*p_info
;
2057 test
= map_test_to_internal_test (test_code
);
2058 if (test
== ITEST_MAX
)
2061 p_info
= &info
[ (int)test
];
2062 eqne_p
= (p_info
->test_code
== XOR
);
2064 mode
= GET_MODE (cmp0
);
2065 if (mode
== VOIDmode
)
2066 mode
= GET_MODE (cmp1
);
2068 /* Eliminate simple branches */
2069 branch_p
= (result
== (rtx
)0);
2072 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2074 /* Comparisons against zero are simple branches */
2075 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2078 /* Test for beq/bne. */
2083 /* allocate a pseudo to calculate the value in. */
2084 result
= gen_reg_rtx (mode
);
2087 /* Make sure we can handle any constants given to us. */
2088 if (GET_CODE (cmp0
) == CONST_INT
)
2089 cmp0
= force_reg (mode
, cmp0
);
2091 if (GET_CODE (cmp1
) == CONST_INT
)
2093 HOST_WIDE_INT value
= INTVAL (cmp1
);
2094 if (value
< p_info
->const_low
2095 || value
> p_info
->const_high
2096 /* ??? Why? And why wasn't the similar code below modified too? */
2098 && HOST_BITS_PER_WIDE_INT
< 64
2099 && p_info
->const_add
!= 0
2100 && ((p_info
->unsignedp
2101 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2103 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2104 != (p_info
->const_add
> 0))))
2105 cmp1
= force_reg (mode
, cmp1
);
2108 /* See if we need to invert the result. */
2109 invert
= (GET_CODE (cmp1
) == CONST_INT
)
2110 ? p_info
->invert_const
2111 : p_info
->invert_reg
;
2113 if (p_invert
!= (int *)0)
2119 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2120 Comparison between two registers, may involve switching operands. */
2121 if (GET_CODE (cmp1
) == CONST_INT
)
2123 if (p_info
->const_add
!= 0)
2125 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2126 /* If modification of cmp1 caused overflow,
2127 we would get the wrong answer if we follow the usual path;
2128 thus, x > 0xffffffffU would turn into x > 0U. */
2129 if ((p_info
->unsignedp
2130 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2131 : new > INTVAL (cmp1
))
2132 != (p_info
->const_add
> 0))
2134 /* This test is always true, but if INVERT is true then
2135 the result of the test needs to be inverted so 0 should
2136 be returned instead. */
2137 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2141 cmp1
= GEN_INT (new);
2144 else if (p_info
->reverse_regs
)
2151 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2155 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2156 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2159 if (test
== ITEST_NE
)
2161 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2165 else if (test
== ITEST_EQ
)
2167 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2168 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2173 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2179 /* Emit the common code for doing conditional branches.
2180 operand[0] is the label to jump to.
2181 The comparison operands are saved away by cmp{si,di,sf,df}. */
2184 gen_conditional_branch (operands
, test_code
)
2186 enum rtx_code test_code
;
2188 enum cmp_type type
= branch_type
;
2189 rtx cmp0
= branch_cmp
[0];
2190 rtx cmp1
= branch_cmp
[1];
2191 enum machine_mode mode
;
2199 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2203 mode
= type
== CMP_SI
? SImode
: DImode
;
2205 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2212 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2214 /* We don't want to build a comparison against a non-zero
2216 cmp1
= force_reg (mode
, cmp1
);
2223 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2225 reg
= gen_reg_rtx (CCmode
);
2227 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2228 0 in the instruction built below. The MIPS FPU handles
2229 inequality testing by testing for equality and looking for a
2231 emit_insn (gen_rtx (SET
, VOIDmode
,
2233 gen_rtx (test_code
== NE
? EQ
: test_code
,
2234 CCmode
, cmp0
, cmp1
)));
2236 test_code
= test_code
== NE
? EQ
: NE
;
2244 /* Generate the branch. */
2246 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2255 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2257 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2258 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2263 /* Emit the common code for conditional moves. OPERANDS is the array
2264 of operands passed to the conditional move defined_expand. */
2267 gen_conditional_move (operands
)
2270 rtx op0
= branch_cmp
[0];
2271 rtx op1
= branch_cmp
[1];
2272 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2273 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2274 enum rtx_code move_code
= NE
;
2275 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2276 enum machine_mode cmp_mode
;
2279 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2298 op0
= force_reg (mode
, branch_cmp
[1]);
2299 op1
= branch_cmp
[0];
2303 op0
= force_reg (mode
, branch_cmp
[1]);
2304 op1
= branch_cmp
[0];
2315 op0
= force_reg (mode
, branch_cmp
[1]);
2316 op1
= branch_cmp
[0];
2320 op0
= force_reg (mode
, branch_cmp
[1]);
2321 op1
= branch_cmp
[0];
2337 if (mode
== SImode
|| mode
== DImode
)
2339 else if (mode
== SFmode
|| mode
== DFmode
)
2344 cmp_reg
= gen_reg_rtx (cmp_mode
);
2345 emit_insn (gen_rtx (SET
, cmp_mode
,
2347 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2348 emit_insn (gen_rtx (SET
, op_mode
,
2350 gen_rtx (IF_THEN_ELSE
, op_mode
,
2351 gen_rtx (move_code
, VOIDmode
,
2353 CONST0_RTX (SImode
)),
2358 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2364 temp<last> = src[MAX_MOVE_REGS-1];
2368 dest[MAX_MOVE_REGS-1] = temp<last>;
2369 src += MAX_MOVE_REGS;
2370 dest += MAX_MOVE_REGS;
2371 } while (src != final);
2373 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2374 registers are needed.
2376 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2377 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2378 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2380 #define MAX_MOVE_REGS 4
2381 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2384 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2385 rtx dest_reg
; /* register holding destination address */
2386 rtx src_reg
; /* register holding source address */
2387 int bytes
; /* # bytes to move */
2388 int align
; /* alignment */
2389 rtx orig_dest
; /* original dest for change_address */
2390 rtx orig_src
; /* original source for making a reg note */
2392 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2393 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2394 rtx align_rtx
= GEN_INT (align
);
2400 if (bytes
< 2*MAX_MOVE_BYTES
)
2403 leftover
= bytes
% MAX_MOVE_BYTES
;
2406 label
= gen_label_rtx ();
2407 final_src
= gen_reg_rtx (Pmode
);
2408 bytes_rtx
= GEN_INT (bytes
);
2414 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2415 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2419 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2420 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2426 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2428 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2433 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2434 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2437 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2438 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2439 emit_insn (gen_cmpdi (src_reg
, final_src
));
2443 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2444 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2445 emit_insn (gen_cmpsi (src_reg
, final_src
));
2447 emit_jump_insn (gen_bne (label
));
2450 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2455 /* Use a library function to move some bytes. */
2458 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2463 /* We want to pass the size as Pmode, which will normally be SImode
2464 but will be DImode if we are using 64 bit longs and pointers. */
2465 if (GET_MODE (bytes_rtx
) != VOIDmode
2466 && GET_MODE (bytes_rtx
) != Pmode
)
2467 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2469 #ifdef TARGET_MEM_FUNCTIONS
2470 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2474 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2475 TREE_UNSIGNED (sizetype
)),
2476 TYPE_MODE (sizetype
));
2478 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2482 convert_to_mode (TYPE_MODE (integer_type_node
),
2484 TREE_UNSIGNED (integer_type_node
)),
2485 TYPE_MODE (integer_type_node
));
2490 /* Expand string/block move operations.
2492 operands[0] is the pointer to the destination.
2493 operands[1] is the pointer to the source.
2494 operands[2] is the number of bytes to move.
2495 operands[3] is the alignment. */
2498 expand_block_move (operands
)
2501 rtx bytes_rtx
= operands
[2];
2502 rtx align_rtx
= operands
[3];
2503 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2504 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2505 int align
= INTVAL (align_rtx
);
2506 rtx orig_src
= operands
[1];
2507 rtx orig_dest
= operands
[0];
2511 if (constp
&& bytes
<= 0)
2514 if (align
> UNITS_PER_WORD
)
2515 align
= UNITS_PER_WORD
;
2517 /* Move the address into scratch registers. */
2518 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2519 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2522 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2524 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2525 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2527 change_address (orig_src
, BLKmode
,
2529 bytes_rtx
, align_rtx
));
2531 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2532 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2534 else if (constp
&& optimize
)
2536 /* If the alignment is not word aligned, generate a test at
2537 runtime, to see whether things wound up aligned, and we
2538 can use the faster lw/sw instead ulw/usw. */
2540 rtx temp
= gen_reg_rtx (Pmode
);
2541 rtx aligned_label
= gen_label_rtx ();
2542 rtx join_label
= gen_label_rtx ();
2543 int leftover
= bytes
% MAX_MOVE_BYTES
;
2549 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2550 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2551 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2555 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2556 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2557 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2559 emit_jump_insn (gen_beq (aligned_label
));
2561 /* Unaligned loop. */
2562 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2563 emit_jump_insn (gen_jump (join_label
));
2567 emit_label (aligned_label
);
2568 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2570 emit_label (join_label
);
2572 /* Bytes at the end of the loop. */
2574 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2576 change_address (orig_src
, BLKmode
,
2583 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2587 /* Emit load/stores for a small constant block_move.
2589 operands[0] is the memory address of the destination.
2590 operands[1] is the memory address of the source.
2591 operands[2] is the number of bytes to move.
2592 operands[3] is the alignment.
2593 operands[4] is a temp register.
2594 operands[5] is a temp register.
2596 operands[3+num_regs] is the last temp register.
2598 The block move type can be one of the following:
2599 BLOCK_MOVE_NORMAL Do all of the block move.
2600 BLOCK_MOVE_NOT_LAST Do all but the last store.
2601 BLOCK_MOVE_LAST Do just the last store. */
2604 output_block_move (insn
, operands
, num_regs
, move_type
)
2608 enum block_move_type move_type
;
2610 rtx dest_reg
= XEXP (operands
[0], 0);
2611 rtx src_reg
= XEXP (operands
[1], 0);
2612 int bytes
= INTVAL (operands
[2]);
2613 int align
= INTVAL (operands
[3]);
2616 int use_lwl_lwr
= FALSE
;
2617 int last_operand
= num_regs
+4;
2623 char *load
; /* load insn without nop */
2624 char *load_nop
; /* load insn with trailing nop */
2625 char *store
; /* store insn */
2626 char *final
; /* if last_store used: NULL or swr */
2627 char *last_store
; /* last store instruction */
2628 int offset
; /* current offset */
2629 enum machine_mode mode
; /* mode to use on (MEM) */
2632 /* Detect a bug in GCC, where it can give us a register
2633 the same as one of the addressing registers and reduce
2634 the number of registers available. */
2636 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2639 if (!reg_mentioned_p (operands
[i
], operands
[0])
2640 && !reg_mentioned_p (operands
[i
], operands
[1]))
2642 xoperands
[safe_regs
++] = operands
[i
];
2645 if (safe_regs
< last_operand
)
2647 xoperands
[0] = operands
[0];
2648 xoperands
[1] = operands
[1];
2649 xoperands
[2] = operands
[2];
2650 xoperands
[3] = operands
[3];
2651 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2654 /* If we are given global or static addresses, and we would be
2655 emitting a few instructions, try to save time by using a
2656 temporary register for the pointer. */
2657 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2659 if (CONSTANT_P (src_reg
))
2662 mips_count_memory_refs (operands
[1], 1);
2664 src_reg
= operands
[ 3 + num_regs
-- ];
2665 if (move_type
!= BLOCK_MOVE_LAST
)
2667 xoperands
[1] = operands
[1];
2668 xoperands
[0] = src_reg
;
2669 if (Pmode
== DImode
)
2670 output_asm_insn ("dla\t%0,%1", xoperands
);
2672 output_asm_insn ("la\t%0,%1", xoperands
);
2676 if (CONSTANT_P (dest_reg
))
2679 mips_count_memory_refs (operands
[0], 1);
2681 dest_reg
= operands
[ 3 + num_regs
-- ];
2682 if (move_type
!= BLOCK_MOVE_LAST
)
2684 xoperands
[1] = operands
[0];
2685 xoperands
[0] = dest_reg
;
2686 if (Pmode
== DImode
)
2687 output_asm_insn ("dla\t%0,%1", xoperands
);
2689 output_asm_insn ("la\t%0,%1", xoperands
);
2694 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2695 are not offsettable, however, offsettable_address_p says they are
2696 offsettable. I think this is a bug in offsettable_address_p.
2697 For expediency, we fix this by just loading the address into a register
2698 if we happen to get one. */
2700 if (GET_CODE (src_reg
) == LO_SUM
)
2702 src_reg
= operands
[ 3 + num_regs
-- ];
2703 if (move_type
!= BLOCK_MOVE_LAST
)
2705 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2706 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2707 xoperands
[0] = src_reg
;
2708 if (Pmode
== DImode
)
2709 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2711 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2715 if (GET_CODE (dest_reg
) == LO_SUM
)
2717 dest_reg
= operands
[ 3 + num_regs
-- ];
2718 if (move_type
!= BLOCK_MOVE_LAST
)
2720 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2721 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2722 xoperands
[0] = dest_reg
;
2723 if (Pmode
== DImode
)
2724 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2726 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2730 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2731 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2733 else if (num_regs
< 1)
2734 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2738 load_store
[num
].offset
= offset
;
2740 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2742 load_store
[num
].load
= "ld\t%0,%1";
2743 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2744 load_store
[num
].store
= "sd\t%0,%1";
2745 load_store
[num
].last_store
= "sd\t%0,%1";
2746 load_store
[num
].final
= (char *)0;
2747 load_store
[num
].mode
= DImode
;
2752 /* ??? Fails because of a MIPS assembler bug? */
2753 else if (TARGET_64BIT
&& bytes
>= 8)
2755 if (BYTES_BIG_ENDIAN
)
2757 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2758 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2759 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2760 load_store
[num
].last_store
= "sdr\t%0,%2";
2761 load_store
[num
].final
= "sdl\t%0,%1";
2765 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2766 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2767 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2768 load_store
[num
].last_store
= "sdr\t%0,%1";
2769 load_store
[num
].final
= "sdl\t%0,%2";
2771 load_store
[num
].mode
= DImode
;
2777 else if (bytes
>= 4 && align
>= 4)
2779 load_store
[num
].load
= "lw\t%0,%1";
2780 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2781 load_store
[num
].store
= "sw\t%0,%1";
2782 load_store
[num
].last_store
= "sw\t%0,%1";
2783 load_store
[num
].final
= (char *)0;
2784 load_store
[num
].mode
= SImode
;
2789 else if (bytes
>= 4)
2791 if (BYTES_BIG_ENDIAN
)
2793 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2794 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2795 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2796 load_store
[num
].last_store
= "swr\t%0,%2";
2797 load_store
[num
].final
= "swl\t%0,%1";
2801 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2802 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2803 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2804 load_store
[num
].last_store
= "swr\t%0,%1";
2805 load_store
[num
].final
= "swl\t%0,%2";
2807 load_store
[num
].mode
= SImode
;
2813 else if (bytes
>= 2 && align
>= 2)
2815 load_store
[num
].load
= "lh\t%0,%1";
2816 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2817 load_store
[num
].store
= "sh\t%0,%1";
2818 load_store
[num
].last_store
= "sh\t%0,%1";
2819 load_store
[num
].final
= (char *)0;
2820 load_store
[num
].mode
= HImode
;
2827 load_store
[num
].load
= "lb\t%0,%1";
2828 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2829 load_store
[num
].store
= "sb\t%0,%1";
2830 load_store
[num
].last_store
= "sb\t%0,%1";
2831 load_store
[num
].final
= (char *)0;
2832 load_store
[num
].mode
= QImode
;
2837 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2839 dslots_load_total
++;
2840 dslots_load_filled
++;
2842 if (CONSTANT_P (src_reg
))
2843 mips_count_memory_refs (src_reg
, 1);
2845 if (CONSTANT_P (dest_reg
))
2846 mips_count_memory_refs (dest_reg
, 1);
2849 /* Emit load/stores now if we have run out of registers or are
2850 at the end of the move. */
2852 if (++num
== num_regs
|| bytes
== 0)
2854 /* If only load/store, we need a NOP after the load. */
2857 load_store
[0].load
= load_store
[0].load_nop
;
2858 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2859 dslots_load_filled
--;
2862 if (move_type
!= BLOCK_MOVE_LAST
)
2864 for (i
= 0; i
< num
; i
++)
2871 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2872 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2874 offset
= load_store
[i
].offset
;
2875 xoperands
[0] = operands
[i
+4];
2876 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2877 plus_constant (src_reg
, offset
));
2882 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2883 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2884 plus_constant (src_reg
,
2889 output_asm_insn (load_store
[i
].load
, xoperands
);
2893 for (i
= 0; i
< num
; i
++)
2895 int last_p
= (i
== num
-1 && bytes
== 0);
2896 int offset
= load_store
[i
].offset
;
2898 xoperands
[0] = operands
[i
+4];
2899 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2900 plus_constant (dest_reg
, offset
));
2906 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2907 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2908 plus_constant (dest_reg
,
2913 if (move_type
== BLOCK_MOVE_NORMAL
)
2914 output_asm_insn (load_store
[i
].store
, xoperands
);
2916 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2919 output_asm_insn (load_store
[i
].store
, xoperands
);
2921 else if (load_store
[i
].final
!= (char *)0)
2922 output_asm_insn (load_store
[i
].final
, xoperands
);
2926 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2929 num
= 0; /* reset load_store */
2930 use_lwl_lwr
= FALSE
;
2938 /* Argument support functions. */
2940 /* Initialize CUMULATIVE_ARGS for a function. */
2943 init_cumulative_args (cum
, fntype
, libname
)
2944 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2945 tree fntype
; /* tree ptr for function decl */
2946 rtx libname
; /* SYMBOL_REF of library name or 0 */
2948 static CUMULATIVE_ARGS zero_cum
;
2949 tree param
, next_param
;
2951 if (TARGET_DEBUG_E_MODE
)
2953 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2955 fputc ('\n', stderr
);
2959 tree ret_type
= TREE_TYPE (fntype
);
2960 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2961 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2962 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2968 /* Determine if this function has variable arguments. This is
2969 indicated by the last argument being 'void_type_mode' if there
2970 are no variable arguments. The standard MIPS calling sequence
2971 passes all arguments in the general purpose registers in this
2974 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2978 next_param
= TREE_CHAIN (param
);
2979 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2980 cum
->gp_reg_found
= 1;
2984 /* Advance the argument to the next argument position. */
2987 function_arg_advance (cum
, mode
, type
, named
)
2988 CUMULATIVE_ARGS
*cum
; /* current arg information */
2989 enum machine_mode mode
; /* current arg mode */
2990 tree type
; /* type of the argument or 0 if lib support */
2991 int named
; /* whether or not the argument was named */
2993 if (TARGET_DEBUG_E_MODE
)
2995 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2996 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3006 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3007 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3009 cum
->gp_reg_found
= 1;
3010 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3015 cum
->gp_reg_found
= 1;
3016 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3021 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3022 cum
->fp_arg_words
++;
3028 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3029 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3031 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3035 cum
->gp_reg_found
= 1;
3036 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3042 cum
->gp_reg_found
= 1;
3048 /* Return an RTL expression containing the register for the given mode,
3049 or 0 if the argument is to be passed on the stack. */
3052 function_arg (cum
, mode
, type
, named
)
3053 CUMULATIVE_ARGS
*cum
; /* current arg information */
3054 enum machine_mode mode
; /* current arg mode */
3055 tree type
; /* type of the argument or 0 if lib support */
3056 int named
; /* != 0 for normal args, == 0 for ... args */
3061 int *arg_words
= &cum
->arg_words
;
3062 int struct_p
= ((type
!= (tree
)0)
3063 && (TREE_CODE (type
) == RECORD_TYPE
3064 || TREE_CODE (type
) == UNION_TYPE
));
3066 if (TARGET_DEBUG_E_MODE
)
3068 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3069 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3072 cum
->last_arg_fp
= 0;
3076 if (mips_abi
== ABI_32
)
3078 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3079 regbase
= GP_ARG_FIRST
;
3082 regbase
= FP_ARG_FIRST
;
3083 /* If the first arg was a float in a floating point register,
3084 then set bias to align this float arg properly. */
3085 if (cum
->arg_words
== 1)
3089 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3092 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3093 cum
->last_arg_fp
= 1;
3094 arg_words
= &cum
->fp_arg_words
;
3095 regbase
= FP_ARG_FIRST
;
3098 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3104 if (mips_abi
== ABI_EABI
3105 && ! TARGET_SOFT_FLOAT
3106 && ! TARGET_SINGLE_FLOAT
)
3107 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3109 cum
->arg_words
+= cum
->arg_words
& 1;
3111 if (mips_abi
== ABI_32
)
3112 regbase
= ((cum
->gp_reg_found
3113 || TARGET_SOFT_FLOAT
3114 || TARGET_SINGLE_FLOAT
3115 || cum
->arg_number
>= 2)
3118 else if (mips_abi
== ABI_EABI
3119 && ! TARGET_SOFT_FLOAT
3120 && ! TARGET_SINGLE_FLOAT
)
3122 cum
->last_arg_fp
= 1;
3123 arg_words
= &cum
->fp_arg_words
;
3124 regbase
= FP_ARG_FIRST
;
3127 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3128 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3132 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3133 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3136 /* Drops through. */
3138 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3139 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3140 cum
->arg_words
+= (cum
->arg_words
& 1);
3141 regbase
= GP_ARG_FIRST
;
3148 regbase
= GP_ARG_FIRST
;
3153 cum
->arg_words
+= (cum
->arg_words
& 1);
3154 regbase
= GP_ARG_FIRST
;
3157 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3159 if (TARGET_DEBUG_E_MODE
)
3160 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3169 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3170 || mips_abi
== ABI_EABI
|| ! named
)
3171 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3174 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3175 structure contains a double in its entirety, then that 64 bit
3176 chunk is passed in a floating point register. */
3179 /* First check to see if there is any such field. */
3180 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3181 if (TREE_CODE (field
) == FIELD_DECL
3182 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3183 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3184 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3185 % BITS_PER_WORD
== 0))
3189 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3192 /* Now handle the special case by returning a PARALLEL
3193 indicating where each 64 bit chunk goes. */
3199 /* ??? If this is a packed structure, then the last hunk won't
3202 /* ??? If this is a structure with a single double field,
3203 it would be more convenient to return (REG:DI %fX) than
3204 a parallel. However, we would have to modify the mips
3205 backend to allow DImode values in fp registers. */
3207 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3208 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3209 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3211 /* assign_parms checks the mode of ENTRY_PARM, so we must
3212 use the actual mode here. */
3213 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3216 regno
= regbase
+ *arg_words
+ bias
;
3217 field
= TYPE_FIELDS (type
);
3218 for (i
= 0; i
< chunks
; i
++)
3222 for (; field
; field
= TREE_CHAIN (field
))
3223 if (TREE_CODE (field
) == FIELD_DECL
3224 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3229 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3230 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3231 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3232 reg
= gen_rtx (REG
, DFmode
,
3233 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3235 reg
= gen_rtx (REG
, word_mode
, regno
);
3237 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3238 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3246 if (TARGET_DEBUG_E_MODE
)
3247 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3248 struct_p
? ", [struct]" : "");
3250 /* The following is a hack in order to pass 1 byte structures
3251 the same way that the MIPS compiler does (namely by passing
3252 the structure in the high byte or half word of the register).
3253 This also makes varargs work. If we have such a structure,
3254 we save the adjustment RTL, and the call define expands will
3255 emit them. For the VOIDmode argument (argument after the
3256 last real argument), pass back a parallel vector holding each
3257 of the adjustments. */
3259 /* ??? function_arg can be called more than once for each argument.
3260 As a result, we compute more adjustments than we need here.
3261 See the CUMULATIVE_ARGS definition in mips.h. */
3263 /* ??? This scheme requires everything smaller than the word size to
3264 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3265 that would mean every int needs to be shifted left, which is very
3266 inefficient. Let's not carry this compatibility to the 64 bit
3267 calling convention for now. */
3269 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3270 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3272 rtx amount
= GEN_INT (BITS_PER_WORD
3273 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3274 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3276 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3278 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3282 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3283 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3290 function_arg_partial_nregs (cum
, mode
, type
, named
)
3291 CUMULATIVE_ARGS
*cum
; /* current arg information */
3292 enum machine_mode mode
; /* current arg mode */
3293 tree type
; /* type of the argument or 0 if lib support */
3294 int named
; /* != 0 for normal args, == 0 for ... args */
3296 if ((mode
== BLKmode
3297 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3298 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3299 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3300 && mips_abi
!= ABI_EABI
)
3303 if (mode
== BLKmode
)
3304 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3307 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3309 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3310 return 0; /* structure fits in registers */
3312 if (TARGET_DEBUG_E_MODE
)
3313 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3314 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3316 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3319 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3321 && mips_abi
!= ABI_EABI
)
3323 if (TARGET_DEBUG_E_MODE
)
3324 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3332 /* Abort after printing out a specific insn. */
3335 abort_with_insn (insn
, reason
)
3344 /* Write a message to stderr (for use in macros expanded in files that do not
3345 include stdio.h). */
3351 fprintf (stderr
, s
, s1
, s2
);
3361 fprintf (stderr
, "compiling '%s' in '%s'\n",
3362 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3363 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3366 #endif /* SIGINFO */
3369 /* Set up the threshold for data to go into the small data area, instead
3370 of the normal data area, and detect any conflicts in the switches. */
3375 register int i
, start
;
3377 register enum machine_mode mode
;
3379 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3381 if (mips_section_threshold
<= 0)
3382 target_flags
&= ~MASK_GPOPT
;
3384 target_flags
|= MASK_GPOPT
;
3386 /* Get the architectural level. */
3387 if (mips_isa_string
== (char *)0)
3389 #ifdef MIPS_ISA_DEFAULT
3390 mips_isa
= MIPS_ISA_DEFAULT
;
3396 else if (isdigit (*mips_isa_string
))
3398 mips_isa
= atoi (mips_isa_string
);
3399 if (mips_isa
< 1 || mips_isa
> 4)
3401 error ("-mips%d not supported", mips_isa
);
3408 error ("bad value (%s) for -mips switch", mips_isa_string
);
3412 #ifdef MIPS_ABI_DEFAULT
3413 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3414 if (mips_abi_string
== (char *) 0)
3415 mips_abi
= MIPS_ABI_DEFAULT
;
3416 else if (! strcmp (mips_abi_string
, "32")
3417 || ! strcmp (mips_abi_string
, "o32"))
3419 else if (! strcmp (mips_abi_string
, "n32"))
3421 else if (! strcmp (mips_abi_string
, "64")
3422 || ! strcmp (mips_abi_string
, "n64"))
3424 else if (! strcmp (mips_abi_string
, "eabi"))
3425 mips_abi
= ABI_EABI
;
3427 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3429 /* A specified ISA defaults the ABI if it was not specified. */
3430 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3437 /* A specified ABI defaults the ISA if it was not specified. */
3438 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3440 if (mips_abi
== ABI_32
)
3442 else if (mips_abi
== ABI_N32
)
3447 /* If both ABI and ISA were specified, check for conflicts. */
3448 else if (mips_isa_string
&& mips_abi_string
)
3450 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3451 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3452 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3455 /* Override TARGET_DEFAULT if necessary. */
3456 if (mips_abi
== ABI_32
)
3457 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3459 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */
3460 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3461 target_flags
|= MASK_LONG64
;
3463 /* ??? This doesn't work yet, so don't let people try to use it. */
3464 if (mips_abi
== ABI_32
)
3465 error ("The -mabi=32 support does not work yet.");
3467 if (mips_abi_string
)
3468 error ("This target does not support the -mabi switch.");
3471 #ifdef MIPS_CPU_STRING_DEFAULT
3472 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3473 greater than that supported by the default processor, then the user gets
3474 an error. Normally, the compiler will just default to the base level cpu
3475 for the indicated isa. */
3476 if (mips_cpu_string
== (char *)0)
3477 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3480 /* Identify the processor type */
3481 if (mips_cpu_string
== (char *)0
3482 || !strcmp (mips_cpu_string
, "default")
3483 || !strcmp (mips_cpu_string
, "DEFAULT"))
3488 mips_cpu_string
= "3000";
3489 mips_cpu
= PROCESSOR_R3000
;
3492 mips_cpu_string
= "6000";
3493 mips_cpu
= PROCESSOR_R6000
;
3496 mips_cpu_string
= "4000";
3497 mips_cpu
= PROCESSOR_R4000
;
3500 mips_cpu_string
= "8000";
3501 mips_cpu
= PROCESSOR_R8000
;
3508 char *p
= mips_cpu_string
;
3511 /* We need to cope with the various "vr" prefixes for the NEC 4300
3512 and 4100 processors. */
3513 if (*p
== 'v' || *p
== 'V')
3518 if (*p
== 'r' || *p
== 'R')
3521 /* Since there is no difference between a R2000 and R3000 in
3522 terms of the scheduler, we collapse them into just an R3000. */
3524 mips_cpu
= PROCESSOR_DEFAULT
;
3528 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3529 mips_cpu
= PROCESSOR_R3000
;
3533 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3534 mips_cpu
= PROCESSOR_R3000
;
3538 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3539 mips_cpu
= PROCESSOR_R4000
;
3540 /* The vr4100 is a non-FP ISA III processor with some extra
3542 else if (!strcmp (p
, "4100")) {
3543 mips_cpu
= PROCESSOR_R4100
;
3544 target_flags
|= MASK_SOFT_FLOAT
;
3546 /* The vr4300 is a standard ISA III processor, but with a different
3548 else if (!strcmp (p
, "4300"))
3549 mips_cpu
= PROCESSOR_R4300
;
3550 /* The r4400 is exactly the same as the r4000 from the compiler's
3552 else if (!strcmp (p
, "4400"))
3553 mips_cpu
= PROCESSOR_R4000
;
3554 else if (!strcmp (p
, "4600"))
3555 mips_cpu
= PROCESSOR_R4600
;
3556 else if (!strcmp (p
, "4650"))
3557 mips_cpu
= PROCESSOR_R4650
;
3561 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3562 mips_cpu
= PROCESSOR_R5000
;
3566 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3567 mips_cpu
= PROCESSOR_R6000
;
3571 if (!strcmp (p
, "8000"))
3572 mips_cpu
= PROCESSOR_R8000
;
3576 if (!strcmp (p
, "orion"))
3577 mips_cpu
= PROCESSOR_R4600
;
3582 && mips_cpu
!= PROCESSOR_R4300
3583 && mips_cpu
!= PROCESSOR_R4100
3584 && mips_cpu
!= PROCESSOR_R5000
)
3585 mips_cpu
= PROCESSOR_DEFAULT
;
3587 if (mips_cpu
== PROCESSOR_DEFAULT
)
3589 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3590 mips_cpu_string
= "default";
3594 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3595 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3596 || ((mips_cpu
== PROCESSOR_R4000
3597 || mips_cpu
== PROCESSOR_R4100
3598 || mips_cpu
== PROCESSOR_R4300
3599 || mips_cpu
== PROCESSOR_R4600
3600 || mips_cpu
== PROCESSOR_R4650
)
3602 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3604 /* make sure sizes of ints/longs/etc. are ok */
3608 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3610 else if (TARGET_LONG64
)
3611 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3613 else if (TARGET_FLOAT64
)
3614 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3616 else if (TARGET_64BIT
)
3617 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3620 if (mips_abi
!= ABI_32
)
3621 flag_pcc_struct_return
= 0;
3623 /* Tell halfpic.c that we have half-pic code if we do. */
3624 if (TARGET_HALF_PIC
)
3627 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3628 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3629 /* ??? -non_shared turns off pic code generation, but this is not
3631 if (TARGET_ABICALLS
)
3633 mips_abicalls
= MIPS_ABICALLS_YES
;
3635 if (mips_section_threshold
> 0)
3636 warning ("-G is incompatible with PIC code which is the default");
3639 mips_abicalls
= MIPS_ABICALLS_NO
;
3641 /* -membedded-pic is a form of PIC code suitable for embedded
3642 systems. All calls are made using PC relative addressing, and
3643 all data is addressed using the $gp register. This requires gas,
3644 which does most of the work, and GNU ld, which automatically
3645 expands PC relative calls which are out of range into a longer
3646 instruction sequence. All gcc really does differently is
3647 generate a different sequence for a switch. */
3648 if (TARGET_EMBEDDED_PIC
)
3651 if (TARGET_ABICALLS
)
3652 warning ("-membedded-pic and -mabicalls are incompatible");
3654 warning ("-G and -membedded-pic are incompatible");
3655 /* Setting mips_section_threshold is not required, because gas
3656 will force everything to be GP addressable anyhow, but
3657 setting it will cause gcc to make better estimates of the
3658 number of instructions required to access a particular data
3660 mips_section_threshold
= 0x7fffffff;
3663 /* ??? This does not work when target addresses are DImode.
3664 This is because we are missing DImode high/lo_sum patterns. */
3666 if (TARGET_GAS
&& optimize
&& ! flag_pic
&& Pmode
== SImode
)
3667 mips_split_addresses
= 1;
3669 mips_split_addresses
= 0;
3671 /* -mrnames says to use the MIPS software convention for register
3672 names instead of the hardware names (ie, $a0 instead of $4).
3673 We do this by switching the names in mips_reg_names, which the
3674 reg_names points into via the REGISTER_NAMES macro. */
3676 if (TARGET_NAME_REGS
)
3677 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3679 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3680 is currently being compiled. */
3682 if (getenv ("GCC_SIGINFO") != (char *)0)
3684 struct sigaction action
;
3685 action
.sa_handler
= siginfo
;
3687 action
.sa_flags
= SA_RESTART
;
3688 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3693 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3694 /* If -mstats and -quiet, make stderr line buffered. */
3695 if (quiet_flag
&& TARGET_STATS
)
3696 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3700 /* Initialize the high and low values for legitimate floating point
3701 constants. Rather than trying to get the accuracy down to the
3702 last bit, just use approximate ranges. */
3703 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3704 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3705 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3706 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3708 mips_print_operand_punct
['?'] = TRUE
;
3709 mips_print_operand_punct
['#'] = TRUE
;
3710 mips_print_operand_punct
['&'] = TRUE
;
3711 mips_print_operand_punct
['!'] = TRUE
;
3712 mips_print_operand_punct
['*'] = TRUE
;
3713 mips_print_operand_punct
['@'] = TRUE
;
3714 mips_print_operand_punct
['.'] = TRUE
;
3715 mips_print_operand_punct
['('] = TRUE
;
3716 mips_print_operand_punct
[')'] = TRUE
;
3717 mips_print_operand_punct
['['] = TRUE
;
3718 mips_print_operand_punct
[']'] = TRUE
;
3719 mips_print_operand_punct
['<'] = TRUE
;
3720 mips_print_operand_punct
['>'] = TRUE
;
3721 mips_print_operand_punct
['{'] = TRUE
;
3722 mips_print_operand_punct
['}'] = TRUE
;
3723 mips_print_operand_punct
['^'] = TRUE
;
3725 mips_char_to_class
['d'] = GR_REGS
;
3726 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3727 mips_char_to_class
['h'] = HI_REG
;
3728 mips_char_to_class
['l'] = LO_REG
;
3729 mips_char_to_class
['a'] = HILO_REG
;
3730 mips_char_to_class
['x'] = MD_REGS
;
3731 mips_char_to_class
['b'] = ALL_REGS
;
3732 mips_char_to_class
['y'] = GR_REGS
;
3733 mips_char_to_class
['z'] = ST_REGS
;
3735 /* Set up array to map GCC register number to debug register number.
3736 Ignore the special purpose register numbers. */
3738 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3739 mips_dbx_regno
[i
] = -1;
3741 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3742 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3743 mips_dbx_regno
[i
] = i
+ start
;
3745 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3746 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3747 mips_dbx_regno
[i
] = i
+ start
;
3749 /* Set up array giving whether a given register can hold a given mode.
3750 At present, restrict ints from being in FP registers, because reload
3751 is a little enthusiastic about storing extra values in FP registers,
3752 and this is not good for things like OS kernels. Also, due to the
3753 mandatory delay, it is as fast to load from cached memory as to move
3754 from the FP register. */
3756 for (mode
= VOIDmode
;
3757 mode
!= MAX_MACHINE_MODE
;
3758 mode
= (enum machine_mode
)((int)mode
+ 1))
3760 register int size
= GET_MODE_SIZE (mode
);
3761 register enum mode_class
class = GET_MODE_CLASS (mode
);
3763 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3770 temp
= (regno
== FPSW_REGNUM
);
3772 temp
= (ST_REG_P (regno
)
3774 || FP_REG_P (regno
));
3777 else if (GP_REG_P (regno
))
3778 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3780 else if (FP_REG_P (regno
))
3781 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3782 && (class == MODE_FLOAT
3783 || class == MODE_COMPLEX_FLOAT
3784 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3785 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3787 else if (MD_REG_P (regno
))
3788 temp
= (class == MODE_INT
3789 && (size
<= UNITS_PER_WORD
3790 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3795 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3802 * The MIPS debug format wants all automatic variables and arguments
3803 * to be in terms of the virtual frame pointer (stack pointer before
3804 * any adjustment in the function), while the MIPS 3.0 linker wants
3805 * the frame pointer to be the stack pointer after the initial
3806 * adjustment. So, we do the adjustment here. The arg pointer (which
3807 * is eliminated) points to the virtual frame pointer, while the frame
3808 * pointer (which may be eliminated) points to the stack pointer after
3809 * the initial adjustments.
3813 mips_debugger_offset (addr
, offset
)
3817 rtx offset2
= const0_rtx
;
3818 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3821 offset
= INTVAL (offset2
);
3823 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3825 int frame_size
= (!current_frame_info
.initialized
)
3826 ? compute_frame_size (get_frame_size ())
3827 : current_frame_info
.total_size
;
3829 offset
= offset
- frame_size
;
3831 /* sdbout_parms does not want this to crash for unrecognized cases. */
3833 else if (reg
!= arg_pointer_rtx
)
3834 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3841 /* A C compound statement to output to stdio stream STREAM the
3842 assembler syntax for an instruction operand X. X is an RTL
3845 CODE is a value that can be used to specify one of several ways
3846 of printing the operand. It is used when identical operands
3847 must be printed differently depending on the context. CODE
3848 comes from the `%' specification that was used to request
3849 printing of the operand. If the specification was just `%DIGIT'
3850 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3851 is the ASCII code for LTR.
3853 If X is a register, this macro should print the register's name.
3854 The names can be found in an array `reg_names' whose type is
3855 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3857 When the machine description has a specification `%PUNCT' (a `%'
3858 followed by a punctuation character), this macro is called with
3859 a null pointer for X and the punctuation character for CODE.
3861 The MIPS specific codes are:
3863 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3864 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3865 'd' output integer constant in decimal,
3866 'z' if the operand is 0, use $0 instead of normal operand.
3867 'D' print second register of double-word register operand.
3868 'L' print low-order register of double-word register operand.
3869 'M' print high-order register of double-word register operand.
3870 'C' print part of opcode for a branch condition.
3871 'N' print part of opcode for a branch condition, inverted.
3872 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3873 'B' print 'z' for EQ, 'n' for NE
3874 'b' print 'n' for EQ, 'z' for NE
3875 'T' print 'f' for EQ, 't' for NE
3876 't' print 't' for EQ, 'f' for NE
3877 'Z' print register and a comma, but print nothing for $fcc0
3878 '(' Turn on .set noreorder
3879 ')' Turn on .set reorder
3880 '[' Turn on .set noat
3882 '<' Turn on .set nomacro
3883 '>' Turn on .set macro
3884 '{' Turn on .set volatile (not GAS)
3885 '}' Turn on .set novolatile (not GAS)
3886 '&' Turn on .set noreorder if filling delay slots
3887 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3888 '!' Turn on .set nomacro if filling delay slots
3889 '#' Print nop if in a .set noreorder section.
3890 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3891 '@' Print the name of the assembler temporary register (at or $1).
3892 '.' Print the name of the register with a hard-wired zero (zero or $0).
3893 '^' Print the name of the pic call-through register (t9 or $25). */
3896 print_operand (file
, op
, letter
)
3897 FILE *file
; /* file to write to */
3898 rtx op
; /* operand to print */
3899 int letter
; /* %<letter> or 0 */
3901 register enum rtx_code code
;
3903 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3908 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3912 if (mips_branch_likely
)
3917 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3921 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3925 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3929 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3930 fputs (".set\tnoreorder\n\t", file
);
3934 if (final_sequence
!= 0)
3936 if (set_noreorder
++ == 0)
3937 fputs (".set\tnoreorder\n\t", file
);
3939 if (set_nomacro
++ == 0)
3940 fputs (".set\tnomacro\n\t", file
);
3945 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3946 fputs ("\n\t.set\tnomacro", file
);
3950 if (set_noreorder
!= 0)
3951 fputs ("\n\tnop", file
);
3953 else if (TARGET_STATS
)
3954 fputs ("\n\t#nop", file
);
3959 if (set_noreorder
++ == 0)
3960 fputs (".set\tnoreorder\n\t", file
);
3964 if (set_noreorder
== 0)
3965 error ("internal error: %%) found without a %%( in assembler pattern");
3967 else if (--set_noreorder
== 0)
3968 fputs ("\n\t.set\treorder", file
);
3973 if (set_noat
++ == 0)
3974 fputs (".set\tnoat\n\t", file
);
3979 error ("internal error: %%] found without a %%[ in assembler pattern");
3981 else if (--set_noat
== 0)
3982 fputs ("\n\t.set\tat", file
);
3987 if (set_nomacro
++ == 0)
3988 fputs (".set\tnomacro\n\t", file
);
3992 if (set_nomacro
== 0)
3993 error ("internal error: %%> found without a %%< in assembler pattern");
3995 else if (--set_nomacro
== 0)
3996 fputs ("\n\t.set\tmacro", file
);
4001 if (set_volatile
++ == 0)
4002 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4006 if (set_volatile
== 0)
4007 error ("internal error: %%} found without a %%{ in assembler pattern");
4009 else if (--set_volatile
== 0)
4010 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4019 error ("PRINT_OPERAND null pointer");
4023 code
= GET_CODE (op
);
4025 if (code
== SIGN_EXTEND
)
4028 code
= GET_CODE (op
);
4034 case EQ
: fputs ("eq", file
); break;
4035 case NE
: fputs ("ne", file
); break;
4036 case GT
: fputs ("gt", file
); break;
4037 case GE
: fputs ("ge", file
); break;
4038 case LT
: fputs ("lt", file
); break;
4039 case LE
: fputs ("le", file
); break;
4040 case GTU
: fputs ("gtu", file
); break;
4041 case GEU
: fputs ("geu", file
); break;
4042 case LTU
: fputs ("ltu", file
); break;
4043 case LEU
: fputs ("leu", file
); break;
4046 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4049 else if (letter
== 'N')
4052 case EQ
: fputs ("ne", file
); break;
4053 case NE
: fputs ("eq", file
); break;
4054 case GT
: fputs ("le", file
); break;
4055 case GE
: fputs ("lt", file
); break;
4056 case LT
: fputs ("ge", file
); break;
4057 case LE
: fputs ("gt", file
); break;
4058 case GTU
: fputs ("leu", file
); break;
4059 case GEU
: fputs ("ltu", file
); break;
4060 case LTU
: fputs ("geu", file
); break;
4061 case LEU
: fputs ("gtu", file
); break;
4064 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4067 else if (letter
== 'S')
4071 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4072 assemble_name (file
, buffer
);
4075 else if (letter
== 'Z')
4077 register int regnum
;
4081 regnum
= REGNO (op
);
4082 if (! ST_REG_P (regnum
))
4084 if (regnum
!= ST_REG_FIRST
)
4085 fprintf (file
, "%s,", reg_names
[regnum
]);
4088 else if (code
== REG
|| code
== SUBREG
)
4090 register int regnum
;
4093 regnum
= REGNO (op
);
4095 regnum
= true_regnum (op
);
4097 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4098 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4102 fprintf (file
, "%s", reg_names
[regnum
]);
4105 else if (code
== MEM
)
4106 output_address (XEXP (op
, 0));
4108 else if (code
== CONST_DOUBLE
4109 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4114 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4115 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4119 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4120 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4122 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4123 && HOST_BITS_PER_WIDE_INT
== 32)
4124 fprintf (file
, "0x%08x", INTVAL(op
));
4126 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4127 && HOST_BITS_PER_WIDE_INT
== 64)
4128 fprintf (file
, "0x%016lx", INTVAL(op
));
4130 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4131 fprintf (file
, "%d", (INTVAL(op
)));
4133 else if (letter
== 'z'
4134 && (GET_CODE (op
) == CONST_INT
)
4135 && INTVAL (op
) == 0)
4136 fputs (reg_names
[GP_REG_FIRST
], file
);
4138 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4139 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4141 else if (letter
== 'B')
4142 fputs (code
== EQ
? "z" : "n", file
);
4143 else if (letter
== 'b')
4144 fputs (code
== EQ
? "n" : "z", file
);
4145 else if (letter
== 'T')
4146 fputs (code
== EQ
? "f" : "t", file
);
4147 else if (letter
== 't')
4148 fputs (code
== EQ
? "t" : "f", file
);
4151 output_addr_const (file
, op
);
4155 /* A C compound statement to output to stdio stream STREAM the
4156 assembler syntax for an instruction operand that is a memory
4157 reference whose address is ADDR. ADDR is an RTL expression.
4159 On some machines, the syntax for a symbolic address depends on
4160 the section that the address refers to. On these machines,
4161 define the macro `ENCODE_SECTION_INFO' to store the information
4162 into the `symbol_ref', and then check for it here. */
4165 print_operand_address (file
, addr
)
4170 error ("PRINT_OPERAND_ADDRESS, null pointer");
4173 switch (GET_CODE (addr
))
4176 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4180 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4181 abort_with_insn (addr
, "Arg pointer not eliminated.");
4183 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4188 register rtx arg0
= XEXP (addr
, 0);
4189 register rtx arg1
= XEXP (addr
, 1);
4191 if (! mips_split_addresses
)
4192 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4194 if (GET_CODE (arg0
) != REG
)
4195 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4197 fprintf (file
, "%%lo(");
4198 print_operand_address (file
, arg1
);
4199 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4205 register rtx reg
= (rtx
)0;
4206 register rtx offset
= (rtx
)0;
4207 register rtx arg0
= XEXP (addr
, 0);
4208 register rtx arg1
= XEXP (addr
, 1);
4210 if (GET_CODE (arg0
) == REG
)
4214 if (GET_CODE (offset
) == REG
)
4215 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4217 else if (GET_CODE (arg1
) == REG
)
4222 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4224 output_addr_const (file
, addr
);
4228 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4230 if (!CONSTANT_P (offset
))
4231 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4233 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4234 abort_with_insn (addr
, "Arg pointer not eliminated.");
4236 output_addr_const (file
, offset
);
4237 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4245 output_addr_const (file
, addr
);
4251 /* If optimizing for the global pointer, keep track of all of
4252 the externs, so that at the end of the file, we can emit
4253 the appropriate .extern declaration for them, before writing
4254 out the text section. We assume that all names passed to
4255 us are in the permanent obstack, so that they will be valid
4256 at the end of the compilation.
4258 If we have -G 0, or the extern size is unknown, don't bother
4259 emitting the .externs. */
4262 mips_output_external (file
, decl
, name
)
4267 register struct extern_list
*p
;
4271 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4272 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4274 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4275 p
->next
= extern_head
;
4281 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4282 if (TREE_CODE (decl
) == FUNCTION_DECL
4283 /* ??? Don't include alloca, since gcc will always expand it
4284 inline. If we don't do this, libg++ fails to build. */
4285 && strcmp (name
, "alloca")
4286 /* ??? Don't include __builtin_next_arg, because then gcc will not
4287 bootstrap under Irix 5.1. */
4288 && strcmp (name
, "__builtin_next_arg"))
4290 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4291 p
->next
= extern_head
;
4301 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4303 mips_output_external_libcall (file
, name
)
4307 register struct extern_list
*p
;
4309 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4310 p
->next
= extern_head
;
4320 /* Compute a string to use as a temporary file name. */
4322 /* On MSDOS, write temp files in current dir
4323 because there's no place else we can expect to use. */
4326 #define P_tmpdir "./"
4334 char *base
= getenv ("TMPDIR");
4337 if (base
== (char *)0)
4340 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4344 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4350 len
= strlen (base
);
4351 /* temp_filename is global, so we must use malloc, not alloca. */
4352 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4353 strcpy (temp_filename
, base
);
4354 if (len
> 0 && temp_filename
[len
-1] != '/')
4355 temp_filename
[len
++] = '/';
4357 strcpy (temp_filename
+ len
, "ctXXXXXX");
4358 mktemp (temp_filename
);
4360 stream
= fopen (temp_filename
, "w+");
4362 pfatal_with_name (temp_filename
);
4365 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4366 it. Otherwise, we delete it now, so that it will be gone even if the
4367 compiler happens to crash. */
4368 unlink (temp_filename
);
4374 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4375 for .file's that start within a function. If we are smuggling stabs, try to
4376 put out a MIPS ECOFF file and a stab. */
4379 mips_output_filename (stream
, name
)
4383 static int first_time
= TRUE
;
4384 char ltext_label_name
[100];
4390 current_function_file
= name
;
4391 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4392 /* This tells mips-tfile that stabs will follow. */
4393 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4394 fprintf (stream
, "\t#@stabs\n");
4397 else if (write_symbols
== DBX_DEBUG
)
4399 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4400 fprintf (stream
, "%s ", ASM_STABS_OP
);
4401 output_quoted_string (stream
, name
);
4402 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4405 else if (name
!= current_function_file
4406 && strcmp (name
, current_function_file
) != 0)
4408 if (inside_function
&& !TARGET_GAS
)
4410 if (!file_in_function_warning
)
4412 file_in_function_warning
= TRUE
;
4413 ignore_line_number
= TRUE
;
4414 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4420 current_function_file
= name
;
4421 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4427 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4428 as well as a .loc, since it is possible that MIPS ECOFF might not be
4429 able to represent the location for inlines that come from a different
4433 mips_output_lineno (stream
, line
)
4437 if (write_symbols
== DBX_DEBUG
)
4440 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4441 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4442 LOCAL_LABEL_PREFIX
, sym_lineno
);
4447 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4448 (ignore_line_number
) ? "#" : "",
4449 num_source_filenames
, line
);
4451 LABEL_AFTER_LOC (stream
);
4456 /* If defined, a C statement to be executed just prior to the
4457 output of assembler code for INSN, to modify the extracted
4458 operands so they will be output differently.
4460 Here the argument OPVEC is the vector containing the operands
4461 extracted from INSN, and NOPERANDS is the number of elements of
4462 the vector which contain meaningful data for this insn. The
4463 contents of this vector are what will be used to convert the
4464 insn template into assembler code, so you can change the
4465 assembler output by changing the contents of the vector.
4467 We use it to check if the current insn needs a nop in front of it
4468 because of load delays, and also to update the delay slot
4471 /* ??? There is no real need for this function, because it never actually
4472 emits a NOP anymore. */
4475 final_prescan_insn (insn
, opvec
, noperands
)
4480 if (dslots_number_nops
> 0)
4482 rtx pattern
= PATTERN (insn
);
4483 int length
= get_attr_length (insn
);
4485 /* Do we need to emit a NOP? */
4487 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4488 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4489 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4490 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4491 fputs ("\t#nop\n", asm_out_file
);
4494 dslots_load_filled
++;
4496 while (--dslots_number_nops
> 0)
4497 fputs ("\t#nop\n", asm_out_file
);
4499 mips_load_reg
= (rtx
)0;
4500 mips_load_reg2
= (rtx
)0;
4501 mips_load_reg3
= (rtx
)0;
4502 mips_load_reg4
= (rtx
)0;
4507 enum rtx_code code
= GET_CODE (insn
);
4508 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4509 dslots_jump_total
++;
4514 /* Output at beginning of assembler file.
4515 If we are optimizing to use the global pointer, create a temporary
4516 file to hold all of the text stuff, and write it out to the end.
4517 This is needed because the MIPS assembler is evidently one pass,
4518 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4519 declaration when the code is processed, it generates a two
4520 instruction sequence. */
4523 mips_asm_file_start (stream
)
4526 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4528 /* Versions of the MIPS assembler before 2.20 generate errors
4529 if a branch inside of a .set noreorder section jumps to a
4530 label outside of the .set noreorder section. Revision 2.20
4531 just set nobopt silently rather than fixing the bug. */
4533 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4534 fprintf (stream
, "\t.set\tnobopt\n");
4536 /* Generate the pseudo ops that System V.4 wants. */
4537 #ifndef ABICALLS_ASM_OP
4538 #define ABICALLS_ASM_OP ".abicalls"
4540 if (TARGET_ABICALLS
)
4541 /* ??? but do not want this (or want pic0) if -non-shared? */
4542 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4544 /* Start a section, so that the first .popsection directive is guaranteed
4545 to have a previously defined section to pop back to. */
4546 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4547 fprintf (stream
, "\t.section\t.text\n");
4549 /* This code exists so that we can put all externs before all symbol
4550 references. This is necessary for the assembler's global pointer
4551 optimizations to work. */
4552 /* ??? Current versions of gas do not require that externs occur before
4553 symbol references. This means that this code is unnecessary when
4554 gas is being used. This gas feature hasn't been well tested as yet
4558 asm_out_data_file
= stream
;
4559 asm_out_text_file
= make_temp_file ();
4562 asm_out_data_file
= asm_out_text_file
= stream
;
4564 if (flag_verbose_asm
)
4565 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4567 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4571 /* If we are optimizing the global pointer, emit the text section now
4572 and any small externs which did not have .comm, etc that are
4573 needed. Also, give a warning if the data area is more than 32K and
4574 -pic because 3 instructions are needed to reference the data
4578 mips_asm_file_end (file
)
4583 struct extern_list
*p
;
4587 HALF_PIC_FINISH (file
);
4593 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4595 name_tree
= get_identifier (p
->name
);
4597 /* Positively ensure only one .extern for any given symbol. */
4598 if (! TREE_ASM_WRITTEN (name_tree
))
4600 TREE_ASM_WRITTEN (name_tree
) = 1;
4601 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4603 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4607 fputs ("\t.extern\t", file
);
4608 assemble_name (file
, p
->name
);
4609 fprintf (file
, ", %d\n", p
->size
);
4617 fprintf (file
, "\n\t.text\n");
4618 rewind (asm_out_text_file
);
4619 if (ferror (asm_out_text_file
))
4620 fatal_io_error (temp_filename
);
4622 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4623 if (fwrite (buffer
, 1, len
, file
) != len
)
4624 pfatal_with_name (asm_file_name
);
4627 pfatal_with_name (temp_filename
);
4629 if (fclose (asm_out_text_file
) != 0)
4630 pfatal_with_name (temp_filename
);
4633 unlink (temp_filename
);
4639 /* Emit either a label, .comm, or .lcomm directive, and mark
4640 that the symbol is used, so that we don't emit an .extern
4641 for it in mips_asm_file_end. */
4644 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4651 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4652 assemble_name (stream
, name
);
4653 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4657 tree name_tree
= get_identifier (name
);
4658 TREE_ASM_WRITTEN (name_tree
) = 1;
4663 /* Output a double precision value to the assembler. If both the
4664 host and target are IEEE, emit the values in hex. */
4667 mips_output_double (stream
, value
)
4669 REAL_VALUE_TYPE value
;
4671 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4673 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4675 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4676 value_long
[0], value
, value_long
[1]);
4678 fprintf (stream
, "\t.double\t%.20g\n", value
);
4683 /* Output a single precision value to the assembler. If both the
4684 host and target are IEEE, emit the values in hex. */
4687 mips_output_float (stream
, value
)
4689 REAL_VALUE_TYPE value
;
4691 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4693 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4695 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4697 fprintf (stream
, "\t.float\t%.12g\n", value
);
4702 /* Return TRUE if any register used in the epilogue is used. This to insure
4703 any insn put into the epilogue delay slots is safe. */
4706 epilogue_reg_mentioned_p (insn
)
4711 register enum rtx_code code
;
4717 if (GET_CODE (insn
) == LABEL_REF
)
4720 code
= GET_CODE (insn
);
4724 regno
= REGNO (insn
);
4725 if (regno
== STACK_POINTER_REGNUM
)
4728 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4731 if (!call_used_regs
[regno
])
4734 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4737 if (!current_frame_info
.initialized
)
4738 compute_frame_size (get_frame_size ());
4740 return (current_frame_info
.total_size
>= 32768);
4750 fmt
= GET_RTX_FORMAT (code
);
4751 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4756 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4757 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4760 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4767 /* Return the bytes needed to compute the frame pointer from the current
4770 Mips stack frames look like:
4772 Before call After call
4773 +-----------------------+ +-----------------------+
4776 | caller's temps. | | caller's temps. |
4778 +-----------------------+ +-----------------------+
4780 | arguments on stack. | | arguments on stack. |
4782 +-----------------------+ +-----------------------+
4783 | 4 words to save | | 4 words to save |
4784 | arguments passed | | arguments passed |
4785 | in registers, even | | in registers, even |
4786 SP->| if not passed. | VFP->| if not passed. |
4787 +-----------------------+ +-----------------------+
4789 | fp register save |
4791 +-----------------------+
4793 | gp register save |
4795 +-----------------------+
4799 +-----------------------+
4801 | alloca allocations |
4803 +-----------------------+
4805 | GP save for V.4 abi |
4807 +-----------------------+
4809 | arguments on stack |
4811 +-----------------------+
4813 | arguments passed |
4814 | in registers, even |
4815 low SP->| if not passed. |
4816 memory +-----------------------+
4821 compute_frame_size (size
)
4822 int size
; /* # of var. bytes allocated */
4825 long total_size
; /* # bytes that the entire frame takes up */
4826 long var_size
; /* # bytes that variables take up */
4827 long args_size
; /* # bytes that outgoing arguments take up */
4828 long extra_size
; /* # extra bytes */
4829 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4830 long gp_reg_size
; /* # bytes needed to store gp regs */
4831 long fp_reg_size
; /* # bytes needed to store fp regs */
4832 long mask
; /* mask of saved gp registers */
4833 long fmask
; /* mask of saved fp registers */
4834 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4835 long fp_bits
; /* bitmask to use for each fp register */
4841 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4842 var_size
= MIPS_STACK_ALIGN (size
);
4843 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4845 /* The MIPS 3.0 linker does not like functions that dynamically
4846 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4847 looks like we are trying to create a second frame pointer to the
4848 function, so allocate some stack space to make it happy. */
4850 if (args_size
== 0 && current_function_calls_alloca
)
4851 args_size
= 4*UNITS_PER_WORD
;
4853 total_size
= var_size
+ args_size
+ extra_size
;
4855 /* Calculate space needed for gp registers. */
4856 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4858 if (MUST_SAVE_REGISTER (regno
))
4860 gp_reg_size
+= UNITS_PER_WORD
;
4861 mask
|= 1L << (regno
- GP_REG_FIRST
);
4865 /* Calculate space needed for fp registers. */
4866 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4877 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4879 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4881 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4882 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4886 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4887 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4889 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4890 for leaf routines (total_size == extra_size) to save the gp reg.
4891 The gp reg is callee saved in the 64 bit ABI, so all routines must
4893 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
))
4894 total_size
= extra_size
= 0;
4895 else if (TARGET_ABICALLS
)
4897 /* Add the context-pointer to the saved registers. */
4898 gp_reg_size
+= UNITS_PER_WORD
;
4899 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4900 total_size
-= gp_reg_rounded
;
4901 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4902 total_size
+= gp_reg_rounded
;
4905 /* Add in space reserved on the stack by the callee for storing arguments
4906 passed in registers. */
4907 if (mips_abi
!= ABI_32
)
4908 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4910 /* Save other computed information. */
4911 current_frame_info
.total_size
= total_size
;
4912 current_frame_info
.var_size
= var_size
;
4913 current_frame_info
.args_size
= args_size
;
4914 current_frame_info
.extra_size
= extra_size
;
4915 current_frame_info
.gp_reg_size
= gp_reg_size
;
4916 current_frame_info
.fp_reg_size
= fp_reg_size
;
4917 current_frame_info
.mask
= mask
;
4918 current_frame_info
.fmask
= fmask
;
4919 current_frame_info
.initialized
= reload_completed
;
4920 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4921 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4925 unsigned long offset
= (args_size
+ extra_size
+ var_size
4926 + gp_reg_size
- UNITS_PER_WORD
);
4927 current_frame_info
.gp_sp_offset
= offset
;
4928 current_frame_info
.gp_save_offset
= offset
- total_size
;
4932 current_frame_info
.gp_sp_offset
= 0;
4933 current_frame_info
.gp_save_offset
= 0;
4939 unsigned long offset
= (args_size
+ extra_size
+ var_size
4940 + gp_reg_rounded
+ fp_reg_size
4941 - fp_inc
* UNITS_PER_FPREG
);
4942 current_frame_info
.fp_sp_offset
= offset
;
4943 current_frame_info
.fp_save_offset
= offset
- total_size
;
4947 current_frame_info
.fp_sp_offset
= 0;
4948 current_frame_info
.fp_save_offset
= 0;
4951 /* Ok, we're done. */
4956 /* Common code to emit the insns (or to write the instructions to a file)
4957 to save/restore registers.
4959 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4960 is not modified within save_restore_insns. */
4962 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4965 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4966 int store_p
; /* true if this is prologue */
4967 rtx large_reg
; /* register holding large offset constant or NULL */
4968 long large_offset
; /* large constant offset value */
4969 FILE *file
; /* file to write instructions to instead of making RTL */
4971 long mask
= current_frame_info
.mask
;
4972 long fmask
= current_frame_info
.fmask
;
4981 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4984 if (mask
== 0 && fmask
== 0)
4987 /* Save registers starting from high to low. The debuggers prefer
4988 at least the return register be stored at func+4, and also it
4989 allows us not to need a nop in the epilog if at least one
4990 register is reloaded in addition to return address. */
4992 /* Save GP registers if needed. */
4995 /* Pick which pointer to use as a base register. For small
4996 frames, just use the stack pointer. Otherwise, use a
4997 temporary register. Save 2 cycles if the save area is near
4998 the end of a large frame, by reusing the constant created in
4999 the prologue/epilogue to adjust the stack frame. */
5001 gp_offset
= current_frame_info
.gp_sp_offset
;
5002 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
5004 if (gp_offset
< 0 || end_offset
< 0)
5005 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5006 gp_offset
, end_offset
);
5008 else if (gp_offset
< 32768)
5010 base_reg_rtx
= stack_pointer_rtx
;
5014 else if (large_reg
!= (rtx
)0
5015 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
5016 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5018 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5019 base_offset
= large_offset
;
5020 if (file
== (FILE *)0)
5023 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5025 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5026 RTX_FRAME_RELATED_P (insn
) = 1;
5029 fprintf (file
, "\t%s\t%s,%s,%s\n",
5030 TARGET_LONG64
? "daddu" : "addu",
5031 reg_names
[MIPS_TEMP2_REGNUM
],
5032 reg_names
[REGNO (large_reg
)],
5033 reg_names
[STACK_POINTER_REGNUM
]);
5038 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5039 base_offset
= gp_offset
;
5040 if (file
== (FILE *)0)
5042 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
5043 RTX_FRAME_RELATED_P (insn
) = 1;
5045 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5047 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5048 RTX_FRAME_RELATED_P (insn
) = 1;
5051 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5052 reg_names
[MIPS_TEMP2_REGNUM
],
5055 TARGET_LONG64
? "daddu" : "addu",
5056 reg_names
[MIPS_TEMP2_REGNUM
],
5057 reg_names
[MIPS_TEMP2_REGNUM
],
5058 reg_names
[STACK_POINTER_REGNUM
]);
5061 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5063 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5065 if (file
== (FILE *)0)
5067 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5068 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5069 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5070 GEN_INT (gp_offset
- base_offset
)));
5074 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5075 RTX_FRAME_RELATED_P (insn
) = 1;
5077 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5078 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5079 emit_move_insn (reg_rtx
, mem_rtx
);
5083 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5084 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5085 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5087 ? (store_p
) ? "sd" : "ld"
5088 : (store_p
) ? "sw" : "lw"),
5090 gp_offset
- base_offset
,
5091 reg_names
[REGNO(base_reg_rtx
)]);
5094 gp_offset
-= UNITS_PER_WORD
;
5100 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5104 /* Save floating point registers if needed. */
5107 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5108 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5110 /* Pick which pointer to use as a base register. */
5111 fp_offset
= current_frame_info
.fp_sp_offset
;
5112 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5114 if (fp_offset
< 0 || end_offset
< 0)
5115 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5116 fp_offset
, end_offset
);
5118 else if (fp_offset
< 32768)
5120 base_reg_rtx
= stack_pointer_rtx
;
5124 else if (base_reg_rtx
!= (rtx
)0
5125 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5126 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5128 ; /* already set up for gp registers above */
5131 else if (large_reg
!= (rtx
)0
5132 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5133 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5135 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5136 base_offset
= large_offset
;
5137 if (file
== (FILE *)0)
5140 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5142 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5143 RTX_FRAME_RELATED_P (insn
) = 1;
5146 fprintf (file
, "\t%s\t%s,%s,%s\n",
5147 TARGET_LONG64
? "daddu" : "addu",
5148 reg_names
[MIPS_TEMP2_REGNUM
],
5149 reg_names
[REGNO (large_reg
)],
5150 reg_names
[STACK_POINTER_REGNUM
]);
5155 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5156 base_offset
= fp_offset
;
5157 if (file
== (FILE *)0)
5159 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
5160 RTX_FRAME_RELATED_P (insn
) = 1;
5162 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5164 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5165 RTX_FRAME_RELATED_P (insn
) = 1;
5168 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5169 reg_names
[MIPS_TEMP2_REGNUM
],
5172 TARGET_LONG64
? "daddu" : "addu",
5173 reg_names
[MIPS_TEMP2_REGNUM
],
5174 reg_names
[MIPS_TEMP2_REGNUM
],
5175 reg_names
[STACK_POINTER_REGNUM
]);
5178 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5180 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5182 if (file
== (FILE *)0)
5184 enum machine_mode sz
=
5185 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5186 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5187 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5188 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5189 GEN_INT (fp_offset
- base_offset
)));
5193 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5194 RTX_FRAME_RELATED_P (insn
) = 1;
5197 emit_move_insn (reg_rtx
, mem_rtx
);
5200 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5201 (TARGET_SINGLE_FLOAT
5202 ? ((store_p
) ? "s.s" : "l.s")
5203 : ((store_p
) ? "s.d" : "l.d")),
5205 fp_offset
- base_offset
,
5206 reg_names
[REGNO(base_reg_rtx
)]);
5209 fp_offset
-= fp_size
;
5216 /* Set up the stack and frame (if desired) for the function. */
5219 function_prologue (file
, size
)
5224 long tsize
= current_frame_info
.total_size
;
5226 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5228 #ifdef SDB_DEBUGGING_INFO
5229 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5230 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5233 inside_function
= 1;
5235 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5236 /* Get the function name the same way that toplev.c does before calling
5237 assemble_start_function. This is needed so that the name used here
5238 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5239 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5241 fputs ("\t.ent\t", file
);
5242 assemble_name (file
, fnname
);
5245 assemble_name (file
, fnname
);
5246 fputs (":\n", file
);
5249 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5250 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5252 reg_names
[31 + GP_REG_FIRST
],
5253 current_frame_info
.var_size
,
5254 current_frame_info
.num_gp
,
5255 current_frame_info
.num_fp
,
5256 current_function_outgoing_args_size
,
5257 current_frame_info
.extra_size
);
5259 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5260 current_frame_info
.mask
,
5261 current_frame_info
.gp_save_offset
,
5262 current_frame_info
.fmask
,
5263 current_frame_info
.fp_save_offset
);
5265 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5267 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5269 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5270 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5273 fprintf (file
, "\t%s\t%s,%s,%d\n",
5274 (TARGET_LONG64
? "dsubu" : "subu"),
5275 sp_str
, sp_str
, tsize
);
5276 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5282 /* Expand the prologue into a bunch of separate insns. */
5285 mips_expand_prologue ()
5289 rtx tmp_rtx
= (rtx
)0;
5290 char *arg_name
= (char *)0;
5291 tree fndecl
= current_function_decl
;
5292 tree fntype
= TREE_TYPE (fndecl
);
5293 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5298 CUMULATIVE_ARGS args_so_far
;
5300 /* If struct value address is treated as the first argument, make it so. */
5301 if (aggregate_value_p (DECL_RESULT (fndecl
))
5302 && ! current_function_returns_pcc_struct
5303 && struct_value_incoming_rtx
== 0)
5305 tree type
= build_pointer_type (fntype
);
5306 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5307 DECL_ARG_TYPE (function_result_decl
) = type
;
5308 TREE_CHAIN (function_result_decl
) = fnargs
;
5309 fnargs
= function_result_decl
;
5312 /* Determine the last argument, and get its name. */
5314 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5315 regno
= GP_ARG_FIRST
;
5317 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5319 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5320 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5323 if (TREE_ADDRESSABLE (passed_type
))
5325 passed_type
= build_pointer_type (passed_type
);
5326 passed_mode
= Pmode
;
5329 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5335 /* passed in a register, so will get homed automatically */
5336 if (GET_MODE (entry_parm
) == BLKmode
)
5337 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5339 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5341 regno
= REGNO (entry_parm
) + words
- 1;
5345 regno
= GP_ARG_LAST
+1;
5349 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5351 next_arg
= TREE_CHAIN (cur_arg
);
5352 if (next_arg
== (tree
)0)
5354 if (DECL_NAME (cur_arg
))
5355 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5361 /* In order to pass small structures by value in registers
5362 compatibly with the MIPS compiler, we need to shift the value
5363 into the high part of the register. Function_arg has encoded a
5364 PARALLEL rtx, holding a vector of adjustments to be made as the
5365 next_arg_reg variable, so we split up the insns, and emit them
5368 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5369 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5371 rtvec adjust
= XVEC (next_arg_reg
, 0);
5372 int num
= GET_NUM_ELEM (adjust
);
5374 for (i
= 0; i
< num
; i
++)
5376 rtx pattern
= RTVEC_ELT (adjust
, i
);
5377 if (GET_CODE (pattern
) != SET
5378 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5379 abort_with_insn (pattern
, "Insn is not a shift");
5381 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5382 emit_insn (pattern
);
5386 tsize
= compute_frame_size (get_frame_size ());
5388 /* If this function is a varargs function, store any registers that
5389 would normally hold arguments ($4 - $7) on the stack. */
5390 if (mips_abi
== ABI_32
5391 && ((TYPE_ARG_TYPES (fntype
) != 0
5392 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5393 || (arg_name
!= (char *)0
5394 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5395 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5397 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5398 rtx ptr
= stack_pointer_rtx
;
5400 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5401 if (TARGET_ABICALLS
)
5404 for (; regno
<= GP_ARG_LAST
; regno
++)
5407 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5408 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5409 gen_rtx (REG
, word_mode
, regno
));
5410 offset
+= UNITS_PER_WORD
;
5416 rtx tsize_rtx
= GEN_INT (tsize
);
5418 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5419 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5425 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5426 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5427 RTX_FRAME_RELATED_P (insn
) = 1;
5428 tsize_rtx
= tmp_rtx
;
5432 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5435 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5438 RTX_FRAME_RELATED_P (insn
) = 1;
5441 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5443 if (frame_pointer_needed
)
5448 insn
= emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5450 insn
= emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5452 RTX_FRAME_RELATED_P (insn
) = 1;
5455 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5456 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5459 /* If we are profiling, make sure no instructions are scheduled before
5460 the call to mcount. */
5462 if (profile_flag
|| profile_block_flag
)
5463 emit_insn (gen_blockage ());
5467 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5469 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5470 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5473 function_epilogue (file
, size
)
5479 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5480 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5481 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5482 int noreorder
= (epilogue_delay
!= 0);
5483 int noepilogue
= FALSE
;
5484 int load_nop
= FALSE
;
5486 rtx tmp_rtx
= (rtx
)0;
5490 /* The epilogue does not depend on any registers, but the stack
5491 registers, so we assume that if we have 1 pending nop, it can be
5492 ignored, and 2 it must be filled (2 nops occur for integer
5493 multiply and divide). */
5495 if (dslots_number_nops
> 0)
5497 if (dslots_number_nops
== 1)
5499 dslots_number_nops
= 0;
5500 dslots_load_filled
++;
5504 while (--dslots_number_nops
> 0)
5505 fputs ("\t#nop\n", asm_out_file
);
5512 fputs ("\t.set\tat\n", file
);
5513 error ("internal gcc error: .set noat left on in epilogue");
5516 if (set_nomacro
!= 0)
5519 fputs ("\t.set\tmacro\n", file
);
5520 error ("internal gcc error: .set nomacro left on in epilogue");
5523 if (set_noreorder
!= 0)
5526 fputs ("\t.set\treorder\n", file
);
5527 error ("internal gcc error: .set noreorder left on in epilogue");
5530 if (set_volatile
!= 0)
5533 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5534 error ("internal gcc error: .set volatile left on in epilogue");
5537 size
= MIPS_STACK_ALIGN (size
);
5538 tsize
= (!current_frame_info
.initialized
)
5539 ? compute_frame_size (size
)
5540 : current_frame_info
.total_size
;
5542 if (tsize
== 0 && epilogue_delay
== 0)
5544 rtx insn
= get_last_insn ();
5546 /* If the last insn was a BARRIER, we don't have to write any code
5547 because a jump (aka return) was put there. */
5548 if (GET_CODE (insn
) == NOTE
)
5549 insn
= prev_nonnote_insn (insn
);
5550 if (insn
&& GET_CODE (insn
) == BARRIER
)
5558 /* In the reload sequence, we don't need to fill the load delay
5559 slots for most of the loads, also see if we can fill the final
5560 delay slot if not otherwise filled by the reload sequence. */
5563 fprintf (file
, "\t.set\tnoreorder\n");
5567 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5568 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5571 if (frame_pointer_needed
)
5572 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5573 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5575 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5577 load_only_r31
= (((current_frame_info
.mask
5578 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5579 ? PIC_OFFSET_TABLE_MASK
: 0))
5581 && current_frame_info
.fmask
== 0);
5585 /* If the only register saved is the return address, we need a
5586 nop, unless we have an instruction to put into it. Otherwise
5587 we don't since reloading multiple registers doesn't reference
5588 the register being loaded. */
5593 final_scan_insn (XEXP (epilogue_delay
, 0),
5597 1); /* nopeepholes */
5600 fprintf (file
, "\tnop\n");
5605 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5608 fprintf (file
, "\t%s\t%s,%s,%s\n",
5609 TARGET_LONG64
? "daddu" : "addu",
5610 sp_str
, sp_str
, t1_str
);
5613 fprintf (file
, "\t%s\t%s,%s,%d\n",
5614 TARGET_LONG64
? "daddu" : "addu",
5615 sp_str
, sp_str
, tsize
);
5617 else if (!load_only_r31
&& epilogue_delay
!= 0)
5618 final_scan_insn (XEXP (epilogue_delay
, 0),
5622 1); /* nopeepholes */
5624 fprintf (file
, "\t.set\treorder\n");
5630 fprintf (file
, "\t%s\t%s,%s,%s\n",
5631 TARGET_LONG64
? "daddu" : "addu",
5632 sp_str
, sp_str
, t1_str
);
5635 fprintf (file
, "\t%s\t%s,%s,%d\n",
5636 TARGET_LONG64
? "daddu" : "addu",
5637 sp_str
, sp_str
, tsize
);
5639 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5643 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5644 /* Get the function name the same way that toplev.c does before calling
5645 assemble_start_function. This is needed so that the name used here
5646 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5647 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5649 fputs ("\t.end\t", file
);
5650 assemble_name (file
, fnname
);
5656 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5657 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5658 int num_regs
= num_gp_regs
+ num_fp_regs
;
5659 char *name
= fnname
;
5664 dslots_load_total
+= num_regs
;
5667 dslots_jump_total
++;
5671 dslots_load_filled
+= num_regs
;
5673 /* If the only register saved is the return register, we
5674 can't fill this register's delay slot. */
5676 if (load_only_r31
&& epilogue_delay
== 0)
5677 dslots_load_filled
--;
5679 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5680 dslots_jump_filled
++;
5684 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5686 (frame_pointer_needed
) ? 'y' : 'n',
5687 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5688 (current_function_calls_alloca
) ? 'y' : 'n',
5689 (current_function_calls_setjmp
) ? 'y' : 'n',
5690 (long)current_frame_info
.total_size
,
5691 (long)current_function_outgoing_args_size
,
5692 num_gp_regs
, num_fp_regs
,
5693 dslots_load_total
, dslots_load_filled
,
5694 dslots_jump_total
, dslots_jump_filled
,
5695 num_refs
[0], num_refs
[1], num_refs
[2]);
5697 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5699 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5700 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5703 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5705 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5706 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5709 fputc ('\n', stderr
);
5712 /* Reset state info for each function. */
5713 inside_function
= FALSE
;
5714 ignore_line_number
= FALSE
;
5715 dslots_load_total
= 0;
5716 dslots_jump_total
= 0;
5717 dslots_load_filled
= 0;
5718 dslots_jump_filled
= 0;
5722 mips_load_reg
= (rtx
)0;
5723 mips_load_reg2
= (rtx
)0;
5724 current_frame_info
= zero_frame_info
;
5726 /* Restore the output file if optimizing the GP (optimizing the GP causes
5727 the text to be diverted to a tempfile, so that data decls come before
5728 references to the data). */
5731 asm_out_file
= asm_out_data_file
;
5735 /* Expand the epilogue into a bunch of separate insns. */
5738 mips_expand_epilogue ()
5740 long tsize
= current_frame_info
.total_size
;
5741 rtx tsize_rtx
= GEN_INT (tsize
);
5742 rtx tmp_rtx
= (rtx
)0;
5746 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5747 emit_move_insn (tmp_rtx
, tsize_rtx
);
5748 tsize_rtx
= tmp_rtx
;
5753 if (frame_pointer_needed
)
5756 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5758 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5761 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5764 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5767 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5771 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5775 /* Define the number of delay slots needed for the function epilogue.
5777 On the mips, we need a slot if either no stack has been allocated,
5778 or the only register saved is the return register. */
5781 mips_epilogue_delay_slots ()
5783 if (!current_frame_info
.initialized
)
5784 (void) compute_frame_size (get_frame_size ());
5786 if (current_frame_info
.total_size
== 0)
5789 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5796 /* Return true if this function is known to have a null epilogue.
5797 This allows the optimizer to omit jumps to jumps if no stack
5801 simple_epilogue_p ()
5803 if (!reload_completed
)
5806 if (current_frame_info
.initialized
)
5807 return current_frame_info
.total_size
== 0;
5809 return (compute_frame_size (get_frame_size ())) == 0;
5812 /* Choose the section to use for the constant rtx expression X that has
5815 mips_select_rtx_section (mode
, x
)
5816 enum machine_mode mode
;
5819 if (TARGET_EMBEDDED_DATA
)
5821 /* For embedded applications, always put constants in read-only data,
5822 in order to reduce RAM usage. */
5823 READONLY_DATA_SECTION ();
5827 /* For hosted applications, always put constants in small data if
5828 possible, as this gives the best performance. */
5830 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5831 && mips_section_threshold
> 0)
5832 SMALL_DATA_SECTION ();
5834 READONLY_DATA_SECTION ();
5838 /* Choose the section to use for DECL. RELOC is true if its value contains
5839 any relocatable expression. */
5841 mips_select_section (decl
, reloc
)
5845 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5847 if (TARGET_EMBEDDED_PIC
5848 && TREE_CODE (decl
) == STRING_CST
5849 && !flag_writable_strings
)
5851 /* For embedded position independent code, put constant strings
5852 in the text section, because the data section is limited to
5857 else if (TARGET_EMBEDDED_DATA
)
5859 /* For embedded applications, always put an object in read-only data
5860 if possible, in order to reduce RAM usage. */
5862 if (((TREE_CODE (decl
) == VAR_DECL
5863 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5864 && DECL_INITIAL (decl
)
5865 && (DECL_INITIAL (decl
) == error_mark_node
5866 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5867 /* Deal with calls from output_constant_def_contents. */
5868 || (TREE_CODE (decl
) != VAR_DECL
5869 && (TREE_CODE (decl
) != STRING_CST
5870 || !flag_writable_strings
)))
5871 && ! (flag_pic
&& reloc
))
5872 READONLY_DATA_SECTION ();
5873 else if (size
> 0 && size
<= mips_section_threshold
)
5874 SMALL_DATA_SECTION ();
5880 /* For hosted applications, always put an object in small data if
5881 possible, as this gives the best performance. */
5883 if (size
> 0 && size
<= mips_section_threshold
)
5884 SMALL_DATA_SECTION ();
5885 else if (((TREE_CODE (decl
) == VAR_DECL
5886 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5887 && DECL_INITIAL (decl
)
5888 && (DECL_INITIAL (decl
) == error_mark_node
5889 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5890 /* Deal with calls from output_constant_def_contents. */
5891 || (TREE_CODE (decl
) != VAR_DECL
5892 && (TREE_CODE (decl
) != STRING_CST
5893 || !flag_writable_strings
)))
5894 && ! (flag_pic
&& reloc
))
5895 READONLY_DATA_SECTION ();
5901 #ifdef MIPS_ABI_DEFAULT
5902 /* Support functions for the 64 bit ABI. */
5904 /* Return register to use for a function return value with VALTYPE for function
5908 mips_function_value (valtype
, func
)
5912 int reg
= GP_RETURN
;
5913 enum machine_mode mode
= TYPE_MODE (valtype
);
5914 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5916 /* ??? How should we return complex float? */
5917 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5919 if (TARGET_SINGLE_FLOAT
5920 && (mclass
== MODE_FLOAT
5921 ? GET_MODE_SIZE (mode
) > 4
5922 : GET_MODE_SIZE (mode
) / 2 > 4))
5927 else if (TREE_CODE (valtype
) == RECORD_TYPE
5928 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5930 /* A struct with only one or two floating point fields is returned in
5931 the floating point registers. */
5932 tree field
, fields
[2];
5935 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5936 field
= TREE_CHAIN (field
))
5938 if (TREE_CODE (field
) != FIELD_DECL
)
5940 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5943 fields
[i
++] = field
;
5946 /* Must check i, so that we reject structures with no elements. */
5951 /* The structure has DImode, but we don't allow DImode values
5952 in FP registers, so we use a PARALLEL even though it isn't
5953 strictly necessary. */
5954 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5956 return gen_rtx (PARALLEL
, mode
,
5958 gen_rtx (EXPR_LIST
, VOIDmode
,
5959 gen_rtx (REG
, field_mode
, FP_RETURN
),
5964 enum machine_mode first_mode
5965 = TYPE_MODE (TREE_TYPE (fields
[0]));
5966 enum machine_mode second_mode
5967 = TYPE_MODE (TREE_TYPE (fields
[1]));
5969 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5971 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5973 return gen_rtx (PARALLEL
, mode
,
5975 gen_rtx (EXPR_LIST
, VOIDmode
,
5976 gen_rtx (REG
, first_mode
, FP_RETURN
),
5977 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5978 gen_rtx (EXPR_LIST
, VOIDmode
,
5979 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5980 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5985 return gen_rtx (REG
, mode
, reg
);
5988 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
5989 nonzero when an argument must be passed by reference. */
5992 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5993 CUMULATIVE_ARGS
*cum
;
5994 enum machine_mode mode
;
6000 if (mips_abi
!= ABI_EABI
)
6003 /* ??? How should SCmode be handled? */
6004 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
6007 size
= int_size_in_bytes (type
);
6008 return size
== -1 || size
> UNITS_PER_WORD
;
6013 /* This function returns the register class required for a secondary
6014 register when copying between one of the registers in CLASS, and X,
6015 using MODE. If IN_P is nonzero, the copy is going from X to the
6016 register, otherwise the register is the source. A return value of
6017 NO_REGS means that no secondary register is required. */
6020 mips_secondary_reload_class (class, mode
, x
, in_p
)
6021 enum reg_class
class;
6022 enum machine_mode mode
;
6028 if (GET_CODE (x
) == SIGN_EXTEND
)
6034 /* We may be called with reg_renumber NULL from regclass.
6035 ??? This is probably a bug. */
6037 regno
= true_regnum (x
);
6040 while (GET_CODE (x
) == SUBREG
)
6042 off
+= SUBREG_WORD (x
);
6045 if (GET_CODE (x
) == REG
)
6046 regno
= REGNO (x
) + off
;
6049 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
6050 regno
= true_regnum (x
);
6052 /* We always require a general register when copying anything to
6053 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
6054 to a general register, or when copying from register 0. */
6055 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
6059 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6063 if (regno
== HILO_REGNUM
)
6067 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6072 /* Copying from HI or LO to anywhere other than a general register
6073 requires a general register. */
6074 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
6076 if (GP_REG_P (regno
))
6080 if (MD_REG_P (regno
))
6082 if (class == GR_REGS
)
6087 /* We can only copy a value to a condition code register from a
6088 floating point register, and even then we require a scratch
6089 floating point register. We can only copy a value out of a
6090 condition code register into a general register. */
6091 if (class == ST_REGS
)
6095 if (GP_REG_P (regno
))
6099 if (ST_REG_P (regno
))
6103 if (class == GR_REGS
)