1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
260 "$fcc5","$fcc6","$fcc7","$rap"
263 /* Mips software names for the registers, used to overwrite the
264 mips_reg_names array. */
266 char mips_sw_reg_names
[][8] =
268 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
269 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
270 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
271 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
272 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
273 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
274 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
275 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
276 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
277 "$fcc5","$fcc6","$fcc7","$rap"
280 /* Map hard register number to register class */
281 enum reg_class mips_regno_to_class
[] =
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
300 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
301 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
304 /* Map register constraint character to register class. */
305 enum reg_class mips_char_to_class
[256] =
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
374 /* Return truth value of whether OP can be used as an operands
375 where a register or 16 bit unsigned integer is needed. */
378 uns_arith_operand (op
, mode
)
380 enum machine_mode mode
;
382 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
385 return register_operand (op
, mode
);
388 /* Return truth value of whether OP can be used as an operands
389 where a 16 bit integer is needed */
392 arith_operand (op
, mode
)
394 enum machine_mode mode
;
396 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
399 return register_operand (op
, mode
);
402 /* Return truth value of whether OP can be used as an operand in a two
403 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
406 arith32_operand (op
, mode
)
408 enum machine_mode mode
;
410 if (GET_CODE (op
) == CONST_INT
)
413 return register_operand (op
, mode
);
416 /* Return truth value of whether OP is a integer which fits in 16 bits */
421 enum machine_mode mode
;
423 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
426 /* Return truth value of whether OP is a 32 bit integer which is too big to
427 be loaded with one instruction. */
432 enum machine_mode mode
;
436 if (GET_CODE (op
) != CONST_INT
)
440 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
443 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
446 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
452 /* Return truth value of whether OP is a register or the constant 0. */
455 reg_or_0_operand (op
, mode
)
457 enum machine_mode mode
;
459 switch (GET_CODE (op
))
465 return (INTVAL (op
) == 0);
468 if (op
!= CONST0_RTX (mode
))
475 return register_operand (op
, mode
);
481 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
484 mips_const_double_ok (op
, mode
)
486 enum machine_mode mode
;
490 if (GET_CODE (op
) != CONST_DOUBLE
)
493 if (mode
== VOIDmode
)
496 if (mode
!= SFmode
&& mode
!= DFmode
)
499 if (op
== CONST0_RTX (mode
))
502 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
503 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
506 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
508 if (REAL_VALUE_ISNAN (d
))
511 if (REAL_VALUE_NEGATIVE (d
))
512 d
= REAL_VALUE_NEGATE (d
);
516 if (REAL_VALUES_LESS (d
, dfhigh
)
517 && REAL_VALUES_LESS (dflow
, d
))
522 if (REAL_VALUES_LESS (d
, sfhigh
)
523 && REAL_VALUES_LESS (sflow
, d
))
530 /* Accept the floating point constant 1 in the appropriate mode. */
533 const_float_1_operand (op
, mode
)
535 enum machine_mode mode
;
538 static REAL_VALUE_TYPE onedf
;
539 static REAL_VALUE_TYPE onesf
;
540 static int one_initialized
;
542 if (GET_CODE (op
) != CONST_DOUBLE
543 || mode
!= GET_MODE (op
)
544 || (mode
!= DFmode
&& mode
!= SFmode
))
547 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
549 /* We only initialize these values if we need them, since we will
550 never get called unless mips_isa >= 4. */
551 if (! one_initialized
)
553 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
554 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
555 one_initialized
= TRUE
;
559 return REAL_VALUES_EQUAL (d
, onedf
);
561 return REAL_VALUES_EQUAL (d
, onesf
);
564 /* Return truth value if a memory operand fits in a single instruction
565 (ie, register + small offset). */
568 simple_memory_operand (op
, mode
)
570 enum machine_mode mode
;
572 rtx addr
, plus0
, plus1
;
574 /* Eliminate non-memory operations */
575 if (GET_CODE (op
) != MEM
)
578 /* dword operations really put out 2 instructions, so eliminate them. */
579 /* ??? This isn't strictly correct. It is OK to accept multiword modes
580 here, since the length attributes are being set correctly, but only
581 if the address is offsettable. LO_SUM is not offsettable. */
582 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
585 /* Decode the address now. */
587 switch (GET_CODE (addr
))
597 return SMALL_INT (op
);
600 plus0
= XEXP (addr
, 0);
601 plus1
= XEXP (addr
, 1);
602 if (GET_CODE (plus0
) == REG
603 && GET_CODE (plus1
) == CONST_INT
604 && SMALL_INT (plus1
))
607 else if (GET_CODE (plus1
) == REG
608 && GET_CODE (plus0
) == CONST_INT
609 && SMALL_INT (plus0
))
616 /* We used to allow small symbol refs here (ie, stuff in .sdata
617 or .sbss), but this causes some bugs in G++. Also, it won't
618 interfere if the MIPS linker rewrites the store instruction
619 because the function is PIC. */
621 case LABEL_REF
: /* never gp relative */
625 /* If -G 0, we can never have a GP relative memory operation.
626 Also, save some time if not optimizing. */
631 rtx offset
= const0_rtx
;
632 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
633 if (GET_CODE (op
) != SYMBOL_REF
)
636 /* let's be paranoid.... */
637 if (! SMALL_INT (offset
))
643 return SYMBOL_REF_FLAG (addr
);
650 /* Return true if the code of this rtx pattern is EQ or NE. */
653 equality_op (op
, mode
)
655 enum machine_mode mode
;
657 if (mode
!= GET_MODE (op
))
660 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
663 /* Return true if the code is a relational operations (EQ, LE, etc.) */
668 enum machine_mode mode
;
670 if (mode
!= GET_MODE (op
))
673 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
676 /* Return true if the operand is either the PC or a label_ref. */
679 pc_or_label_operand (op
, mode
)
681 enum machine_mode mode
;
686 if (GET_CODE (op
) == LABEL_REF
)
692 /* Test for a valid operand for a call instruction.
693 Don't allow the arg pointer register or virtual regs
694 since they may change into reg + const, which the patterns
698 call_insn_operand (op
, mode
)
700 enum machine_mode mode
;
702 if (CONSTANT_ADDRESS_P (op
)
703 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
704 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
705 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
710 /* Return true if OPERAND is valid as a source operand for a move
714 move_operand (op
, mode
)
716 enum machine_mode mode
;
718 return (general_operand (op
, mode
)
719 && ! (mips_split_addresses
&& mips_check_split (op
, mode
)));
722 /* Return true if we split the address into high and low parts. */
724 /* ??? We should also handle reg+array somewhere. We get four
725 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
726 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
727 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
728 out of the address, then we have 4 instructions to combine. Perhaps
729 add a 3->2 define_split for combine. */
731 /* ??? We could also split a CONST_INT here if it is a large_int().
732 However, it doesn't seem to be very useful to have %hi(constant).
733 We would be better off by doing the masking ourselves and then putting
734 the explicit high part of the constant in the RTL. This will give better
735 optimization. Also, %hi(constant) needs assembler changes to work.
736 There is already a define_split that does this. */
739 mips_check_split (address
, mode
)
741 enum machine_mode mode
;
743 /* ??? This is the same check used in simple_memory_operand.
744 We use it here because LO_SUM is not offsettable. */
745 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
748 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
749 || (GET_CODE (address
) == CONST
750 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
751 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
752 || GET_CODE (address
) == LABEL_REF
)
758 /* Returns an operand string for the given instruction's delay slot,
759 after updating filled delay slot statistics.
761 We assume that operands[0] is the target register that is set.
763 In order to check the next insn, most of this functionality is moved
764 to FINAL_PRESCAN_INSN, and we just set the global variables that
767 /* ??? This function no longer does anything useful, because final_prescan_insn
768 now will never emit a nop. */
771 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
772 char *ret
; /* normal string to return */
773 enum delay_type type
; /* type of delay */
774 rtx operands
[]; /* operands to use */
775 rtx cur_insn
; /* current insn */
777 register rtx set_reg
;
778 register enum machine_mode mode
;
779 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
780 register int num_nops
;
782 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
785 else if (type
== DELAY_HILO
)
791 /* Make sure that we don't put nop's after labels. */
792 next_insn
= NEXT_INSN (cur_insn
);
793 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
794 next_insn
= NEXT_INSN (next_insn
);
796 dslots_load_total
+= num_nops
;
797 if (TARGET_DEBUG_F_MODE
799 || type
== DELAY_NONE
800 || operands
== (rtx
*)0
801 || cur_insn
== (rtx
)0
802 || next_insn
== (rtx
)0
803 || GET_CODE (next_insn
) == CODE_LABEL
804 || (set_reg
= operands
[0]) == (rtx
)0)
806 dslots_number_nops
= 0;
807 mips_load_reg
= (rtx
)0;
808 mips_load_reg2
= (rtx
)0;
809 mips_load_reg3
= (rtx
)0;
810 mips_load_reg4
= (rtx
)0;
814 set_reg
= operands
[0];
815 if (set_reg
== (rtx
)0)
818 while (GET_CODE (set_reg
) == SUBREG
)
819 set_reg
= SUBREG_REG (set_reg
);
821 mode
= GET_MODE (set_reg
);
822 dslots_number_nops
= num_nops
;
823 mips_load_reg
= set_reg
;
824 if (GET_MODE_SIZE (mode
)
825 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
826 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
830 if (type
== DELAY_HILO
)
832 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
833 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
845 /* Determine whether a memory reference takes one (based off of the GP pointer),
846 two (normal), or three (label + reg) instructions, and bump the appropriate
847 counter for -mstats. */
850 mips_count_memory_refs (op
, num
)
856 rtx addr
, plus0
, plus1
;
857 enum rtx_code code0
, code1
;
860 if (TARGET_DEBUG_B_MODE
)
862 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
866 /* Skip MEM if passed, otherwise handle movsi of address. */
867 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
869 /* Loop, going through the address RTL */
873 switch (GET_CODE (addr
))
884 plus0
= XEXP (addr
, 0);
885 plus1
= XEXP (addr
, 1);
886 code0
= GET_CODE (plus0
);
887 code1
= GET_CODE (plus1
);
897 if (code0
== CONST_INT
)
912 if (code1
== CONST_INT
)
919 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
926 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
936 n_words
= 2; /* always 2 words */
940 addr
= XEXP (addr
, 0);
945 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
954 n_words
+= additional
;
958 num_refs
[n_words
-1] += num
;
962 /* Return RTL for the offset from the current function to the
966 embedded_pic_offset (x
)
969 if (embedded_pic_fnaddr_rtx
== NULL
)
973 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
975 /* Output code at function start to initialize the pseudo-reg. */
976 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
977 inline functions, because it is called after RTL for the function
978 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
979 does not get copied, and ends up not matching the rest of the RTL.
980 This solution works, but means that we get unnecessary code to
981 initialize this value every time a function is inlined into another
984 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
985 XEXP (DECL_RTL (current_function_decl
), 0)));
986 seq
= gen_sequence ();
988 push_topmost_sequence ();
989 emit_insn_after (seq
, get_insns ());
990 pop_topmost_sequence ();
993 return gen_rtx (CONST
, Pmode
,
994 gen_rtx (MINUS
, Pmode
, x
,
995 XEXP (DECL_RTL (current_function_decl
), 0)));
998 /* Return the appropriate instructions to move one operand to another. */
1001 mips_move_1word (operands
, insn
, unsignedp
)
1007 rtx op0
= operands
[0];
1008 rtx op1
= operands
[1];
1009 enum rtx_code code0
= GET_CODE (op0
);
1010 enum rtx_code code1
= GET_CODE (op1
);
1011 enum machine_mode mode
= GET_MODE (op0
);
1012 int subreg_word0
= 0;
1013 int subreg_word1
= 0;
1014 enum delay_type delay
= DELAY_NONE
;
1016 while (code0
== SUBREG
)
1018 subreg_word0
+= SUBREG_WORD (op0
);
1019 op0
= SUBREG_REG (op0
);
1020 code0
= GET_CODE (op0
);
1023 while (code1
== SUBREG
)
1025 subreg_word1
+= SUBREG_WORD (op1
);
1026 op1
= SUBREG_REG (op1
);
1027 code1
= GET_CODE (op1
);
1030 /* For our purposes, a condition code mode is the same as SImode. */
1036 int regno0
= REGNO (op0
) + subreg_word0
;
1040 int regno1
= REGNO (op1
) + subreg_word1
;
1042 /* Just in case, don't do anything for assigning a register
1043 to itself, unless we are filling a delay slot. */
1044 if (regno0
== regno1
&& set_nomacro
== 0)
1047 else if (GP_REG_P (regno0
))
1049 if (GP_REG_P (regno1
))
1050 ret
= "move\t%0,%1";
1052 else if (MD_REG_P (regno1
))
1055 if (regno1
!= HILO_REGNUM
)
1061 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1062 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1067 if (FP_REG_P (regno1
))
1068 ret
= "mfc1\t%0,%1";
1070 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1071 ret
= "cfc1\t%0,$31";
1075 else if (FP_REG_P (regno0
))
1077 if (GP_REG_P (regno1
))
1080 ret
= "mtc1\t%1,%0";
1083 if (FP_REG_P (regno1
))
1084 ret
= "mov.s\t%0,%1";
1087 else if (MD_REG_P (regno0
))
1089 if (GP_REG_P (regno1
))
1092 if (regno0
!= HILO_REGNUM
)
1097 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1099 if (GP_REG_P (regno1
))
1102 ret
= "ctc1\t%0,$31";
1107 else if (code1
== MEM
)
1112 mips_count_memory_refs (op1
, 1);
1114 if (GP_REG_P (regno0
))
1116 /* For loads, use the mode of the memory item, instead of the
1117 target, so zero/sign extend can use this code as well. */
1118 switch (GET_MODE (op1
))
1127 ret
= ((unsignedp
&& TARGET_64BIT
)
1132 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1135 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1140 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1143 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1145 int i
= strlen (ret
);
1146 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1149 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1150 ret
= volatile_buffer
;
1154 else if (code1
== CONST_INT
1155 || (code1
== CONST_DOUBLE
1156 && GET_MODE (op1
) == VOIDmode
))
1158 if (code1
== CONST_DOUBLE
)
1160 /* This can happen when storing constants into long long
1161 bitfields. Just store the least significant word of
1163 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1166 if (INTVAL (op1
) == 0)
1168 if (GP_REG_P (regno0
))
1169 ret
= "move\t%0,%z1";
1171 else if (FP_REG_P (regno0
))
1174 ret
= "mtc1\t%z1,%0";
1177 else if (MD_REG_P (regno0
))
1184 else if (GP_REG_P (regno0
))
1185 /* Don't use X format, because that will give out of range
1186 numbers for 64 bit host and 32 bit target. */
1187 ret
= "li\t%0,%1\t\t\t# %X1";
1190 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1192 if (op1
== CONST0_RTX (SFmode
))
1194 if (GP_REG_P (regno0
))
1195 ret
= "move\t%0,%.";
1197 else if (FP_REG_P (regno0
))
1200 ret
= "mtc1\t%.,%0";
1207 ret
= "li.s\t%0,%1";
1211 else if (code1
== LABEL_REF
)
1214 mips_count_memory_refs (op1
, 1);
1219 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1221 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1223 rtx offset
= const0_rtx
;
1225 if (GET_CODE (op1
) == CONST
)
1226 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1228 if (GET_CODE (op1
) == SYMBOL_REF
)
1230 operands
[2] = HALF_PIC_PTR (op1
);
1233 mips_count_memory_refs (operands
[2], 1);
1235 if (INTVAL (offset
) == 0)
1238 ret
= (unsignedp
&& TARGET_64BIT
1244 dslots_load_total
++;
1245 operands
[3] = offset
;
1246 if (unsignedp
&& TARGET_64BIT
)
1247 ret
= (SMALL_INT (offset
))
1248 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1249 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1251 ret
= (SMALL_INT (offset
))
1252 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1253 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1260 mips_count_memory_refs (op1
, 1);
1266 else if (code1
== PLUS
)
1268 rtx add_op0
= XEXP (op1
, 0);
1269 rtx add_op1
= XEXP (op1
, 1);
1271 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1273 add_op0
= XEXP (op1
, 1); /* reverse operands */
1274 add_op1
= XEXP (op1
, 0);
1277 operands
[2] = add_op0
;
1278 operands
[3] = add_op1
;
1279 ret
= "add%:\t%0,%2,%3";
1282 else if (code1
== HIGH
)
1284 operands
[1] = XEXP (op1
, 0);
1285 ret
= "lui\t%0,%%hi(%1)";
1289 else if (code0
== MEM
)
1292 mips_count_memory_refs (op0
, 1);
1296 int regno1
= REGNO (op1
) + subreg_word1
;
1298 if (GP_REG_P (regno1
))
1303 case SFmode
: ret
= "sw\t%1,%0"; break;
1304 case SImode
: ret
= "sw\t%1,%0"; break;
1305 case HImode
: ret
= "sh\t%1,%0"; break;
1306 case QImode
: ret
= "sb\t%1,%0"; break;
1310 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1314 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1319 case SFmode
: ret
= "sw\t%z1,%0"; break;
1320 case SImode
: ret
= "sw\t%z1,%0"; break;
1321 case HImode
: ret
= "sh\t%z1,%0"; break;
1322 case QImode
: ret
= "sb\t%z1,%0"; break;
1326 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1331 case SFmode
: ret
= "sw\t%.,%0"; break;
1332 case SImode
: ret
= "sw\t%.,%0"; break;
1333 case HImode
: ret
= "sh\t%.,%0"; break;
1334 case QImode
: ret
= "sb\t%.,%0"; break;
1338 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1340 int i
= strlen (ret
);
1341 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1344 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1345 ret
= volatile_buffer
;
1349 if (ret
== (char *)0)
1351 abort_with_insn (insn
, "Bad move");
1355 if (delay
!= DELAY_NONE
)
1356 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1362 /* Return the appropriate instructions to move 2 words */
1365 mips_move_2words (operands
, insn
)
1370 rtx op0
= operands
[0];
1371 rtx op1
= operands
[1];
1372 enum rtx_code code0
= GET_CODE (operands
[0]);
1373 enum rtx_code code1
= GET_CODE (operands
[1]);
1374 int subreg_word0
= 0;
1375 int subreg_word1
= 0;
1376 enum delay_type delay
= DELAY_NONE
;
1378 while (code0
== SUBREG
)
1380 subreg_word0
+= SUBREG_WORD (op0
);
1381 op0
= SUBREG_REG (op0
);
1382 code0
= GET_CODE (op0
);
1385 while (code1
== SUBREG
)
1387 subreg_word1
+= SUBREG_WORD (op1
);
1388 op1
= SUBREG_REG (op1
);
1389 code1
= GET_CODE (op1
);
1394 int regno0
= REGNO (op0
) + subreg_word0
;
1398 int regno1
= REGNO (op1
) + subreg_word1
;
1400 /* Just in case, don't do anything for assigning a register
1401 to itself, unless we are filling a delay slot. */
1402 if (regno0
== regno1
&& set_nomacro
== 0)
1405 else if (FP_REG_P (regno0
))
1407 if (FP_REG_P (regno1
))
1408 ret
= "mov.d\t%0,%1";
1416 abort_with_insn (insn
, "Bad move");
1417 #ifdef TARGET_FP_CALL_32
1418 if (FP_CALL_GP_REG_P (regno1
))
1419 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1422 ret
= "dmtc1\t%1,%0";
1425 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1429 else if (FP_REG_P (regno1
))
1435 abort_with_insn (insn
, "Bad move");
1436 #ifdef TARGET_FP_CALL_32
1437 if (FP_CALL_GP_REG_P (regno0
))
1438 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1441 ret
= "dmfc1\t%0,%1";
1444 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1447 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1452 if (regno0
!= HILO_REGNUM
)
1454 else if (regno1
== 0)
1455 ret
= "mtlo\t%.\n\tmthi\t%.";
1458 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1461 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1466 if (regno1
!= HILO_REGNUM
)
1470 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1473 else if (TARGET_64BIT
)
1474 ret
= "move\t%0,%1";
1476 else if (regno0
!= (regno1
+1))
1477 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1480 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1483 else if (code1
== CONST_DOUBLE
)
1485 /* Move zero from $0 unless !TARGET_64BIT and recipient
1486 is 64-bit fp reg, in which case generate a constant. */
1487 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1488 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1490 if (GET_MODE (op1
) == DFmode
)
1493 #ifdef TARGET_FP_CALL_32
1494 if (FP_CALL_GP_REG_P (regno0
))
1496 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1498 split_double (op1
, operands
+ 2, operands
+ 3);
1499 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1502 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1506 ret
= "li.d\t%0,%1";
1509 else if (TARGET_64BIT
)
1514 split_double (op1
, operands
+ 2, operands
+ 3);
1515 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1521 if (GP_REG_P (regno0
))
1523 #ifdef TARGET_FP_CALL_32
1524 && ! FP_CALL_GP_REG_P (regno0
)
1528 : "move\t%0,%.\n\tmove\t%D0,%.";
1530 else if (FP_REG_P (regno0
))
1533 ret
= (TARGET_64BIT
)
1535 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1540 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1542 if (GP_REG_P (regno0
))
1543 ret
= (TARGET_64BIT
)
1545 : "move\t%0,%.\n\tmove\t%D0,%.";
1547 else if (FP_REG_P (regno0
))
1550 ret
= (TARGET_64BIT
)
1554 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1556 else if (MD_REG_P (regno0
))
1559 if (regno0
!= HILO_REGNUM
)
1562 ret
= "mtlo\t%.\n\tmthi\t%.";
1566 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1570 if (HOST_BITS_PER_WIDE_INT
< 64)
1571 /* We can't use 'X' for negative numbers, because then we won't
1572 get the right value for the upper 32 bits. */
1573 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1574 : "dli\t%0,%X1\t\t# %1");
1576 /* We must use 'X', because otherwise LONG_MIN will print as
1577 a number that the assembler won't accept. */
1578 ret
= "dli\t%0,%X1\t\t# %1";
1580 else if (HOST_BITS_PER_WIDE_INT
< 64)
1582 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1583 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1587 /* We use multiple shifts here, to avoid warnings about out
1588 of range shifts on 32 bit hosts. */
1589 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1590 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1591 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1595 else if (code1
== MEM
)
1600 mips_count_memory_refs (op1
, 2);
1602 if (FP_REG_P (regno0
))
1605 else if (TARGET_64BIT
)
1607 #ifdef TARGET_FP_CALL_32
1608 if (FP_CALL_GP_REG_P (regno0
))
1610 if (offsettable_address_p (FALSE
, SImode
, op1
))
1611 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1613 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1620 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1622 operands
[2] = adj_offsettable_operand (op1
, 4);
1623 if (reg_mentioned_p (op0
, op1
))
1624 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1626 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1629 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1631 int i
= strlen (ret
);
1632 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1635 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1636 ret
= volatile_buffer
;
1640 else if (code1
== LABEL_REF
1641 || code1
== SYMBOL_REF
1645 mips_count_memory_refs (op1
, 2);
1647 ret
= "dla\t%0,%a1";
1651 else if (code0
== MEM
)
1655 int regno1
= REGNO (op1
) + subreg_word1
;
1657 if (FP_REG_P (regno1
))
1660 else if (TARGET_64BIT
)
1662 #ifdef TARGET_FP_CALL_32
1663 if (FP_CALL_GP_REG_P (regno1
))
1664 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1670 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1672 operands
[2] = adj_offsettable_operand (op0
, 4);
1673 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1677 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1678 || (code1
== CONST_DOUBLE
1679 && op1
== CONST0_RTX (GET_MODE (op1
))))
1681 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1687 operands
[2] = adj_offsettable_operand (op0
, 4);
1688 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1693 mips_count_memory_refs (op0
, 2);
1695 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1697 int i
= strlen (ret
);
1698 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1701 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1702 ret
= volatile_buffer
;
1706 if (ret
== (char *)0)
1708 abort_with_insn (insn
, "Bad move");
1712 if (delay
!= DELAY_NONE
)
1713 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1719 /* Provide the costs of an addressing mode that contains ADDR.
1720 If ADDR is not a valid address, its cost is irrelevant. */
1723 mips_address_cost (addr
)
1726 switch (GET_CODE (addr
))
1739 rtx offset
= const0_rtx
;
1740 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1741 if (GET_CODE (addr
) == LABEL_REF
)
1744 if (GET_CODE (addr
) != SYMBOL_REF
)
1747 if (! SMALL_INT (offset
))
1753 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1757 register rtx plus0
= XEXP (addr
, 0);
1758 register rtx plus1
= XEXP (addr
, 1);
1760 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1762 plus0
= XEXP (addr
, 1);
1763 plus1
= XEXP (addr
, 0);
1766 if (GET_CODE (plus0
) != REG
)
1769 switch (GET_CODE (plus1
))
1775 return (SMALL_INT (plus1
) ? 1 : 2);
1782 return mips_address_cost (plus1
) + 1;
1790 /* Return true if X is an address which needs a temporary register when
1791 reloaded while generating PIC code. */
1794 pic_address_needs_scratch (x
)
1797 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1798 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1799 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1800 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1801 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1807 /* Make normal rtx_code into something we can index from an array */
1809 static enum internal_test
1810 map_test_to_internal_test (test_code
)
1811 enum rtx_code test_code
;
1813 enum internal_test test
= ITEST_MAX
;
1818 case EQ
: test
= ITEST_EQ
; break;
1819 case NE
: test
= ITEST_NE
; break;
1820 case GT
: test
= ITEST_GT
; break;
1821 case GE
: test
= ITEST_GE
; break;
1822 case LT
: test
= ITEST_LT
; break;
1823 case LE
: test
= ITEST_LE
; break;
1824 case GTU
: test
= ITEST_GTU
; break;
1825 case GEU
: test
= ITEST_GEU
; break;
1826 case LTU
: test
= ITEST_LTU
; break;
1827 case LEU
: test
= ITEST_LEU
; break;
1834 /* Generate the code to compare two integer values. The return value is:
1835 (reg:SI xx) The pseudo register the comparison is in
1836 (rtx)0 No register, generate a simple branch.
1838 ??? This is called with result nonzero by the Scond patterns in
1839 mips.md. These patterns are called with a target in the mode of
1840 the Scond instruction pattern. Since this must be a constant, we
1841 must use SImode. This means that if RESULT is non-zero, it will
1842 always be an SImode register, even if TARGET_64BIT is true. We
1843 cope with this by calling convert_move rather than emit_move_insn.
1844 This will sometimes lead to an unnecessary extension of the result;
1856 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
1857 enum rtx_code test_code
; /* relational test (EQ, etc) */
1858 rtx result
; /* result to store comp. or 0 if branch */
1859 rtx cmp0
; /* first operand to compare */
1860 rtx cmp1
; /* second operand to compare */
1861 int *p_invert
; /* NULL or ptr to hold whether branch needs */
1862 /* to reverse its test */
1865 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
1866 int const_low
; /* low bound of constant we can accept */
1867 int const_high
; /* high bound of constant we can accept */
1868 int const_add
; /* constant to add (convert LE -> LT) */
1869 int reverse_regs
; /* reverse registers in test */
1870 int invert_const
; /* != 0 if invert value if cmp1 is constant */
1871 int invert_reg
; /* != 0 if invert value if cmp1 is register */
1872 int unsignedp
; /* != 0 for unsigned comparisons. */
1875 static struct cmp_info info
[ (int)ITEST_MAX
] = {
1877 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
1878 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
1879 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
1880 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
1881 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
1882 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
1883 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
1884 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
1885 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
1886 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
1889 enum internal_test test
;
1890 enum machine_mode mode
;
1891 struct cmp_info
*p_info
;
1898 test
= map_test_to_internal_test (test_code
);
1899 if (test
== ITEST_MAX
)
1902 p_info
= &info
[ (int)test
];
1903 eqne_p
= (p_info
->test_code
== XOR
);
1905 mode
= GET_MODE (cmp0
);
1906 if (mode
== VOIDmode
)
1907 mode
= GET_MODE (cmp1
);
1909 /* Eliminate simple branches */
1910 branch_p
= (result
== (rtx
)0);
1913 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
1915 /* Comparisons against zero are simple branches */
1916 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1919 /* Test for beq/bne. */
1924 /* allocate a pseudo to calculate the value in. */
1925 result
= gen_reg_rtx (mode
);
1928 /* Make sure we can handle any constants given to us. */
1929 if (GET_CODE (cmp0
) == CONST_INT
)
1930 cmp0
= force_reg (mode
, cmp0
);
1932 if (GET_CODE (cmp1
) == CONST_INT
)
1934 HOST_WIDE_INT value
= INTVAL (cmp1
);
1935 if (value
< p_info
->const_low
1936 || value
> p_info
->const_high
1937 /* ??? Why? And why wasn't the similar code below modified too? */
1939 && HOST_BITS_PER_WIDE_INT
< 64
1940 && p_info
->const_add
!= 0
1941 && ((p_info
->unsignedp
1942 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
1944 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
1945 != (p_info
->const_add
> 0))))
1946 cmp1
= force_reg (mode
, cmp1
);
1949 /* See if we need to invert the result. */
1950 invert
= (GET_CODE (cmp1
) == CONST_INT
)
1951 ? p_info
->invert_const
1952 : p_info
->invert_reg
;
1954 if (p_invert
!= (int *)0)
1960 /* Comparison to constants, may involve adding 1 to change a LT into LE.
1961 Comparison between two registers, may involve switching operands. */
1962 if (GET_CODE (cmp1
) == CONST_INT
)
1964 if (p_info
->const_add
!= 0)
1966 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
1967 /* If modification of cmp1 caused overflow,
1968 we would get the wrong answer if we follow the usual path;
1969 thus, x > 0xffffffffU would turn into x > 0U. */
1970 if ((p_info
->unsignedp
1971 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
1972 : new > INTVAL (cmp1
))
1973 != (p_info
->const_add
> 0))
1975 /* This test is always true, but if INVERT is true then
1976 the result of the test needs to be inverted so 0 should
1977 be returned instead. */
1978 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
1982 cmp1
= GEN_INT (new);
1985 else if (p_info
->reverse_regs
)
1992 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
1996 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
1997 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2000 if (test
== ITEST_NE
)
2002 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2006 else if (test
== ITEST_EQ
)
2008 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2009 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2014 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2020 /* Emit the common code for doing conditional branches.
2021 operand[0] is the label to jump to.
2022 The comparison operands are saved away by cmp{si,di,sf,df}. */
2025 gen_conditional_branch (operands
, test_code
)
2027 enum rtx_code test_code
;
2029 enum cmp_type type
= branch_type
;
2030 rtx cmp0
= branch_cmp
[0];
2031 rtx cmp1
= branch_cmp
[1];
2032 enum machine_mode mode
;
2040 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2044 mode
= type
== CMP_SI
? SImode
: DImode
;
2046 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2053 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2055 /* We don't want to build a comparison against a non-zero
2057 cmp1
= force_reg (mode
, cmp1
);
2064 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2066 reg
= gen_reg_rtx (CCmode
);
2068 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2069 0 in the instruction built below. The MIPS FPU handles
2070 inequality testing by testing for equality and looking for a
2072 emit_insn (gen_rtx (SET
, VOIDmode
,
2074 gen_rtx (test_code
== NE
? EQ
: test_code
,
2075 CCmode
, cmp0
, cmp1
)));
2077 test_code
= test_code
== NE
? EQ
: NE
;
2085 /* Generate the branch. */
2087 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2096 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2098 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2099 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2104 /* Emit the common code for conditional moves. OPERANDS is the array
2105 of operands passed to the conditional move defined_expand. */
2108 gen_conditional_move (operands
)
2111 rtx op0
= branch_cmp
[0];
2112 rtx op1
= branch_cmp
[1];
2113 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2114 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2115 enum rtx_code move_code
= NE
;
2116 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2117 enum machine_mode cmp_mode
;
2120 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2139 op0
= force_reg (mode
, branch_cmp
[1]);
2140 op1
= branch_cmp
[0];
2144 op0
= force_reg (mode
, branch_cmp
[1]);
2145 op1
= branch_cmp
[0];
2156 op0
= force_reg (mode
, branch_cmp
[1]);
2157 op1
= branch_cmp
[0];
2161 op0
= force_reg (mode
, branch_cmp
[1]);
2162 op1
= branch_cmp
[0];
2178 if (mode
== SImode
|| mode
== DImode
)
2180 else if (mode
== SFmode
|| mode
== DFmode
)
2185 cmp_reg
= gen_reg_rtx (cmp_mode
);
2186 emit_insn (gen_rtx (SET
, cmp_mode
,
2188 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2189 emit_insn (gen_rtx (SET
, op_mode
,
2191 gen_rtx (IF_THEN_ELSE
, op_mode
,
2192 gen_rtx (move_code
, VOIDmode
,
2194 CONST0_RTX (SImode
)),
2200 /* Internal code to generate the load and store of one word/short/byte.
2201 The load is emitted directly, and the store insn is returned. */
2203 #define UNITS_PER_MIPS_DWORD 8
2204 #define UNITS_PER_MIPS_WORD 4
2205 #define UNITS_PER_MIPS_HWORD 2
2208 block_move_load_store (dest_reg
, src_reg
, p_bytes
, p_offset
, align
, orig_src
)
2209 rtx src_reg
; /* register holding source memory address */
2210 rtx dest_reg
; /* register holding dest. memory address */
2211 int *p_bytes
; /* pointer to # bytes remaining */
2212 int *p_offset
; /* pointer to current offset */
2213 int align
; /* alignment */
2214 rtx orig_src
; /* original source for making a reg note */
2216 int bytes
; /* # bytes remaining */
2217 int offset
; /* offset to use */
2218 int size
; /* size in bytes of load/store */
2219 enum machine_mode mode
; /* mode to use for load/store */
2220 rtx reg
; /* temporary register */
2221 rtx src_addr
; /* source address */
2222 rtx dest_addr
; /* destination address */
2223 rtx insn
; /* insn of the load */
2224 rtx orig_src_addr
; /* original source address */
2225 rtx (*load_func
)(); /* function to generate load insn */
2226 rtx (*store_func
)(); /* function to generate destination insn */
2229 if (bytes
<= 0 || align
<= 0)
2232 if (bytes
>= UNITS_PER_MIPS_DWORD
&& align
>= UNIS_PER_MIPS_DWORD
)
2235 size
= UNITS_PER_MIPS_DWORD
;
2236 load_func
= gen_movdi
;
2237 store_func
= gen_movdi
;
2239 else if (bytes
>= UNITS_PER_MIPS_WORD
&& align
>= UNITS_PER_MIPS_WORD
)
2242 size
= UNITS_PER_MIPS_WORD
;
2243 load_func
= gen_movsi
;
2244 store_func
= gen_movsi
;
2248 /* Don't generate unaligned moves here, rather defer those to the
2249 general movestrsi_internal pattern.
2250 If this gets commented back in, then should add the dword equivalent. */
2251 else if (bytes
>= UNITS_PER_MIPS_WORD
)
2254 size
= UNITS_PER_MIPS_WORD
;
2255 load_func
= gen_movsi_ulw
;
2256 store_func
= gen_movsi_usw
;
2260 else if (bytes
>= UNITS_PER_MIPS_SHORT
&& align
>= UNITS_PER_MIPS_SHORT
)
2263 size
= UNITS_PER_MIPS_SHORT
;
2264 load_func
= gen_movhi
;
2265 store_func
= gen_movhi
;
2272 load_func
= gen_movqi
;
2273 store_func
= gen_movqi
;
2277 *p_offset
= offset
+ size
;
2278 *p_bytes
= bytes
- size
;
2283 dest_addr
= dest_reg
;
2287 src_addr
= gen_rtx (PLUS
, Pmode
, src_reg
, GEN_INT (offset
));
2288 dest_addr
= gen_rtx (PLUS
, Pmode
, dest_reg
, GEN_INT (offset
));
2291 reg
= gen_reg_rtx (mode
);
2292 insn
= emit_insn ((*load_func
) (reg
, gen_rtx (MEM
, mode
, src_addr
)));
2293 orig_src_addr
= XEXP (orig_src
, 0);
2294 if (CONSTANT_P (orig_src_addr
))
2295 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUIV
,
2296 plus_constant (orig_src_addr
, offset
),
2299 return (*store_func
) (gen_rtx (MEM
, mode
, dest_addr
), reg
);
2304 /* Write a series of loads/stores to move some bytes. Generate load/stores as follows:
2316 This way, no NOP's are needed, except at the end, and only
2317 two temp registers are needed. Two delay slots are used
2318 in deference to the R4000. */
2322 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2323 rtx dest_reg
; /* register holding destination address */
2324 rtx src_reg
; /* register holding source address */
2325 int bytes
; /* # bytes to move */
2326 int align
; /* max alignment to assume */
2327 rtx orig_src
; /* original source for making a reg note */
2330 rtx prev2_store
= (rtx
)0;
2331 rtx prev_store
= (rtx
)0;
2332 rtx cur_store
= (rtx
)0;
2336 /* Is there a store to do? */
2338 emit_insn (prev2_store
);
2340 prev2_store
= prev_store
;
2341 prev_store
= cur_store
;
2342 cur_store
= block_move_load_store (dest_reg
, src_reg
,
2347 /* Finish up last three stores. */
2349 emit_insn (prev2_store
);
2352 emit_insn (prev_store
);
2355 emit_insn (cur_store
);
2360 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2366 temp<last> = src[MAX_MOVE_REGS-1];
2370 dest[MAX_MOVE_REGS-1] = temp<last>;
2371 src += MAX_MOVE_REGS;
2372 dest += MAX_MOVE_REGS;
2373 } while (src != final);
2375 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2376 registers are needed.
2378 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2379 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2380 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2382 #define MAX_MOVE_REGS 4
2383 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2385 /* ??? Should add code to use DWORD load/stores. */
2388 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
)
2389 rtx dest_reg
; /* register holding destination address */
2390 rtx src_reg
; /* register holding source address */
2391 int bytes
; /* # bytes to move */
2392 int align
; /* alignment */
2393 rtx orig_src
; /* original source for making a reg note */
2395 rtx dest_mem
= gen_rtx (MEM
, BLKmode
, dest_reg
);
2396 rtx src_mem
= gen_rtx (MEM
, BLKmode
, src_reg
);
2397 rtx align_rtx
= GEN_INT (align
);
2403 if (bytes
< 2*MAX_MOVE_BYTES
)
2406 leftover
= bytes
% MAX_MOVE_BYTES
;
2409 label
= gen_label_rtx ();
2410 final_src
= gen_reg_rtx (Pmode
);
2411 bytes_rtx
= GEN_INT (bytes
);
2417 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2418 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2422 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2423 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2429 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2431 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2436 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2437 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2440 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2441 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2442 emit_insn (gen_cmpdi (src_reg
, final_src
));
2446 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2447 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2448 emit_insn (gen_cmpsi (src_reg
, final_src
));
2450 emit_jump_insn (gen_bne (label
));
2453 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2459 /* Use a library function to move some bytes. */
2462 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2467 /* We want to pass the size as Pmode, which will normally be SImode
2468 but will be DImode if we are using 64 bit longs and pointers. */
2469 if (GET_MODE (bytes_rtx
) != VOIDmode
2470 && GET_MODE (bytes_rtx
) != Pmode
)
2471 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2473 #ifdef TARGET_MEM_FUNCTIONS
2474 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2478 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2479 TREE_UNSIGNED (sizetype
)),
2480 TYPE_MODE (sizetype
));
2482 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2486 convert_to_mode (TYPE_MODE (integer_type_node
),
2488 TREE_UNSIGNED (integer_type_node
)),
2489 TYPE_MODE (integer_type_node
));
2494 /* Expand string/block move operations.
2496 operands[0] is the pointer to the destination.
2497 operands[1] is the pointer to the source.
2498 operands[2] is the number of bytes to move.
2499 operands[3] is the alignment. */
2502 expand_block_move (operands
)
2505 rtx bytes_rtx
= operands
[2];
2506 rtx align_rtx
= operands
[3];
2507 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2508 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2509 int align
= INTVAL (align_rtx
);
2510 rtx orig_src
= operands
[1];
2514 if (constp
&& bytes
<= 0)
2517 if (align
> UNITS_PER_WORD
)
2518 align
= UNITS_PER_WORD
;
2520 /* Move the address into scratch registers. */
2521 dest_reg
= copy_addr_to_reg (XEXP (operands
[0], 0));
2522 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2525 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2528 else if (constp
&& bytes
<= 3*align
)
2529 block_move_sequence (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2532 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2533 emit_insn (gen_movstrsi_internal (change_address (operands
[0],
2535 change_address (orig_src
, BLKmode
,
2537 bytes_rtx
, align_rtx
));
2539 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2540 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_src
);
2542 else if (constp
&& optimize
)
2544 /* If the alignment is not word aligned, generate a test at
2545 runtime, to see whether things wound up aligned, and we
2546 can use the faster lw/sw instead ulw/usw. */
2548 rtx temp
= gen_reg_rtx (Pmode
);
2549 rtx aligned_label
= gen_label_rtx ();
2550 rtx join_label
= gen_label_rtx ();
2551 int leftover
= bytes
% MAX_MOVE_BYTES
;
2557 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2558 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2559 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2563 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2564 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2565 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2567 emit_jump_insn (gen_beq (aligned_label
));
2569 /* Unaligned loop. */
2570 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_src
);
2571 emit_jump_insn (gen_jump (join_label
));
2575 emit_label (aligned_label
);
2576 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_src
);
2577 emit_label (join_label
);
2579 /* Bytes at the end of the loop. */
2583 if (leftover
<= 3*align
)
2584 block_move_sequence (dest_reg
, src_reg
, leftover
, align
, orig_src
);
2588 emit_insn (gen_movstrsi_internal (gen_rtx (MEM
, BLKmode
, dest_reg
),
2589 gen_rtx (MEM
, BLKmode
, src_reg
),
2596 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2600 /* Emit load/stores for a small constant block_move.
2602 operands[0] is the memory address of the destination.
2603 operands[1] is the memory address of the source.
2604 operands[2] is the number of bytes to move.
2605 operands[3] is the alignment.
2606 operands[4] is a temp register.
2607 operands[5] is a temp register.
2609 operands[3+num_regs] is the last temp register.
2611 The block move type can be one of the following:
2612 BLOCK_MOVE_NORMAL Do all of the block move.
2613 BLOCK_MOVE_NOT_LAST Do all but the last store.
2614 BLOCK_MOVE_LAST Do just the last store. */
2617 output_block_move (insn
, operands
, num_regs
, move_type
)
2621 enum block_move_type move_type
;
2623 rtx dest_reg
= XEXP (operands
[0], 0);
2624 rtx src_reg
= XEXP (operands
[1], 0);
2625 int bytes
= INTVAL (operands
[2]);
2626 int align
= INTVAL (operands
[3]);
2629 int use_lwl_lwr
= FALSE
;
2630 int last_operand
= num_regs
+4;
2636 char *load
; /* load insn without nop */
2637 char *load_nop
; /* load insn with trailing nop */
2638 char *store
; /* store insn */
2639 char *final
; /* if last_store used: NULL or swr */
2640 char *last_store
; /* last store instruction */
2641 int offset
; /* current offset */
2642 enum machine_mode mode
; /* mode to use on (MEM) */
2645 /* Detect a bug in GCC, where it can give us a register
2646 the same as one of the addressing registers and reduce
2647 the number of registers available. */
2649 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2652 if (!reg_mentioned_p (operands
[i
], operands
[0])
2653 && !reg_mentioned_p (operands
[i
], operands
[1]))
2655 xoperands
[safe_regs
++] = operands
[i
];
2658 if (safe_regs
< last_operand
)
2660 xoperands
[0] = operands
[0];
2661 xoperands
[1] = operands
[1];
2662 xoperands
[2] = operands
[2];
2663 xoperands
[3] = operands
[3];
2664 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2667 /* If we are given global or static addresses, and we would be
2668 emitting a few instructions, try to save time by using a
2669 temporary register for the pointer. */
2670 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
))
2672 if (CONSTANT_P (src_reg
))
2675 mips_count_memory_refs (operands
[1], 1);
2677 src_reg
= operands
[ 3 + num_regs
-- ];
2678 if (move_type
!= BLOCK_MOVE_LAST
)
2680 xoperands
[1] = operands
[1];
2681 xoperands
[0] = src_reg
;
2682 if (Pmode
== DImode
)
2683 output_asm_insn ("dla\t%0,%1", xoperands
);
2685 output_asm_insn ("la\t%0,%1", xoperands
);
2689 if (CONSTANT_P (dest_reg
))
2692 mips_count_memory_refs (operands
[0], 1);
2694 dest_reg
= operands
[ 3 + num_regs
-- ];
2695 if (move_type
!= BLOCK_MOVE_LAST
)
2697 xoperands
[1] = operands
[0];
2698 xoperands
[0] = dest_reg
;
2699 if (Pmode
== DImode
)
2700 output_asm_insn ("dla\t%0,%1", xoperands
);
2702 output_asm_insn ("la\t%0,%1", xoperands
);
2707 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2708 are not offsettable, however, offsettable_address_p says they are
2709 offsettable. I think this is a bug in offsettable_address_p.
2710 For expediency, we fix this by just loading the address into a register
2711 if we happen to get one. */
2713 if (GET_CODE (src_reg
) == LO_SUM
)
2715 src_reg
= operands
[ 3 + num_regs
-- ];
2716 if (move_type
!= BLOCK_MOVE_LAST
)
2718 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2719 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2720 xoperands
[0] = src_reg
;
2721 if (Pmode
== DImode
)
2722 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2724 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2728 if (GET_CODE (dest_reg
) == LO_SUM
)
2730 dest_reg
= operands
[ 3 + num_regs
-- ];
2731 if (move_type
!= BLOCK_MOVE_LAST
)
2733 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2734 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2735 xoperands
[0] = dest_reg
;
2736 if (Pmode
== DImode
)
2737 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2739 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2743 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2744 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2746 else if (num_regs
< 1)
2747 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2751 load_store
[num
].offset
= offset
;
2753 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2755 load_store
[num
].load
= "ld\t%0,%1";
2756 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2757 load_store
[num
].store
= "sd\t%0,%1";
2758 load_store
[num
].last_store
= "sd\t%0,%1";
2759 load_store
[num
].final
= (char *)0;
2760 load_store
[num
].mode
= DImode
;
2765 /* ??? Fails because of a MIPS assembler bug? */
2766 else if (TARGET_64BIT
&& bytes
>= 8)
2768 if (BYTES_BIG_ENDIAN
)
2770 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2771 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2772 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2773 load_store
[num
].last_store
= "sdr\t%0,%2";
2774 load_store
[num
].final
= "sdl\t%0,%1";
2778 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2779 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2780 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2781 load_store
[num
].last_store
= "sdr\t%0,%1";
2782 load_store
[num
].final
= "sdl\t%0,%2";
2784 load_store
[num
].mode
= DImode
;
2790 else if (bytes
>= 4 && align
>= 4)
2792 load_store
[num
].load
= "lw\t%0,%1";
2793 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2794 load_store
[num
].store
= "sw\t%0,%1";
2795 load_store
[num
].last_store
= "sw\t%0,%1";
2796 load_store
[num
].final
= (char *)0;
2797 load_store
[num
].mode
= SImode
;
2802 else if (bytes
>= 4)
2804 if (BYTES_BIG_ENDIAN
)
2806 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2807 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2808 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2809 load_store
[num
].last_store
= "swr\t%0,%2";
2810 load_store
[num
].final
= "swl\t%0,%1";
2814 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2815 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2816 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2817 load_store
[num
].last_store
= "swr\t%0,%1";
2818 load_store
[num
].final
= "swl\t%0,%2";
2820 load_store
[num
].mode
= SImode
;
2826 else if (bytes
>= 2 && align
>= 2)
2828 load_store
[num
].load
= "lh\t%0,%1";
2829 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2830 load_store
[num
].store
= "sh\t%0,%1";
2831 load_store
[num
].last_store
= "sh\t%0,%1";
2832 load_store
[num
].final
= (char *)0;
2833 load_store
[num
].mode
= HImode
;
2840 load_store
[num
].load
= "lb\t%0,%1";
2841 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2842 load_store
[num
].store
= "sb\t%0,%1";
2843 load_store
[num
].last_store
= "sb\t%0,%1";
2844 load_store
[num
].final
= (char *)0;
2845 load_store
[num
].mode
= QImode
;
2850 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2852 dslots_load_total
++;
2853 dslots_load_filled
++;
2855 if (CONSTANT_P (src_reg
))
2856 mips_count_memory_refs (src_reg
, 1);
2858 if (CONSTANT_P (dest_reg
))
2859 mips_count_memory_refs (dest_reg
, 1);
2862 /* Emit load/stores now if we have run out of registers or are
2863 at the end of the move. */
2865 if (++num
== num_regs
|| bytes
== 0)
2867 /* If only load/store, we need a NOP after the load. */
2870 load_store
[0].load
= load_store
[0].load_nop
;
2871 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2872 dslots_load_filled
--;
2875 if (move_type
!= BLOCK_MOVE_LAST
)
2877 for (i
= 0; i
< num
; i
++)
2884 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2885 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2887 offset
= load_store
[i
].offset
;
2888 xoperands
[0] = operands
[i
+4];
2889 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2890 plus_constant (src_reg
, offset
));
2895 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2896 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2897 plus_constant (src_reg
,
2902 output_asm_insn (load_store
[i
].load
, xoperands
);
2906 for (i
= 0; i
< num
; i
++)
2908 int last_p
= (i
== num
-1 && bytes
== 0);
2909 int offset
= load_store
[i
].offset
;
2911 xoperands
[0] = operands
[i
+4];
2912 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2913 plus_constant (dest_reg
, offset
));
2919 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2920 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2921 plus_constant (dest_reg
,
2926 if (move_type
== BLOCK_MOVE_NORMAL
)
2927 output_asm_insn (load_store
[i
].store
, xoperands
);
2929 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2932 output_asm_insn (load_store
[i
].store
, xoperands
);
2934 else if (load_store
[i
].final
!= (char *)0)
2935 output_asm_insn (load_store
[i
].final
, xoperands
);
2939 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2942 num
= 0; /* reset load_store */
2943 use_lwl_lwr
= FALSE
;
2951 /* Argument support functions. */
2953 /* Initialize CUMULATIVE_ARGS for a function. */
2956 init_cumulative_args (cum
, fntype
, libname
)
2957 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2958 tree fntype
; /* tree ptr for function decl */
2959 rtx libname
; /* SYMBOL_REF of library name or 0 */
2961 static CUMULATIVE_ARGS zero_cum
;
2962 tree param
, next_param
;
2964 if (TARGET_DEBUG_E_MODE
)
2966 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2968 fputc ('\n', stderr
);
2972 tree ret_type
= TREE_TYPE (fntype
);
2973 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2974 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2975 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2981 /* Determine if this function has variable arguments. This is
2982 indicated by the last argument being 'void_type_mode' if there
2983 are no variable arguments. The standard MIPS calling sequence
2984 passes all arguments in the general purpose registers in this
2987 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
2991 next_param
= TREE_CHAIN (param
);
2992 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
2993 cum
->gp_reg_found
= 1;
2997 /* Advance the argument to the next argument position. */
3000 function_arg_advance (cum
, mode
, type
, named
)
3001 CUMULATIVE_ARGS
*cum
; /* current arg information */
3002 enum machine_mode mode
; /* current arg mode */
3003 tree type
; /* type of the argument or 0 if lib support */
3004 int named
; /* whether or not the argument was named */
3006 if (TARGET_DEBUG_E_MODE
)
3008 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3009 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3019 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3020 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3022 cum
->gp_reg_found
= 1;
3023 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3028 cum
->gp_reg_found
= 1;
3029 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3034 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3035 cum
->fp_arg_words
++;
3041 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3042 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3044 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3048 cum
->gp_reg_found
= 1;
3049 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3055 cum
->gp_reg_found
= 1;
3061 /* Return an RTL expression containing the register for the given mode,
3062 or 0 if the argument is to be passed on the stack. */
3065 function_arg (cum
, mode
, type
, named
)
3066 CUMULATIVE_ARGS
*cum
; /* current arg information */
3067 enum machine_mode mode
; /* current arg mode */
3068 tree type
; /* type of the argument or 0 if lib support */
3069 int named
; /* != 0 for normal args, == 0 for ... args */
3074 int *arg_words
= &cum
->arg_words
;
3075 int struct_p
= ((type
!= (tree
)0)
3076 && (TREE_CODE (type
) == RECORD_TYPE
3077 || TREE_CODE (type
) == UNION_TYPE
));
3079 if (TARGET_DEBUG_E_MODE
)
3081 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3082 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3085 cum
->last_arg_fp
= 0;
3089 if (mips_abi
== ABI_32
)
3091 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3092 regbase
= GP_ARG_FIRST
;
3095 regbase
= FP_ARG_FIRST
;
3096 /* If the first arg was a float in a floating point register,
3097 then set bias to align this float arg properly. */
3098 if (cum
->arg_words
== 1)
3102 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3105 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3106 cum
->last_arg_fp
= 1;
3107 arg_words
= &cum
->fp_arg_words
;
3108 regbase
= FP_ARG_FIRST
;
3111 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3117 if (mips_abi
== ABI_EABI
3118 && ! TARGET_SOFT_FLOAT
3119 && ! TARGET_SINGLE_FLOAT
)
3120 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3122 cum
->arg_words
+= cum
->arg_words
& 1;
3124 if (mips_abi
== ABI_32
)
3125 regbase
= ((cum
->gp_reg_found
3126 || TARGET_SOFT_FLOAT
3127 || TARGET_SINGLE_FLOAT
3128 || cum
->arg_number
>= 2)
3131 else if (mips_abi
== ABI_EABI
3132 && ! TARGET_SOFT_FLOAT
3133 && ! TARGET_SINGLE_FLOAT
)
3135 cum
->last_arg_fp
= 1;
3136 arg_words
= &cum
->fp_arg_words
;
3137 regbase
= FP_ARG_FIRST
;
3140 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3141 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3145 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3146 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3149 /* Drops through. */
3151 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3152 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3153 cum
->arg_words
+= (cum
->arg_words
& 1);
3154 regbase
= GP_ARG_FIRST
;
3161 regbase
= GP_ARG_FIRST
;
3166 cum
->arg_words
+= (cum
->arg_words
& 1);
3167 regbase
= GP_ARG_FIRST
;
3170 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3172 if (TARGET_DEBUG_E_MODE
)
3173 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3182 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3183 || mips_abi
== ABI_EABI
|| ! named
)
3184 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3187 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3188 structure contains a double in its entirety, then that 64 bit
3189 chunk is passed in a floating point register. */
3192 /* First check to see if there is any such field. */
3193 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3194 if (TREE_CODE (field
) == FIELD_DECL
3195 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3196 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3197 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3198 % BITS_PER_WORD
== 0))
3202 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3205 /* Now handle the special case by returning a PARALLEL
3206 indicating where each 64 bit chunk goes. */
3212 /* ??? If this is a packed structure, then the last hunk won't
3215 /* ??? If this is a structure with a single double field,
3216 it would be more convenient to return (REG:DI %fX) than
3217 a parallel. However, we would have to modify the mips
3218 backend to allow DImode values in fp registers. */
3220 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3221 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3222 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3224 /* assign_parms checks the mode of ENTRY_PARM, so we must
3225 use the actual mode here. */
3226 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3229 regno
= regbase
+ *arg_words
+ bias
;
3230 field
= TYPE_FIELDS (type
);
3231 for (i
= 0; i
< chunks
; i
++)
3235 for (; field
; field
= TREE_CHAIN (field
))
3236 if (TREE_CODE (field
) == FIELD_DECL
3237 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3242 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3243 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3244 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3245 reg
= gen_rtx (REG
, DFmode
,
3246 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3248 reg
= gen_rtx (REG
, word_mode
, regno
);
3250 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3251 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3259 if (TARGET_DEBUG_E_MODE
)
3260 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3261 struct_p
? ", [struct]" : "");
3263 /* The following is a hack in order to pass 1 byte structures
3264 the same way that the MIPS compiler does (namely by passing
3265 the structure in the high byte or half word of the register).
3266 This also makes varargs work. If we have such a structure,
3267 we save the adjustment RTL, and the call define expands will
3268 emit them. For the VOIDmode argument (argument after the
3269 last real argument), pass back a parallel vector holding each
3270 of the adjustments. */
3272 /* ??? function_arg can be called more than once for each argument.
3273 As a result, we compute more adjustments than we need here.
3274 See the CUMULATIVE_ARGS definition in mips.h. */
3276 /* ??? This scheme requires everything smaller than the word size to
3277 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3278 that would mean every int needs to be shifted left, which is very
3279 inefficient. Let's not carry this compatibility to the 64 bit
3280 calling convention for now. */
3282 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3283 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3285 rtx amount
= GEN_INT (BITS_PER_WORD
3286 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3287 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3289 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3291 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3295 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3296 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3303 function_arg_partial_nregs (cum
, mode
, type
, named
)
3304 CUMULATIVE_ARGS
*cum
; /* current arg information */
3305 enum machine_mode mode
; /* current arg mode */
3306 tree type
; /* type of the argument or 0 if lib support */
3307 int named
; /* != 0 for normal args, == 0 for ... args */
3309 if ((mode
== BLKmode
3310 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3311 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3312 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3313 && mips_abi
!= ABI_EABI
)
3316 if (mode
== BLKmode
)
3317 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3320 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3322 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3323 return 0; /* structure fits in registers */
3325 if (TARGET_DEBUG_E_MODE
)
3326 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3327 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3329 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3332 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3334 && mips_abi
!= ABI_EABI
)
3336 if (TARGET_DEBUG_E_MODE
)
3337 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3345 /* Abort after printing out a specific insn. */
3348 abort_with_insn (insn
, reason
)
3357 /* Write a message to stderr (for use in macros expanded in files that do not
3358 include stdio.h). */
3364 fprintf (stderr
, s
, s1
, s2
);
3374 fprintf (stderr
, "compiling '%s' in '%s'\n",
3375 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3376 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3379 #endif /* SIGINFO */
3382 /* Set up the threshold for data to go into the small data area, instead
3383 of the normal data area, and detect any conflicts in the switches. */
3388 register int i
, start
;
3390 register enum machine_mode mode
;
3392 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3394 if (mips_section_threshold
<= 0)
3395 target_flags
&= ~MASK_GPOPT
;
3397 target_flags
|= MASK_GPOPT
;
3399 /* Get the architectural level. */
3400 if (mips_isa_string
== (char *)0)
3402 #ifdef MIPS_ISA_DEFAULT
3403 mips_isa
= MIPS_ISA_DEFAULT
;
3409 else if (isdigit (*mips_isa_string
))
3411 mips_isa
= atoi (mips_isa_string
);
3412 if (mips_isa
< 1 || mips_isa
> 4)
3414 error ("-mips%d not supported", mips_isa
);
3421 error ("bad value (%s) for -mips switch", mips_isa_string
);
3425 #ifdef MIPS_ABI_DEFAULT
3426 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3427 if (mips_abi_string
== (char *) 0)
3428 mips_abi
= MIPS_ABI_DEFAULT
;
3429 else if (! strcmp (mips_abi_string
, "32")
3430 || ! strcmp (mips_abi_string
, "o32"))
3432 else if (! strcmp (mips_abi_string
, "n32"))
3434 else if (! strcmp (mips_abi_string
, "64")
3435 || ! strcmp (mips_abi_string
, "n64"))
3437 else if (! strcmp (mips_abi_string
, "eabi"))
3438 mips_abi
= ABI_EABI
;
3440 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3442 /* A specified ISA defaults the ABI if it was not specified. */
3443 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3450 /* A specified ABI defaults the ISA if it was not specified. */
3451 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3453 if (mips_abi
== ABI_32
)
3455 else if (mips_abi
== ABI_N32
)
3460 /* If both ABI and ISA were specified, check for conflicts. */
3461 else if (mips_isa_string
&& mips_abi_string
)
3463 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3464 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3465 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3468 /* Override TARGET_DEFAULT if necessary. */
3469 if (mips_abi
== ABI_32
)
3470 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3472 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */
3473 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3474 target_flags
|= MASK_LONG64
;
3476 /* ??? This doesn't work yet, so don't let people try to use it. */
3477 if (mips_abi
== ABI_32
)
3478 error ("The -mabi=32 support does not work yet.");
3480 if (mips_abi_string
)
3481 error ("This target does not support the -mabi switch.");
3484 #ifdef MIPS_CPU_STRING_DEFAULT
3485 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3486 greater than that supported by the default processor, then the user gets
3487 an error. Normally, the compiler will just default to the base level cpu
3488 for the indicated isa. */
3489 if (mips_cpu_string
== (char *)0)
3490 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3493 /* Identify the processor type */
3494 if (mips_cpu_string
== (char *)0
3495 || !strcmp (mips_cpu_string
, "default")
3496 || !strcmp (mips_cpu_string
, "DEFAULT"))
3501 mips_cpu_string
= "3000";
3502 mips_cpu
= PROCESSOR_R3000
;
3505 mips_cpu_string
= "6000";
3506 mips_cpu
= PROCESSOR_R6000
;
3509 mips_cpu_string
= "4000";
3510 mips_cpu
= PROCESSOR_R4000
;
3513 mips_cpu_string
= "8000";
3514 mips_cpu
= PROCESSOR_R8000
;
3521 char *p
= mips_cpu_string
;
3524 /* We need to cope with the various "vr" prefixes for the NEC 4300
3525 and 4100 processors. */
3526 if (*p
== 'v' || *p
== 'V')
3531 if (*p
== 'r' || *p
== 'R')
3534 /* Since there is no difference between a R2000 and R3000 in
3535 terms of the scheduler, we collapse them into just an R3000. */
3537 mips_cpu
= PROCESSOR_DEFAULT
;
3541 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3542 mips_cpu
= PROCESSOR_R3000
;
3546 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3547 mips_cpu
= PROCESSOR_R3000
;
3551 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3552 mips_cpu
= PROCESSOR_R4000
;
3553 /* The vr4100 is a non-FP ISA III processor with some extra
3555 else if (!strcmp (p
, "4100")) {
3556 mips_cpu
= PROCESSOR_R4100
;
3557 target_flags
|= MASK_SOFT_FLOAT
;
3559 /* The vr4300 is a standard ISA III processor, but with a different
3561 else if (!strcmp (p
, "4300"))
3562 mips_cpu
= PROCESSOR_R4300
;
3563 /* The r4400 is exactly the same as the r4000 from the compiler's
3565 else if (!strcmp (p
, "4400"))
3566 mips_cpu
= PROCESSOR_R4000
;
3567 else if (!strcmp (p
, "4600"))
3568 mips_cpu
= PROCESSOR_R4600
;
3569 else if (!strcmp (p
, "4650"))
3570 mips_cpu
= PROCESSOR_R4650
;
3574 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3575 mips_cpu
= PROCESSOR_R5000
;
3579 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3580 mips_cpu
= PROCESSOR_R6000
;
3584 if (!strcmp (p
, "8000"))
3585 mips_cpu
= PROCESSOR_R8000
;
3589 if (!strcmp (p
, "orion"))
3590 mips_cpu
= PROCESSOR_R4600
;
3595 && mips_cpu
!= PROCESSOR_R4300
3596 && mips_cpu
!= PROCESSOR_R4100
3597 && mips_cpu
!= PROCESSOR_R5000
)
3598 mips_cpu
= PROCESSOR_DEFAULT
;
3600 if (mips_cpu
== PROCESSOR_DEFAULT
)
3602 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3603 mips_cpu_string
= "default";
3607 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3608 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3609 || ((mips_cpu
== PROCESSOR_R4000
3610 || mips_cpu
== PROCESSOR_R4100
3611 || mips_cpu
== PROCESSOR_R4300
3612 || mips_cpu
== PROCESSOR_R4600
3613 || mips_cpu
== PROCESSOR_R4650
)
3615 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3617 /* make sure sizes of ints/longs/etc. are ok */
3621 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3623 else if (TARGET_LONG64
)
3624 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3626 else if (TARGET_FLOAT64
)
3627 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3629 else if (TARGET_64BIT
)
3630 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3633 if (mips_abi
!= ABI_32
)
3634 flag_pcc_struct_return
= 0;
3636 /* Tell halfpic.c that we have half-pic code if we do. */
3637 if (TARGET_HALF_PIC
)
3640 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3641 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3642 /* ??? -non_shared turns off pic code generation, but this is not
3644 if (TARGET_ABICALLS
)
3646 mips_abicalls
= MIPS_ABICALLS_YES
;
3648 if (mips_section_threshold
> 0)
3649 warning ("-G is incompatible with PIC code which is the default");
3652 mips_abicalls
= MIPS_ABICALLS_NO
;
3654 /* -membedded-pic is a form of PIC code suitable for embedded
3655 systems. All calls are made using PC relative addressing, and
3656 all data is addressed using the $gp register. This requires gas,
3657 which does most of the work, and GNU ld, which automatically
3658 expands PC relative calls which are out of range into a longer
3659 instruction sequence. All gcc really does differently is
3660 generate a different sequence for a switch. */
3661 if (TARGET_EMBEDDED_PIC
)
3664 if (TARGET_ABICALLS
)
3665 warning ("-membedded-pic and -mabicalls are incompatible");
3667 warning ("-G and -membedded-pic are incompatible");
3668 /* Setting mips_section_threshold is not required, because gas
3669 will force everything to be GP addressable anyhow, but
3670 setting it will cause gcc to make better estimates of the
3671 number of instructions required to access a particular data
3673 mips_section_threshold
= 0x7fffffff;
3676 /* ??? This does not work when target addresses are DImode.
3677 This is because we are missing DImode high/lo_sum patterns. */
3679 if (TARGET_GAS
&& optimize
&& ! flag_pic
&& Pmode
== SImode
)
3680 mips_split_addresses
= 1;
3682 mips_split_addresses
= 0;
3684 /* -mrnames says to use the MIPS software convention for register
3685 names instead of the hardware names (ie, $a0 instead of $4).
3686 We do this by switching the names in mips_reg_names, which the
3687 reg_names points into via the REGISTER_NAMES macro. */
3689 if (TARGET_NAME_REGS
)
3690 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3692 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3693 is currently being compiled. */
3695 if (getenv ("GCC_SIGINFO") != (char *)0)
3697 struct sigaction action
;
3698 action
.sa_handler
= siginfo
;
3700 action
.sa_flags
= SA_RESTART
;
3701 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3706 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3707 /* If -mstats and -quiet, make stderr line buffered. */
3708 if (quiet_flag
&& TARGET_STATS
)
3709 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3713 /* Initialize the high and low values for legitimate floating point
3714 constants. Rather than trying to get the accuracy down to the
3715 last bit, just use approximate ranges. */
3716 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3717 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3718 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3719 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3721 mips_print_operand_punct
['?'] = TRUE
;
3722 mips_print_operand_punct
['#'] = TRUE
;
3723 mips_print_operand_punct
['&'] = TRUE
;
3724 mips_print_operand_punct
['!'] = TRUE
;
3725 mips_print_operand_punct
['*'] = TRUE
;
3726 mips_print_operand_punct
['@'] = TRUE
;
3727 mips_print_operand_punct
['.'] = TRUE
;
3728 mips_print_operand_punct
['('] = TRUE
;
3729 mips_print_operand_punct
[')'] = TRUE
;
3730 mips_print_operand_punct
['['] = TRUE
;
3731 mips_print_operand_punct
[']'] = TRUE
;
3732 mips_print_operand_punct
['<'] = TRUE
;
3733 mips_print_operand_punct
['>'] = TRUE
;
3734 mips_print_operand_punct
['{'] = TRUE
;
3735 mips_print_operand_punct
['}'] = TRUE
;
3736 mips_print_operand_punct
['^'] = TRUE
;
3738 mips_char_to_class
['d'] = GR_REGS
;
3739 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3740 mips_char_to_class
['h'] = HI_REG
;
3741 mips_char_to_class
['l'] = LO_REG
;
3742 mips_char_to_class
['a'] = HILO_REG
;
3743 mips_char_to_class
['x'] = MD_REGS
;
3744 mips_char_to_class
['b'] = ALL_REGS
;
3745 mips_char_to_class
['y'] = GR_REGS
;
3746 mips_char_to_class
['z'] = ST_REGS
;
3748 /* Set up array to map GCC register number to debug register number.
3749 Ignore the special purpose register numbers. */
3751 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3752 mips_dbx_regno
[i
] = -1;
3754 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3755 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3756 mips_dbx_regno
[i
] = i
+ start
;
3758 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3759 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3760 mips_dbx_regno
[i
] = i
+ start
;
3762 /* Set up array giving whether a given register can hold a given mode.
3763 At present, restrict ints from being in FP registers, because reload
3764 is a little enthusiastic about storing extra values in FP registers,
3765 and this is not good for things like OS kernels. Also, due to the
3766 mandatory delay, it is as fast to load from cached memory as to move
3767 from the FP register. */
3769 for (mode
= VOIDmode
;
3770 mode
!= MAX_MACHINE_MODE
;
3771 mode
= (enum machine_mode
)((int)mode
+ 1))
3773 register int size
= GET_MODE_SIZE (mode
);
3774 register enum mode_class
class = GET_MODE_CLASS (mode
);
3776 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3783 temp
= (regno
== FPSW_REGNUM
);
3785 temp
= (ST_REG_P (regno
)
3787 || FP_REG_P (regno
));
3790 else if (GP_REG_P (regno
))
3791 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3793 else if (FP_REG_P (regno
))
3794 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3795 && (class == MODE_FLOAT
3796 || class == MODE_COMPLEX_FLOAT
3797 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3798 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3800 else if (MD_REG_P (regno
))
3801 temp
= (class == MODE_INT
3802 && (size
<= UNITS_PER_WORD
3803 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3808 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3815 * The MIPS debug format wants all automatic variables and arguments
3816 * to be in terms of the virtual frame pointer (stack pointer before
3817 * any adjustment in the function), while the MIPS 3.0 linker wants
3818 * the frame pointer to be the stack pointer after the initial
3819 * adjustment. So, we do the adjustment here. The arg pointer (which
3820 * is eliminated) points to the virtual frame pointer, while the frame
3821 * pointer (which may be eliminated) points to the stack pointer after
3822 * the initial adjustments.
3826 mips_debugger_offset (addr
, offset
)
3830 rtx offset2
= const0_rtx
;
3831 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3834 offset
= INTVAL (offset2
);
3836 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3838 int frame_size
= (!current_frame_info
.initialized
)
3839 ? compute_frame_size (get_frame_size ())
3840 : current_frame_info
.total_size
;
3842 offset
= offset
- frame_size
;
3844 /* sdbout_parms does not want this to crash for unrecognized cases. */
3846 else if (reg
!= arg_pointer_rtx
)
3847 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3854 /* A C compound statement to output to stdio stream STREAM the
3855 assembler syntax for an instruction operand X. X is an RTL
3858 CODE is a value that can be used to specify one of several ways
3859 of printing the operand. It is used when identical operands
3860 must be printed differently depending on the context. CODE
3861 comes from the `%' specification that was used to request
3862 printing of the operand. If the specification was just `%DIGIT'
3863 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3864 is the ASCII code for LTR.
3866 If X is a register, this macro should print the register's name.
3867 The names can be found in an array `reg_names' whose type is
3868 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3870 When the machine description has a specification `%PUNCT' (a `%'
3871 followed by a punctuation character), this macro is called with
3872 a null pointer for X and the punctuation character for CODE.
3874 The MIPS specific codes are:
3876 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3877 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3878 'd' output integer constant in decimal,
3879 'z' if the operand is 0, use $0 instead of normal operand.
3880 'D' print second register of double-word register operand.
3881 'L' print low-order register of double-word register operand.
3882 'M' print high-order register of double-word register operand.
3883 'C' print part of opcode for a branch condition.
3884 'N' print part of opcode for a branch condition, inverted.
3885 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3886 'B' print 'z' for EQ, 'n' for NE
3887 'b' print 'n' for EQ, 'z' for NE
3888 'T' print 'f' for EQ, 't' for NE
3889 't' print 't' for EQ, 'f' for NE
3890 'Z' print register and a comma, but print nothing for $fcc0
3891 '(' Turn on .set noreorder
3892 ')' Turn on .set reorder
3893 '[' Turn on .set noat
3895 '<' Turn on .set nomacro
3896 '>' Turn on .set macro
3897 '{' Turn on .set volatile (not GAS)
3898 '}' Turn on .set novolatile (not GAS)
3899 '&' Turn on .set noreorder if filling delay slots
3900 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3901 '!' Turn on .set nomacro if filling delay slots
3902 '#' Print nop if in a .set noreorder section.
3903 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3904 '@' Print the name of the assembler temporary register (at or $1).
3905 '.' Print the name of the register with a hard-wired zero (zero or $0).
3906 '^' Print the name of the pic call-through register (t9 or $25). */
3909 print_operand (file
, op
, letter
)
3910 FILE *file
; /* file to write to */
3911 rtx op
; /* operand to print */
3912 int letter
; /* %<letter> or 0 */
3914 register enum rtx_code code
;
3916 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3921 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3925 if (mips_branch_likely
)
3930 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3934 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3938 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3942 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3943 fputs (".set\tnoreorder\n\t", file
);
3947 if (final_sequence
!= 0)
3949 if (set_noreorder
++ == 0)
3950 fputs (".set\tnoreorder\n\t", file
);
3952 if (set_nomacro
++ == 0)
3953 fputs (".set\tnomacro\n\t", file
);
3958 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3959 fputs ("\n\t.set\tnomacro", file
);
3963 if (set_noreorder
!= 0)
3964 fputs ("\n\tnop", file
);
3966 else if (TARGET_STATS
)
3967 fputs ("\n\t#nop", file
);
3972 if (set_noreorder
++ == 0)
3973 fputs (".set\tnoreorder\n\t", file
);
3977 if (set_noreorder
== 0)
3978 error ("internal error: %%) found without a %%( in assembler pattern");
3980 else if (--set_noreorder
== 0)
3981 fputs ("\n\t.set\treorder", file
);
3986 if (set_noat
++ == 0)
3987 fputs (".set\tnoat\n\t", file
);
3992 error ("internal error: %%] found without a %%[ in assembler pattern");
3994 else if (--set_noat
== 0)
3995 fputs ("\n\t.set\tat", file
);
4000 if (set_nomacro
++ == 0)
4001 fputs (".set\tnomacro\n\t", file
);
4005 if (set_nomacro
== 0)
4006 error ("internal error: %%> found without a %%< in assembler pattern");
4008 else if (--set_nomacro
== 0)
4009 fputs ("\n\t.set\tmacro", file
);
4014 if (set_volatile
++ == 0)
4015 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4019 if (set_volatile
== 0)
4020 error ("internal error: %%} found without a %%{ in assembler pattern");
4022 else if (--set_volatile
== 0)
4023 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4032 error ("PRINT_OPERAND null pointer");
4036 code
= GET_CODE (op
);
4040 case EQ
: fputs ("eq", file
); break;
4041 case NE
: fputs ("ne", file
); break;
4042 case GT
: fputs ("gt", file
); break;
4043 case GE
: fputs ("ge", file
); break;
4044 case LT
: fputs ("lt", file
); break;
4045 case LE
: fputs ("le", file
); break;
4046 case GTU
: fputs ("gtu", file
); break;
4047 case GEU
: fputs ("geu", file
); break;
4048 case LTU
: fputs ("ltu", file
); break;
4049 case LEU
: fputs ("leu", file
); break;
4052 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4055 else if (letter
== 'N')
4058 case EQ
: fputs ("ne", file
); break;
4059 case NE
: fputs ("eq", file
); break;
4060 case GT
: fputs ("le", file
); break;
4061 case GE
: fputs ("lt", file
); break;
4062 case LT
: fputs ("ge", file
); break;
4063 case LE
: fputs ("gt", file
); break;
4064 case GTU
: fputs ("leu", file
); break;
4065 case GEU
: fputs ("ltu", file
); break;
4066 case LTU
: fputs ("geu", file
); break;
4067 case LEU
: fputs ("gtu", file
); break;
4070 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4073 else if (letter
== 'S')
4077 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4078 assemble_name (file
, buffer
);
4081 else if (letter
== 'Z')
4083 register int regnum
;
4087 regnum
= REGNO (op
);
4088 if (! ST_REG_P (regnum
))
4090 if (regnum
!= ST_REG_FIRST
)
4091 fprintf (file
, "%s,", reg_names
[regnum
]);
4094 else if (code
== REG
)
4096 register int regnum
= REGNO (op
);
4098 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4099 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4103 fprintf (file
, "%s", reg_names
[regnum
]);
4106 else if (code
== MEM
)
4107 output_address (XEXP (op
, 0));
4109 else if (code
== CONST_DOUBLE
4110 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4115 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4116 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4120 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4121 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4123 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4124 && HOST_BITS_PER_WIDE_INT
== 32)
4125 fprintf (file
, "0x%08x", INTVAL(op
));
4127 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4128 && HOST_BITS_PER_WIDE_INT
== 64)
4129 fprintf (file
, "0x%016lx", INTVAL(op
));
4131 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4132 fprintf (file
, "%d", (INTVAL(op
)));
4134 else if (letter
== 'z'
4135 && (GET_CODE (op
) == CONST_INT
)
4136 && INTVAL (op
) == 0)
4137 fputs (reg_names
[GP_REG_FIRST
], file
);
4139 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4140 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4142 else if (letter
== 'B')
4143 fputs (code
== EQ
? "z" : "n", file
);
4144 else if (letter
== 'b')
4145 fputs (code
== EQ
? "n" : "z", file
);
4146 else if (letter
== 'T')
4147 fputs (code
== EQ
? "f" : "t", file
);
4148 else if (letter
== 't')
4149 fputs (code
== EQ
? "t" : "f", file
);
4152 output_addr_const (file
, op
);
4156 /* A C compound statement to output to stdio stream STREAM the
4157 assembler syntax for an instruction operand that is a memory
4158 reference whose address is ADDR. ADDR is an RTL expression.
4160 On some machines, the syntax for a symbolic address depends on
4161 the section that the address refers to. On these machines,
4162 define the macro `ENCODE_SECTION_INFO' to store the information
4163 into the `symbol_ref', and then check for it here. */
4166 print_operand_address (file
, addr
)
4171 error ("PRINT_OPERAND_ADDRESS, null pointer");
4174 switch (GET_CODE (addr
))
4177 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4181 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4182 abort_with_insn (addr
, "Arg pointer not eliminated.");
4184 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4189 register rtx arg0
= XEXP (addr
, 0);
4190 register rtx arg1
= XEXP (addr
, 1);
4192 if (! mips_split_addresses
)
4193 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4195 if (GET_CODE (arg0
) != REG
)
4196 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4198 fprintf (file
, "%%lo(");
4199 print_operand_address (file
, arg1
);
4200 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4206 register rtx reg
= (rtx
)0;
4207 register rtx offset
= (rtx
)0;
4208 register rtx arg0
= XEXP (addr
, 0);
4209 register rtx arg1
= XEXP (addr
, 1);
4211 if (GET_CODE (arg0
) == REG
)
4215 if (GET_CODE (offset
) == REG
)
4216 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4218 else if (GET_CODE (arg1
) == REG
)
4223 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4225 output_addr_const (file
, addr
);
4229 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4231 if (!CONSTANT_P (offset
))
4232 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4234 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4235 abort_with_insn (addr
, "Arg pointer not eliminated.");
4237 output_addr_const (file
, offset
);
4238 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4246 output_addr_const (file
, addr
);
4252 /* If optimizing for the global pointer, keep track of all of
4253 the externs, so that at the end of the file, we can emit
4254 the appropriate .extern declaration for them, before writing
4255 out the text section. We assume that all names passed to
4256 us are in the permanent obstack, so that they will be valid
4257 at the end of the compilation.
4259 If we have -G 0, or the extern size is unknown, don't bother
4260 emitting the .externs. */
4263 mips_output_external (file
, decl
, name
)
4268 register struct extern_list
*p
;
4272 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4273 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4275 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4276 p
->next
= extern_head
;
4282 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4283 if (TREE_CODE (decl
) == FUNCTION_DECL
4284 /* ??? Don't include alloca, since gcc will always expand it
4285 inline. If we don't do this, libg++ fails to build. */
4286 && strcmp (name
, "alloca")
4287 /* ??? Don't include __builtin_next_arg, because then gcc will not
4288 bootstrap under Irix 5.1. */
4289 && strcmp (name
, "__builtin_next_arg"))
4291 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4292 p
->next
= extern_head
;
4302 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4304 mips_output_external_libcall (file
, name
)
4308 register struct extern_list
*p
;
4310 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4311 p
->next
= extern_head
;
4321 /* Compute a string to use as a temporary file name. */
4323 /* On MSDOS, write temp files in current dir
4324 because there's no place else we can expect to use. */
4327 #define P_tmpdir "./"
4335 char *base
= getenv ("TMPDIR");
4338 if (base
== (char *)0)
4341 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4345 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4351 len
= strlen (base
);
4352 /* temp_filename is global, so we must use malloc, not alloca. */
4353 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4354 strcpy (temp_filename
, base
);
4355 if (len
> 0 && temp_filename
[len
-1] != '/')
4356 temp_filename
[len
++] = '/';
4358 strcpy (temp_filename
+ len
, "ctXXXXXX");
4359 mktemp (temp_filename
);
4361 stream
= fopen (temp_filename
, "w+");
4363 pfatal_with_name (temp_filename
);
4366 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4367 it. Otherwise, we delete it now, so that it will be gone even if the
4368 compiler happens to crash. */
4369 unlink (temp_filename
);
4375 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4376 for .file's that start within a function. If we are smuggling stabs, try to
4377 put out a MIPS ECOFF file and a stab. */
4380 mips_output_filename (stream
, name
)
4384 static int first_time
= TRUE
;
4385 char ltext_label_name
[100];
4391 current_function_file
= name
;
4392 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4393 /* This tells mips-tfile that stabs will follow. */
4394 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4395 fprintf (stream
, "\t#@stabs\n");
4398 else if (write_symbols
== DBX_DEBUG
)
4400 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4401 fprintf (stream
, "%s ", ASM_STABS_OP
);
4402 output_quoted_string (stream
, name
);
4403 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4406 else if (name
!= current_function_file
4407 && strcmp (name
, current_function_file
) != 0)
4409 if (inside_function
&& !TARGET_GAS
)
4411 if (!file_in_function_warning
)
4413 file_in_function_warning
= TRUE
;
4414 ignore_line_number
= TRUE
;
4415 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4421 current_function_file
= name
;
4422 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4428 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4429 as well as a .loc, since it is possible that MIPS ECOFF might not be
4430 able to represent the location for inlines that come from a different
4434 mips_output_lineno (stream
, line
)
4438 if (write_symbols
== DBX_DEBUG
)
4441 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4442 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4443 LOCAL_LABEL_PREFIX
, sym_lineno
);
4448 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4449 (ignore_line_number
) ? "#" : "",
4450 num_source_filenames
, line
);
4452 LABEL_AFTER_LOC (stream
);
4457 /* If defined, a C statement to be executed just prior to the
4458 output of assembler code for INSN, to modify the extracted
4459 operands so they will be output differently.
4461 Here the argument OPVEC is the vector containing the operands
4462 extracted from INSN, and NOPERANDS is the number of elements of
4463 the vector which contain meaningful data for this insn. The
4464 contents of this vector are what will be used to convert the
4465 insn template into assembler code, so you can change the
4466 assembler output by changing the contents of the vector.
4468 We use it to check if the current insn needs a nop in front of it
4469 because of load delays, and also to update the delay slot
4472 /* ??? There is no real need for this function, because it never actually
4473 emits a NOP anymore. */
4476 final_prescan_insn (insn
, opvec
, noperands
)
4481 if (dslots_number_nops
> 0)
4483 rtx pattern
= PATTERN (insn
);
4484 int length
= get_attr_length (insn
);
4486 /* Do we need to emit a NOP? */
4488 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4489 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4490 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4491 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4492 fputs ("\t#nop\n", asm_out_file
);
4495 dslots_load_filled
++;
4497 while (--dslots_number_nops
> 0)
4498 fputs ("\t#nop\n", asm_out_file
);
4500 mips_load_reg
= (rtx
)0;
4501 mips_load_reg2
= (rtx
)0;
4502 mips_load_reg3
= (rtx
)0;
4503 mips_load_reg4
= (rtx
)0;
4508 enum rtx_code code
= GET_CODE (insn
);
4509 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4510 dslots_jump_total
++;
4515 /* Output at beginning of assembler file.
4516 If we are optimizing to use the global pointer, create a temporary
4517 file to hold all of the text stuff, and write it out to the end.
4518 This is needed because the MIPS assembler is evidently one pass,
4519 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4520 declaration when the code is processed, it generates a two
4521 instruction sequence. */
4524 mips_asm_file_start (stream
)
4527 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4529 /* Versions of the MIPS assembler before 2.20 generate errors
4530 if a branch inside of a .set noreorder section jumps to a
4531 label outside of the .set noreorder section. Revision 2.20
4532 just set nobopt silently rather than fixing the bug. */
4534 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4535 fprintf (stream
, "\t.set\tnobopt\n");
4537 /* Generate the pseudo ops that System V.4 wants. */
4538 #ifndef ABICALLS_ASM_OP
4539 #define ABICALLS_ASM_OP ".abicalls"
4541 if (TARGET_ABICALLS
)
4542 /* ??? but do not want this (or want pic0) if -non-shared? */
4543 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4545 /* Start a section, so that the first .popsection directive is guaranteed
4546 to have a previously defined section to pop back to. */
4547 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4548 fprintf (stream
, "\t.section\t.text\n");
4550 /* This code exists so that we can put all externs before all symbol
4551 references. This is necessary for the assembler's global pointer
4552 optimizations to work. */
4553 /* ??? Current versions of gas do not require that externs occur before
4554 symbol references. This means that this code is unnecessary when
4555 gas is being used. This gas feature hasn't been well tested as yet
4559 asm_out_data_file
= stream
;
4560 asm_out_text_file
= make_temp_file ();
4563 asm_out_data_file
= asm_out_text_file
= stream
;
4565 if (flag_verbose_asm
)
4566 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4568 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4572 /* If we are optimizing the global pointer, emit the text section now
4573 and any small externs which did not have .comm, etc that are
4574 needed. Also, give a warning if the data area is more than 32K and
4575 -pic because 3 instructions are needed to reference the data
4579 mips_asm_file_end (file
)
4584 struct extern_list
*p
;
4588 HALF_PIC_FINISH (file
);
4594 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4596 name_tree
= get_identifier (p
->name
);
4598 /* Positively ensure only one .extern for any given symbol. */
4599 if (! TREE_ASM_WRITTEN (name_tree
))
4601 TREE_ASM_WRITTEN (name_tree
) = 1;
4602 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4604 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4608 fputs ("\t.extern\t", file
);
4609 assemble_name (file
, p
->name
);
4610 fprintf (file
, ", %d\n", p
->size
);
4618 fprintf (file
, "\n\t.text\n");
4619 rewind (asm_out_text_file
);
4620 if (ferror (asm_out_text_file
))
4621 fatal_io_error (temp_filename
);
4623 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4624 if (fwrite (buffer
, 1, len
, file
) != len
)
4625 pfatal_with_name (asm_file_name
);
4628 pfatal_with_name (temp_filename
);
4630 if (fclose (asm_out_text_file
) != 0)
4631 pfatal_with_name (temp_filename
);
4634 unlink (temp_filename
);
4640 /* Emit either a label, .comm, or .lcomm directive, and mark
4641 that the symbol is used, so that we don't emit an .extern
4642 for it in mips_asm_file_end. */
4645 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4652 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4653 assemble_name (stream
, name
);
4654 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4658 tree name_tree
= get_identifier (name
);
4659 TREE_ASM_WRITTEN (name_tree
) = 1;
4664 /* Output a double precision value to the assembler. If both the
4665 host and target are IEEE, emit the values in hex. */
4668 mips_output_double (stream
, value
)
4670 REAL_VALUE_TYPE value
;
4672 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4674 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4676 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4677 value_long
[0], value
, value_long
[1]);
4679 fprintf (stream
, "\t.double\t%.20g\n", value
);
4684 /* Output a single precision value to the assembler. If both the
4685 host and target are IEEE, emit the values in hex. */
4688 mips_output_float (stream
, value
)
4690 REAL_VALUE_TYPE value
;
4692 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4694 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4696 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4698 fprintf (stream
, "\t.float\t%.12g\n", value
);
4703 /* Return TRUE if any register used in the epilogue is used. This to insure
4704 any insn put into the epilogue delay slots is safe. */
4707 epilogue_reg_mentioned_p (insn
)
4712 register enum rtx_code code
;
4718 if (GET_CODE (insn
) == LABEL_REF
)
4721 code
= GET_CODE (insn
);
4725 regno
= REGNO (insn
);
4726 if (regno
== STACK_POINTER_REGNUM
)
4729 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4732 if (!call_used_regs
[regno
])
4735 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4738 if (!current_frame_info
.initialized
)
4739 compute_frame_size (get_frame_size ());
4741 return (current_frame_info
.total_size
>= 32768);
4751 fmt
= GET_RTX_FORMAT (code
);
4752 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4757 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4758 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4761 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4768 /* Return the bytes needed to compute the frame pointer from the current
4771 Mips stack frames look like:
4773 Before call After call
4774 +-----------------------+ +-----------------------+
4777 | caller's temps. | | caller's temps. |
4779 +-----------------------+ +-----------------------+
4781 | arguments on stack. | | arguments on stack. |
4783 +-----------------------+ +-----------------------+
4784 | 4 words to save | | 4 words to save |
4785 | arguments passed | | arguments passed |
4786 | in registers, even | | in registers, even |
4787 SP->| if not passed. | VFP->| if not passed. |
4788 +-----------------------+ +-----------------------+
4790 | fp register save |
4792 +-----------------------+
4794 | gp register save |
4796 +-----------------------+
4800 +-----------------------+
4802 | alloca allocations |
4804 +-----------------------+
4806 | GP save for V.4 abi |
4808 +-----------------------+
4810 | arguments on stack |
4812 +-----------------------+
4814 | arguments passed |
4815 | in registers, even |
4816 low SP->| if not passed. |
4817 memory +-----------------------+
4822 compute_frame_size (size
)
4823 int size
; /* # of var. bytes allocated */
4826 long total_size
; /* # bytes that the entire frame takes up */
4827 long var_size
; /* # bytes that variables take up */
4828 long args_size
; /* # bytes that outgoing arguments take up */
4829 long extra_size
; /* # extra bytes */
4830 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4831 long gp_reg_size
; /* # bytes needed to store gp regs */
4832 long fp_reg_size
; /* # bytes needed to store fp regs */
4833 long mask
; /* mask of saved gp registers */
4834 long fmask
; /* mask of saved fp registers */
4835 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4836 long fp_bits
; /* bitmask to use for each fp register */
4842 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4843 var_size
= MIPS_STACK_ALIGN (size
);
4844 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4846 /* The MIPS 3.0 linker does not like functions that dynamically
4847 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4848 looks like we are trying to create a second frame pointer to the
4849 function, so allocate some stack space to make it happy. */
4851 if (args_size
== 0 && current_function_calls_alloca
)
4852 args_size
= 4*UNITS_PER_WORD
;
4854 total_size
= var_size
+ args_size
+ extra_size
;
4856 /* Calculate space needed for gp registers. */
4857 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4859 if (MUST_SAVE_REGISTER (regno
))
4861 gp_reg_size
+= UNITS_PER_WORD
;
4862 mask
|= 1L << (regno
- GP_REG_FIRST
);
4866 /* Calculate space needed for fp registers. */
4867 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4878 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4880 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4882 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4883 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4887 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4888 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4890 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4891 for leaf routines (total_size == extra_size) to save the gp reg.
4892 The gp reg is callee saved in the 64 bit ABI, so all routines must
4894 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
))
4895 total_size
= extra_size
= 0;
4896 else if (TARGET_ABICALLS
)
4898 /* Add the context-pointer to the saved registers. */
4899 gp_reg_size
+= UNITS_PER_WORD
;
4900 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4901 total_size
-= gp_reg_rounded
;
4902 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4903 total_size
+= gp_reg_rounded
;
4906 /* Add in space reserved on the stack by the callee for storing arguments
4907 passed in registers. */
4908 if (mips_abi
!= ABI_32
)
4909 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4911 /* Save other computed information. */
4912 current_frame_info
.total_size
= total_size
;
4913 current_frame_info
.var_size
= var_size
;
4914 current_frame_info
.args_size
= args_size
;
4915 current_frame_info
.extra_size
= extra_size
;
4916 current_frame_info
.gp_reg_size
= gp_reg_size
;
4917 current_frame_info
.fp_reg_size
= fp_reg_size
;
4918 current_frame_info
.mask
= mask
;
4919 current_frame_info
.fmask
= fmask
;
4920 current_frame_info
.initialized
= reload_completed
;
4921 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4922 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4926 unsigned long offset
= (args_size
+ extra_size
+ var_size
4927 + gp_reg_size
- UNITS_PER_WORD
);
4928 current_frame_info
.gp_sp_offset
= offset
;
4929 current_frame_info
.gp_save_offset
= offset
- total_size
;
4933 current_frame_info
.gp_sp_offset
= 0;
4934 current_frame_info
.gp_save_offset
= 0;
4940 unsigned long offset
= (args_size
+ extra_size
+ var_size
4941 + gp_reg_rounded
+ fp_reg_size
4942 - fp_inc
* UNITS_PER_FPREG
);
4943 current_frame_info
.fp_sp_offset
= offset
;
4944 current_frame_info
.fp_save_offset
= offset
- total_size
+ UNITS_PER_WORD
;
4948 current_frame_info
.fp_sp_offset
= 0;
4949 current_frame_info
.fp_save_offset
= 0;
4952 /* Ok, we're done. */
4957 /* Common code to emit the insns (or to write the instructions to a file)
4958 to save/restore registers.
4960 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4961 is not modified within save_restore_insns. */
4963 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4966 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4967 int store_p
; /* true if this is prologue */
4968 rtx large_reg
; /* register holding large offset constant or NULL */
4969 long large_offset
; /* large constant offset value */
4970 FILE *file
; /* file to write instructions to instead of making RTL */
4972 long mask
= current_frame_info
.mask
;
4973 long fmask
= current_frame_info
.fmask
;
4981 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4984 if (mask
== 0 && fmask
== 0)
4987 /* Save registers starting from high to low. The debuggers prefer
4988 at least the return register be stored at func+4, and also it
4989 allows us not to need a nop in the epilog if at least one
4990 register is reloaded in addition to return address. */
4992 /* Save GP registers if needed. */
4995 /* Pick which pointer to use as a base register. For small
4996 frames, just use the stack pointer. Otherwise, use a
4997 temporary register. Save 2 cycles if the save area is near
4998 the end of a large frame, by reusing the constant created in
4999 the prologue/epilogue to adjust the stack frame. */
5001 gp_offset
= current_frame_info
.gp_sp_offset
;
5002 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
5004 if (gp_offset
< 0 || end_offset
< 0)
5005 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5006 gp_offset
, end_offset
);
5008 else if (gp_offset
< 32768)
5010 base_reg_rtx
= stack_pointer_rtx
;
5014 else if (large_reg
!= (rtx
)0
5015 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
5016 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5018 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5019 base_offset
= large_offset
;
5020 if (file
== (FILE *)0)
5023 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5025 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5028 fprintf (file
, "\t%s\t%s,%s,%s\n",
5029 TARGET_LONG64
? "daddu" : "addu",
5030 reg_names
[MIPS_TEMP2_REGNUM
],
5031 reg_names
[REGNO (large_reg
)],
5032 reg_names
[STACK_POINTER_REGNUM
]);
5037 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5038 base_offset
= gp_offset
;
5039 if (file
== (FILE *)0)
5041 emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
5043 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5045 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5048 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5049 reg_names
[MIPS_TEMP2_REGNUM
],
5052 TARGET_LONG64
? "daddu" : "addu",
5053 reg_names
[MIPS_TEMP2_REGNUM
],
5054 reg_names
[MIPS_TEMP2_REGNUM
],
5055 reg_names
[STACK_POINTER_REGNUM
]);
5058 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5060 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5062 if (file
== (FILE *)0)
5064 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5065 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5066 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5067 GEN_INT (gp_offset
- base_offset
)));
5070 emit_move_insn (mem_rtx
, reg_rtx
);
5071 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5072 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5073 emit_move_insn (reg_rtx
, mem_rtx
);
5077 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5078 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5079 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5081 ? (store_p
) ? "sd" : "ld"
5082 : (store_p
) ? "sw" : "lw"),
5084 gp_offset
- base_offset
,
5085 reg_names
[REGNO(base_reg_rtx
)]);
5088 gp_offset
-= UNITS_PER_WORD
;
5094 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5098 /* Save floating point registers if needed. */
5101 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5102 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5104 /* Pick which pointer to use as a base register. */
5105 fp_offset
= current_frame_info
.fp_sp_offset
;
5106 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5108 if (fp_offset
< 0 || end_offset
< 0)
5109 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5110 fp_offset
, end_offset
);
5112 else if (fp_offset
< 32768)
5114 base_reg_rtx
= stack_pointer_rtx
;
5118 else if (base_reg_rtx
!= (rtx
)0
5119 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5120 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5122 ; /* already set up for gp registers above */
5125 else if (large_reg
!= (rtx
)0
5126 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5127 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5129 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5130 base_offset
= large_offset
;
5131 if (file
== (FILE *)0)
5134 emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5136 emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5139 fprintf (file
, "\t%s\t%s,%s,%s\n",
5140 TARGET_LONG64
? "daddu" : "addu",
5141 reg_names
[MIPS_TEMP2_REGNUM
],
5142 reg_names
[REGNO (large_reg
)],
5143 reg_names
[STACK_POINTER_REGNUM
]);
5148 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5149 base_offset
= fp_offset
;
5150 if (file
== (FILE *)0)
5152 emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
5154 emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5156 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5159 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5160 reg_names
[MIPS_TEMP2_REGNUM
],
5163 TARGET_LONG64
? "daddu" : "addu",
5164 reg_names
[MIPS_TEMP2_REGNUM
],
5165 reg_names
[MIPS_TEMP2_REGNUM
],
5166 reg_names
[STACK_POINTER_REGNUM
]);
5169 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5171 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5173 if (file
== (FILE *)0)
5175 enum machine_mode sz
=
5176 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5177 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5178 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5179 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5180 GEN_INT (fp_offset
- base_offset
)));
5183 emit_move_insn (mem_rtx
, reg_rtx
);
5185 emit_move_insn (reg_rtx
, mem_rtx
);
5188 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5189 (TARGET_SINGLE_FLOAT
5190 ? ((store_p
) ? "s.s" : "l.s")
5191 : ((store_p
) ? "s.d" : "l.d")),
5193 fp_offset
- base_offset
,
5194 reg_names
[REGNO(base_reg_rtx
)]);
5197 fp_offset
-= fp_size
;
5204 /* Set up the stack and frame (if desired) for the function. */
5207 function_prologue (file
, size
)
5212 long tsize
= current_frame_info
.total_size
;
5214 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5216 #ifdef SDB_DEBUGGING_INFO
5217 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5218 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5221 inside_function
= 1;
5223 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5224 /* Get the function name the same way that toplev.c does before calling
5225 assemble_start_function. This is needed so that the name used here
5226 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5227 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5229 fputs ("\t.ent\t", file
);
5230 assemble_name (file
, fnname
);
5233 assemble_name (file
, fnname
);
5234 fputs (":\n", file
);
5237 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5238 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5240 reg_names
[31 + GP_REG_FIRST
],
5241 current_frame_info
.var_size
,
5242 current_frame_info
.num_gp
,
5243 current_frame_info
.num_fp
,
5244 current_function_outgoing_args_size
,
5245 current_frame_info
.extra_size
);
5247 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5248 current_frame_info
.mask
,
5249 current_frame_info
.gp_save_offset
,
5250 current_frame_info
.fmask
,
5251 current_frame_info
.fp_save_offset
);
5253 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5255 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5257 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5258 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5261 fprintf (file
, "\t%s\t%s,%s,%d\n",
5262 (TARGET_LONG64
? "dsubu" : "subu"),
5263 sp_str
, sp_str
, tsize
);
5264 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5270 /* Expand the prologue into a bunch of separate insns. */
5273 mips_expand_prologue ()
5277 rtx tmp_rtx
= (rtx
)0;
5278 char *arg_name
= (char *)0;
5279 tree fndecl
= current_function_decl
;
5280 tree fntype
= TREE_TYPE (fndecl
);
5281 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5286 CUMULATIVE_ARGS args_so_far
;
5288 /* If struct value address is treated as the first argument, make it so. */
5289 if (aggregate_value_p (DECL_RESULT (fndecl
))
5290 && ! current_function_returns_pcc_struct
5291 && struct_value_incoming_rtx
== 0)
5293 tree type
= build_pointer_type (fntype
);
5294 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5295 DECL_ARG_TYPE (function_result_decl
) = type
;
5296 TREE_CHAIN (function_result_decl
) = fnargs
;
5297 fnargs
= function_result_decl
;
5300 /* Determine the last argument, and get its name. */
5302 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5303 regno
= GP_ARG_FIRST
;
5305 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5307 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5308 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5311 if (TREE_ADDRESSABLE (passed_type
))
5313 passed_type
= build_pointer_type (passed_type
);
5314 passed_mode
= Pmode
;
5317 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5323 /* passed in a register, so will get homed automatically */
5324 if (GET_MODE (entry_parm
) == BLKmode
)
5325 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5327 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5329 regno
= REGNO (entry_parm
) + words
- 1;
5333 regno
= GP_ARG_LAST
+1;
5337 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5339 next_arg
= TREE_CHAIN (cur_arg
);
5340 if (next_arg
== (tree
)0)
5342 if (DECL_NAME (cur_arg
))
5343 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5349 /* In order to pass small structures by value in registers
5350 compatibly with the MIPS compiler, we need to shift the value
5351 into the high part of the register. Function_arg has encoded a
5352 PARALLEL rtx, holding a vector of adjustments to be made as the
5353 next_arg_reg variable, so we split up the insns, and emit them
5356 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5357 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5359 rtvec adjust
= XVEC (next_arg_reg
, 0);
5360 int num
= GET_NUM_ELEM (adjust
);
5362 for (i
= 0; i
< num
; i
++)
5364 rtx pattern
= RTVEC_ELT (adjust
, i
);
5365 if (GET_CODE (pattern
) != SET
5366 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5367 abort_with_insn (pattern
, "Insn is not a shift");
5369 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5370 emit_insn (pattern
);
5374 tsize
= compute_frame_size (get_frame_size ());
5376 /* If this function is a varargs function, store any registers that
5377 would normally hold arguments ($4 - $7) on the stack. */
5378 if (mips_abi
== ABI_32
5379 && ((TYPE_ARG_TYPES (fntype
) != 0
5380 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5381 || (arg_name
!= (char *)0
5382 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5383 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5385 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5386 rtx ptr
= stack_pointer_rtx
;
5388 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5389 if (TARGET_ABICALLS
)
5392 for (; regno
<= GP_ARG_LAST
; regno
++)
5395 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5396 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5397 gen_rtx (REG
, word_mode
, regno
));
5398 offset
+= UNITS_PER_WORD
;
5404 rtx tsize_rtx
= GEN_INT (tsize
);
5406 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5407 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5411 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5412 emit_move_insn (tmp_rtx
, tsize_rtx
);
5413 tsize_rtx
= tmp_rtx
;
5417 emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5420 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5424 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5426 if (frame_pointer_needed
)
5429 emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5431 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5434 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5435 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5438 /* If we are profiling, make sure no instructions are scheduled before
5439 the call to mcount. */
5441 if (profile_flag
|| profile_block_flag
)
5442 emit_insn (gen_blockage ());
5446 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5448 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5449 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5452 function_epilogue (file
, size
)
5458 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5459 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5460 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5461 int noreorder
= (epilogue_delay
!= 0);
5462 int noepilogue
= FALSE
;
5463 int load_nop
= FALSE
;
5465 rtx tmp_rtx
= (rtx
)0;
5469 /* The epilogue does not depend on any registers, but the stack
5470 registers, so we assume that if we have 1 pending nop, it can be
5471 ignored, and 2 it must be filled (2 nops occur for integer
5472 multiply and divide). */
5474 if (dslots_number_nops
> 0)
5476 if (dslots_number_nops
== 1)
5478 dslots_number_nops
= 0;
5479 dslots_load_filled
++;
5483 while (--dslots_number_nops
> 0)
5484 fputs ("\t#nop\n", asm_out_file
);
5491 fputs ("\t.set\tat\n", file
);
5492 error ("internal gcc error: .set noat left on in epilogue");
5495 if (set_nomacro
!= 0)
5498 fputs ("\t.set\tmacro\n", file
);
5499 error ("internal gcc error: .set nomacro left on in epilogue");
5502 if (set_noreorder
!= 0)
5505 fputs ("\t.set\treorder\n", file
);
5506 error ("internal gcc error: .set noreorder left on in epilogue");
5509 if (set_volatile
!= 0)
5512 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5513 error ("internal gcc error: .set volatile left on in epilogue");
5516 size
= MIPS_STACK_ALIGN (size
);
5517 tsize
= (!current_frame_info
.initialized
)
5518 ? compute_frame_size (size
)
5519 : current_frame_info
.total_size
;
5521 if (tsize
== 0 && epilogue_delay
== 0)
5523 rtx insn
= get_last_insn ();
5525 /* If the last insn was a BARRIER, we don't have to write any code
5526 because a jump (aka return) was put there. */
5527 if (GET_CODE (insn
) == NOTE
)
5528 insn
= prev_nonnote_insn (insn
);
5529 if (insn
&& GET_CODE (insn
) == BARRIER
)
5537 /* In the reload sequence, we don't need to fill the load delay
5538 slots for most of the loads, also see if we can fill the final
5539 delay slot if not otherwise filled by the reload sequence. */
5542 fprintf (file
, "\t.set\tnoreorder\n");
5546 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5547 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5550 if (frame_pointer_needed
)
5551 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5552 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5554 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5556 load_only_r31
= (((current_frame_info
.mask
5557 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5558 ? PIC_OFFSET_TABLE_MASK
: 0))
5560 && current_frame_info
.fmask
== 0);
5564 /* If the only register saved is the return address, we need a
5565 nop, unless we have an instruction to put into it. Otherwise
5566 we don't since reloading multiple registers doesn't reference
5567 the register being loaded. */
5572 final_scan_insn (XEXP (epilogue_delay
, 0),
5576 1); /* nopeepholes */
5579 fprintf (file
, "\tnop\n");
5584 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5587 fprintf (file
, "\t%s\t%s,%s,%s\n",
5588 TARGET_LONG64
? "daddu" : "addu",
5589 sp_str
, sp_str
, t1_str
);
5592 fprintf (file
, "\t%s\t%s,%s,%d\n",
5593 TARGET_LONG64
? "daddu" : "addu",
5594 sp_str
, sp_str
, tsize
);
5596 else if (!load_only_r31
&& epilogue_delay
!= 0)
5597 final_scan_insn (XEXP (epilogue_delay
, 0),
5601 1); /* nopeepholes */
5603 fprintf (file
, "\t.set\treorder\n");
5609 fprintf (file
, "\t%s\t%s,%s,%s\n",
5610 TARGET_LONG64
? "daddu" : "addu",
5611 sp_str
, sp_str
, t1_str
);
5614 fprintf (file
, "\t%s\t%s,%s,%d\n",
5615 TARGET_LONG64
? "daddu" : "addu",
5616 sp_str
, sp_str
, tsize
);
5618 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5622 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5623 /* Get the function name the same way that toplev.c does before calling
5624 assemble_start_function. This is needed so that the name used here
5625 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5626 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5628 fputs ("\t.end\t", file
);
5629 assemble_name (file
, fnname
);
5635 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5636 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5637 int num_regs
= num_gp_regs
+ num_fp_regs
;
5638 char *name
= fnname
;
5643 dslots_load_total
+= num_regs
;
5646 dslots_jump_total
++;
5650 dslots_load_filled
+= num_regs
;
5652 /* If the only register saved is the return register, we
5653 can't fill this register's delay slot. */
5655 if (load_only_r31
&& epilogue_delay
== 0)
5656 dslots_load_filled
--;
5658 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5659 dslots_jump_filled
++;
5663 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5665 (frame_pointer_needed
) ? 'y' : 'n',
5666 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5667 (current_function_calls_alloca
) ? 'y' : 'n',
5668 (current_function_calls_setjmp
) ? 'y' : 'n',
5669 (long)current_frame_info
.total_size
,
5670 (long)current_function_outgoing_args_size
,
5671 num_gp_regs
, num_fp_regs
,
5672 dslots_load_total
, dslots_load_filled
,
5673 dslots_jump_total
, dslots_jump_filled
,
5674 num_refs
[0], num_refs
[1], num_refs
[2]);
5676 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5678 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5679 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5682 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5684 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5685 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5688 fputc ('\n', stderr
);
5691 /* Reset state info for each function. */
5692 inside_function
= FALSE
;
5693 ignore_line_number
= FALSE
;
5694 dslots_load_total
= 0;
5695 dslots_jump_total
= 0;
5696 dslots_load_filled
= 0;
5697 dslots_jump_filled
= 0;
5701 mips_load_reg
= (rtx
)0;
5702 mips_load_reg2
= (rtx
)0;
5703 current_frame_info
= zero_frame_info
;
5705 /* Restore the output file if optimizing the GP (optimizing the GP causes
5706 the text to be diverted to a tempfile, so that data decls come before
5707 references to the data). */
5710 asm_out_file
= asm_out_data_file
;
5714 /* Expand the epilogue into a bunch of separate insns. */
5717 mips_expand_epilogue ()
5719 long tsize
= current_frame_info
.total_size
;
5720 rtx tsize_rtx
= GEN_INT (tsize
);
5721 rtx tmp_rtx
= (rtx
)0;
5725 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5726 emit_move_insn (tmp_rtx
, tsize_rtx
);
5727 tsize_rtx
= tmp_rtx
;
5732 if (frame_pointer_needed
)
5735 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5737 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5740 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5743 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5746 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5750 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5754 /* Define the number of delay slots needed for the function epilogue.
5756 On the mips, we need a slot if either no stack has been allocated,
5757 or the only register saved is the return register. */
5760 mips_epilogue_delay_slots ()
5762 if (!current_frame_info
.initialized
)
5763 (void) compute_frame_size (get_frame_size ());
5765 if (current_frame_info
.total_size
== 0)
5768 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5775 /* Return true if this function is known to have a null epilogue.
5776 This allows the optimizer to omit jumps to jumps if no stack
5780 simple_epilogue_p ()
5782 if (!reload_completed
)
5785 if (current_frame_info
.initialized
)
5786 return current_frame_info
.total_size
== 0;
5788 return (compute_frame_size (get_frame_size ())) == 0;
5791 /* Choose the section to use for the constant rtx expression X that has
5794 mips_select_rtx_section (mode
, x
)
5795 enum machine_mode mode
;
5798 if (TARGET_EMBEDDED_DATA
)
5800 /* For embedded applications, always put constants in read-only data,
5801 in order to reduce RAM usage. */
5802 READONLY_DATA_SECTION ();
5806 /* For hosted applications, always put constants in small data if
5807 possible, as this gives the best performance. */
5809 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5810 && mips_section_threshold
> 0)
5811 SMALL_DATA_SECTION ();
5813 READONLY_DATA_SECTION ();
5817 /* Choose the section to use for DECL. RELOC is true if its value contains
5818 any relocatable expression. */
5820 mips_select_section (decl
, reloc
)
5824 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5826 if (TARGET_EMBEDDED_PIC
5827 && TREE_CODE (decl
) == STRING_CST
5828 && !flag_writable_strings
)
5830 /* For embedded position independent code, put constant strings
5831 in the text section, because the data section is limited to
5836 else if (TARGET_EMBEDDED_DATA
)
5838 /* For embedded applications, always put an object in read-only data
5839 if possible, in order to reduce RAM usage. */
5841 if (((TREE_CODE (decl
) == VAR_DECL
5842 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5843 && DECL_INITIAL (decl
)
5844 && (DECL_INITIAL (decl
) == error_mark_node
5845 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5846 /* Deal with calls from output_constant_def_contents. */
5847 || (TREE_CODE (decl
) != VAR_DECL
5848 && (TREE_CODE (decl
) != STRING_CST
5849 || !flag_writable_strings
)))
5850 && ! (flag_pic
&& reloc
))
5851 READONLY_DATA_SECTION ();
5852 else if (size
> 0 && size
<= mips_section_threshold
)
5853 SMALL_DATA_SECTION ();
5859 /* For hosted applications, always put an object in small data if
5860 possible, as this gives the best performance. */
5862 if (size
> 0 && size
<= mips_section_threshold
)
5863 SMALL_DATA_SECTION ();
5864 else if (((TREE_CODE (decl
) == VAR_DECL
5865 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5866 && DECL_INITIAL (decl
)
5867 && (DECL_INITIAL (decl
) == error_mark_node
5868 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5869 /* Deal with calls from output_constant_def_contents. */
5870 || (TREE_CODE (decl
) != VAR_DECL
5871 && (TREE_CODE (decl
) != STRING_CST
5872 || !flag_writable_strings
)))
5873 && ! (flag_pic
&& reloc
))
5874 READONLY_DATA_SECTION ();
5880 #ifdef MIPS_ABI_DEFAULT
5881 /* Support functions for the 64 bit ABI. */
5883 /* Return register to use for a function return value with VALTYPE for function
5887 mips_function_value (valtype
, func
)
5891 int reg
= GP_RETURN
;
5892 enum machine_mode mode
= TYPE_MODE (valtype
);
5893 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5895 /* ??? How should we return complex float? */
5896 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5898 else if (TREE_CODE (valtype
) == RECORD_TYPE
5899 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5901 /* A struct with only one or two floating point fields is returned in
5902 the floating point registers. */
5903 tree field
, fields
[2];
5906 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5907 field
= TREE_CHAIN (field
))
5909 if (TREE_CODE (field
) != FIELD_DECL
)
5911 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5914 fields
[i
++] = field
;
5917 /* Must check i, so that we reject structures with no elements. */
5922 /* The structure has DImode, but we don't allow DImode values
5923 in FP registers, so we use a PARALLEL even though it isn't
5924 strictly necessary. */
5925 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5927 return gen_rtx (PARALLEL
, mode
,
5929 gen_rtx (EXPR_LIST
, VOIDmode
,
5930 gen_rtx (REG
, field_mode
, FP_RETURN
),
5935 enum machine_mode first_mode
5936 = TYPE_MODE (TREE_TYPE (fields
[0]));
5937 enum machine_mode second_mode
5938 = TYPE_MODE (TREE_TYPE (fields
[1]));
5940 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5942 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5944 return gen_rtx (PARALLEL
, mode
,
5946 gen_rtx (EXPR_LIST
, VOIDmode
,
5947 gen_rtx (REG
, first_mode
, FP_RETURN
),
5948 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5949 gen_rtx (EXPR_LIST
, VOIDmode
,
5950 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5951 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5956 return gen_rtx (REG
, mode
, reg
);
5959 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
5960 nonzero when an argument must be passed by reference. */
5963 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5964 CUMULATIVE_ARGS
*cum
;
5965 enum machine_mode mode
;
5971 if (mips_abi
!= ABI_EABI
)
5974 /* ??? How should SCmode be handled? */
5975 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
5978 size
= int_size_in_bytes (type
);
5979 return size
== -1 || size
> UNITS_PER_WORD
;
5984 /* This function returns the register class required for a secondary
5985 register when copying between one of the registers in CLASS, and X,
5986 using MODE. If IN_P is nonzero, the copy is going from X to the
5987 register, otherwise the register is the source. A return value of
5988 NO_REGS means that no secondary register is required. */
5991 mips_secondary_reload_class (class, mode
, x
, in_p
)
5992 enum reg_class
class;
5993 enum machine_mode mode
;
5999 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
6000 regno
= true_regnum (x
);
6002 /* We always require a general register when copying anything to
6003 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
6004 to a general register, or when copying from register 0. */
6005 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
6009 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6013 if (regno
== HILO_REGNUM
)
6017 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6022 /* Copying from HI or LO to anywhere other than a general register
6023 requires a general register. */
6024 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
6026 if (GP_REG_P (regno
))
6030 if (MD_REG_P (regno
))
6032 if (class == GR_REGS
)
6037 /* We can only copy a value to a condition code register from a
6038 floating point register, and even then we require a scratch
6039 floating point register. We can only copy a value out of a
6040 condition code register into a general register. */
6041 if (class == ST_REGS
)
6045 if (GP_REG_P (regno
))
6049 if (ST_REG_P (regno
))
6053 if (class == GR_REGS
)